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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
90.37 97.82 93.79 97.44 73.44 96.21 98.17 75.75


Total test records in report: 2976
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T2819 /workspace/coverage/default/46.usbdev_aon_wake_reset.256830644 Jul 31 05:47:02 PM PDT 24 Jul 31 05:47:17 PM PDT 24 13399099546 ps
T2820 /workspace/coverage/default/29.usbdev_aon_wake_resume.1344848972 Jul 31 05:44:26 PM PDT 24 Jul 31 05:45:00 PM PDT 24 23348896820 ps
T2821 /workspace/coverage/default/43.usbdev_bitstuff_err.590841584 Jul 31 05:46:21 PM PDT 24 Jul 31 05:46:22 PM PDT 24 162372221 ps
T2822 /workspace/coverage/default/29.usbdev_min_length_out_transaction.2461612273 Jul 31 05:44:28 PM PDT 24 Jul 31 05:44:29 PM PDT 24 148663718 ps
T2823 /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2892772110 Jul 31 05:44:57 PM PDT 24 Jul 31 05:44:58 PM PDT 24 183168506 ps
T2824 /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3458383323 Jul 31 05:39:34 PM PDT 24 Jul 31 05:39:36 PM PDT 24 224499965 ps
T2825 /workspace/coverage/default/7.usbdev_link_resume.2903130915 Jul 31 05:40:44 PM PDT 24 Jul 31 05:41:11 PM PDT 24 23297582388 ps
T2826 /workspace/coverage/default/28.usbdev_device_timeout.1361112778 Jul 31 05:44:20 PM PDT 24 Jul 31 05:44:50 PM PDT 24 1328173106 ps
T2827 /workspace/coverage/default/19.usbdev_pkt_sent.2192772042 Jul 31 05:42:58 PM PDT 24 Jul 31 05:42:59 PM PDT 24 242760231 ps
T2828 /workspace/coverage/default/25.usbdev_enable.121917151 Jul 31 05:43:57 PM PDT 24 Jul 31 05:43:58 PM PDT 24 61552572 ps
T2829 /workspace/coverage/default/1.usbdev_spurious_pids_ignored.3827627974 Jul 31 05:39:30 PM PDT 24 Jul 31 05:40:33 PM PDT 24 6155413504 ps
T2830 /workspace/coverage/default/37.usbdev_low_speed_traffic.168691501 Jul 31 05:45:36 PM PDT 24 Jul 31 05:46:54 PM PDT 24 7618555587 ps
T2831 /workspace/coverage/default/5.usbdev_rand_suspends.1539043263 Jul 31 05:40:27 PM PDT 24 Jul 31 05:42:08 PM PDT 24 12015211760 ps
T2832 /workspace/coverage/default/3.usbdev_in_trans.3112539552 Jul 31 05:39:52 PM PDT 24 Jul 31 05:39:53 PM PDT 24 167776211 ps
T2833 /workspace/coverage/default/8.usbdev_alert_test.1585344541 Jul 31 05:41:07 PM PDT 24 Jul 31 05:41:08 PM PDT 24 90314273 ps
T2834 /workspace/coverage/default/31.usbdev_aon_wake_resume.2804492087 Jul 31 05:44:51 PM PDT 24 Jul 31 05:45:21 PM PDT 24 23356191835 ps
T2835 /workspace/coverage/default/20.usbdev_max_length_in_transaction.3735391488 Jul 31 05:43:05 PM PDT 24 Jul 31 05:43:06 PM PDT 24 264587036 ps
T2836 /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3302031241 Jul 31 05:41:38 PM PDT 24 Jul 31 05:41:39 PM PDT 24 196525045 ps
T2837 /workspace/coverage/default/21.usbdev_in_stall.1746831606 Jul 31 05:43:13 PM PDT 24 Jul 31 05:43:14 PM PDT 24 138685743 ps
T2838 /workspace/coverage/default/15.usbdev_disable_endpoint.36449448 Jul 31 05:42:18 PM PDT 24 Jul 31 05:42:20 PM PDT 24 501251744 ps
T2839 /workspace/coverage/default/26.usbdev_pending_in_trans.1034463067 Jul 31 05:44:03 PM PDT 24 Jul 31 05:44:04 PM PDT 24 152617201 ps
T2840 /workspace/coverage/default/45.usbdev_rx_crc_err.2071523359 Jul 31 05:46:43 PM PDT 24 Jul 31 05:46:44 PM PDT 24 180122164 ps
T2841 /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.479884371 Jul 31 05:39:32 PM PDT 24 Jul 31 05:39:33 PM PDT 24 267505825 ps
T2842 /workspace/coverage/default/23.usbdev_stream_len_max.2894288114 Jul 31 05:43:37 PM PDT 24 Jul 31 05:43:39 PM PDT 24 685277206 ps
T2843 /workspace/coverage/default/9.usbdev_av_buffer.1484051506 Jul 31 05:41:11 PM PDT 24 Jul 31 05:41:12 PM PDT 24 213260572 ps
T2844 /workspace/coverage/default/7.usbdev_endpoint_access.1690543094 Jul 31 05:40:44 PM PDT 24 Jul 31 05:40:46 PM PDT 24 954938795 ps
T2845 /workspace/coverage/default/37.usbdev_max_length_in_transaction.1683345350 Jul 31 05:45:36 PM PDT 24 Jul 31 05:45:38 PM PDT 24 300772650 ps
T2846 /workspace/coverage/default/38.usbdev_pkt_sent.629633474 Jul 31 05:45:49 PM PDT 24 Jul 31 05:45:50 PM PDT 24 266173401 ps
T155 /workspace/coverage/default/6.usbdev_rand_bus_disconnects.653924563 Jul 31 05:40:36 PM PDT 24 Jul 31 05:41:58 PM PDT 24 11197132461 ps
T2847 /workspace/coverage/default/15.usbdev_random_length_out_transaction.2662558793 Jul 31 05:42:18 PM PDT 24 Jul 31 05:42:19 PM PDT 24 215921007 ps
T2848 /workspace/coverage/default/13.usbdev_device_address.4065809030 Jul 31 05:41:53 PM PDT 24 Jul 31 05:42:18 PM PDT 24 10822730584 ps
T2849 /workspace/coverage/default/1.usbdev_aon_wake_resume.2492841889 Jul 31 05:39:23 PM PDT 24 Jul 31 05:39:52 PM PDT 24 23435707085 ps
T2850 /workspace/coverage/default/13.usbdev_phy_config_pinflip.3767887585 Jul 31 05:41:58 PM PDT 24 Jul 31 05:42:00 PM PDT 24 217276823 ps
T2851 /workspace/coverage/default/27.usbdev_endpoint_access.113086939 Jul 31 05:44:08 PM PDT 24 Jul 31 05:44:10 PM PDT 24 895513826 ps
T2852 /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2691086294 Jul 31 05:42:31 PM PDT 24 Jul 31 05:42:37 PM PDT 24 3823721554 ps
T2853 /workspace/coverage/default/34.usbdev_iso_retraction.171242754 Jul 31 05:45:20 PM PDT 24 Jul 31 05:45:50 PM PDT 24 4711875220 ps
T2854 /workspace/coverage/default/28.usbdev_random_length_in_transaction.2320742853 Jul 31 05:44:16 PM PDT 24 Jul 31 05:44:17 PM PDT 24 177157612 ps
T2855 /workspace/coverage/default/30.usbdev_min_length_in_transaction.1974669426 Jul 31 05:44:41 PM PDT 24 Jul 31 05:44:42 PM PDT 24 150974228 ps
T2856 /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2702784050 Jul 31 05:40:58 PM PDT 24 Jul 31 05:42:58 PM PDT 24 4070522960 ps
T2857 /workspace/coverage/default/1.usbdev_freq_hiclk.289501964 Jul 31 05:39:23 PM PDT 24 Jul 31 05:42:09 PM PDT 24 112190653172 ps
T2858 /workspace/coverage/default/22.usbdev_max_length_in_transaction.168618374 Jul 31 05:43:25 PM PDT 24 Jul 31 05:43:26 PM PDT 24 250570129 ps
T2859 /workspace/coverage/default/28.usbdev_max_length_out_transaction.3891721563 Jul 31 05:44:17 PM PDT 24 Jul 31 05:44:18 PM PDT 24 198649121 ps
T2860 /workspace/coverage/default/13.usbdev_stream_len_max.2857809592 Jul 31 05:42:01 PM PDT 24 Jul 31 05:42:04 PM PDT 24 1018230457 ps
T2861 /workspace/coverage/default/39.usbdev_link_in_err.2586967494 Jul 31 05:45:51 PM PDT 24 Jul 31 05:45:52 PM PDT 24 198564687 ps
T2862 /workspace/coverage/default/31.usbdev_link_in_err.881866643 Jul 31 05:44:51 PM PDT 24 Jul 31 05:44:52 PM PDT 24 182430000 ps
T2863 /workspace/coverage/default/18.usbdev_pkt_sent.1899044919 Jul 31 05:42:53 PM PDT 24 Jul 31 05:42:54 PM PDT 24 235900438 ps
T2864 /workspace/coverage/default/30.usbdev_streaming_out.678287226 Jul 31 05:44:49 PM PDT 24 Jul 31 05:45:27 PM PDT 24 4566034741 ps
T2865 /workspace/coverage/default/42.usbdev_invalid_sync.1128046466 Jul 31 05:46:20 PM PDT 24 Jul 31 05:47:06 PM PDT 24 6176699029 ps
T2866 /workspace/coverage/default/5.usbdev_device_timeout.443439990 Jul 31 05:40:14 PM PDT 24 Jul 31 05:40:15 PM PDT 24 224263267 ps
T2867 /workspace/coverage/default/35.usbdev_random_length_out_transaction.7971709 Jul 31 05:45:24 PM PDT 24 Jul 31 05:45:25 PM PDT 24 196223292 ps
T2868 /workspace/coverage/default/35.usbdev_device_timeout.1732661867 Jul 31 05:45:17 PM PDT 24 Jul 31 05:45:21 PM PDT 24 307084698 ps
T186 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.827137981 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:11 PM PDT 24 526957215 ps
T208 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2762710870 Jul 31 07:13:54 PM PDT 24 Jul 31 07:13:56 PM PDT 24 168432083 ps
T187 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2841303724 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:36 PM PDT 24 102767195 ps
T188 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.75471894 Jul 31 07:16:38 PM PDT 24 Jul 31 07:16:39 PM PDT 24 107740666 ps
T209 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.175564305 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:36 PM PDT 24 136592525 ps
T193 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1202161292 Jul 31 07:16:50 PM PDT 24 Jul 31 07:16:51 PM PDT 24 33994165 ps
T253 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.79226115 Jul 31 07:13:38 PM PDT 24 Jul 31 07:13:42 PM PDT 24 161419608 ps
T196 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3596433378 Jul 31 07:13:59 PM PDT 24 Jul 31 07:14:00 PM PDT 24 46320816 ps
T194 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1249651259 Jul 31 07:16:43 PM PDT 24 Jul 31 07:16:44 PM PDT 24 50983461 ps
T189 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1100926687 Jul 31 07:16:34 PM PDT 24 Jul 31 07:16:39 PM PDT 24 789187813 ps
T207 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.424329495 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:09 PM PDT 24 88276021 ps
T215 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3468513159 Jul 31 07:13:38 PM PDT 24 Jul 31 07:13:40 PM PDT 24 70017039 ps
T190 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1602637690 Jul 31 07:14:00 PM PDT 24 Jul 31 07:14:02 PM PDT 24 301404273 ps
T212 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.989652018 Jul 31 07:13:58 PM PDT 24 Jul 31 07:14:01 PM PDT 24 472550842 ps
T264 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.223637133 Jul 31 07:13:29 PM PDT 24 Jul 31 07:13:30 PM PDT 24 96622124 ps
T216 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.626278583 Jul 31 07:13:59 PM PDT 24 Jul 31 07:14:02 PM PDT 24 92556935 ps
T265 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3481668982 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:38 PM PDT 24 329121729 ps
T261 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2706376712 Jul 31 07:13:38 PM PDT 24 Jul 31 07:13:39 PM PDT 24 45000989 ps
T195 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.780024688 Jul 31 07:16:34 PM PDT 24 Jul 31 07:16:35 PM PDT 24 42976295 ps
T231 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3600673219 Jul 31 07:14:15 PM PDT 24 Jul 31 07:14:17 PM PDT 24 117974383 ps
T266 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2199266990 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:38 PM PDT 24 145985504 ps
T232 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2165717520 Jul 31 07:13:46 PM PDT 24 Jul 31 07:13:48 PM PDT 24 88086701 ps
T267 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3729432651 Jul 31 07:14:06 PM PDT 24 Jul 31 07:14:08 PM PDT 24 148603816 ps
T254 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3319256644 Jul 31 07:13:22 PM PDT 24 Jul 31 07:13:31 PM PDT 24 1522704417 ps
T278 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2986166772 Jul 31 07:16:43 PM PDT 24 Jul 31 07:16:44 PM PDT 24 73781188 ps
T233 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2355769711 Jul 31 07:16:39 PM PDT 24 Jul 31 07:16:41 PM PDT 24 182649025 ps
T235 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2558460268 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:39 PM PDT 24 662299453 ps
T220 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3580972715 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:40 PM PDT 24 253451293 ps
T297 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4201618946 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:38 PM PDT 24 41381758 ps
T2869 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4046884676 Jul 31 07:13:45 PM PDT 24 Jul 31 07:13:50 PM PDT 24 560810510 ps
T234 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3060698046 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:40 PM PDT 24 486317768 ps
T279 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1153101606 Jul 31 07:13:18 PM PDT 24 Jul 31 07:13:19 PM PDT 24 51059695 ps
T298 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1002940484 Jul 31 07:16:50 PM PDT 24 Jul 31 07:16:51 PM PDT 24 110078374 ps
T303 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3333105888 Jul 31 07:14:15 PM PDT 24 Jul 31 07:14:15 PM PDT 24 39908540 ps
T268 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1908602276 Jul 31 07:13:58 PM PDT 24 Jul 31 07:13:59 PM PDT 24 91503925 ps
T269 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.614227185 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:37 PM PDT 24 113843906 ps
T222 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1007445048 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:38 PM PDT 24 129500835 ps
T2870 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.147403431 Jul 31 07:13:53 PM PDT 24 Jul 31 07:13:57 PM PDT 24 482508183 ps
T255 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1817569959 Jul 31 07:13:31 PM PDT 24 Jul 31 07:13:32 PM PDT 24 107983278 ps
T256 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3105590961 Jul 31 07:13:47 PM PDT 24 Jul 31 07:13:48 PM PDT 24 58032949 ps
T275 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4011210526 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:39 PM PDT 24 176906765 ps
T300 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3077782123 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:37 PM PDT 24 76844163 ps
T257 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.809513035 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:38 PM PDT 24 63445229 ps
T258 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3129544116 Jul 31 07:13:30 PM PDT 24 Jul 31 07:13:32 PM PDT 24 109122569 ps
T228 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3929406271 Jul 31 07:16:34 PM PDT 24 Jul 31 07:16:36 PM PDT 24 131002427 ps
T2871 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2079041325 Jul 31 07:14:04 PM PDT 24 Jul 31 07:14:06 PM PDT 24 108030949 ps
T299 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.540241218 Jul 31 07:13:31 PM PDT 24 Jul 31 07:13:31 PM PDT 24 42068244 ps
T2872 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.131705196 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:36 PM PDT 24 42005261 ps
T224 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1005833231 Jul 31 07:14:04 PM PDT 24 Jul 31 07:14:10 PM PDT 24 1979469005 ps
T308 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1652882142 Jul 31 07:14:15 PM PDT 24 Jul 31 07:14:20 PM PDT 24 1140372413 ps
T221 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1284279284 Jul 31 07:13:59 PM PDT 24 Jul 31 07:14:00 PM PDT 24 126519105 ps
T2873 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.228419115 Jul 31 07:13:59 PM PDT 24 Jul 31 07:14:01 PM PDT 24 105186902 ps
T2874 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3679759401 Jul 31 07:13:46 PM PDT 24 Jul 31 07:13:51 PM PDT 24 694834679 ps
T276 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.745304162 Jul 31 07:14:08 PM PDT 24 Jul 31 07:14:11 PM PDT 24 544893085 ps
T227 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1174919355 Jul 31 07:13:22 PM PDT 24 Jul 31 07:13:24 PM PDT 24 116795770 ps
T277 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.128133428 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:43 PM PDT 24 1705829108 ps
T259 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3690195239 Jul 31 07:13:29 PM PDT 24 Jul 31 07:13:33 PM PDT 24 329915484 ps
T225 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2975549705 Jul 31 07:13:48 PM PDT 24 Jul 31 07:13:50 PM PDT 24 186241438 ps
T301 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3919450379 Jul 31 07:16:42 PM PDT 24 Jul 31 07:16:43 PM PDT 24 33385193 ps
T2875 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.875909401 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:38 PM PDT 24 36396416 ps
T260 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3898897736 Jul 31 07:14:06 PM PDT 24 Jul 31 07:14:07 PM PDT 24 35348891 ps
T2876 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3193510476 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:36 PM PDT 24 57314564 ps
T2877 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1947436091 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:36 PM PDT 24 86656520 ps
T310 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2416608808 Jul 31 07:13:46 PM PDT 24 Jul 31 07:13:51 PM PDT 24 641767738 ps
T263 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2338144339 Jul 31 07:13:46 PM PDT 24 Jul 31 07:13:47 PM PDT 24 122912572 ps
T2878 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1984498931 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:39 PM PDT 24 441965219 ps
T2879 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.913793768 Jul 31 07:13:59 PM PDT 24 Jul 31 07:14:00 PM PDT 24 68307806 ps
T2880 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.716934974 Jul 31 07:14:14 PM PDT 24 Jul 31 07:14:15 PM PDT 24 124698910 ps
T223 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4109767607 Jul 31 07:13:29 PM PDT 24 Jul 31 07:13:31 PM PDT 24 70079427 ps
T2881 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2388986854 Jul 31 07:16:51 PM PDT 24 Jul 31 07:16:52 PM PDT 24 30611041 ps
T302 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4250395608 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:37 PM PDT 24 28503740 ps
T229 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.250131496 Jul 31 07:16:34 PM PDT 24 Jul 31 07:16:36 PM PDT 24 178352531 ps
T2882 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4269095695 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:38 PM PDT 24 165570284 ps
T2883 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.84034935 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:08 PM PDT 24 44793044 ps
T226 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.493085721 Jul 31 07:14:06 PM PDT 24 Jul 31 07:14:10 PM PDT 24 109859050 ps
T2884 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.33553919 Jul 31 07:13:38 PM PDT 24 Jul 31 07:13:42 PM PDT 24 689187120 ps
T2885 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.957962787 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:38 PM PDT 24 148085198 ps
T2886 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3578301847 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:36 PM PDT 24 43296039 ps
T304 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1686804299 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:41 PM PDT 24 1274130450 ps
T2887 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2197605968 Jul 31 07:16:43 PM PDT 24 Jul 31 07:16:45 PM PDT 24 105047098 ps
T2888 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2835132606 Jul 31 07:14:14 PM PDT 24 Jul 31 07:14:16 PM PDT 24 192494815 ps
T2889 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1462703875 Jul 31 07:16:38 PM PDT 24 Jul 31 07:16:39 PM PDT 24 42802102 ps
T2890 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3412432286 Jul 31 07:16:46 PM PDT 24 Jul 31 07:16:47 PM PDT 24 97260382 ps
T2891 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.227581346 Jul 31 07:16:42 PM PDT 24 Jul 31 07:16:43 PM PDT 24 67204406 ps
T2892 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1794393675 Jul 31 07:13:29 PM PDT 24 Jul 31 07:13:30 PM PDT 24 90108066 ps
T2893 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2896677102 Jul 31 07:13:38 PM PDT 24 Jul 31 07:13:39 PM PDT 24 97195276 ps
T262 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3084734826 Jul 31 07:13:50 PM PDT 24 Jul 31 07:13:54 PM PDT 24 348866884 ps
T2894 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.376167508 Jul 31 07:13:23 PM PDT 24 Jul 31 07:13:24 PM PDT 24 81892722 ps
T2895 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2395013993 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:08 PM PDT 24 71923798 ps
T2896 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3522149604 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:08 PM PDT 24 121935600 ps
T2897 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.840584486 Jul 31 07:13:20 PM PDT 24 Jul 31 07:13:21 PM PDT 24 55497305 ps
T2898 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3174882948 Jul 31 07:13:53 PM PDT 24 Jul 31 07:13:55 PM PDT 24 68062737 ps
T2899 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3397833357 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:38 PM PDT 24 93112339 ps
T2900 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2725813730 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:37 PM PDT 24 120281055 ps
T2901 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1922652829 Jul 31 07:16:40 PM PDT 24 Jul 31 07:16:41 PM PDT 24 44155620 ps
T2902 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1790226479 Jul 31 07:13:12 PM PDT 24 Jul 31 07:13:14 PM PDT 24 85133528 ps
T306 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2859346287 Jul 31 07:13:29 PM PDT 24 Jul 31 07:13:32 PM PDT 24 393389677 ps
T2903 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3104420280 Jul 31 07:16:42 PM PDT 24 Jul 31 07:16:44 PM PDT 24 45375540 ps
T2904 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1706500113 Jul 31 07:13:46 PM PDT 24 Jul 31 07:13:47 PM PDT 24 45534917 ps
T2905 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4132554282 Jul 31 07:13:30 PM PDT 24 Jul 31 07:13:35 PM PDT 24 504908740 ps
T2906 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3662511244 Jul 31 07:13:46 PM PDT 24 Jul 31 07:13:46 PM PDT 24 38457875 ps
T2907 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.853559685 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:37 PM PDT 24 70493735 ps
T2908 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1222752929 Jul 31 07:13:54 PM PDT 24 Jul 31 07:13:55 PM PDT 24 51593238 ps
T2909 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1173810423 Jul 31 07:16:38 PM PDT 24 Jul 31 07:16:42 PM PDT 24 261055407 ps
T2910 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2989551261 Jul 31 07:13:46 PM PDT 24 Jul 31 07:13:48 PM PDT 24 281372299 ps
T2911 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3330616004 Jul 31 07:13:38 PM PDT 24 Jul 31 07:13:40 PM PDT 24 156762943 ps
T2912 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1902661395 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:37 PM PDT 24 53257333 ps
T2913 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4130519976 Jul 31 07:13:53 PM PDT 24 Jul 31 07:13:55 PM PDT 24 68911184 ps
T2914 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2310048441 Jul 31 07:13:27 PM PDT 24 Jul 31 07:13:29 PM PDT 24 160819720 ps
T2915 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.104581580 Jul 31 07:13:23 PM PDT 24 Jul 31 07:13:28 PM PDT 24 734399583 ps
T2916 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.970261173 Jul 31 07:16:51 PM PDT 24 Jul 31 07:16:52 PM PDT 24 47618420 ps
T2917 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3987784202 Jul 31 07:16:40 PM PDT 24 Jul 31 07:16:43 PM PDT 24 285142379 ps
T2918 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.810135382 Jul 31 07:13:53 PM PDT 24 Jul 31 07:14:01 PM PDT 24 1853010859 ps
T2919 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1109729621 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:37 PM PDT 24 185542175 ps
T2920 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3252708183 Jul 31 07:13:54 PM PDT 24 Jul 31 07:13:56 PM PDT 24 101338307 ps
T2921 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2900444566 Jul 31 07:14:01 PM PDT 24 Jul 31 07:14:02 PM PDT 24 82380067 ps
T2922 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1423065901 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:36 PM PDT 24 65034258 ps
T2923 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.478526733 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:39 PM PDT 24 225135174 ps
T2924 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1920730644 Jul 31 07:16:33 PM PDT 24 Jul 31 07:16:34 PM PDT 24 76692490 ps
T2925 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2006432376 Jul 31 07:14:14 PM PDT 24 Jul 31 07:14:15 PM PDT 24 39562201 ps
T2926 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.433669635 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:10 PM PDT 24 201837525 ps
T2927 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1807841933 Jul 31 07:13:28 PM PDT 24 Jul 31 07:13:30 PM PDT 24 140194846 ps
T2928 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2748828135 Jul 31 07:13:37 PM PDT 24 Jul 31 07:13:40 PM PDT 24 195546124 ps
T2929 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.494851470 Jul 31 07:14:04 PM PDT 24 Jul 31 07:14:06 PM PDT 24 83256846 ps
T309 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3032504516 Jul 31 07:13:58 PM PDT 24 Jul 31 07:14:04 PM PDT 24 1119372181 ps
T2930 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.342513211 Jul 31 07:16:44 PM PDT 24 Jul 31 07:16:45 PM PDT 24 67457129 ps
T2931 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1541169973 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:37 PM PDT 24 55810918 ps
T307 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.612629360 Jul 31 07:14:13 PM PDT 24 Jul 31 07:14:18 PM PDT 24 522720278 ps
T2932 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2589717314 Jul 31 07:13:21 PM PDT 24 Jul 31 07:13:23 PM PDT 24 206536627 ps
T230 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2786196274 Jul 31 07:13:24 PM PDT 24 Jul 31 07:13:30 PM PDT 24 2189274478 ps
T2933 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1669679683 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:08 PM PDT 24 78811467 ps
T2934 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1518299630 Jul 31 07:13:22 PM PDT 24 Jul 31 07:13:24 PM PDT 24 109191904 ps
T2935 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1320739872 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:38 PM PDT 24 126084529 ps
T2936 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3179240817 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:37 PM PDT 24 92359511 ps
T2937 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.25315896 Jul 31 07:14:15 PM PDT 24 Jul 31 07:14:18 PM PDT 24 80793659 ps
T2938 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2479975767 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:38 PM PDT 24 202340253 ps
T2939 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3598894254 Jul 31 07:16:45 PM PDT 24 Jul 31 07:16:46 PM PDT 24 65377315 ps
T2940 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3114489810 Jul 31 07:13:24 PM PDT 24 Jul 31 07:13:25 PM PDT 24 108403476 ps
T2941 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1669054929 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:36 PM PDT 24 67333035 ps
T2942 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4132582326 Jul 31 07:13:37 PM PDT 24 Jul 31 07:13:42 PM PDT 24 790268607 ps
T2943 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.166088219 Jul 31 07:13:47 PM PDT 24 Jul 31 07:13:48 PM PDT 24 144539189 ps
T2944 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1199053457 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:09 PM PDT 24 94823847 ps
T305 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2200713685 Jul 31 07:16:38 PM PDT 24 Jul 31 07:16:43 PM PDT 24 783919935 ps
T2945 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.238718927 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:39 PM PDT 24 295249575 ps
T2946 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3775864143 Jul 31 07:16:34 PM PDT 24 Jul 31 07:16:35 PM PDT 24 64308324 ps
T2947 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3892353971 Jul 31 07:16:38 PM PDT 24 Jul 31 07:16:39 PM PDT 24 66713418 ps
T2948 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4171377986 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:37 PM PDT 24 69929254 ps
T2949 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1903170933 Jul 31 07:16:35 PM PDT 24 Jul 31 07:16:41 PM PDT 24 800638983 ps
T2950 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.735709491 Jul 31 07:13:22 PM PDT 24 Jul 31 07:13:25 PM PDT 24 117965017 ps
T2951 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3545358855 Jul 31 07:14:15 PM PDT 24 Jul 31 07:14:16 PM PDT 24 130762863 ps
T2952 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1926479701 Jul 31 07:16:38 PM PDT 24 Jul 31 07:16:39 PM PDT 24 201229985 ps
T2953 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1178771694 Jul 31 07:14:00 PM PDT 24 Jul 31 07:14:01 PM PDT 24 53869988 ps
T2954 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.284130504 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:08 PM PDT 24 246335641 ps
T2955 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.632347638 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:37 PM PDT 24 35653137 ps
T2956 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4093898016 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:40 PM PDT 24 219840708 ps
T2957 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3308491677 Jul 31 07:16:43 PM PDT 24 Jul 31 07:16:44 PM PDT 24 35946239 ps
T2958 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3766634642 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:37 PM PDT 24 114707602 ps
T2959 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1547449092 Jul 31 07:16:36 PM PDT 24 Jul 31 07:16:37 PM PDT 24 43796512 ps
T2960 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3478091581 Jul 31 07:16:34 PM PDT 24 Jul 31 07:16:35 PM PDT 24 58483306 ps
T2961 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2509603467 Jul 31 07:13:38 PM PDT 24 Jul 31 07:13:39 PM PDT 24 136272016 ps
T2962 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3419078136 Jul 31 07:16:49 PM PDT 24 Jul 31 07:16:50 PM PDT 24 30776416 ps
T2963 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2357337109 Jul 31 07:16:42 PM PDT 24 Jul 31 07:16:43 PM PDT 24 43260088 ps
T2964 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.336464265 Jul 31 07:14:04 PM PDT 24 Jul 31 07:14:05 PM PDT 24 33699403 ps
T2965 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2371850157 Jul 31 07:16:43 PM PDT 24 Jul 31 07:16:44 PM PDT 24 69122916 ps
T2966 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2240262709 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:08 PM PDT 24 44925210 ps
T2967 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.484344807 Jul 31 07:16:44 PM PDT 24 Jul 31 07:16:44 PM PDT 24 39382039 ps
T2968 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1987350667 Jul 31 07:16:37 PM PDT 24 Jul 31 07:16:38 PM PDT 24 43276434 ps
T2969 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.276665934 Jul 31 07:13:13 PM PDT 24 Jul 31 07:13:20 PM PDT 24 2295648063 ps
T2970 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.373174393 Jul 31 07:16:47 PM PDT 24 Jul 31 07:16:47 PM PDT 24 45913340 ps
T2971 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.218272303 Jul 31 07:13:54 PM PDT 24 Jul 31 07:13:55 PM PDT 24 95898827 ps
T2972 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2561696373 Jul 31 07:16:44 PM PDT 24 Jul 31 07:16:44 PM PDT 24 57840165 ps
T2973 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.305568337 Jul 31 07:14:07 PM PDT 24 Jul 31 07:14:08 PM PDT 24 104769985 ps
T2974 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1389240016 Jul 31 07:16:44 PM PDT 24 Jul 31 07:16:44 PM PDT 24 73049744 ps
T2975 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3841238303 Jul 31 07:13:37 PM PDT 24 Jul 31 07:13:40 PM PDT 24 95817204 ps
T2976 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3670842236 Jul 31 07:13:30 PM PDT 24 Jul 31 07:13:36 PM PDT 24 1001049728 ps

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1173346850
Short name T7
Test name
Test status
Simulation time 13420905939 ps
CPU time 17.01 seconds
Started Jul 31 05:41:07 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 207224 kb
Host smart-35d32048-3b41-4f87-8456-84f2a8d2e417
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173346850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1173346850
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_device_address.4153171267
Short name T74
Test name
Test status
Simulation time 8660539941 ps
CPU time 18.66 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:46:07 PM PDT 24
Peak memory 207204 kb
Host smart-73cb5de5-8f89-4f8a-9e32-e6d2a91e059c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41531
71267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.4153171267
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.2715319800
Short name T6
Test name
Test status
Simulation time 11901819910 ps
CPU time 74.24 seconds
Started Jul 31 05:40:46 PM PDT 24
Finished Jul 31 05:42:01 PM PDT 24
Peak memory 217992 kb
Host smart-bcff888a-e618-479a-a1e9-fff9cff324a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2715319800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.2715319800
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.4201618946
Short name T297
Test name
Test status
Simulation time 41381758 ps
CPU time 0.76 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 206540 kb
Host smart-934d87f4-33d6-4a98-8ca3-a277fd41d959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4201618946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.4201618946
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.989652018
Short name T212
Test name
Test status
Simulation time 472550842 ps
CPU time 2.7 seconds
Started Jul 31 07:13:58 PM PDT 24
Finished Jul 31 07:14:01 PM PDT 24
Peak memory 206700 kb
Host smart-1167a3a2-96de-4a4f-b3e4-4a3e87452fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=989652018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.989652018
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2965420066
Short name T90
Test name
Test status
Simulation time 200278201 ps
CPU time 0.91 seconds
Started Jul 31 05:47:14 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 206996 kb
Host smart-18552356-2971-4157-a9a4-a28957d1f0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29654
20066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2965420066
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3049825217
Short name T53
Test name
Test status
Simulation time 1157774039 ps
CPU time 2.97 seconds
Started Jul 31 05:39:48 PM PDT 24
Finished Jul 31 05:39:51 PM PDT 24
Peak memory 207148 kb
Host smart-00de5214-6690-4198-81d3-36a3291009b0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3049825217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3049825217
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.1008452488
Short name T37
Test name
Test status
Simulation time 10524135366 ps
CPU time 134.82 seconds
Started Jul 31 05:46:25 PM PDT 24
Finished Jul 31 05:48:40 PM PDT 24
Peak memory 207180 kb
Host smart-85ce2d6c-71ae-4f34-9880-24ad8a34993e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1008452488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.1008452488
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2401769934
Short name T19
Test name
Test status
Simulation time 135825891 ps
CPU time 0.82 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:39:28 PM PDT 24
Peak memory 207004 kb
Host smart-1a9913d8-4bfb-4330-bd09-d61f7880cf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24017
69934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2401769934
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2881115623
Short name T428
Test name
Test status
Simulation time 4417193173 ps
CPU time 6.9 seconds
Started Jul 31 05:42:11 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 207176 kb
Host smart-2127991d-65c1-4687-8b9a-86c3f8a28fdf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881115623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.2881115623
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2506339419
Short name T105
Test name
Test status
Simulation time 169461481 ps
CPU time 0.95 seconds
Started Jul 31 05:41:36 PM PDT 24
Finished Jul 31 05:41:37 PM PDT 24
Peak memory 207028 kb
Host smart-2a4ee896-cc45-46f9-96d8-2fe9d7baeb31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25063
39419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2506339419
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.4186564331
Short name T98
Test name
Test status
Simulation time 314353115 ps
CPU time 1.1 seconds
Started Jul 31 05:39:14 PM PDT 24
Finished Jul 31 05:39:15 PM PDT 24
Peak memory 206996 kb
Host smart-4e3fedb4-297f-4383-a4ba-f4210072d6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41865
64331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.4186564331
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.3848480467
Short name T32
Test name
Test status
Simulation time 37741638 ps
CPU time 0.7 seconds
Started Jul 31 05:40:20 PM PDT 24
Finished Jul 31 05:40:21 PM PDT 24
Peak memory 206964 kb
Host smart-bcd1c582-059d-4b1a-9d6b-d8aa7e659766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38484
80467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3848480467
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.626278583
Short name T216
Test name
Test status
Simulation time 92556935 ps
CPU time 2.51 seconds
Started Jul 31 07:13:59 PM PDT 24
Finished Jul 31 07:14:02 PM PDT 24
Peak memory 214952 kb
Host smart-6cfe1cda-1055-4b4c-b226-fc8f421a7eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=626278583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.626278583
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1202161292
Short name T193
Test name
Test status
Simulation time 33994165 ps
CPU time 0.73 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:51 PM PDT 24
Peak memory 206500 kb
Host smart-13fcab25-36f7-48de-b608-9c8722b33bd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1202161292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1202161292
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.2054668606
Short name T198
Test name
Test status
Simulation time 778264670 ps
CPU time 1.56 seconds
Started Jul 31 05:39:38 PM PDT 24
Finished Jul 31 05:39:40 PM PDT 24
Peak memory 223948 kb
Host smart-a39ed03d-9342-478a-88cc-06d6ca5ab7f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2054668606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.2054668606
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2968366663
Short name T138
Test name
Test status
Simulation time 7468763556 ps
CPU time 80.3 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:41:10 PM PDT 24
Peak memory 217376 kb
Host smart-e842f4d7-8fa4-4e74-a438-fc1518126212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29683
66663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2968366663
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.429750944
Short name T30
Test name
Test status
Simulation time 34365895 ps
CPU time 0.69 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:31 PM PDT 24
Peak memory 207020 kb
Host smart-b0557e13-2b88-4b2e-a7ad-6cd527efdfc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=429750944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.429750944
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.2859604762
Short name T39
Test name
Test status
Simulation time 20218946995 ps
CPU time 26.16 seconds
Started Jul 31 05:39:21 PM PDT 24
Finished Jul 31 05:39:48 PM PDT 24
Peak memory 206716 kb
Host smart-2d84547b-42ee-4a6c-8132-64a1b4a064b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28596
04762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2859604762
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.166294128
Short name T65
Test name
Test status
Simulation time 140565240 ps
CPU time 0.88 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:43:27 PM PDT 24
Peak memory 206972 kb
Host smart-ec25917a-926e-4a9c-900d-f771005a279d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16629
4128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.166294128
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.175564305
Short name T209
Test name
Test status
Simulation time 136592525 ps
CPU time 1.05 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 206620 kb
Host smart-655dac2d-b6a4-4862-aa7e-d653fa24e727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=175564305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.175564305
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3591061015
Short name T147
Test name
Test status
Simulation time 3858068851 ps
CPU time 43.58 seconds
Started Jul 31 05:44:09 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 216804 kb
Host smart-811abd57-fb91-4523-92e5-11d962f15c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35910
61015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3591061015
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2276726629
Short name T82
Test name
Test status
Simulation time 19239415017 ps
CPU time 44.23 seconds
Started Jul 31 05:42:46 PM PDT 24
Finished Jul 31 05:43:30 PM PDT 24
Peak memory 207268 kb
Host smart-e79783f8-6ac5-4e16-84e6-2108cb9874dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22767
26629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2276726629
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.2256545341
Short name T70
Test name
Test status
Simulation time 6415702964 ps
CPU time 65.17 seconds
Started Jul 31 05:39:46 PM PDT 24
Finished Jul 31 05:40:51 PM PDT 24
Peak memory 223440 kb
Host smart-a8ec621c-2453-49d0-8173-252428f9971e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256545341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.2256545341
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1002940484
Short name T298
Test name
Test status
Simulation time 110078374 ps
CPU time 0.85 seconds
Started Jul 31 07:16:50 PM PDT 24
Finished Jul 31 07:16:51 PM PDT 24
Peak memory 206568 kb
Host smart-d4e38e30-0b23-42f6-b444-bad950c16300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1002940484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1002940484
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1736190464
Short name T601
Test name
Test status
Simulation time 210532954 ps
CPU time 0.89 seconds
Started Jul 31 05:39:28 PM PDT 24
Finished Jul 31 05:39:29 PM PDT 24
Peak memory 207012 kb
Host smart-cf27ba5b-5586-48d0-b94f-683a5fa1174f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17361
90464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1736190464
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1414697214
Short name T42
Test name
Test status
Simulation time 361733737 ps
CPU time 1.27 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:27 PM PDT 24
Peak memory 206596 kb
Host smart-618734c8-5416-49f8-839f-5084f38fb263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14146
97214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1414697214
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2892100219
Short name T343
Test name
Test status
Simulation time 215649720 ps
CPU time 0.96 seconds
Started Jul 31 05:43:27 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 206996 kb
Host smart-8cead4b7-f982-4f6b-a47e-1313b1f08f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28921
00219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2892100219
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3321757578
Short name T321
Test name
Test status
Simulation time 15292357407 ps
CPU time 31.91 seconds
Started Jul 31 05:43:13 PM PDT 24
Finished Jul 31 05:43:45 PM PDT 24
Peak memory 207140 kb
Host smart-065a9f37-1d35-4d8b-92c6-dad492fa71e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33217
57578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3321757578
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_device_address.1534455289
Short name T318
Test name
Test status
Simulation time 8191900303 ps
CPU time 18.5 seconds
Started Jul 31 05:45:39 PM PDT 24
Finished Jul 31 05:45:58 PM PDT 24
Peak memory 207176 kb
Host smart-773160a8-54de-4c50-b09e-ff5625a4ede4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15344
55289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1534455289
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.276665934
Short name T2969
Test name
Test status
Simulation time 2295648063 ps
CPU time 6.88 seconds
Started Jul 31 07:13:13 PM PDT 24
Finished Jul 31 07:13:20 PM PDT 24
Peak memory 206792 kb
Host smart-4fb84de7-614b-4c1e-a70f-9014fffb1661
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=276665934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.276665934
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4109767607
Short name T223
Test name
Test status
Simulation time 70079427 ps
CPU time 1.79 seconds
Started Jul 31 07:13:29 PM PDT 24
Finished Jul 31 07:13:31 PM PDT 24
Peak memory 206760 kb
Host smart-f76b3fd6-48a0-4098-ae9e-0a61e52f5946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4109767607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4109767607
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.561227982
Short name T150
Test name
Test status
Simulation time 10883114655 ps
CPU time 81.12 seconds
Started Jul 31 05:39:40 PM PDT 24
Finished Jul 31 05:41:01 PM PDT 24
Peak memory 223452 kb
Host smart-026966fa-17ed-4388-8041-cc3680653a28
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=561227982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.561227982
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.2137450828
Short name T641
Test name
Test status
Simulation time 87202836815 ps
CPU time 152.07 seconds
Started Jul 31 05:39:35 PM PDT 24
Finished Jul 31 05:42:07 PM PDT 24
Peak memory 207176 kb
Host smart-0d34f38b-2f93-4238-854b-ca4724c7a794
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2137450828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.2137450828
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/30.usbdev_device_address.3020187009
Short name T296
Test name
Test status
Simulation time 16140361358 ps
CPU time 41.58 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 207232 kb
Host smart-5a58103e-96dd-4d37-9f47-24c9d996f5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30201
87009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3020187009
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.1093399999
Short name T64
Test name
Test status
Simulation time 430233766 ps
CPU time 1.46 seconds
Started Jul 31 05:39:11 PM PDT 24
Finished Jul 31 05:39:12 PM PDT 24
Peak memory 206992 kb
Host smart-d6b14e3c-e265-42ab-98cf-6354b808ec54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10933
99999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.1093399999
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.943556888
Short name T56
Test name
Test status
Simulation time 178293316 ps
CPU time 0.87 seconds
Started Jul 31 05:39:02 PM PDT 24
Finished Jul 31 05:39:03 PM PDT 24
Peak memory 206996 kb
Host smart-17b7d5ce-3ead-4a3a-9551-e59664718021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94355
6888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.943556888
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.1424649621
Short name T663
Test name
Test status
Simulation time 159424579 ps
CPU time 0.83 seconds
Started Jul 31 05:42:02 PM PDT 24
Finished Jul 31 05:42:03 PM PDT 24
Peak memory 206996 kb
Host smart-80619483-a6f6-41fa-9045-245cf622fd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14246
49621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.1424649621
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.3485193243
Short name T5
Test name
Test status
Simulation time 6765929391 ps
CPU time 185.97 seconds
Started Jul 31 05:41:14 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 215420 kb
Host smart-3f271772-00fe-4ff4-8c4f-c4a21396b871
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485193243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.3485193243
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.612629360
Short name T307
Test name
Test status
Simulation time 522720278 ps
CPU time 4.01 seconds
Started Jul 31 07:14:13 PM PDT 24
Finished Jul 31 07:14:18 PM PDT 24
Peak memory 206744 kb
Host smart-afbb45cd-f859-4a8b-9763-ec7f012c255d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=612629360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.612629360
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1004403778
Short name T76
Test name
Test status
Simulation time 15093490340 ps
CPU time 102.32 seconds
Started Jul 31 05:39:59 PM PDT 24
Finished Jul 31 05:41:41 PM PDT 24
Peak memory 217984 kb
Host smart-665265b9-9063-4d8c-9609-2403f84eec29
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004403778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1004403778
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2006432376
Short name T2925
Test name
Test status
Simulation time 39562201 ps
CPU time 0.74 seconds
Started Jul 31 07:14:14 PM PDT 24
Finished Jul 31 07:14:15 PM PDT 24
Peak memory 206480 kb
Host smart-e950997f-21e9-4744-a703-46d2a8c8a821
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2006432376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2006432376
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1682953695
Short name T328
Test name
Test status
Simulation time 5204521289 ps
CPU time 52.41 seconds
Started Jul 31 05:39:12 PM PDT 24
Finished Jul 31 05:40:05 PM PDT 24
Peak memory 215328 kb
Host smart-34658284-f669-40b7-a532-4e19ef097e8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16829
53695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1682953695
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.4163418331
Short name T325
Test name
Test status
Simulation time 82108214681 ps
CPU time 134.53 seconds
Started Jul 31 05:39:10 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 207228 kb
Host smart-e526f28a-56b9-4c87-8baa-c6fd9279e0f7
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4163418331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.4163418331
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.2439547258
Short name T331
Test name
Test status
Simulation time 95009562507 ps
CPU time 154.73 seconds
Started Jul 31 05:39:10 PM PDT 24
Finished Jul 31 05:41:45 PM PDT 24
Peak memory 207172 kb
Host smart-0b20cadc-585e-462c-8a9b-8a0f372801f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439547258 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.2439547258
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2899409381
Short name T144
Test name
Test status
Simulation time 8301135522 ps
CPU time 43.04 seconds
Started Jul 31 05:39:21 PM PDT 24
Finished Jul 31 05:40:04 PM PDT 24
Peak memory 218064 kb
Host smart-78ffe500-779a-4645-a9d1-251cb2ffb3df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899409381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2899409381
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.687215463
Short name T135
Test name
Test status
Simulation time 208825293 ps
CPU time 0.92 seconds
Started Jul 31 05:39:21 PM PDT 24
Finished Jul 31 05:39:22 PM PDT 24
Peak memory 206608 kb
Host smart-d57cd04c-9c86-400f-86c5-a33107425ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68721
5463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.687215463
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.2662906657
Short name T537
Test name
Test status
Simulation time 171891710 ps
CPU time 0.84 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 206984 kb
Host smart-caaf70e0-fcdf-4e8d-89fc-a0f3183dd439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26629
06657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.2662906657
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3871052583
Short name T445
Test name
Test status
Simulation time 144863188 ps
CPU time 0.85 seconds
Started Jul 31 05:41:23 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 206952 kb
Host smart-f3943ba1-3784-4d6c-a9df-c23e8a0bf71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38710
52583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3871052583
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.1566385598
Short name T96
Test name
Test status
Simulation time 139880918 ps
CPU time 0.86 seconds
Started Jul 31 05:39:26 PM PDT 24
Finished Jul 31 05:39:27 PM PDT 24
Peak memory 206944 kb
Host smart-49d3e43e-9de2-43d4-937e-be99c49ff628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15663
85598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.1566385598
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3074777949
Short name T33
Test name
Test status
Simulation time 44289592 ps
CPU time 0.72 seconds
Started Jul 31 05:39:41 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206928 kb
Host smart-113412b9-f474-4693-8999-0271db6452cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30747
77949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3074777949
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3060444929
Short name T49
Test name
Test status
Simulation time 174384119 ps
CPU time 0.98 seconds
Started Jul 31 05:39:03 PM PDT 24
Finished Jul 31 05:39:04 PM PDT 24
Peak memory 206984 kb
Host smart-b91ea53a-275f-4f96-94b4-b3dfa229d0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30604
44929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3060444929
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.2428114904
Short name T58
Test name
Test status
Simulation time 4164721492 ps
CPU time 10.06 seconds
Started Jul 31 05:39:09 PM PDT 24
Finished Jul 31 05:39:20 PM PDT 24
Peak memory 207264 kb
Host smart-760b4583-07fc-4f7f-9fe2-7a5aff00fe80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24281
14904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.2428114904
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.877108577
Short name T59
Test name
Test status
Simulation time 165612788 ps
CPU time 0.95 seconds
Started Jul 31 05:39:13 PM PDT 24
Finished Jul 31 05:39:14 PM PDT 24
Peak memory 207008 kb
Host smart-63e919e9-a8ee-4799-8e72-d2b95a659dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87710
8577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.877108577
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3737179684
Short name T1675
Test name
Test status
Simulation time 181094890 ps
CPU time 0.88 seconds
Started Jul 31 05:39:20 PM PDT 24
Finished Jul 31 05:39:21 PM PDT 24
Peak memory 206972 kb
Host smart-6ca3b8a2-9742-40d9-86a0-dffcdbcc0b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37371
79684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3737179684
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.487412209
Short name T51
Test name
Test status
Simulation time 172703264 ps
CPU time 0.93 seconds
Started Jul 31 05:39:24 PM PDT 24
Finished Jul 31 05:39:25 PM PDT 24
Peak memory 206960 kb
Host smart-6cb780e6-d16b-4ff0-94ac-9322fdccaebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48741
2209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.487412209
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2786196274
Short name T230
Test name
Test status
Simulation time 2189274478 ps
CPU time 5.49 seconds
Started Jul 31 07:13:24 PM PDT 24
Finished Jul 31 07:13:30 PM PDT 24
Peak memory 206856 kb
Host smart-b7c5617c-0aa5-499c-9515-a091eadf1d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2786196274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2786196274
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.2870813134
Short name T110
Test name
Test status
Simulation time 214034173 ps
CPU time 0.98 seconds
Started Jul 31 05:39:15 PM PDT 24
Finished Jul 31 05:39:16 PM PDT 24
Peak memory 206984 kb
Host smart-c7c0b04d-1bc5-44ab-9e44-c04424ad8364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28708
13134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.2870813134
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.3185378282
Short name T44
Test name
Test status
Simulation time 361667234 ps
CPU time 1.27 seconds
Started Jul 31 05:39:20 PM PDT 24
Finished Jul 31 05:39:21 PM PDT 24
Peak memory 206992 kb
Host smart-2d7af472-2995-4306-9911-40c5fac387ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31853
78282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3185378282
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2517311027
Short name T139
Test name
Test status
Simulation time 6445315605 ps
CPU time 191.77 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:42:37 PM PDT 24
Peak memory 215384 kb
Host smart-fca14aa6-e709-4322-9e29-a438fb2d8719
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25173
11027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2517311027
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2261441302
Short name T2467
Test name
Test status
Simulation time 217877708 ps
CPU time 0.97 seconds
Started Jul 31 05:39:30 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 206984 kb
Host smart-2950b014-d627-4690-82d2-16f8a7826466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22614
41302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2261441302
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.1427643445
Short name T1984
Test name
Test status
Simulation time 197691877 ps
CPU time 0.92 seconds
Started Jul 31 05:41:24 PM PDT 24
Finished Jul 31 05:41:25 PM PDT 24
Peak memory 206992 kb
Host smart-e5d94e33-023f-4a63-bca2-00288f85077d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14276
43445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.1427643445
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.3219561560
Short name T822
Test name
Test status
Simulation time 156035457 ps
CPU time 1.29 seconds
Started Jul 31 05:41:33 PM PDT 24
Finished Jul 31 05:41:34 PM PDT 24
Peak memory 207084 kb
Host smart-4a36d6dc-035e-4d8f-ab3e-8e45056928d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
61560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3219561560
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3660315216
Short name T127
Test name
Test status
Simulation time 255836335 ps
CPU time 0.99 seconds
Started Jul 31 05:41:44 PM PDT 24
Finished Jul 31 05:41:45 PM PDT 24
Peak memory 206980 kb
Host smart-cf99aa01-093a-423f-a566-1606c2b2baa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36603
15216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3660315216
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.2178529020
Short name T117
Test name
Test status
Simulation time 189507730 ps
CPU time 0.93 seconds
Started Jul 31 05:41:57 PM PDT 24
Finished Jul 31 05:41:58 PM PDT 24
Peak memory 207024 kb
Host smart-6ea581bf-4b18-498a-990a-c503426b528d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21785
29020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2178529020
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.1922041817
Short name T120
Test name
Test status
Simulation time 255786980 ps
CPU time 1.01 seconds
Started Jul 31 05:42:35 PM PDT 24
Finished Jul 31 05:42:36 PM PDT 24
Peak memory 206968 kb
Host smart-26ec73dc-9a38-4abf-8088-cb40141f37b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19220
41817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.1922041817
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1827098622
Short name T125
Test name
Test status
Simulation time 222048788 ps
CPU time 0.99 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:01 PM PDT 24
Peak memory 207020 kb
Host smart-331424c7-a540-4703-ac82-aa86f69fe8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18270
98622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1827098622
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.4167702015
Short name T132
Test name
Test status
Simulation time 192306892 ps
CPU time 0.98 seconds
Started Jul 31 05:39:40 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206972 kb
Host smart-9842d5cd-7605-4ae8-9416-80886c81787f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41677
02015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.4167702015
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.4186986350
Short name T115
Test name
Test status
Simulation time 232435878 ps
CPU time 1.02 seconds
Started Jul 31 05:43:27 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 207012 kb
Host smart-470f5859-a4d0-45ce-93ac-7b3ad885e947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41869
86350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.4186986350
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3609839133
Short name T108
Test name
Test status
Simulation time 206308737 ps
CPU time 0.93 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:43:38 PM PDT 24
Peak memory 206968 kb
Host smart-525ee667-f912-47d8-a07d-33ad029d17db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36098
39133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3609839133
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2724151823
Short name T133
Test name
Test status
Simulation time 235476333 ps
CPU time 0.99 seconds
Started Jul 31 05:43:45 PM PDT 24
Finished Jul 31 05:43:46 PM PDT 24
Peak memory 207040 kb
Host smart-0d5eea72-ebb2-48e4-890e-498371b6a75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27241
51823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2724151823
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.735709491
Short name T2950
Test name
Test status
Simulation time 117965017 ps
CPU time 3.2 seconds
Started Jul 31 07:13:22 PM PDT 24
Finished Jul 31 07:13:25 PM PDT 24
Peak memory 206808 kb
Host smart-85c13d20-6097-41f0-b9b6-2044fb47047a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=735709491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.735709491
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3319256644
Short name T254
Test name
Test status
Simulation time 1522704417 ps
CPU time 8.15 seconds
Started Jul 31 07:13:22 PM PDT 24
Finished Jul 31 07:13:31 PM PDT 24
Peak memory 206664 kb
Host smart-3eebbd9d-0735-4d59-a174-9f005b081b7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3319256644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3319256644
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.840584486
Short name T2897
Test name
Test status
Simulation time 55497305 ps
CPU time 0.81 seconds
Started Jul 31 07:13:20 PM PDT 24
Finished Jul 31 07:13:21 PM PDT 24
Peak memory 206616 kb
Host smart-38747b8a-960c-4bc2-a274-4296f64223b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=840584486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.840584486
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1174919355
Short name T227
Test name
Test status
Simulation time 116795770 ps
CPU time 1.42 seconds
Started Jul 31 07:13:22 PM PDT 24
Finished Jul 31 07:13:24 PM PDT 24
Peak memory 216552 kb
Host smart-d6f2cf00-1545-4b64-9871-a304f14199ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174919355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1174919355
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.376167508
Short name T2894
Test name
Test status
Simulation time 81892722 ps
CPU time 0.83 seconds
Started Jul 31 07:13:23 PM PDT 24
Finished Jul 31 07:13:24 PM PDT 24
Peak memory 206556 kb
Host smart-aecaed33-d95e-427a-be59-a90dba9cf1ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=376167508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.376167508
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1153101606
Short name T279
Test name
Test status
Simulation time 51059695 ps
CPU time 0.73 seconds
Started Jul 31 07:13:18 PM PDT 24
Finished Jul 31 07:13:19 PM PDT 24
Peak memory 206496 kb
Host smart-6df61d77-de8e-44a4-baed-2e5927a005fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1153101606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1153101606
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2310048441
Short name T2914
Test name
Test status
Simulation time 160819720 ps
CPU time 2.3 seconds
Started Jul 31 07:13:27 PM PDT 24
Finished Jul 31 07:13:29 PM PDT 24
Peak memory 214716 kb
Host smart-bb6d826a-844c-483b-af54-519ac8c6d6ac
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2310048441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2310048441
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.104581580
Short name T2915
Test name
Test status
Simulation time 734399583 ps
CPU time 4.97 seconds
Started Jul 31 07:13:23 PM PDT 24
Finished Jul 31 07:13:28 PM PDT 24
Peak memory 206624 kb
Host smart-45b97927-36ab-49ed-800c-b9b99f707f29
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=104581580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.104581580
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2589717314
Short name T2932
Test name
Test status
Simulation time 206536627 ps
CPU time 1.75 seconds
Started Jul 31 07:13:21 PM PDT 24
Finished Jul 31 07:13:23 PM PDT 24
Peak memory 206708 kb
Host smart-e8054c72-2c51-4434-9f48-3f434fa2d2da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2589717314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2589717314
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1790226479
Short name T2902
Test name
Test status
Simulation time 85133528 ps
CPU time 2 seconds
Started Jul 31 07:13:12 PM PDT 24
Finished Jul 31 07:13:14 PM PDT 24
Peak memory 206692 kb
Host smart-ca8d6446-497d-494c-b005-a4155f95799c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1790226479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1790226479
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3690195239
Short name T259
Test name
Test status
Simulation time 329915484 ps
CPU time 3.36 seconds
Started Jul 31 07:13:29 PM PDT 24
Finished Jul 31 07:13:33 PM PDT 24
Peak memory 206660 kb
Host smart-c43ee6be-785a-4df0-9cb8-a862cbf5322e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3690195239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3690195239
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3670842236
Short name T2976
Test name
Test status
Simulation time 1001049728 ps
CPU time 5.67 seconds
Started Jul 31 07:13:30 PM PDT 24
Finished Jul 31 07:13:36 PM PDT 24
Peak memory 206632 kb
Host smart-b50ecd7a-f9b9-46a8-8cea-66909fe40dbb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3670842236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.3670842236
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1817569959
Short name T255
Test name
Test status
Simulation time 107983278 ps
CPU time 0.91 seconds
Started Jul 31 07:13:31 PM PDT 24
Finished Jul 31 07:13:32 PM PDT 24
Peak memory 206508 kb
Host smart-f822350a-51a1-4ba7-a76e-432af888a00f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1817569959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1817569959
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1807841933
Short name T2927
Test name
Test status
Simulation time 140194846 ps
CPU time 1.8 seconds
Started Jul 31 07:13:28 PM PDT 24
Finished Jul 31 07:13:30 PM PDT 24
Peak memory 215040 kb
Host smart-d27d9182-f543-4a10-9dce-c5b25d609603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807841933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1807841933
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.223637133
Short name T264
Test name
Test status
Simulation time 96622124 ps
CPU time 1.1 seconds
Started Jul 31 07:13:29 PM PDT 24
Finished Jul 31 07:13:30 PM PDT 24
Peak memory 206576 kb
Host smart-b72af93d-6742-4633-8ccb-2150c46ed376
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=223637133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.223637133
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3114489810
Short name T2940
Test name
Test status
Simulation time 108403476 ps
CPU time 0.8 seconds
Started Jul 31 07:13:24 PM PDT 24
Finished Jul 31 07:13:25 PM PDT 24
Peak memory 206548 kb
Host smart-3b831398-83e1-4f28-9d10-c689c36754ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3114489810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3114489810
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3129544116
Short name T258
Test name
Test status
Simulation time 109122569 ps
CPU time 2.22 seconds
Started Jul 31 07:13:30 PM PDT 24
Finished Jul 31 07:13:32 PM PDT 24
Peak memory 206592 kb
Host smart-238b1635-9751-4e83-bc7d-b2692f9b145e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3129544116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3129544116
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4132554282
Short name T2905
Test name
Test status
Simulation time 504908740 ps
CPU time 4.41 seconds
Started Jul 31 07:13:30 PM PDT 24
Finished Jul 31 07:13:35 PM PDT 24
Peak memory 206704 kb
Host smart-aa53853b-8631-4969-b807-efb6f3f86b8a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4132554282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.4132554282
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1794393675
Short name T2892
Test name
Test status
Simulation time 90108066 ps
CPU time 1.07 seconds
Started Jul 31 07:13:29 PM PDT 24
Finished Jul 31 07:13:30 PM PDT 24
Peak memory 206780 kb
Host smart-4690f74e-4a40-4b08-9bda-e0fd60d3628d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1794393675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1794393675
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1518299630
Short name T2934
Test name
Test status
Simulation time 109191904 ps
CPU time 2.16 seconds
Started Jul 31 07:13:22 PM PDT 24
Finished Jul 31 07:13:24 PM PDT 24
Peak memory 222424 kb
Host smart-84b97416-78d2-4558-b129-9c5c7f9144ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1518299630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1518299630
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3600673219
Short name T231
Test name
Test status
Simulation time 117974383 ps
CPU time 1.36 seconds
Started Jul 31 07:14:15 PM PDT 24
Finished Jul 31 07:14:17 PM PDT 24
Peak memory 215016 kb
Host smart-75c74df2-5772-4bfb-ae46-26a990d99360
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600673219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3600673219
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.716934974
Short name T2880
Test name
Test status
Simulation time 124698910 ps
CPU time 0.91 seconds
Started Jul 31 07:14:14 PM PDT 24
Finished Jul 31 07:14:15 PM PDT 24
Peak memory 206532 kb
Host smart-ab3e0520-695a-45cd-84f4-05168451dd64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=716934974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.716934974
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3333105888
Short name T303
Test name
Test status
Simulation time 39908540 ps
CPU time 0.7 seconds
Started Jul 31 07:14:15 PM PDT 24
Finished Jul 31 07:14:15 PM PDT 24
Peak memory 206528 kb
Host smart-2f6cf7d0-542f-47f4-a8e8-784551e45e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3333105888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3333105888
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2835132606
Short name T2888
Test name
Test status
Simulation time 192494815 ps
CPU time 1.65 seconds
Started Jul 31 07:14:14 PM PDT 24
Finished Jul 31 07:14:16 PM PDT 24
Peak memory 206776 kb
Host smart-1a93324d-c699-4682-a22f-350181fa7c3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2835132606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2835132606
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.433669635
Short name T2926
Test name
Test status
Simulation time 201837525 ps
CPU time 2.87 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:10 PM PDT 24
Peak memory 223056 kb
Host smart-2cd3b9e0-83b1-4368-b848-3f51ba21eb78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=433669635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.433669635
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1652882142
Short name T308
Test name
Test status
Simulation time 1140372413 ps
CPU time 5.25 seconds
Started Jul 31 07:14:15 PM PDT 24
Finished Jul 31 07:14:20 PM PDT 24
Peak memory 206724 kb
Host smart-06b60457-09f3-4811-87c4-fb4ccbb44dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1652882142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1652882142
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1902661395
Short name T2912
Test name
Test status
Simulation time 53257333 ps
CPU time 1.27 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 214880 kb
Host smart-6cea4a56-2491-4309-8b76-2d2627552604
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902661395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1902661395
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3478091581
Short name T2960
Test name
Test status
Simulation time 58483306 ps
CPU time 1.01 seconds
Started Jul 31 07:16:34 PM PDT 24
Finished Jul 31 07:16:35 PM PDT 24
Peak memory 206600 kb
Host smart-88cf69ce-1526-45a8-b993-a3717a10f41e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3478091581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3478091581
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1984498931
Short name T2878
Test name
Test status
Simulation time 441965219 ps
CPU time 1.84 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 206684 kb
Host smart-156eb1c0-1f99-4b18-ac2f-66a8959cab73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1984498931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1984498931
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.25315896
Short name T2937
Test name
Test status
Simulation time 80793659 ps
CPU time 2.24 seconds
Started Jul 31 07:14:15 PM PDT 24
Finished Jul 31 07:14:18 PM PDT 24
Peak memory 215020 kb
Host smart-b2bdf0eb-aa86-4845-822c-fa0d0f5d87d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=25315896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.25315896
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3179240817
Short name T2936
Test name
Test status
Simulation time 92359511 ps
CPU time 2.25 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 214984 kb
Host smart-b0f8236b-892d-4496-a1a9-400ef9efe31d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179240817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3179240817
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3775864143
Short name T2946
Test name
Test status
Simulation time 64308324 ps
CPU time 0.87 seconds
Started Jul 31 07:16:34 PM PDT 24
Finished Jul 31 07:16:35 PM PDT 24
Peak memory 206508 kb
Host smart-181be038-0378-4c49-8f67-e9da8966a518
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3775864143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3775864143
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1423065901
Short name T2922
Test name
Test status
Simulation time 65034258 ps
CPU time 0.77 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 206544 kb
Host smart-ab0001ea-653e-43c4-9398-d26915cdf592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1423065901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1423065901
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.614227185
Short name T269
Test name
Test status
Simulation time 113843906 ps
CPU time 1.66 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206772 kb
Host smart-77d6a55e-9204-4334-9135-f33585d55a58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=614227185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.614227185
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3987784202
Short name T2917
Test name
Test status
Simulation time 285142379 ps
CPU time 3 seconds
Started Jul 31 07:16:40 PM PDT 24
Finished Jul 31 07:16:43 PM PDT 24
Peak memory 222832 kb
Host smart-8dec31b3-b500-44b9-98e8-5b8738fce316
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3987784202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3987784202
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2200713685
Short name T305
Test name
Test status
Simulation time 783919935 ps
CPU time 4.82 seconds
Started Jul 31 07:16:38 PM PDT 24
Finished Jul 31 07:16:43 PM PDT 24
Peak memory 206636 kb
Host smart-918a7d96-730d-4d23-9b60-e2f1b7c5a475
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2200713685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2200713685
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2355769711
Short name T233
Test name
Test status
Simulation time 182649025 ps
CPU time 1.92 seconds
Started Jul 31 07:16:39 PM PDT 24
Finished Jul 31 07:16:41 PM PDT 24
Peak memory 217088 kb
Host smart-67a6af41-cbc4-481d-bddb-f3febe122d98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355769711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2355769711
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.853559685
Short name T2907
Test name
Test status
Simulation time 70493735 ps
CPU time 0.96 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206708 kb
Host smart-7a79798b-124d-4385-9a68-45a663f52b28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=853559685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.853559685
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.131705196
Short name T2872
Test name
Test status
Simulation time 42005261 ps
CPU time 0.71 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 206608 kb
Host smart-34df4d0d-ec18-4436-bc00-5324720e5159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=131705196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.131705196
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2479975767
Short name T2938
Test name
Test status
Simulation time 202340253 ps
CPU time 1.73 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 206816 kb
Host smart-f757a0ee-fa97-4d03-8a5c-f6d614603cc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2479975767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2479975767
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3580972715
Short name T220
Test name
Test status
Simulation time 253451293 ps
CPU time 3.32 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:40 PM PDT 24
Peak memory 206684 kb
Host smart-037c5ef5-18d1-4093-8c25-d802f8a0780f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3580972715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3580972715
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1903170933
Short name T2949
Test name
Test status
Simulation time 800638983 ps
CPU time 5.34 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:41 PM PDT 24
Peak memory 206804 kb
Host smart-211a129b-7562-43c5-b2cb-4dad4005a1eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1903170933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1903170933
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1109729621
Short name T2919
Test name
Test status
Simulation time 185542175 ps
CPU time 1.86 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 215040 kb
Host smart-e8fc9d0c-90bc-466f-92f9-536814c0ba24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109729621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1109729621
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1947436091
Short name T2877
Test name
Test status
Simulation time 86656520 ps
CPU time 0.99 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 206616 kb
Host smart-44867d4c-acea-4226-a5c9-bcc533e5919b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1947436091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1947436091
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3578301847
Short name T2886
Test name
Test status
Simulation time 43296039 ps
CPU time 0.75 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 206500 kb
Host smart-437913bb-4259-4fd2-b11d-51b0bcc1e7a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3578301847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3578301847
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4011210526
Short name T275
Test name
Test status
Simulation time 176906765 ps
CPU time 1.26 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 206732 kb
Host smart-fabf39e4-50de-4cb3-9598-ca8922aac5dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4011210526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.4011210526
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.250131496
Short name T229
Test name
Test status
Simulation time 178352531 ps
CPU time 1.85 seconds
Started Jul 31 07:16:34 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 206728 kb
Host smart-44d27658-55e2-4dcc-8a83-3d063ef09cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=250131496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.250131496
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3060698046
Short name T234
Test name
Test status
Simulation time 486317768 ps
CPU time 2.81 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:40 PM PDT 24
Peak memory 206724 kb
Host smart-f09456aa-d0c9-426a-b42b-e6cb9e8250e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3060698046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3060698046
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.75471894
Short name T188
Test name
Test status
Simulation time 107740666 ps
CPU time 1.4 seconds
Started Jul 31 07:16:38 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 214868 kb
Host smart-c95dd169-4d74-4f59-a695-d6a00d6e9396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75471894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev
_csr_mem_rw_with_rand_reset.75471894
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4171377986
Short name T2948
Test name
Test status
Simulation time 69929254 ps
CPU time 1.03 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206640 kb
Host smart-bee0be1b-e7fb-4e1b-88a1-3a90d8e2ff97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4171377986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4171377986
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3193510476
Short name T2876
Test name
Test status
Simulation time 57314564 ps
CPU time 0.81 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 206524 kb
Host smart-e56513f5-d4a2-4bad-8dab-06cbcd02aa0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3193510476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3193510476
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.957962787
Short name T2885
Test name
Test status
Simulation time 148085198 ps
CPU time 1.19 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 206712 kb
Host smart-369b2d4a-64e2-4372-ab47-910fdd687cfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=957962787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.957962787
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1320739872
Short name T2935
Test name
Test status
Simulation time 126084529 ps
CPU time 2.82 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 220564 kb
Host smart-a7a689e6-7dd8-43dc-8ae9-9938316df6dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1320739872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1320739872
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.238718927
Short name T2945
Test name
Test status
Simulation time 295249575 ps
CPU time 2.44 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 206712 kb
Host smart-51cb30c7-68b8-419a-bc3a-095d874ab510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=238718927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.238718927
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3397833357
Short name T2899
Test name
Test status
Simulation time 93112339 ps
CPU time 2.27 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 214920 kb
Host smart-4100f7f1-0b9d-47d0-a3a0-46b466b542ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397833357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3397833357
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3766634642
Short name T2958
Test name
Test status
Simulation time 114707602 ps
CPU time 1.02 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206640 kb
Host smart-70a5520e-ea0b-4f24-b7b6-6952725a6602
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3766634642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3766634642
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1669054929
Short name T2941
Test name
Test status
Simulation time 67333035 ps
CPU time 0.7 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 206512 kb
Host smart-f5173b74-3c73-4d23-8640-3ddfdbad41b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1669054929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1669054929
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1926479701
Short name T2952
Test name
Test status
Simulation time 201229985 ps
CPU time 1.65 seconds
Started Jul 31 07:16:38 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 206736 kb
Host smart-1aabacfe-8053-4428-a842-6547d42aa86b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1926479701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1926479701
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2725813730
Short name T2900
Test name
Test status
Simulation time 120281055 ps
CPU time 1.56 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206732 kb
Host smart-5edd40e0-f77b-41f7-b8f0-789672758c8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2725813730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2725813730
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2558460268
Short name T235
Test name
Test status
Simulation time 662299453 ps
CPU time 2.87 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 206712 kb
Host smart-ced857f3-6f9c-451f-aed9-010cdaac25a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2558460268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2558460268
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2841303724
Short name T187
Test name
Test status
Simulation time 102767195 ps
CPU time 1.26 seconds
Started Jul 31 07:16:35 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 214936 kb
Host smart-78ae0773-841a-4e9c-ae7c-f6ffa311094c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841303724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2841303724
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1920730644
Short name T2924
Test name
Test status
Simulation time 76692490 ps
CPU time 1.03 seconds
Started Jul 31 07:16:33 PM PDT 24
Finished Jul 31 07:16:34 PM PDT 24
Peak memory 206620 kb
Host smart-2d9acc5a-c589-4e6e-b4f8-69427cd44d38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1920730644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1920730644
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.780024688
Short name T195
Test name
Test status
Simulation time 42976295 ps
CPU time 0.7 seconds
Started Jul 31 07:16:34 PM PDT 24
Finished Jul 31 07:16:35 PM PDT 24
Peak memory 206540 kb
Host smart-449c79d2-016b-4a11-88fa-60c636fbbcfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=780024688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.780024688
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2199266990
Short name T266
Test name
Test status
Simulation time 145985504 ps
CPU time 1.26 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 206696 kb
Host smart-03a55152-5a88-45d3-8157-cfb2820d5df2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2199266990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2199266990
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1173810423
Short name T2909
Test name
Test status
Simulation time 261055407 ps
CPU time 2.92 seconds
Started Jul 31 07:16:38 PM PDT 24
Finished Jul 31 07:16:42 PM PDT 24
Peak memory 206672 kb
Host smart-3d2fb20a-ea9e-4330-86f9-064714493e30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1173810423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1173810423
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1686804299
Short name T304
Test name
Test status
Simulation time 1274130450 ps
CPU time 4.84 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:41 PM PDT 24
Peak memory 206644 kb
Host smart-5abd8c86-b63c-4fcf-990d-7279e5d54bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1686804299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1686804299
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1007445048
Short name T222
Test name
Test status
Simulation time 129500835 ps
CPU time 1.71 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 214952 kb
Host smart-cbbe10c8-946f-414d-a115-f69d40df3c0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007445048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.1007445048
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.809513035
Short name T257
Test name
Test status
Simulation time 63445229 ps
CPU time 0.86 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 206496 kb
Host smart-01173d45-6e82-49b0-a0ca-dd3fdff507e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=809513035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.809513035
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3077782123
Short name T300
Test name
Test status
Simulation time 76844163 ps
CPU time 0.74 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206556 kb
Host smart-834b9146-1491-4acf-ae4c-b54346dac09b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3077782123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3077782123
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3481668982
Short name T265
Test name
Test status
Simulation time 329121729 ps
CPU time 1.72 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 206668 kb
Host smart-2b3de92e-2197-4a17-8207-428b2c5079e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3481668982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3481668982
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.478526733
Short name T2923
Test name
Test status
Simulation time 225135174 ps
CPU time 2.27 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 206688 kb
Host smart-890d7243-28d6-4433-8d9e-a2b9d1d594a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=478526733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.478526733
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.128133428
Short name T277
Test name
Test status
Simulation time 1705829108 ps
CPU time 5.73 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:43 PM PDT 24
Peak memory 206784 kb
Host smart-b682de29-8bb9-4a4c-9ffc-02aff9ae7116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=128133428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.128133428
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3929406271
Short name T228
Test name
Test status
Simulation time 131002427 ps
CPU time 1.69 seconds
Started Jul 31 07:16:34 PM PDT 24
Finished Jul 31 07:16:36 PM PDT 24
Peak memory 214912 kb
Host smart-2cc969cf-c713-40d7-8e58-cc50f5c00e50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929406271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3929406271
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.632347638
Short name T2955
Test name
Test status
Simulation time 35653137 ps
CPU time 0.69 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206524 kb
Host smart-12432315-5c9e-4c0d-abb3-e4db06827bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=632347638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.632347638
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4269095695
Short name T2882
Test name
Test status
Simulation time 165570284 ps
CPU time 1.14 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 206832 kb
Host smart-37aa1eae-3cb0-47f6-9ea7-264be04058cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4269095695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.4269095695
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4093898016
Short name T2956
Test name
Test status
Simulation time 219840708 ps
CPU time 2.53 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:40 PM PDT 24
Peak memory 220252 kb
Host smart-8eb78bb6-cb10-4d8e-ad6d-fadc6b5ed171
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4093898016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4093898016
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1100926687
Short name T189
Test name
Test status
Simulation time 789187813 ps
CPU time 4.82 seconds
Started Jul 31 07:16:34 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 206632 kb
Host smart-ed171878-4e13-4b01-8bd3-e622ea25592e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1100926687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1100926687
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.79226115
Short name T253
Test name
Test status
Simulation time 161419608 ps
CPU time 3.39 seconds
Started Jul 31 07:13:38 PM PDT 24
Finished Jul 31 07:13:42 PM PDT 24
Peak memory 206660 kb
Host smart-5a7072c5-209f-4e18-b2b2-d2cd7eab0966
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=79226115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.79226115
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.33553919
Short name T2884
Test name
Test status
Simulation time 689187120 ps
CPU time 4.46 seconds
Started Jul 31 07:13:38 PM PDT 24
Finished Jul 31 07:13:42 PM PDT 24
Peak memory 206636 kb
Host smart-f494aa54-fd28-4607-abca-02707b8793c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=33553919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.33553919
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2896677102
Short name T2893
Test name
Test status
Simulation time 97195276 ps
CPU time 0.85 seconds
Started Jul 31 07:13:38 PM PDT 24
Finished Jul 31 07:13:39 PM PDT 24
Peak memory 206384 kb
Host smart-f43462f4-0ad0-4bef-a727-23de4b846af4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2896677102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2896677102
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3330616004
Short name T2911
Test name
Test status
Simulation time 156762943 ps
CPU time 1.89 seconds
Started Jul 31 07:13:38 PM PDT 24
Finished Jul 31 07:13:40 PM PDT 24
Peak memory 215056 kb
Host smart-1647add4-ab83-4774-b2df-22d5393d5e2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330616004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.3330616004
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2706376712
Short name T261
Test name
Test status
Simulation time 45000989 ps
CPU time 0.96 seconds
Started Jul 31 07:13:38 PM PDT 24
Finished Jul 31 07:13:39 PM PDT 24
Peak memory 206636 kb
Host smart-f78f37ec-4517-403b-8188-32902ad0e549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2706376712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2706376712
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.540241218
Short name T299
Test name
Test status
Simulation time 42068244 ps
CPU time 0.71 seconds
Started Jul 31 07:13:31 PM PDT 24
Finished Jul 31 07:13:31 PM PDT 24
Peak memory 206536 kb
Host smart-0572bb7c-cc5e-47c8-b371-0637e0eb368c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=540241218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.540241218
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2748828135
Short name T2928
Test name
Test status
Simulation time 195546124 ps
CPU time 2.57 seconds
Started Jul 31 07:13:37 PM PDT 24
Finished Jul 31 07:13:40 PM PDT 24
Peak memory 214784 kb
Host smart-0ad6d8b4-0f4f-4bde-aefb-1a7179e21480
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2748828135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2748828135
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3841238303
Short name T2975
Test name
Test status
Simulation time 95817204 ps
CPU time 2.31 seconds
Started Jul 31 07:13:37 PM PDT 24
Finished Jul 31 07:13:40 PM PDT 24
Peak memory 206612 kb
Host smart-59b58f00-bbec-4b9a-a28d-1277cfbdffc4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3841238303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3841238303
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2509603467
Short name T2961
Test name
Test status
Simulation time 136272016 ps
CPU time 1.58 seconds
Started Jul 31 07:13:38 PM PDT 24
Finished Jul 31 07:13:39 PM PDT 24
Peak memory 206744 kb
Host smart-7504d672-b976-4c82-825a-9e8deff621f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2509603467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2509603467
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2859346287
Short name T306
Test name
Test status
Simulation time 393389677 ps
CPU time 2.83 seconds
Started Jul 31 07:13:29 PM PDT 24
Finished Jul 31 07:13:32 PM PDT 24
Peak memory 206736 kb
Host smart-06e47c59-a167-4d46-9167-09cc0f1b53e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2859346287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2859346287
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1541169973
Short name T2931
Test name
Test status
Simulation time 55810918 ps
CPU time 0.74 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206512 kb
Host smart-8add6ffe-6276-4556-bc92-7878f320bf62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1541169973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1541169973
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.4250395608
Short name T302
Test name
Test status
Simulation time 28503740 ps
CPU time 0.71 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206564 kb
Host smart-61fda90f-b14c-42e7-a9ea-4de09173bdfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4250395608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.4250395608
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1547449092
Short name T2959
Test name
Test status
Simulation time 43796512 ps
CPU time 0.71 seconds
Started Jul 31 07:16:36 PM PDT 24
Finished Jul 31 07:16:37 PM PDT 24
Peak memory 206540 kb
Host smart-6d5f3413-36f8-4a36-88c8-50126360bf29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1547449092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1547449092
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.875909401
Short name T2875
Test name
Test status
Simulation time 36396416 ps
CPU time 0.69 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 206544 kb
Host smart-4441ffd3-fcf8-4c55-9238-4e28fd454ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=875909401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.875909401
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3892353971
Short name T2947
Test name
Test status
Simulation time 66713418 ps
CPU time 0.74 seconds
Started Jul 31 07:16:38 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 206540 kb
Host smart-1476cd1c-efa0-4900-8621-f8b9eaa2aa40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3892353971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3892353971
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1462703875
Short name T2889
Test name
Test status
Simulation time 42802102 ps
CPU time 0.72 seconds
Started Jul 31 07:16:38 PM PDT 24
Finished Jul 31 07:16:39 PM PDT 24
Peak memory 206540 kb
Host smart-a13d52d6-2ac0-4675-a22a-fbaf12f1cd7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1462703875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1462703875
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1987350667
Short name T2968
Test name
Test status
Simulation time 43276434 ps
CPU time 0.73 seconds
Started Jul 31 07:16:37 PM PDT 24
Finished Jul 31 07:16:38 PM PDT 24
Peak memory 206540 kb
Host smart-db1705b7-d620-460c-b8f9-0c5a8bb5ad6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1987350667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1987350667
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.2986166772
Short name T278
Test name
Test status
Simulation time 73781188 ps
CPU time 0.73 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 206500 kb
Host smart-442a1358-5ab6-45a0-8bd2-522a20f56259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2986166772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2986166772
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.1249651259
Short name T194
Test name
Test status
Simulation time 50983461 ps
CPU time 0.71 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 206492 kb
Host smart-70785823-9099-4e12-a219-3036ce95f98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1249651259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1249651259
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3084734826
Short name T262
Test name
Test status
Simulation time 348866884 ps
CPU time 3.52 seconds
Started Jul 31 07:13:50 PM PDT 24
Finished Jul 31 07:13:54 PM PDT 24
Peak memory 206784 kb
Host smart-f66ea084-1b17-4959-994c-b861e174115d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3084734826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3084734826
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4046884676
Short name T2869
Test name
Test status
Simulation time 560810510 ps
CPU time 4.18 seconds
Started Jul 31 07:13:45 PM PDT 24
Finished Jul 31 07:13:50 PM PDT 24
Peak memory 206668 kb
Host smart-2f9fae1b-e2e9-44b3-a129-1590d1df3428
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4046884676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.4046884676
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2989551261
Short name T2910
Test name
Test status
Simulation time 281372299 ps
CPU time 1.16 seconds
Started Jul 31 07:13:46 PM PDT 24
Finished Jul 31 07:13:48 PM PDT 24
Peak memory 206540 kb
Host smart-b3bcc50b-c3d4-4d75-9a27-4684ea31c8a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2989551261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2989551261
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2165717520
Short name T232
Test name
Test status
Simulation time 88086701 ps
CPU time 2.5 seconds
Started Jul 31 07:13:46 PM PDT 24
Finished Jul 31 07:13:48 PM PDT 24
Peak memory 214988 kb
Host smart-edaeac9d-5ee4-4c16-bbfc-7196be40beba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165717520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2165717520
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2338144339
Short name T263
Test name
Test status
Simulation time 122912572 ps
CPU time 0.93 seconds
Started Jul 31 07:13:46 PM PDT 24
Finished Jul 31 07:13:47 PM PDT 24
Peak memory 206624 kb
Host smart-c36179c3-bafe-4424-9f29-a0a7f767938b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2338144339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2338144339
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3662511244
Short name T2906
Test name
Test status
Simulation time 38457875 ps
CPU time 0.72 seconds
Started Jul 31 07:13:46 PM PDT 24
Finished Jul 31 07:13:46 PM PDT 24
Peak memory 206564 kb
Host smart-bdc9b7c6-f214-453d-b676-066d210be905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3662511244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3662511244
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3105590961
Short name T256
Test name
Test status
Simulation time 58032949 ps
CPU time 1.29 seconds
Started Jul 31 07:13:47 PM PDT 24
Finished Jul 31 07:13:48 PM PDT 24
Peak memory 214780 kb
Host smart-a07c3a7c-a5a6-491d-9cfc-b93b40156634
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3105590961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3105590961
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3679759401
Short name T2874
Test name
Test status
Simulation time 694834679 ps
CPU time 4.59 seconds
Started Jul 31 07:13:46 PM PDT 24
Finished Jul 31 07:13:51 PM PDT 24
Peak memory 206604 kb
Host smart-a261e758-75db-4191-9968-4f8f8035b103
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3679759401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3679759401
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.166088219
Short name T2943
Test name
Test status
Simulation time 144539189 ps
CPU time 1.11 seconds
Started Jul 31 07:13:47 PM PDT 24
Finished Jul 31 07:13:48 PM PDT 24
Peak memory 206388 kb
Host smart-46c499a0-3991-4e52-82ce-952ad9b578d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=166088219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.166088219
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3468513159
Short name T215
Test name
Test status
Simulation time 70017039 ps
CPU time 1.73 seconds
Started Jul 31 07:13:38 PM PDT 24
Finished Jul 31 07:13:40 PM PDT 24
Peak memory 206780 kb
Host smart-18f7c75c-c136-43f3-8e4a-0883fb294442
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3468513159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3468513159
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.4132582326
Short name T2942
Test name
Test status
Simulation time 790268607 ps
CPU time 4.69 seconds
Started Jul 31 07:13:37 PM PDT 24
Finished Jul 31 07:13:42 PM PDT 24
Peak memory 206720 kb
Host smart-baabcc4c-fc98-4c84-9409-ae0fdeed6f77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4132582326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.4132582326
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3308491677
Short name T2957
Test name
Test status
Simulation time 35946239 ps
CPU time 0.72 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 206492 kb
Host smart-c1317ea5-1fc3-43cc-ba87-00890174522f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3308491677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3308491677
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1922652829
Short name T2901
Test name
Test status
Simulation time 44155620 ps
CPU time 0.71 seconds
Started Jul 31 07:16:40 PM PDT 24
Finished Jul 31 07:16:41 PM PDT 24
Peak memory 206504 kb
Host smart-5f19babf-badf-42b6-a3c8-745fba944bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1922652829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1922652829
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2561696373
Short name T2972
Test name
Test status
Simulation time 57840165 ps
CPU time 0.75 seconds
Started Jul 31 07:16:44 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 206532 kb
Host smart-ebb471b7-4184-4cef-969e-4cc74cecc25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2561696373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2561696373
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2388986854
Short name T2881
Test name
Test status
Simulation time 30611041 ps
CPU time 0.74 seconds
Started Jul 31 07:16:51 PM PDT 24
Finished Jul 31 07:16:52 PM PDT 24
Peak memory 206524 kb
Host smart-31037d3a-4a34-475e-86ab-e44c3fa0a4c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2388986854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2388986854
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3919450379
Short name T301
Test name
Test status
Simulation time 33385193 ps
CPU time 0.69 seconds
Started Jul 31 07:16:42 PM PDT 24
Finished Jul 31 07:16:43 PM PDT 24
Peak memory 206544 kb
Host smart-190f3e13-7e5f-41b9-bbf7-402221900a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3919450379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3919450379
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.484344807
Short name T2967
Test name
Test status
Simulation time 39382039 ps
CPU time 0.72 seconds
Started Jul 31 07:16:44 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 206484 kb
Host smart-444593c0-dea7-4315-9bfc-c736a6574ddf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=484344807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.484344807
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1389240016
Short name T2974
Test name
Test status
Simulation time 73049744 ps
CPU time 0.76 seconds
Started Jul 31 07:16:44 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 206480 kb
Host smart-9ef6c635-c883-405c-b02f-5ca8d0347ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1389240016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1389240016
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.970261173
Short name T2916
Test name
Test status
Simulation time 47618420 ps
CPU time 0.72 seconds
Started Jul 31 07:16:51 PM PDT 24
Finished Jul 31 07:16:52 PM PDT 24
Peak memory 206568 kb
Host smart-d1b65e0d-df0f-4ed2-bf88-f883a80626b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=970261173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.970261173
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2357337109
Short name T2963
Test name
Test status
Simulation time 43260088 ps
CPU time 0.69 seconds
Started Jul 31 07:16:42 PM PDT 24
Finished Jul 31 07:16:43 PM PDT 24
Peak memory 206544 kb
Host smart-c02dc5a3-4858-4af4-8b93-592620e33220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357337109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2357337109
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2762710870
Short name T208
Test name
Test status
Simulation time 168432083 ps
CPU time 2.12 seconds
Started Jul 31 07:13:54 PM PDT 24
Finished Jul 31 07:13:56 PM PDT 24
Peak memory 206636 kb
Host smart-f582744e-405c-4760-a1c3-a36a02468424
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2762710870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2762710870
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.810135382
Short name T2918
Test name
Test status
Simulation time 1853010859 ps
CPU time 8.24 seconds
Started Jul 31 07:13:53 PM PDT 24
Finished Jul 31 07:14:01 PM PDT 24
Peak memory 206644 kb
Host smart-dfae58dd-d032-4038-a2fa-25a1f6afbc84
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=810135382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.810135382
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.218272303
Short name T2971
Test name
Test status
Simulation time 95898827 ps
CPU time 0.93 seconds
Started Jul 31 07:13:54 PM PDT 24
Finished Jul 31 07:13:55 PM PDT 24
Peak memory 206492 kb
Host smart-fc965c11-e8e8-4666-a4f3-f9549c5dd104
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=218272303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.218272303
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.4130519976
Short name T2913
Test name
Test status
Simulation time 68911184 ps
CPU time 1.49 seconds
Started Jul 31 07:13:53 PM PDT 24
Finished Jul 31 07:13:55 PM PDT 24
Peak memory 214972 kb
Host smart-291f9ce4-3905-4c83-897e-85b562d0fa1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130519976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.4130519976
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1222752929
Short name T2908
Test name
Test status
Simulation time 51593238 ps
CPU time 0.84 seconds
Started Jul 31 07:13:54 PM PDT 24
Finished Jul 31 07:13:55 PM PDT 24
Peak memory 206572 kb
Host smart-09dcbf96-91fb-4e72-8144-8de0144db9a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1222752929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1222752929
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1706500113
Short name T2904
Test name
Test status
Simulation time 45534917 ps
CPU time 0.74 seconds
Started Jul 31 07:13:46 PM PDT 24
Finished Jul 31 07:13:47 PM PDT 24
Peak memory 206520 kb
Host smart-be5e4c39-3a72-4a44-ac23-905bbf3192b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1706500113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1706500113
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3252708183
Short name T2920
Test name
Test status
Simulation time 101338307 ps
CPU time 1.44 seconds
Started Jul 31 07:13:54 PM PDT 24
Finished Jul 31 07:13:56 PM PDT 24
Peak memory 214664 kb
Host smart-d62f821d-ce1f-463d-b356-1786d3d231a1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3252708183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3252708183
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.147403431
Short name T2870
Test name
Test status
Simulation time 482508183 ps
CPU time 4.52 seconds
Started Jul 31 07:13:53 PM PDT 24
Finished Jul 31 07:13:57 PM PDT 24
Peak memory 206680 kb
Host smart-e4b4f4cf-f6ec-472f-b427-c8cfb4d5abbf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=147403431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.147403431
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.1908602276
Short name T268
Test name
Test status
Simulation time 91503925 ps
CPU time 0.99 seconds
Started Jul 31 07:13:58 PM PDT 24
Finished Jul 31 07:13:59 PM PDT 24
Peak memory 206556 kb
Host smart-96d3ef44-d0ba-4d59-a348-fd9f5e155724
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1908602276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.1908602276
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2975549705
Short name T225
Test name
Test status
Simulation time 186241438 ps
CPU time 2.24 seconds
Started Jul 31 07:13:48 PM PDT 24
Finished Jul 31 07:13:50 PM PDT 24
Peak memory 214980 kb
Host smart-98aadd3c-6312-4b7f-a1b3-caa6a9c6dcec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2975549705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2975549705
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.2416608808
Short name T310
Test name
Test status
Simulation time 641767738 ps
CPU time 4.26 seconds
Started Jul 31 07:13:46 PM PDT 24
Finished Jul 31 07:13:51 PM PDT 24
Peak memory 206752 kb
Host smart-d6ac160d-72a7-4131-bd2a-94801a4481cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2416608808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.2416608808
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.3412432286
Short name T2890
Test name
Test status
Simulation time 97260382 ps
CPU time 0.8 seconds
Started Jul 31 07:16:46 PM PDT 24
Finished Jul 31 07:16:47 PM PDT 24
Peak memory 206548 kb
Host smart-1d8d86d6-9497-4c4e-96db-96f81feba65b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3412432286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3412432286
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.342513211
Short name T2930
Test name
Test status
Simulation time 67457129 ps
CPU time 0.76 seconds
Started Jul 31 07:16:44 PM PDT 24
Finished Jul 31 07:16:45 PM PDT 24
Peak memory 206504 kb
Host smart-60208e75-0ee5-4835-9fe0-a80e79668403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=342513211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.342513211
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3598894254
Short name T2939
Test name
Test status
Simulation time 65377315 ps
CPU time 0.78 seconds
Started Jul 31 07:16:45 PM PDT 24
Finished Jul 31 07:16:46 PM PDT 24
Peak memory 206392 kb
Host smart-fd7683e0-c4c5-408d-bf13-2624d419d072
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3598894254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3598894254
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3419078136
Short name T2962
Test name
Test status
Simulation time 30776416 ps
CPU time 0.68 seconds
Started Jul 31 07:16:49 PM PDT 24
Finished Jul 31 07:16:50 PM PDT 24
Peak memory 206548 kb
Host smart-6162ab20-a1f2-47da-a374-64553fd34714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3419078136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3419078136
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2197605968
Short name T2887
Test name
Test status
Simulation time 105047098 ps
CPU time 0.79 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:45 PM PDT 24
Peak memory 206484 kb
Host smart-d30e7fc3-fae3-48c8-b1ae-9149691c4d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2197605968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2197605968
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2371850157
Short name T2965
Test name
Test status
Simulation time 69122916 ps
CPU time 0.74 seconds
Started Jul 31 07:16:43 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 206532 kb
Host smart-9742393d-1bc0-470f-9797-d6e3c7f4623c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2371850157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2371850157
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.227581346
Short name T2891
Test name
Test status
Simulation time 67204406 ps
CPU time 0.76 seconds
Started Jul 31 07:16:42 PM PDT 24
Finished Jul 31 07:16:43 PM PDT 24
Peak memory 206504 kb
Host smart-ebf42344-3801-4832-a747-ec13a3fa99f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=227581346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.227581346
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.373174393
Short name T2970
Test name
Test status
Simulation time 45913340 ps
CPU time 0.69 seconds
Started Jul 31 07:16:47 PM PDT 24
Finished Jul 31 07:16:47 PM PDT 24
Peak memory 206544 kb
Host smart-9ad0fd09-3b98-45b6-9c80-d6b1bbc829d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=373174393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.373174393
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3104420280
Short name T2903
Test name
Test status
Simulation time 45375540 ps
CPU time 0.71 seconds
Started Jul 31 07:16:42 PM PDT 24
Finished Jul 31 07:16:44 PM PDT 24
Peak memory 206480 kb
Host smart-aca7d3d3-8229-457c-913d-d09d92727bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104420280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3104420280
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.494851470
Short name T2929
Test name
Test status
Simulation time 83256846 ps
CPU time 1.36 seconds
Started Jul 31 07:14:04 PM PDT 24
Finished Jul 31 07:14:06 PM PDT 24
Peak memory 214912 kb
Host smart-f70479dd-af88-45e3-af94-b554003dc584
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494851470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.494851470
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1178771694
Short name T2953
Test name
Test status
Simulation time 53869988 ps
CPU time 0.84 seconds
Started Jul 31 07:14:00 PM PDT 24
Finished Jul 31 07:14:01 PM PDT 24
Peak memory 206572 kb
Host smart-6032bee0-4397-434b-88ff-e9cff4fee219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1178771694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1178771694
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3596433378
Short name T196
Test name
Test status
Simulation time 46320816 ps
CPU time 0.68 seconds
Started Jul 31 07:13:59 PM PDT 24
Finished Jul 31 07:14:00 PM PDT 24
Peak memory 206500 kb
Host smart-db13502d-5950-401f-8cb9-582708f9ee13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3596433378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3596433378
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1602637690
Short name T190
Test name
Test status
Simulation time 301404273 ps
CPU time 1.63 seconds
Started Jul 31 07:14:00 PM PDT 24
Finished Jul 31 07:14:02 PM PDT 24
Peak memory 206768 kb
Host smart-87f5027c-a7e9-4263-b889-e9dc9668d116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1602637690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1602637690
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3174882948
Short name T2898
Test name
Test status
Simulation time 68062737 ps
CPU time 1.89 seconds
Started Jul 31 07:13:53 PM PDT 24
Finished Jul 31 07:13:55 PM PDT 24
Peak memory 206776 kb
Host smart-fc42d98a-2fb4-40a4-a999-731f03682cc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3174882948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3174882948
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3032504516
Short name T309
Test name
Test status
Simulation time 1119372181 ps
CPU time 4.94 seconds
Started Jul 31 07:13:58 PM PDT 24
Finished Jul 31 07:14:04 PM PDT 24
Peak memory 206704 kb
Host smart-13b1324c-c9c2-44c9-8370-ed33cbe4af24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3032504516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3032504516
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2079041325
Short name T2871
Test name
Test status
Simulation time 108030949 ps
CPU time 1.31 seconds
Started Jul 31 07:14:04 PM PDT 24
Finished Jul 31 07:14:06 PM PDT 24
Peak memory 215076 kb
Host smart-5bae3649-86eb-4d38-acc2-f3475e5e415e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079041325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2079041325
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2900444566
Short name T2921
Test name
Test status
Simulation time 82380067 ps
CPU time 1.01 seconds
Started Jul 31 07:14:01 PM PDT 24
Finished Jul 31 07:14:02 PM PDT 24
Peak memory 206604 kb
Host smart-84c128b4-5e93-444d-8b98-3e8a3791ebef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2900444566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2900444566
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.913793768
Short name T2879
Test name
Test status
Simulation time 68307806 ps
CPU time 0.74 seconds
Started Jul 31 07:13:59 PM PDT 24
Finished Jul 31 07:14:00 PM PDT 24
Peak memory 206492 kb
Host smart-4769c1bb-2f08-435e-a379-cb327a03b085
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=913793768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.913793768
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.228419115
Short name T2873
Test name
Test status
Simulation time 105186902 ps
CPU time 1.11 seconds
Started Jul 31 07:13:59 PM PDT 24
Finished Jul 31 07:14:01 PM PDT 24
Peak memory 206704 kb
Host smart-affa38dd-ffc8-40a1-8899-be1670cc35fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=228419115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.228419115
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3545358855
Short name T2951
Test name
Test status
Simulation time 130762863 ps
CPU time 1.29 seconds
Started Jul 31 07:14:15 PM PDT 24
Finished Jul 31 07:14:16 PM PDT 24
Peak memory 214820 kb
Host smart-4b4bc807-f355-4ff9-a92b-e0234b7a87f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545358855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.3545358855
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3898897736
Short name T260
Test name
Test status
Simulation time 35348891 ps
CPU time 0.83 seconds
Started Jul 31 07:14:06 PM PDT 24
Finished Jul 31 07:14:07 PM PDT 24
Peak memory 206640 kb
Host smart-fbf322d1-d6b6-4249-b5cf-d9bb7a199c96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3898897736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3898897736
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.336464265
Short name T2964
Test name
Test status
Simulation time 33699403 ps
CPU time 0.75 seconds
Started Jul 31 07:14:04 PM PDT 24
Finished Jul 31 07:14:05 PM PDT 24
Peak memory 206560 kb
Host smart-3c0027c1-0cca-4476-811c-9a74b90fed94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=336464265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.336464265
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3522149604
Short name T2896
Test name
Test status
Simulation time 121935600 ps
CPU time 1.14 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:08 PM PDT 24
Peak memory 206688 kb
Host smart-c5b093f2-a5b5-44bf-967d-1237667ef2f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3522149604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3522149604
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1284279284
Short name T221
Test name
Test status
Simulation time 126519105 ps
CPU time 1.66 seconds
Started Jul 31 07:13:59 PM PDT 24
Finished Jul 31 07:14:00 PM PDT 24
Peak memory 206684 kb
Host smart-b584f306-468c-43f3-9c28-12f626b2a9e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284279284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1284279284
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1005833231
Short name T224
Test name
Test status
Simulation time 1979469005 ps
CPU time 5.97 seconds
Started Jul 31 07:14:04 PM PDT 24
Finished Jul 31 07:14:10 PM PDT 24
Peak memory 206772 kb
Host smart-55b88fce-c82b-49ec-97fd-aca121cc66c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1005833231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1005833231
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.305568337
Short name T2973
Test name
Test status
Simulation time 104769985 ps
CPU time 1.64 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:08 PM PDT 24
Peak memory 215004 kb
Host smart-8ac9dd05-e77a-4b8e-98c3-4992da852ef2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305568337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.305568337
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1669679683
Short name T2933
Test name
Test status
Simulation time 78811467 ps
CPU time 0.92 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:08 PM PDT 24
Peak memory 206576 kb
Host smart-fe7b3544-7cb1-46bf-9259-431b6b8d2855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1669679683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1669679683
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2240262709
Short name T2966
Test name
Test status
Simulation time 44925210 ps
CPU time 0.73 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:08 PM PDT 24
Peak memory 206548 kb
Host smart-3aac2638-edb5-41d3-b83d-2c33d1dcea37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2240262709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2240262709
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.284130504
Short name T2954
Test name
Test status
Simulation time 246335641 ps
CPU time 1.47 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:08 PM PDT 24
Peak memory 206640 kb
Host smart-6b2b5609-2d69-4fa5-9d7c-0c23f36ba649
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=284130504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.284130504
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.493085721
Short name T226
Test name
Test status
Simulation time 109859050 ps
CPU time 3.43 seconds
Started Jul 31 07:14:06 PM PDT 24
Finished Jul 31 07:14:10 PM PDT 24
Peak memory 214912 kb
Host smart-3a5bfbc7-8753-4bdb-a744-73f4efbf12c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=493085721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.493085721
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.745304162
Short name T276
Test name
Test status
Simulation time 544893085 ps
CPU time 2.9 seconds
Started Jul 31 07:14:08 PM PDT 24
Finished Jul 31 07:14:11 PM PDT 24
Peak memory 206652 kb
Host smart-7ffb3a19-42af-42a1-bd8b-e272c24e1ef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=745304162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.745304162
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1199053457
Short name T2944
Test name
Test status
Simulation time 94823847 ps
CPU time 1.29 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:09 PM PDT 24
Peak memory 214796 kb
Host smart-707f49dc-774f-48a6-8200-0a777a7ac212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199053457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1199053457
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2395013993
Short name T2895
Test name
Test status
Simulation time 71923798 ps
CPU time 0.84 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:08 PM PDT 24
Peak memory 206672 kb
Host smart-d2a8409e-bb6b-414f-b113-ddfca13a14d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2395013993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2395013993
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.84034935
Short name T2883
Test name
Test status
Simulation time 44793044 ps
CPU time 0.74 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:08 PM PDT 24
Peak memory 206512 kb
Host smart-76950712-d1d5-4de3-a831-1e8527bf449e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=84034935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.84034935
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3729432651
Short name T267
Test name
Test status
Simulation time 148603816 ps
CPU time 1.65 seconds
Started Jul 31 07:14:06 PM PDT 24
Finished Jul 31 07:14:08 PM PDT 24
Peak memory 206672 kb
Host smart-ff81be23-c8b7-4422-9820-b099e286b367
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3729432651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3729432651
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.424329495
Short name T207
Test name
Test status
Simulation time 88276021 ps
CPU time 1.78 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:09 PM PDT 24
Peak memory 222388 kb
Host smart-a1cb3660-2498-4cc8-b91d-dc4e4f4667dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=424329495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.424329495
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.827137981
Short name T186
Test name
Test status
Simulation time 526957215 ps
CPU time 4.22 seconds
Started Jul 31 07:14:07 PM PDT 24
Finished Jul 31 07:14:11 PM PDT 24
Peak memory 206756 kb
Host smart-3344b390-2779-4caf-b9d8-d52f0a1e335d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=827137981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.827137981
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.4294555235
Short name T1721
Test name
Test status
Simulation time 60020773 ps
CPU time 0.68 seconds
Started Jul 31 05:39:19 PM PDT 24
Finished Jul 31 05:39:20 PM PDT 24
Peak memory 207004 kb
Host smart-f44a4593-f119-487e-9880-5d2c50639983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4294555235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.4294555235
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3095482886
Short name T1667
Test name
Test status
Simulation time 3513721951 ps
CPU time 5.14 seconds
Started Jul 31 05:39:04 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 207116 kb
Host smart-7a073b84-f1c0-4191-a2c6-7b47a60f0d96
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095482886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.3095482886
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.1490020123
Short name T873
Test name
Test status
Simulation time 13370642312 ps
CPU time 14.94 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:21 PM PDT 24
Peak memory 207224 kb
Host smart-d72cebd7-2576-45ce-9a1a-ed6a92bf0280
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490020123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.1490020123
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1533085592
Short name T622
Test name
Test status
Simulation time 23367756123 ps
CPU time 35.26 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:39:40 PM PDT 24
Peak memory 207160 kb
Host smart-618da013-2874-475e-907f-852b07bc903f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533085592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.1533085592
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1139649385
Short name T2171
Test name
Test status
Simulation time 185836715 ps
CPU time 0.93 seconds
Started Jul 31 05:39:01 PM PDT 24
Finished Jul 31 05:39:02 PM PDT 24
Peak memory 207020 kb
Host smart-c12545af-2033-4e42-969e-3229b23f108c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11396
49385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1139649385
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.3965252741
Short name T533
Test name
Test status
Simulation time 158102358 ps
CPU time 0.89 seconds
Started Jul 31 05:39:08 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 206984 kb
Host smart-a1f1720b-6e7a-4582-bed3-b6e2b3248cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39652
52741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.3965252741
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.1913766440
Short name T1676
Test name
Test status
Simulation time 426876047 ps
CPU time 1.51 seconds
Started Jul 31 05:39:10 PM PDT 24
Finished Jul 31 05:39:11 PM PDT 24
Peak memory 206988 kb
Host smart-f151110d-88ef-4089-ace3-1a8ced39926b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19137
66440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1913766440
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2834880297
Short name T1797
Test name
Test status
Simulation time 976552303 ps
CPU time 2.95 seconds
Started Jul 31 05:39:09 PM PDT 24
Finished Jul 31 05:39:12 PM PDT 24
Peak memory 207096 kb
Host smart-2861fe26-a4aa-4da4-ad20-79ae7f97c374
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2834880297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2834880297
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.1691757371
Short name T1221
Test name
Test status
Simulation time 9957015578 ps
CPU time 23.45 seconds
Started Jul 31 05:39:07 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 207236 kb
Host smart-1e69f175-2ed4-47c7-b2ba-aa9cdf83181b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16917
57371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.1691757371
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_device_timeout.1762314643
Short name T1257
Test name
Test status
Simulation time 3630856833 ps
CPU time 22.79 seconds
Started Jul 31 05:39:10 PM PDT 24
Finished Jul 31 05:39:33 PM PDT 24
Peak memory 207244 kb
Host smart-f5852136-cbbc-475c-a016-72b9caa1952d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762314643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.1762314643
Directory /workspace/0.usbdev_device_timeout/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.380284442
Short name T2435
Test name
Test status
Simulation time 413466638 ps
CPU time 1.35 seconds
Started Jul 31 05:39:10 PM PDT 24
Finished Jul 31 05:39:12 PM PDT 24
Peak memory 206952 kb
Host smart-e4e25f05-9db8-4398-8b35-dcf456418b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38028
4442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.380284442
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.3727367394
Short name T1577
Test name
Test status
Simulation time 182376737 ps
CPU time 0.9 seconds
Started Jul 31 05:39:11 PM PDT 24
Finished Jul 31 05:39:12 PM PDT 24
Peak memory 206964 kb
Host smart-56c4affe-382f-40de-a8b8-f380600738de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37273
67394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.3727367394
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_enable.2923581486
Short name T1505
Test name
Test status
Simulation time 45524975 ps
CPU time 0.72 seconds
Started Jul 31 05:39:10 PM PDT 24
Finished Jul 31 05:39:11 PM PDT 24
Peak memory 206940 kb
Host smart-4a4e51f6-f7f4-4bb7-a889-5f0e03bec606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29235
81486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2923581486
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1369405443
Short name T2630
Test name
Test status
Simulation time 960990261 ps
CPU time 2.8 seconds
Started Jul 31 05:39:09 PM PDT 24
Finished Jul 31 05:39:12 PM PDT 24
Peak memory 207120 kb
Host smart-103daada-27fa-4b44-83f8-beb8f5572035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13694
05443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1369405443
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3177298552
Short name T2675
Test name
Test status
Simulation time 307282165 ps
CPU time 2.26 seconds
Started Jul 31 05:39:09 PM PDT 24
Finished Jul 31 05:39:12 PM PDT 24
Peak memory 207040 kb
Host smart-ac41b2b0-d6b8-4777-a8e8-b0a9e3ff2798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31772
98552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3177298552
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3805308055
Short name T2691
Test name
Test status
Simulation time 95181622036 ps
CPU time 145.79 seconds
Started Jul 31 05:39:09 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 207236 kb
Host smart-46a9552c-7268-4c04-b1b9-16b30e0fa880
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3805308055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3805308055
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.4041280772
Short name T951
Test name
Test status
Simulation time 95295936345 ps
CPU time 148.41 seconds
Started Jul 31 05:39:10 PM PDT 24
Finished Jul 31 05:41:39 PM PDT 24
Peak memory 207180 kb
Host smart-d614c1bc-1dd7-40b7-94ff-b5ba9965683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041280772 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.4041280772
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.309947121
Short name T1210
Test name
Test status
Simulation time 95193880359 ps
CPU time 165.67 seconds
Started Jul 31 05:39:11 PM PDT 24
Finished Jul 31 05:41:57 PM PDT 24
Peak memory 207204 kb
Host smart-e231cfca-bacb-4029-b1d5-e67d37b5cc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30994
7121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.309947121
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2626118413
Short name T1373
Test name
Test status
Simulation time 178639478 ps
CPU time 1.01 seconds
Started Jul 31 05:39:08 PM PDT 24
Finished Jul 31 05:39:09 PM PDT 24
Peak memory 207056 kb
Host smart-734af45f-9f12-4500-a780-1a0e645a88bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2626118413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2626118413
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3194976280
Short name T2254
Test name
Test status
Simulation time 148603647 ps
CPU time 0.83 seconds
Started Jul 31 05:39:28 PM PDT 24
Finished Jul 31 05:39:29 PM PDT 24
Peak memory 206928 kb
Host smart-4adf962d-1cf4-4f26-bf30-9bf22c23c320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31949
76280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3194976280
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2561563355
Short name T513
Test name
Test status
Simulation time 200707906 ps
CPU time 0.99 seconds
Started Jul 31 05:39:14 PM PDT 24
Finished Jul 31 05:39:15 PM PDT 24
Peak memory 206996 kb
Host smart-3dde1ed3-15c2-439f-b6d7-3a7f6da581b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25615
63355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2561563355
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.1298216823
Short name T996
Test name
Test status
Simulation time 7234808904 ps
CPU time 76.08 seconds
Started Jul 31 05:39:05 PM PDT 24
Finished Jul 31 05:40:21 PM PDT 24
Peak memory 215452 kb
Host smart-44038449-87f5-4a23-bfd7-0b1d2207c8d7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1298216823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.1298216823
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.2739684118
Short name T1610
Test name
Test status
Simulation time 11871954159 ps
CPU time 138.19 seconds
Started Jul 31 05:39:16 PM PDT 24
Finished Jul 31 05:41:34 PM PDT 24
Peak memory 207100 kb
Host smart-6738e8e9-5b43-4603-b577-62eed5cb6547
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2739684118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.2739684118
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3360032344
Short name T1279
Test name
Test status
Simulation time 189169336 ps
CPU time 0.93 seconds
Started Jul 31 05:39:13 PM PDT 24
Finished Jul 31 05:39:14 PM PDT 24
Peak memory 206980 kb
Host smart-ddecd5d9-a42e-41dd-b4fe-6dd2b9b4aee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33600
32344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3360032344
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.3605790300
Short name T62
Test name
Test status
Simulation time 476659661 ps
CPU time 1.47 seconds
Started Jul 31 05:39:17 PM PDT 24
Finished Jul 31 05:39:19 PM PDT 24
Peak memory 206992 kb
Host smart-c1e93486-0c34-4fbe-b3f1-c3f029cc9b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36057
90300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.3605790300
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2701973854
Short name T353
Test name
Test status
Simulation time 23351587638 ps
CPU time 26.1 seconds
Started Jul 31 05:39:17 PM PDT 24
Finished Jul 31 05:39:43 PM PDT 24
Peak memory 207176 kb
Host smart-cdf2153b-4dfe-4078-b16f-85b3ba1bb146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27019
73854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2701973854
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3468761114
Short name T2374
Test name
Test status
Simulation time 3322845564 ps
CPU time 5.19 seconds
Started Jul 31 05:39:28 PM PDT 24
Finished Jul 31 05:39:33 PM PDT 24
Peak memory 207104 kb
Host smart-e34548e1-e1f3-48ee-b58a-58f2fa1cf010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34687
61114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3468761114
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.1872348219
Short name T141
Test name
Test status
Simulation time 4769658211 ps
CPU time 32.3 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:40:02 PM PDT 24
Peak memory 217452 kb
Host smart-c985b120-d912-49ab-ad15-e91a615c81ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18723
48219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.1872348219
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.2491605004
Short name T434
Test name
Test status
Simulation time 4112585073 ps
CPU time 38.23 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:40:06 PM PDT 24
Peak memory 216752 kb
Host smart-3f30eac7-2782-4ae5-8679-ec1ae1caaa3f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2491605004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.2491605004
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2662029940
Short name T840
Test name
Test status
Simulation time 238628093 ps
CPU time 0.99 seconds
Started Jul 31 05:39:13 PM PDT 24
Finished Jul 31 05:39:14 PM PDT 24
Peak memory 206984 kb
Host smart-6dc4288b-14dd-49e8-b3dd-3cacd3bef326
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2662029940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2662029940
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.873684681
Short name T481
Test name
Test status
Simulation time 237854598 ps
CPU time 1.01 seconds
Started Jul 31 05:39:28 PM PDT 24
Finished Jul 31 05:39:30 PM PDT 24
Peak memory 206952 kb
Host smart-b9c47bdf-1666-46e1-b49f-15bbf9082893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87368
4681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.873684681
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.905404832
Short name T871
Test name
Test status
Simulation time 6306526100 ps
CPU time 61.42 seconds
Started Jul 31 05:39:16 PM PDT 24
Finished Jul 31 05:40:18 PM PDT 24
Peak memory 217048 kb
Host smart-1dee2786-a511-4f7b-8e90-d232123c25b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90540
4832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.905404832
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1655893115
Short name T355
Test name
Test status
Simulation time 5012519308 ps
CPU time 155.21 seconds
Started Jul 31 05:39:13 PM PDT 24
Finished Jul 31 05:41:48 PM PDT 24
Peak memory 215392 kb
Host smart-a5f78b1a-1575-4292-ab5a-e4b869747715
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1655893115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1655893115
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1202447288
Short name T1642
Test name
Test status
Simulation time 156608310 ps
CPU time 0.88 seconds
Started Jul 31 05:39:13 PM PDT 24
Finished Jul 31 05:39:14 PM PDT 24
Peak memory 206980 kb
Host smart-8ce9e75e-3903-4711-82b8-4b932715a49a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1202447288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1202447288
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3504570260
Short name T1319
Test name
Test status
Simulation time 188324665 ps
CPU time 0.88 seconds
Started Jul 31 05:39:13 PM PDT 24
Finished Jul 31 05:39:14 PM PDT 24
Peak memory 206984 kb
Host smart-73315406-af4e-4b4b-9652-04343852661a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35045
70260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3504570260
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2707301375
Short name T63
Test name
Test status
Simulation time 497204042 ps
CPU time 1.7 seconds
Started Jul 31 05:39:16 PM PDT 24
Finished Jul 31 05:39:18 PM PDT 24
Peak memory 206984 kb
Host smart-678f30ce-14f0-4c94-ba63-9665dbc20c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27073
01375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2707301375
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2517113977
Short name T1838
Test name
Test status
Simulation time 162478409 ps
CPU time 0.93 seconds
Started Jul 31 05:39:14 PM PDT 24
Finished Jul 31 05:39:15 PM PDT 24
Peak memory 206992 kb
Host smart-c9436461-63c8-4045-b406-580fd9711ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25171
13977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2517113977
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1363327168
Short name T1843
Test name
Test status
Simulation time 197926912 ps
CPU time 0.95 seconds
Started Jul 31 05:39:14 PM PDT 24
Finished Jul 31 05:39:15 PM PDT 24
Peak memory 206996 kb
Host smart-e460da29-cab1-483c-8147-9a8b20a3e652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13633
27168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1363327168
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1681549945
Short name T1891
Test name
Test status
Simulation time 161918204 ps
CPU time 0.96 seconds
Started Jul 31 05:39:14 PM PDT 24
Finished Jul 31 05:39:15 PM PDT 24
Peak memory 206992 kb
Host smart-351081a5-b37b-4fe0-bc86-47990ba8d5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16815
49945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1681549945
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2780853725
Short name T494
Test name
Test status
Simulation time 158963741 ps
CPU time 0.87 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:39:28 PM PDT 24
Peak memory 206960 kb
Host smart-65fca5e6-e13c-41a6-9aa9-443ef950d5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27808
53725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2780853725
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2475493173
Short name T1115
Test name
Test status
Simulation time 183451913 ps
CPU time 0.91 seconds
Started Jul 31 05:39:12 PM PDT 24
Finished Jul 31 05:39:13 PM PDT 24
Peak memory 207000 kb
Host smart-41c3ced0-ce81-4c52-9ea6-355cda2f1ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
93173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2475493173
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.1840080871
Short name T1830
Test name
Test status
Simulation time 241019919 ps
CPU time 1.05 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:39:28 PM PDT 24
Peak memory 206976 kb
Host smart-044f65a4-2da3-4e02-9eab-b3c1475b3de5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1840080871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1840080871
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3458383323
Short name T2824
Test name
Test status
Simulation time 224499965 ps
CPU time 0.98 seconds
Started Jul 31 05:39:34 PM PDT 24
Finished Jul 31 05:39:36 PM PDT 24
Peak memory 206960 kb
Host smart-22697e9d-4a64-413c-9f56-0dbf44bb7dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34583
83323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3458383323
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.3583952926
Short name T842
Test name
Test status
Simulation time 256456008 ps
CPU time 1.12 seconds
Started Jul 31 05:39:28 PM PDT 24
Finished Jul 31 05:39:29 PM PDT 24
Peak memory 206964 kb
Host smart-de3b50f9-b851-434e-b8f5-da70584ae82c
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3583952926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.3583952926
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.796482341
Short name T191
Test name
Test status
Simulation time 274976955 ps
CPU time 1.04 seconds
Started Jul 31 05:39:34 PM PDT 24
Finished Jul 31 05:39:36 PM PDT 24
Peak memory 206984 kb
Host smart-b14c6ea7-aae6-4c47-9435-8b75f0efa24c
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=796482341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.796482341
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.621322453
Short name T1634
Test name
Test status
Simulation time 146256291 ps
CPU time 0.82 seconds
Started Jul 31 05:39:17 PM PDT 24
Finished Jul 31 05:39:18 PM PDT 24
Peak memory 206960 kb
Host smart-890af0cd-c044-4621-86e8-c59fe756e577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62132
2453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.621322453
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1185092129
Short name T580
Test name
Test status
Simulation time 36041712 ps
CPU time 0.69 seconds
Started Jul 31 05:39:24 PM PDT 24
Finished Jul 31 05:39:25 PM PDT 24
Peak memory 206944 kb
Host smart-dffdbc84-ed1b-493b-9a57-59bb4a36eb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11850
92129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1185092129
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2080810445
Short name T2132
Test name
Test status
Simulation time 21730298374 ps
CPU time 53.1 seconds
Started Jul 31 05:39:21 PM PDT 24
Finished Jul 31 05:40:14 PM PDT 24
Peak memory 223620 kb
Host smart-f1b50fa7-339a-40ed-bbf8-c167982630a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20808
10445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2080810445
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2662820379
Short name T1411
Test name
Test status
Simulation time 183020114 ps
CPU time 0.9 seconds
Started Jul 31 05:39:19 PM PDT 24
Finished Jul 31 05:39:20 PM PDT 24
Peak memory 206976 kb
Host smart-bb0b9f6d-133a-4c25-adf1-e7397946dbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26628
20379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2662820379
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.367183037
Short name T2062
Test name
Test status
Simulation time 211393851 ps
CPU time 0.99 seconds
Started Jul 31 05:39:20 PM PDT 24
Finished Jul 31 05:39:21 PM PDT 24
Peak memory 206968 kb
Host smart-4896148c-5485-4c32-9e1d-7232288e3b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36718
3037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.367183037
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.3212589412
Short name T1945
Test name
Test status
Simulation time 8528335098 ps
CPU time 58.62 seconds
Started Jul 31 05:39:19 PM PDT 24
Finished Jul 31 05:40:18 PM PDT 24
Peak memory 223604 kb
Host smart-d08e7eab-0947-4d54-9dd0-074f0cad839b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3212589412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.3212589412
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3884490820
Short name T2521
Test name
Test status
Simulation time 11491676406 ps
CPU time 236.06 seconds
Started Jul 31 05:39:20 PM PDT 24
Finished Jul 31 05:43:17 PM PDT 24
Peak memory 215444 kb
Host smart-7f8d8ee9-dab8-4b70-adff-1d1bbc0733ce
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884490820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3884490820
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1201619104
Short name T1131
Test name
Test status
Simulation time 161942292 ps
CPU time 0.9 seconds
Started Jul 31 05:39:18 PM PDT 24
Finished Jul 31 05:39:19 PM PDT 24
Peak memory 206984 kb
Host smart-4f0f289b-46c9-4211-86a3-7c3fc0064fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016
19104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1201619104
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.324468851
Short name T335
Test name
Test status
Simulation time 179560822 ps
CPU time 0.94 seconds
Started Jul 31 05:39:19 PM PDT 24
Finished Jul 31 05:39:20 PM PDT 24
Peak memory 206996 kb
Host smart-ed5bd158-70af-4ed1-ba83-3afd38e8423f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32446
8851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.324468851
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.3004728456
Short name T1728
Test name
Test status
Simulation time 200141527 ps
CPU time 0.89 seconds
Started Jul 31 05:39:21 PM PDT 24
Finished Jul 31 05:39:22 PM PDT 24
Peak memory 206964 kb
Host smart-63ea5be9-0027-4a6c-b158-c9fad3f23bef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30047
28456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.3004728456
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.1390409238
Short name T185
Test name
Test status
Simulation time 545153664 ps
CPU time 1.31 seconds
Started Jul 31 05:39:20 PM PDT 24
Finished Jul 31 05:39:21 PM PDT 24
Peak memory 223040 kb
Host smart-69c4a60e-c452-4be4-a8b4-0b3a0233ef80
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1390409238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1390409238
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.24309812
Short name T1513
Test name
Test status
Simulation time 204230892 ps
CPU time 0.96 seconds
Started Jul 31 05:39:20 PM PDT 24
Finished Jul 31 05:39:21 PM PDT 24
Peak memory 206992 kb
Host smart-68fbeb18-af2a-4916-90e9-71fa08fbdd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24309
812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.24309812
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2090362028
Short name T2595
Test name
Test status
Simulation time 142096992 ps
CPU time 0.86 seconds
Started Jul 31 05:39:18 PM PDT 24
Finished Jul 31 05:39:19 PM PDT 24
Peak memory 206960 kb
Host smart-1968515d-af04-4885-a1f7-f3271a877032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20903
62028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2090362028
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3849221396
Short name T2367
Test name
Test status
Simulation time 241228100 ps
CPU time 0.98 seconds
Started Jul 31 05:39:22 PM PDT 24
Finished Jul 31 05:39:23 PM PDT 24
Peak memory 207024 kb
Host smart-9e59ab10-2c95-43cf-aa8c-68276131dcd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38492
21396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3849221396
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2314888380
Short name T1799
Test name
Test status
Simulation time 229990077 ps
CPU time 1.09 seconds
Started Jul 31 05:39:21 PM PDT 24
Finished Jul 31 05:39:22 PM PDT 24
Peak memory 206976 kb
Host smart-2a1ea25e-4cb9-441f-a915-27d9586f6b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23148
88380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2314888380
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.2636688628
Short name T2296
Test name
Test status
Simulation time 4648547186 ps
CPU time 34.62 seconds
Started Jul 31 05:39:22 PM PDT 24
Finished Jul 31 05:39:56 PM PDT 24
Peak memory 215052 kb
Host smart-19a7ef5a-8bb5-4487-b94c-0a5e6ae98332
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2636688628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.2636688628
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2573107300
Short name T1806
Test name
Test status
Simulation time 168071532 ps
CPU time 0.86 seconds
Started Jul 31 05:39:17 PM PDT 24
Finished Jul 31 05:39:18 PM PDT 24
Peak memory 207036 kb
Host smart-8d86c3ef-acb0-4e30-8229-461435aad866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25731
07300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2573107300
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.503083760
Short name T431
Test name
Test status
Simulation time 1020340718 ps
CPU time 2.5 seconds
Started Jul 31 05:39:19 PM PDT 24
Finished Jul 31 05:39:22 PM PDT 24
Peak memory 207076 kb
Host smart-c8f0fe92-6f5c-4fcc-8e6a-794bea9b2e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50308
3760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.503083760
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3113215155
Short name T2616
Test name
Test status
Simulation time 5333696309 ps
CPU time 41.22 seconds
Started Jul 31 05:39:24 PM PDT 24
Finished Jul 31 05:40:06 PM PDT 24
Peak memory 207260 kb
Host smart-892b1b40-d258-4d51-920a-4cc650497ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31132
15155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3113215155
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3252227732
Short name T166
Test name
Test status
Simulation time 13617822671 ps
CPU time 300.66 seconds
Started Jul 31 05:39:24 PM PDT 24
Finished Jul 31 05:44:25 PM PDT 24
Peak memory 215380 kb
Host smart-3fb650f9-d7ce-40f1-8b17-3316a4804e40
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252227732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3252227732
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.2893809392
Short name T2262
Test name
Test status
Simulation time 1530768929 ps
CPU time 13.49 seconds
Started Jul 31 05:39:09 PM PDT 24
Finished Jul 31 05:39:22 PM PDT 24
Peak memory 207068 kb
Host smart-105a8365-0101-4903-aa5f-5ef9d7179213
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893809392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.2893809392
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.3962760832
Short name T441
Test name
Test status
Simulation time 67065797 ps
CPU time 0.72 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:37 PM PDT 24
Peak memory 207008 kb
Host smart-cdeca85e-a402-4cb0-801f-6eb7af1711c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3962760832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.3962760832
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.505592091
Short name T1482
Test name
Test status
Simulation time 3582398656 ps
CPU time 5.71 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 207156 kb
Host smart-09232a5f-2b89-456e-a9e0-acd50b58d00f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505592091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon
_wake_disconnect.505592091
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.2064573389
Short name T961
Test name
Test status
Simulation time 13422754159 ps
CPU time 15.22 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 207236 kb
Host smart-004bf59d-15a3-458e-aad1-761866d5c84f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064573389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.2064573389
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.2492841889
Short name T2849
Test name
Test status
Simulation time 23435707085 ps
CPU time 29.01 seconds
Started Jul 31 05:39:23 PM PDT 24
Finished Jul 31 05:39:52 PM PDT 24
Peak memory 207164 kb
Host smart-fbd851ca-1d62-4e6f-8802-67ba1c73d62e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492841889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_resume.2492841889
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.123060859
Short name T1126
Test name
Test status
Simulation time 221167238 ps
CPU time 0.94 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:26 PM PDT 24
Peak memory 206996 kb
Host smart-cf9dd21b-8fb0-4b3a-ade5-60f89736812a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12306
0859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.123060859
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2972974045
Short name T239
Test name
Test status
Simulation time 153226355 ps
CPU time 0.88 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:30 PM PDT 24
Peak memory 206948 kb
Host smart-f9a883d4-14cd-4fea-950d-004b853e0fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29729
74045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2972974045
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2923229067
Short name T953
Test name
Test status
Simulation time 457163444 ps
CPU time 1.66 seconds
Started Jul 31 05:39:26 PM PDT 24
Finished Jul 31 05:39:28 PM PDT 24
Peak memory 206984 kb
Host smart-5839b2da-2f0d-4867-9e4a-ce508461dd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29232
29067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2923229067
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2180442489
Short name T1207
Test name
Test status
Simulation time 753026917 ps
CPU time 2.17 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:28 PM PDT 24
Peak memory 207004 kb
Host smart-30e6dda0-63c7-4e93-9dbf-31b2e2fbc4ac
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2180442489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2180442489
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2046880074
Short name T2434
Test name
Test status
Simulation time 11171272732 ps
CPU time 23.89 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:49 PM PDT 24
Peak memory 207200 kb
Host smart-31800658-7b89-4f14-8fd1-1ba3c3918f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20468
80074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2046880074
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_device_timeout.2072533805
Short name T613
Test name
Test status
Simulation time 145069881 ps
CPU time 0.89 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:27 PM PDT 24
Peak memory 206948 kb
Host smart-a74c9521-7e90-4999-98a9-a1aa3c09744e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072533805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.2072533805
Directory /workspace/1.usbdev_device_timeout/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.3630826889
Short name T2667
Test name
Test status
Simulation time 459099818 ps
CPU time 1.62 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 206992 kb
Host smart-19f919e9-53f3-451d-af89-0f2b9fdd5137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36308
26889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.3630826889
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_enable.2444824424
Short name T989
Test name
Test status
Simulation time 56897980 ps
CPU time 0.8 seconds
Started Jul 31 05:39:22 PM PDT 24
Finished Jul 31 05:39:23 PM PDT 24
Peak memory 206996 kb
Host smart-287c1f44-9efd-4af3-8d93-329259edb267
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24448
24424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2444824424
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1556182409
Short name T2274
Test name
Test status
Simulation time 891712689 ps
CPU time 2.51 seconds
Started Jul 31 05:39:23 PM PDT 24
Finished Jul 31 05:39:26 PM PDT 24
Peak memory 207092 kb
Host smart-a7f4ca12-9f93-4180-8641-3815ef637ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15561
82409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1556182409
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2088534553
Short name T946
Test name
Test status
Simulation time 399260032 ps
CPU time 2.86 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:39:30 PM PDT 24
Peak memory 207080 kb
Host smart-10bb5744-94a1-44a0-9250-3aa398e493bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20885
34553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2088534553
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.289501964
Short name T2857
Test name
Test status
Simulation time 112190653172 ps
CPU time 165.96 seconds
Started Jul 31 05:39:23 PM PDT 24
Finished Jul 31 05:42:09 PM PDT 24
Peak memory 207216 kb
Host smart-cd3b3de3-a60c-4e51-a863-a708259779df
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=289501964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.289501964
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.2924726390
Short name T1753
Test name
Test status
Simulation time 101069218764 ps
CPU time 146.83 seconds
Started Jul 31 05:39:26 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 207192 kb
Host smart-00914789-79c3-43da-ac0e-1277fa6a695b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924726390 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.2924726390
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2698462378
Short name T1246
Test name
Test status
Simulation time 85111298840 ps
CPU time 136.32 seconds
Started Jul 31 05:39:26 PM PDT 24
Finished Jul 31 05:41:42 PM PDT 24
Peak memory 207236 kb
Host smart-653e4ec5-a22a-4d41-b1c2-c0f397aae7d4
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2698462378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2698462378
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.2457949667
Short name T2723
Test name
Test status
Simulation time 88224526111 ps
CPU time 147.65 seconds
Started Jul 31 05:39:24 PM PDT 24
Finished Jul 31 05:41:51 PM PDT 24
Peak memory 207220 kb
Host smart-a85c637a-34d6-451e-bf27-4177e686b1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457949667 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.2457949667
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3326173207
Short name T2555
Test name
Test status
Simulation time 85130329923 ps
CPU time 139.4 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:41:46 PM PDT 24
Peak memory 207180 kb
Host smart-f7ad7d56-a7be-492c-98f4-8a67eaf03f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33261
73207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3326173207
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.3610753085
Short name T1330
Test name
Test status
Simulation time 192655076 ps
CPU time 1.04 seconds
Started Jul 31 05:39:24 PM PDT 24
Finished Jul 31 05:39:25 PM PDT 24
Peak memory 207100 kb
Host smart-3bb8c879-4f0f-49be-87b0-e593fcba8790
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3610753085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.3610753085
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.1674867351
Short name T2195
Test name
Test status
Simulation time 191078035 ps
CPU time 0.85 seconds
Started Jul 31 05:39:26 PM PDT 24
Finished Jul 31 05:39:27 PM PDT 24
Peak memory 206976 kb
Host smart-91f79ba7-072e-4b46-b4d3-c3e44f01bb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16748
67351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.1674867351
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2965270686
Short name T2780
Test name
Test status
Simulation time 240348614 ps
CPU time 0.99 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:26 PM PDT 24
Peak memory 206984 kb
Host smart-ed7ded4b-8ba3-4c40-bdad-6efd38b9d519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29652
70686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2965270686
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.3660770822
Short name T2652
Test name
Test status
Simulation time 8896951291 ps
CPU time 85.11 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:40:53 PM PDT 24
Peak memory 216968 kb
Host smart-8ef2b568-188a-4d58-b343-be4cec56b350
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3660770822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.3660770822
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.2888971506
Short name T1024
Test name
Test status
Simulation time 7942090886 ps
CPU time 53.92 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:40:19 PM PDT 24
Peak memory 207200 kb
Host smart-3de0d337-e00d-40c8-9536-0b5dbf0e0725
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2888971506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.2888971506
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.529489279
Short name T514
Test name
Test status
Simulation time 197065030 ps
CPU time 0.91 seconds
Started Jul 31 05:39:24 PM PDT 24
Finished Jul 31 05:39:25 PM PDT 24
Peak memory 206968 kb
Host smart-4b7a6409-d7e3-430e-84c0-6437d4782c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52948
9279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.529489279
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.541248938
Short name T1886
Test name
Test status
Simulation time 23314284090 ps
CPU time 29.4 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:55 PM PDT 24
Peak memory 207232 kb
Host smart-52a418ff-209e-4322-9746-699dc0914f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54124
8938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.541248938
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.1473622653
Short name T357
Test name
Test status
Simulation time 3342983881 ps
CPU time 5.43 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:35 PM PDT 24
Peak memory 207172 kb
Host smart-4be75b5f-176e-4d30-bbcc-89d407ce1941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14736
22653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1473622653
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.809968317
Short name T322
Test name
Test status
Simulation time 5691675978 ps
CPU time 172.05 seconds
Started Jul 31 05:39:26 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 215372 kb
Host smart-38e3a8c0-e50a-438d-854a-5e2e4c7bf05f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80996
8317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.809968317
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1366355324
Short name T1959
Test name
Test status
Simulation time 5330910233 ps
CPU time 44.34 seconds
Started Jul 31 05:39:26 PM PDT 24
Finished Jul 31 05:40:10 PM PDT 24
Peak memory 216632 kb
Host smart-e7b56e3c-0e70-4700-9713-a8ef8039a281
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1366355324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1366355324
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.1605774691
Short name T1544
Test name
Test status
Simulation time 233209747 ps
CPU time 1.02 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:26 PM PDT 24
Peak memory 206944 kb
Host smart-ed52ec80-af92-4dca-bd0d-7fce63e87cfd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1605774691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.1605774691
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1881064843
Short name T412
Test name
Test status
Simulation time 196049225 ps
CPU time 1 seconds
Started Jul 31 05:39:24 PM PDT 24
Finished Jul 31 05:39:25 PM PDT 24
Peak memory 206964 kb
Host smart-965dbcd3-453d-46f1-90b5-ba0fb9c4a484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18810
64843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1881064843
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.4182623693
Short name T751
Test name
Test status
Simulation time 4165269332 ps
CPU time 125.6 seconds
Started Jul 31 05:39:30 PM PDT 24
Finished Jul 31 05:41:36 PM PDT 24
Peak memory 215384 kb
Host smart-f0b76add-40a8-4ce6-b369-80832966f035
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4182623693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.4182623693
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1425050673
Short name T1708
Test name
Test status
Simulation time 163620239 ps
CPU time 0.89 seconds
Started Jul 31 05:39:25 PM PDT 24
Finished Jul 31 05:39:26 PM PDT 24
Peak memory 206980 kb
Host smart-e5c65522-fbd2-4260-8143-aa90b40f49c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1425050673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1425050673
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.3183557399
Short name T2734
Test name
Test status
Simulation time 188920508 ps
CPU time 0.92 seconds
Started Jul 31 05:39:24 PM PDT 24
Finished Jul 31 05:39:25 PM PDT 24
Peak memory 207000 kb
Host smart-59a4e2f2-f5db-4c84-b609-dd86bcaa3602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31835
57399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.3183557399
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.796620677
Short name T2538
Test name
Test status
Simulation time 215814437 ps
CPU time 1.07 seconds
Started Jul 31 05:39:37 PM PDT 24
Finished Jul 31 05:39:38 PM PDT 24
Peak memory 207024 kb
Host smart-697217f3-f502-40b8-aadc-41d6bae6871d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79662
0677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.796620677
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.829590511
Short name T2192
Test name
Test status
Simulation time 183014858 ps
CPU time 0.92 seconds
Started Jul 31 05:39:30 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 206996 kb
Host smart-228dd4b8-52f1-4906-b179-ebda7895aa24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82959
0511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.829590511
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2472913392
Short name T2061
Test name
Test status
Simulation time 153252164 ps
CPU time 0.86 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:30 PM PDT 24
Peak memory 206976 kb
Host smart-ffee5316-c7fc-4bfe-a3f0-e3cf8713974f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24729
13392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2472913392
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3837747112
Short name T1324
Test name
Test status
Simulation time 167630319 ps
CPU time 0.94 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:30 PM PDT 24
Peak memory 207048 kb
Host smart-c0bf7338-7be5-4918-b101-eae1ad005456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38377
47112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3837747112
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1490532639
Short name T372
Test name
Test status
Simulation time 190772314 ps
CPU time 0.93 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:30 PM PDT 24
Peak memory 206976 kb
Host smart-740ffd30-5bdc-47ee-b16d-ae104b55fd00
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1490532639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1490532639
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.479884371
Short name T2841
Test name
Test status
Simulation time 267505825 ps
CPU time 1.1 seconds
Started Jul 31 05:39:32 PM PDT 24
Finished Jul 31 05:39:33 PM PDT 24
Peak memory 206988 kb
Host smart-993a54d2-f9aa-49c1-8642-81397679f66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47988
4371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.479884371
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3226070591
Short name T2570
Test name
Test status
Simulation time 161975157 ps
CPU time 0.82 seconds
Started Jul 31 05:39:30 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 206960 kb
Host smart-e05e622a-5f33-4df4-bf58-7c7be8d570ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260
70591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3226070591
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.526879879
Short name T2475
Test name
Test status
Simulation time 50203177 ps
CPU time 0.72 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:30 PM PDT 24
Peak memory 206992 kb
Host smart-71ec7d2d-3d04-47cf-9c41-3a8b593259a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52687
9879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.526879879
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.2849093106
Short name T1377
Test name
Test status
Simulation time 6553566411 ps
CPU time 19.45 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:49 PM PDT 24
Peak memory 215452 kb
Host smart-2cceb4ce-1ba8-4d93-b373-325737c3f9ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28490
93106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.2849093106
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.746866087
Short name T2297
Test name
Test status
Simulation time 150451430 ps
CPU time 0.86 seconds
Started Jul 31 05:39:30 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 207016 kb
Host smart-06b4855e-1651-4907-8b01-3394b8e11682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74686
6087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.746866087
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.3855675047
Short name T1549
Test name
Test status
Simulation time 192738509 ps
CPU time 0.93 seconds
Started Jul 31 05:39:28 PM PDT 24
Finished Jul 31 05:39:29 PM PDT 24
Peak memory 207004 kb
Host smart-2ff0065e-ab59-421e-be3b-fcdcb0bada01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38556
75047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3855675047
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1313011535
Short name T2029
Test name
Test status
Simulation time 10879803523 ps
CPU time 60.78 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:40:30 PM PDT 24
Peak memory 216384 kb
Host smart-eb750a43-879b-42eb-b83c-2428dd14f349
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313011535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1313011535
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2374898079
Short name T1179
Test name
Test status
Simulation time 14132275380 ps
CPU time 83.49 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:40:51 PM PDT 24
Peak memory 223488 kb
Host smart-1b6f0205-3d93-4809-9647-c71607dc3235
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2374898079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2374898079
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.1467214659
Short name T2135
Test name
Test status
Simulation time 12618633731 ps
CPU time 70.41 seconds
Started Jul 31 05:39:31 PM PDT 24
Finished Jul 31 05:40:41 PM PDT 24
Peak memory 223400 kb
Host smart-13705c04-c688-4329-a34e-e898b4cfb52e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467214659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1467214659
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.2367621215
Short name T1099
Test name
Test status
Simulation time 202597847 ps
CPU time 0.92 seconds
Started Jul 31 05:39:32 PM PDT 24
Finished Jul 31 05:39:33 PM PDT 24
Peak memory 206980 kb
Host smart-8a16fa86-29ea-4563-9a06-f5201e0a151f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23676
21215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.2367621215
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.827472323
Short name T917
Test name
Test status
Simulation time 184819857 ps
CPU time 0.97 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 207000 kb
Host smart-4366f5c0-f089-4882-b50f-e8c6436360a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82747
2323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.827472323
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2754827659
Short name T72
Test name
Test status
Simulation time 159363083 ps
CPU time 0.89 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:37 PM PDT 24
Peak memory 207024 kb
Host smart-78499d0b-9c14-4e73-82e3-b048b0e9bdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27548
27659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2754827659
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1081896353
Short name T2739
Test name
Test status
Simulation time 407693610 ps
CPU time 1.55 seconds
Started Jul 31 05:39:37 PM PDT 24
Finished Jul 31 05:39:39 PM PDT 24
Peak memory 207020 kb
Host smart-7540a36a-4a07-4314-aebd-3c778bb0f8f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10818
96353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1081896353
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.2433019027
Short name T2257
Test name
Test status
Simulation time 299898277 ps
CPU time 1.12 seconds
Started Jul 31 05:39:34 PM PDT 24
Finished Jul 31 05:39:36 PM PDT 24
Peak memory 206964 kb
Host smart-ba1e048b-4a6e-4b58-8d2d-584bc787f8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24330
19027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2433019027
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1245384287
Short name T618
Test name
Test status
Simulation time 200614771 ps
CPU time 0.88 seconds
Started Jul 31 05:39:37 PM PDT 24
Finished Jul 31 05:39:38 PM PDT 24
Peak memory 206992 kb
Host smart-90e330e4-3bed-4243-85a5-c949589ccd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12453
84287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1245384287
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.2478820503
Short name T1254
Test name
Test status
Simulation time 144990544 ps
CPU time 0.83 seconds
Started Jul 31 05:39:30 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 206976 kb
Host smart-862e7c7b-32ce-49a0-bdbb-3405dda1c43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24788
20503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.2478820503
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.1047894963
Short name T633
Test name
Test status
Simulation time 230584032 ps
CPU time 1.07 seconds
Started Jul 31 05:39:37 PM PDT 24
Finished Jul 31 05:39:39 PM PDT 24
Peak memory 207028 kb
Host smart-7afdbb94-55e1-444f-b201-7c84a06d4145
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10478
94963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1047894963
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.3827627974
Short name T2829
Test name
Test status
Simulation time 6155413504 ps
CPU time 62.88 seconds
Started Jul 31 05:39:30 PM PDT 24
Finished Jul 31 05:40:33 PM PDT 24
Peak memory 216680 kb
Host smart-39ab0369-5652-4bb6-a663-18710a1a4be2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3827627974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.3827627974
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2284486031
Short name T1155
Test name
Test status
Simulation time 203377365 ps
CPU time 0.96 seconds
Started Jul 31 05:39:30 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 207024 kb
Host smart-ea0153a9-d82a-4676-9eaf-865fc7931a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22844
86031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2284486031
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.3767859828
Short name T2331
Test name
Test status
Simulation time 173830283 ps
CPU time 0.89 seconds
Started Jul 31 05:39:32 PM PDT 24
Finished Jul 31 05:39:33 PM PDT 24
Peak memory 207036 kb
Host smart-35be58f6-c492-46ee-b916-96f4c4806587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
59828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3767859828
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.3309642572
Short name T630
Test name
Test status
Simulation time 810221014 ps
CPU time 2.06 seconds
Started Jul 31 05:39:29 PM PDT 24
Finished Jul 31 05:39:31 PM PDT 24
Peak memory 206988 kb
Host smart-67920992-4500-42ff-be4f-8ebe79b94a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33096
42572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.3309642572
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.1006135859
Short name T1266
Test name
Test status
Simulation time 7456445364 ps
CPU time 204.65 seconds
Started Jul 31 05:39:31 PM PDT 24
Finished Jul 31 05:42:56 PM PDT 24
Peak memory 215380 kb
Host smart-d5fd89cf-00fd-41f2-a72c-c241deb7e8ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10061
35859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.1006135859
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1031884523
Short name T73
Test name
Test status
Simulation time 19310993337 ps
CPU time 466.76 seconds
Started Jul 31 05:39:35 PM PDT 24
Finished Jul 31 05:47:22 PM PDT 24
Peak memory 215408 kb
Host smart-78630344-2b4f-4a10-81ed-604ec6aa6892
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031884523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1031884523
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.2796348882
Short name T2283
Test name
Test status
Simulation time 4323723129 ps
CPU time 37.78 seconds
Started Jul 31 05:39:27 PM PDT 24
Finished Jul 31 05:40:05 PM PDT 24
Peak memory 207184 kb
Host smart-978ef1dc-3bf8-4113-8666-7b5fbd95be81
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796348882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.2796348882
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.999595377
Short name T1307
Test name
Test status
Simulation time 54936917 ps
CPU time 0.68 seconds
Started Jul 31 05:41:27 PM PDT 24
Finished Jul 31 05:41:28 PM PDT 24
Peak memory 207024 kb
Host smart-180a182b-17c0-40ae-8e2d-ebc4c9b40760
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=999595377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.999595377
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.4126039083
Short name T2185
Test name
Test status
Simulation time 4178967340 ps
CPU time 6.44 seconds
Started Jul 31 05:41:15 PM PDT 24
Finished Jul 31 05:41:22 PM PDT 24
Peak memory 207152 kb
Host smart-7c851596-e070-4c47-928a-4b69d9b26255
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126039083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.4126039083
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3313540405
Short name T698
Test name
Test status
Simulation time 13374139493 ps
CPU time 16.44 seconds
Started Jul 31 05:41:16 PM PDT 24
Finished Jul 31 05:41:33 PM PDT 24
Peak memory 207212 kb
Host smart-7f371b52-7ead-479a-a1f3-fea7d197dcb3
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313540405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3313540405
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.764813484
Short name T721
Test name
Test status
Simulation time 23397898882 ps
CPU time 30.06 seconds
Started Jul 31 05:41:16 PM PDT 24
Finished Jul 31 05:41:46 PM PDT 24
Peak memory 207208 kb
Host smart-0befc684-c650-4a1b-bcd3-94d40ce8caae
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764813484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_ao
n_wake_resume.764813484
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2332482836
Short name T1965
Test name
Test status
Simulation time 164382401 ps
CPU time 0.88 seconds
Started Jul 31 05:41:16 PM PDT 24
Finished Jul 31 05:41:17 PM PDT 24
Peak memory 206972 kb
Host smart-abd1285a-7d91-4ae8-8891-ccf5110d3761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23324
82836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2332482836
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1198143315
Short name T625
Test name
Test status
Simulation time 163331103 ps
CPU time 0.87 seconds
Started Jul 31 05:41:15 PM PDT 24
Finished Jul 31 05:41:16 PM PDT 24
Peak memory 206936 kb
Host smart-0589f663-d321-4abc-9c50-2d66125d0b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11981
43315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1198143315
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1441093492
Short name T517
Test name
Test status
Simulation time 424441085 ps
CPU time 1.51 seconds
Started Jul 31 05:41:16 PM PDT 24
Finished Jul 31 05:41:18 PM PDT 24
Peak memory 206956 kb
Host smart-fef5d831-1213-4524-8870-7d242d8c7da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14410
93492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1441093492
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2221768293
Short name T2186
Test name
Test status
Simulation time 1145123441 ps
CPU time 3.25 seconds
Started Jul 31 05:41:18 PM PDT 24
Finished Jul 31 05:41:21 PM PDT 24
Peak memory 207116 kb
Host smart-fbcc03f6-9413-45a2-b2b3-f1269a9ff7aa
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2221768293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2221768293
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1164300010
Short name T800
Test name
Test status
Simulation time 7535849091 ps
CPU time 18.44 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:41:40 PM PDT 24
Peak memory 207168 kb
Host smart-d0c45103-fdfa-404a-9e92-ff9d4e1e5106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11643
00010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1164300010
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_device_timeout.3585103883
Short name T1229
Test name
Test status
Simulation time 2931367005 ps
CPU time 26.49 seconds
Started Jul 31 05:41:14 PM PDT 24
Finished Jul 31 05:41:41 PM PDT 24
Peak memory 207212 kb
Host smart-b311ef32-dfa6-4e2b-a6c3-48b5e66063ca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585103883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.3585103883
Directory /workspace/10.usbdev_device_timeout/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.1941769652
Short name T1238
Test name
Test status
Simulation time 324140383 ps
CPU time 1.36 seconds
Started Jul 31 05:41:17 PM PDT 24
Finished Jul 31 05:41:19 PM PDT 24
Peak memory 206948 kb
Host smart-6509f50a-cfcb-47af-a9b7-ffd8e5e4403b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19417
69652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.1941769652
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3879829521
Short name T2510
Test name
Test status
Simulation time 140360430 ps
CPU time 0.85 seconds
Started Jul 31 05:41:17 PM PDT 24
Finished Jul 31 05:41:18 PM PDT 24
Peak memory 206984 kb
Host smart-5ead749f-16b6-4751-9d27-32a7186192c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38798
29521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3879829521
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.737193234
Short name T2751
Test name
Test status
Simulation time 31980090 ps
CPU time 0.7 seconds
Started Jul 31 05:41:17 PM PDT 24
Finished Jul 31 05:41:18 PM PDT 24
Peak memory 206964 kb
Host smart-42f62dc2-a595-4262-b6b5-3cc6d145e6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73719
3234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.737193234
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.1222643996
Short name T1803
Test name
Test status
Simulation time 793730938 ps
CPU time 2.17 seconds
Started Jul 31 05:41:16 PM PDT 24
Finished Jul 31 05:41:18 PM PDT 24
Peak memory 207116 kb
Host smart-daa0e092-b02d-40a1-a27d-33206c155c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12226
43996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1222643996
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.578034069
Short name T1501
Test name
Test status
Simulation time 145693358 ps
CPU time 1.45 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:41:23 PM PDT 24
Peak memory 206984 kb
Host smart-0ac09c7f-698a-4e63-a5ef-fac6242745b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57803
4069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.578034069
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.1066129890
Short name T1691
Test name
Test status
Simulation time 193898486 ps
CPU time 1.02 seconds
Started Jul 31 05:41:23 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 207092 kb
Host smart-89ba5a06-93c2-4672-8e4d-0fa1dbef5b75
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1066129890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1066129890
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.2399566219
Short name T17
Test name
Test status
Simulation time 154257470 ps
CPU time 0.85 seconds
Started Jul 31 05:41:21 PM PDT 24
Finished Jul 31 05:41:22 PM PDT 24
Peak memory 206956 kb
Host smart-bceb9da8-8221-43b2-9333-564185fb37e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23995
66219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.2399566219
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.777409190
Short name T1510
Test name
Test status
Simulation time 215683485 ps
CPU time 1.05 seconds
Started Jul 31 05:41:23 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 206972 kb
Host smart-cbeb8062-d386-40b5-805b-4813c0806494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77740
9190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.777409190
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1252984677
Short name T397
Test name
Test status
Simulation time 7330724126 ps
CPU time 57.08 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 215452 kb
Host smart-b4ff5f60-cf4f-4cc5-9312-4c10f645ad35
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1252984677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1252984677
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.1003798201
Short name T890
Test name
Test status
Simulation time 10411393197 ps
CPU time 133.4 seconds
Started Jul 31 05:41:23 PM PDT 24
Finished Jul 31 05:43:36 PM PDT 24
Peak memory 207180 kb
Host smart-384ee70d-7944-43c3-b59b-fedef7511377
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1003798201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1003798201
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.4102889757
Short name T486
Test name
Test status
Simulation time 255134973 ps
CPU time 1.05 seconds
Started Jul 31 05:41:21 PM PDT 24
Finished Jul 31 05:41:22 PM PDT 24
Peak memory 207000 kb
Host smart-f769aba3-dde0-419e-9155-1b0ce5b1c751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41028
89757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.4102889757
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2783094889
Short name T2397
Test name
Test status
Simulation time 23313784570 ps
CPU time 26.31 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:41:48 PM PDT 24
Peak memory 207136 kb
Host smart-2bf90ec8-527e-46fa-ad99-7a5f9b117b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27830
94889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2783094889
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.701330865
Short name T603
Test name
Test status
Simulation time 3271806555 ps
CPU time 5.08 seconds
Started Jul 31 05:41:20 PM PDT 24
Finished Jul 31 05:41:25 PM PDT 24
Peak memory 207116 kb
Host smart-095e66d4-a950-4168-bd37-c4406aafa6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70133
0865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.701330865
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2962527366
Short name T671
Test name
Test status
Simulation time 5826485098 ps
CPU time 48.94 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:42:11 PM PDT 24
Peak memory 217448 kb
Host smart-bb7b9ed9-ab13-450e-b389-81a77264e325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29625
27366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2962527366
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.113688782
Short name T2416
Test name
Test status
Simulation time 3740334422 ps
CPU time 106.13 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:43:08 PM PDT 24
Peak memory 215408 kb
Host smart-4105334d-c4b4-4df1-a090-9ecb28636ef0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=113688782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.113688782
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.341742096
Short name T387
Test name
Test status
Simulation time 250286799 ps
CPU time 1.04 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:41:23 PM PDT 24
Peak memory 207000 kb
Host smart-fdb67468-f5a9-4ff1-8bc3-0589ccfe34eb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=341742096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.341742096
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3624353785
Short name T1495
Test name
Test status
Simulation time 186292207 ps
CPU time 0.93 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:41:23 PM PDT 24
Peak memory 206988 kb
Host smart-d2ed5bbe-931b-4956-b0d1-fac6ebfa5928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36243
53785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3624353785
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1543645734
Short name T691
Test name
Test status
Simulation time 5627502744 ps
CPU time 64.93 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:42:27 PM PDT 24
Peak memory 216864 kb
Host smart-49fe885f-8390-432c-9b19-c15ad08ee72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15436
45734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1543645734
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2835351120
Short name T2609
Test name
Test status
Simulation time 7499344476 ps
CPU time 220.67 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:45:03 PM PDT 24
Peak memory 215436 kb
Host smart-674de80f-6663-4f04-bb9c-a1ea5d7ffaa0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2835351120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2835351120
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.665665011
Short name T379
Test name
Test status
Simulation time 165057429 ps
CPU time 0.89 seconds
Started Jul 31 05:41:27 PM PDT 24
Finished Jul 31 05:41:28 PM PDT 24
Peak memory 206996 kb
Host smart-82226ee2-3ea6-41a2-9522-9b7251668e3e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=665665011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.665665011
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.2472797694
Short name T2676
Test name
Test status
Simulation time 151602918 ps
CPU time 0.88 seconds
Started Jul 31 05:41:25 PM PDT 24
Finished Jul 31 05:41:26 PM PDT 24
Peak memory 206988 kb
Host smart-48f8317d-de7e-44d1-af68-08259ca374fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24727
97694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.2472797694
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.4205513602
Short name T1816
Test name
Test status
Simulation time 178660175 ps
CPU time 0.93 seconds
Started Jul 31 05:41:23 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 206992 kb
Host smart-61ac0f02-4749-4404-ae29-0454fc2ccf41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42055
13602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.4205513602
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1069984861
Short name T2805
Test name
Test status
Simulation time 158922857 ps
CPU time 0.9 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:41:22 PM PDT 24
Peak memory 207016 kb
Host smart-e5be7b94-9533-4b0e-98fd-d44ea2c43c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10699
84861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1069984861
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2836070354
Short name T2600
Test name
Test status
Simulation time 187954083 ps
CPU time 0.98 seconds
Started Jul 31 05:41:26 PM PDT 24
Finished Jul 31 05:41:27 PM PDT 24
Peak memory 206968 kb
Host smart-bef042cd-1d94-4028-ace5-88b43e077423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28360
70354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2836070354
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.168640436
Short name T1561
Test name
Test status
Simulation time 158041072 ps
CPU time 0.84 seconds
Started Jul 31 05:41:23 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 207024 kb
Host smart-93a4a380-9704-46f4-bbeb-889f62e5c266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16864
0436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.168640436
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1443535763
Short name T674
Test name
Test status
Simulation time 225777544 ps
CPU time 1.01 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:41:23 PM PDT 24
Peak memory 207016 kb
Host smart-f2511556-7173-4185-b1b1-b475cb627a98
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1443535763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1443535763
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.767995250
Short name T2760
Test name
Test status
Simulation time 77671528 ps
CPU time 0.71 seconds
Started Jul 31 05:41:20 PM PDT 24
Finished Jul 31 05:41:21 PM PDT 24
Peak memory 206964 kb
Host smart-57fb49b7-7f40-4d11-9a84-3f82c50f1594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76799
5250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.767995250
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.392553075
Short name T248
Test name
Test status
Simulation time 18523270070 ps
CPU time 45.11 seconds
Started Jul 31 05:41:24 PM PDT 24
Finished Jul 31 05:42:09 PM PDT 24
Peak memory 215444 kb
Host smart-fb3326a0-efff-46db-9eec-4153e6f7e8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39255
3075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.392553075
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.2017589131
Short name T922
Test name
Test status
Simulation time 223825798 ps
CPU time 0.91 seconds
Started Jul 31 05:41:20 PM PDT 24
Finished Jul 31 05:41:21 PM PDT 24
Peak memory 206920 kb
Host smart-f0518940-824e-40ca-b574-e15f2412919b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20175
89131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2017589131
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.1638023117
Short name T380
Test name
Test status
Simulation time 201203979 ps
CPU time 0.94 seconds
Started Jul 31 05:41:23 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 206992 kb
Host smart-7e46797e-b438-4076-944f-edc6623a8e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16380
23117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.1638023117
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.712890089
Short name T2750
Test name
Test status
Simulation time 213550786 ps
CPU time 0.95 seconds
Started Jul 31 05:41:23 PM PDT 24
Finished Jul 31 05:41:24 PM PDT 24
Peak memory 206992 kb
Host smart-dfb1d0f7-d041-4109-bd14-fdd6e8c1c858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71289
0089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.712890089
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.252363543
Short name T2489
Test name
Test status
Simulation time 168632247 ps
CPU time 0.89 seconds
Started Jul 31 05:41:21 PM PDT 24
Finished Jul 31 05:41:22 PM PDT 24
Peak memory 207028 kb
Host smart-a1fbeb09-cc9f-4c33-b0eb-00def57a6def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25236
3543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.252363543
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.4238900073
Short name T2288
Test name
Test status
Simulation time 155238614 ps
CPU time 0.82 seconds
Started Jul 31 05:41:29 PM PDT 24
Finished Jul 31 05:41:30 PM PDT 24
Peak memory 206956 kb
Host smart-404af56c-8c19-42c0-8cc0-2bfc20df9eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
00073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.4238900073
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2965898382
Short name T1477
Test name
Test status
Simulation time 155957756 ps
CPU time 0.83 seconds
Started Jul 31 05:41:26 PM PDT 24
Finished Jul 31 05:41:27 PM PDT 24
Peak memory 206940 kb
Host smart-1b893897-bf82-4a0c-b09c-63064bbfcdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29658
98382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2965898382
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3046327914
Short name T2190
Test name
Test status
Simulation time 148436316 ps
CPU time 0.86 seconds
Started Jul 31 05:41:28 PM PDT 24
Finished Jul 31 05:41:29 PM PDT 24
Peak memory 206980 kb
Host smart-f96508f7-2f72-4619-955d-eb491040cc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30463
27914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3046327914
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.801292778
Short name T1143
Test name
Test status
Simulation time 241094022 ps
CPU time 1.08 seconds
Started Jul 31 05:41:31 PM PDT 24
Finished Jul 31 05:41:33 PM PDT 24
Peak memory 207004 kb
Host smart-a79902e0-8183-4cc0-8559-725fe277001e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80129
2778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.801292778
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.3595026554
Short name T2334
Test name
Test status
Simulation time 4313939988 ps
CPU time 129.84 seconds
Started Jul 31 05:41:28 PM PDT 24
Finished Jul 31 05:43:37 PM PDT 24
Peak memory 215412 kb
Host smart-e7a54980-a2bd-4e32-ad57-b3dadb9fa06d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3595026554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.3595026554
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3159297085
Short name T1188
Test name
Test status
Simulation time 163698032 ps
CPU time 0.85 seconds
Started Jul 31 05:41:29 PM PDT 24
Finished Jul 31 05:41:30 PM PDT 24
Peak memory 207008 kb
Host smart-5fb02c31-e938-4dd7-99ab-c786cb894fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31592
97085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3159297085
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.3693727966
Short name T2581
Test name
Test status
Simulation time 192911674 ps
CPU time 0.95 seconds
Started Jul 31 05:41:31 PM PDT 24
Finished Jul 31 05:41:32 PM PDT 24
Peak memory 207004 kb
Host smart-a434e4f1-afe8-4d2a-8222-c59e3b1fc71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36937
27966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3693727966
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.3522473978
Short name T1080
Test name
Test status
Simulation time 246824937 ps
CPU time 1.01 seconds
Started Jul 31 05:41:28 PM PDT 24
Finished Jul 31 05:41:29 PM PDT 24
Peak memory 206936 kb
Host smart-f97aefde-3551-4431-8566-96135e9be154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35224
73978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3522473978
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3175988794
Short name T1227
Test name
Test status
Simulation time 5171050436 ps
CPU time 150.32 seconds
Started Jul 31 05:41:31 PM PDT 24
Finished Jul 31 05:44:01 PM PDT 24
Peak memory 215392 kb
Host smart-75aa26e0-a75a-4334-8d09-6af74636948a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31759
88794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3175988794
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.1709462843
Short name T1492
Test name
Test status
Simulation time 4309268812 ps
CPU time 39.63 seconds
Started Jul 31 05:41:22 PM PDT 24
Finished Jul 31 05:42:01 PM PDT 24
Peak memory 207204 kb
Host smart-57f550db-7e01-44cf-ac08-07ec59bc254f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709462843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.1709462843
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3577465995
Short name T1351
Test name
Test status
Simulation time 51054687 ps
CPU time 0.69 seconds
Started Jul 31 05:41:41 PM PDT 24
Finished Jul 31 05:41:42 PM PDT 24
Peak memory 207044 kb
Host smart-32badb9e-3692-4eed-bb70-459b92546042
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3577465995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3577465995
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3167403830
Short name T1902
Test name
Test status
Simulation time 4194376008 ps
CPU time 6.45 seconds
Started Jul 31 05:41:30 PM PDT 24
Finished Jul 31 05:41:36 PM PDT 24
Peak memory 207100 kb
Host smart-684e21af-99bf-4725-9653-3e13512cf1c8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167403830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.3167403830
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3484855681
Short name T1558
Test name
Test status
Simulation time 13467465226 ps
CPU time 15.77 seconds
Started Jul 31 05:41:30 PM PDT 24
Finished Jul 31 05:41:46 PM PDT 24
Peak memory 207236 kb
Host smart-544d9b58-01f8-4688-8066-d274e8491b9d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484855681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3484855681
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3890888432
Short name T757
Test name
Test status
Simulation time 23413188331 ps
CPU time 35.43 seconds
Started Jul 31 05:41:30 PM PDT 24
Finished Jul 31 05:42:06 PM PDT 24
Peak memory 207184 kb
Host smart-b611b396-59bf-4b07-8cb5-6f46cc548cb6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890888432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.3890888432
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.4255419331
Short name T2704
Test name
Test status
Simulation time 159834773 ps
CPU time 0.88 seconds
Started Jul 31 05:41:28 PM PDT 24
Finished Jul 31 05:41:29 PM PDT 24
Peak memory 206964 kb
Host smart-de382a56-ef32-4782-9b09-d60a1f877dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42554
19331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.4255419331
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3913114091
Short name T2355
Test name
Test status
Simulation time 151412741 ps
CPU time 0.89 seconds
Started Jul 31 05:41:29 PM PDT 24
Finished Jul 31 05:41:30 PM PDT 24
Peak memory 206924 kb
Host smart-c7eee4f6-ad13-40a2-a4f2-5e1b8d71bc72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39131
14091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3913114091
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.227578954
Short name T1455
Test name
Test status
Simulation time 216634994 ps
CPU time 1.07 seconds
Started Jul 31 05:41:28 PM PDT 24
Finished Jul 31 05:41:29 PM PDT 24
Peak memory 206948 kb
Host smart-d0e1b281-2f1b-44d3-8279-0eeaa6377d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22757
8954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.227578954
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.717051392
Short name T1251
Test name
Test status
Simulation time 644539110 ps
CPU time 1.9 seconds
Started Jul 31 05:41:27 PM PDT 24
Finished Jul 31 05:41:29 PM PDT 24
Peak memory 206996 kb
Host smart-0800c823-b8dd-4bf7-afb8-275e95450c10
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=717051392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.717051392
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2124071823
Short name T164
Test name
Test status
Simulation time 7743199572 ps
CPU time 17.68 seconds
Started Jul 31 05:41:32 PM PDT 24
Finished Jul 31 05:41:49 PM PDT 24
Peak memory 207160 kb
Host smart-19a2f10b-2ad0-48a1-9ed3-62bbf915693f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21240
71823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2124071823
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_device_timeout.3374103875
Short name T2764
Test name
Test status
Simulation time 998714064 ps
CPU time 21.17 seconds
Started Jul 31 05:41:32 PM PDT 24
Finished Jul 31 05:41:54 PM PDT 24
Peak memory 207096 kb
Host smart-7972f574-384e-4c3d-892b-41533b05dce8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374103875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.3374103875
Directory /workspace/11.usbdev_device_timeout/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2293760375
Short name T2067
Test name
Test status
Simulation time 379294389 ps
CPU time 1.28 seconds
Started Jul 31 05:41:33 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 206952 kb
Host smart-1b8f83de-23e9-4d00-8426-bc9329224354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22937
60375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2293760375
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3120570822
Short name T2272
Test name
Test status
Simulation time 140976443 ps
CPU time 0.81 seconds
Started Jul 31 05:41:32 PM PDT 24
Finished Jul 31 05:41:33 PM PDT 24
Peak memory 206948 kb
Host smart-676a28ec-c7d0-4236-9bfe-710b491e0a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31205
70822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3120570822
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.539152174
Short name T2085
Test name
Test status
Simulation time 68269516 ps
CPU time 0.75 seconds
Started Jul 31 05:41:38 PM PDT 24
Finished Jul 31 05:41:39 PM PDT 24
Peak memory 206952 kb
Host smart-21834ef2-edcf-4f78-a424-d7c290c68b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53915
2174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.539152174
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2999653402
Short name T1792
Test name
Test status
Simulation time 1001656872 ps
CPU time 2.57 seconds
Started Jul 31 05:41:33 PM PDT 24
Finished Jul 31 05:41:36 PM PDT 24
Peak memory 207140 kb
Host smart-e9ff895b-78dc-4a1e-af14-4e1b14e8cfef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29996
53402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2999653402
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.1158679231
Short name T1035
Test name
Test status
Simulation time 210388452 ps
CPU time 1.14 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 215300 kb
Host smart-148a444a-0c3c-4464-b863-ecc004b4d6a6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1158679231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1158679231
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1758235064
Short name T914
Test name
Test status
Simulation time 140504146 ps
CPU time 0.83 seconds
Started Jul 31 05:41:38 PM PDT 24
Finished Jul 31 05:41:38 PM PDT 24
Peak memory 206936 kb
Host smart-31587d76-ea42-4e09-bb23-d800a3534697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17582
35064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1758235064
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3466680615
Short name T2513
Test name
Test status
Simulation time 186307909 ps
CPU time 0.96 seconds
Started Jul 31 05:41:36 PM PDT 24
Finished Jul 31 05:41:37 PM PDT 24
Peak memory 207012 kb
Host smart-fc8137ba-669a-4b9d-98da-8b9f1282927c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34666
80615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3466680615
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.3314357037
Short name T482
Test name
Test status
Simulation time 9272108616 ps
CPU time 268.22 seconds
Started Jul 31 05:41:39 PM PDT 24
Finished Jul 31 05:46:07 PM PDT 24
Peak memory 215412 kb
Host smart-681d4bcb-6593-4ae7-af05-3811fcb43bd7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3314357037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.3314357037
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.3175796429
Short name T1724
Test name
Test status
Simulation time 5401044230 ps
CPU time 38.34 seconds
Started Jul 31 05:41:36 PM PDT 24
Finished Jul 31 05:42:15 PM PDT 24
Peak memory 207192 kb
Host smart-99fd4c97-629f-45da-9e68-da895e2cf961
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3175796429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.3175796429
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.2155214991
Short name T2208
Test name
Test status
Simulation time 243647711 ps
CPU time 1.01 seconds
Started Jul 31 05:41:32 PM PDT 24
Finished Jul 31 05:41:33 PM PDT 24
Peak memory 206920 kb
Host smart-78823459-99b7-46f6-931e-7093eaf9b13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21552
14991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.2155214991
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1514782488
Short name T392
Test name
Test status
Simulation time 23312364121 ps
CPU time 29.69 seconds
Started Jul 31 05:41:35 PM PDT 24
Finished Jul 31 05:42:05 PM PDT 24
Peak memory 207160 kb
Host smart-bc3295b8-de20-485e-ac9c-11d6269afa6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15147
82488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1514782488
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2548294631
Short name T748
Test name
Test status
Simulation time 3329798776 ps
CPU time 5.49 seconds
Started Jul 31 05:41:36 PM PDT 24
Finished Jul 31 05:41:42 PM PDT 24
Peak memory 207128 kb
Host smart-ce709632-30e0-4c1b-b267-24d0a438f499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482
94631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2548294631
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.1439257827
Short name T586
Test name
Test status
Simulation time 9393054850 ps
CPU time 89.6 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:43:04 PM PDT 24
Peak memory 217432 kb
Host smart-d1095bd8-6e01-4153-9ec5-8e29c4c2e66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14392
57827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.1439257827
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3101619141
Short name T1641
Test name
Test status
Simulation time 2972589564 ps
CPU time 84.96 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 215436 kb
Host smart-6d36f353-7bf4-409f-b417-473a2046cdbf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3101619141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3101619141
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.809076448
Short name T2738
Test name
Test status
Simulation time 244728778 ps
CPU time 1 seconds
Started Jul 31 05:41:38 PM PDT 24
Finished Jul 31 05:41:39 PM PDT 24
Peak memory 207024 kb
Host smart-ee4e920b-f298-4c9c-9bb5-9c56b5985a1d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=809076448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.809076448
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2026732375
Short name T1057
Test name
Test status
Simulation time 194110559 ps
CPU time 0.91 seconds
Started Jul 31 05:41:33 PM PDT 24
Finished Jul 31 05:41:34 PM PDT 24
Peak memory 206984 kb
Host smart-eb3bb176-5f15-4154-bcb8-83f2542297ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20267
32375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2026732375
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1187264137
Short name T2009
Test name
Test status
Simulation time 3097892514 ps
CPU time 32.53 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:42:06 PM PDT 24
Peak memory 216960 kb
Host smart-6b69b51e-51c0-4bc1-b332-e1d172271928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11872
64137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1187264137
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.1945519861
Short name T1819
Test name
Test status
Simulation time 4900702860 ps
CPU time 37.96 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:42:12 PM PDT 24
Peak memory 216868 kb
Host smart-c8fb0d93-b164-4cb0-bcf5-796b798b874a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1945519861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.1945519861
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.1206588214
Short name T1142
Test name
Test status
Simulation time 154241389 ps
CPU time 0.86 seconds
Started Jul 31 05:41:33 PM PDT 24
Finished Jul 31 05:41:34 PM PDT 24
Peak memory 206988 kb
Host smart-7b254aac-881b-49bb-963c-e9806efa5c5d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1206588214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.1206588214
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3475152796
Short name T390
Test name
Test status
Simulation time 150974381 ps
CPU time 0.88 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 207024 kb
Host smart-8f05b83c-309c-4e8b-9f25-ffe857ead4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34751
52796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3475152796
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.1389713895
Short name T997
Test name
Test status
Simulation time 200602584 ps
CPU time 0.97 seconds
Started Jul 31 05:41:38 PM PDT 24
Finished Jul 31 05:41:39 PM PDT 24
Peak memory 206964 kb
Host smart-ca1cfc0d-19c0-465b-81a4-c9bf5ca6622e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13897
13895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.1389713895
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.516106257
Short name T1846
Test name
Test status
Simulation time 214228642 ps
CPU time 0.93 seconds
Started Jul 31 05:41:37 PM PDT 24
Finished Jul 31 05:41:38 PM PDT 24
Peak memory 207020 kb
Host smart-540d3728-80d7-4055-9cca-1333e46cf7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51610
6257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.516106257
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.3921156440
Short name T165
Test name
Test status
Simulation time 146437123 ps
CPU time 0.83 seconds
Started Jul 31 05:41:33 PM PDT 24
Finished Jul 31 05:41:34 PM PDT 24
Peak memory 206996 kb
Host smart-b6fff23d-e707-459e-be8d-2c20798803e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39211
56440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.3921156440
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.3926591693
Short name T2285
Test name
Test status
Simulation time 203577712 ps
CPU time 0.96 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 207000 kb
Host smart-857a60cc-6282-43bd-8376-6383dad8b124
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3926591693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.3926591693
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.980665633
Short name T2031
Test name
Test status
Simulation time 173217007 ps
CPU time 0.84 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 206944 kb
Host smart-82c3623c-6ad4-4f7a-b40d-30778f15e2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98066
5633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.980665633
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3541704357
Short name T2316
Test name
Test status
Simulation time 109722761 ps
CPU time 0.77 seconds
Started Jul 31 05:41:36 PM PDT 24
Finished Jul 31 05:41:36 PM PDT 24
Peak memory 206972 kb
Host smart-cdc9a949-4e75-4d57-a9c2-c3203ad8b8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
04357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3541704357
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1347345416
Short name T2727
Test name
Test status
Simulation time 21307563894 ps
CPU time 55.64 seconds
Started Jul 31 05:41:38 PM PDT 24
Finished Jul 31 05:42:34 PM PDT 24
Peak memory 215420 kb
Host smart-cc5ef588-bb12-4f3e-90c8-276294d5845d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13473
45416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1347345416
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.804748928
Short name T2535
Test name
Test status
Simulation time 168559760 ps
CPU time 0.9 seconds
Started Jul 31 05:41:39 PM PDT 24
Finished Jul 31 05:41:40 PM PDT 24
Peak memory 206988 kb
Host smart-4832e601-e769-40c2-aec6-ff5f7501af30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80474
8928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.804748928
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1754653878
Short name T1058
Test name
Test status
Simulation time 188448876 ps
CPU time 0.93 seconds
Started Jul 31 05:41:39 PM PDT 24
Finished Jul 31 05:41:40 PM PDT 24
Peak memory 206968 kb
Host smart-d9427958-b829-4db2-b24f-f7975983c986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546
53878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1754653878
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2616450540
Short name T2606
Test name
Test status
Simulation time 261047907 ps
CPU time 1.04 seconds
Started Jul 31 05:41:41 PM PDT 24
Finished Jul 31 05:41:42 PM PDT 24
Peak memory 206964 kb
Host smart-239c81a4-c38a-433c-ba63-063c03099960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26164
50540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2616450540
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.1284013086
Short name T1628
Test name
Test status
Simulation time 234743264 ps
CPU time 0.96 seconds
Started Jul 31 05:41:41 PM PDT 24
Finished Jul 31 05:41:42 PM PDT 24
Peak memory 207036 kb
Host smart-cb12030b-e586-4ad6-b5e9-2b68491a0a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12840
13086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.1284013086
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3398111983
Short name T2216
Test name
Test status
Simulation time 143346720 ps
CPU time 0.86 seconds
Started Jul 31 05:41:40 PM PDT 24
Finished Jul 31 05:41:41 PM PDT 24
Peak memory 206940 kb
Host smart-c2287432-9d68-4ac2-8c0b-3523b064ffea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33981
11983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3398111983
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.4117058786
Short name T21
Test name
Test status
Simulation time 154147087 ps
CPU time 0.95 seconds
Started Jul 31 05:41:40 PM PDT 24
Finished Jul 31 05:41:41 PM PDT 24
Peak memory 206952 kb
Host smart-ca11c72b-e061-4f3f-9a3b-2a5c174b1edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41170
58786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.4117058786
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3991133153
Short name T1926
Test name
Test status
Simulation time 182487843 ps
CPU time 0.85 seconds
Started Jul 31 05:41:40 PM PDT 24
Finished Jul 31 05:41:41 PM PDT 24
Peak memory 207048 kb
Host smart-206045e7-52ae-431c-9dcb-e0555765e879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39911
33153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3991133153
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1802592891
Short name T1837
Test name
Test status
Simulation time 242627269 ps
CPU time 1.12 seconds
Started Jul 31 05:41:39 PM PDT 24
Finished Jul 31 05:41:41 PM PDT 24
Peak memory 206988 kb
Host smart-7fc9475e-fb1a-4f3f-8c27-20e62d1dc110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
92891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1802592891
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.1395814741
Short name T2567
Test name
Test status
Simulation time 4416333974 ps
CPU time 35.11 seconds
Started Jul 31 05:41:40 PM PDT 24
Finished Jul 31 05:42:15 PM PDT 24
Peak memory 215412 kb
Host smart-e1893586-b16f-482c-98c8-664c47841655
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1395814741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.1395814741
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.3302031241
Short name T2836
Test name
Test status
Simulation time 196525045 ps
CPU time 0.94 seconds
Started Jul 31 05:41:38 PM PDT 24
Finished Jul 31 05:41:39 PM PDT 24
Peak memory 207000 kb
Host smart-3fb786ce-b4ff-42f3-8cac-19aa4b556ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33020
31241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3302031241
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.1338384008
Short name T2394
Test name
Test status
Simulation time 158831382 ps
CPU time 0.89 seconds
Started Jul 31 05:41:39 PM PDT 24
Finished Jul 31 05:41:40 PM PDT 24
Peak memory 206976 kb
Host smart-6d798cc0-3a75-4c53-9177-fdf6ad2bc25d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13383
84008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.1338384008
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.218049105
Short name T347
Test name
Test status
Simulation time 629898142 ps
CPU time 1.72 seconds
Started Jul 31 05:41:38 PM PDT 24
Finished Jul 31 05:41:40 PM PDT 24
Peak memory 207000 kb
Host smart-857dcf35-683f-46fc-9c4e-ac00ea5424a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21804
9105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.218049105
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.1158000661
Short name T1225
Test name
Test status
Simulation time 4784663742 ps
CPU time 34.99 seconds
Started Jul 31 05:41:40 PM PDT 24
Finished Jul 31 05:42:15 PM PDT 24
Peak memory 216868 kb
Host smart-eec4d580-a139-4505-b600-ac64b5ce8329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11580
00661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.1158000661
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.3916010826
Short name T1203
Test name
Test status
Simulation time 2945919758 ps
CPU time 24.83 seconds
Started Jul 31 05:41:34 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 207252 kb
Host smart-30e83197-35a8-4611-abc6-eef3bbe18dff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916010826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos
t_handshake.3916010826
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.1738643890
Short name T2478
Test name
Test status
Simulation time 58024629 ps
CPU time 0.72 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 207016 kb
Host smart-049a8877-d90b-4fb1-9c35-36330ecd4bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1738643890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.1738643890
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3982017065
Short name T733
Test name
Test status
Simulation time 3753923955 ps
CPU time 5.39 seconds
Started Jul 31 05:41:41 PM PDT 24
Finished Jul 31 05:41:46 PM PDT 24
Peak memory 207180 kb
Host smart-c8e12cf9-2700-48ce-9eaf-56ca5b83d72c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982017065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_disconnect.3982017065
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1039371248
Short name T1586
Test name
Test status
Simulation time 13369248380 ps
CPU time 14.68 seconds
Started Jul 31 05:41:41 PM PDT 24
Finished Jul 31 05:41:55 PM PDT 24
Peak memory 207228 kb
Host smart-812f2b27-cfb7-497b-94ab-1def8ae34693
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039371248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1039371248
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.633833326
Short name T2550
Test name
Test status
Simulation time 23321206399 ps
CPU time 27.18 seconds
Started Jul 31 05:41:41 PM PDT 24
Finished Jul 31 05:42:08 PM PDT 24
Peak memory 207196 kb
Host smart-3a21fb76-d721-452d-9f97-9c76c6776ab6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633833326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_ao
n_wake_resume.633833326
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.4086936582
Short name T1365
Test name
Test status
Simulation time 191706117 ps
CPU time 0.94 seconds
Started Jul 31 05:41:39 PM PDT 24
Finished Jul 31 05:41:40 PM PDT 24
Peak memory 207004 kb
Host smart-add5162b-0649-46c3-8a24-b9f513595e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40869
36582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.4086936582
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.3456931689
Short name T1119
Test name
Test status
Simulation time 151739370 ps
CPU time 0.9 seconds
Started Jul 31 05:41:40 PM PDT 24
Finished Jul 31 05:41:41 PM PDT 24
Peak memory 206924 kb
Host smart-b8e072f6-c851-4b12-8baa-194926bddf36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34569
31689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3456931689
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.1280954145
Short name T2539
Test name
Test status
Simulation time 288140211 ps
CPU time 1.12 seconds
Started Jul 31 05:41:42 PM PDT 24
Finished Jul 31 05:41:43 PM PDT 24
Peak memory 207004 kb
Host smart-0b58b492-a18b-4f46-97fe-cac0f2ded823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12809
54145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.1280954145
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.3994848395
Short name T2812
Test name
Test status
Simulation time 517735248 ps
CPU time 1.4 seconds
Started Jul 31 05:41:39 PM PDT 24
Finished Jul 31 05:41:41 PM PDT 24
Peak memory 206964 kb
Host smart-c32eb107-9139-4dcd-a07b-7d06e2d01b4b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3994848395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.3994848395
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.4080966064
Short name T1444
Test name
Test status
Simulation time 8572855690 ps
CPU time 19.31 seconds
Started Jul 31 05:41:39 PM PDT 24
Finished Jul 31 05:41:58 PM PDT 24
Peak memory 207228 kb
Host smart-e42117f8-3ff8-437c-907c-90fb69b997db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40809
66064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.4080966064
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_device_timeout.3256226000
Short name T2455
Test name
Test status
Simulation time 428212925 ps
CPU time 7.54 seconds
Started Jul 31 05:41:42 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 207120 kb
Host smart-f0efd481-6265-430a-9bb0-c83caabe7c2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256226000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.3256226000
Directory /workspace/12.usbdev_device_timeout/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.624121060
Short name T692
Test name
Test status
Simulation time 410049674 ps
CPU time 1.47 seconds
Started Jul 31 05:41:41 PM PDT 24
Finished Jul 31 05:41:42 PM PDT 24
Peak memory 206964 kb
Host smart-1b3079ca-54d1-4a3f-94f8-d28b972445b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62412
1060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.624121060
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.2986775157
Short name T865
Test name
Test status
Simulation time 146145670 ps
CPU time 0.83 seconds
Started Jul 31 05:41:38 PM PDT 24
Finished Jul 31 05:41:39 PM PDT 24
Peak memory 206952 kb
Host smart-2c04cc00-fbde-49a3-b86a-1ea55b355d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867
75157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2986775157
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3692748861
Short name T1439
Test name
Test status
Simulation time 35649609 ps
CPU time 0.69 seconds
Started Jul 31 05:41:39 PM PDT 24
Finished Jul 31 05:41:39 PM PDT 24
Peak memory 206936 kb
Host smart-5e9bf791-e20f-4857-b15f-4163ed331727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36927
48861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3692748861
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2655348628
Short name T920
Test name
Test status
Simulation time 874952134 ps
CPU time 2.48 seconds
Started Jul 31 05:41:40 PM PDT 24
Finished Jul 31 05:41:42 PM PDT 24
Peak memory 207100 kb
Host smart-44439f20-2cfc-4051-899a-6f9765c1d441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26553
48628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2655348628
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2323054496
Short name T2015
Test name
Test status
Simulation time 409704950 ps
CPU time 2.57 seconds
Started Jul 31 05:41:40 PM PDT 24
Finished Jul 31 05:41:42 PM PDT 24
Peak memory 207048 kb
Host smart-1be97de4-af8e-468f-847e-6f98dbe4f2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23230
54496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2323054496
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.2630557619
Short name T1734
Test name
Test status
Simulation time 174269593 ps
CPU time 0.88 seconds
Started Jul 31 05:41:45 PM PDT 24
Finished Jul 31 05:41:46 PM PDT 24
Peak memory 207020 kb
Host smart-76e6a2c1-7638-433d-87b9-a8d2c336e9ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2630557619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2630557619
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2346559763
Short name T2527
Test name
Test status
Simulation time 145554010 ps
CPU time 0.81 seconds
Started Jul 31 05:41:47 PM PDT 24
Finished Jul 31 05:41:48 PM PDT 24
Peak memory 206964 kb
Host smart-a7567d95-5c83-4a5b-bdb1-576c414e2d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
59763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2346559763
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1203911492
Short name T1173
Test name
Test status
Simulation time 253518175 ps
CPU time 1.01 seconds
Started Jul 31 05:41:45 PM PDT 24
Finished Jul 31 05:41:47 PM PDT 24
Peak memory 207004 kb
Host smart-457e66cd-97f8-42f0-91e8-bd76a40a9b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12039
11492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1203911492
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.3877326419
Short name T1916
Test name
Test status
Simulation time 4931390533 ps
CPU time 139.04 seconds
Started Jul 31 05:41:47 PM PDT 24
Finished Jul 31 05:44:06 PM PDT 24
Peak memory 215372 kb
Host smart-b123eed8-6bd5-467e-90b4-87b27b46936f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3877326419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.3877326419
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.2787237474
Short name T628
Test name
Test status
Simulation time 5052207638 ps
CPU time 35.14 seconds
Started Jul 31 05:41:44 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 207176 kb
Host smart-cbb110b0-dea4-4955-8a6a-4af89b80e38c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2787237474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2787237474
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.577131340
Short name T1218
Test name
Test status
Simulation time 161700061 ps
CPU time 0.86 seconds
Started Jul 31 05:41:49 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 207032 kb
Host smart-d41609e1-818f-4bde-8810-243a7eb7029e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57713
1340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.577131340
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2818305640
Short name T704
Test name
Test status
Simulation time 23346193937 ps
CPU time 25.34 seconds
Started Jul 31 05:41:47 PM PDT 24
Finished Jul 31 05:42:12 PM PDT 24
Peak memory 207204 kb
Host smart-593bfb96-9c9a-4c13-83c2-ebb02115e3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28183
05640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2818305640
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.4057678045
Short name T2326
Test name
Test status
Simulation time 3264829951 ps
CPU time 5.45 seconds
Started Jul 31 05:41:45 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 207132 kb
Host smart-204d6ffd-cba2-4cde-8680-59a60b569cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40576
78045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.4057678045
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.1745126802
Short name T294
Test name
Test status
Simulation time 8123307513 ps
CPU time 59.05 seconds
Started Jul 31 05:41:49 PM PDT 24
Finished Jul 31 05:42:48 PM PDT 24
Peak memory 217532 kb
Host smart-d0b5f0b0-b992-40ba-9fdf-8ffc40339c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17451
26802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1745126802
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2217139181
Short name T1668
Test name
Test status
Simulation time 6371088952 ps
CPU time 59.44 seconds
Started Jul 31 05:41:47 PM PDT 24
Finished Jul 31 05:42:47 PM PDT 24
Peak memory 207232 kb
Host smart-886a25e3-1aa3-47b3-b1a1-814b772813a1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2217139181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2217139181
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.140204749
Short name T2808
Test name
Test status
Simulation time 249219921 ps
CPU time 1.01 seconds
Started Jul 31 05:41:45 PM PDT 24
Finished Jul 31 05:41:46 PM PDT 24
Peak memory 207020 kb
Host smart-58eba17b-0bdd-4df8-a93f-d677f4678e56
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=140204749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.140204749
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1849242817
Short name T1597
Test name
Test status
Simulation time 199806284 ps
CPU time 0.93 seconds
Started Jul 31 05:41:46 PM PDT 24
Finished Jul 31 05:41:47 PM PDT 24
Peak memory 207012 kb
Host smart-18f5ff6d-9354-4385-b8a4-a46af04961c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18492
42817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1849242817
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.1730892791
Short name T2744
Test name
Test status
Simulation time 3841373541 ps
CPU time 28.86 seconds
Started Jul 31 05:41:49 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 215424 kb
Host smart-636b0a1f-b983-4cf2-8d3b-e10290e987d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17308
92791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.1730892791
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.2469551019
Short name T394
Test name
Test status
Simulation time 4640696260 ps
CPU time 34.11 seconds
Started Jul 31 05:41:47 PM PDT 24
Finished Jul 31 05:42:22 PM PDT 24
Peak memory 207224 kb
Host smart-998d96df-a201-4540-8a34-4dd68e19e105
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2469551019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.2469551019
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2942931404
Short name T506
Test name
Test status
Simulation time 164417647 ps
CPU time 0.87 seconds
Started Jul 31 05:41:44 PM PDT 24
Finished Jul 31 05:41:45 PM PDT 24
Peak memory 206984 kb
Host smart-c9964fc8-2fb7-4579-8523-5154e188b0d8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2942931404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2942931404
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1410426726
Short name T1751
Test name
Test status
Simulation time 147346014 ps
CPU time 0.84 seconds
Started Jul 31 05:41:45 PM PDT 24
Finished Jul 31 05:41:46 PM PDT 24
Peak memory 207000 kb
Host smart-027bedeb-020d-4d72-989f-78a7050ae83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14104
26726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1410426726
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3132704500
Short name T722
Test name
Test status
Simulation time 168352072 ps
CPU time 0.87 seconds
Started Jul 31 05:41:49 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 207036 kb
Host smart-0ded4aeb-192a-491d-af09-294b0cee1568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31327
04500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3132704500
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3268451612
Short name T2476
Test name
Test status
Simulation time 158252629 ps
CPU time 0.84 seconds
Started Jul 31 05:41:47 PM PDT 24
Finished Jul 31 05:41:48 PM PDT 24
Peak memory 207016 kb
Host smart-e61558cd-39d0-4949-a7e2-94f1917bfbe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32684
51612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3268451612
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3005053148
Short name T1973
Test name
Test status
Simulation time 189308148 ps
CPU time 0.88 seconds
Started Jul 31 05:41:50 PM PDT 24
Finished Jul 31 05:41:51 PM PDT 24
Peak memory 206996 kb
Host smart-ac430ac3-ab42-40c3-bcd7-78e9ab372eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30050
53148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3005053148
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1022902216
Short name T1369
Test name
Test status
Simulation time 163145310 ps
CPU time 0.8 seconds
Started Jul 31 05:41:44 PM PDT 24
Finished Jul 31 05:41:45 PM PDT 24
Peak memory 206972 kb
Host smart-fe5d1ac6-8e9e-44ee-9290-56d132218531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10229
02216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1022902216
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.3597361343
Short name T1613
Test name
Test status
Simulation time 235502281 ps
CPU time 1.09 seconds
Started Jul 31 05:41:49 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 206996 kb
Host smart-e8dae409-7bc9-4eec-8653-ed846b7ddc53
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3597361343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.3597361343
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.780982550
Short name T2619
Test name
Test status
Simulation time 149508097 ps
CPU time 0.85 seconds
Started Jul 31 05:41:49 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 206964 kb
Host smart-411ac2ab-10db-4c56-bb1e-bfe36c7f5833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78098
2550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.780982550
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3618280689
Short name T25
Test name
Test status
Simulation time 51527227 ps
CPU time 0.69 seconds
Started Jul 31 05:41:48 PM PDT 24
Finished Jul 31 05:41:49 PM PDT 24
Peak memory 206996 kb
Host smart-b4bb55ff-dcc7-424b-b64a-b2699be811a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36182
80689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3618280689
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2994077338
Short name T273
Test name
Test status
Simulation time 21152603366 ps
CPU time 50.64 seconds
Started Jul 31 05:41:46 PM PDT 24
Finished Jul 31 05:42:37 PM PDT 24
Peak memory 215368 kb
Host smart-61b1da9d-2cce-4125-b498-20d2eeb0536e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29940
77338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2994077338
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.4101164956
Short name T1509
Test name
Test status
Simulation time 160124585 ps
CPU time 0.91 seconds
Started Jul 31 05:41:50 PM PDT 24
Finished Jul 31 05:41:51 PM PDT 24
Peak memory 207000 kb
Host smart-aabbfab8-f0cf-46f1-8fbe-8181276a5cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41011
64956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.4101164956
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.81842206
Short name T1589
Test name
Test status
Simulation time 229378606 ps
CPU time 0.94 seconds
Started Jul 31 05:41:47 PM PDT 24
Finished Jul 31 05:41:48 PM PDT 24
Peak memory 206968 kb
Host smart-7cc4aa21-3553-45bd-8497-79c0843847ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81842
206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.81842206
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.3310120466
Short name T1200
Test name
Test status
Simulation time 301971311 ps
CPU time 1.05 seconds
Started Jul 31 05:41:49 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 206996 kb
Host smart-b38e379a-50ca-4562-b43c-3a8d39ee101a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33101
20466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3310120466
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3988139466
Short name T1802
Test name
Test status
Simulation time 145659483 ps
CPU time 0.93 seconds
Started Jul 31 05:41:47 PM PDT 24
Finished Jul 31 05:41:48 PM PDT 24
Peak memory 207000 kb
Host smart-502de19e-06f6-4559-bad8-5cb34569de81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39881
39466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3988139466
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.440454498
Short name T636
Test name
Test status
Simulation time 142636166 ps
CPU time 0.84 seconds
Started Jul 31 05:41:49 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 206984 kb
Host smart-7bf16513-9529-4f3f-ba6b-0978df7e5fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44045
4498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.440454498
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.104230224
Short name T218
Test name
Test status
Simulation time 183798376 ps
CPU time 0.9 seconds
Started Jul 31 05:41:49 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 206952 kb
Host smart-556b9273-7e01-4044-a0fb-ff8060d82ca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10423
0224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.104230224
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.264047768
Short name T919
Test name
Test status
Simulation time 170022398 ps
CPU time 0.89 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 206924 kb
Host smart-28c5c708-e729-4f5e-aff5-f89aacf7bbf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26404
7768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.264047768
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.405850970
Short name T2748
Test name
Test status
Simulation time 260157441 ps
CPU time 1.09 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 206984 kb
Host smart-f2811ad1-bd60-4c99-996e-3244d0d2690c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40585
0970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.405850970
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.1455496327
Short name T1659
Test name
Test status
Simulation time 5054443019 ps
CPU time 146.86 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:44:19 PM PDT 24
Peak memory 215452 kb
Host smart-c5e469ab-8d69-4495-84e0-8760a506a30f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1455496327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.1455496327
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.1852554092
Short name T290
Test name
Test status
Simulation time 178774002 ps
CPU time 0.89 seconds
Started Jul 31 05:41:51 PM PDT 24
Finished Jul 31 05:41:52 PM PDT 24
Peak memory 207040 kb
Host smart-b8d80ec0-90a9-4a89-9ada-37f48b5da4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18525
54092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.1852554092
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.3231914770
Short name T2103
Test name
Test status
Simulation time 208872554 ps
CPU time 0.87 seconds
Started Jul 31 05:41:54 PM PDT 24
Finished Jul 31 05:41:55 PM PDT 24
Peak memory 206996 kb
Host smart-e1334dde-ff01-4332-9e71-90677e522382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32319
14770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.3231914770
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3070680950
Short name T1581
Test name
Test status
Simulation time 1334572861 ps
CPU time 3.23 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:41:55 PM PDT 24
Peak memory 207048 kb
Host smart-6aed1951-2bf4-44c8-99b1-59271714efa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30706
80950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3070680950
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.1014176880
Short name T2310
Test name
Test status
Simulation time 4535657517 ps
CPU time 47.94 seconds
Started Jul 31 05:41:55 PM PDT 24
Finished Jul 31 05:42:44 PM PDT 24
Peak memory 207220 kb
Host smart-6e8bbaf2-0797-4932-8bf0-8c3e342559f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10141
76880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.1014176880
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.1353384892
Short name T1178
Test name
Test status
Simulation time 741746755 ps
CPU time 15.87 seconds
Started Jul 31 05:41:38 PM PDT 24
Finished Jul 31 05:41:54 PM PDT 24
Peak memory 207068 kb
Host smart-f53c390e-5826-4d4b-85a7-f07fff33f8fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353384892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.1353384892
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.263034843
Short name T701
Test name
Test status
Simulation time 40971775 ps
CPU time 0.66 seconds
Started Jul 31 05:42:05 PM PDT 24
Finished Jul 31 05:42:05 PM PDT 24
Peak memory 207020 kb
Host smart-c367cf5b-2e91-45c7-bcf3-fe5eec6ac197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=263034843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.263034843
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3738700981
Short name T9
Test name
Test status
Simulation time 4103097998 ps
CPU time 6.29 seconds
Started Jul 31 05:41:51 PM PDT 24
Finished Jul 31 05:41:58 PM PDT 24
Peak memory 207136 kb
Host smart-f7778d89-6243-4ac9-be62-11489c54e6e8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738700981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.3738700981
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.2131525922
Short name T938
Test name
Test status
Simulation time 13344834962 ps
CPU time 16.39 seconds
Started Jul 31 05:41:51 PM PDT 24
Finished Jul 31 05:42:07 PM PDT 24
Peak memory 207220 kb
Host smart-78b18420-3229-4ba9-a88e-281452495ae2
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131525922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.2131525922
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.4181709537
Short name T662
Test name
Test status
Simulation time 23344017953 ps
CPU time 28.56 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 207188 kb
Host smart-d4dc4701-bac0-4f2c-9a58-c2beded65634
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181709537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.4181709537
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.2862042060
Short name T939
Test name
Test status
Simulation time 163351570 ps
CPU time 0.82 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 206988 kb
Host smart-10326b0c-35cc-4bb5-9afb-f3e55e2ba170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28620
42060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.2862042060
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2362971344
Short name T2073
Test name
Test status
Simulation time 190361742 ps
CPU time 0.91 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 206928 kb
Host smart-62a65150-dec0-4d8d-801c-f130b4dbe15b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23629
71344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2362971344
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.679743186
Short name T2709
Test name
Test status
Simulation time 243989457 ps
CPU time 1.12 seconds
Started Jul 31 05:41:54 PM PDT 24
Finished Jul 31 05:41:56 PM PDT 24
Peak memory 206992 kb
Host smart-de64e589-9f35-4dcf-b141-bf3acabf06c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67974
3186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.679743186
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2059962121
Short name T2572
Test name
Test status
Simulation time 1049460502 ps
CPU time 3.08 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:41:55 PM PDT 24
Peak memory 207120 kb
Host smart-049a05eb-3a58-4e39-8a11-95f583ff659b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2059962121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2059962121
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.4065809030
Short name T2848
Test name
Test status
Simulation time 10822730584 ps
CPU time 24.61 seconds
Started Jul 31 05:41:53 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 207220 kb
Host smart-ee5ca4e0-710c-424c-950c-9abf076bc832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40658
09030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.4065809030
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_device_timeout.360836825
Short name T935
Test name
Test status
Simulation time 2878625854 ps
CPU time 19.48 seconds
Started Jul 31 05:41:54 PM PDT 24
Finished Jul 31 05:42:14 PM PDT 24
Peak memory 207236 kb
Host smart-b94150ed-9829-4a92-9156-c42e871c034a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360836825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.360836825
Directory /workspace/13.usbdev_device_timeout/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.383794994
Short name T2736
Test name
Test status
Simulation time 459502325 ps
CPU time 1.45 seconds
Started Jul 31 05:41:51 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 206972 kb
Host smart-040e84d0-e83c-454a-bb85-7f4856c8bac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38379
4994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.383794994
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3596537887
Short name T2086
Test name
Test status
Simulation time 198693937 ps
CPU time 0.86 seconds
Started Jul 31 05:41:51 PM PDT 24
Finished Jul 31 05:41:52 PM PDT 24
Peak memory 206940 kb
Host smart-96b5fc38-e6d1-4e75-b6e1-b35228235b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
37887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3596537887
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.4072059658
Short name T2598
Test name
Test status
Simulation time 57406042 ps
CPU time 0.73 seconds
Started Jul 31 05:41:51 PM PDT 24
Finished Jul 31 05:41:52 PM PDT 24
Peak memory 206948 kb
Host smart-ea8c7acd-e451-46e6-8823-10c6090f7e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40720
59658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.4072059658
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.1257643044
Short name T2318
Test name
Test status
Simulation time 963866788 ps
CPU time 2.49 seconds
Started Jul 31 05:41:52 PM PDT 24
Finished Jul 31 05:41:54 PM PDT 24
Peak memory 207048 kb
Host smart-2b253b57-f2af-4618-a242-fe023c8a3a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12576
43044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.1257643044
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.4208574683
Short name T1474
Test name
Test status
Simulation time 281898926 ps
CPU time 2.32 seconds
Started Jul 31 05:41:50 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 207044 kb
Host smart-ff741603-675b-430d-8dd4-b8a408f004b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42085
74683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.4208574683
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.2618917457
Short name T311
Test name
Test status
Simulation time 203226194 ps
CPU time 1.1 seconds
Started Jul 31 05:41:51 PM PDT 24
Finished Jul 31 05:41:52 PM PDT 24
Peak memory 207104 kb
Host smart-46e78fd8-d984-4af2-b8e0-05f05f2a89b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2618917457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.2618917457
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.1128536905
Short name T573
Test name
Test status
Simulation time 142915482 ps
CPU time 0.84 seconds
Started Jul 31 05:41:57 PM PDT 24
Finished Jul 31 05:41:58 PM PDT 24
Peak memory 206952 kb
Host smart-2d5d8974-845c-4d03-b8cd-f8be1f0683af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11285
36905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.1128536905
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1771816934
Short name T623
Test name
Test status
Simulation time 242941385 ps
CPU time 1.01 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 207020 kb
Host smart-2f8176b1-7e0c-4556-8c23-b7dc9db06c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17718
16934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1771816934
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.44651351
Short name T659
Test name
Test status
Simulation time 10685247500 ps
CPU time 82.09 seconds
Started Jul 31 05:41:53 PM PDT 24
Finished Jul 31 05:43:15 PM PDT 24
Peak memory 216760 kb
Host smart-59274b1c-95f7-448a-a9ee-f24fe47feb87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=44651351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.44651351
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.4253695816
Short name T1771
Test name
Test status
Simulation time 13947064143 ps
CPU time 90.68 seconds
Started Jul 31 05:41:56 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 207144 kb
Host smart-64ec475b-8993-4455-851f-5efc53a432a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4253695816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.4253695816
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.4023121825
Short name T2765
Test name
Test status
Simulation time 193086614 ps
CPU time 0.97 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 206988 kb
Host smart-1c92b38b-c3e5-4678-ac2f-bb5fbde51bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40231
21825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.4023121825
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2243635747
Short name T388
Test name
Test status
Simulation time 23288236851 ps
CPU time 26.66 seconds
Started Jul 31 05:41:57 PM PDT 24
Finished Jul 31 05:42:24 PM PDT 24
Peak memory 207216 kb
Host smart-ec22031e-5b7b-456a-a34a-3a31afcafbe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22436
35747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2243635747
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2023181653
Short name T1925
Test name
Test status
Simulation time 3269085662 ps
CPU time 5.33 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:42:03 PM PDT 24
Peak memory 207128 kb
Host smart-acd03f4e-e6e0-47ac-b43d-fc43048376c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20231
81653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2023181653
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2288707138
Short name T1955
Test name
Test status
Simulation time 7289205966 ps
CPU time 215.03 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:45:33 PM PDT 24
Peak memory 215408 kb
Host smart-13229f5c-fb7d-4b8d-bc00-7bde862932b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22887
07138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2288707138
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1646250568
Short name T1283
Test name
Test status
Simulation time 3482839943 ps
CPU time 36.19 seconds
Started Jul 31 05:41:57 PM PDT 24
Finished Jul 31 05:42:33 PM PDT 24
Peak memory 215416 kb
Host smart-cc5e51ff-d6c8-4708-861b-7c728950b8cb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1646250568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1646250568
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.47044669
Short name T1010
Test name
Test status
Simulation time 256046130 ps
CPU time 1.03 seconds
Started Jul 31 05:42:00 PM PDT 24
Finished Jul 31 05:42:01 PM PDT 24
Peak memory 206992 kb
Host smart-72d9e6d6-e9cc-4a5a-aae6-bd21fa29a83c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=47044669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.47044669
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1265496168
Short name T2242
Test name
Test status
Simulation time 186702035 ps
CPU time 0.91 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 206972 kb
Host smart-79a6da60-18f3-4e9b-a0c6-52ead638592d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12654
96168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1265496168
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.1560125061
Short name T652
Test name
Test status
Simulation time 4779223980 ps
CPU time 48.6 seconds
Started Jul 31 05:42:00 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 217000 kb
Host smart-1501c2e8-1d8f-421c-aee5-dda2176cc0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15601
25061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.1560125061
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3533211419
Short name T655
Test name
Test status
Simulation time 4273228403 ps
CPU time 32.54 seconds
Started Jul 31 05:41:56 PM PDT 24
Finished Jul 31 05:42:28 PM PDT 24
Peak memory 207212 kb
Host smart-c6ee29fc-71b4-44c1-af7a-0a67a0ec7870
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3533211419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3533211419
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2467235024
Short name T1968
Test name
Test status
Simulation time 148745712 ps
CPU time 0.85 seconds
Started Jul 31 05:41:57 PM PDT 24
Finished Jul 31 05:41:58 PM PDT 24
Peak memory 206996 kb
Host smart-35c1d7a4-b5d1-442f-8fcd-36f2b9593ef2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2467235024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2467235024
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.1148655779
Short name T420
Test name
Test status
Simulation time 179141458 ps
CPU time 0.94 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 206976 kb
Host smart-3d6f87e8-e77d-493d-938f-4e29f2d13571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11486
55779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.1148655779
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1163057355
Short name T1763
Test name
Test status
Simulation time 154208697 ps
CPU time 0.89 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 207016 kb
Host smart-97707393-16cd-43e1-b438-827a3400b3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11630
57355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1163057355
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.1106806589
Short name T2694
Test name
Test status
Simulation time 180872817 ps
CPU time 0.87 seconds
Started Jul 31 05:41:56 PM PDT 24
Finished Jul 31 05:41:57 PM PDT 24
Peak memory 207000 kb
Host smart-50fec1bf-d55b-4725-91eb-c18905e923f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11068
06589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1106806589
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.90738708
Short name T2733
Test name
Test status
Simulation time 234712413 ps
CPU time 1.01 seconds
Started Jul 31 05:41:57 PM PDT 24
Finished Jul 31 05:41:58 PM PDT 24
Peak memory 206984 kb
Host smart-fd00ef2f-587b-4300-b64c-cc800070cda3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90738
708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.90738708
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.856045061
Short name T1205
Test name
Test status
Simulation time 163215058 ps
CPU time 0.84 seconds
Started Jul 31 05:41:56 PM PDT 24
Finished Jul 31 05:41:57 PM PDT 24
Peak memory 206952 kb
Host smart-6cc9bdcd-5ca9-4148-8e6f-d8da2fdaaa2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85604
5061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.856045061
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3767887585
Short name T2850
Test name
Test status
Simulation time 217276823 ps
CPU time 1.03 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:42:00 PM PDT 24
Peak memory 207024 kb
Host smart-0b5e7af6-5bbf-4ceb-aed3-631f71460d69
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3767887585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3767887585
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.93287170
Short name T515
Test name
Test status
Simulation time 168891292 ps
CPU time 0.84 seconds
Started Jul 31 05:41:55 PM PDT 24
Finished Jul 31 05:41:56 PM PDT 24
Peak memory 206956 kb
Host smart-9f59d02a-bdae-4f61-b122-4dcfa82d03fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93287
170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.93287170
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.439336406
Short name T1918
Test name
Test status
Simulation time 42036540 ps
CPU time 0.7 seconds
Started Jul 31 05:41:59 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 206944 kb
Host smart-ebb904cf-0203-4119-a7a6-dff250ac7b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43933
6406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.439336406
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.2946657043
Short name T1446
Test name
Test status
Simulation time 11970824785 ps
CPU time 32.03 seconds
Started Jul 31 05:41:57 PM PDT 24
Finished Jul 31 05:42:29 PM PDT 24
Peak memory 215460 kb
Host smart-cefd2e0d-1e7f-4d6f-a704-d811299b0749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29466
57043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.2946657043
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3662693573
Short name T2497
Test name
Test status
Simulation time 179354132 ps
CPU time 0.94 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 207004 kb
Host smart-4e075d9f-0fc7-4534-ae26-a8adb9720d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36626
93573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3662693573
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.3223069806
Short name T2512
Test name
Test status
Simulation time 224522338 ps
CPU time 1.08 seconds
Started Jul 31 05:41:58 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 206964 kb
Host smart-6ab83e7f-b2db-48e3-b9d2-96324fd3af55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32230
69806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.3223069806
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.248007786
Short name T1013
Test name
Test status
Simulation time 226933029 ps
CPU time 0.98 seconds
Started Jul 31 05:42:03 PM PDT 24
Finished Jul 31 05:42:04 PM PDT 24
Peak memory 206992 kb
Host smart-9a8b9114-6580-429f-ac46-349c631ae792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24800
7786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.248007786
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1033411573
Short name T1132
Test name
Test status
Simulation time 169326365 ps
CPU time 0.92 seconds
Started Jul 31 05:42:05 PM PDT 24
Finished Jul 31 05:42:06 PM PDT 24
Peak memory 206988 kb
Host smart-49ade7de-c3f9-46a3-81ea-1d812051f15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10334
11573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1033411573
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2509010029
Short name T67
Test name
Test status
Simulation time 198476980 ps
CPU time 0.96 seconds
Started Jul 31 05:42:03 PM PDT 24
Finished Jul 31 05:42:04 PM PDT 24
Peak memory 207024 kb
Host smart-dd5dd00d-e537-4386-88cc-1454281f3d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25090
10029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2509010029
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1290468568
Short name T1153
Test name
Test status
Simulation time 164896962 ps
CPU time 0.87 seconds
Started Jul 31 05:42:06 PM PDT 24
Finished Jul 31 05:42:07 PM PDT 24
Peak memory 206960 kb
Host smart-da1404a8-ac75-45dd-b9fb-9ae19c366df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12904
68568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1290468568
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_smoke.240315980
Short name T1876
Test name
Test status
Simulation time 217967357 ps
CPU time 1.02 seconds
Started Jul 31 05:42:00 PM PDT 24
Finished Jul 31 05:42:01 PM PDT 24
Peak memory 206984 kb
Host smart-4b04330f-5bcb-4c55-9c25-aed57c70f3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24031
5980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.240315980
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2002544010
Short name T2199
Test name
Test status
Simulation time 3792939342 ps
CPU time 31.1 seconds
Started Jul 31 05:42:00 PM PDT 24
Finished Jul 31 05:42:31 PM PDT 24
Peak memory 215424 kb
Host smart-8939f798-e77a-4166-bfce-10d610d300bd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2002544010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2002544010
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1188907572
Short name T583
Test name
Test status
Simulation time 255254706 ps
CPU time 1.04 seconds
Started Jul 31 05:42:03 PM PDT 24
Finished Jul 31 05:42:04 PM PDT 24
Peak memory 207024 kb
Host smart-47b0ea59-db7f-4730-94de-948daa1a33e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11889
07572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1188907572
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.3004310137
Short name T409
Test name
Test status
Simulation time 189915003 ps
CPU time 0.96 seconds
Started Jul 31 05:42:01 PM PDT 24
Finished Jul 31 05:42:02 PM PDT 24
Peak memory 206924 kb
Host smart-ccedf48b-9ac8-4a9d-b0c5-1083a3c64f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30043
10137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.3004310137
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.2857809592
Short name T2860
Test name
Test status
Simulation time 1018230457 ps
CPU time 2.49 seconds
Started Jul 31 05:42:01 PM PDT 24
Finished Jul 31 05:42:04 PM PDT 24
Peak memory 207120 kb
Host smart-ff05c7de-5308-4f71-9352-1ce0a5fa604d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28578
09592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2857809592
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3146372805
Short name T885
Test name
Test status
Simulation time 6736328622 ps
CPU time 67.67 seconds
Started Jul 31 05:42:04 PM PDT 24
Finished Jul 31 05:43:12 PM PDT 24
Peak memory 207220 kb
Host smart-d025797e-3685-4860-a13f-fe8b934f7662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31463
72805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3146372805
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.1167176722
Short name T2459
Test name
Test status
Simulation time 4951951615 ps
CPU time 34.32 seconds
Started Jul 31 05:41:51 PM PDT 24
Finished Jul 31 05:42:26 PM PDT 24
Peak memory 207232 kb
Host smart-ee8dcea5-62f9-4423-998b-792be66af2dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167176722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.1167176722
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2100387932
Short name T367
Test name
Test status
Simulation time 122784514 ps
CPU time 0.72 seconds
Started Jul 31 05:42:11 PM PDT 24
Finished Jul 31 05:42:12 PM PDT 24
Peak memory 206996 kb
Host smart-8e38897a-d8cc-4e9d-9ceb-6165718432fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2100387932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2100387932
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3103906493
Short name T1316
Test name
Test status
Simulation time 3937580722 ps
CPU time 5.33 seconds
Started Jul 31 05:42:06 PM PDT 24
Finished Jul 31 05:42:12 PM PDT 24
Peak memory 207132 kb
Host smart-62209fac-ced7-4f1b-b175-a35592261dfe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103906493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.3103906493
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3957593477
Short name T1037
Test name
Test status
Simulation time 13375268592 ps
CPU time 14.53 seconds
Started Jul 31 05:42:01 PM PDT 24
Finished Jul 31 05:42:16 PM PDT 24
Peak memory 207240 kb
Host smart-6b7d398c-95ef-4d43-ab77-281da59bd909
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957593477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3957593477
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1732296593
Short name T1476
Test name
Test status
Simulation time 23384706117 ps
CPU time 30.37 seconds
Started Jul 31 05:42:02 PM PDT 24
Finished Jul 31 05:42:32 PM PDT 24
Peak memory 207164 kb
Host smart-fc04d02f-a4ac-4c35-b7c3-9fa909af0bbe
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732296593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_resume.1732296593
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1861058642
Short name T1491
Test name
Test status
Simulation time 156184331 ps
CPU time 0.89 seconds
Started Jul 31 05:42:00 PM PDT 24
Finished Jul 31 05:42:01 PM PDT 24
Peak memory 207036 kb
Host smart-925c7b43-98b4-425c-9053-38cbe7e26597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18610
58642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1861058642
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3253780094
Short name T1951
Test name
Test status
Simulation time 155778484 ps
CPU time 1.02 seconds
Started Jul 31 05:42:01 PM PDT 24
Finished Jul 31 05:42:02 PM PDT 24
Peak memory 206948 kb
Host smart-4f1a31a7-d263-4d6d-a372-b10493a6e635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32537
80094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3253780094
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3448863160
Short name T720
Test name
Test status
Simulation time 477548622 ps
CPU time 1.77 seconds
Started Jul 31 05:42:01 PM PDT 24
Finished Jul 31 05:42:03 PM PDT 24
Peak memory 206984 kb
Host smart-8e5f4b9c-64dd-4b2b-84f1-17aa20740b76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
63160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3448863160
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.182026692
Short name T1614
Test name
Test status
Simulation time 425231059 ps
CPU time 1.32 seconds
Started Jul 31 05:42:05 PM PDT 24
Finished Jul 31 05:42:07 PM PDT 24
Peak memory 207000 kb
Host smart-7f9ed700-699c-491f-95b1-e12e785f60a3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=182026692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.182026692
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1790262610
Short name T1736
Test name
Test status
Simulation time 18922179682 ps
CPU time 38.38 seconds
Started Jul 31 05:42:02 PM PDT 24
Finished Jul 31 05:42:40 PM PDT 24
Peak memory 207160 kb
Host smart-769cdf9d-238d-4758-b804-463fd717f563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17902
62610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1790262610
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_device_timeout.2469348308
Short name T1167
Test name
Test status
Simulation time 424313428 ps
CPU time 8.01 seconds
Started Jul 31 05:42:06 PM PDT 24
Finished Jul 31 05:42:14 PM PDT 24
Peak memory 207116 kb
Host smart-06fdb9f9-6e3f-4ce5-929f-4eb87c1b0fcd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469348308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.2469348308
Directory /workspace/14.usbdev_device_timeout/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.3768344830
Short name T792
Test name
Test status
Simulation time 483392988 ps
CPU time 1.66 seconds
Started Jul 31 05:42:03 PM PDT 24
Finished Jul 31 05:42:05 PM PDT 24
Peak memory 206964 kb
Host smart-00232abe-e7b0-4d2c-82cb-eb923497315d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37683
44830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.3768344830
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2602467866
Short name T591
Test name
Test status
Simulation time 134980914 ps
CPU time 0.8 seconds
Started Jul 31 05:42:04 PM PDT 24
Finished Jul 31 05:42:05 PM PDT 24
Peak memory 206960 kb
Host smart-3792a3b2-8a7a-4398-bb45-2f76f606404b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26024
67866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2602467866
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3665997362
Short name T1582
Test name
Test status
Simulation time 40883948 ps
CPU time 0.68 seconds
Started Jul 31 05:42:06 PM PDT 24
Finished Jul 31 05:42:07 PM PDT 24
Peak memory 206956 kb
Host smart-28fcae9f-c455-4bfb-985e-2e185dd9909e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36659
97362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3665997362
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.1750980791
Short name T562
Test name
Test status
Simulation time 793302792 ps
CPU time 2.1 seconds
Started Jul 31 05:42:06 PM PDT 24
Finished Jul 31 05:42:08 PM PDT 24
Peak memory 207076 kb
Host smart-e525b122-d39f-4453-9d53-f17d2a14e895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17509
80791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.1750980791
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1596415304
Short name T1431
Test name
Test status
Simulation time 210131326 ps
CPU time 1.32 seconds
Started Jul 31 05:42:06 PM PDT 24
Finished Jul 31 05:42:08 PM PDT 24
Peak memory 207096 kb
Host smart-56e23591-dc03-4ff8-bc43-3caf6dc1079f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15964
15304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1596415304
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3346543294
Short name T1447
Test name
Test status
Simulation time 292615010 ps
CPU time 1.29 seconds
Started Jul 31 05:42:08 PM PDT 24
Finished Jul 31 05:42:09 PM PDT 24
Peak memory 215284 kb
Host smart-7cd23253-9af5-4dcc-a3e3-138f489f76b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3346543294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3346543294
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3346304384
Short name T1101
Test name
Test status
Simulation time 141598067 ps
CPU time 0.83 seconds
Started Jul 31 05:42:06 PM PDT 24
Finished Jul 31 05:42:07 PM PDT 24
Peak memory 206968 kb
Host smart-47a13219-7c8a-4b72-a97f-01f3a6749017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33463
04384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3346304384
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.418385418
Short name T1300
Test name
Test status
Simulation time 163518260 ps
CPU time 0.87 seconds
Started Jul 31 05:42:08 PM PDT 24
Finished Jul 31 05:42:09 PM PDT 24
Peak memory 206992 kb
Host smart-fb53dca9-77e2-4101-9055-8d4bafedb449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41838
5418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.418385418
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.2170447660
Short name T1376
Test name
Test status
Simulation time 8693239198 ps
CPU time 238.09 seconds
Started Jul 31 05:42:08 PM PDT 24
Finished Jul 31 05:46:07 PM PDT 24
Peak memory 215408 kb
Host smart-7ca8b582-e1b2-4b84-89c1-ae8f2535ed7f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2170447660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.2170447660
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.1261960797
Short name T814
Test name
Test status
Simulation time 5791905701 ps
CPU time 68.51 seconds
Started Jul 31 05:42:07 PM PDT 24
Finished Jul 31 05:43:16 PM PDT 24
Peak memory 207156 kb
Host smart-312a203b-bba4-4d0d-93bb-259b4bf5fc7c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1261960797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.1261960797
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.941850742
Short name T813
Test name
Test status
Simulation time 199459406 ps
CPU time 0.95 seconds
Started Jul 31 05:42:11 PM PDT 24
Finished Jul 31 05:42:12 PM PDT 24
Peak memory 206988 kb
Host smart-d74e542a-5d88-42b0-9108-53bb2c43831f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94185
0742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.941850742
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.81470972
Short name T179
Test name
Test status
Simulation time 23358699967 ps
CPU time 27.39 seconds
Started Jul 31 05:42:09 PM PDT 24
Finished Jul 31 05:42:36 PM PDT 24
Peak memory 207220 kb
Host smart-7c09707c-af63-41a3-8012-59b56ad33e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81470
972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.81470972
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1978660575
Short name T1934
Test name
Test status
Simulation time 3284582202 ps
CPU time 4.95 seconds
Started Jul 31 05:42:09 PM PDT 24
Finished Jul 31 05:42:14 PM PDT 24
Peak memory 207124 kb
Host smart-5b51ec74-c846-47ca-9592-b86026d389c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19786
60575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1978660575
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.150619480
Short name T2071
Test name
Test status
Simulation time 7528232450 ps
CPU time 73.78 seconds
Started Jul 31 05:42:10 PM PDT 24
Finished Jul 31 05:43:23 PM PDT 24
Peak memory 217244 kb
Host smart-6e313e9f-7659-4b85-990a-1a3c4bba103d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15061
9480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.150619480
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2436437881
Short name T1290
Test name
Test status
Simulation time 5087657097 ps
CPU time 52.3 seconds
Started Jul 31 05:42:11 PM PDT 24
Finished Jul 31 05:43:04 PM PDT 24
Peak memory 216708 kb
Host smart-5c829f96-adbb-4e20-ae4a-5bc667dcbd00
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2436437881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2436437881
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2024844421
Short name T877
Test name
Test status
Simulation time 255788706 ps
CPU time 1.07 seconds
Started Jul 31 05:42:10 PM PDT 24
Finished Jul 31 05:42:11 PM PDT 24
Peak memory 206992 kb
Host smart-9fe2a1e8-5808-4850-aa7c-73a192cafb22
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2024844421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2024844421
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4263584660
Short name T2492
Test name
Test status
Simulation time 274672668 ps
CPU time 1.04 seconds
Started Jul 31 05:42:08 PM PDT 24
Finished Jul 31 05:42:09 PM PDT 24
Peak memory 206984 kb
Host smart-4c0a72cf-4f6b-4f38-a320-1eb8a5b79ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42635
84660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4263584660
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.4258345741
Short name T2777
Test name
Test status
Simulation time 4087768474 ps
CPU time 41.84 seconds
Started Jul 31 05:42:11 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 216732 kb
Host smart-7025099a-625c-4a80-ad2d-04ee3857fd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42583
45741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.4258345741
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.4285099592
Short name T974
Test name
Test status
Simulation time 7015625624 ps
CPU time 54.62 seconds
Started Jul 31 05:42:08 PM PDT 24
Finished Jul 31 05:43:03 PM PDT 24
Peak memory 207232 kb
Host smart-d9503f1f-2aad-45b7-be25-8c16858e1092
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4285099592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.4285099592
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2759784404
Short name T921
Test name
Test status
Simulation time 159133161 ps
CPU time 0.84 seconds
Started Jul 31 05:42:10 PM PDT 24
Finished Jul 31 05:42:11 PM PDT 24
Peak memory 206972 kb
Host smart-13b23fbd-61e7-4de3-8df7-c09c1ba20c60
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2759784404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2759784404
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2958093331
Short name T1429
Test name
Test status
Simulation time 156109221 ps
CPU time 0.91 seconds
Started Jul 31 05:42:05 PM PDT 24
Finished Jul 31 05:42:06 PM PDT 24
Peak memory 206984 kb
Host smart-a69e6870-4eca-4a48-aae5-7f6a2dd4d939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29580
93331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2958093331
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1365205358
Short name T18
Test name
Test status
Simulation time 206618725 ps
CPU time 0.91 seconds
Started Jul 31 05:42:08 PM PDT 24
Finished Jul 31 05:42:09 PM PDT 24
Peak memory 207000 kb
Host smart-8d1b255b-1502-4b51-aeee-1d1e0b6b10ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13652
05358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1365205358
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.86376025
Short name T1331
Test name
Test status
Simulation time 209464896 ps
CPU time 0.91 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 207000 kb
Host smart-98f90dc2-19ec-40e0-8883-99a70066c8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86376
025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.86376025
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1582994476
Short name T1533
Test name
Test status
Simulation time 197268084 ps
CPU time 0.93 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 207000 kb
Host smart-1446bc85-1f6e-49db-a1fe-ecc37e36649d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15829
94476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1582994476
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.536369990
Short name T1528
Test name
Test status
Simulation time 247288285 ps
CPU time 0.96 seconds
Started Jul 31 05:42:14 PM PDT 24
Finished Jul 31 05:42:15 PM PDT 24
Peak memory 206920 kb
Host smart-30b2e68f-04a6-4064-8c75-f1fbed75a743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53636
9990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.536369990
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.1526272867
Short name T156
Test name
Test status
Simulation time 164151265 ps
CPU time 0.9 seconds
Started Jul 31 05:42:12 PM PDT 24
Finished Jul 31 05:42:13 PM PDT 24
Peak memory 206972 kb
Host smart-87828ede-5964-4ab3-aeb9-d676ab0b06d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15262
72867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.1526272867
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.338069272
Short name T1714
Test name
Test status
Simulation time 233725371 ps
CPU time 1.07 seconds
Started Jul 31 05:42:11 PM PDT 24
Finished Jul 31 05:42:12 PM PDT 24
Peak memory 206980 kb
Host smart-1edb78a3-0681-473d-923e-2c6019434580
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=338069272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.338069272
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3195917370
Short name T181
Test name
Test status
Simulation time 144861286 ps
CPU time 0.81 seconds
Started Jul 31 05:42:15 PM PDT 24
Finished Jul 31 05:42:16 PM PDT 24
Peak memory 206976 kb
Host smart-5d61b103-0eb0-48fc-a2c4-3e007eaf8a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31959
17370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3195917370
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2278386332
Short name T34
Test name
Test status
Simulation time 33468865 ps
CPU time 0.68 seconds
Started Jul 31 05:42:15 PM PDT 24
Finished Jul 31 05:42:15 PM PDT 24
Peak memory 206956 kb
Host smart-0e2e0851-efe2-492f-8c43-69ad692a76f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22783
86332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2278386332
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.725646593
Short name T2484
Test name
Test status
Simulation time 21981720409 ps
CPU time 56.96 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:43:15 PM PDT 24
Peak memory 215436 kb
Host smart-02ed2a6e-a989-425c-bbe4-b6af047a76e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72564
6593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.725646593
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2707132115
Short name T639
Test name
Test status
Simulation time 173839142 ps
CPU time 0.89 seconds
Started Jul 31 05:42:17 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 206984 kb
Host smart-05c0f25a-69ef-4490-8e29-79ab7ac624c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27071
32115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2707132115
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.4119531587
Short name T1183
Test name
Test status
Simulation time 183043320 ps
CPU time 0.91 seconds
Started Jul 31 05:42:14 PM PDT 24
Finished Jul 31 05:42:15 PM PDT 24
Peak memory 206976 kb
Host smart-753287e4-7cb8-4247-9ac8-1ca5a9f15449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41195
31587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.4119531587
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3264557372
Short name T1062
Test name
Test status
Simulation time 186710049 ps
CPU time 0.9 seconds
Started Jul 31 05:42:13 PM PDT 24
Finished Jul 31 05:42:14 PM PDT 24
Peak memory 206996 kb
Host smart-7d98fda2-67e6-425c-81d6-d1496171fec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32645
57372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3264557372
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.4291980996
Short name T1049
Test name
Test status
Simulation time 221509159 ps
CPU time 0.94 seconds
Started Jul 31 05:42:13 PM PDT 24
Finished Jul 31 05:42:14 PM PDT 24
Peak memory 206980 kb
Host smart-b98b93ee-779d-4920-a249-1ecba45f6c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42919
80996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.4291980996
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.978735071
Short name T1735
Test name
Test status
Simulation time 185118195 ps
CPU time 0.89 seconds
Started Jul 31 05:42:14 PM PDT 24
Finished Jul 31 05:42:15 PM PDT 24
Peak memory 206920 kb
Host smart-b058ca64-77eb-4c22-880e-cf592cf37f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97873
5071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.978735071
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.195916545
Short name T1148
Test name
Test status
Simulation time 151808415 ps
CPU time 0.82 seconds
Started Jul 31 05:42:12 PM PDT 24
Finished Jul 31 05:42:13 PM PDT 24
Peak memory 206952 kb
Host smart-b279ab25-1fb6-4f9f-af25-f9f24774320c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19591
6545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.195916545
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3230698138
Short name T2411
Test name
Test status
Simulation time 149064875 ps
CPU time 0.84 seconds
Started Jul 31 05:42:13 PM PDT 24
Finished Jul 31 05:42:14 PM PDT 24
Peak memory 206972 kb
Host smart-8667d269-220d-496a-9a39-e825f323efc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32306
98138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3230698138
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.2145752916
Short name T1588
Test name
Test status
Simulation time 220508139 ps
CPU time 0.99 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 206996 kb
Host smart-a0855c3d-987b-4f1d-82ab-8363659e8b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21457
52916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.2145752916
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3423250646
Short name T1666
Test name
Test status
Simulation time 3192235666 ps
CPU time 31.03 seconds
Started Jul 31 05:42:14 PM PDT 24
Finished Jul 31 05:42:45 PM PDT 24
Peak memory 215364 kb
Host smart-8bf63b27-69c4-4b14-99d4-ea39b1796e15
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3423250646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3423250646
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.239328738
Short name T2035
Test name
Test status
Simulation time 154456601 ps
CPU time 0.87 seconds
Started Jul 31 05:42:13 PM PDT 24
Finished Jul 31 05:42:14 PM PDT 24
Peak memory 206980 kb
Host smart-56615b9b-4569-4a46-9ab6-72ad1e1fdd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23932
8738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.239328738
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3679092214
Short name T2690
Test name
Test status
Simulation time 206829056 ps
CPU time 0.93 seconds
Started Jul 31 05:42:13 PM PDT 24
Finished Jul 31 05:42:14 PM PDT 24
Peak memory 206976 kb
Host smart-49b9ee42-7fe4-4f00-9af9-0fea0da4ee42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36790
92214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3679092214
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.3379761879
Short name T2605
Test name
Test status
Simulation time 806359440 ps
CPU time 2.17 seconds
Started Jul 31 05:42:16 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 206956 kb
Host smart-1fb7a597-997e-4596-affa-7b317909fb6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33797
61879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.3379761879
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3789693487
Short name T899
Test name
Test status
Simulation time 5574392970 ps
CPU time 165.03 seconds
Started Jul 31 05:42:15 PM PDT 24
Finished Jul 31 05:45:00 PM PDT 24
Peak memory 215376 kb
Host smart-49e13afe-ee9c-472d-9904-fb75fbe656c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37896
93487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3789693487
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.1641772373
Short name T2012
Test name
Test status
Simulation time 3775206985 ps
CPU time 26.19 seconds
Started Jul 31 05:42:01 PM PDT 24
Finished Jul 31 05:42:28 PM PDT 24
Peak memory 207212 kb
Host smart-d93ca14d-555b-4f3f-aee1-c4e00c7f7cb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641772373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos
t_handshake.1641772373
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2860387565
Short name T795
Test name
Test status
Simulation time 31495596 ps
CPU time 0.69 seconds
Started Jul 31 05:42:25 PM PDT 24
Finished Jul 31 05:42:26 PM PDT 24
Peak memory 207032 kb
Host smart-b97116e0-674f-4694-af4a-a3513b9ec19c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2860387565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2860387565
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.4076199427
Short name T854
Test name
Test status
Simulation time 13344056975 ps
CPU time 15.82 seconds
Started Jul 31 05:42:12 PM PDT 24
Finished Jul 31 05:42:28 PM PDT 24
Peak memory 207208 kb
Host smart-cb98b63d-7c40-407d-b436-99392fb8c745
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076199427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.4076199427
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2883665312
Short name T1607
Test name
Test status
Simulation time 23385326924 ps
CPU time 28.56 seconds
Started Jul 31 05:42:11 PM PDT 24
Finished Jul 31 05:42:40 PM PDT 24
Peak memory 207188 kb
Host smart-a2f62ec8-e698-4bdc-9716-dfb21e31d201
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883665312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2883665312
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.636060119
Short name T85
Test name
Test status
Simulation time 148533503 ps
CPU time 0.85 seconds
Started Jul 31 05:42:14 PM PDT 24
Finished Jul 31 05:42:15 PM PDT 24
Peak memory 206992 kb
Host smart-f5f19af3-124c-488b-a376-7016bd2bf3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63606
0119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.636060119
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3382175124
Short name T1987
Test name
Test status
Simulation time 144739722 ps
CPU time 0.84 seconds
Started Jul 31 05:42:16 PM PDT 24
Finished Jul 31 05:42:17 PM PDT 24
Peak memory 206948 kb
Host smart-a114e1f3-d516-4cb2-b2e1-6ae2afea8d26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33821
75124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3382175124
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.3466719865
Short name T1578
Test name
Test status
Simulation time 447603640 ps
CPU time 1.52 seconds
Started Jul 31 05:42:17 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 207000 kb
Host smart-523ca48d-b771-4670-b168-f24ebe2030e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34667
19865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.3466719865
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2276213755
Short name T1350
Test name
Test status
Simulation time 1235088088 ps
CPU time 3.26 seconds
Started Jul 31 05:42:13 PM PDT 24
Finished Jul 31 05:42:16 PM PDT 24
Peak memory 207116 kb
Host smart-eeb917a0-ac9d-4b99-aa43-03e380709280
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2276213755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2276213755
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2634572907
Short name T2804
Test name
Test status
Simulation time 17922310416 ps
CPU time 39.57 seconds
Started Jul 31 05:42:11 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 207216 kb
Host smart-d3026f9e-49de-46f2-9667-624f2aa882b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26345
72907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2634572907
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.3447617337
Short name T957
Test name
Test status
Simulation time 4264334492 ps
CPU time 28.45 seconds
Started Jul 31 05:42:16 PM PDT 24
Finished Jul 31 05:42:45 PM PDT 24
Peak memory 207228 kb
Host smart-8bae88f6-c3c5-4f0e-8bf7-2ecd2d454f27
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447617337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.3447617337
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.36449448
Short name T2838
Test name
Test status
Simulation time 501251744 ps
CPU time 1.62 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 206940 kb
Host smart-f1de4f1f-0373-4f88-9480-18205deb18c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36449
448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.36449448
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1848867221
Short name T861
Test name
Test status
Simulation time 147265097 ps
CPU time 0.82 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 206956 kb
Host smart-dfcf646b-37f5-405a-a44d-10e4967c2faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18488
67221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1848867221
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.1741572068
Short name T1409
Test name
Test status
Simulation time 40912588 ps
CPU time 0.72 seconds
Started Jul 31 05:42:17 PM PDT 24
Finished Jul 31 05:42:17 PM PDT 24
Peak memory 206948 kb
Host smart-90bbddb1-3ebf-4f5f-b3c9-0f291ebd0233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17415
72068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.1741572068
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3327753850
Short name T1762
Test name
Test status
Simulation time 961190487 ps
CPU time 2.6 seconds
Started Jul 31 05:42:20 PM PDT 24
Finished Jul 31 05:42:22 PM PDT 24
Peak memory 207104 kb
Host smart-d10816da-262e-4b43-81cc-a3fcbcc11cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277
53850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3327753850
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.2395207241
Short name T2025
Test name
Test status
Simulation time 184830323 ps
CPU time 1.41 seconds
Started Jul 31 05:42:17 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 207040 kb
Host smart-60b3d440-daaf-4871-ac3f-28794d7a6d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952
07241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.2395207241
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.3932638503
Short name T2332
Test name
Test status
Simulation time 210167319 ps
CPU time 1.17 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 207112 kb
Host smart-6763d4c4-d0e0-4c30-9615-09342c147fb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3932638503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.3932638503
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2089834853
Short name T1546
Test name
Test status
Simulation time 143357185 ps
CPU time 0.81 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 206932 kb
Host smart-5ed69b42-5cba-4d30-8649-0750a7eab884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
34853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2089834853
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2643750708
Short name T1122
Test name
Test status
Simulation time 183201099 ps
CPU time 0.92 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 207004 kb
Host smart-574a71ec-13ab-4b80-994d-46a9e7bdeff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26437
50708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2643750708
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1867069999
Short name T849
Test name
Test status
Simulation time 5129440735 ps
CPU time 51.47 seconds
Started Jul 31 05:42:23 PM PDT 24
Finished Jul 31 05:43:15 PM PDT 24
Peak memory 215396 kb
Host smart-74b0da09-3727-43b1-909e-673eefa5c113
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1867069999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1867069999
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.3222206477
Short name T1717
Test name
Test status
Simulation time 8215720953 ps
CPU time 60.77 seconds
Started Jul 31 05:42:20 PM PDT 24
Finished Jul 31 05:43:21 PM PDT 24
Peak memory 207208 kb
Host smart-ef0d17bd-2cc9-4ea5-9598-20a942566c29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3222206477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.3222206477
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.4000794847
Short name T2645
Test name
Test status
Simulation time 212847014 ps
CPU time 0.96 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 206992 kb
Host smart-295f2ded-699f-4241-9684-5ac3c668ffd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40007
94847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.4000794847
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3017336182
Short name T1967
Test name
Test status
Simulation time 23356088205 ps
CPU time 29.19 seconds
Started Jul 31 05:42:20 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 207184 kb
Host smart-44404294-016a-47da-bee1-4544cb735a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173
36182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3017336182
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3920869306
Short name T1554
Test name
Test status
Simulation time 3324148562 ps
CPU time 5.29 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:23 PM PDT 24
Peak memory 207168 kb
Host smart-cced531f-8101-42f5-be3f-c083445066fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39208
69306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3920869306
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.1414944107
Short name T2075
Test name
Test status
Simulation time 8984420874 ps
CPU time 88.45 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:43:48 PM PDT 24
Peak memory 217332 kb
Host smart-f9fb2b00-0136-4eb3-b626-e1d33b0ad383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14149
44107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1414944107
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2276889024
Short name T1779
Test name
Test status
Simulation time 5269907116 ps
CPU time 56.48 seconds
Started Jul 31 05:42:20 PM PDT 24
Finished Jul 31 05:43:17 PM PDT 24
Peak memory 216924 kb
Host smart-d905b2ca-535d-4342-af22-d927ca96dafb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2276889024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2276889024
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3326296059
Short name T945
Test name
Test status
Simulation time 313977490 ps
CPU time 1.1 seconds
Started Jul 31 05:42:23 PM PDT 24
Finished Jul 31 05:42:24 PM PDT 24
Peak memory 206984 kb
Host smart-117c70a4-3d0e-4dde-87c8-5a9c76f5cf2b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3326296059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3326296059
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3199839409
Short name T1784
Test name
Test status
Simulation time 196172217 ps
CPU time 0.9 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 207008 kb
Host smart-b36737e9-7d51-4d25-b454-13424114de7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31998
39409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3199839409
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.4025703297
Short name T437
Test name
Test status
Simulation time 3443815549 ps
CPU time 98.68 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:43:58 PM PDT 24
Peak memory 215372 kb
Host smart-27cf464d-304c-47d0-835f-71ac998572de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40257
03297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.4025703297
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.33340333
Short name T402
Test name
Test status
Simulation time 4398396253 ps
CPU time 135.07 seconds
Started Jul 31 05:42:23 PM PDT 24
Finished Jul 31 05:44:38 PM PDT 24
Peak memory 215392 kb
Host smart-c3b8bc9e-0e96-44eb-b097-f49159821a22
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=33340333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.33340333
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.113303914
Short name T2454
Test name
Test status
Simulation time 201801286 ps
CPU time 0.93 seconds
Started Jul 31 05:42:16 PM PDT 24
Finished Jul 31 05:42:17 PM PDT 24
Peak memory 206992 kb
Host smart-377dafcd-ac1e-4e5c-849e-b6af4babe2ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=113303914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.113303914
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1802144111
Short name T1885
Test name
Test status
Simulation time 145425807 ps
CPU time 0.84 seconds
Started Jul 31 05:42:17 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 206976 kb
Host smart-63c64803-7a14-46d8-a262-319c670a4c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18021
44111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1802144111
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1850003249
Short name T768
Test name
Test status
Simulation time 184442597 ps
CPU time 0.92 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:42:21 PM PDT 24
Peak memory 206996 kb
Host smart-bb385f93-9e74-493a-9299-59f13bb1f01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18500
03249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1850003249
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1195567634
Short name T424
Test name
Test status
Simulation time 209554979 ps
CPU time 0.97 seconds
Started Jul 31 05:42:17 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 207024 kb
Host smart-06b6ba67-5085-4ec0-8fab-f9054dbeb41c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11955
67634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1195567634
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3538830412
Short name T1145
Test name
Test status
Simulation time 159459815 ps
CPU time 0.84 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 207032 kb
Host smart-875b31e0-13ab-4e84-8250-31aaf1a842bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35388
30412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3538830412
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.997737461
Short name T875
Test name
Test status
Simulation time 184689148 ps
CPU time 0.91 seconds
Started Jul 31 05:42:17 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 206980 kb
Host smart-3cbf95c5-9677-4241-ba8a-871fdb7069fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99773
7461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.997737461
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2222027434
Short name T2219
Test name
Test status
Simulation time 156737109 ps
CPU time 0.94 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 207048 kb
Host smart-57d6b241-f9c5-4015-a6cd-d14b71828c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22220
27434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2222027434
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.2162933595
Short name T1764
Test name
Test status
Simulation time 283615525 ps
CPU time 1.03 seconds
Started Jul 31 05:42:23 PM PDT 24
Finished Jul 31 05:42:24 PM PDT 24
Peak memory 207000 kb
Host smart-774962f4-f191-46af-b338-75de4242a782
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2162933595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.2162933595
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3328063336
Short name T2533
Test name
Test status
Simulation time 166112511 ps
CPU time 0.86 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 206956 kb
Host smart-3141b957-79a0-487c-96e6-4da797d062a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33280
63336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3328063336
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3840291768
Short name T2599
Test name
Test status
Simulation time 87772727 ps
CPU time 0.78 seconds
Started Jul 31 05:42:17 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 206952 kb
Host smart-befc6d4b-f588-45c5-abfc-2231c6226318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38402
91768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3840291768
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.2343114887
Short name T2421
Test name
Test status
Simulation time 11364440543 ps
CPU time 28.11 seconds
Started Jul 31 05:42:21 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 215456 kb
Host smart-e58c46bc-40a2-4fa8-8f9c-883db8c879ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23431
14887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2343114887
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.121973650
Short name T2366
Test name
Test status
Simulation time 170269561 ps
CPU time 0.92 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 206992 kb
Host smart-87803da9-71c8-4ac7-b492-fa5c150b9050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12197
3650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.121973650
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.638072415
Short name T137
Test name
Test status
Simulation time 224758790 ps
CPU time 0.98 seconds
Started Jul 31 05:42:17 PM PDT 24
Finished Jul 31 05:42:18 PM PDT 24
Peak memory 206976 kb
Host smart-3bd8dc12-b243-4a4a-973d-e7cff23be4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63807
2415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.638072415
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2286989994
Short name T505
Test name
Test status
Simulation time 245958549 ps
CPU time 0.98 seconds
Started Jul 31 05:42:19 PM PDT 24
Finished Jul 31 05:42:20 PM PDT 24
Peak memory 206976 kb
Host smart-02a6e0f5-8807-43dd-a468-38768cfd3356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22869
89994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2286989994
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2662558793
Short name T2847
Test name
Test status
Simulation time 215921007 ps
CPU time 0.91 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:19 PM PDT 24
Peak memory 206988 kb
Host smart-94665aca-f22d-4b48-a50e-e6253803b8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26625
58793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2662558793
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.2277228876
Short name T2150
Test name
Test status
Simulation time 153262293 ps
CPU time 0.86 seconds
Started Jul 31 05:42:20 PM PDT 24
Finished Jul 31 05:42:21 PM PDT 24
Peak memory 207000 kb
Host smart-5502568a-37c8-4fd7-bec6-9fe713b139cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22772
28876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.2277228876
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.3323648465
Short name T2575
Test name
Test status
Simulation time 163114755 ps
CPU time 0.83 seconds
Started Jul 31 05:42:27 PM PDT 24
Finished Jul 31 05:42:27 PM PDT 24
Peak memory 206952 kb
Host smart-45b629b6-3c47-475e-9113-43b595ea9078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33236
48465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3323648465
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2482621290
Short name T1774
Test name
Test status
Simulation time 167213797 ps
CPU time 0.84 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:24 PM PDT 24
Peak memory 207036 kb
Host smart-4ed9dfdf-9eb5-4244-a94e-0bf414c44231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24826
21290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2482621290
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2247641529
Short name T2444
Test name
Test status
Simulation time 220829285 ps
CPU time 1.04 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:25 PM PDT 24
Peak memory 206980 kb
Host smart-dc6b5034-0e10-4888-a936-cc59b576251e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22476
41529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2247641529
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2054354539
Short name T2770
Test name
Test status
Simulation time 5340485258 ps
CPU time 63.72 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 215372 kb
Host smart-f3d5256e-52a8-4053-afd6-aa72a95a2359
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2054354539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2054354539
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.220114184
Short name T1498
Test name
Test status
Simulation time 172834913 ps
CPU time 0.9 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:25 PM PDT 24
Peak memory 206980 kb
Host smart-e2d93fc8-1e6d-4a2f-8f22-a0d436e38c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22011
4184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.220114184
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2262031629
Short name T2278
Test name
Test status
Simulation time 153523537 ps
CPU time 0.89 seconds
Started Jul 31 05:42:22 PM PDT 24
Finished Jul 31 05:42:23 PM PDT 24
Peak memory 206968 kb
Host smart-1c3f3157-f844-49e2-b3de-5fc8d8a644f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
31629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2262031629
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3893527795
Short name T92
Test name
Test status
Simulation time 668591967 ps
CPU time 1.86 seconds
Started Jul 31 05:42:25 PM PDT 24
Finished Jul 31 05:42:27 PM PDT 24
Peak memory 207004 kb
Host smart-6a99c833-8767-483c-a6fd-3f377c2f8611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38935
27795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3893527795
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2745544803
Short name T1834
Test name
Test status
Simulation time 2917496301 ps
CPU time 23.61 seconds
Started Jul 31 05:42:25 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 216760 kb
Host smart-aad73004-1aa5-418c-8f08-fd66a2acac25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27455
44803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2745544803
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.3254169676
Short name T1333
Test name
Test status
Simulation time 736520182 ps
CPU time 5.39 seconds
Started Jul 31 05:42:18 PM PDT 24
Finished Jul 31 05:42:24 PM PDT 24
Peak memory 207156 kb
Host smart-a248fe53-59ea-4db0-a532-a1b4412623f4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254169676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.3254169676
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3472106667
Short name T464
Test name
Test status
Simulation time 3647740130 ps
CPU time 5.29 seconds
Started Jul 31 05:42:27 PM PDT 24
Finished Jul 31 05:42:33 PM PDT 24
Peak memory 207172 kb
Host smart-1700489a-4315-492f-a70a-5ec39442be5a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472106667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_disconnect.3472106667
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.56619592
Short name T830
Test name
Test status
Simulation time 13330804913 ps
CPU time 15.08 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:40 PM PDT 24
Peak memory 207244 kb
Host smart-0e7d5a86-df78-4670-a371-e8628ca9f6db
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=56619592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.56619592
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2931618053
Short name T492
Test name
Test status
Simulation time 23429831049 ps
CPU time 29.21 seconds
Started Jul 31 05:42:25 PM PDT 24
Finished Jul 31 05:42:55 PM PDT 24
Peak memory 207200 kb
Host smart-c3b07469-df15-408a-9d1c-3899c6d572ad
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931618053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.2931618053
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.506551610
Short name T991
Test name
Test status
Simulation time 150543433 ps
CPU time 0.85 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:25 PM PDT 24
Peak memory 206996 kb
Host smart-ac6b2525-313f-44bb-bbf4-4350f1f6e3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50655
1610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.506551610
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1197591145
Short name T173
Test name
Test status
Simulation time 143746643 ps
CPU time 0.84 seconds
Started Jul 31 05:42:27 PM PDT 24
Finished Jul 31 05:42:28 PM PDT 24
Peak memory 207016 kb
Host smart-d01be00d-6405-41f3-ad21-b8e1be82d534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11975
91145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1197591145
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1796188553
Short name T1570
Test name
Test status
Simulation time 325380663 ps
CPU time 1.23 seconds
Started Jul 31 05:42:25 PM PDT 24
Finished Jul 31 05:42:27 PM PDT 24
Peak memory 206976 kb
Host smart-a9d491aa-8d5a-409d-9b24-f522fd3538be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17961
88553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1796188553
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1915042830
Short name T2640
Test name
Test status
Simulation time 302800057 ps
CPU time 1.08 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:26 PM PDT 24
Peak memory 206984 kb
Host smart-a9e0fc0e-8853-45f5-8268-060c61a4bed5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1915042830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1915042830
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.1750725317
Short name T2210
Test name
Test status
Simulation time 12823924290 ps
CPU time 26.49 seconds
Started Jul 31 05:42:27 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 207196 kb
Host smart-5c208726-bf8a-4d3b-91c6-bde4842d4768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17507
25317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1750725317
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_device_timeout.2282558010
Short name T878
Test name
Test status
Simulation time 1097563602 ps
CPU time 9.12 seconds
Started Jul 31 05:42:26 PM PDT 24
Finished Jul 31 05:42:36 PM PDT 24
Peak memory 207152 kb
Host smart-0c5a33b4-c21e-498b-b1be-681fb8fad415
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282558010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.2282558010
Directory /workspace/16.usbdev_device_timeout/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1125863869
Short name T2385
Test name
Test status
Simulation time 369739932 ps
CPU time 1.33 seconds
Started Jul 31 05:42:25 PM PDT 24
Finished Jul 31 05:42:26 PM PDT 24
Peak memory 206940 kb
Host smart-7b08fda5-486f-469e-bfd8-cf56d3b236ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11258
63869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1125863869
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3407608062
Short name T767
Test name
Test status
Simulation time 158004842 ps
CPU time 0.85 seconds
Started Jul 31 05:42:25 PM PDT 24
Finished Jul 31 05:42:26 PM PDT 24
Peak memory 206960 kb
Host smart-3868e12d-fd56-4b43-8fef-c3084bd1a03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34076
08062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3407608062
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.4249354624
Short name T1866
Test name
Test status
Simulation time 40019067 ps
CPU time 0.74 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:25 PM PDT 24
Peak memory 206936 kb
Host smart-3ca145da-9979-4397-9e05-fd98f96143f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42493
54624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.4249354624
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.4126902225
Short name T2197
Test name
Test status
Simulation time 791868769 ps
CPU time 2.36 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:27 PM PDT 24
Peak memory 207152 kb
Host smart-13000879-d6ab-4fd8-9796-ebaa670a3047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269
02225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.4126902225
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3526854291
Short name T176
Test name
Test status
Simulation time 196150492 ps
CPU time 2.33 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:26 PM PDT 24
Peak memory 207012 kb
Host smart-a99d1625-e194-458a-9057-528e417b7ad1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35268
54291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3526854291
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1077628214
Short name T1990
Test name
Test status
Simulation time 227007723 ps
CPU time 1.22 seconds
Started Jul 31 05:42:26 PM PDT 24
Finished Jul 31 05:42:28 PM PDT 24
Peak memory 215296 kb
Host smart-9b16fe15-cf31-4e26-adb9-ba6cbf65100f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1077628214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1077628214
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1394393890
Short name T960
Test name
Test status
Simulation time 140488035 ps
CPU time 0.83 seconds
Started Jul 31 05:42:22 PM PDT 24
Finished Jul 31 05:42:23 PM PDT 24
Peak memory 206968 kb
Host smart-9213a4b4-2e92-4560-84e1-c4edf2f796dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13943
93890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1394393890
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.4104971929
Short name T2715
Test name
Test status
Simulation time 204559188 ps
CPU time 0.96 seconds
Started Jul 31 05:42:23 PM PDT 24
Finished Jul 31 05:42:24 PM PDT 24
Peak memory 206984 kb
Host smart-30130508-eac5-4a0c-9423-05591a6684f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41049
71929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.4104971929
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.886006909
Short name T2696
Test name
Test status
Simulation time 8644717380 ps
CPU time 261.47 seconds
Started Jul 31 05:42:25 PM PDT 24
Finished Jul 31 05:46:47 PM PDT 24
Peak memory 215468 kb
Host smart-cebe79f6-606f-454b-bca6-eb9cd18150fb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=886006909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.886006909
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.2390568159
Short name T2101
Test name
Test status
Simulation time 11137824549 ps
CPU time 135.31 seconds
Started Jul 31 05:42:26 PM PDT 24
Finished Jul 31 05:44:41 PM PDT 24
Peak memory 207160 kb
Host smart-ba71dddc-1805-452d-b812-3202e1149a25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2390568159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.2390568159
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2157363104
Short name T1096
Test name
Test status
Simulation time 173928926 ps
CPU time 0.87 seconds
Started Jul 31 05:42:24 PM PDT 24
Finished Jul 31 05:42:25 PM PDT 24
Peak memory 206964 kb
Host smart-60303192-6073-4ad9-8e89-85cc70f08ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21573
63104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2157363104
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.1716081999
Short name T507
Test name
Test status
Simulation time 23392133036 ps
CPU time 27.31 seconds
Started Jul 31 05:42:27 PM PDT 24
Finished Jul 31 05:42:54 PM PDT 24
Peak memory 207188 kb
Host smart-c42ce1e3-b887-4859-8c68-0370ef027d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17160
81999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.1716081999
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3741312435
Short name T1081
Test name
Test status
Simulation time 3298856631 ps
CPU time 5.35 seconds
Started Jul 31 05:42:28 PM PDT 24
Finished Jul 31 05:42:33 PM PDT 24
Peak memory 207144 kb
Host smart-39e4972d-10a7-432a-aa04-9bd18836f8c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37413
12435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3741312435
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.3746246193
Short name T148
Test name
Test status
Simulation time 6059538123 ps
CPU time 172.87 seconds
Started Jul 31 05:42:32 PM PDT 24
Finished Jul 31 05:45:25 PM PDT 24
Peak memory 215380 kb
Host smart-4de56e7a-f94d-47f2-afc3-14dc7d3041d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37462
46193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.3746246193
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.2304258407
Short name T1063
Test name
Test status
Simulation time 5764715629 ps
CPU time 170.35 seconds
Started Jul 31 05:42:32 PM PDT 24
Finished Jul 31 05:45:22 PM PDT 24
Peak memory 215432 kb
Host smart-4070c3c6-99ce-4f11-ad76-5083fcbb0638
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2304258407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.2304258407
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.6327734
Short name T1773
Test name
Test status
Simulation time 249275225 ps
CPU time 1.08 seconds
Started Jul 31 05:42:34 PM PDT 24
Finished Jul 31 05:42:36 PM PDT 24
Peak memory 206964 kb
Host smart-94c963ad-fafa-4319-bdf8-dff8dd9d5cdb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=6327734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.6327734
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.857706782
Short name T2427
Test name
Test status
Simulation time 208873718 ps
CPU time 0.98 seconds
Started Jul 31 05:42:33 PM PDT 24
Finished Jul 31 05:42:34 PM PDT 24
Peak memory 206984 kb
Host smart-5756afd3-9c1b-4e1f-9d32-92c4ad9f928c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85770
6782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.857706782
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.2285271432
Short name T679
Test name
Test status
Simulation time 5289216488 ps
CPU time 51.26 seconds
Started Jul 31 05:42:34 PM PDT 24
Finished Jul 31 05:43:25 PM PDT 24
Peak memory 215424 kb
Host smart-db6cce54-cd50-401c-8373-3a8ca67d88fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22852
71432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.2285271432
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3958416178
Short name T1280
Test name
Test status
Simulation time 4718175518 ps
CPU time 41.48 seconds
Started Jul 31 05:42:29 PM PDT 24
Finished Jul 31 05:43:11 PM PDT 24
Peak memory 215428 kb
Host smart-7adfda8b-92dc-4528-b4df-fe4b8731165a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3958416178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3958416178
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1367875949
Short name T1998
Test name
Test status
Simulation time 152909782 ps
CPU time 0.85 seconds
Started Jul 31 05:42:30 PM PDT 24
Finished Jul 31 05:42:31 PM PDT 24
Peak memory 206996 kb
Host smart-7fb5bfeb-5565-40c0-a764-62bc8beeb240
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1367875949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1367875949
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.201669926
Short name T2580
Test name
Test status
Simulation time 168339907 ps
CPU time 0.88 seconds
Started Jul 31 05:42:30 PM PDT 24
Finished Jul 31 05:42:31 PM PDT 24
Peak memory 206948 kb
Host smart-dd2406f4-b720-4f42-90b8-edbcccdac20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20166
9926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.201669926
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.4056493211
Short name T2295
Test name
Test status
Simulation time 182301375 ps
CPU time 0.9 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:32 PM PDT 24
Peak memory 206980 kb
Host smart-fda313b6-b9e4-4fa9-8e98-0b0fcd0403dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40564
93211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.4056493211
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.1086745481
Short name T2205
Test name
Test status
Simulation time 199370924 ps
CPU time 0.94 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:32 PM PDT 24
Peak memory 206992 kb
Host smart-c1bf9f7d-4410-461d-ad32-ad1eb7a67b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10867
45481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.1086745481
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1113810405
Short name T2518
Test name
Test status
Simulation time 166030077 ps
CPU time 0.91 seconds
Started Jul 31 05:42:32 PM PDT 24
Finished Jul 31 05:42:33 PM PDT 24
Peak memory 206996 kb
Host smart-c352fbe6-9f61-488f-b6e4-48cd64570d61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11138
10405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1113810405
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1794573149
Short name T1401
Test name
Test status
Simulation time 175428018 ps
CPU time 0.88 seconds
Started Jul 31 05:42:30 PM PDT 24
Finished Jul 31 05:42:31 PM PDT 24
Peak memory 206984 kb
Host smart-3b036d51-c6e8-4f79-8583-1daf29e353f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17945
73149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1794573149
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.2623432109
Short name T730
Test name
Test status
Simulation time 240944435 ps
CPU time 1.13 seconds
Started Jul 31 05:42:33 PM PDT 24
Finished Jul 31 05:42:35 PM PDT 24
Peak memory 206968 kb
Host smart-9a28f27a-3775-4836-b65d-5b30d2c28208
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2623432109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.2623432109
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1175010728
Short name T769
Test name
Test status
Simulation time 175450585 ps
CPU time 0.89 seconds
Started Jul 31 05:42:29 PM PDT 24
Finished Jul 31 05:42:30 PM PDT 24
Peak memory 206948 kb
Host smart-0bfbdedb-f9d6-430e-919d-a6ba73aa52b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11750
10728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1175010728
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.3537569259
Short name T1146
Test name
Test status
Simulation time 64265039 ps
CPU time 0.77 seconds
Started Jul 31 05:42:33 PM PDT 24
Finished Jul 31 05:42:33 PM PDT 24
Peak memory 206984 kb
Host smart-f3c00109-1665-4139-aaf8-ba769c5842d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35375
69259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3537569259
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1130652386
Short name T1182
Test name
Test status
Simulation time 14165642974 ps
CPU time 41.34 seconds
Started Jul 31 05:42:34 PM PDT 24
Finished Jul 31 05:43:16 PM PDT 24
Peak memory 219980 kb
Host smart-d9196d46-9e99-49e9-8904-24f445163403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11306
52386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1130652386
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1344294192
Short name T737
Test name
Test status
Simulation time 160983748 ps
CPU time 0.87 seconds
Started Jul 31 05:42:29 PM PDT 24
Finished Jul 31 05:42:30 PM PDT 24
Peak memory 206980 kb
Host smart-5177b720-37d6-49a0-aebc-3997da24ae8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13442
94192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1344294192
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.3811583293
Short name T1746
Test name
Test status
Simulation time 275892769 ps
CPU time 1.04 seconds
Started Jul 31 05:42:32 PM PDT 24
Finished Jul 31 05:42:34 PM PDT 24
Peak memory 206968 kb
Host smart-6c758358-e382-4515-91c1-aac43fbca23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38115
83293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3811583293
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.375858415
Short name T360
Test name
Test status
Simulation time 203382604 ps
CPU time 0.97 seconds
Started Jul 31 05:42:30 PM PDT 24
Finished Jul 31 05:42:31 PM PDT 24
Peak memory 206984 kb
Host smart-d5f186a4-cc94-409e-98b6-427778699a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37585
8415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.375858415
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.339823393
Short name T1977
Test name
Test status
Simulation time 149988356 ps
CPU time 0.88 seconds
Started Jul 31 05:42:30 PM PDT 24
Finished Jul 31 05:42:31 PM PDT 24
Peak memory 206996 kb
Host smart-f5ffc242-30e6-4bbf-9b28-7a3ed14e821f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33982
3393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.339823393
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.179801348
Short name T1465
Test name
Test status
Simulation time 221872453 ps
CPU time 0.94 seconds
Started Jul 31 05:42:32 PM PDT 24
Finished Jul 31 05:42:33 PM PDT 24
Peak memory 206996 kb
Host smart-68b56354-fa0e-40d9-905d-028b46903e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17980
1348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.179801348
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.4073307815
Short name T2529
Test name
Test status
Simulation time 163047747 ps
CPU time 0.83 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:32 PM PDT 24
Peak memory 206964 kb
Host smart-6e676681-7922-46b6-a280-5dbc3e5d1908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40733
07815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.4073307815
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.1848496165
Short name T2456
Test name
Test status
Simulation time 162385946 ps
CPU time 0.86 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:32 PM PDT 24
Peak memory 206988 kb
Host smart-9a0e6552-209a-4029-a62e-0c08b7474ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18484
96165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.1848496165
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1798255448
Short name T1887
Test name
Test status
Simulation time 222072790 ps
CPU time 1.03 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:32 PM PDT 24
Peak memory 207008 kb
Host smart-5319d4e7-e0b8-4061-b884-ba5b8a179d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17982
55448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1798255448
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.3664185160
Short name T1430
Test name
Test status
Simulation time 4542034283 ps
CPU time 127.06 seconds
Started Jul 31 05:42:29 PM PDT 24
Finished Jul 31 05:44:36 PM PDT 24
Peak memory 215320 kb
Host smart-fcab1e73-a4ee-4e26-b533-66e9589cbd62
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3664185160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.3664185160
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2583459912
Short name T1103
Test name
Test status
Simulation time 183960744 ps
CPU time 0.9 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:32 PM PDT 24
Peak memory 206992 kb
Host smart-fbc49070-8a54-49e2-a156-24d123c76c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25834
59912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2583459912
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.976900168
Short name T2139
Test name
Test status
Simulation time 166850433 ps
CPU time 0.86 seconds
Started Jul 31 05:42:32 PM PDT 24
Finished Jul 31 05:42:33 PM PDT 24
Peak memory 207004 kb
Host smart-bf8571ba-4f6e-4b5e-b02c-a72929983d09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97690
0168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.976900168
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3282568635
Short name T1740
Test name
Test status
Simulation time 552668112 ps
CPU time 1.65 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:32 PM PDT 24
Peak memory 206980 kb
Host smart-25621ebf-5126-486d-93b4-39de37d39d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32825
68635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3282568635
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.1850486592
Short name T2663
Test name
Test status
Simulation time 2610573824 ps
CPU time 75.74 seconds
Started Jul 31 05:42:33 PM PDT 24
Finished Jul 31 05:43:49 PM PDT 24
Peak memory 215424 kb
Host smart-0ef4af3b-db66-415c-a3dd-b9883a6d742c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18504
86592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1850486592
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.3959960130
Short name T2260
Test name
Test status
Simulation time 1554745980 ps
CPU time 37.64 seconds
Started Jul 31 05:42:25 PM PDT 24
Finished Jul 31 05:43:03 PM PDT 24
Peak memory 207068 kb
Host smart-ff5ff522-936a-4b9e-8a69-65e77686352c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959960130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos
t_handshake.3959960130
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1776106526
Short name T735
Test name
Test status
Simulation time 48751325 ps
CPU time 0.67 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 207024 kb
Host smart-56756bb3-82d6-4db6-84ca-bf6cd0080f30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1776106526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1776106526
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.2691086294
Short name T2852
Test name
Test status
Simulation time 3823721554 ps
CPU time 5.24 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:37 PM PDT 24
Peak memory 207132 kb
Host smart-6222ccf7-6275-4081-a701-acc0f35e80fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691086294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.2691086294
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1727060691
Short name T1583
Test name
Test status
Simulation time 13373446566 ps
CPU time 15.62 seconds
Started Jul 31 05:42:31 PM PDT 24
Finished Jul 31 05:42:47 PM PDT 24
Peak memory 207224 kb
Host smart-107e39e5-c9eb-4d1d-983d-7145f795ec1f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727060691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1727060691
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.311669019
Short name T828
Test name
Test status
Simulation time 23340540917 ps
CPU time 28.49 seconds
Started Jul 31 05:42:37 PM PDT 24
Finished Jul 31 05:43:06 PM PDT 24
Peak memory 207180 kb
Host smart-abe638de-fbbf-409f-a5c8-9e39c0e5ee56
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311669019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_ao
n_wake_resume.311669019
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.4292708972
Short name T585
Test name
Test status
Simulation time 162646387 ps
CPU time 0.92 seconds
Started Jul 31 05:42:38 PM PDT 24
Finished Jul 31 05:42:39 PM PDT 24
Peak memory 206976 kb
Host smart-618d7612-5741-4c75-a803-a49e5905303c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42927
08972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.4292708972
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.3499725009
Short name T1
Test name
Test status
Simulation time 151951454 ps
CPU time 0.83 seconds
Started Jul 31 05:42:36 PM PDT 24
Finished Jul 31 05:42:37 PM PDT 24
Peak memory 206940 kb
Host smart-11bb2722-1379-4d67-a4c9-2d6d91087d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34997
25009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.3499725009
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2788810661
Short name T491
Test name
Test status
Simulation time 544304280 ps
CPU time 1.65 seconds
Started Jul 31 05:42:37 PM PDT 24
Finished Jul 31 05:42:39 PM PDT 24
Peak memory 207056 kb
Host smart-8379447d-6010-4eb4-9849-4b7008cd7b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27888
10661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2788810661
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2928872528
Short name T1358
Test name
Test status
Simulation time 944272426 ps
CPU time 2.41 seconds
Started Jul 31 05:42:36 PM PDT 24
Finished Jul 31 05:42:38 PM PDT 24
Peak memory 207144 kb
Host smart-d740d968-5b0c-4af7-a1ee-be0204067802
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2928872528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2928872528
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.4040979546
Short name T2173
Test name
Test status
Simulation time 7829138792 ps
CPU time 21.2 seconds
Started Jul 31 05:42:45 PM PDT 24
Finished Jul 31 05:43:06 PM PDT 24
Peak memory 207208 kb
Host smart-00428b7d-fe35-4eb6-a420-67efdaa70d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40409
79546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.4040979546
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_device_timeout.1973870431
Short name T1818
Test name
Test status
Simulation time 4304291857 ps
CPU time 31.97 seconds
Started Jul 31 05:42:36 PM PDT 24
Finished Jul 31 05:43:08 PM PDT 24
Peak memory 207184 kb
Host smart-03e7f4f3-2cd0-45b9-ae52-29571b0ba3e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973870431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.1973870431
Directory /workspace/17.usbdev_device_timeout/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.163053800
Short name T282
Test name
Test status
Simulation time 502671640 ps
CPU time 1.64 seconds
Started Jul 31 05:42:37 PM PDT 24
Finished Jul 31 05:42:39 PM PDT 24
Peak memory 206968 kb
Host smart-43f1b32c-a991-46f0-b9b8-c9bc6238f30b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16305
3800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.163053800
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3921624135
Short name T2816
Test name
Test status
Simulation time 163329815 ps
CPU time 0.88 seconds
Started Jul 31 05:42:37 PM PDT 24
Finished Jul 31 05:42:38 PM PDT 24
Peak memory 206928 kb
Host smart-5c6bde94-b8c3-4f01-8f7f-38de7ca8bcd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39216
24135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3921624135
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.197860015
Short name T2440
Test name
Test status
Simulation time 29313425 ps
CPU time 0.69 seconds
Started Jul 31 05:42:38 PM PDT 24
Finished Jul 31 05:42:38 PM PDT 24
Peak memory 206944 kb
Host smart-5803ece3-d850-4812-ab2d-96ff1e4801b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19786
0015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.197860015
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.362125726
Short name T2423
Test name
Test status
Simulation time 871341550 ps
CPU time 2.54 seconds
Started Jul 31 05:42:35 PM PDT 24
Finished Jul 31 05:42:38 PM PDT 24
Peak memory 207132 kb
Host smart-424a74af-e25f-46fb-8a76-02c8f83ebe10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36212
5726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.362125726
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.3116888532
Short name T2471
Test name
Test status
Simulation time 219746293 ps
CPU time 1.85 seconds
Started Jul 31 05:42:45 PM PDT 24
Finished Jul 31 05:42:47 PM PDT 24
Peak memory 207024 kb
Host smart-60aa9e7d-cdcc-4798-86cf-f782caac5fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31168
88532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.3116888532
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1617877796
Short name T2430
Test name
Test status
Simulation time 216148713 ps
CPU time 0.9 seconds
Started Jul 31 05:42:35 PM PDT 24
Finished Jul 31 05:42:36 PM PDT 24
Peak memory 207004 kb
Host smart-c1206a85-62ac-4354-9aee-4edc347315e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1617877796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1617877796
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3707627690
Short name T454
Test name
Test status
Simulation time 182201954 ps
CPU time 0.91 seconds
Started Jul 31 05:42:37 PM PDT 24
Finished Jul 31 05:42:38 PM PDT 24
Peak memory 206936 kb
Host smart-ed855c2c-6222-419e-a0be-2dbaf09725c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37076
27690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3707627690
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1451321667
Short name T496
Test name
Test status
Simulation time 203266292 ps
CPU time 0.91 seconds
Started Jul 31 05:42:34 PM PDT 24
Finished Jul 31 05:42:36 PM PDT 24
Peak memory 206996 kb
Host smart-f49b23ad-fbc9-4501-96cc-b10e9ee1e0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14513
21667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1451321667
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.1550494898
Short name T2314
Test name
Test status
Simulation time 9118509417 ps
CPU time 90.44 seconds
Started Jul 31 05:42:37 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 207180 kb
Host smart-483584d2-aa84-4695-9739-d69a7359b8a3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1550494898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.1550494898
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.1351720522
Short name T81
Test name
Test status
Simulation time 7788911841 ps
CPU time 97.28 seconds
Started Jul 31 05:42:38 PM PDT 24
Finished Jul 31 05:44:15 PM PDT 24
Peak memory 207200 kb
Host smart-7dd48b65-5118-4fa9-a01f-fb87f548ec2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1351720522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.1351720522
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.1556550149
Short name T1633
Test name
Test status
Simulation time 193515178 ps
CPU time 0.92 seconds
Started Jul 31 05:42:35 PM PDT 24
Finished Jul 31 05:42:36 PM PDT 24
Peak memory 207000 kb
Host smart-df76d002-d91a-4f6a-9542-b3863d476454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15565
50149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.1556550149
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.1416846440
Short name T839
Test name
Test status
Simulation time 23378202291 ps
CPU time 26.77 seconds
Started Jul 31 05:42:46 PM PDT 24
Finished Jul 31 05:43:13 PM PDT 24
Peak memory 207200 kb
Host smart-3413d41c-a716-47c8-92c2-11d50aabcf20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14168
46440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.1416846440
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.552793824
Short name T1466
Test name
Test status
Simulation time 3302594215 ps
CPU time 5.88 seconds
Started Jul 31 05:42:36 PM PDT 24
Finished Jul 31 05:42:42 PM PDT 24
Peak memory 207116 kb
Host smart-e0f2738d-d65b-491d-8042-4e34f44feee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55279
3824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.552793824
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.2455691671
Short name T1108
Test name
Test status
Simulation time 7747395567 ps
CPU time 60.01 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:43:48 PM PDT 24
Peak memory 217344 kb
Host smart-0f4abb6a-74ef-4fdc-82a1-d41f7db98445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24556
91671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.2455691671
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.3611729750
Short name T2118
Test name
Test status
Simulation time 3542518472 ps
CPU time 37.78 seconds
Started Jul 31 05:42:36 PM PDT 24
Finished Jul 31 05:43:14 PM PDT 24
Peak memory 216564 kb
Host smart-b6c5ee35-e9a8-4296-835d-45570f37b7d2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3611729750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.3611729750
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2700705298
Short name T820
Test name
Test status
Simulation time 247394444 ps
CPU time 1.03 seconds
Started Jul 31 05:42:37 PM PDT 24
Finished Jul 31 05:42:38 PM PDT 24
Peak memory 207000 kb
Host smart-b986686b-db1a-4792-b7d2-0869f2edc95c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2700705298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2700705298
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2363288132
Short name T1719
Test name
Test status
Simulation time 195988057 ps
CPU time 0.95 seconds
Started Jul 31 05:42:34 PM PDT 24
Finished Jul 31 05:42:35 PM PDT 24
Peak memory 206988 kb
Host smart-dc65858f-0b3c-4128-bd3c-6e8be6abfcd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23632
88132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2363288132
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.84840718
Short name T558
Test name
Test status
Simulation time 3542312363 ps
CPU time 105.4 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:44:33 PM PDT 24
Peak memory 215380 kb
Host smart-4af4eebc-45da-4758-842c-58c4d8efc879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84840
718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.84840718
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3995423516
Short name T1547
Test name
Test status
Simulation time 5507067388 ps
CPU time 162.38 seconds
Started Jul 31 05:42:38 PM PDT 24
Finished Jul 31 05:45:20 PM PDT 24
Peak memory 215416 kb
Host smart-2788516b-53bc-4517-b902-d49d7b520524
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3995423516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3995423516
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.543836743
Short name T856
Test name
Test status
Simulation time 168238571 ps
CPU time 0.89 seconds
Started Jul 31 05:42:37 PM PDT 24
Finished Jul 31 05:42:38 PM PDT 24
Peak memory 206980 kb
Host smart-4a10c89a-e417-4939-a744-55f8c108ae46
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=543836743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.543836743
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2290233970
Short name T2286
Test name
Test status
Simulation time 150871866 ps
CPU time 0.83 seconds
Started Jul 31 05:42:36 PM PDT 24
Finished Jul 31 05:42:37 PM PDT 24
Peak memory 206996 kb
Host smart-c83948ec-5675-42d7-b12e-b42e711c5fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22902
33970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2290233970
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2283328110
Short name T111
Test name
Test status
Simulation time 230302983 ps
CPU time 1.03 seconds
Started Jul 31 05:42:35 PM PDT 24
Finished Jul 31 05:42:36 PM PDT 24
Peak memory 207000 kb
Host smart-451b1c47-c59b-4414-a117-f68c75ec783e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22833
28110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2283328110
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.841377954
Short name T600
Test name
Test status
Simulation time 174449093 ps
CPU time 0.9 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:48 PM PDT 24
Peak memory 207000 kb
Host smart-99de5868-7497-456f-ae9d-91ca27a6028c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84137
7954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.841377954
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.3789288153
Short name T1009
Test name
Test status
Simulation time 164777207 ps
CPU time 0.88 seconds
Started Jul 31 05:42:38 PM PDT 24
Finished Jul 31 05:42:39 PM PDT 24
Peak memory 207016 kb
Host smart-c10486a8-fb20-4af6-8a1c-1d47d5e64bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37892
88153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.3789288153
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.850994975
Short name T579
Test name
Test status
Simulation time 196093158 ps
CPU time 0.96 seconds
Started Jul 31 05:42:37 PM PDT 24
Finished Jul 31 05:42:38 PM PDT 24
Peak memory 207028 kb
Host smart-21809a07-dd19-4ae5-9c7b-92eb6af7a4da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85099
4975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.850994975
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.849509517
Short name T1193
Test name
Test status
Simulation time 152943098 ps
CPU time 0.83 seconds
Started Jul 31 05:42:35 PM PDT 24
Finished Jul 31 05:42:36 PM PDT 24
Peak memory 207000 kb
Host smart-cf16e0e9-cbbd-42d7-9ad4-55acc889c05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84950
9517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.849509517
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.2601296972
Short name T2264
Test name
Test status
Simulation time 263681735 ps
CPU time 1.09 seconds
Started Jul 31 05:42:38 PM PDT 24
Finished Jul 31 05:42:39 PM PDT 24
Peak memory 207016 kb
Host smart-d0922a43-643a-4e9d-84ff-2f39ce53d945
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2601296972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.2601296972
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.393294301
Short name T1292
Test name
Test status
Simulation time 149846040 ps
CPU time 0.86 seconds
Started Jul 31 05:42:45 PM PDT 24
Finished Jul 31 05:42:46 PM PDT 24
Peak memory 206964 kb
Host smart-4a8add36-c566-45c2-95ee-de3b88055b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39329
4301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.393294301
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2940596089
Short name T1417
Test name
Test status
Simulation time 36646346 ps
CPU time 0.69 seconds
Started Jul 31 05:42:46 PM PDT 24
Finished Jul 31 05:42:47 PM PDT 24
Peak memory 206964 kb
Host smart-b52a017d-3b1c-4c29-9dee-fcda853c08c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29405
96089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2940596089
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3280379687
Short name T250
Test name
Test status
Simulation time 13041620466 ps
CPU time 34.73 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:43:23 PM PDT 24
Peak memory 220004 kb
Host smart-624fb693-90bf-4d29-a65b-13dc324dcaac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32803
79687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3280379687
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2561092423
Short name T375
Test name
Test status
Simulation time 228257446 ps
CPU time 0.95 seconds
Started Jul 31 05:42:43 PM PDT 24
Finished Jul 31 05:42:44 PM PDT 24
Peak memory 206920 kb
Host smart-685bf33b-aab9-4d0e-a3b4-0510c5b35a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25610
92423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2561092423
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1112218458
Short name T571
Test name
Test status
Simulation time 233054043 ps
CPU time 0.99 seconds
Started Jul 31 05:42:45 PM PDT 24
Finished Jul 31 05:42:46 PM PDT 24
Peak memory 206956 kb
Host smart-4f2c6c4d-5e79-4d1f-9bbb-0e4a0c816286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11122
18458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1112218458
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.1670410684
Short name T2625
Test name
Test status
Simulation time 271057659 ps
CPU time 0.98 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 207012 kb
Host smart-06ee1a70-3d6c-45f6-96e5-bb48ea9f1e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16704
10684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.1670410684
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.866948767
Short name T2255
Test name
Test status
Simulation time 150048277 ps
CPU time 0.89 seconds
Started Jul 31 05:42:45 PM PDT 24
Finished Jul 31 05:42:46 PM PDT 24
Peak memory 206992 kb
Host smart-a367f854-0e1a-4848-8887-a8990a6185f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86694
8767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.866948767
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.986418987
Short name T2387
Test name
Test status
Simulation time 190000134 ps
CPU time 0.98 seconds
Started Jul 31 05:42:49 PM PDT 24
Finished Jul 31 05:42:50 PM PDT 24
Peak memory 207012 kb
Host smart-5f664c2c-a930-4440-b34e-13312797c0b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98641
8987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.986418987
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.956271027
Short name T2229
Test name
Test status
Simulation time 219477033 ps
CPU time 0.96 seconds
Started Jul 31 05:42:45 PM PDT 24
Finished Jul 31 05:42:46 PM PDT 24
Peak memory 206960 kb
Host smart-fabfd812-d7df-4267-a542-0d8e44597b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95627
1027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.956271027
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1678502384
Short name T2557
Test name
Test status
Simulation time 158044179 ps
CPU time 0.9 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:48 PM PDT 24
Peak memory 206992 kb
Host smart-804d3373-6b72-4a3d-a9cc-1426ec38ff39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16785
02384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1678502384
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.4023236592
Short name T1320
Test name
Test status
Simulation time 231805381 ps
CPU time 1.07 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:48 PM PDT 24
Peak memory 206988 kb
Host smart-76855732-89e0-458a-bc49-70b1d0760c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40232
36592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.4023236592
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.1073697325
Short name T1473
Test name
Test status
Simulation time 4883212676 ps
CPU time 38.95 seconds
Started Jul 31 05:42:46 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 215432 kb
Host smart-47d1201d-4756-410b-8725-792b656cb41b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1073697325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.1073697325
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1201987583
Short name T889
Test name
Test status
Simulation time 169133929 ps
CPU time 0.87 seconds
Started Jul 31 05:42:46 PM PDT 24
Finished Jul 31 05:42:47 PM PDT 24
Peak memory 206996 kb
Host smart-dfa837f3-e57c-4e9b-ae0d-45bb628829b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12019
87583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1201987583
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2219042111
Short name T1650
Test name
Test status
Simulation time 160737597 ps
CPU time 0.89 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:48 PM PDT 24
Peak memory 206992 kb
Host smart-55d60533-2d4e-4bb7-8657-13af9a03ef29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22190
42111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2219042111
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.1283522355
Short name T1957
Test name
Test status
Simulation time 264221982 ps
CPU time 1.11 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:48 PM PDT 24
Peak memory 206964 kb
Host smart-2601118f-7555-4833-870d-cf3a497ba0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12835
22355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.1283522355
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.527101512
Short name T1112
Test name
Test status
Simulation time 4160635044 ps
CPU time 33.61 seconds
Started Jul 31 05:42:49 PM PDT 24
Finished Jul 31 05:43:23 PM PDT 24
Peak memory 216952 kb
Host smart-695b9515-c445-4442-9eb4-9860ddf9f209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52710
1512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.527101512
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.2791770376
Short name T425
Test name
Test status
Simulation time 430948931 ps
CPU time 8.18 seconds
Started Jul 31 05:42:36 PM PDT 24
Finished Jul 31 05:42:44 PM PDT 24
Peak memory 207124 kb
Host smart-483e487c-5928-467c-b86e-181d10638606
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791770376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.2791770376
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.913103406
Short name T2794
Test name
Test status
Simulation time 35098590 ps
CPU time 0.67 seconds
Started Jul 31 05:42:58 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 207000 kb
Host smart-a6af68f1-e3f3-4e3f-bf43-2e8166298fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=913103406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.913103406
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.3340898908
Short name T2251
Test name
Test status
Simulation time 3707081130 ps
CPU time 5.53 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 207164 kb
Host smart-63013776-cd87-4603-b9b9-23a3270be9ac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340898908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_disconnect.3340898908
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.2041328176
Short name T656
Test name
Test status
Simulation time 13534471373 ps
CPU time 16.51 seconds
Started Jul 31 05:42:46 PM PDT 24
Finished Jul 31 05:43:03 PM PDT 24
Peak memory 207228 kb
Host smart-9dfa1de1-73d2-4cf2-8143-f13ada281c32
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041328176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.2041328176
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.4290388847
Short name T629
Test name
Test status
Simulation time 23340768596 ps
CPU time 32.55 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:43:21 PM PDT 24
Peak memory 207188 kb
Host smart-4c95f1e8-b0ef-45a7-84be-03ac15350f84
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290388847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.4290388847
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2357431667
Short name T427
Test name
Test status
Simulation time 183889461 ps
CPU time 0.97 seconds
Started Jul 31 05:42:45 PM PDT 24
Finished Jul 31 05:42:46 PM PDT 24
Peak memory 206972 kb
Host smart-66903c19-8880-4db4-99a7-9926f242711a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23574
31667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2357431667
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.892422256
Short name T1993
Test name
Test status
Simulation time 178157796 ps
CPU time 0.9 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 206964 kb
Host smart-5fadbf2a-8a8a-4821-aafd-ecdba684ab16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89242
2256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.892422256
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.2028656630
Short name T1879
Test name
Test status
Simulation time 458900191 ps
CPU time 1.73 seconds
Started Jul 31 05:42:46 PM PDT 24
Finished Jul 31 05:42:48 PM PDT 24
Peak memory 207016 kb
Host smart-0a0e4391-eef6-439a-8c0a-9734991590ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20286
56630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.2028656630
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.596267196
Short name T1612
Test name
Test status
Simulation time 444587922 ps
CPU time 1.47 seconds
Started Jul 31 05:42:49 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 206996 kb
Host smart-fc8fba54-247b-4f7f-917f-833f78d9daf1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=596267196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.596267196
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_timeout.2329610221
Short name T1244
Test name
Test status
Simulation time 1968330040 ps
CPU time 13.65 seconds
Started Jul 31 05:42:49 PM PDT 24
Finished Jul 31 05:43:02 PM PDT 24
Peak memory 207112 kb
Host smart-c6a32dd9-bf2f-49e5-b542-4112f7a164c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329610221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.2329610221
Directory /workspace/18.usbdev_device_timeout/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1144886646
Short name T518
Test name
Test status
Simulation time 492129740 ps
CPU time 1.51 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 206960 kb
Host smart-d1b9f8f3-233d-4889-ac6c-de56a622b0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11448
86646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1144886646
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.3452892205
Short name T36
Test name
Test status
Simulation time 144981534 ps
CPU time 0.87 seconds
Started Jul 31 05:42:45 PM PDT 24
Finished Jul 31 05:42:46 PM PDT 24
Peak memory 206968 kb
Host smart-76e5f288-73b9-40dd-b2a9-fd0941f2766f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34528
92205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3452892205
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2085034
Short name T1152
Test name
Test status
Simulation time 39615250 ps
CPU time 0.72 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 206924 kb
Host smart-00934266-51cb-43f4-8328-dac1414c106f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20850
34 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2085034
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.392840858
Short name T2252
Test name
Test status
Simulation time 863981752 ps
CPU time 2.49 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:42:50 PM PDT 24
Peak memory 207132 kb
Host smart-3f035f5f-6b26-47b8-950b-8c50d02f714e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39284
0858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.392840858
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.2489610354
Short name T2141
Test name
Test status
Simulation time 238455902 ps
CPU time 1.94 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 207092 kb
Host smart-2306e240-e144-4e66-a11c-af6d8aee61de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24896
10354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.2489610354
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.483710014
Short name T534
Test name
Test status
Simulation time 149893106 ps
CPU time 0.88 seconds
Started Jul 31 05:42:46 PM PDT 24
Finished Jul 31 05:42:47 PM PDT 24
Peak memory 207012 kb
Host smart-885f3ff2-d72e-4ae5-9eab-f279b590d4ba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=483710014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.483710014
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.3096026267
Short name T2052
Test name
Test status
Simulation time 142744891 ps
CPU time 0.85 seconds
Started Jul 31 05:42:49 PM PDT 24
Finished Jul 31 05:42:50 PM PDT 24
Peak memory 206952 kb
Host smart-a4987585-6a7d-492a-972d-a839dd3a6085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30960
26267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3096026267
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.3143941509
Short name T2669
Test name
Test status
Simulation time 178842487 ps
CPU time 0.95 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:48 PM PDT 24
Peak memory 207000 kb
Host smart-e5edc926-969e-479e-b534-20839d042301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31439
41509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.3143941509
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.318230573
Short name T943
Test name
Test status
Simulation time 7857369728 ps
CPU time 223.2 seconds
Started Jul 31 05:42:50 PM PDT 24
Finished Jul 31 05:46:33 PM PDT 24
Peak memory 215488 kb
Host smart-09384d89-b234-41d5-b2b0-51b62ba41ef1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=318230573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.318230573
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.4290386986
Short name T2362
Test name
Test status
Simulation time 5973139195 ps
CPU time 46.65 seconds
Started Jul 31 05:42:49 PM PDT 24
Finished Jul 31 05:43:36 PM PDT 24
Peak memory 207160 kb
Host smart-404edbb3-c8c9-4303-a5d3-dd05622d43ad
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4290386986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.4290386986
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.1838925004
Short name T2737
Test name
Test status
Simulation time 202994737 ps
CPU time 0.9 seconds
Started Jul 31 05:42:48 PM PDT 24
Finished Jul 31 05:42:49 PM PDT 24
Peak memory 207016 kb
Host smart-ac04c926-1613-4e58-bace-ac97513034df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18389
25004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.1838925004
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1431504880
Short name T1571
Test name
Test status
Simulation time 23299002896 ps
CPU time 28.62 seconds
Started Jul 31 05:42:46 PM PDT 24
Finished Jul 31 05:43:15 PM PDT 24
Peak memory 207212 kb
Host smart-cf23fd6c-902f-4512-8fe2-edeeded97853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14315
04880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1431504880
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.3450567290
Short name T524
Test name
Test status
Simulation time 3333821308 ps
CPU time 5.36 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:52 PM PDT 24
Peak memory 207144 kb
Host smart-2079a1e4-8b11-4ca8-8499-e2af623a07d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34505
67290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.3450567290
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3245228623
Short name T95
Test name
Test status
Simulation time 9673458701 ps
CPU time 295.06 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 215356 kb
Host smart-0448279e-799d-412b-a8b1-4b4aed98a980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32452
28623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3245228623
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.2913345500
Short name T2702
Test name
Test status
Simulation time 4338401960 ps
CPU time 130.73 seconds
Started Jul 31 05:42:49 PM PDT 24
Finished Jul 31 05:45:00 PM PDT 24
Peak memory 223216 kb
Host smart-30619925-df9e-49c4-8473-de1ae2ba8395
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2913345500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.2913345500
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3279059153
Short name T2415
Test name
Test status
Simulation time 251978151 ps
CPU time 1 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:42:48 PM PDT 24
Peak memory 207024 kb
Host smart-56c647a8-2c51-4812-bddf-ede88f2c66e7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3279059153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3279059153
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2437417536
Short name T1553
Test name
Test status
Simulation time 197536867 ps
CPU time 0.95 seconds
Started Jul 31 05:42:51 PM PDT 24
Finished Jul 31 05:42:52 PM PDT 24
Peak memory 206992 kb
Host smart-22e85620-b551-4dc8-b801-9ed830d9808b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24374
17536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2437417536
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.2033235885
Short name T460
Test name
Test status
Simulation time 6159455669 ps
CPU time 168.57 seconds
Started Jul 31 05:42:50 PM PDT 24
Finished Jul 31 05:45:39 PM PDT 24
Peak memory 215428 kb
Host smart-97facd69-045b-46d7-ab0c-5e99617eaa1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20332
35885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.2033235885
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1622864875
Short name T2446
Test name
Test status
Simulation time 6493456595 ps
CPU time 188.78 seconds
Started Jul 31 05:42:47 PM PDT 24
Finished Jul 31 05:45:56 PM PDT 24
Peak memory 215440 kb
Host smart-b0fb5cf8-e4f7-49eb-b209-008ba8eaadb3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1622864875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1622864875
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3141003985
Short name T500
Test name
Test status
Simulation time 205934043 ps
CPU time 0.93 seconds
Started Jul 31 05:42:50 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 207004 kb
Host smart-aa1d7a81-7289-4714-b5b4-eb51b3574f3b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3141003985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3141003985
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.3548697352
Short name T1897
Test name
Test status
Simulation time 151189838 ps
CPU time 0.86 seconds
Started Jul 31 05:42:49 PM PDT 24
Finished Jul 31 05:42:50 PM PDT 24
Peak memory 207000 kb
Host smart-cff4f2f0-7e0d-4c86-8943-d28ad79317bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35486
97352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.3548697352
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.2924303028
Short name T2579
Test name
Test status
Simulation time 199112728 ps
CPU time 0.98 seconds
Started Jul 31 05:42:50 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 207024 kb
Host smart-bb6249cf-4a79-492e-bbbb-eec57b892bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29243
03028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2924303028
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.53898125
Short name T1066
Test name
Test status
Simulation time 165884345 ps
CPU time 0.87 seconds
Started Jul 31 05:42:50 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 207056 kb
Host smart-95de9201-2f75-4f99-81ed-7c1b1361117c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53898
125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.53898125
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1980572561
Short name T416
Test name
Test status
Simulation time 171311659 ps
CPU time 0.98 seconds
Started Jul 31 05:42:50 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 206964 kb
Host smart-ff16771d-c21d-4ad2-b551-524fa9bf16b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19805
72561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1980572561
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.304049772
Short name T2096
Test name
Test status
Simulation time 171099230 ps
CPU time 0.9 seconds
Started Jul 31 05:42:51 PM PDT 24
Finished Jul 31 05:42:52 PM PDT 24
Peak memory 206992 kb
Host smart-31869524-0eb4-4a32-b965-d1944dd8e4e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30404
9772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.304049772
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1012463740
Short name T1297
Test name
Test status
Simulation time 162171684 ps
CPU time 0.84 seconds
Started Jul 31 05:42:50 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 206960 kb
Host smart-c20110e8-f0b8-4f9d-8e7e-0668d6006476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10124
63740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1012463740
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.699447534
Short name T2485
Test name
Test status
Simulation time 243515266 ps
CPU time 1.04 seconds
Started Jul 31 05:42:50 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 207032 kb
Host smart-22d979a3-10b6-4c27-8a53-9c2bcd56dc84
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=699447534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.699447534
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3328949922
Short name T1562
Test name
Test status
Simulation time 142715981 ps
CPU time 0.94 seconds
Started Jul 31 05:42:50 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 206992 kb
Host smart-9329012a-f29f-419f-8e4f-d808ef5240b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33289
49922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3328949922
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.2378699217
Short name T2164
Test name
Test status
Simulation time 37620424 ps
CPU time 0.68 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 206960 kb
Host smart-3a262d36-ad7e-4302-83e7-3613bd3ef8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23786
99217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.2378699217
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3310848820
Short name T1657
Test name
Test status
Simulation time 19252809517 ps
CPU time 45.87 seconds
Started Jul 31 05:42:51 PM PDT 24
Finished Jul 31 05:43:37 PM PDT 24
Peak memory 215432 kb
Host smart-1434dc51-7d6a-4304-9adf-25afd6061dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33108
48820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3310848820
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.3614350827
Short name T1811
Test name
Test status
Simulation time 189033654 ps
CPU time 0.9 seconds
Started Jul 31 05:42:54 PM PDT 24
Finished Jul 31 05:42:55 PM PDT 24
Peak memory 207052 kb
Host smart-8aecfd62-8462-416f-96fc-b26084a41c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36143
50827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.3614350827
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.1899044919
Short name T2863
Test name
Test status
Simulation time 235900438 ps
CPU time 1.02 seconds
Started Jul 31 05:42:53 PM PDT 24
Finished Jul 31 05:42:54 PM PDT 24
Peak memory 206964 kb
Host smart-b0e94705-6ffc-4d09-bbd3-5e7e0b0ef449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18990
44919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.1899044919
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.1840588063
Short name T1308
Test name
Test status
Simulation time 180690589 ps
CPU time 0.87 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 206976 kb
Host smart-40900535-7c5e-4bec-b9bc-0245cb94ce2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18405
88063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1840588063
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.2827665224
Short name T568
Test name
Test status
Simulation time 182379170 ps
CPU time 0.9 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 206916 kb
Host smart-8680ebfe-fdf1-4d80-a39e-878a81e21596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28276
65224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2827665224
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1622225325
Short name T2207
Test name
Test status
Simulation time 197851180 ps
CPU time 0.9 seconds
Started Jul 31 05:42:51 PM PDT 24
Finished Jul 31 05:42:52 PM PDT 24
Peak memory 207000 kb
Host smart-2b4e2db3-a81c-454d-a5c8-64d912dd4a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16222
25325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1622225325
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.3693907845
Short name T2191
Test name
Test status
Simulation time 150074221 ps
CPU time 0.83 seconds
Started Jul 31 05:42:55 PM PDT 24
Finished Jul 31 05:42:56 PM PDT 24
Peak memory 206960 kb
Host smart-881d918d-5cb4-49a2-8aed-b2e6c11c5cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36939
07845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3693907845
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2213057408
Short name T2788
Test name
Test status
Simulation time 229769855 ps
CPU time 0.92 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:43:00 PM PDT 24
Peak memory 206976 kb
Host smart-0733e238-c104-4f7b-baac-b19dc34b0eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22130
57408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2213057408
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2104007351
Short name T963
Test name
Test status
Simulation time 239384258 ps
CPU time 1.05 seconds
Started Jul 31 05:42:58 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 206976 kb
Host smart-97b5be0c-e70f-4b26-8045-0c2dfe0f9fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21040
07351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2104007351
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3333951551
Short name T1857
Test name
Test status
Simulation time 6133153046 ps
CPU time 187.73 seconds
Started Jul 31 05:42:53 PM PDT 24
Finished Jul 31 05:46:00 PM PDT 24
Peak memory 215396 kb
Host smart-9481f413-aefb-415f-963b-4c2f043cbd1d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3333951551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3333951551
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1139045978
Short name T2717
Test name
Test status
Simulation time 192687692 ps
CPU time 0.93 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 206996 kb
Host smart-564fa8d3-5a60-4620-ad3d-a8d9c308a44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11390
45978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1139045978
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3851525545
Short name T1743
Test name
Test status
Simulation time 165686726 ps
CPU time 0.89 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 206968 kb
Host smart-c977ba18-6383-42f3-8b31-bf381fe105dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38515
25545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3851525545
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.2139302055
Short name T391
Test name
Test status
Simulation time 466380562 ps
CPU time 1.47 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:42:54 PM PDT 24
Peak memory 206940 kb
Host smart-35d2a68a-beb1-44c9-8099-b854771d5890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21393
02055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.2139302055
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.4196610805
Short name T557
Test name
Test status
Simulation time 3154459690 ps
CPU time 25.61 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:43:18 PM PDT 24
Peak memory 215388 kb
Host smart-8f514c46-ccd6-48a2-8d75-c0c96557f2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41966
10805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.4196610805
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.913490788
Short name T2517
Test name
Test status
Simulation time 4991040339 ps
CPU time 32.06 seconds
Started Jul 31 05:42:49 PM PDT 24
Finished Jul 31 05:43:22 PM PDT 24
Peak memory 207260 kb
Host smart-ae17ed52-6e38-41f1-9c6c-764c1d659507
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913490788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_host
_handshake.913490788
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.194441491
Short name T574
Test name
Test status
Simulation time 57956676 ps
CPU time 0.69 seconds
Started Jul 31 05:42:57 PM PDT 24
Finished Jul 31 05:42:58 PM PDT 24
Peak memory 207036 kb
Host smart-a757fcd2-f531-432a-9780-f12f4e1a2a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=194441491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.194441491
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.3221098736
Short name T1285
Test name
Test status
Simulation time 3505407853 ps
CPU time 5.1 seconds
Started Jul 31 05:42:54 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 207132 kb
Host smart-58405ffb-8ed7-49b3-aecc-996758af47e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221098736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.3221098736
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3490898063
Short name T1652
Test name
Test status
Simulation time 13444130311 ps
CPU time 17.3 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:43:16 PM PDT 24
Peak memory 207192 kb
Host smart-e4d0dd65-1eef-403a-9798-654a3080ef00
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490898063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3490898063
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.3245193839
Short name T2114
Test name
Test status
Simulation time 23389147326 ps
CPU time 25.49 seconds
Started Jul 31 05:42:53 PM PDT 24
Finished Jul 31 05:43:19 PM PDT 24
Peak memory 207184 kb
Host smart-83aa013d-0fee-4cd5-a45a-2edee177e3cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245193839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_resume.3245193839
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2933522871
Short name T699
Test name
Test status
Simulation time 168306899 ps
CPU time 0.92 seconds
Started Jul 31 05:42:56 PM PDT 24
Finished Jul 31 05:42:57 PM PDT 24
Peak memory 207048 kb
Host smart-6eae4294-3f27-4871-aae7-db4f9fbcbdce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29335
22871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2933522871
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2226086831
Short name T1647
Test name
Test status
Simulation time 172819765 ps
CPU time 0.87 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 206960 kb
Host smart-53f08b3e-706c-44ef-aab2-8b42cd6d3faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22260
86831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2226086831
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.4068414263
Short name T1572
Test name
Test status
Simulation time 510528651 ps
CPU time 1.87 seconds
Started Jul 31 05:42:55 PM PDT 24
Finished Jul 31 05:42:57 PM PDT 24
Peak memory 206976 kb
Host smart-fc48fd2d-22ed-4b76-8272-bc50224c6497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40684
14263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.4068414263
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1599857929
Short name T1592
Test name
Test status
Simulation time 396838013 ps
CPU time 1.25 seconds
Started Jul 31 05:42:53 PM PDT 24
Finished Jul 31 05:42:54 PM PDT 24
Peak memory 207000 kb
Host smart-9091e63e-7ec8-4c6e-8ee4-840bc8968658
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1599857929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1599857929
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.3231146577
Short name T2649
Test name
Test status
Simulation time 20874230425 ps
CPU time 50.76 seconds
Started Jul 31 05:42:54 PM PDT 24
Finished Jul 31 05:43:45 PM PDT 24
Peak memory 207228 kb
Host smart-94507154-ddf0-4486-be34-0f399b1fc720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32311
46577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.3231146577
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_device_timeout.3898075843
Short name T401
Test name
Test status
Simulation time 275020952 ps
CPU time 4.46 seconds
Started Jul 31 05:42:53 PM PDT 24
Finished Jul 31 05:42:58 PM PDT 24
Peak memory 207056 kb
Host smart-1270b515-d3c4-47d2-954f-7929adb0a752
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898075843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.3898075843
Directory /workspace/19.usbdev_device_timeout/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.2428272516
Short name T1276
Test name
Test status
Simulation time 388429047 ps
CPU time 1.32 seconds
Started Jul 31 05:42:55 PM PDT 24
Finished Jul 31 05:42:56 PM PDT 24
Peak memory 206968 kb
Host smart-a119d0ac-5676-4043-9287-33ddbfadbb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24282
72516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.2428272516
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1488772858
Short name T1711
Test name
Test status
Simulation time 156212198 ps
CPU time 0.81 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:42:53 PM PDT 24
Peak memory 206956 kb
Host smart-698d4a7d-c157-4f1e-a4a7-9a8872f4e0d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14887
72858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1488772858
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.1521710278
Short name T1209
Test name
Test status
Simulation time 50493892 ps
CPU time 0.71 seconds
Started Jul 31 05:42:53 PM PDT 24
Finished Jul 31 05:42:54 PM PDT 24
Peak memory 206956 kb
Host smart-10a4a4e3-737d-48b3-86f0-64626407b5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15217
10278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1521710278
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.4234021109
Short name T1311
Test name
Test status
Simulation time 921962776 ps
CPU time 2.3 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:42:54 PM PDT 24
Peak memory 207060 kb
Host smart-03213749-1857-4a24-8f29-f2191086206f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42340
21109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.4234021109
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.681034880
Short name T2116
Test name
Test status
Simulation time 195730902 ps
CPU time 1.6 seconds
Started Jul 31 05:42:56 PM PDT 24
Finished Jul 31 05:42:58 PM PDT 24
Peak memory 207012 kb
Host smart-7515e3a0-5c5d-4374-84c6-5c1468d9b503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68103
4880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.681034880
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.3456039739
Short name T87
Test name
Test status
Simulation time 193449037 ps
CPU time 1 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:01 PM PDT 24
Peak memory 207076 kb
Host smart-d7d4c67b-1c4b-4e97-8261-f0196d09578c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3456039739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.3456039739
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2259267298
Short name T345
Test name
Test status
Simulation time 143772172 ps
CPU time 0.8 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:01 PM PDT 24
Peak memory 206988 kb
Host smart-d9572124-d4f2-478b-8b74-565749c8960b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22592
67298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2259267298
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3073855819
Short name T675
Test name
Test status
Simulation time 277438259 ps
CPU time 1.07 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:43:00 PM PDT 24
Peak memory 207036 kb
Host smart-775e8538-1b2f-4a23-bd6f-87d1ea1f6aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30738
55819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3073855819
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.2132661373
Short name T2330
Test name
Test status
Simulation time 9446016487 ps
CPU time 271.48 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:47:31 PM PDT 24
Peak memory 215428 kb
Host smart-6ef5518c-61ef-4b40-b26a-89f098b33268
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2132661373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2132661373
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.2062855751
Short name T1226
Test name
Test status
Simulation time 7933944561 ps
CPU time 51.91 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:52 PM PDT 24
Peak memory 207164 kb
Host smart-ab55252e-2394-4192-a0fa-592aa5227ab0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2062855751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.2062855751
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.4229234486
Short name T824
Test name
Test status
Simulation time 169189052 ps
CPU time 0.89 seconds
Started Jul 31 05:42:56 PM PDT 24
Finished Jul 31 05:42:57 PM PDT 24
Peak memory 206980 kb
Host smart-2b0ed9d5-aff0-4672-9d88-4d8ce5e7c460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42292
34486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.4229234486
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.4187434162
Short name T2220
Test name
Test status
Simulation time 23288167725 ps
CPU time 26.25 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:27 PM PDT 24
Peak memory 207188 kb
Host smart-19a60561-1ae3-46dd-9b19-dd3931bff16e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41874
34162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.4187434162
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.633515884
Short name T1245
Test name
Test status
Simulation time 3318407070 ps
CPU time 5.11 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:05 PM PDT 24
Peak memory 207120 kb
Host smart-304ba948-5aba-4c94-865c-ddc7b3a497e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63351
5884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.633515884
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1631253456
Short name T312
Test name
Test status
Simulation time 6812099139 ps
CPU time 199.13 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 215404 kb
Host smart-7e6fe575-02c9-498e-be5d-082424943d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16312
53456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1631253456
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.242953510
Short name T1694
Test name
Test status
Simulation time 5317836061 ps
CPU time 152.23 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:45:32 PM PDT 24
Peak memory 215400 kb
Host smart-c7c3acdc-f577-469d-8dd3-17d64ccd9bbf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=242953510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.242953510
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.1656884001
Short name T1927
Test name
Test status
Simulation time 262618883 ps
CPU time 1.02 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:43:00 PM PDT 24
Peak memory 207000 kb
Host smart-9e32eb96-17a7-496c-9bcf-6bce7624b378
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1656884001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.1656884001
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1333845933
Short name T490
Test name
Test status
Simulation time 256951857 ps
CPU time 1.04 seconds
Started Jul 31 05:43:02 PM PDT 24
Finished Jul 31 05:43:03 PM PDT 24
Peak memory 207012 kb
Host smart-f96120a4-12f6-4cb5-8ba7-c1afd2e0d142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13338
45933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1333845933
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.1546574374
Short name T2648
Test name
Test status
Simulation time 4320600938 ps
CPU time 130.93 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:45:10 PM PDT 24
Peak memory 215360 kb
Host smart-c641eb07-038f-4d28-9d4e-c57cdaa9baf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465
74374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.1546574374
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2885161044
Short name T1702
Test name
Test status
Simulation time 6935448601 ps
CPU time 208.11 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:46:27 PM PDT 24
Peak memory 215388 kb
Host smart-afca9e8e-29fe-424b-9dcf-65619a819fe2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2885161044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2885161044
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.4191037891
Short name T1514
Test name
Test status
Simulation time 183761187 ps
CPU time 0.88 seconds
Started Jul 31 05:42:58 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 207032 kb
Host smart-8603db45-d315-414e-b3b0-5811a9448822
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4191037891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.4191037891
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1628721622
Short name T1015
Test name
Test status
Simulation time 146973882 ps
CPU time 0.83 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:43:00 PM PDT 24
Peak memory 206984 kb
Host smart-1e9d480d-755a-4a0f-bb4b-07f8b9bf9b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16287
21622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1628721622
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.1270736578
Short name T2742
Test name
Test status
Simulation time 165919143 ps
CPU time 0.86 seconds
Started Jul 31 05:43:01 PM PDT 24
Finished Jul 31 05:43:02 PM PDT 24
Peak memory 206988 kb
Host smart-d0e29971-c89a-405b-8ef8-8cc141b9a705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12707
36578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.1270736578
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.3618094940
Short name T2138
Test name
Test status
Simulation time 160754326 ps
CPU time 0.88 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:01 PM PDT 24
Peak memory 206980 kb
Host smart-bf734a3a-5cf3-4ef4-ab66-e6b481575de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36180
94940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.3618094940
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1181606283
Short name T286
Test name
Test status
Simulation time 162187327 ps
CPU time 0.87 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:43:00 PM PDT 24
Peak memory 207052 kb
Host smart-b01341d8-3a98-41e8-8563-b68e91279168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11816
06283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1181606283
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.4078607369
Short name T2377
Test name
Test status
Simulation time 197123766 ps
CPU time 0.86 seconds
Started Jul 31 05:42:58 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 206996 kb
Host smart-75f2e9f3-7e64-4ddb-9c08-d1ba2df3a7b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40786
07369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.4078607369
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.1846744285
Short name T832
Test name
Test status
Simulation time 196456642 ps
CPU time 1.02 seconds
Started Jul 31 05:42:58 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 206996 kb
Host smart-6189ea64-7db2-4b90-ad2c-4da4cee5d480
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1846744285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.1846744285
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1001472198
Short name T981
Test name
Test status
Simulation time 186001841 ps
CPU time 0.92 seconds
Started Jul 31 05:43:01 PM PDT 24
Finished Jul 31 05:43:02 PM PDT 24
Peak memory 206952 kb
Host smart-e0498946-5fbd-4bb1-a9e9-33cd407a4639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10014
72198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1001472198
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.2104103924
Short name T1909
Test name
Test status
Simulation time 32643911 ps
CPU time 0.66 seconds
Started Jul 31 05:43:01 PM PDT 24
Finished Jul 31 05:43:02 PM PDT 24
Peak memory 206944 kb
Host smart-a5f6b677-9168-4119-9192-68e0590e9d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21041
03924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.2104103924
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2598202512
Short name T1029
Test name
Test status
Simulation time 21465936325 ps
CPU time 50.83 seconds
Started Jul 31 05:42:56 PM PDT 24
Finished Jul 31 05:43:47 PM PDT 24
Peak memory 215488 kb
Host smart-fc8c1f4c-c828-4977-9088-928dfd0c18ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25982
02512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2598202512
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.281419914
Short name T2546
Test name
Test status
Simulation time 163996679 ps
CPU time 0.9 seconds
Started Jul 31 05:42:57 PM PDT 24
Finished Jul 31 05:42:58 PM PDT 24
Peak memory 206984 kb
Host smart-ed28fa5f-5be3-4356-9e60-9558e88878da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28141
9914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.281419914
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2192772042
Short name T2827
Test name
Test status
Simulation time 242760231 ps
CPU time 1.14 seconds
Started Jul 31 05:42:58 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 206968 kb
Host smart-62ea5d6d-d0a5-4a5f-922a-83c7ad43ce84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21927
72042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2192772042
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3505472790
Short name T2646
Test name
Test status
Simulation time 213658291 ps
CPU time 1.01 seconds
Started Jul 31 05:43:01 PM PDT 24
Finished Jul 31 05:43:02 PM PDT 24
Peak memory 206988 kb
Host smart-a17e9e77-a38e-4818-b825-809702bc2d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35054
72790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3505472790
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2903955976
Short name T1162
Test name
Test status
Simulation time 169546781 ps
CPU time 0.88 seconds
Started Jul 31 05:42:58 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 206988 kb
Host smart-33b7cfa4-3c79-48ef-93d8-61a13b5dd093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29039
55976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2903955976
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.4150913579
Short name T2225
Test name
Test status
Simulation time 200506377 ps
CPU time 1.02 seconds
Started Jul 31 05:43:01 PM PDT 24
Finished Jul 31 05:43:02 PM PDT 24
Peak memory 206992 kb
Host smart-39061694-2ba3-440b-82d3-d27e4bb52ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509
13579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.4150913579
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2865173833
Short name T2699
Test name
Test status
Simulation time 159863116 ps
CPU time 0.85 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:01 PM PDT 24
Peak memory 206972 kb
Host smart-3caab459-dd50-4f3f-9c0f-9befd34aa4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28651
73833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2865173833
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3480124073
Short name T1994
Test name
Test status
Simulation time 194683297 ps
CPU time 0.93 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:01 PM PDT 24
Peak memory 206992 kb
Host smart-984a49c5-3e8f-4286-9f42-83cd8bb4edc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34801
24073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3480124073
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.98363356
Short name T2080
Test name
Test status
Simulation time 219829748 ps
CPU time 1.12 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:01 PM PDT 24
Peak memory 207016 kb
Host smart-6c74c4c9-7251-44f9-afdd-3edfce19df67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98363
356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.98363356
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3114935085
Short name T687
Test name
Test status
Simulation time 3891594447 ps
CPU time 120.11 seconds
Started Jul 31 05:42:58 PM PDT 24
Finished Jul 31 05:44:58 PM PDT 24
Peak memory 215344 kb
Host smart-360d2e8a-f307-4dd2-a0ac-214b32bd08f5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3114935085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3114935085
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.339680382
Short name T2379
Test name
Test status
Simulation time 157928459 ps
CPU time 0.88 seconds
Started Jul 31 05:42:57 PM PDT 24
Finished Jul 31 05:42:58 PM PDT 24
Peak memory 207004 kb
Host smart-3b903d61-3cbb-4c10-9bbc-903ca66910e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33968
0382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.339680382
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.3678823231
Short name T605
Test name
Test status
Simulation time 166375173 ps
CPU time 0.92 seconds
Started Jul 31 05:42:59 PM PDT 24
Finished Jul 31 05:43:00 PM PDT 24
Peak memory 207048 kb
Host smart-54a6ede2-6eb1-4398-9ff7-52ef585be888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36788
23231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3678823231
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.2857564108
Short name T1392
Test name
Test status
Simulation time 1374230620 ps
CPU time 3.61 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:04 PM PDT 24
Peak memory 207028 kb
Host smart-6cc0467e-48b5-4d3e-bcf9-96f3cfcd59b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28575
64108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2857564108
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.4158255286
Short name T817
Test name
Test status
Simulation time 2857379961 ps
CPU time 22.55 seconds
Started Jul 31 05:42:57 PM PDT 24
Finished Jul 31 05:43:20 PM PDT 24
Peak memory 216832 kb
Host smart-91de9175-d22a-4304-b5bd-8e34b7cc1bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41582
55286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.4158255286
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.4046864222
Short name T1385
Test name
Test status
Simulation time 1269013195 ps
CPU time 30.72 seconds
Started Jul 31 05:42:52 PM PDT 24
Finished Jul 31 05:43:23 PM PDT 24
Peak memory 207100 kb
Host smart-6385c92e-2d66-4dcc-afaa-63e06d3ffbca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046864222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.4046864222
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3608883031
Short name T1564
Test name
Test status
Simulation time 38936574 ps
CPU time 0.69 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:39:51 PM PDT 24
Peak memory 207008 kb
Host smart-246f4c6d-21e6-44b1-aa1e-9093b6070655
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3608883031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3608883031
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.448422928
Short name T2237
Test name
Test status
Simulation time 3842307455 ps
CPU time 5.91 seconds
Started Jul 31 05:39:34 PM PDT 24
Finished Jul 31 05:39:41 PM PDT 24
Peak memory 207124 kb
Host smart-ec1036e6-b30f-4d30-8a48-59414ed24ab0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448422928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon
_wake_disconnect.448422928
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3683111517
Short name T2451
Test name
Test status
Simulation time 13354000435 ps
CPU time 17.09 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:54 PM PDT 24
Peak memory 207200 kb
Host smart-f3e24645-61d0-41e4-aa68-a7e108a6c2eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683111517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3683111517
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1784349395
Short name T2792
Test name
Test status
Simulation time 23409130268 ps
CPU time 29.21 seconds
Started Jul 31 05:39:39 PM PDT 24
Finished Jul 31 05:40:08 PM PDT 24
Peak memory 207176 kb
Host smart-8dabb32e-1a10-400b-97d5-cb031e7d9a00
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784349395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.1784349395
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.635711507
Short name T374
Test name
Test status
Simulation time 197541486 ps
CPU time 0.88 seconds
Started Jul 31 05:39:39 PM PDT 24
Finished Jul 31 05:39:41 PM PDT 24
Peak memory 206988 kb
Host smart-8733f1a6-eeb2-4806-8593-75181b13eac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63571
1507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.635711507
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.3406359618
Short name T47
Test name
Test status
Simulation time 146932723 ps
CPU time 0.83 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:38 PM PDT 24
Peak memory 206996 kb
Host smart-53f57065-e58a-4226-becc-2ac2232db392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34063
59618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3406359618
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2294245006
Short name T94
Test name
Test status
Simulation time 155874226 ps
CPU time 0.83 seconds
Started Jul 31 05:39:35 PM PDT 24
Finished Jul 31 05:39:36 PM PDT 24
Peak memory 206972 kb
Host smart-9af98745-5f91-4481-b88a-5cebc85c3ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22942
45006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2294245006
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2784687963
Short name T1710
Test name
Test status
Simulation time 151678755 ps
CPU time 0.84 seconds
Started Jul 31 05:39:37 PM PDT 24
Finished Jul 31 05:39:38 PM PDT 24
Peak memory 206948 kb
Host smart-137b1238-2fbd-4721-b215-85a9e9e88d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27846
87963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2784687963
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.1618058347
Short name T2583
Test name
Test status
Simulation time 496608249 ps
CPU time 1.85 seconds
Started Jul 31 05:39:37 PM PDT 24
Finished Jul 31 05:39:39 PM PDT 24
Peak memory 206980 kb
Host smart-cab5190e-c657-4e95-8f2b-5dac0d732f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16180
58347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1618058347
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3089977932
Short name T1237
Test name
Test status
Simulation time 1221182635 ps
CPU time 3.29 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:40 PM PDT 24
Peak memory 207080 kb
Host smart-df98cd21-c5a6-43df-a5e8-ad3d9228e97e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3089977932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3089977932
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1181430316
Short name T1306
Test name
Test status
Simulation time 18776017677 ps
CPU time 42.14 seconds
Started Jul 31 05:39:33 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 207172 kb
Host smart-0b160e49-7ff5-42b5-8673-0e12777861ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
30316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1181430316
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_device_timeout.1405593772
Short name T986
Test name
Test status
Simulation time 767794066 ps
CPU time 5.49 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 207044 kb
Host smart-188d8dc4-5763-448d-a0c0-52d4e26ce825
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405593772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.1405593772
Directory /workspace/2.usbdev_device_timeout/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.751216252
Short name T1720
Test name
Test status
Simulation time 431227674 ps
CPU time 1.44 seconds
Started Jul 31 05:39:38 PM PDT 24
Finished Jul 31 05:39:39 PM PDT 24
Peak memory 206960 kb
Host smart-b37d9ff3-089b-4d8c-8bc8-d4363e778d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75121
6252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.751216252
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.1898683974
Short name T782
Test name
Test status
Simulation time 143669830 ps
CPU time 0.8 seconds
Started Jul 31 05:39:35 PM PDT 24
Finished Jul 31 05:39:36 PM PDT 24
Peak memory 206960 kb
Host smart-4b00cc2d-1b0c-497a-9c5a-2b040fea4668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18986
83974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1898683974
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.1141710889
Short name T886
Test name
Test status
Simulation time 29751928 ps
CPU time 0.72 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:37 PM PDT 24
Peak memory 206932 kb
Host smart-52942b0d-3184-4502-b275-ea3835c1030a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11417
10889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.1141710889
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1824089474
Short name T1523
Test name
Test status
Simulation time 971698854 ps
CPU time 2.85 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:39 PM PDT 24
Peak memory 207048 kb
Host smart-f6c64ba8-bae1-4d3a-a14d-9c2747f91c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18240
89474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1824089474
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.3274602365
Short name T2048
Test name
Test status
Simulation time 198726196 ps
CPU time 1.3 seconds
Started Jul 31 05:39:34 PM PDT 24
Finished Jul 31 05:39:35 PM PDT 24
Peak memory 207124 kb
Host smart-740d7a3b-e77f-4bdc-9cf1-c77e782826af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32746
02365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3274602365
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.4190088032
Short name T217
Test name
Test status
Simulation time 86209988683 ps
CPU time 137.44 seconds
Started Jul 31 05:39:39 PM PDT 24
Finished Jul 31 05:41:57 PM PDT 24
Peak memory 207180 kb
Host smart-e3a9b197-bb19-4b62-ba05-19f0ddf9c616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190088032 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.4190088032
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1601013100
Short name T326
Test name
Test status
Simulation time 89110466600 ps
CPU time 146.01 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:42:02 PM PDT 24
Peak memory 207260 kb
Host smart-a77cff06-42bc-454b-a887-a723db7d9b7f
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1601013100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1601013100
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.3679251995
Short name T2407
Test name
Test status
Simulation time 119084451017 ps
CPU time 230.6 seconds
Started Jul 31 05:39:38 PM PDT 24
Finished Jul 31 05:43:29 PM PDT 24
Peak memory 207196 kb
Host smart-00af88a0-59a3-4f0d-8740-21fa94057e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679251995 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.3679251995
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3589707179
Short name T703
Test name
Test status
Simulation time 87167748987 ps
CPU time 137.7 seconds
Started Jul 31 05:39:40 PM PDT 24
Finished Jul 31 05:41:57 PM PDT 24
Peak memory 207212 kb
Host smart-9318a6e9-6a96-42a5-9f11-d3d18687ea42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35897
07179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3589707179
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.1621329770
Short name T1451
Test name
Test status
Simulation time 196860341 ps
CPU time 1.08 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:37 PM PDT 24
Peak memory 215296 kb
Host smart-c522e944-1f23-4c90-9f0d-b8534eb9f80f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1621329770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.1621329770
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.1682656189
Short name T2483
Test name
Test status
Simulation time 153366931 ps
CPU time 0.84 seconds
Started Jul 31 05:39:34 PM PDT 24
Finished Jul 31 05:39:35 PM PDT 24
Peak memory 206952 kb
Host smart-d88161fc-26d8-4382-9bb8-a59c71f4ba4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16826
56189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.1682656189
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1793071103
Short name T1742
Test name
Test status
Simulation time 259775460 ps
CPU time 1.1 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:39:37 PM PDT 24
Peak memory 206964 kb
Host smart-834c2291-3c7c-4f94-9358-f51454b78f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17930
71103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1793071103
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.3049137224
Short name T1623
Test name
Test status
Simulation time 6399264262 ps
CPU time 67.67 seconds
Started Jul 31 05:39:36 PM PDT 24
Finished Jul 31 05:40:44 PM PDT 24
Peak memory 216736 kb
Host smart-c95e2e5d-f1b3-4029-b36d-0a4943f6ac97
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3049137224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.3049137224
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.649179085
Short name T97
Test name
Test status
Simulation time 8034868424 ps
CPU time 58.83 seconds
Started Jul 31 05:39:40 PM PDT 24
Finished Jul 31 05:40:39 PM PDT 24
Peak memory 207216 kb
Host smart-d4f30926-96aa-47ce-9d57-fbeb3f4ea5ab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=649179085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.649179085
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.2181612982
Short name T2601
Test name
Test status
Simulation time 200415325 ps
CPU time 0.91 seconds
Started Jul 31 05:39:41 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206992 kb
Host smart-e2cec4a0-2a2d-4530-a0e5-b07a241f52f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21816
12982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.2181612982
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1134263722
Short name T2
Test name
Test status
Simulation time 23355298909 ps
CPU time 32.06 seconds
Started Jul 31 05:39:42 PM PDT 24
Finished Jul 31 05:40:14 PM PDT 24
Peak memory 207192 kb
Host smart-09ada190-c2f0-455b-ae21-80dc8e31d272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11342
63722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1134263722
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.761847553
Short name T884
Test name
Test status
Simulation time 3269242390 ps
CPU time 5.37 seconds
Started Jul 31 05:39:39 PM PDT 24
Finished Jul 31 05:39:45 PM PDT 24
Peak memory 207140 kb
Host smart-dd69956d-4d40-4910-b87e-18f2aa341070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76184
7553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.761847553
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.275379502
Short name T2112
Test name
Test status
Simulation time 7745692234 ps
CPU time 61.51 seconds
Started Jul 31 05:39:38 PM PDT 24
Finished Jul 31 05:40:40 PM PDT 24
Peak memory 217180 kb
Host smart-4b64080e-44f9-4e45-9cde-2db14e75f41c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27537
9502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.275379502
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3956613898
Short name T358
Test name
Test status
Simulation time 4537284586 ps
CPU time 38.34 seconds
Started Jul 31 05:39:38 PM PDT 24
Finished Jul 31 05:40:17 PM PDT 24
Peak memory 207212 kb
Host smart-1cc6d45e-b721-497a-ab9d-b03b612334ab
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3956613898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3956613898
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1025264256
Short name T432
Test name
Test status
Simulation time 243602141 ps
CPU time 1.05 seconds
Started Jul 31 05:39:43 PM PDT 24
Finished Jul 31 05:39:44 PM PDT 24
Peak memory 207024 kb
Host smart-1db30c50-82e1-42cd-b906-6ad01e9de66c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1025264256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1025264256
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2322849822
Short name T2775
Test name
Test status
Simulation time 186727630 ps
CPU time 0.91 seconds
Started Jul 31 05:39:41 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206984 kb
Host smart-ac6ee866-0184-4856-97a8-2112451c74b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23228
49822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2322849822
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.790909786
Short name T903
Test name
Test status
Simulation time 4543692906 ps
CPU time 34.31 seconds
Started Jul 31 05:39:44 PM PDT 24
Finished Jul 31 05:40:18 PM PDT 24
Peak memory 215388 kb
Host smart-e40a5d28-cddd-461d-93f1-cbbc34c43487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79090
9786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.790909786
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.2430626590
Short name T575
Test name
Test status
Simulation time 6647736943 ps
CPU time 65.6 seconds
Started Jul 31 05:39:40 PM PDT 24
Finished Jul 31 05:40:45 PM PDT 24
Peak memory 207196 kb
Host smart-7ce12a88-dc61-4f4b-8a6c-dac883a8f738
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2430626590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.2430626590
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1588795129
Short name T1326
Test name
Test status
Simulation time 182061211 ps
CPU time 0.93 seconds
Started Jul 31 05:39:41 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206988 kb
Host smart-ac5eb621-ce1a-410d-94eb-d9bd7f92ef3f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1588795129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1588795129
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.588895100
Short name T664
Test name
Test status
Simulation time 144331766 ps
CPU time 0.82 seconds
Started Jul 31 05:39:41 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206984 kb
Host smart-966b2732-41d3-474c-8be9-003abf5c2e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58889
5100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.588895100
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2969898466
Short name T2524
Test name
Test status
Simulation time 153697088 ps
CPU time 0.92 seconds
Started Jul 31 05:39:44 PM PDT 24
Finished Jul 31 05:39:45 PM PDT 24
Peak memory 207024 kb
Host smart-a6895f79-a7a6-4caf-9cdd-7f020d377af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29698
98466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2969898466
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3702976162
Short name T2287
Test name
Test status
Simulation time 195234468 ps
CPU time 0.93 seconds
Started Jul 31 05:39:40 PM PDT 24
Finished Jul 31 05:39:41 PM PDT 24
Peak memory 207036 kb
Host smart-10f592cb-6390-484d-83b2-9d3bb2d28aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37029
76162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3702976162
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1543961417
Short name T475
Test name
Test status
Simulation time 255221027 ps
CPU time 1.04 seconds
Started Jul 31 05:39:39 PM PDT 24
Finished Jul 31 05:39:40 PM PDT 24
Peak memory 206980 kb
Host smart-da9f3f48-df1c-42c4-8d86-622c771de019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15439
61417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1543961417
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3731401718
Short name T809
Test name
Test status
Simulation time 155497878 ps
CPU time 0.88 seconds
Started Jul 31 05:39:42 PM PDT 24
Finished Jul 31 05:39:43 PM PDT 24
Peak memory 206988 kb
Host smart-7d6ae47d-d1f6-4f11-b78d-0716c366c706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37314
01718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3731401718
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.844164099
Short name T1381
Test name
Test status
Simulation time 193236077 ps
CPU time 0.98 seconds
Started Jul 31 05:39:41 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206972 kb
Host smart-26c00dc5-6d69-43f2-bd3d-9b8ed230889d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=844164099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.844164099
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.3883072196
Short name T192
Test name
Test status
Simulation time 238382840 ps
CPU time 1.06 seconds
Started Jul 31 05:39:41 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206992 kb
Host smart-ceac1d5e-a3ab-4168-aca6-d12f607e5f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38830
72196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.3883072196
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1885545687
Short name T2540
Test name
Test status
Simulation time 147412807 ps
CPU time 0.83 seconds
Started Jul 31 05:39:40 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206956 kb
Host smart-1d581e1f-3504-4867-9add-401a16ae47d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18855
45687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1885545687
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.1629358644
Short name T1515
Test name
Test status
Simulation time 13694475765 ps
CPU time 36.2 seconds
Started Jul 31 05:39:41 PM PDT 24
Finished Jul 31 05:40:17 PM PDT 24
Peak memory 219820 kb
Host smart-2dfe52ba-b560-4262-8f5c-e47210ccf9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16293
58644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.1629358644
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.2773249001
Short name T2289
Test name
Test status
Simulation time 193972167 ps
CPU time 0.96 seconds
Started Jul 31 05:39:39 PM PDT 24
Finished Jul 31 05:39:40 PM PDT 24
Peak memory 207000 kb
Host smart-a831ead5-3cfc-4661-835a-0a6988a14b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27732
49001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2773249001
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1324199902
Short name T1247
Test name
Test status
Simulation time 254759862 ps
CPU time 0.93 seconds
Started Jul 31 05:39:39 PM PDT 24
Finished Jul 31 05:39:41 PM PDT 24
Peak memory 206992 kb
Host smart-a3b41309-62f8-4df7-b522-7c4b91f3bd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13241
99902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1324199902
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3525544235
Short name T252
Test name
Test status
Simulation time 9558814990 ps
CPU time 67.55 seconds
Started Jul 31 05:39:40 PM PDT 24
Finished Jul 31 05:40:47 PM PDT 24
Peak memory 223556 kb
Host smart-b621f73b-baa0-4623-baca-4732b4f392c6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3525544235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3525544235
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.57570351
Short name T2145
Test name
Test status
Simulation time 12486957296 ps
CPU time 71.21 seconds
Started Jul 31 05:39:39 PM PDT 24
Finished Jul 31 05:40:50 PM PDT 24
Peak memory 223608 kb
Host smart-2321774a-70c4-42b7-a787-c60d1d34a7b0
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=57570351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.57570351
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.1661046243
Short name T858
Test name
Test status
Simulation time 265872483 ps
CPU time 1.02 seconds
Started Jul 31 05:39:41 PM PDT 24
Finished Jul 31 05:39:42 PM PDT 24
Peak memory 206968 kb
Host smart-5ae95bb5-e1be-416a-b044-4656e7b09b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16610
46243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1661046243
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.877444472
Short name T1689
Test name
Test status
Simulation time 249038562 ps
CPU time 1.03 seconds
Started Jul 31 05:39:45 PM PDT 24
Finished Jul 31 05:39:46 PM PDT 24
Peak memory 206984 kb
Host smart-03d52da8-5312-448e-915e-d92163e43ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87744
4472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.877444472
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2110195840
Short name T403
Test name
Test status
Simulation time 255207251 ps
CPU time 0.97 seconds
Started Jul 31 05:39:46 PM PDT 24
Finished Jul 31 05:39:48 PM PDT 24
Peak memory 207000 kb
Host smart-fcb3e413-a9ab-447d-954d-ac9f6ac9b766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21101
95840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2110195840
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.833270787
Short name T1536
Test name
Test status
Simulation time 177282477 ps
CPU time 0.84 seconds
Started Jul 31 05:39:45 PM PDT 24
Finished Jul 31 05:39:46 PM PDT 24
Peak memory 206996 kb
Host smart-0aeb3f35-cb97-4913-9e7f-848419f86d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83327
0787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.833270787
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.313063454
Short name T183
Test name
Test status
Simulation time 425708223 ps
CPU time 1.27 seconds
Started Jul 31 05:39:44 PM PDT 24
Finished Jul 31 05:39:46 PM PDT 24
Peak memory 222984 kb
Host smart-1c0e9d2d-dff6-4f5b-9a22-1947167fb695
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=313063454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.313063454
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.3571262949
Short name T43
Test name
Test status
Simulation time 423853908 ps
CPU time 1.44 seconds
Started Jul 31 05:39:48 PM PDT 24
Finished Jul 31 05:39:49 PM PDT 24
Peak memory 206972 kb
Host smart-b9d46762-6950-49f4-8d1d-b3b6e98b3442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35712
62949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3571262949
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2295629247
Short name T523
Test name
Test status
Simulation time 221029082 ps
CPU time 0.93 seconds
Started Jul 31 05:39:46 PM PDT 24
Finished Jul 31 05:39:47 PM PDT 24
Peak memory 207008 kb
Host smart-737fe22f-4860-43d9-8b1a-458c11a5c67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956
29247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2295629247
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.908755075
Short name T1593
Test name
Test status
Simulation time 178788434 ps
CPU time 0.91 seconds
Started Jul 31 05:39:49 PM PDT 24
Finished Jul 31 05:39:50 PM PDT 24
Peak memory 206940 kb
Host smart-2d4a098a-778c-4cd7-89c0-2c5a30850fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90875
5075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.908755075
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.4093101236
Short name T1223
Test name
Test status
Simulation time 166862715 ps
CPU time 0.88 seconds
Started Jul 31 05:39:45 PM PDT 24
Finished Jul 31 05:39:46 PM PDT 24
Peak memory 206996 kb
Host smart-b61cec4a-343d-4635-938c-94514e1ba287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40931
01236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.4093101236
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.286711389
Short name T1382
Test name
Test status
Simulation time 221063712 ps
CPU time 1.02 seconds
Started Jul 31 05:39:49 PM PDT 24
Finished Jul 31 05:39:51 PM PDT 24
Peak memory 206968 kb
Host smart-d02b6558-9508-40bf-ad75-19c53b86e1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28671
1389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.286711389
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.1491625631
Short name T2294
Test name
Test status
Simulation time 3921823970 ps
CPU time 107.82 seconds
Started Jul 31 05:39:47 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 215420 kb
Host smart-2258e139-530d-481e-9d20-40e47d9c4b09
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1491625631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.1491625631
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.2764423791
Short name T1343
Test name
Test status
Simulation time 146253125 ps
CPU time 0.87 seconds
Started Jul 31 05:39:45 PM PDT 24
Finished Jul 31 05:39:46 PM PDT 24
Peak memory 207020 kb
Host smart-3b12f117-91ea-4b7c-bb78-db7db8b68334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27644
23791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2764423791
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.511092809
Short name T199
Test name
Test status
Simulation time 187454372 ps
CPU time 0.92 seconds
Started Jul 31 05:39:46 PM PDT 24
Finished Jul 31 05:39:48 PM PDT 24
Peak memory 206972 kb
Host smart-779efce3-fd02-4116-9560-646eaf51e249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51109
2809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.511092809
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.2184688925
Short name T2042
Test name
Test status
Simulation time 472370556 ps
CPU time 1.47 seconds
Started Jul 31 05:39:47 PM PDT 24
Finished Jul 31 05:39:48 PM PDT 24
Peak memory 206952 kb
Host smart-e7a9166c-f7f9-4ff7-8d60-451dd7bcb2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846
88925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2184688925
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.171584707
Short name T2365
Test name
Test status
Simulation time 4363750837 ps
CPU time 123.14 seconds
Started Jul 31 05:39:44 PM PDT 24
Finished Jul 31 05:41:47 PM PDT 24
Peak memory 215380 kb
Host smart-81204064-4bbe-429d-9660-13cabb71a4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17158
4707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.171584707
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.2862413517
Short name T1487
Test name
Test status
Simulation time 1169229757 ps
CPU time 25.55 seconds
Started Jul 31 05:39:35 PM PDT 24
Finished Jul 31 05:40:00 PM PDT 24
Peak memory 207120 kb
Host smart-7ab0e52b-7bcb-45f7-a625-af9abefd06ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862413517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host
_handshake.2862413517
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.3898698635
Short name T1863
Test name
Test status
Simulation time 48664495 ps
CPU time 0.67 seconds
Started Jul 31 05:43:08 PM PDT 24
Finished Jul 31 05:43:09 PM PDT 24
Peak memory 207032 kb
Host smart-711cb205-4427-477b-89f9-781141c394a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3898698635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.3898698635
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1947749980
Short name T2615
Test name
Test status
Simulation time 3443029962 ps
CPU time 5.82 seconds
Started Jul 31 05:43:03 PM PDT 24
Finished Jul 31 05:43:09 PM PDT 24
Peak memory 207100 kb
Host smart-eaf91922-4592-44e0-9873-6cc1366aa5e8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947749980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.1947749980
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.1049783049
Short name T12
Test name
Test status
Simulation time 13368686389 ps
CPU time 15.56 seconds
Started Jul 31 05:43:03 PM PDT 24
Finished Jul 31 05:43:18 PM PDT 24
Peak memory 207192 kb
Host smart-9ad0c072-a3e3-4827-bbe6-bc7aa4c2cd0f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049783049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.1049783049
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1023231087
Short name T648
Test name
Test status
Simulation time 23321275985 ps
CPU time 29.84 seconds
Started Jul 31 05:43:03 PM PDT 24
Finished Jul 31 05:43:33 PM PDT 24
Peak memory 207208 kb
Host smart-89a0fda8-d272-4727-8785-7849eed69a9c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023231087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.1023231087
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.3681722489
Short name T2056
Test name
Test status
Simulation time 153974176 ps
CPU time 0.85 seconds
Started Jul 31 05:43:02 PM PDT 24
Finished Jul 31 05:43:03 PM PDT 24
Peak memory 206972 kb
Host smart-c6272e2f-6cbd-4081-a7cc-4d6a3e0642bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36817
22489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3681722489
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.4179543396
Short name T2447
Test name
Test status
Simulation time 155046376 ps
CPU time 0.81 seconds
Started Jul 31 05:43:10 PM PDT 24
Finished Jul 31 05:43:11 PM PDT 24
Peak memory 206944 kb
Host smart-89f2ed73-877e-4542-90ca-8074077a6b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41795
43396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.4179543396
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.1765508538
Short name T2641
Test name
Test status
Simulation time 254926695 ps
CPU time 1.14 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:43:07 PM PDT 24
Peak memory 207004 kb
Host smart-5554f86c-8c7f-4889-92f2-887d4178ec6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17655
08538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.1765508538
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.172328471
Short name T1125
Test name
Test status
Simulation time 799949649 ps
CPU time 2.13 seconds
Started Jul 31 05:43:01 PM PDT 24
Finished Jul 31 05:43:04 PM PDT 24
Peak memory 207012 kb
Host smart-732df9d2-dda5-4123-babe-05611ea0805b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=172328471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.172328471
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2334366177
Short name T1490
Test name
Test status
Simulation time 14129825366 ps
CPU time 30.94 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:43:37 PM PDT 24
Peak memory 207160 kb
Host smart-ad27bc45-36fb-4e71-a06c-1ffd909c1765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23343
66177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2334366177
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_device_timeout.4205998056
Short name T376
Test name
Test status
Simulation time 601362784 ps
CPU time 12.33 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:43:18 PM PDT 24
Peak memory 207040 kb
Host smart-63f1d974-cda1-4fff-872d-9223a23ecdef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205998056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.4205998056
Directory /workspace/20.usbdev_device_timeout/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2132343909
Short name T202
Test name
Test status
Simulation time 367631140 ps
CPU time 1.26 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:43:08 PM PDT 24
Peak memory 206952 kb
Host smart-6b4f38c2-343d-4b21-ac9d-f96e2476616e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21323
43909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2132343909
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2933586382
Short name T590
Test name
Test status
Simulation time 199500493 ps
CPU time 0.93 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:43:07 PM PDT 24
Peak memory 206984 kb
Host smart-67d3a2aa-77f3-4391-8f29-f1e2705966bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29335
86382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2933586382
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.740387426
Short name T911
Test name
Test status
Simulation time 46968324 ps
CPU time 0.78 seconds
Started Jul 31 05:43:02 PM PDT 24
Finished Jul 31 05:43:03 PM PDT 24
Peak memory 206964 kb
Host smart-152b364c-676c-48cb-9f9f-c3b99c352b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74038
7426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.740387426
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3638509197
Short name T1230
Test name
Test status
Simulation time 947925087 ps
CPU time 2.61 seconds
Started Jul 31 05:43:02 PM PDT 24
Finished Jul 31 05:43:05 PM PDT 24
Peak memory 207060 kb
Host smart-734330e9-a3f0-4ec1-b839-60a33ca9e5f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36385
09197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3638509197
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2368663594
Short name T1396
Test name
Test status
Simulation time 193827111 ps
CPU time 2.37 seconds
Started Jul 31 05:43:01 PM PDT 24
Finished Jul 31 05:43:04 PM PDT 24
Peak memory 207076 kb
Host smart-860ea687-fbd6-4161-80c7-f50186644643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23686
63594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2368663594
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.3453368894
Short name T1594
Test name
Test status
Simulation time 171099958 ps
CPU time 0.9 seconds
Started Jul 31 05:43:02 PM PDT 24
Finished Jul 31 05:43:03 PM PDT 24
Peak memory 206980 kb
Host smart-21a05ec8-d849-49e0-a47c-efef685154ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3453368894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3453368894
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.2392955559
Short name T916
Test name
Test status
Simulation time 159892197 ps
CPU time 0.87 seconds
Started Jul 31 05:43:02 PM PDT 24
Finished Jul 31 05:43:03 PM PDT 24
Peak memory 206964 kb
Host smart-c512c784-90e5-4a05-af5a-a2b001f2a332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23929
55559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.2392955559
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.3259037915
Short name T2499
Test name
Test status
Simulation time 185616664 ps
CPU time 0.96 seconds
Started Jul 31 05:43:08 PM PDT 24
Finished Jul 31 05:43:09 PM PDT 24
Peak memory 207020 kb
Host smart-2e7ff0a9-79b3-46c8-9196-cc3a3b21162c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32590
37915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3259037915
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_invalid_sync.2024601282
Short name T569
Test name
Test status
Simulation time 4777013714 ps
CPU time 39.1 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:43:46 PM PDT 24
Peak memory 216776 kb
Host smart-3d8defb5-e41b-46a6-8f08-29e5d2da214b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2024601282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2024601282
Directory /workspace/20.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2680907314
Short name T2162
Test name
Test status
Simulation time 7621821743 ps
CPU time 51.42 seconds
Started Jul 31 05:43:04 PM PDT 24
Finished Jul 31 05:43:56 PM PDT 24
Peak memory 207212 kb
Host smart-ca3f4b08-e5f2-4c99-a6c1-92a59e384a3a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2680907314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2680907314
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.751777934
Short name T1682
Test name
Test status
Simulation time 218866030 ps
CPU time 1 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:10 PM PDT 24
Peak memory 206996 kb
Host smart-046529db-33d4-47ad-8e7c-31967ba4be6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75177
7934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.751777934
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.4040007912
Short name T2204
Test name
Test status
Simulation time 23344281664 ps
CPU time 30.61 seconds
Started Jul 31 05:43:03 PM PDT 24
Finished Jul 31 05:43:34 PM PDT 24
Peak memory 207200 kb
Host smart-6092ed9c-a9b5-4d9e-b091-151602c1e093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40400
07912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.4040007912
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.281636480
Short name T1478
Test name
Test status
Simulation time 3272778910 ps
CPU time 4.72 seconds
Started Jul 31 05:43:00 PM PDT 24
Finished Jul 31 05:43:05 PM PDT 24
Peak memory 207116 kb
Host smart-3f04e330-5da4-488b-8e5b-4dc38366a3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28163
6480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.281636480
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.4242396630
Short name T2315
Test name
Test status
Simulation time 5506140229 ps
CPU time 42.65 seconds
Started Jul 31 05:43:03 PM PDT 24
Finished Jul 31 05:43:45 PM PDT 24
Peak memory 218204 kb
Host smart-6360bd2e-28e1-4184-bea5-4f2268038922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42423
96630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.4242396630
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.1289580211
Short name T1129
Test name
Test status
Simulation time 5953860375 ps
CPU time 181.64 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:46:08 PM PDT 24
Peak memory 215412 kb
Host smart-a8ce7ce1-7f31-49c5-8246-0ae8363bde84
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1289580211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.1289580211
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.3735391488
Short name T2835
Test name
Test status
Simulation time 264587036 ps
CPU time 1 seconds
Started Jul 31 05:43:05 PM PDT 24
Finished Jul 31 05:43:06 PM PDT 24
Peak memory 207012 kb
Host smart-b4e55a00-7af7-4ac2-8e20-7eb9451cc908
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3735391488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3735391488
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.898659528
Short name T1944
Test name
Test status
Simulation time 200626712 ps
CPU time 0.97 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:43:07 PM PDT 24
Peak memory 206984 kb
Host smart-74e6d519-b7ef-4525-95df-95713779fd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89865
9528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.898659528
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.2234642730
Short name T1500
Test name
Test status
Simulation time 5500476230 ps
CPU time 42.91 seconds
Started Jul 31 05:43:03 PM PDT 24
Finished Jul 31 05:43:46 PM PDT 24
Peak memory 216896 kb
Host smart-9f0129b7-9e1d-4990-980d-b86c816afde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22346
42730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.2234642730
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2456918378
Short name T219
Test name
Test status
Simulation time 3506992868 ps
CPU time 100.18 seconds
Started Jul 31 05:43:08 PM PDT 24
Finished Jul 31 05:44:48 PM PDT 24
Peak memory 215420 kb
Host smart-44ddb9db-88fe-4872-82e4-1d6a4cbb3b63
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2456918378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2456918378
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.2947179215
Short name T1438
Test name
Test status
Simulation time 196294230 ps
CPU time 0.9 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:10 PM PDT 24
Peak memory 207024 kb
Host smart-21d08724-1fed-4a1b-9357-c7029ad53ea8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2947179215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.2947179215
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.4165036382
Short name T756
Test name
Test status
Simulation time 140492191 ps
CPU time 0.86 seconds
Started Jul 31 05:43:07 PM PDT 24
Finished Jul 31 05:43:08 PM PDT 24
Peak memory 206976 kb
Host smart-50cda9fd-48b6-491b-b702-22164a585e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41650
36382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.4165036382
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2718301786
Short name T2345
Test name
Test status
Simulation time 192997935 ps
CPU time 0.96 seconds
Started Jul 31 05:43:05 PM PDT 24
Finished Jul 31 05:43:06 PM PDT 24
Peak memory 207016 kb
Host smart-400308f7-f5a6-41ed-bd22-7942e70a8c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27183
01786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2718301786
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2755245507
Short name T446
Test name
Test status
Simulation time 169960138 ps
CPU time 0.89 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:43:07 PM PDT 24
Peak memory 206964 kb
Host smart-fe08de35-cf39-4403-9b28-23757ed7fce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27552
45507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2755245507
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.246383992
Short name T2319
Test name
Test status
Simulation time 166435437 ps
CPU time 0.92 seconds
Started Jul 31 05:43:05 PM PDT 24
Finished Jul 31 05:43:06 PM PDT 24
Peak memory 206988 kb
Host smart-8ed47d6d-d223-41a0-a05c-98929d6ff9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24638
3992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.246383992
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2646442346
Short name T2501
Test name
Test status
Simulation time 196556976 ps
CPU time 0.92 seconds
Started Jul 31 05:43:04 PM PDT 24
Finished Jul 31 05:43:05 PM PDT 24
Peak memory 206992 kb
Host smart-9c9ed38e-310e-48c9-834d-447f7d972876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26464
42346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2646442346
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3427818341
Short name T1506
Test name
Test status
Simulation time 157501822 ps
CPU time 0.88 seconds
Started Jul 31 05:43:10 PM PDT 24
Finished Jul 31 05:43:11 PM PDT 24
Peak memory 207008 kb
Host smart-10e6bfbc-13f9-4817-877e-e6ac664ccf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34278
18341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3427818341
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.496516866
Short name T99
Test name
Test status
Simulation time 235003165 ps
CPU time 1.03 seconds
Started Jul 31 05:43:11 PM PDT 24
Finished Jul 31 05:43:12 PM PDT 24
Peak memory 207044 kb
Host smart-af446ccf-e693-4b79-a5c4-cee81e0dec98
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=496516866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.496516866
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.4108420017
Short name T1688
Test name
Test status
Simulation time 215339779 ps
CPU time 0.93 seconds
Started Jul 31 05:43:08 PM PDT 24
Finished Jul 31 05:43:09 PM PDT 24
Peak memory 206964 kb
Host smart-c2e707c8-cfcb-445e-899e-1fab3d23b52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41084
20017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.4108420017
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1945086024
Short name T2498
Test name
Test status
Simulation time 38009854 ps
CPU time 0.69 seconds
Started Jul 31 05:43:11 PM PDT 24
Finished Jul 31 05:43:12 PM PDT 24
Peak memory 206936 kb
Host smart-708d6193-f93f-40c8-8706-7bbf05b15f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19450
86024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1945086024
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.819018544
Short name T773
Test name
Test status
Simulation time 15376972996 ps
CPU time 38.17 seconds
Started Jul 31 05:43:18 PM PDT 24
Finished Jul 31 05:43:57 PM PDT 24
Peak memory 223640 kb
Host smart-00a03412-8bb0-4f16-8694-c0736adbdf92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81901
8544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.819018544
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2388801349
Short name T1849
Test name
Test status
Simulation time 157726425 ps
CPU time 0.86 seconds
Started Jul 31 05:43:10 PM PDT 24
Finished Jul 31 05:43:10 PM PDT 24
Peak memory 207020 kb
Host smart-fd14250c-80f1-42d4-a447-73aee8bb2ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23888
01349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2388801349
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.1502048039
Short name T596
Test name
Test status
Simulation time 223161933 ps
CPU time 1.03 seconds
Started Jul 31 05:43:13 PM PDT 24
Finished Jul 31 05:43:14 PM PDT 24
Peak memory 206948 kb
Host smart-591f4327-dc37-43b7-82f4-f07a3670d3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15020
48039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.1502048039
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.536564020
Short name T913
Test name
Test status
Simulation time 190158407 ps
CPU time 0.89 seconds
Started Jul 31 05:43:10 PM PDT 24
Finished Jul 31 05:43:11 PM PDT 24
Peak memory 207000 kb
Host smart-7fdb6ac4-d552-4346-807f-56877c6d0c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53656
4020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.536564020
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2186040034
Short name T1574
Test name
Test status
Simulation time 157105733 ps
CPU time 0.9 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:10 PM PDT 24
Peak memory 206972 kb
Host smart-76ca5a21-5eb7-465d-9222-aaf738064599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21860
40034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2186040034
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3498068857
Short name T1878
Test name
Test status
Simulation time 178600192 ps
CPU time 0.88 seconds
Started Jul 31 05:43:10 PM PDT 24
Finished Jul 31 05:43:11 PM PDT 24
Peak memory 206972 kb
Host smart-ee322d79-3026-455c-8418-50edf5256521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34980
68857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3498068857
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3346637204
Short name T610
Test name
Test status
Simulation time 208218344 ps
CPU time 0.97 seconds
Started Jul 31 05:43:07 PM PDT 24
Finished Jul 31 05:43:08 PM PDT 24
Peak memory 207000 kb
Host smart-a2596c6c-59dd-4eca-a803-e605b550b335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33466
37204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3346637204
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1199697998
Short name T2541
Test name
Test status
Simulation time 228984889 ps
CPU time 0.91 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:10 PM PDT 24
Peak memory 207052 kb
Host smart-b5e74095-093e-4105-ac0a-9d0e4e0f3865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11996
97998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1199697998
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.63131939
Short name T549
Test name
Test status
Simulation time 230183165 ps
CPU time 1.02 seconds
Started Jul 31 05:43:08 PM PDT 24
Finished Jul 31 05:43:09 PM PDT 24
Peak memory 207028 kb
Host smart-07f91eba-8ec8-41f8-838f-6d8d18399fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63131
939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.63131939
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1317705557
Short name T1670
Test name
Test status
Simulation time 5141510620 ps
CPU time 53.96 seconds
Started Jul 31 05:43:07 PM PDT 24
Finished Jul 31 05:44:01 PM PDT 24
Peak memory 215412 kb
Host smart-095ac78c-99cc-4b1f-bda8-273c905e326a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1317705557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1317705557
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.4281445609
Short name T1858
Test name
Test status
Simulation time 186771939 ps
CPU time 0.89 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:10 PM PDT 24
Peak memory 207000 kb
Host smart-a4b64871-fe71-4bbd-ba9a-fb13605f6b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42814
45609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.4281445609
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1262088506
Short name T2105
Test name
Test status
Simulation time 165565853 ps
CPU time 0.85 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:10 PM PDT 24
Peak memory 206984 kb
Host smart-3b43e93d-d3d2-4edc-80a7-6cbdd33da2e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12620
88506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1262088506
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.287283718
Short name T859
Test name
Test status
Simulation time 735822938 ps
CPU time 1.89 seconds
Started Jul 31 05:43:11 PM PDT 24
Finished Jul 31 05:43:13 PM PDT 24
Peak memory 206952 kb
Host smart-89ae0024-d5f3-4359-a327-480ef0042d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28728
3718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.287283718
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2583111519
Short name T2505
Test name
Test status
Simulation time 4640175987 ps
CPU time 139.17 seconds
Started Jul 31 05:43:06 PM PDT 24
Finished Jul 31 05:45:25 PM PDT 24
Peak memory 215356 kb
Host smart-034a663b-3679-4d17-8724-7c41c3a5f42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25831
11519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2583111519
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.3304267660
Short name T2781
Test name
Test status
Simulation time 2045791898 ps
CPU time 17.86 seconds
Started Jul 31 05:43:05 PM PDT 24
Finished Jul 31 05:43:23 PM PDT 24
Peak memory 207156 kb
Host smart-27dcdcb3-0f4e-4357-8b42-69c9fae4f475
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304267660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos
t_handshake.3304267660
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1946522297
Short name T1243
Test name
Test status
Simulation time 37432000 ps
CPU time 0.69 seconds
Started Jul 31 05:43:22 PM PDT 24
Finished Jul 31 05:43:23 PM PDT 24
Peak memory 207016 kb
Host smart-a87da073-00bd-41a3-aa06-2a003a3070d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1946522297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1946522297
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.4084865526
Short name T2626
Test name
Test status
Simulation time 3793092521 ps
CPU time 6.25 seconds
Started Jul 31 05:43:08 PM PDT 24
Finished Jul 31 05:43:14 PM PDT 24
Peak memory 207164 kb
Host smart-4dcb0b68-6874-4abc-b5f8-6e1c01cb5edb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084865526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.4084865526
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3713534098
Short name T1064
Test name
Test status
Simulation time 13395063692 ps
CPU time 19.76 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:29 PM PDT 24
Peak memory 207196 kb
Host smart-32060153-c655-442a-91a9-7c8355bf16e6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713534098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3713534098
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.2922905889
Short name T211
Test name
Test status
Simulation time 23336586641 ps
CPU time 32.88 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:42 PM PDT 24
Peak memory 207196 kb
Host smart-48bb3fce-55e8-4c39-ad5b-79aef7f0bcf5
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922905889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.2922905889
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1577909680
Short name T1030
Test name
Test status
Simulation time 169844938 ps
CPU time 0.86 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:10 PM PDT 24
Peak memory 206976 kb
Host smart-7c715ad9-716e-424f-be5b-c6d27e118805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15779
09680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1577909680
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.2354722209
Short name T1258
Test name
Test status
Simulation time 141738932 ps
CPU time 0.84 seconds
Started Jul 31 05:43:20 PM PDT 24
Finished Jul 31 05:43:20 PM PDT 24
Peak memory 206996 kb
Host smart-a7c327a5-5ec8-4381-8810-15f852d1f6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23547
22209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.2354722209
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2338901183
Short name T775
Test name
Test status
Simulation time 229349116 ps
CPU time 1.08 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:10 PM PDT 24
Peak memory 206976 kb
Host smart-88506080-3a90-40cd-b795-5447c7e2aadc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23389
01183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2338901183
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2426449236
Short name T1770
Test name
Test status
Simulation time 1116365151 ps
CPU time 2.77 seconds
Started Jul 31 05:43:12 PM PDT 24
Finished Jul 31 05:43:15 PM PDT 24
Peak memory 207120 kb
Host smart-eeae8d5c-d1f3-43df-9e3b-48125377eced
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2426449236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2426449236
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_timeout.2717738689
Short name T545
Test name
Test status
Simulation time 295384591 ps
CPU time 4.66 seconds
Started Jul 31 05:43:11 PM PDT 24
Finished Jul 31 05:43:16 PM PDT 24
Peak memory 207100 kb
Host smart-85be91d9-60a2-453c-9876-1f202c22b37a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717738689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.2717738689
Directory /workspace/21.usbdev_device_timeout/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.1862850092
Short name T284
Test name
Test status
Simulation time 349361111 ps
CPU time 1.38 seconds
Started Jul 31 05:43:11 PM PDT 24
Finished Jul 31 05:43:13 PM PDT 24
Peak memory 206952 kb
Host smart-936d468e-6afd-49bb-a57c-33fdbc0c8737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18628
50092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.1862850092
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1831852738
Short name T2245
Test name
Test status
Simulation time 142895901 ps
CPU time 0.86 seconds
Started Jul 31 05:43:10 PM PDT 24
Finished Jul 31 05:43:11 PM PDT 24
Peak memory 206968 kb
Host smart-88abf352-3c35-451c-a5e1-0b5058849f7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18318
52738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1831852738
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2088882453
Short name T1047
Test name
Test status
Simulation time 47127355 ps
CPU time 0.7 seconds
Started Jul 31 05:43:10 PM PDT 24
Finished Jul 31 05:43:11 PM PDT 24
Peak memory 206940 kb
Host smart-86e6e678-46b3-4bbe-b986-d98eca69275d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20888
82453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2088882453
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3722320851
Short name T805
Test name
Test status
Simulation time 992580772 ps
CPU time 2.66 seconds
Started Jul 31 05:43:11 PM PDT 24
Finished Jul 31 05:43:13 PM PDT 24
Peak memory 207116 kb
Host smart-d169c9d6-5772-49d6-b219-b70bb1080b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37223
20851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3722320851
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.1831986587
Short name T1412
Test name
Test status
Simulation time 377278972 ps
CPU time 2.9 seconds
Started Jul 31 05:43:10 PM PDT 24
Finished Jul 31 05:43:13 PM PDT 24
Peak memory 207092 kb
Host smart-0966268b-ea96-4171-af96-1824a2b47b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18319
86587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.1831986587
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3723933111
Short name T1090
Test name
Test status
Simulation time 195725831 ps
CPU time 1.05 seconds
Started Jul 31 05:43:13 PM PDT 24
Finished Jul 31 05:43:14 PM PDT 24
Peak memory 215296 kb
Host smart-d9e0fad4-4282-4a45-8a70-3c5317c46b4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3723933111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3723933111
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.1746831606
Short name T2837
Test name
Test status
Simulation time 138685743 ps
CPU time 0.83 seconds
Started Jul 31 05:43:13 PM PDT 24
Finished Jul 31 05:43:14 PM PDT 24
Peak memory 206924 kb
Host smart-c414b3ed-b41f-469d-849a-152e17083257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17468
31606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.1746831606
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1090511684
Short name T28
Test name
Test status
Simulation time 211040681 ps
CPU time 0.94 seconds
Started Jul 31 05:43:12 PM PDT 24
Finished Jul 31 05:43:13 PM PDT 24
Peak memory 207004 kb
Host smart-52fffa3e-a6e4-4f0a-b48d-360f1b62250f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10905
11684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1090511684
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.1632939876
Short name T1559
Test name
Test status
Simulation time 5895568285 ps
CPU time 168.74 seconds
Started Jul 31 05:43:13 PM PDT 24
Finished Jul 31 05:46:02 PM PDT 24
Peak memory 215456 kb
Host smart-32badfa9-256b-4557-b9e0-7d6a638296a5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1632939876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1632939876
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.1019237758
Short name T831
Test name
Test status
Simulation time 10283844711 ps
CPU time 68.06 seconds
Started Jul 31 05:43:15 PM PDT 24
Finished Jul 31 05:44:23 PM PDT 24
Peak memory 207156 kb
Host smart-ce330267-5414-485b-ae3f-d3ff19469479
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1019237758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.1019237758
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.862996614
Short name T2364
Test name
Test status
Simulation time 257565347 ps
CPU time 1.06 seconds
Started Jul 31 05:43:13 PM PDT 24
Finished Jul 31 05:43:14 PM PDT 24
Peak memory 207048 kb
Host smart-5f3f8485-cb48-4e3e-a430-64b6589fe37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86299
6614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.862996614
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3703481863
Short name T1127
Test name
Test status
Simulation time 23330844182 ps
CPU time 33.93 seconds
Started Jul 31 05:43:15 PM PDT 24
Finished Jul 31 05:43:49 PM PDT 24
Peak memory 207164 kb
Host smart-d9932a13-8977-4cca-92ff-62423c0e9160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37034
81863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3703481863
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.2361749962
Short name T781
Test name
Test status
Simulation time 3284170676 ps
CPU time 5.57 seconds
Started Jul 31 05:43:12 PM PDT 24
Finished Jul 31 05:43:18 PM PDT 24
Peak memory 207100 kb
Host smart-90f2f411-962e-4f63-b37f-300e3a23dacf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23617
49962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.2361749962
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.796209450
Short name T1600
Test name
Test status
Simulation time 5496341262 ps
CPU time 40.76 seconds
Started Jul 31 05:43:24 PM PDT 24
Finished Jul 31 05:44:05 PM PDT 24
Peak memory 223596 kb
Host smart-58e7db1f-2c86-4821-be19-c0a8e06b9584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79620
9450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.796209450
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1606969176
Short name T293
Test name
Test status
Simulation time 5175665609 ps
CPU time 152.47 seconds
Started Jul 31 05:43:12 PM PDT 24
Finished Jul 31 05:45:45 PM PDT 24
Peak memory 215436 kb
Host smart-eb607d8e-6105-4707-b61f-7b22ef3de365
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1606969176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1606969176
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.2592794254
Short name T1624
Test name
Test status
Simulation time 251004202 ps
CPU time 0.99 seconds
Started Jul 31 05:43:24 PM PDT 24
Finished Jul 31 05:43:25 PM PDT 24
Peak memory 207012 kb
Host smart-d4e49c9b-50d0-4300-a1be-087be957b751
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2592794254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.2592794254
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.524167364
Short name T651
Test name
Test status
Simulation time 233949560 ps
CPU time 1.02 seconds
Started Jul 31 05:43:17 PM PDT 24
Finished Jul 31 05:43:18 PM PDT 24
Peak memory 206988 kb
Host smart-303725db-3019-4248-91f8-f4c959609fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52416
7364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.524167364
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.2855675937
Short name T2351
Test name
Test status
Simulation time 4071142096 ps
CPU time 122.09 seconds
Started Jul 31 05:43:16 PM PDT 24
Finished Jul 31 05:45:18 PM PDT 24
Peak memory 215372 kb
Host smart-5f51932f-e709-49c6-ba22-9c1caefc4a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28556
75937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.2855675937
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1070746143
Short name T1395
Test name
Test status
Simulation time 5013859128 ps
CPU time 155.6 seconds
Started Jul 31 05:43:14 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 215388 kb
Host smart-c64a1192-486d-4794-ae8e-d7add0480534
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1070746143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1070746143
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.360830816
Short name T474
Test name
Test status
Simulation time 189355816 ps
CPU time 0.89 seconds
Started Jul 31 05:43:14 PM PDT 24
Finished Jul 31 05:43:15 PM PDT 24
Peak memory 207024 kb
Host smart-3833c143-bf4e-41d9-babc-7c64a59a8e00
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=360830816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.360830816
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.942241105
Short name T2307
Test name
Test status
Simulation time 148749405 ps
CPU time 0.83 seconds
Started Jul 31 05:43:19 PM PDT 24
Finished Jul 31 05:43:20 PM PDT 24
Peak memory 206984 kb
Host smart-eca60d71-127f-4ace-903e-4d36d7c411bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94224
1105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.942241105
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.704610595
Short name T2774
Test name
Test status
Simulation time 236486584 ps
CPU time 0.92 seconds
Started Jul 31 05:43:15 PM PDT 24
Finished Jul 31 05:43:16 PM PDT 24
Peak memory 207000 kb
Host smart-5f5a55c3-59ca-46a2-a2bc-1f2a9a79a8b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70461
0595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.704610595
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.3836859118
Short name T2238
Test name
Test status
Simulation time 167558856 ps
CPU time 0.94 seconds
Started Jul 31 05:43:16 PM PDT 24
Finished Jul 31 05:43:17 PM PDT 24
Peak memory 206992 kb
Host smart-df9b136d-3344-43c5-a2f4-1babdaa43cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38368
59118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.3836859118
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.2187341804
Short name T341
Test name
Test status
Simulation time 173793630 ps
CPU time 0.85 seconds
Started Jul 31 05:43:24 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 207020 kb
Host smart-576fa4be-99b2-404a-b13c-49cd859604fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21873
41804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2187341804
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.4113777125
Short name T2084
Test name
Test status
Simulation time 207296768 ps
CPU time 0.9 seconds
Started Jul 31 05:43:24 PM PDT 24
Finished Jul 31 05:43:25 PM PDT 24
Peak memory 207028 kb
Host smart-817992ba-fc8b-4459-8d52-9c9337d8e6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
77125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.4113777125
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1638366649
Short name T749
Test name
Test status
Simulation time 153807848 ps
CPU time 0.92 seconds
Started Jul 31 05:43:16 PM PDT 24
Finished Jul 31 05:43:17 PM PDT 24
Peak memory 206968 kb
Host smart-189dc5d4-ad21-427b-9cbe-3c092a48a887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16383
66649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1638366649
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.660277855
Short name T2461
Test name
Test status
Simulation time 222427146 ps
CPU time 1.03 seconds
Started Jul 31 05:43:14 PM PDT 24
Finished Jul 31 05:43:15 PM PDT 24
Peak memory 206996 kb
Host smart-7bd998d9-17d6-46c8-9aab-c4d33468e5da
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=660277855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.660277855
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3718837133
Short name T35
Test name
Test status
Simulation time 146493933 ps
CPU time 0.88 seconds
Started Jul 31 05:43:12 PM PDT 24
Finished Jul 31 05:43:13 PM PDT 24
Peak memory 206984 kb
Host smart-c73f9f99-4f05-4eed-90c1-aa09fc9258d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37188
37133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3718837133
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1564401364
Short name T2755
Test name
Test status
Simulation time 75048517 ps
CPU time 0.73 seconds
Started Jul 31 05:43:19 PM PDT 24
Finished Jul 31 05:43:19 PM PDT 24
Peak memory 206932 kb
Host smart-4b407659-68ca-4d26-b46f-701287c1ab7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15644
01364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1564401364
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.850684569
Short name T270
Test name
Test status
Simulation time 7455510703 ps
CPU time 19.06 seconds
Started Jul 31 05:43:16 PM PDT 24
Finished Jul 31 05:43:35 PM PDT 24
Peak memory 215404 kb
Host smart-0efacd34-c3d2-4552-85b0-8f96b39b1004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85068
4569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.850684569
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3658806768
Short name T479
Test name
Test status
Simulation time 168252785 ps
CPU time 0.92 seconds
Started Jul 31 05:43:16 PM PDT 24
Finished Jul 31 05:43:17 PM PDT 24
Peak memory 207024 kb
Host smart-9deeb4c3-daec-4fef-bad4-2843cc80e9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36588
06768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3658806768
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1123682907
Short name T1045
Test name
Test status
Simulation time 203771595 ps
CPU time 0.96 seconds
Started Jul 31 05:43:16 PM PDT 24
Finished Jul 31 05:43:17 PM PDT 24
Peak memory 206980 kb
Host smart-169c6f66-f9e5-49a8-a05e-ac5a674264f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11236
82907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1123682907
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2734101638
Short name T503
Test name
Test status
Simulation time 160491158 ps
CPU time 0.94 seconds
Started Jul 31 05:43:15 PM PDT 24
Finished Jul 31 05:43:16 PM PDT 24
Peak memory 206992 kb
Host smart-f3bd4e29-8390-4197-8112-d7540d8fdda7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27341
01638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2734101638
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.1072819679
Short name T2013
Test name
Test status
Simulation time 157814284 ps
CPU time 0.85 seconds
Started Jul 31 05:43:15 PM PDT 24
Finished Jul 31 05:43:16 PM PDT 24
Peak memory 206996 kb
Host smart-4e20e5fe-fc03-42b4-86c2-7df33aa6b6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10728
19679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.1072819679
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2830674831
Short name T2637
Test name
Test status
Simulation time 187341182 ps
CPU time 0.91 seconds
Started Jul 31 05:43:15 PM PDT 24
Finished Jul 31 05:43:16 PM PDT 24
Peak memory 206960 kb
Host smart-9bbaf49e-7d05-4edb-88e5-bfdc8e789b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28306
74831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2830674831
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2686417782
Short name T2392
Test name
Test status
Simulation time 167989067 ps
CPU time 0.86 seconds
Started Jul 31 05:43:14 PM PDT 24
Finished Jul 31 05:43:15 PM PDT 24
Peak memory 206952 kb
Host smart-b6b3edc4-1761-41d1-b8f0-80a6350c9d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26864
17782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2686417782
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3245747079
Short name T2018
Test name
Test status
Simulation time 178660231 ps
CPU time 0.88 seconds
Started Jul 31 05:43:24 PM PDT 24
Finished Jul 31 05:43:25 PM PDT 24
Peak memory 207024 kb
Host smart-758f17f1-bf02-4761-a0ee-87284dc0f11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32457
47079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3245747079
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1063027514
Short name T1616
Test name
Test status
Simulation time 232921154 ps
CPU time 1.12 seconds
Started Jul 31 05:43:14 PM PDT 24
Finished Jul 31 05:43:15 PM PDT 24
Peak memory 207008 kb
Host smart-a04d776f-9684-4cf3-b096-72fccb66eb78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10630
27514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1063027514
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3492620644
Short name T1508
Test name
Test status
Simulation time 4725763683 ps
CPU time 50.1 seconds
Started Jul 31 05:43:14 PM PDT 24
Finished Jul 31 05:44:04 PM PDT 24
Peak memory 216952 kb
Host smart-c008071d-00e9-45cb-8b1f-8f77b7ea0d64
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3492620644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3492620644
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.363231371
Short name T2370
Test name
Test status
Simulation time 173804652 ps
CPU time 0.87 seconds
Started Jul 31 05:43:12 PM PDT 24
Finished Jul 31 05:43:13 PM PDT 24
Peak memory 206976 kb
Host smart-28715952-d599-48aa-9f35-a0ea9fc35d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36323
1371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.363231371
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1294556187
Short name T2487
Test name
Test status
Simulation time 163758319 ps
CPU time 0.88 seconds
Started Jul 31 05:43:19 PM PDT 24
Finished Jul 31 05:43:20 PM PDT 24
Peak memory 206996 kb
Host smart-fd1cc8d9-4c74-4c57-86c9-28ca52c99159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12945
56187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1294556187
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.369415941
Short name T317
Test name
Test status
Simulation time 1195464416 ps
CPU time 2.88 seconds
Started Jul 31 05:43:21 PM PDT 24
Finished Jul 31 05:43:24 PM PDT 24
Peak memory 207016 kb
Host smart-c3679dce-4f8f-409d-87e3-92cb102c39d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36941
5941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.369415941
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3334693773
Short name T2386
Test name
Test status
Simulation time 5485633972 ps
CPU time 59.87 seconds
Started Jul 31 05:43:20 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 207212 kb
Host smart-d31425c8-7a8b-4f7c-a87e-a4a51c9f5b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33346
93773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3334693773
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.1345860635
Short name T2168
Test name
Test status
Simulation time 1182363800 ps
CPU time 26.92 seconds
Started Jul 31 05:43:09 PM PDT 24
Finished Jul 31 05:43:36 PM PDT 24
Peak memory 207124 kb
Host smart-5810ecf1-777d-42a7-b493-4ea277c17e20
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345860635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.1345860635
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2813819842
Short name T860
Test name
Test status
Simulation time 39056586 ps
CPU time 0.65 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:43:33 PM PDT 24
Peak memory 207032 kb
Host smart-bfd81c62-3cf3-47c9-9553-f9bb1aa32ca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2813819842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2813819842
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.2999824457
Short name T2107
Test name
Test status
Simulation time 3963745918 ps
CPU time 7.09 seconds
Started Jul 31 05:43:20 PM PDT 24
Finished Jul 31 05:43:27 PM PDT 24
Peak memory 207108 kb
Host smart-728e4a98-06ad-498b-bd61-f2ca57fe1777
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999824457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.2999824457
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.3863782911
Short name T435
Test name
Test status
Simulation time 13340545785 ps
CPU time 14.49 seconds
Started Jul 31 05:43:25 PM PDT 24
Finished Jul 31 05:43:39 PM PDT 24
Peak memory 207228 kb
Host smart-06c47bac-d8a3-46a2-9b18-649e9915f9e8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863782911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.3863782911
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.4274807698
Short name T1398
Test name
Test status
Simulation time 23402945127 ps
CPU time 27.99 seconds
Started Jul 31 05:43:21 PM PDT 24
Finished Jul 31 05:43:49 PM PDT 24
Peak memory 207192 kb
Host smart-7f5022b9-b6e3-4031-ac24-f1af30c62fcb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274807698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_resume.4274807698
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1250221162
Short name T1817
Test name
Test status
Simulation time 148141290 ps
CPU time 0.86 seconds
Started Jul 31 05:43:25 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 207004 kb
Host smart-102ad824-47eb-424e-9d80-b617aa62b6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12502
21162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1250221162
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1080382215
Short name T2664
Test name
Test status
Simulation time 416739078 ps
CPU time 1.45 seconds
Started Jul 31 05:43:24 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 207024 kb
Host smart-21a7ca3d-3e30-4775-bcb8-4b0c12e8e164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803
82215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1080382215
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.2500903864
Short name T1566
Test name
Test status
Simulation time 542652143 ps
CPU time 1.69 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:43:32 PM PDT 24
Peak memory 206996 kb
Host smart-a58289d4-f8e1-41a3-9d4c-2ab6a44767da
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2500903864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.2500903864
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.1503066150
Short name T2158
Test name
Test status
Simulation time 20735400249 ps
CPU time 53.41 seconds
Started Jul 31 05:43:24 PM PDT 24
Finished Jul 31 05:44:17 PM PDT 24
Peak memory 207140 kb
Host smart-e250291a-fcba-439e-9b7f-5967dd7923eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15030
66150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1503066150
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_device_timeout.706237050
Short name T853
Test name
Test status
Simulation time 1461821062 ps
CPU time 35.47 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:44:02 PM PDT 24
Peak memory 207056 kb
Host smart-f4eb42d4-3fd8-491e-85f5-c66aaaadd677
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706237050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.706237050
Directory /workspace/22.usbdev_device_timeout/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.397205276
Short name T1936
Test name
Test status
Simulation time 482471919 ps
CPU time 1.48 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 206952 kb
Host smart-499b7154-9674-43fa-9250-30c5b1558bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39720
5276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.397205276
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1428913752
Short name T665
Test name
Test status
Simulation time 134514791 ps
CPU time 0.87 seconds
Started Jul 31 05:43:25 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 206968 kb
Host smart-e1ce7bf3-11dd-4f05-bebd-310d00237cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14289
13752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1428913752
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.2610907995
Short name T793
Test name
Test status
Simulation time 29473537 ps
CPU time 0.72 seconds
Started Jul 31 05:43:25 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 206912 kb
Host smart-37eeebea-e6fc-4776-b74e-b6b86dd64ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26109
07995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2610907995
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3330738728
Short name T2593
Test name
Test status
Simulation time 1039776163 ps
CPU time 2.69 seconds
Started Jul 31 05:43:25 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 207056 kb
Host smart-f0a5a776-05a1-4c7e-846a-99fd026d169e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33307
38728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3330738728
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3782487179
Short name T2137
Test name
Test status
Simulation time 296437333 ps
CPU time 2.44 seconds
Started Jul 31 05:43:24 PM PDT 24
Finished Jul 31 05:43:27 PM PDT 24
Peak memory 207048 kb
Host smart-15fe0685-4fd6-4796-9415-9fd212946b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37824
87179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3782487179
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.1845706024
Short name T1191
Test name
Test status
Simulation time 236062286 ps
CPU time 1.27 seconds
Started Jul 31 05:43:28 PM PDT 24
Finished Jul 31 05:43:29 PM PDT 24
Peak memory 215260 kb
Host smart-ce5a3aa8-4730-4af9-9ac1-179f7f6d1c57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1845706024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1845706024
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1944855447
Short name T2046
Test name
Test status
Simulation time 146597266 ps
CPU time 0.84 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:43:27 PM PDT 24
Peak memory 206964 kb
Host smart-08dfe043-af62-4cb8-bac7-ced0ed2217fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19448
55447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1944855447
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3368169283
Short name T780
Test name
Test status
Simulation time 241440965 ps
CPU time 1.05 seconds
Started Jul 31 05:43:27 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 206964 kb
Host smart-a6c1f24b-eef8-4f0d-9e58-99ee0e12f805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33681
69283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3368169283
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.3019520587
Short name T1342
Test name
Test status
Simulation time 9209148166 ps
CPU time 95.3 seconds
Started Jul 31 05:43:28 PM PDT 24
Finished Jul 31 05:45:03 PM PDT 24
Peak memory 216904 kb
Host smart-73dda8b3-72c9-4098-946e-bfb491a65303
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3019520587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.3019520587
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.68640927
Short name T1681
Test name
Test status
Simulation time 13923574817 ps
CPU time 88.61 seconds
Started Jul 31 05:43:29 PM PDT 24
Finished Jul 31 05:44:57 PM PDT 24
Peak memory 207176 kb
Host smart-b2f4fa05-53c5-4d97-927f-6d8f00c2ded2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=68640927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.68640927
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.2812140526
Short name T1233
Test name
Test status
Simulation time 176163905 ps
CPU time 0.92 seconds
Started Jul 31 05:43:27 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 206992 kb
Host smart-3a713b2e-cf25-4b90-b07c-b6aa01f7072d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28121
40526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.2812140526
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1187991172
Short name T1089
Test name
Test status
Simulation time 23422863944 ps
CPU time 26.21 seconds
Started Jul 31 05:43:25 PM PDT 24
Finished Jul 31 05:43:52 PM PDT 24
Peak memory 207220 kb
Host smart-f1a4bdad-5e12-45ec-ac21-2b404d43581b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11879
91172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1187991172
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3641199161
Short name T2068
Test name
Test status
Simulation time 3311208744 ps
CPU time 4.99 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:43:32 PM PDT 24
Peak memory 207140 kb
Host smart-3b78637c-5589-4a09-829c-0933124fbea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36411
99161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3641199161
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.3185243520
Short name T1442
Test name
Test status
Simulation time 6703112627 ps
CPU time 196.34 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:46:43 PM PDT 24
Peak memory 215420 kb
Host smart-d3e9add9-e4a2-402d-a02e-41722bc7c3a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31852
43520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.3185243520
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.3997436194
Short name T1687
Test name
Test status
Simulation time 4374687408 ps
CPU time 122.8 seconds
Started Jul 31 05:43:24 PM PDT 24
Finished Jul 31 05:45:26 PM PDT 24
Peak memory 215388 kb
Host smart-aeabcae9-b05f-4404-ac37-8e123b2732bc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3997436194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.3997436194
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.168618374
Short name T2858
Test name
Test status
Simulation time 250570129 ps
CPU time 1.02 seconds
Started Jul 31 05:43:25 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 206976 kb
Host smart-6b87ba0d-ec58-4dff-a65f-93a3d0c3a259
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=168618374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.168618374
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2304011138
Short name T351
Test name
Test status
Simulation time 201894978 ps
CPU time 0.99 seconds
Started Jul 31 05:43:29 PM PDT 24
Finished Jul 31 05:43:30 PM PDT 24
Peak memory 206980 kb
Host smart-a8247f41-3028-41a8-ac96-c80ef417ba41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23040
11138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2304011138
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.3628558721
Short name T1111
Test name
Test status
Simulation time 3815821111 ps
CPU time 40.03 seconds
Started Jul 31 05:43:27 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 216972 kb
Host smart-ee536192-2e41-421e-9d53-11bdacbec8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36285
58721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.3628558721
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1976633514
Short name T1042
Test name
Test status
Simulation time 6360075086 ps
CPU time 64.37 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 207204 kb
Host smart-38018aac-df5d-46f4-b1dd-a2a4122dbd7d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1976633514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1976633514
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1766363564
Short name T1018
Test name
Test status
Simulation time 152513776 ps
CPU time 0.86 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:43:31 PM PDT 24
Peak memory 207000 kb
Host smart-dea165fb-72e3-411c-b247-1429f5cdd240
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1766363564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1766363564
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3511691760
Short name T1504
Test name
Test status
Simulation time 163227861 ps
CPU time 0.86 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:43:27 PM PDT 24
Peak memory 206988 kb
Host smart-99fb8e4f-4e83-4587-a610-95e4f0af84c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35116
91760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3511691760
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3578893478
Short name T447
Test name
Test status
Simulation time 165888568 ps
CPU time 0.88 seconds
Started Jul 31 05:43:28 PM PDT 24
Finished Jul 31 05:43:29 PM PDT 24
Peak memory 206996 kb
Host smart-1d4f5818-830b-4666-9778-54e35649e97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35788
93478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3578893478
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.3742132339
Short name T581
Test name
Test status
Simulation time 154809585 ps
CPU time 0.83 seconds
Started Jul 31 05:43:29 PM PDT 24
Finished Jul 31 05:43:30 PM PDT 24
Peak memory 206964 kb
Host smart-adc06238-cd53-44b0-9580-9170cf2fa111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37421
32339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.3742132339
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.1717112126
Short name T1463
Test name
Test status
Simulation time 212206348 ps
CPU time 0.92 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:43:27 PM PDT 24
Peak memory 207020 kb
Host smart-f7aece8f-ce20-44d1-aa27-d0011b17053c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17171
12126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.1717112126
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3419724915
Short name T1565
Test name
Test status
Simulation time 150482715 ps
CPU time 0.86 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 207000 kb
Host smart-c97d8606-5930-4b5b-9a7d-00f3bb74d16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34197
24915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3419724915
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1876453303
Short name T1092
Test name
Test status
Simulation time 232886615 ps
CPU time 1.09 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 206988 kb
Host smart-681f9cbc-4436-4733-b203-31ffa4dd5cee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1876453303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1876453303
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3604973118
Short name T1854
Test name
Test status
Simulation time 157381800 ps
CPU time 0.84 seconds
Started Jul 31 05:43:29 PM PDT 24
Finished Jul 31 05:43:30 PM PDT 24
Peak memory 206968 kb
Host smart-5df8cc76-b964-408a-954a-185bc9ac9c30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36049
73118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3604973118
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3424463502
Short name T1805
Test name
Test status
Simulation time 39065401 ps
CPU time 0.71 seconds
Started Jul 31 05:43:25 PM PDT 24
Finished Jul 31 05:43:26 PM PDT 24
Peak memory 207020 kb
Host smart-04c14312-03ab-4397-929d-0b9f13a6e1c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34244
63502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3424463502
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.423247259
Short name T1268
Test name
Test status
Simulation time 14919612856 ps
CPU time 38.49 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:44:05 PM PDT 24
Peak memory 215452 kb
Host smart-e5008f89-64fd-4337-b26b-d63b12acfe5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42324
7259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.423247259
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1655451131
Short name T1033
Test name
Test status
Simulation time 161515048 ps
CPU time 0.96 seconds
Started Jul 31 05:43:29 PM PDT 24
Finished Jul 31 05:43:30 PM PDT 24
Peak memory 206940 kb
Host smart-7b72cb3e-1f9a-4eda-b25a-1845fc5bfd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16554
51131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1655451131
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.1124877243
Short name T1560
Test name
Test status
Simulation time 233336457 ps
CPU time 1 seconds
Started Jul 31 05:43:26 PM PDT 24
Finished Jul 31 05:43:27 PM PDT 24
Peak memory 206992 kb
Host smart-0b19cae5-5d64-49a4-8a37-ab6182be5a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11248
77243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1124877243
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.401859173
Short name T684
Test name
Test status
Simulation time 189222181 ps
CPU time 0.94 seconds
Started Jul 31 05:43:27 PM PDT 24
Finished Jul 31 05:43:28 PM PDT 24
Peak memory 206996 kb
Host smart-01ec4c32-f29f-46ac-9753-26ff1fc60298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40185
9173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.401859173
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.4243604541
Short name T2181
Test name
Test status
Simulation time 207158546 ps
CPU time 0.91 seconds
Started Jul 31 05:43:28 PM PDT 24
Finished Jul 31 05:43:29 PM PDT 24
Peak memory 206984 kb
Host smart-e627c268-f368-435b-8599-947a9a47b2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42436
04541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.4243604541
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.4014209572
Short name T2063
Test name
Test status
Simulation time 155213861 ps
CPU time 0.83 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:43:32 PM PDT 24
Peak memory 206964 kb
Host smart-288ba90e-c5e8-4b01-bdb3-d8a9c25e1eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40142
09572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.4014209572
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.2865425102
Short name T1831
Test name
Test status
Simulation time 156247102 ps
CPU time 0.83 seconds
Started Jul 31 05:43:28 PM PDT 24
Finished Jul 31 05:43:30 PM PDT 24
Peak memory 206980 kb
Host smart-7a6bfd32-c40d-41c5-91f4-505ab7722293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28654
25102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.2865425102
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.615447802
Short name T426
Test name
Test status
Simulation time 209799898 ps
CPU time 0.98 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:43:33 PM PDT 24
Peak memory 206976 kb
Host smart-85f4fff2-ca05-455c-a3ca-bb27557641e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61544
7802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.615447802
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.4178444161
Short name T1291
Test name
Test status
Simulation time 6008602364 ps
CPU time 48.47 seconds
Started Jul 31 05:43:31 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 215408 kb
Host smart-9af28565-3bb7-46b8-87dc-141b98eb7540
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4178444161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.4178444161
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1388711901
Short name T825
Test name
Test status
Simulation time 163313433 ps
CPU time 0.94 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:43:31 PM PDT 24
Peak memory 206992 kb
Host smart-ac3b59c7-b5f2-470b-9bdf-b0102e9e3a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13887
11901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1388711901
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.4102843502
Short name T369
Test name
Test status
Simulation time 175864732 ps
CPU time 0.88 seconds
Started Jul 31 05:43:31 PM PDT 24
Finished Jul 31 05:43:32 PM PDT 24
Peak memory 207004 kb
Host smart-4faf924f-2b2f-4619-ae27-fffffeb7f99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41028
43502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.4102843502
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3650456138
Short name T1160
Test name
Test status
Simulation time 264524949 ps
CPU time 1.13 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:43:33 PM PDT 24
Peak memory 206964 kb
Host smart-9dde15c0-5c0b-47a8-935d-940e7e420631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36504
56138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3650456138
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.2008842577
Short name T833
Test name
Test status
Simulation time 6473807214 ps
CPU time 189.07 seconds
Started Jul 31 05:43:29 PM PDT 24
Finished Jul 31 05:46:38 PM PDT 24
Peak memory 215372 kb
Host smart-82e330f2-4f01-4981-8be0-0a23e93bd2dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20088
42577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.2008842577
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.2314661540
Short name T2317
Test name
Test status
Simulation time 278632128 ps
CPU time 4.2 seconds
Started Jul 31 05:43:25 PM PDT 24
Finished Jul 31 05:43:30 PM PDT 24
Peak memory 207048 kb
Host smart-a3c6e3db-844e-4729-9814-f145b40cea0d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314661540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos
t_handshake.2314661540
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.1928383176
Short name T1134
Test name
Test status
Simulation time 37312791 ps
CPU time 0.66 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:39 PM PDT 24
Peak memory 207020 kb
Host smart-bd75ef90-a970-47c1-ae7b-af8745b6c646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1928383176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1928383176
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.471392704
Short name T812
Test name
Test status
Simulation time 4278130090 ps
CPU time 5.73 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:43:37 PM PDT 24
Peak memory 207156 kb
Host smart-b4a721bc-d63a-4a5d-832c-b869f0c5df25
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471392704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_ao
n_wake_disconnect.471392704
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.912412280
Short name T2243
Test name
Test status
Simulation time 13392308419 ps
CPU time 15.35 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:43:48 PM PDT 24
Peak memory 207224 kb
Host smart-d4d2f286-ca03-40ad-b472-733623806e26
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=912412280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.912412280
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3520211949
Short name T2312
Test name
Test status
Simulation time 23426429835 ps
CPU time 30.12 seconds
Started Jul 31 05:43:29 PM PDT 24
Finished Jul 31 05:43:59 PM PDT 24
Peak memory 207120 kb
Host smart-669977ab-5070-4b90-ab51-28effd0bc4b1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520211949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_resume.3520211949
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3690646165
Short name T487
Test name
Test status
Simulation time 171404253 ps
CPU time 0.88 seconds
Started Jul 31 05:43:33 PM PDT 24
Finished Jul 31 05:43:34 PM PDT 24
Peak memory 207016 kb
Host smart-ec7fd621-3d8d-4eaa-90f8-74da784b799f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36906
46165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3690646165
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.1496933503
Short name T2758
Test name
Test status
Simulation time 141354846 ps
CPU time 0.88 seconds
Started Jul 31 05:43:29 PM PDT 24
Finished Jul 31 05:43:30 PM PDT 24
Peak memory 206956 kb
Host smart-2c1a3c78-4e6c-4c80-915d-19e311f98322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
33503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.1496933503
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1549404809
Short name T465
Test name
Test status
Simulation time 287722793 ps
CPU time 1.2 seconds
Started Jul 31 05:43:31 PM PDT 24
Finished Jul 31 05:43:32 PM PDT 24
Peak memory 206976 kb
Host smart-1184d9db-8601-45f2-8179-f25789a469c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15494
04809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1549404809
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1125125798
Short name T1730
Test name
Test status
Simulation time 868649500 ps
CPU time 2.21 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:43:34 PM PDT 24
Peak memory 207108 kb
Host smart-83c210f3-eaf3-44fa-8451-cf584287de4a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1125125798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1125125798
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2834892351
Short name T1727
Test name
Test status
Simulation time 5808342203 ps
CPU time 13.4 seconds
Started Jul 31 05:43:33 PM PDT 24
Finished Jul 31 05:43:46 PM PDT 24
Peak memory 207176 kb
Host smart-10d09f8b-c655-428f-af69-56ef715dbfd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28348
92351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2834892351
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_device_timeout.1011435469
Short name T2424
Test name
Test status
Simulation time 1547112310 ps
CPU time 36.49 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 207184 kb
Host smart-c4181dab-9194-4670-87d3-f2cda6ebfbf9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011435469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.1011435469
Directory /workspace/23.usbdev_device_timeout/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.1015636463
Short name T2749
Test name
Test status
Simulation time 338387373 ps
CPU time 1.26 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:43:32 PM PDT 24
Peak memory 206936 kb
Host smart-aa7062e8-0418-4e6f-ae76-8d168a61da20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10156
36463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.1015636463
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1574990296
Short name T970
Test name
Test status
Simulation time 133942716 ps
CPU time 0.87 seconds
Started Jul 31 05:43:33 PM PDT 24
Finished Jul 31 05:43:34 PM PDT 24
Peak memory 206968 kb
Host smart-8897f500-6751-483b-a21f-ef71ea36fdf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15749
90296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1574990296
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3867139693
Short name T799
Test name
Test status
Simulation time 53888248 ps
CPU time 0.74 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:43:32 PM PDT 24
Peak memory 206964 kb
Host smart-d6b93f8c-7e14-47c8-8e38-0c30b7ca0b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38671
39693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3867139693
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.3544748926
Short name T895
Test name
Test status
Simulation time 953631332 ps
CPU time 2.69 seconds
Started Jul 31 05:43:33 PM PDT 24
Finished Jul 31 05:43:36 PM PDT 24
Peak memory 207116 kb
Host smart-3e9a3bff-dbda-4977-a3f8-2cb1048a84f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35447
48926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.3544748926
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.470289253
Short name T1076
Test name
Test status
Simulation time 202434274 ps
CPU time 1.45 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:43:32 PM PDT 24
Peak memory 207048 kb
Host smart-ddf16560-e957-4692-9d42-af6d843714d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47028
9253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.470289253
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.727066667
Short name T2747
Test name
Test status
Simulation time 172063113 ps
CPU time 0.98 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:43:33 PM PDT 24
Peak memory 215296 kb
Host smart-ddbdfb90-c7f6-43ce-a917-a7408dfecb59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=727066667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.727066667
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1003433387
Short name T1360
Test name
Test status
Simulation time 156261640 ps
CPU time 0.82 seconds
Started Jul 31 05:43:33 PM PDT 24
Finished Jul 31 05:43:34 PM PDT 24
Peak memory 206992 kb
Host smart-d0ef4361-7de6-4cb1-9369-56acca72c620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10034
33387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1003433387
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.3723531860
Short name T93
Test name
Test status
Simulation time 162685197 ps
CPU time 0.91 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:43:32 PM PDT 24
Peak memory 206972 kb
Host smart-6f785084-1b4d-4cac-a0ca-bb705bfbf34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37235
31860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.3723531860
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.236697344
Short name T2353
Test name
Test status
Simulation time 7237648913 ps
CPU time 56.05 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:44:28 PM PDT 24
Peak memory 215472 kb
Host smart-bf9e797d-896a-4a7e-b95b-854013652a29
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=236697344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.236697344
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.935895642
Short name T2472
Test name
Test status
Simulation time 5611610521 ps
CPU time 37.18 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:44:09 PM PDT 24
Peak memory 207156 kb
Host smart-2d1c5ff9-e01e-4a40-a13d-6efbfd65c132
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=935895642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.935895642
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.1768435452
Short name T1760
Test name
Test status
Simulation time 217801510 ps
CPU time 0.95 seconds
Started Jul 31 05:43:33 PM PDT 24
Finished Jul 31 05:43:34 PM PDT 24
Peak memory 206988 kb
Host smart-6c3fcc7e-8d90-4fdf-bb44-3f5d0b649eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17684
35452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1768435452
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.3950102829
Short name T1842
Test name
Test status
Simulation time 23346711365 ps
CPU time 30.5 seconds
Started Jul 31 05:43:33 PM PDT 24
Finished Jul 31 05:44:04 PM PDT 24
Peak memory 207232 kb
Host smart-1b4acbd1-37b1-4b95-8aa7-1f6e10d35fe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39501
02829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3950102829
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.1414662735
Short name T1347
Test name
Test status
Simulation time 3328433616 ps
CPU time 6.07 seconds
Started Jul 31 05:43:34 PM PDT 24
Finished Jul 31 05:43:40 PM PDT 24
Peak memory 207092 kb
Host smart-eb3a1370-4b50-4159-9faf-f6863f5291ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14146
62735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1414662735
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3952658413
Short name T882
Test name
Test status
Simulation time 9780205021 ps
CPU time 98.29 seconds
Started Jul 31 05:43:31 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 217088 kb
Host smart-748eb475-292a-446a-831f-03fd2c65631d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39526
58413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3952658413
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.3385759047
Short name T2679
Test name
Test status
Simulation time 7750519269 ps
CPU time 80.64 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 207188 kb
Host smart-99d93246-abe3-4602-b384-48a9506b44b1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3385759047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.3385759047
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2680464540
Short name T1874
Test name
Test status
Simulation time 240544480 ps
CPU time 1.01 seconds
Started Jul 31 05:43:32 PM PDT 24
Finished Jul 31 05:43:33 PM PDT 24
Peak memory 207004 kb
Host smart-7bb03b3b-b9ea-40fa-b0ef-4706dcfdacc5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2680464540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2680464540
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.2986068418
Short name T478
Test name
Test status
Simulation time 194756577 ps
CPU time 0.96 seconds
Started Jul 31 05:43:30 PM PDT 24
Finished Jul 31 05:43:31 PM PDT 24
Peak memory 207004 kb
Host smart-74111d51-a9ed-4814-a834-13e411e34cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29860
68418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.2986068418
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2580020819
Short name T1437
Test name
Test status
Simulation time 5631554041 ps
CPU time 59.51 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:44:36 PM PDT 24
Peak memory 217004 kb
Host smart-4c129548-a341-4bae-a83c-b8de121acc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25800
20819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2580020819
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1420671549
Short name T2130
Test name
Test status
Simulation time 4678175141 ps
CPU time 37.71 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:44:15 PM PDT 24
Peak memory 217012 kb
Host smart-d58bc8cc-95db-4c10-8dbf-4e24c64496a2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1420671549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1420671549
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.715072119
Short name T2271
Test name
Test status
Simulation time 149855847 ps
CPU time 0.83 seconds
Started Jul 31 05:43:39 PM PDT 24
Finished Jul 31 05:43:40 PM PDT 24
Peak memory 207000 kb
Host smart-fa56adbe-29bb-41d0-89d1-dcd22753f6c0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=715072119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.715072119
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3123767707
Short name T1707
Test name
Test status
Simulation time 146929104 ps
CPU time 0.9 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:39 PM PDT 24
Peak memory 206988 kb
Host smart-35530190-f9b3-4320-93d7-03dc923018da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31237
67707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3123767707
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.300636679
Short name T1117
Test name
Test status
Simulation time 160844200 ps
CPU time 0.92 seconds
Started Jul 31 05:43:40 PM PDT 24
Finished Jul 31 05:43:41 PM PDT 24
Peak memory 207040 kb
Host smart-0d6abf93-8330-4137-87a7-6e4bc6250758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30063
6679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.300636679
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1661814857
Short name T2631
Test name
Test status
Simulation time 164697400 ps
CPU time 0.88 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:39 PM PDT 24
Peak memory 207004 kb
Host smart-b6ea4417-ba0a-465f-8033-4261453e33dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16618
14857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1661814857
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1065028891
Short name T909
Test name
Test status
Simulation time 148165813 ps
CPU time 0.84 seconds
Started Jul 31 05:43:36 PM PDT 24
Finished Jul 31 05:43:37 PM PDT 24
Peak memory 207000 kb
Host smart-e8286e43-2966-4d8d-a8d2-5b17b3a850ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10650
28891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1065028891
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.4206726923
Short name T2305
Test name
Test status
Simulation time 233388637 ps
CPU time 1 seconds
Started Jul 31 05:43:40 PM PDT 24
Finished Jul 31 05:43:41 PM PDT 24
Peak memory 206976 kb
Host smart-835bc58b-925d-4d86-86b3-62fd63286032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42067
26923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.4206726923
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.2444309849
Short name T2536
Test name
Test status
Simulation time 222776318 ps
CPU time 1.04 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:40 PM PDT 24
Peak memory 207016 kb
Host smart-63c250e5-685c-4f04-8175-b7cdf93ab1a1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2444309849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.2444309849
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.218950707
Short name T1982
Test name
Test status
Simulation time 146426410 ps
CPU time 0.85 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:39 PM PDT 24
Peak memory 206968 kb
Host smart-eb3996b1-7294-4e94-b608-5d30143bb68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21895
0707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.218950707
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3734371054
Short name T690
Test name
Test status
Simulation time 77584736 ps
CPU time 0.75 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:43:38 PM PDT 24
Peak memory 206968 kb
Host smart-30f04a17-e47c-4c92-8449-91ee4ef4b0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37343
71054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3734371054
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.1829908101
Short name T2439
Test name
Test status
Simulation time 13847566504 ps
CPU time 36.31 seconds
Started Jul 31 05:43:59 PM PDT 24
Finished Jul 31 05:44:36 PM PDT 24
Peak memory 215420 kb
Host smart-f9b64aa4-f7aa-49f4-aa82-5a061a1b0ab0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18299
08101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.1829908101
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2596189393
Short name T1070
Test name
Test status
Simulation time 154531736 ps
CPU time 0.86 seconds
Started Jul 31 05:43:41 PM PDT 24
Finished Jul 31 05:43:42 PM PDT 24
Peak memory 206996 kb
Host smart-8d8b30c7-fe93-46f7-91cb-6d45e39f93ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25961
89393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2596189393
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.4225670240
Short name T892
Test name
Test status
Simulation time 211135558 ps
CPU time 1.04 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:39 PM PDT 24
Peak memory 206960 kb
Host smart-395f5c97-7d21-4562-ad48-0620c2a9bc18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42256
70240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.4225670240
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.3174834309
Short name T1695
Test name
Test status
Simulation time 204649211 ps
CPU time 0.94 seconds
Started Jul 31 05:43:35 PM PDT 24
Finished Jul 31 05:43:36 PM PDT 24
Peak memory 206920 kb
Host smart-e600e9d9-a147-47ff-8412-9cd2a8f0f1cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31748
34309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.3174834309
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.869378369
Short name T2300
Test name
Test status
Simulation time 149361236 ps
CPU time 0.88 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:43:38 PM PDT 24
Peak memory 206968 kb
Host smart-86bf12d6-8192-43a2-9888-5cf6e0e30f69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86937
8369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.869378369
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.2771322464
Short name T1091
Test name
Test status
Simulation time 152974766 ps
CPU time 0.89 seconds
Started Jul 31 05:43:42 PM PDT 24
Finished Jul 31 05:43:43 PM PDT 24
Peak memory 207000 kb
Host smart-556e7563-f1f3-451d-8ef5-1434f803cb51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27713
22464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.2771322464
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1451211981
Short name T2801
Test name
Test status
Simulation time 152347689 ps
CPU time 0.88 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:43:38 PM PDT 24
Peak memory 206968 kb
Host smart-3875956c-805b-4f6d-9fd7-dbf6aeb1913e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14512
11981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1451211981
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2826792595
Short name T615
Test name
Test status
Simulation time 156137326 ps
CPU time 0.83 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:39 PM PDT 24
Peak memory 206976 kb
Host smart-9d203e0c-aa8b-4840-8f68-9f460cbf7106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28267
92595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2826792595
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3919058463
Short name T1135
Test name
Test status
Simulation time 308226311 ps
CPU time 1.07 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:43:38 PM PDT 24
Peak memory 206968 kb
Host smart-4b9c2dad-1762-46de-b57e-f7d573bb3ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39190
58463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3919058463
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2768522161
Short name T1240
Test name
Test status
Simulation time 4833482671 ps
CPU time 49.51 seconds
Started Jul 31 05:43:41 PM PDT 24
Finished Jul 31 05:44:31 PM PDT 24
Peak memory 216856 kb
Host smart-14d9608e-6a8b-4b3e-a4ec-9011c9c1a050
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2768522161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2768522161
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.1177967144
Short name T1494
Test name
Test status
Simulation time 160684455 ps
CPU time 0.87 seconds
Started Jul 31 05:43:42 PM PDT 24
Finished Jul 31 05:43:42 PM PDT 24
Peak memory 207012 kb
Host smart-835aef6d-d7ae-46c3-acd2-44d9fdf380ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11779
67144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.1177967144
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.2437306812
Short name T2201
Test name
Test status
Simulation time 185654138 ps
CPU time 0.9 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:39 PM PDT 24
Peak memory 207032 kb
Host smart-d36f77a5-7f5d-4bc5-a3cb-c2eefee3cb5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373
06812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2437306812
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2894288114
Short name T2842
Test name
Test status
Simulation time 685277206 ps
CPU time 1.88 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:43:39 PM PDT 24
Peak memory 206968 kb
Host smart-5a387a10-07f9-47f2-b4e2-9faf4c27c9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942
88114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2894288114
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.3283929370
Short name T2769
Test name
Test status
Simulation time 4727455755 ps
CPU time 136.83 seconds
Started Jul 31 05:43:40 PM PDT 24
Finished Jul 31 05:45:57 PM PDT 24
Peak memory 215432 kb
Host smart-934ff7de-5e2f-41cc-b6f7-4d8a1e3e0a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32839
29370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.3283929370
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.1543552961
Short name T52
Test name
Test status
Simulation time 4299045829 ps
CPU time 39.77 seconds
Started Jul 31 05:43:29 PM PDT 24
Finished Jul 31 05:44:09 PM PDT 24
Peak memory 207224 kb
Host smart-587c0d09-1f6b-4f9f-a341-bcd12c646162
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543552961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos
t_handshake.1543552961
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.3638626386
Short name T1253
Test name
Test status
Simulation time 52509531 ps
CPU time 0.67 seconds
Started Jul 31 05:43:48 PM PDT 24
Finished Jul 31 05:43:48 PM PDT 24
Peak memory 207076 kb
Host smart-c6a89faf-38c3-43a0-877a-2aad21b57866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3638626386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.3638626386
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.365798508
Short name T915
Test name
Test status
Simulation time 4256738718 ps
CPU time 5.72 seconds
Started Jul 31 05:43:39 PM PDT 24
Finished Jul 31 05:43:44 PM PDT 24
Peak memory 207140 kb
Host smart-95c881dc-4e1e-4fbb-93ac-fa2bd11d129b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365798508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_ao
n_wake_disconnect.365798508
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2408090742
Short name T797
Test name
Test status
Simulation time 13337581353 ps
CPU time 15.28 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:43:53 PM PDT 24
Peak memory 207224 kb
Host smart-073120fb-e934-4fbc-92e9-246fc96fbfca
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408090742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2408090742
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2037170675
Short name T1441
Test name
Test status
Simulation time 23548422154 ps
CPU time 28.91 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:44:08 PM PDT 24
Peak memory 207212 kb
Host smart-200a8472-26a8-40ed-8e5d-da3b76e641f8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037170675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.2037170675
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3738420370
Short name T1999
Test name
Test status
Simulation time 175872081 ps
CPU time 0.97 seconds
Started Jul 31 05:43:36 PM PDT 24
Finished Jul 31 05:43:37 PM PDT 24
Peak memory 206992 kb
Host smart-d96fbf65-afd5-459a-80ae-cceabe9a732c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37384
20370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3738420370
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3538039631
Short name T1848
Test name
Test status
Simulation time 154475223 ps
CPU time 0.86 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:43:38 PM PDT 24
Peak memory 206952 kb
Host smart-ae20e4eb-72b8-4408-af1a-fd1ecd3616b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35380
39631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3538039631
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1686019284
Short name T1908
Test name
Test status
Simulation time 162424398 ps
CPU time 0.86 seconds
Started Jul 31 05:43:39 PM PDT 24
Finished Jul 31 05:43:40 PM PDT 24
Peak memory 206952 kb
Host smart-e8f9463b-a329-4d0a-82b4-df7029fe0d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16860
19284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1686019284
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.1121612602
Short name T2196
Test name
Test status
Simulation time 1164711547 ps
CPU time 2.9 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:41 PM PDT 24
Peak memory 207064 kb
Host smart-31828cf6-15cc-40e4-b629-69e4ace861af
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1121612602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1121612602
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.2158730838
Short name T283
Test name
Test status
Simulation time 11856103025 ps
CPU time 26.15 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:44:03 PM PDT 24
Peak memory 207200 kb
Host smart-206712f6-e373-409b-81d3-72572893f0e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21587
30838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.2158730838
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_device_timeout.1355316589
Short name T1352
Test name
Test status
Simulation time 1902619084 ps
CPU time 12.7 seconds
Started Jul 31 05:43:38 PM PDT 24
Finished Jul 31 05:43:51 PM PDT 24
Peak memory 207092 kb
Host smart-170dfa3c-bccf-46ed-8ce6-ddca22811c18
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355316589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.1355316589
Directory /workspace/24.usbdev_device_timeout/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.534328343
Short name T1911
Test name
Test status
Simulation time 485295259 ps
CPU time 1.49 seconds
Started Jul 31 05:43:43 PM PDT 24
Finished Jul 31 05:43:44 PM PDT 24
Peak memory 206956 kb
Host smart-a1c7a500-cc2d-464a-88c0-2b24e2ccac58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53432
8343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.534328343
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.539238216
Short name T551
Test name
Test status
Simulation time 138636015 ps
CPU time 0.78 seconds
Started Jul 31 05:43:41 PM PDT 24
Finished Jul 31 05:43:42 PM PDT 24
Peak memory 206960 kb
Host smart-99851d0f-c1ac-4a57-b4a3-5d5435f6c4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53923
8216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.539238216
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1224955999
Short name T686
Test name
Test status
Simulation time 47359822 ps
CPU time 0.72 seconds
Started Jul 31 05:43:51 PM PDT 24
Finished Jul 31 05:43:52 PM PDT 24
Peak memory 206956 kb
Host smart-81f77d9e-1705-41bd-80da-0fd971f5a7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12249
55999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1224955999
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.1000666455
Short name T2128
Test name
Test status
Simulation time 882454307 ps
CPU time 2.73 seconds
Started Jul 31 05:43:42 PM PDT 24
Finished Jul 31 05:43:45 PM PDT 24
Peak memory 207124 kb
Host smart-0332dc00-7157-4073-a8d0-0645d65280e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10006
66455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.1000666455
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.3284906547
Short name T758
Test name
Test status
Simulation time 239514981 ps
CPU time 2.06 seconds
Started Jul 31 05:43:41 PM PDT 24
Finished Jul 31 05:43:43 PM PDT 24
Peak memory 207024 kb
Host smart-3de300bc-bc13-48c2-84eb-3ae513fba4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32849
06547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.3284906547
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2327814973
Short name T2117
Test name
Test status
Simulation time 203477476 ps
CPU time 0.89 seconds
Started Jul 31 05:43:43 PM PDT 24
Finished Jul 31 05:43:44 PM PDT 24
Peak memory 206980 kb
Host smart-c45ab467-4d0a-485a-8c98-ca3b466c8de4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2327814973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2327814973
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2745030074
Short name T88
Test name
Test status
Simulation time 161054708 ps
CPU time 0.87 seconds
Started Jul 31 05:43:40 PM PDT 24
Finished Jul 31 05:43:41 PM PDT 24
Peak memory 206956 kb
Host smart-24b3e29d-fc37-44c2-a90c-5c13ff553269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27450
30074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2745030074
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1293046780
Short name T2651
Test name
Test status
Simulation time 187145192 ps
CPU time 0.96 seconds
Started Jul 31 05:43:45 PM PDT 24
Finished Jul 31 05:43:46 PM PDT 24
Peak memory 206992 kb
Host smart-a7c9c72d-31b4-447e-ba17-23a86571a4fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12930
46780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1293046780
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.3602471439
Short name T80
Test name
Test status
Simulation time 5968890888 ps
CPU time 59.5 seconds
Started Jul 31 05:43:46 PM PDT 24
Finished Jul 31 05:44:45 PM PDT 24
Peak memory 215452 kb
Host smart-c21ee74b-6097-4070-a388-3dad16f5dbec
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3602471439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3602471439
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.2614422437
Short name T1980
Test name
Test status
Simulation time 10778613141 ps
CPU time 126.1 seconds
Started Jul 31 05:43:42 PM PDT 24
Finished Jul 31 05:45:48 PM PDT 24
Peak memory 207196 kb
Host smart-0fd7595e-c65c-46d8-97ed-5f619ae4c8e4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2614422437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.2614422437
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.893668276
Short name T988
Test name
Test status
Simulation time 194541332 ps
CPU time 0.88 seconds
Started Jul 31 05:43:44 PM PDT 24
Finished Jul 31 05:43:45 PM PDT 24
Peak memory 206996 kb
Host smart-baf5dfbc-64f2-4e46-9f87-270d98e10c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89366
8276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.893668276
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.3474582499
Short name T1186
Test name
Test status
Simulation time 23284065242 ps
CPU time 27.36 seconds
Started Jul 31 05:43:39 PM PDT 24
Finished Jul 31 05:44:06 PM PDT 24
Peak memory 207156 kb
Host smart-fe9502ed-25b6-42bf-90ad-06f2d4268069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34745
82499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.3474582499
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.4171411849
Short name T744
Test name
Test status
Simulation time 3292422739 ps
CPU time 4.76 seconds
Started Jul 31 05:43:41 PM PDT 24
Finished Jul 31 05:43:46 PM PDT 24
Peak memory 207120 kb
Host smart-4a895ba0-f02f-4bae-ba3d-87dd699da0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41714
11849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.4171411849
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.3837945172
Short name T2136
Test name
Test status
Simulation time 8178577927 ps
CPU time 60.81 seconds
Started Jul 31 05:43:43 PM PDT 24
Finished Jul 31 05:44:44 PM PDT 24
Peak memory 217420 kb
Host smart-8422da83-a9fb-47d3-af0b-0ccdb790a994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38379
45172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.3837945172
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.209614900
Short name T2125
Test name
Test status
Simulation time 4861874093 ps
CPU time 147.57 seconds
Started Jul 31 05:43:44 PM PDT 24
Finished Jul 31 05:46:12 PM PDT 24
Peak memory 215392 kb
Host smart-0e34f96b-9223-4bbe-9bce-154da0c35f89
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=209614900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.209614900
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3289850364
Short name T525
Test name
Test status
Simulation time 265314002 ps
CPU time 1.01 seconds
Started Jul 31 05:43:45 PM PDT 24
Finished Jul 31 05:43:46 PM PDT 24
Peak memory 207020 kb
Host smart-c381ebe9-465d-4baa-8f03-81ade41cb7ea
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3289850364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3289850364
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2243062102
Short name T442
Test name
Test status
Simulation time 222867243 ps
CPU time 0.97 seconds
Started Jul 31 05:43:45 PM PDT 24
Finished Jul 31 05:43:46 PM PDT 24
Peak memory 207008 kb
Host smart-4dc183e2-5109-4195-b3c7-7549299248a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22430
62102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2243062102
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.2364871964
Short name T2209
Test name
Test status
Simulation time 5260160620 ps
CPU time 154.78 seconds
Started Jul 31 05:43:41 PM PDT 24
Finished Jul 31 05:46:16 PM PDT 24
Peak memory 215428 kb
Host smart-06546a65-59e7-4a8a-931f-e800a6bb908b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23648
71964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.2364871964
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3291349120
Short name T1956
Test name
Test status
Simulation time 5717099063 ps
CPU time 59.53 seconds
Started Jul 31 05:43:45 PM PDT 24
Finished Jul 31 05:44:45 PM PDT 24
Peak memory 207260 kb
Host smart-1b54f2c3-aaf8-49b3-9adb-f8b26d20e34b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3291349120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3291349120
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.266323375
Short name T2644
Test name
Test status
Simulation time 157648116 ps
CPU time 0.86 seconds
Started Jul 31 05:43:42 PM PDT 24
Finished Jul 31 05:43:43 PM PDT 24
Peak memory 207000 kb
Host smart-09f9f7d1-de0f-4aef-b620-e01b9e649fa9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=266323375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.266323375
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.3441075831
Short name T1368
Test name
Test status
Simulation time 181773381 ps
CPU time 0.86 seconds
Started Jul 31 05:43:44 PM PDT 24
Finished Jul 31 05:43:45 PM PDT 24
Peak memory 207012 kb
Host smart-9045d159-f853-46b7-858f-b7d2d10dc18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34410
75831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.3441075831
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.3813619737
Short name T2077
Test name
Test status
Simulation time 154980481 ps
CPU time 0.9 seconds
Started Jul 31 05:43:45 PM PDT 24
Finished Jul 31 05:43:46 PM PDT 24
Peak memory 207004 kb
Host smart-717aa092-3a55-4952-9448-5ad49373bf2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38136
19737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3813619737
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.214137459
Short name T1644
Test name
Test status
Simulation time 177527691 ps
CPU time 0.95 seconds
Started Jul 31 05:43:40 PM PDT 24
Finished Jul 31 05:43:41 PM PDT 24
Peak memory 207000 kb
Host smart-0a4012c1-cfd0-4d8a-88fb-2a1cc0dfb36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21413
7459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.214137459
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.4092083816
Short name T1166
Test name
Test status
Simulation time 187147198 ps
CPU time 0.87 seconds
Started Jul 31 05:43:44 PM PDT 24
Finished Jul 31 05:43:45 PM PDT 24
Peak memory 206988 kb
Host smart-4c2b48b9-c684-4b09-8e42-2f74d93f53c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40920
83816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.4092083816
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3475456087
Short name T171
Test name
Test status
Simulation time 217220067 ps
CPU time 0.96 seconds
Started Jul 31 05:43:43 PM PDT 24
Finished Jul 31 05:43:44 PM PDT 24
Peak memory 206980 kb
Host smart-d0153dfb-58f1-4b81-9db0-7847c801df96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34754
56087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3475456087
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1880128886
Short name T844
Test name
Test status
Simulation time 238476242 ps
CPU time 1.02 seconds
Started Jul 31 05:43:42 PM PDT 24
Finished Jul 31 05:43:43 PM PDT 24
Peak memory 206968 kb
Host smart-f1fca4ac-1ac7-4829-9a9a-855eda480550
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1880128886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1880128886
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3848876565
Short name T1208
Test name
Test status
Simulation time 220755629 ps
CPU time 0.91 seconds
Started Jul 31 05:43:42 PM PDT 24
Finished Jul 31 05:43:43 PM PDT 24
Peak memory 206952 kb
Host smart-2114488b-cad7-47bd-9413-da874bc6372e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38488
76565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3848876565
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.3257339818
Short name T806
Test name
Test status
Simulation time 30756556 ps
CPU time 0.67 seconds
Started Jul 31 05:43:43 PM PDT 24
Finished Jul 31 05:43:44 PM PDT 24
Peak memory 206960 kb
Host smart-ad63d736-4009-4277-bfc7-5f6c48362bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32573
39818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3257339818
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.209842025
Short name T249
Test name
Test status
Simulation time 14578929670 ps
CPU time 37.83 seconds
Started Jul 31 05:43:42 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 220312 kb
Host smart-a79c3ad7-70f0-4c93-8b0f-1d2ad41a7930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20984
2025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.209842025
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1460342870
Short name T26
Test name
Test status
Simulation time 213135754 ps
CPU time 0.97 seconds
Started Jul 31 05:43:41 PM PDT 24
Finished Jul 31 05:43:42 PM PDT 24
Peak memory 206992 kb
Host smart-235b8cde-69e4-42bd-b0e1-abf0a6cccfb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14603
42870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1460342870
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.3386244676
Short name T1121
Test name
Test status
Simulation time 243297209 ps
CPU time 1.01 seconds
Started Jul 31 05:43:41 PM PDT 24
Finished Jul 31 05:43:42 PM PDT 24
Peak memory 206964 kb
Host smart-6bf3b4d7-0ae2-495f-8b68-f5e9628bf5a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33862
44676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3386244676
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.4121220577
Short name T2094
Test name
Test status
Simulation time 249687340 ps
CPU time 1.05 seconds
Started Jul 31 05:43:41 PM PDT 24
Finished Jul 31 05:43:42 PM PDT 24
Peak memory 206968 kb
Host smart-14c2230d-f7af-4f85-a3d8-0c139619da28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41212
20577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.4121220577
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.285285219
Short name T1530
Test name
Test status
Simulation time 163146983 ps
CPU time 0.88 seconds
Started Jul 31 05:43:47 PM PDT 24
Finished Jul 31 05:43:48 PM PDT 24
Peak memory 206980 kb
Host smart-871c2c7d-4f12-44b0-87e4-21e8887453f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28528
5219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.285285219
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1899134658
Short name T1250
Test name
Test status
Simulation time 167962667 ps
CPU time 0.88 seconds
Started Jul 31 05:43:52 PM PDT 24
Finished Jul 31 05:43:53 PM PDT 24
Peak memory 206968 kb
Host smart-2a7723d9-462e-45b6-925d-c832783b9437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18991
34658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1899134658
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1623113852
Short name T2556
Test name
Test status
Simulation time 164629868 ps
CPU time 0.89 seconds
Started Jul 31 05:43:48 PM PDT 24
Finished Jul 31 05:43:49 PM PDT 24
Peak memory 206936 kb
Host smart-d76ac522-ffb0-489e-9cd8-fef37ca3690c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16231
13852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1623113852
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3456460495
Short name T2008
Test name
Test status
Simulation time 151470459 ps
CPU time 0.84 seconds
Started Jul 31 05:43:59 PM PDT 24
Finished Jul 31 05:44:00 PM PDT 24
Peak memory 206972 kb
Host smart-4c1fa499-b5f2-46ac-a904-a4b738afb75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34564
60495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3456460495
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1257670223
Short name T978
Test name
Test status
Simulation time 213907597 ps
CPU time 1 seconds
Started Jul 31 05:43:48 PM PDT 24
Finished Jul 31 05:43:49 PM PDT 24
Peak memory 206980 kb
Host smart-67a53967-6296-4864-908c-2b6baef3963b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12576
70223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1257670223
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1760540269
Short name T1795
Test name
Test status
Simulation time 4358610314 ps
CPU time 35.07 seconds
Started Jul 31 05:43:48 PM PDT 24
Finished Jul 31 05:44:23 PM PDT 24
Peak memory 216996 kb
Host smart-563edd9f-0d5d-4118-8c8d-97ee068f9555
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1760540269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1760540269
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.3522227688
Short name T2553
Test name
Test status
Simulation time 248060559 ps
CPU time 0.92 seconds
Started Jul 31 05:43:48 PM PDT 24
Finished Jul 31 05:43:49 PM PDT 24
Peak memory 206980 kb
Host smart-83e55335-fe1a-401b-9213-09dbe5ba21e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35222
27688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.3522227688
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.493999122
Short name T2796
Test name
Test status
Simulation time 145063760 ps
CPU time 0.83 seconds
Started Jul 31 05:43:49 PM PDT 24
Finished Jul 31 05:43:50 PM PDT 24
Peak memory 206952 kb
Host smart-cef41d25-7bca-477d-a808-5f3a616c0499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49399
9122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.493999122
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1269481486
Short name T2055
Test name
Test status
Simulation time 208571118 ps
CPU time 1.01 seconds
Started Jul 31 05:43:46 PM PDT 24
Finished Jul 31 05:43:47 PM PDT 24
Peak memory 206952 kb
Host smart-b4aacea8-d6bf-4383-9bff-517ba15077a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12694
81486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1269481486
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.765662149
Short name T2342
Test name
Test status
Simulation time 5501162705 ps
CPU time 59.06 seconds
Started Jul 31 05:43:50 PM PDT 24
Finished Jul 31 05:44:49 PM PDT 24
Peak memory 207192 kb
Host smart-6a250172-f9d1-4212-ab55-eb2ef93aebe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76566
2149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.765662149
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.2283922636
Short name T2247
Test name
Test status
Simulation time 1172125378 ps
CPU time 27.63 seconds
Started Jul 31 05:43:37 PM PDT 24
Finished Jul 31 05:44:05 PM PDT 24
Peak memory 207044 kb
Host smart-a6df9765-eb93-4fe7-8d39-4de0a4d8a684
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283922636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos
t_handshake.2283922636
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.3233152870
Short name T407
Test name
Test status
Simulation time 33967424 ps
CPU time 0.7 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:43:57 PM PDT 24
Peak memory 207052 kb
Host smart-e7fb40d5-7159-4101-8c78-20ad02ce3070
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3233152870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.3233152870
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.3498413384
Short name T180
Test name
Test status
Simulation time 3764332860 ps
CPU time 5.99 seconds
Started Jul 31 05:43:49 PM PDT 24
Finished Jul 31 05:43:55 PM PDT 24
Peak memory 207132 kb
Host smart-345359ed-9a93-4db2-b8fa-a6d430421bce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498413384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.3498413384
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3439843360
Short name T755
Test name
Test status
Simulation time 13352761457 ps
CPU time 15.96 seconds
Started Jul 31 05:43:48 PM PDT 24
Finished Jul 31 05:44:04 PM PDT 24
Peak memory 207228 kb
Host smart-da82078d-8867-437c-a764-c652fa1f9521
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439843360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3439843360
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2436220897
Short name T1363
Test name
Test status
Simulation time 23392184664 ps
CPU time 27.19 seconds
Started Jul 31 05:43:48 PM PDT 24
Finished Jul 31 05:44:15 PM PDT 24
Peak memory 207216 kb
Host smart-8db3ce15-904c-4ef6-bf04-2fde9c34486a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436220897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.2436220897
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.1278885890
Short name T2642
Test name
Test status
Simulation time 144928300 ps
CPU time 0.84 seconds
Started Jul 31 05:43:52 PM PDT 24
Finished Jul 31 05:43:53 PM PDT 24
Peak memory 207000 kb
Host smart-83308eb8-fe5d-4ff9-86f9-b8ebd25f0b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12788
85890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.1278885890
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2443094573
Short name T1776
Test name
Test status
Simulation time 153181179 ps
CPU time 0.96 seconds
Started Jul 31 05:43:50 PM PDT 24
Finished Jul 31 05:43:51 PM PDT 24
Peak memory 206944 kb
Host smart-a97734f1-9292-4d50-9a49-8dbfa4ef0dc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24430
94573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2443094573
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.4097417777
Short name T592
Test name
Test status
Simulation time 460730907 ps
CPU time 1.51 seconds
Started Jul 31 05:43:57 PM PDT 24
Finished Jul 31 05:43:58 PM PDT 24
Peak memory 206976 kb
Host smart-ffaa6e3a-2102-4170-8619-5cd413f5c0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40974
17777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.4097417777
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.892381912
Short name T2591
Test name
Test status
Simulation time 1330734567 ps
CPU time 3.47 seconds
Started Jul 31 05:43:50 PM PDT 24
Finished Jul 31 05:43:53 PM PDT 24
Peak memory 207168 kb
Host smart-6def736b-98b2-4e7a-9d96-dfb67dc71126
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=892381912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.892381912
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.2502536326
Short name T160
Test name
Test status
Simulation time 7816387419 ps
CPU time 18.2 seconds
Started Jul 31 05:43:48 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 207192 kb
Host smart-d4197e63-69d9-4b22-893b-3021a73d35dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25025
36326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.2502536326
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_device_timeout.2084928396
Short name T2577
Test name
Test status
Simulation time 574237679 ps
CPU time 11.4 seconds
Started Jul 31 05:43:49 PM PDT 24
Finished Jul 31 05:44:01 PM PDT 24
Peak memory 207000 kb
Host smart-b069964f-801c-4690-b6f4-5ba35663007f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084928396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.2084928396
Directory /workspace/25.usbdev_device_timeout/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3418350993
Short name T2231
Test name
Test status
Simulation time 450225362 ps
CPU time 1.47 seconds
Started Jul 31 05:43:50 PM PDT 24
Finished Jul 31 05:43:52 PM PDT 24
Peak memory 206952 kb
Host smart-ce24eaac-1c0d-40b9-b971-e8c2078dd9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34183
50993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3418350993
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.423805119
Short name T1725
Test name
Test status
Simulation time 204887760 ps
CPU time 0.9 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:43:57 PM PDT 24
Peak memory 206944 kb
Host smart-9f2eadca-669e-4544-ab9a-8a8f088a1c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380
5119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.423805119
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.121917151
Short name T2828
Test name
Test status
Simulation time 61552572 ps
CPU time 0.75 seconds
Started Jul 31 05:43:57 PM PDT 24
Finished Jul 31 05:43:58 PM PDT 24
Peak memory 206940 kb
Host smart-eea8067a-791d-422d-975c-41d54d485d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12191
7151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.121917151
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.3225284746
Short name T2298
Test name
Test status
Simulation time 848905537 ps
CPU time 2.26 seconds
Started Jul 31 05:43:52 PM PDT 24
Finished Jul 31 05:43:54 PM PDT 24
Peak memory 207124 kb
Host smart-d8be5f7d-ce56-4de3-a881-9f4055183b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32252
84746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.3225284746
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2786191626
Short name T1685
Test name
Test status
Simulation time 150487239 ps
CPU time 1.35 seconds
Started Jul 31 05:43:51 PM PDT 24
Finished Jul 31 05:43:52 PM PDT 24
Peak memory 207088 kb
Host smart-004df2b1-0ad7-4afd-880f-a98930959d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27861
91626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2786191626
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.524614107
Short name T468
Test name
Test status
Simulation time 171042571 ps
CPU time 0.94 seconds
Started Jul 31 05:43:49 PM PDT 24
Finished Jul 31 05:43:50 PM PDT 24
Peak memory 207060 kb
Host smart-0b29f258-4e3c-4098-bee4-5359a4e13d7a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=524614107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.524614107
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1810046283
Short name T1907
Test name
Test status
Simulation time 141324292 ps
CPU time 0.82 seconds
Started Jul 31 05:43:52 PM PDT 24
Finished Jul 31 05:43:53 PM PDT 24
Peak memory 206964 kb
Host smart-c15b1340-573e-4e2a-96c0-54a0e63d8b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18100
46283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1810046283
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.3986099301
Short name T1556
Test name
Test status
Simulation time 154682900 ps
CPU time 0.87 seconds
Started Jul 31 05:43:48 PM PDT 24
Finished Jul 31 05:43:49 PM PDT 24
Peak memory 206976 kb
Host smart-9f05e8c8-b541-4038-b45e-357fbf134921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39860
99301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3986099301
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.3307352831
Short name T2327
Test name
Test status
Simulation time 7669946822 ps
CPU time 235.33 seconds
Started Jul 31 05:43:47 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 215432 kb
Host smart-c390f3dc-1a39-41f1-abf8-3d29548db8c1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3307352831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.3307352831
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.4217684931
Short name T2098
Test name
Test status
Simulation time 5288740414 ps
CPU time 60.73 seconds
Started Jul 31 05:43:50 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 207172 kb
Host smart-ff286995-7be8-4419-9520-f3727f48554d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4217684931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.4217684931
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1066592629
Short name T1388
Test name
Test status
Simulation time 243892514 ps
CPU time 0.94 seconds
Started Jul 31 05:43:59 PM PDT 24
Finished Jul 31 05:44:00 PM PDT 24
Peak memory 206972 kb
Host smart-435a1f4a-52ea-4299-9fc1-81fd4d51f437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10665
92629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1066592629
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.2452915718
Short name T1899
Test name
Test status
Simulation time 23325023204 ps
CPU time 32 seconds
Started Jul 31 05:43:50 PM PDT 24
Finished Jul 31 05:44:22 PM PDT 24
Peak memory 207212 kb
Host smart-34257c52-9ded-4567-82aa-e05d6dfa2ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24529
15718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.2452915718
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.3702642824
Short name T1939
Test name
Test status
Simulation time 3347888709 ps
CPU time 5.94 seconds
Started Jul 31 05:43:57 PM PDT 24
Finished Jul 31 05:44:03 PM PDT 24
Peak memory 207124 kb
Host smart-48209d35-9c59-4555-abc8-4b3ec67e1c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37026
42824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.3702642824
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3952649649
Short name T1661
Test name
Test status
Simulation time 7577501730 ps
CPU time 58.5 seconds
Started Jul 31 05:43:50 PM PDT 24
Finished Jul 31 05:44:49 PM PDT 24
Peak memory 223568 kb
Host smart-fc89b3be-b8ed-4dc0-bc09-140606cb58fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39526
49649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3952649649
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.1320087328
Short name T2174
Test name
Test status
Simulation time 5589249939 ps
CPU time 63.18 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:45:00 PM PDT 24
Peak memory 207256 kb
Host smart-ffcf71cc-26ce-4625-9a83-48b6f941818d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1320087328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.1320087328
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2688648444
Short name T1052
Test name
Test status
Simulation time 262477936 ps
CPU time 1.1 seconds
Started Jul 31 05:43:58 PM PDT 24
Finished Jul 31 05:43:59 PM PDT 24
Peak memory 207012 kb
Host smart-a7fe5b9f-dd85-4ed4-97ca-a0b0b88e2a5a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2688648444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2688648444
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.3110093823
Short name T2791
Test name
Test status
Simulation time 211988977 ps
CPU time 0.94 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:43:57 PM PDT 24
Peak memory 207012 kb
Host smart-78e8fdbd-c602-41e7-8adf-b8fbf4426cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31100
93823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3110093823
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2484524948
Short name T924
Test name
Test status
Simulation time 5178271410 ps
CPU time 39.16 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 215460 kb
Host smart-b2072067-655c-464e-a27d-d5da890fb872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24845
24948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2484524948
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.695800344
Short name T2693
Test name
Test status
Simulation time 4219786807 ps
CPU time 44.22 seconds
Started Jul 31 05:43:55 PM PDT 24
Finished Jul 31 05:44:39 PM PDT 24
Peak memory 207196 kb
Host smart-b25e99ea-f245-4066-8707-fc4102e051d5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=695800344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.695800344
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.201573085
Short name T1905
Test name
Test status
Simulation time 172533269 ps
CPU time 0.89 seconds
Started Jul 31 05:43:54 PM PDT 24
Finished Jul 31 05:43:55 PM PDT 24
Peak memory 206964 kb
Host smart-d803712c-6cd6-4d3f-abba-5f8a8fdb1776
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=201573085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.201573085
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.590746549
Short name T2180
Test name
Test status
Simulation time 146777137 ps
CPU time 0.88 seconds
Started Jul 31 05:43:57 PM PDT 24
Finished Jul 31 05:43:58 PM PDT 24
Peak memory 207032 kb
Host smart-3fc46b9a-8dc1-4be6-b7eb-7b7d3e550326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59074
6549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.590746549
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.838925177
Short name T129
Test name
Test status
Simulation time 216760250 ps
CPU time 1.01 seconds
Started Jul 31 05:43:55 PM PDT 24
Finished Jul 31 05:43:56 PM PDT 24
Peak memory 206984 kb
Host smart-99b05b86-0fed-45a2-8783-b94af9d07a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83892
5177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.838925177
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3863427049
Short name T763
Test name
Test status
Simulation time 179829361 ps
CPU time 0.92 seconds
Started Jul 31 05:43:54 PM PDT 24
Finished Jul 31 05:43:55 PM PDT 24
Peak memory 206976 kb
Host smart-1e28952f-a903-44d0-8ccb-74eb0f678ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38634
27049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3863427049
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.1006237430
Short name T881
Test name
Test status
Simulation time 172664266 ps
CPU time 0.88 seconds
Started Jul 31 05:43:57 PM PDT 24
Finished Jul 31 05:43:58 PM PDT 24
Peak memory 207012 kb
Host smart-1db785cf-5403-4e03-8ba1-4a749aa6156a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10062
37430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.1006237430
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.1395953127
Short name T547
Test name
Test status
Simulation time 151095160 ps
CPU time 0.88 seconds
Started Jul 31 05:43:53 PM PDT 24
Finished Jul 31 05:43:54 PM PDT 24
Peak memory 207000 kb
Host smart-76115047-d3c3-499e-9555-d94ab9c2b57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13959
53127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.1395953127
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.2246965862
Short name T170
Test name
Test status
Simulation time 226120695 ps
CPU time 0.95 seconds
Started Jul 31 05:43:55 PM PDT 24
Finished Jul 31 05:43:56 PM PDT 24
Peak memory 207012 kb
Host smart-490e1c6b-ca4a-4b9f-8c0b-b83dfe1ce135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22469
65862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.2246965862
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.3459077966
Short name T1608
Test name
Test status
Simulation time 224644131 ps
CPU time 0.96 seconds
Started Jul 31 05:43:53 PM PDT 24
Finished Jul 31 05:43:54 PM PDT 24
Peak memory 206996 kb
Host smart-0fb50245-a476-4ef8-8295-b9ffdf8ca159
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3459077966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.3459077966
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3267621364
Short name T2277
Test name
Test status
Simulation time 164076291 ps
CPU time 0.85 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:43:57 PM PDT 24
Peak memory 206964 kb
Host smart-d504b4e8-6ebc-4d05-8891-5423342830a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32676
21364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3267621364
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.881404037
Short name T1781
Test name
Test status
Simulation time 44313345 ps
CPU time 0.73 seconds
Started Jul 31 05:43:55 PM PDT 24
Finished Jul 31 05:43:56 PM PDT 24
Peak memory 206936 kb
Host smart-4604d32e-84ea-4a23-9e3b-cc899b109fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88140
4037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.881404037
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2749432514
Short name T2800
Test name
Test status
Simulation time 17273657749 ps
CPU time 39.93 seconds
Started Jul 31 05:43:54 PM PDT 24
Finished Jul 31 05:44:34 PM PDT 24
Peak memory 215408 kb
Host smart-821d8c02-45b2-4eaa-a804-ab581876b275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27494
32514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2749432514
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1370885758
Short name T2612
Test name
Test status
Simulation time 166694186 ps
CPU time 0.86 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:43:56 PM PDT 24
Peak memory 206968 kb
Host smart-29cb2b7b-842b-4c75-82a9-e31e4483daa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13708
85758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1370885758
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3589663981
Short name T555
Test name
Test status
Simulation time 175874321 ps
CPU time 0.95 seconds
Started Jul 31 05:43:59 PM PDT 24
Finished Jul 31 05:44:01 PM PDT 24
Peak memory 206984 kb
Host smart-5acece5e-eaee-4096-ad91-87de7a479259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35896
63981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3589663981
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2747508447
Short name T808
Test name
Test status
Simulation time 222139005 ps
CPU time 0.98 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:43:58 PM PDT 24
Peak memory 207036 kb
Host smart-f0ccac84-e331-41c3-9a47-3014bb73333c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27475
08447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2747508447
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3382597631
Short name T2338
Test name
Test status
Simulation time 172015043 ps
CPU time 0.91 seconds
Started Jul 31 05:43:58 PM PDT 24
Finished Jul 31 05:43:59 PM PDT 24
Peak memory 207024 kb
Host smart-d57a9c13-294d-42ba-b061-f14b629e3b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33825
97631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3382597631
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1992416820
Short name T1531
Test name
Test status
Simulation time 180381532 ps
CPU time 0.89 seconds
Started Jul 31 05:43:54 PM PDT 24
Finished Jul 31 05:43:55 PM PDT 24
Peak memory 206972 kb
Host smart-c54ebdbf-4b10-4f1f-8334-3acb5d79e76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19924
16820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1992416820
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.301140856
Short name T1932
Test name
Test status
Simulation time 161956308 ps
CPU time 0.87 seconds
Started Jul 31 05:43:52 PM PDT 24
Finished Jul 31 05:43:53 PM PDT 24
Peak memory 206952 kb
Host smart-7905f6cb-3ee2-47bb-bc5d-7cba0d040bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30114
0856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.301140856
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.4292152608
Short name T461
Test name
Test status
Simulation time 152172503 ps
CPU time 0.87 seconds
Started Jul 31 05:43:55 PM PDT 24
Finished Jul 31 05:43:56 PM PDT 24
Peak memory 207000 kb
Host smart-7729bd08-4436-4ca1-9d84-a1740e8e4872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42921
52608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.4292152608
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3090004765
Short name T1602
Test name
Test status
Simulation time 258154256 ps
CPU time 1.08 seconds
Started Jul 31 05:43:57 PM PDT 24
Finished Jul 31 05:43:59 PM PDT 24
Peak memory 206992 kb
Host smart-75fcaac2-c4d7-4397-959f-073f2219ce97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
04765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3090004765
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.2220832535
Short name T816
Test name
Test status
Simulation time 5044792441 ps
CPU time 38.24 seconds
Started Jul 31 05:43:53 PM PDT 24
Finished Jul 31 05:44:32 PM PDT 24
Peak memory 216800 kb
Host smart-6cab2731-9e0c-48c1-a570-05c5c0c434b1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2220832535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2220832535
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1445058334
Short name T2551
Test name
Test status
Simulation time 144250004 ps
CPU time 0.88 seconds
Started Jul 31 05:43:55 PM PDT 24
Finished Jul 31 05:43:56 PM PDT 24
Peak memory 207012 kb
Host smart-a2f025fd-f076-4681-9395-ae99ee6b34b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14450
58334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1445058334
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2190919254
Short name T2388
Test name
Test status
Simulation time 155849264 ps
CPU time 0.88 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:43:57 PM PDT 24
Peak memory 206980 kb
Host smart-025fbd2e-72cc-44e6-98de-84994d75adfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21909
19254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2190919254
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.4000586301
Short name T2516
Test name
Test status
Simulation time 1121952484 ps
CPU time 2.55 seconds
Started Jul 31 05:43:56 PM PDT 24
Finished Jul 31 05:43:58 PM PDT 24
Peak memory 207156 kb
Host smart-fd5e1187-1078-48e9-b5d0-52f8e7690fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40005
86301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.4000586301
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.1904842070
Short name T567
Test name
Test status
Simulation time 5497717703 ps
CPU time 44.78 seconds
Started Jul 31 05:43:57 PM PDT 24
Finished Jul 31 05:44:42 PM PDT 24
Peak memory 207192 kb
Host smart-c62ed4f7-40d1-4d36-8d7b-750b66ef245b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19048
42070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1904842070
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.3139485640
Short name T1502
Test name
Test status
Simulation time 1165340193 ps
CPU time 26.4 seconds
Started Jul 31 05:43:58 PM PDT 24
Finished Jul 31 05:44:24 PM PDT 24
Peak memory 207108 kb
Host smart-a6bafd35-fed1-48f5-93ff-3ec6fb966447
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139485640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.3139485640
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.758986316
Short name T1703
Test name
Test status
Simulation time 43315111 ps
CPU time 0.68 seconds
Started Jul 31 05:44:05 PM PDT 24
Finished Jul 31 05:44:06 PM PDT 24
Peak memory 207044 kb
Host smart-6aafe264-029e-40e5-92b6-05d6e0ef09b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=758986316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.758986316
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2592965576
Short name T762
Test name
Test status
Simulation time 4200847750 ps
CPU time 6.41 seconds
Started Jul 31 05:43:54 PM PDT 24
Finished Jul 31 05:44:00 PM PDT 24
Peak memory 207136 kb
Host smart-23372ae7-b35f-41c7-b746-4bb93e14eeb2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592965576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_disconnect.2592965576
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.3438536520
Short name T1677
Test name
Test status
Simulation time 13368089951 ps
CPU time 14.23 seconds
Started Jul 31 05:43:53 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 207200 kb
Host smart-e60a22ee-c767-465f-afdc-a4c5ab5f217a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438536520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.3438536520
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.598180456
Short name T1123
Test name
Test status
Simulation time 23310021844 ps
CPU time 25.9 seconds
Started Jul 31 05:43:55 PM PDT 24
Finished Jul 31 05:44:21 PM PDT 24
Peak memory 207200 kb
Host smart-6e368989-b11c-41ed-91a2-29975adb73ae
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598180456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ao
n_wake_resume.598180456
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2444496010
Short name T1638
Test name
Test status
Simulation time 149203725 ps
CPU time 1.05 seconds
Started Jul 31 05:43:59 PM PDT 24
Finished Jul 31 05:44:00 PM PDT 24
Peak memory 206996 kb
Host smart-4ad78c3f-a933-4597-a8c2-c8cf3aae09d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24444
96010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2444496010
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.803426722
Short name T845
Test name
Test status
Simulation time 146838499 ps
CPU time 0.85 seconds
Started Jul 31 05:43:53 PM PDT 24
Finished Jul 31 05:43:54 PM PDT 24
Peak memory 206960 kb
Host smart-e7bb29e0-0a34-49fa-aed1-cfd372d9539a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80342
6722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.803426722
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2399790762
Short name T1621
Test name
Test status
Simulation time 294537490 ps
CPU time 1.27 seconds
Started Jul 31 05:43:58 PM PDT 24
Finished Jul 31 05:43:59 PM PDT 24
Peak memory 207036 kb
Host smart-c67b5b29-52fb-4702-9343-965885cb7d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23997
90762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2399790762
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.1484605947
Short name T458
Test name
Test status
Simulation time 818378999 ps
CPU time 2.21 seconds
Started Jul 31 05:43:55 PM PDT 24
Finished Jul 31 05:43:57 PM PDT 24
Peak memory 207060 kb
Host smart-b2409984-db7e-4b39-9943-0fe343241d7e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1484605947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.1484605947
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1048293594
Short name T2766
Test name
Test status
Simulation time 21521754972 ps
CPU time 42.47 seconds
Started Jul 31 05:43:53 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 207236 kb
Host smart-11aa680c-c1ec-430d-b7e0-12e7a6bc86e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10482
93594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1048293594
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_device_timeout.3536169716
Short name T993
Test name
Test status
Simulation time 422011097 ps
CPU time 8.19 seconds
Started Jul 31 05:43:58 PM PDT 24
Finished Jul 31 05:44:06 PM PDT 24
Peak memory 207144 kb
Host smart-2d5217e2-72f8-4c51-8bf4-b24139156831
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536169716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.3536169716
Directory /workspace/26.usbdev_device_timeout/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1905501258
Short name T2106
Test name
Test status
Simulation time 444409231 ps
CPU time 1.42 seconds
Started Jul 31 05:43:54 PM PDT 24
Finished Jul 31 05:43:55 PM PDT 24
Peak memory 206948 kb
Host smart-453ec0b6-6d5b-40d2-9045-a48b8220eeae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19055
01258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1905501258
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3899634276
Short name T2041
Test name
Test status
Simulation time 142011918 ps
CPU time 0.87 seconds
Started Jul 31 05:43:57 PM PDT 24
Finished Jul 31 05:43:58 PM PDT 24
Peak memory 207012 kb
Host smart-9e197852-b2c1-4ac6-a8d7-c80938189df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38996
34276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3899634276
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1802039813
Short name T1780
Test name
Test status
Simulation time 39984856 ps
CPU time 0.71 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 206984 kb
Host smart-66548307-da5e-4694-b6d2-2f8cf3c210f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18020
39813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1802039813
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.2537652439
Short name T621
Test name
Test status
Simulation time 1051940462 ps
CPU time 2.61 seconds
Started Jul 31 05:44:02 PM PDT 24
Finished Jul 31 05:44:05 PM PDT 24
Peak memory 207144 kb
Host smart-6f6fb143-9706-4b1a-a35a-eea091ee4370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25376
52439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2537652439
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.1505362703
Short name T2372
Test name
Test status
Simulation time 286766038 ps
CPU time 2.2 seconds
Started Jul 31 05:44:02 PM PDT 24
Finished Jul 31 05:44:05 PM PDT 24
Peak memory 207028 kb
Host smart-1100d3b9-15e7-4d5b-9558-0e85399d2755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15053
62703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.1505362703
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.791864058
Short name T2718
Test name
Test status
Simulation time 248733344 ps
CPU time 1.22 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:08 PM PDT 24
Peak memory 215276 kb
Host smart-70bcbdb7-9a26-4cf6-b76b-ff9934c0fd54
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=791864058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.791864058
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2746719481
Short name T1199
Test name
Test status
Simulation time 168273668 ps
CPU time 0.87 seconds
Started Jul 31 05:44:01 PM PDT 24
Finished Jul 31 05:44:02 PM PDT 24
Peak memory 206980 kb
Host smart-680f5441-1aa5-479d-b0fd-db6cc80cc3cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27467
19481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2746719481
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.500807090
Short name T1869
Test name
Test status
Simulation time 201650246 ps
CPU time 0.93 seconds
Started Jul 31 05:44:10 PM PDT 24
Finished Jul 31 05:44:11 PM PDT 24
Peak memory 206984 kb
Host smart-33d774ca-6d3b-4026-b596-dbc23c7d8860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50080
7090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.500807090
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.1066150406
Short name T2425
Test name
Test status
Simulation time 8668495265 ps
CPU time 246.95 seconds
Started Jul 31 05:44:02 PM PDT 24
Finished Jul 31 05:48:09 PM PDT 24
Peak memory 215396 kb
Host smart-b9e24c5a-44c8-4bbb-809d-95739c2d80de
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1066150406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.1066150406
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3298728367
Short name T2396
Test name
Test status
Simulation time 230580291 ps
CPU time 1.1 seconds
Started Jul 31 05:43:59 PM PDT 24
Finished Jul 31 05:44:01 PM PDT 24
Peak memory 206992 kb
Host smart-49716b60-241f-4104-9288-5f6a1f02664c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32987
28367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3298728367
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.812827417
Short name T2160
Test name
Test status
Simulation time 23290294758 ps
CPU time 25.99 seconds
Started Jul 31 05:44:01 PM PDT 24
Finished Jul 31 05:44:27 PM PDT 24
Peak memory 207196 kb
Host smart-0aef0dd5-f535-44d7-9d12-732535cd7195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81282
7417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.812827417
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.3966022707
Short name T417
Test name
Test status
Simulation time 3270529398 ps
CPU time 5.56 seconds
Started Jul 31 05:44:00 PM PDT 24
Finished Jul 31 05:44:06 PM PDT 24
Peak memory 207140 kb
Host smart-1ea43388-ad3e-4363-9927-88ca83a87d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39660
22707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.3966022707
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.3895295132
Short name T958
Test name
Test status
Simulation time 5737678551 ps
CPU time 166.32 seconds
Started Jul 31 05:44:03 PM PDT 24
Finished Jul 31 05:46:50 PM PDT 24
Peak memory 215352 kb
Host smart-b307b025-a57c-4227-ba46-7e4119d35642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38952
95132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.3895295132
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.405840930
Short name T1748
Test name
Test status
Simulation time 6009923509 ps
CPU time 49.31 seconds
Started Jul 31 05:44:03 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 207216 kb
Host smart-342d2c65-87b6-43e4-adbf-5bd9e2a187d4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=405840930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.405840930
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.2996911004
Short name T752
Test name
Test status
Simulation time 249942287 ps
CPU time 1.04 seconds
Started Jul 31 05:43:59 PM PDT 24
Finished Jul 31 05:44:00 PM PDT 24
Peak memory 206988 kb
Host smart-68af5ede-d7a7-4f07-a93d-99cc603b49b9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2996911004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.2996911004
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.694443227
Short name T429
Test name
Test status
Simulation time 193904468 ps
CPU time 0.94 seconds
Started Jul 31 05:44:07 PM PDT 24
Finished Jul 31 05:44:08 PM PDT 24
Peak memory 207020 kb
Host smart-00cc26a8-2e5d-4fa5-a82e-eac496fff81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69444
3227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.694443227
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3034959140
Short name T2393
Test name
Test status
Simulation time 4938752676 ps
CPU time 40.41 seconds
Started Jul 31 05:44:02 PM PDT 24
Finished Jul 31 05:44:43 PM PDT 24
Peak memory 216792 kb
Host smart-ddcf42b1-d5d1-40f9-9574-6f761c34be52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30349
59140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3034959140
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.359005932
Short name T2408
Test name
Test status
Simulation time 7884407861 ps
CPU time 235.28 seconds
Started Jul 31 05:44:00 PM PDT 24
Finished Jul 31 05:47:56 PM PDT 24
Peak memory 215384 kb
Host smart-6a578d2c-7f23-444e-91e6-c1149e0559ca
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=359005932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.359005932
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.1603693153
Short name T560
Test name
Test status
Simulation time 153918862 ps
CPU time 0.87 seconds
Started Jul 31 05:44:05 PM PDT 24
Finished Jul 31 05:44:06 PM PDT 24
Peak memory 206984 kb
Host smart-a78b0b10-4ee9-4bfd-bbee-20f052010fa8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1603693153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.1603693153
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2218802798
Short name T1001
Test name
Test status
Simulation time 153399035 ps
CPU time 0.99 seconds
Started Jul 31 05:44:03 PM PDT 24
Finished Jul 31 05:44:04 PM PDT 24
Peak memory 206984 kb
Host smart-ce69a848-cd24-4f9a-8acf-f92938055d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22188
02798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2218802798
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.723332200
Short name T2665
Test name
Test status
Simulation time 185071258 ps
CPU time 0.91 seconds
Started Jul 31 05:44:03 PM PDT 24
Finished Jul 31 05:44:04 PM PDT 24
Peak memory 207016 kb
Host smart-67017119-8ae9-4c18-85bc-2144552de32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72333
2200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.723332200
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.2088051660
Short name T728
Test name
Test status
Simulation time 221608732 ps
CPU time 0.97 seconds
Started Jul 31 05:44:02 PM PDT 24
Finished Jul 31 05:44:03 PM PDT 24
Peak memory 206980 kb
Host smart-0d57a5a9-afa4-443e-9384-ac1534227665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20880
51660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2088051660
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2719504996
Short name T2044
Test name
Test status
Simulation time 183652007 ps
CPU time 0.93 seconds
Started Jul 31 05:44:00 PM PDT 24
Finished Jul 31 05:44:01 PM PDT 24
Peak memory 206996 kb
Host smart-2dcc609b-852d-4631-94e3-19fe4a9cdb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27195
04996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2719504996
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3221743737
Short name T2115
Test name
Test status
Simulation time 191095085 ps
CPU time 0.91 seconds
Started Jul 31 05:43:59 PM PDT 24
Finished Jul 31 05:44:00 PM PDT 24
Peak memory 207000 kb
Host smart-452b6cca-3568-4cb4-a0b8-a3eb2083842d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32217
43737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3221743737
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1034463067
Short name T2839
Test name
Test status
Simulation time 152617201 ps
CPU time 0.83 seconds
Started Jul 31 05:44:03 PM PDT 24
Finished Jul 31 05:44:04 PM PDT 24
Peak memory 206988 kb
Host smart-6b872ea6-2cd2-4bea-b5c1-43bd29d3b591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10344
63067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1034463067
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.2899102133
Short name T2240
Test name
Test status
Simulation time 203585744 ps
CPU time 1.02 seconds
Started Jul 31 05:44:02 PM PDT 24
Finished Jul 31 05:44:03 PM PDT 24
Peak memory 207012 kb
Host smart-fa687f49-200e-446c-9f4b-09e9b8601be4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2899102133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.2899102133
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.1818921369
Short name T2479
Test name
Test status
Simulation time 150057420 ps
CPU time 0.91 seconds
Started Jul 31 05:44:09 PM PDT 24
Finished Jul 31 05:44:10 PM PDT 24
Peak memory 206984 kb
Host smart-4831f9be-f52b-42de-a1f9-eb7d3bf7b800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18189
21369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.1818921369
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1732060948
Short name T1496
Test name
Test status
Simulation time 36035450 ps
CPU time 0.69 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 206968 kb
Host smart-2a613bc1-6bf0-4e1f-8e95-2752ad6022a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17320
60948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1732060948
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1689363480
Short name T2036
Test name
Test status
Simulation time 9065013872 ps
CPU time 22.25 seconds
Started Jul 31 05:44:10 PM PDT 24
Finished Jul 31 05:44:32 PM PDT 24
Peak memory 215440 kb
Host smart-fca5a0a9-319c-4086-978b-b86512af72f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16893
63480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1689363480
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.21438815
Short name T742
Test name
Test status
Simulation time 164642414 ps
CPU time 0.83 seconds
Started Jul 31 05:44:09 PM PDT 24
Finished Jul 31 05:44:10 PM PDT 24
Peak memory 207024 kb
Host smart-d46d67a7-4439-41d5-bb00-2a477cf258e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21438
815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.21438815
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3216725596
Short name T1485
Test name
Test status
Simulation time 182898254 ps
CPU time 0.89 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 206972 kb
Host smart-bc1b6e2e-6269-4a4d-beb9-46b813194111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32167
25596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3216725596
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2856435146
Short name T872
Test name
Test status
Simulation time 241312302 ps
CPU time 0.98 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 206992 kb
Host smart-5bb27dbf-7930-4b2e-a297-0c9a54816094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28564
35146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2856435146
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.4290360186
Short name T740
Test name
Test status
Simulation time 174997282 ps
CPU time 0.89 seconds
Started Jul 31 05:44:07 PM PDT 24
Finished Jul 31 05:44:08 PM PDT 24
Peak memory 207000 kb
Host smart-8d9d8d96-3da2-479c-8ab8-cded20cde2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42903
60186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.4290360186
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3556769526
Short name T295
Test name
Test status
Simulation time 157613917 ps
CPU time 0.9 seconds
Started Jul 31 05:44:07 PM PDT 24
Finished Jul 31 05:44:08 PM PDT 24
Peak memory 206972 kb
Host smart-3c7c1031-b79d-456f-a4e4-a676959d2381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35567
69526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3556769526
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2509509991
Short name T617
Test name
Test status
Simulation time 154078743 ps
CPU time 0.87 seconds
Started Jul 31 05:44:04 PM PDT 24
Finished Jul 31 05:44:05 PM PDT 24
Peak memory 206968 kb
Host smart-d00958fe-c97a-41e6-8d3f-79553c03f28d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25095
09991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2509509991
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.728658180
Short name T359
Test name
Test status
Simulation time 201869498 ps
CPU time 0.94 seconds
Started Jul 31 05:44:07 PM PDT 24
Finished Jul 31 05:44:08 PM PDT 24
Peak memory 207016 kb
Host smart-a8ff6c63-616e-4f3c-911d-7d6ee3754783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72865
8180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.728658180
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2565502444
Short name T1075
Test name
Test status
Simulation time 221570485 ps
CPU time 1.02 seconds
Started Jul 31 05:44:10 PM PDT 24
Finished Jul 31 05:44:11 PM PDT 24
Peak memory 207028 kb
Host smart-4582a124-0492-48ed-86a5-99743bcc851d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25655
02444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2565502444
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2461487810
Short name T1464
Test name
Test status
Simulation time 5571587361 ps
CPU time 169.25 seconds
Started Jul 31 05:44:05 PM PDT 24
Finished Jul 31 05:46:54 PM PDT 24
Peak memory 215392 kb
Host smart-ccf1b094-766e-489e-9194-c969e25e4f6f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2461487810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2461487810
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3434335310
Short name T620
Test name
Test status
Simulation time 161502745 ps
CPU time 0.87 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 207000 kb
Host smart-24730c0a-fd51-48d2-8009-69088aefac5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34343
35310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3434335310
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2522910774
Short name T1986
Test name
Test status
Simulation time 168120288 ps
CPU time 0.86 seconds
Started Jul 31 05:44:09 PM PDT 24
Finished Jul 31 05:44:10 PM PDT 24
Peak memory 206972 kb
Host smart-3d099733-ce4a-4b88-ab31-7ea2421f5778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25229
10774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2522910774
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.1913288608
Short name T1812
Test name
Test status
Simulation time 945373950 ps
CPU time 2.49 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:08 PM PDT 24
Peak memory 207008 kb
Host smart-ca9f0eb6-399b-403b-b334-811f183f9f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19132
88608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.1913288608
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.1376752099
Short name T1541
Test name
Test status
Simulation time 4568125375 ps
CPU time 43.6 seconds
Started Jul 31 05:44:10 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 216796 kb
Host smart-fc23a4ff-d5d3-4573-838d-ced783dadc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13767
52099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.1376752099
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.3609982590
Short name T84
Test name
Test status
Simulation time 1012553129 ps
CPU time 23.47 seconds
Started Jul 31 05:43:57 PM PDT 24
Finished Jul 31 05:44:21 PM PDT 24
Peak memory 207112 kb
Host smart-654cd363-59a1-4550-89d6-869ed0f11f63
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609982590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.3609982590
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.741273306
Short name T1609
Test name
Test status
Simulation time 56605848 ps
CPU time 0.69 seconds
Started Jul 31 05:44:12 PM PDT 24
Finished Jul 31 05:44:12 PM PDT 24
Peak memory 207012 kb
Host smart-982bbe9a-9f2a-4b0e-84df-50d9d6814fe2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=741273306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.741273306
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2541578249
Short name T210
Test name
Test status
Simulation time 3733886625 ps
CPU time 5.48 seconds
Started Jul 31 05:44:07 PM PDT 24
Finished Jul 31 05:44:13 PM PDT 24
Peak memory 207168 kb
Host smart-c05c1461-0ad4-4b07-bd6f-47769da5ce12
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541578249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.2541578249
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2551371505
Short name T836
Test name
Test status
Simulation time 13400053393 ps
CPU time 16 seconds
Started Jul 31 05:44:04 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 207212 kb
Host smart-b6fa6cc6-9a1c-4622-89e2-17e76767ff4c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551371505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2551371505
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.2009438534
Short name T932
Test name
Test status
Simulation time 23407382333 ps
CPU time 27.59 seconds
Started Jul 31 05:44:08 PM PDT 24
Finished Jul 31 05:44:36 PM PDT 24
Peak memory 207184 kb
Host smart-9255daf9-f5ed-4aff-882a-23b82c03c6f3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009438534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.2009438534
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.3572708790
Short name T969
Test name
Test status
Simulation time 154683261 ps
CPU time 0.86 seconds
Started Jul 31 05:44:10 PM PDT 24
Finished Jul 31 05:44:11 PM PDT 24
Peak memory 207024 kb
Host smart-5c849ab8-a9f1-4654-8871-a86dcc74c6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35727
08790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.3572708790
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.286729724
Short name T2291
Test name
Test status
Simulation time 203474519 ps
CPU time 0.89 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 206964 kb
Host smart-19d142f6-0b8d-46d0-8add-163425945eae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28672
9724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.286729724
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.1685168904
Short name T995
Test name
Test status
Simulation time 434244704 ps
CPU time 1.54 seconds
Started Jul 31 05:44:08 PM PDT 24
Finished Jul 31 05:44:09 PM PDT 24
Peak memory 207004 kb
Host smart-80871a4d-48f3-4342-a1c5-02301974a26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16851
68904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.1685168904
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.1600171065
Short name T2383
Test name
Test status
Simulation time 1245880919 ps
CPU time 3.41 seconds
Started Jul 31 05:44:05 PM PDT 24
Finished Jul 31 05:44:09 PM PDT 24
Peak memory 207148 kb
Host smart-368bb901-3d16-4685-9c4b-75dccd87107e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1600171065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1600171065
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.2267677531
Short name T168
Test name
Test status
Simulation time 6454417383 ps
CPU time 16.59 seconds
Started Jul 31 05:44:05 PM PDT 24
Finished Jul 31 05:44:22 PM PDT 24
Peak memory 207220 kb
Host smart-d5c3f81f-809f-4195-ac66-f913e488b478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22676
77531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2267677531
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_device_timeout.906966179
Short name T966
Test name
Test status
Simulation time 722707361 ps
CPU time 16.03 seconds
Started Jul 31 05:44:08 PM PDT 24
Finished Jul 31 05:44:24 PM PDT 24
Peak memory 207016 kb
Host smart-0978500e-1dcd-4896-b3fa-752c7ec4f3e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906966179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.906966179
Directory /workspace/27.usbdev_device_timeout/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1316341929
Short name T2809
Test name
Test status
Simulation time 430093522 ps
CPU time 1.42 seconds
Started Jul 31 05:44:08 PM PDT 24
Finished Jul 31 05:44:09 PM PDT 24
Peak memory 206972 kb
Host smart-dc879d24-55d8-4f5e-88f4-b57807e4e889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13163
41929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1316341929
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.1379978069
Short name T38
Test name
Test status
Simulation time 194118101 ps
CPU time 0.87 seconds
Started Jul 31 05:44:07 PM PDT 24
Finished Jul 31 05:44:08 PM PDT 24
Peak memory 206964 kb
Host smart-ced7162c-3c30-4dd0-bf6a-995807b3fc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13799
78069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.1379978069
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.2149859532
Short name T2304
Test name
Test status
Simulation time 40030857 ps
CPU time 0.7 seconds
Started Jul 31 05:44:09 PM PDT 24
Finished Jul 31 05:44:10 PM PDT 24
Peak memory 206964 kb
Host smart-db506914-56a3-4fd3-a1b8-ef59c8120f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21498
59532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2149859532
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.113086939
Short name T2851
Test name
Test status
Simulation time 895513826 ps
CPU time 2.39 seconds
Started Jul 31 05:44:08 PM PDT 24
Finished Jul 31 05:44:10 PM PDT 24
Peak memory 207136 kb
Host smart-54468acc-edad-4528-b279-9a6afd7ebbf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11308
6939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.113086939
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3560967843
Short name T1136
Test name
Test status
Simulation time 192638483 ps
CPU time 1.84 seconds
Started Jul 31 05:44:08 PM PDT 24
Finished Jul 31 05:44:10 PM PDT 24
Peak memory 207044 kb
Host smart-e0156930-6331-4848-99e5-aa6a64b6e314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35609
67843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3560967843
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.2409088121
Short name T1529
Test name
Test status
Simulation time 173007177 ps
CPU time 0.97 seconds
Started Jul 31 05:44:10 PM PDT 24
Finished Jul 31 05:44:11 PM PDT 24
Peak memory 215320 kb
Host smart-413cf342-4494-48f6-a03f-a04f9f77abd9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2409088121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2409088121
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2733722058
Short name T1457
Test name
Test status
Simulation time 167411963 ps
CPU time 0.88 seconds
Started Jul 31 05:44:11 PM PDT 24
Finished Jul 31 05:44:12 PM PDT 24
Peak memory 206956 kb
Host smart-cb4d74db-7841-4316-9cda-f36438d295e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27337
22058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2733722058
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3021229749
Short name T2768
Test name
Test status
Simulation time 241263399 ps
CPU time 1.05 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 206972 kb
Host smart-a4ec7082-1ae2-41d6-b6a0-d31991be4837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30212
29749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3021229749
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.52880020
Short name T371
Test name
Test status
Simulation time 8656581108 ps
CPU time 259.72 seconds
Started Jul 31 05:44:05 PM PDT 24
Finished Jul 31 05:48:25 PM PDT 24
Peak memory 215356 kb
Host smart-0d7333cc-4334-499c-be21-64b1d53909a2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=52880020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.52880020
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.1279888532
Short name T666
Test name
Test status
Simulation time 6892293335 ps
CPU time 48.71 seconds
Started Jul 31 05:44:07 PM PDT 24
Finished Jul 31 05:44:56 PM PDT 24
Peak memory 207212 kb
Host smart-b270c9e4-af6e-41a9-8d8f-9b2d441619c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1279888532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.1279888532
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.1461615830
Short name T646
Test name
Test status
Simulation time 193712747 ps
CPU time 0.9 seconds
Started Jul 31 05:44:04 PM PDT 24
Finished Jul 31 05:44:05 PM PDT 24
Peak memory 206980 kb
Host smart-1e10a8d4-ead1-4e5a-afa9-15dade6efe6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14616
15830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1461615830
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.2314435700
Short name T2178
Test name
Test status
Simulation time 23311797053 ps
CPU time 25.84 seconds
Started Jul 31 05:44:08 PM PDT 24
Finished Jul 31 05:44:34 PM PDT 24
Peak memory 207228 kb
Host smart-1ce5e767-e78a-4b85-afab-65e1bb64367c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23144
35700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.2314435700
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.1088802813
Short name T1353
Test name
Test status
Simulation time 3275977244 ps
CPU time 4.84 seconds
Started Jul 31 05:44:11 PM PDT 24
Finished Jul 31 05:44:16 PM PDT 24
Peak memory 207136 kb
Host smart-651fbade-1018-4ae4-8a12-39f5bc11bd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10888
02813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.1088802813
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.959482844
Short name T810
Test name
Test status
Simulation time 8969295415 ps
CPU time 90.63 seconds
Started Jul 31 05:44:08 PM PDT 24
Finished Jul 31 05:45:39 PM PDT 24
Peak memory 215408 kb
Host smart-fc92bf22-2810-40f2-a605-4bd5d0d5ce16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95948
2844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.959482844
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1165156456
Short name T2343
Test name
Test status
Simulation time 3688791302 ps
CPU time 108.95 seconds
Started Jul 31 05:44:11 PM PDT 24
Finished Jul 31 05:46:01 PM PDT 24
Peak memory 215432 kb
Host smart-7559f6a3-db03-4137-844a-3177a57a9855
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1165156456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1165156456
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.672247657
Short name T381
Test name
Test status
Simulation time 240595581 ps
CPU time 1.09 seconds
Started Jul 31 05:44:07 PM PDT 24
Finished Jul 31 05:44:09 PM PDT 24
Peak memory 206980 kb
Host smart-21e1cfeb-b0db-434b-97b6-bc0a7a783b98
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=672247657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.672247657
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.4173422117
Short name T2563
Test name
Test status
Simulation time 204337465 ps
CPU time 0.92 seconds
Started Jul 31 05:44:05 PM PDT 24
Finished Jul 31 05:44:06 PM PDT 24
Peak memory 207056 kb
Host smart-f66a3638-5d8e-4a6e-85db-fec74588b5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734
22117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.4173422117
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.3389282077
Short name T1587
Test name
Test status
Simulation time 7665509088 ps
CPU time 80.39 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:45:27 PM PDT 24
Peak memory 207216 kb
Host smart-ae9b17d2-f7df-42e9-ada7-4975bc0911eb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3389282077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.3389282077
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.3888474509
Short name T1284
Test name
Test status
Simulation time 156181320 ps
CPU time 0.86 seconds
Started Jul 31 05:44:06 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 206996 kb
Host smart-1a76da1e-d3f7-4c71-bb94-282ad055456f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3888474509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.3888474509
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.3961209457
Short name T1301
Test name
Test status
Simulation time 156033137 ps
CPU time 0.82 seconds
Started Jul 31 05:44:12 PM PDT 24
Finished Jul 31 05:44:13 PM PDT 24
Peak memory 206980 kb
Host smart-9af5cc2e-2826-41f1-886a-cca31e5914dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39612
09457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.3961209457
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1895229623
Short name T122
Test name
Test status
Simulation time 204562069 ps
CPU time 0.95 seconds
Started Jul 31 05:44:11 PM PDT 24
Finished Jul 31 05:44:12 PM PDT 24
Peak memory 206920 kb
Host smart-73c107dc-bcc6-40da-a1fc-3326b70c3a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18952
29623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1895229623
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.467030907
Short name T1804
Test name
Test status
Simulation time 163171622 ps
CPU time 0.91 seconds
Started Jul 31 05:44:13 PM PDT 24
Finished Jul 31 05:44:14 PM PDT 24
Peak memory 206996 kb
Host smart-b41d6a08-a313-4145-b8b9-135fc88ba12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46703
0907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.467030907
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.2661795912
Short name T1402
Test name
Test status
Simulation time 188288683 ps
CPU time 0.96 seconds
Started Jul 31 05:44:14 PM PDT 24
Finished Jul 31 05:44:15 PM PDT 24
Peak memory 206976 kb
Host smart-73d140e2-7a27-4bc2-af2b-bc7012bafa77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26617
95912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2661795912
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2631438277
Short name T1517
Test name
Test status
Simulation time 243272520 ps
CPU time 0.99 seconds
Started Jul 31 05:44:12 PM PDT 24
Finished Jul 31 05:44:13 PM PDT 24
Peak memory 207040 kb
Host smart-812cbb81-e936-41aa-9e1c-d8d377110be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26314
38277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2631438277
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.4034939286
Short name T2815
Test name
Test status
Simulation time 175427274 ps
CPU time 0.94 seconds
Started Jul 31 05:44:15 PM PDT 24
Finished Jul 31 05:44:16 PM PDT 24
Peak memory 207004 kb
Host smart-f3557db3-c58b-4f01-a166-1e2f678eb33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40349
39286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.4034939286
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3256006351
Short name T1637
Test name
Test status
Simulation time 182340168 ps
CPU time 0.9 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:44:18 PM PDT 24
Peak memory 207028 kb
Host smart-5b630891-603e-4f78-9b5d-24df54185692
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3256006351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3256006351
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.249819419
Short name T597
Test name
Test status
Simulation time 199044821 ps
CPU time 0.89 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:44:18 PM PDT 24
Peak memory 206932 kb
Host smart-380b61bb-0d06-42ac-baea-912db2a052b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24981
9419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.249819419
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3577295402
Short name T848
Test name
Test status
Simulation time 43069283 ps
CPU time 0.68 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:44:16 PM PDT 24
Peak memory 206944 kb
Host smart-373d19c8-4ed7-43fd-ae3a-6608d239a4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35772
95402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3577295402
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.566854363
Short name T2060
Test name
Test status
Simulation time 17803655614 ps
CPU time 48.02 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 215404 kb
Host smart-0601bda7-c6f1-4d9a-9cfa-1b46cd5a6de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56685
4363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.566854363
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.180057056
Short name T2419
Test name
Test status
Simulation time 174312598 ps
CPU time 0.9 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:44:17 PM PDT 24
Peak memory 206984 kb
Host smart-db3b644b-b236-47f3-ad56-425a8119391b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18005
7056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.180057056
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.1105978640
Short name T2076
Test name
Test status
Simulation time 212368559 ps
CPU time 0.98 seconds
Started Jul 31 05:44:13 PM PDT 24
Finished Jul 31 05:44:14 PM PDT 24
Peak memory 206964 kb
Host smart-d9e11e69-a72f-43b8-ab41-de8542595880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11059
78640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1105978640
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.773398681
Short name T2688
Test name
Test status
Simulation time 242083428 ps
CPU time 1.03 seconds
Started Jul 31 05:44:18 PM PDT 24
Finished Jul 31 05:44:19 PM PDT 24
Peak memory 206968 kb
Host smart-2aec1688-06da-433a-accb-79be9f353071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77339
8681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.773398681
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.4010007947
Short name T1512
Test name
Test status
Simulation time 174974658 ps
CPU time 0.93 seconds
Started Jul 31 05:44:14 PM PDT 24
Finished Jul 31 05:44:15 PM PDT 24
Peak memory 207028 kb
Host smart-1e91188d-271a-47f0-a6d6-0b3cfff20091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40100
07947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.4010007947
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3909668436
Short name T1599
Test name
Test status
Simulation time 159742121 ps
CPU time 0.85 seconds
Started Jul 31 05:44:15 PM PDT 24
Finished Jul 31 05:44:16 PM PDT 24
Peak memory 206988 kb
Host smart-4e2ef41d-7cc0-4ed9-bdde-7c8913736f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39096
68436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3909668436
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1284518949
Short name T462
Test name
Test status
Simulation time 200549129 ps
CPU time 0.84 seconds
Started Jul 31 05:44:15 PM PDT 24
Finished Jul 31 05:44:16 PM PDT 24
Peak memory 206960 kb
Host smart-af185bcd-7d6c-43e9-a17d-df823b7e54cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12845
18949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1284518949
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3750298328
Short name T1890
Test name
Test status
Simulation time 153453529 ps
CPU time 0.83 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:44:18 PM PDT 24
Peak memory 207024 kb
Host smart-939ffb1c-6b38-4581-bace-c51315fe0933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37502
98328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3750298328
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1665614134
Short name T2547
Test name
Test status
Simulation time 271662121 ps
CPU time 1.12 seconds
Started Jul 31 05:44:15 PM PDT 24
Finished Jul 31 05:44:16 PM PDT 24
Peak memory 206996 kb
Host smart-9d9a6517-8157-45b8-a364-33cd020cb31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16656
14134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1665614134
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2727346016
Short name T1008
Test name
Test status
Simulation time 5684279842 ps
CPU time 59.88 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:45:17 PM PDT 24
Peak memory 216728 kb
Host smart-7d3f0aed-aec0-49bc-9c59-7c0f74a3532d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2727346016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2727346016
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.388158009
Short name T2284
Test name
Test status
Simulation time 191275949 ps
CPU time 0.95 seconds
Started Jul 31 05:44:14 PM PDT 24
Finished Jul 31 05:44:15 PM PDT 24
Peak memory 207012 kb
Host smart-396446c4-fc55-4b8c-b154-28202ea92149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38815
8009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.388158009
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2744609781
Short name T681
Test name
Test status
Simulation time 226185882 ps
CPU time 1.09 seconds
Started Jul 31 05:44:15 PM PDT 24
Finished Jul 31 05:44:16 PM PDT 24
Peak memory 206992 kb
Host smart-ade3393a-694a-42b0-ac30-a3f3adaf4b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27446
09781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2744609781
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.3699570505
Short name T1027
Test name
Test status
Simulation time 1085522184 ps
CPU time 2.6 seconds
Started Jul 31 05:44:15 PM PDT 24
Finished Jul 31 05:44:18 PM PDT 24
Peak memory 207076 kb
Host smart-88396fac-fc90-4d3a-926b-f20e0f2aba15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36995
70505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.3699570505
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.3479026012
Short name T1270
Test name
Test status
Simulation time 7830032211 ps
CPU time 77.87 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:45:33 PM PDT 24
Peak memory 207228 kb
Host smart-113bff73-5c62-4950-b2c8-469982f91284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34790
26012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.3479026012
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.3591531521
Short name T787
Test name
Test status
Simulation time 762078730 ps
CPU time 15.79 seconds
Started Jul 31 05:44:10 PM PDT 24
Finished Jul 31 05:44:26 PM PDT 24
Peak memory 207044 kb
Host smart-4a74833b-9ac0-489c-9a09-c95ab51f5212
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591531521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.3591531521
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.837064011
Short name T178
Test name
Test status
Simulation time 39045893 ps
CPU time 0.69 seconds
Started Jul 31 05:44:24 PM PDT 24
Finished Jul 31 05:44:25 PM PDT 24
Peak memory 207032 kb
Host smart-be70a4ba-bd8a-428e-9fb5-2e176582b85d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=837064011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.837064011
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.2463114535
Short name T11
Test name
Test status
Simulation time 3658710826 ps
CPU time 5.25 seconds
Started Jul 31 05:44:14 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 207136 kb
Host smart-eed06b7e-e722-4ba6-a565-f765585ca49d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463114535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.2463114535
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1671980709
Short name T240
Test name
Test status
Simulation time 13303423324 ps
CPU time 15.83 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:44:32 PM PDT 24
Peak memory 207200 kb
Host smart-8c268590-b002-46b5-82e0-058f19d44025
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671980709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1671980709
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3843032784
Short name T2745
Test name
Test status
Simulation time 23304553283 ps
CPU time 27.53 seconds
Started Jul 31 05:44:14 PM PDT 24
Finished Jul 31 05:44:41 PM PDT 24
Peak memory 207188 kb
Host smart-e33af02a-f307-4552-a0c8-03c009364e62
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843032784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.3843032784
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.3801851601
Short name T2473
Test name
Test status
Simulation time 156720636 ps
CPU time 0.82 seconds
Started Jul 31 05:44:14 PM PDT 24
Finished Jul 31 05:44:15 PM PDT 24
Peak memory 206992 kb
Host smart-2061e187-f2d8-4c9a-b225-4ef2b7b040fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38018
51601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.3801851601
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.845927619
Short name T510
Test name
Test status
Simulation time 181708799 ps
CPU time 0.85 seconds
Started Jul 31 05:44:15 PM PDT 24
Finished Jul 31 05:44:16 PM PDT 24
Peak memory 206964 kb
Host smart-ae1a007b-0bb5-4f84-8a30-edc8b2953543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84592
7619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.845927619
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2489561796
Short name T399
Test name
Test status
Simulation time 330325717 ps
CPU time 1.27 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:44:17 PM PDT 24
Peak memory 206988 kb
Host smart-590da4c2-139a-4557-a2f8-31e3391733eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24895
61796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2489561796
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3054157422
Short name T467
Test name
Test status
Simulation time 967438759 ps
CPU time 2.65 seconds
Started Jul 31 05:44:19 PM PDT 24
Finished Jul 31 05:44:22 PM PDT 24
Peak memory 207128 kb
Host smart-82599c8a-7d2a-4772-83f4-9e9711c8ccd8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3054157422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3054157422
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.78438660
Short name T1679
Test name
Test status
Simulation time 23240817560 ps
CPU time 51.64 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 207164 kb
Host smart-7f5d4953-f7e2-4f51-bcef-81f01506d779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78438
660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.78438660
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_device_timeout.1361112778
Short name T2826
Test name
Test status
Simulation time 1328173106 ps
CPU time 29.34 seconds
Started Jul 31 05:44:20 PM PDT 24
Finished Jul 31 05:44:50 PM PDT 24
Peak memory 207040 kb
Host smart-5841e410-9d1d-450d-94b7-319ed641059f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361112778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.1361112778
Directory /workspace/28.usbdev_device_timeout/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3230530752
Short name T2503
Test name
Test status
Simulation time 437473264 ps
CPU time 1.48 seconds
Started Jul 31 05:44:20 PM PDT 24
Finished Jul 31 05:44:22 PM PDT 24
Peak memory 206936 kb
Host smart-838260a0-5c86-40e9-b157-50de4c084c03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32305
30752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3230530752
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.3847321089
Short name T1231
Test name
Test status
Simulation time 145949396 ps
CPU time 0.87 seconds
Started Jul 31 05:44:23 PM PDT 24
Finished Jul 31 05:44:24 PM PDT 24
Peak memory 206952 kb
Host smart-b0bdeac3-8729-4841-bd76-94bafef9489c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38473
21089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.3847321089
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.424037279
Short name T363
Test name
Test status
Simulation time 40164246 ps
CPU time 0.75 seconds
Started Jul 31 05:44:19 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 206964 kb
Host smart-84f0174e-3c75-451d-83c5-10c3e26957b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
7279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.424037279
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.436524360
Short name T2803
Test name
Test status
Simulation time 870728069 ps
CPU time 2.33 seconds
Started Jul 31 05:44:19 PM PDT 24
Finished Jul 31 05:44:22 PM PDT 24
Peak memory 207116 kb
Host smart-2dfb0068-4de0-4ca9-9db9-a8b82dd1c689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43652
4360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.436524360
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.4172993490
Short name T846
Test name
Test status
Simulation time 208116925 ps
CPU time 1.6 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:44:19 PM PDT 24
Peak memory 207052 kb
Host smart-f3cbafbd-7c11-4779-ba1c-f3995b70732f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41729
93490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.4172993490
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.674058216
Short name T2266
Test name
Test status
Simulation time 211593702 ps
CPU time 1.24 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:44:19 PM PDT 24
Peak memory 215276 kb
Host smart-7dd220d9-d148-4222-8030-3941fb64f234
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=674058216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.674058216
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.3513107694
Short name T552
Test name
Test status
Simulation time 157613532 ps
CPU time 0.84 seconds
Started Jul 31 05:44:19 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 206960 kb
Host smart-c56989c9-2c50-4f37-8965-3535620a9905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35131
07694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3513107694
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3966101076
Short name T750
Test name
Test status
Simulation time 228384610 ps
CPU time 0.99 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:44:18 PM PDT 24
Peak memory 207000 kb
Host smart-85112e14-02a2-48ed-9ca9-48705604bd0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39661
01076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3966101076
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.4169913950
Short name T710
Test name
Test status
Simulation time 8452659128 ps
CPU time 89.5 seconds
Started Jul 31 05:44:27 PM PDT 24
Finished Jul 31 05:45:57 PM PDT 24
Peak memory 216724 kb
Host smart-fdb0e90b-c934-4f25-8917-d8b3a3e5efc8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4169913950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.4169913950
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3052512400
Short name T2358
Test name
Test status
Simulation time 230707936 ps
CPU time 1.01 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:44:18 PM PDT 24
Peak memory 207000 kb
Host smart-0c5eb383-ea34-4bf2-beb3-c6a8b12a1ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30525
12400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3052512400
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2395298962
Short name T1981
Test name
Test status
Simulation time 23354344090 ps
CPU time 31.93 seconds
Started Jul 31 05:44:19 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 207148 kb
Host smart-8cf9e6b4-d023-4c8a-b218-5c83ece74ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952
98962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2395298962
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3964180707
Short name T2578
Test name
Test status
Simulation time 3373988826 ps
CPU time 4.65 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:44:21 PM PDT 24
Peak memory 207140 kb
Host smart-8b59c0c6-352b-4e6c-8717-7f92a3deb215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39641
80707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3964180707
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.1469955513
Short name T1952
Test name
Test status
Simulation time 7893721256 ps
CPU time 226.4 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:48:03 PM PDT 24
Peak memory 215412 kb
Host smart-63e8cea9-e2bd-433a-9139-fae365a46703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14699
55513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1469955513
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.39063132
Short name T1576
Test name
Test status
Simulation time 5468673670 ps
CPU time 56.38 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:45:13 PM PDT 24
Peak memory 215396 kb
Host smart-b766a95c-5c9d-4796-aa75-8d6e2cda00f1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=39063132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.39063132
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.1487397573
Short name T1653
Test name
Test status
Simulation time 263326788 ps
CPU time 1.05 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:44:18 PM PDT 24
Peak memory 207004 kb
Host smart-1afda5c6-20a8-434d-8f37-89617085cdec
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1487397573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.1487397573
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3891721563
Short name T2859
Test name
Test status
Simulation time 198649121 ps
CPU time 0.94 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:44:18 PM PDT 24
Peak memory 206988 kb
Host smart-b7085a35-e98c-4002-b988-22154b5dcb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38917
21563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3891721563
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.4126481579
Short name T485
Test name
Test status
Simulation time 4381527183 ps
CPU time 127.25 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:46:23 PM PDT 24
Peak memory 215396 kb
Host smart-5a772dfb-3fc3-44ae-80b5-9dc0adb5b137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41264
81579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.4126481579
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3609311249
Short name T213
Test name
Test status
Simulation time 4840822093 ps
CPU time 137.22 seconds
Started Jul 31 05:44:20 PM PDT 24
Finished Jul 31 05:46:37 PM PDT 24
Peak memory 215416 kb
Host smart-03b7b064-5545-4fec-af11-d5a248858b7a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3609311249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3609311249
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1659481804
Short name T2706
Test name
Test status
Simulation time 156642936 ps
CPU time 0.88 seconds
Started Jul 31 05:44:20 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 207024 kb
Host smart-ec8fd702-be12-4739-84d0-be221e645add
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1659481804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1659481804
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.712718038
Short name T2592
Test name
Test status
Simulation time 159005299 ps
CPU time 0.9 seconds
Started Jul 31 05:44:19 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 207012 kb
Host smart-35321cb5-5304-4a61-923b-f4b97bb55616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71271
8038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.712718038
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.3054107534
Short name T130
Test name
Test status
Simulation time 252378411 ps
CPU time 0.98 seconds
Started Jul 31 05:44:19 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 206984 kb
Host smart-5cdbd3ab-cc10-4683-97b8-965d66f6b0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30541
07534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.3054107534
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2899834506
Short name T2146
Test name
Test status
Simulation time 200742820 ps
CPU time 0.91 seconds
Started Jul 31 05:44:20 PM PDT 24
Finished Jul 31 05:44:21 PM PDT 24
Peak memory 206964 kb
Host smart-50b56ba1-ed05-4058-afda-93a76148281a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28998
34506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2899834506
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.531646266
Short name T2176
Test name
Test status
Simulation time 149568256 ps
CPU time 0.84 seconds
Started Jul 31 05:44:18 PM PDT 24
Finished Jul 31 05:44:19 PM PDT 24
Peak memory 206988 kb
Host smart-02158ffb-1343-472e-8d99-79718ce0f9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53164
6266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.531646266
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.187343752
Short name T2024
Test name
Test status
Simulation time 205376239 ps
CPU time 0.88 seconds
Started Jul 31 05:44:18 PM PDT 24
Finished Jul 31 05:44:19 PM PDT 24
Peak memory 206972 kb
Host smart-f109e9ff-68e2-45b1-acc3-924afe177729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18734
3752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.187343752
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3376360894
Short name T1929
Test name
Test status
Simulation time 220112860 ps
CPU time 0.98 seconds
Started Jul 31 05:44:19 PM PDT 24
Finished Jul 31 05:44:20 PM PDT 24
Peak memory 206996 kb
Host smart-dae5a164-b0d9-4f33-91b8-2474188eae01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33763
60894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3376360894
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.4229288216
Short name T1100
Test name
Test status
Simulation time 199036516 ps
CPU time 0.94 seconds
Started Jul 31 05:44:17 PM PDT 24
Finished Jul 31 05:44:18 PM PDT 24
Peak memory 206972 kb
Host smart-0f9f6c1a-400d-42e2-85d0-4b1174388d34
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4229288216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.4229288216
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1265186691
Short name T611
Test name
Test status
Simulation time 149994236 ps
CPU time 0.8 seconds
Started Jul 31 05:44:27 PM PDT 24
Finished Jul 31 05:44:28 PM PDT 24
Peak memory 206968 kb
Host smart-68882872-43dc-4a18-afe0-63426af414af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12651
86691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1265186691
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.4172157846
Short name T1615
Test name
Test status
Simulation time 47542521 ps
CPU time 0.71 seconds
Started Jul 31 05:44:22 PM PDT 24
Finished Jul 31 05:44:23 PM PDT 24
Peak memory 206944 kb
Host smart-15db215b-be0d-48c0-80ee-8c36d070505d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41721
57846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.4172157846
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.4284967553
Short name T272
Test name
Test status
Simulation time 16687183647 ps
CPU time 38.97 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:44:55 PM PDT 24
Peak memory 215460 kb
Host smart-19b0413d-770e-4e39-843c-1d9361cf540f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42849
67553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.4284967553
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.4130287074
Short name T862
Test name
Test status
Simulation time 171583087 ps
CPU time 0.86 seconds
Started Jul 31 05:44:21 PM PDT 24
Finished Jul 31 05:44:22 PM PDT 24
Peak memory 206984 kb
Host smart-aaeffa23-1dd7-4342-bf7a-8c3619e7e539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41302
87074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.4130287074
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2031852402
Short name T2253
Test name
Test status
Simulation time 215246958 ps
CPU time 0.94 seconds
Started Jul 31 05:44:21 PM PDT 24
Finished Jul 31 05:44:22 PM PDT 24
Peak memory 206988 kb
Host smart-6156c8a6-c5b8-4b44-b128-5efa6b3bba32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20318
52402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2031852402
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2320742853
Short name T2854
Test name
Test status
Simulation time 177157612 ps
CPU time 0.93 seconds
Started Jul 31 05:44:16 PM PDT 24
Finished Jul 31 05:44:17 PM PDT 24
Peak memory 206992 kb
Host smart-c0669bff-6a22-43ce-b9b3-c465086e3811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23207
42853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2320742853
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1481434278
Short name T715
Test name
Test status
Simulation time 184287848 ps
CPU time 0.96 seconds
Started Jul 31 05:44:26 PM PDT 24
Finished Jul 31 05:44:27 PM PDT 24
Peak memory 206996 kb
Host smart-ed2c89bb-1388-4392-9755-ce5b83023b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814
34278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1481434278
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.51890812
Short name T2623
Test name
Test status
Simulation time 145616484 ps
CPU time 0.83 seconds
Started Jul 31 05:44:24 PM PDT 24
Finished Jul 31 05:44:25 PM PDT 24
Peak memory 206936 kb
Host smart-0b0ef562-631e-4517-b714-e650b1f08aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51890
812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.51890812
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.1150075864
Short name T2144
Test name
Test status
Simulation time 152193992 ps
CPU time 0.81 seconds
Started Jul 31 05:44:21 PM PDT 24
Finished Jul 31 05:44:22 PM PDT 24
Peak memory 206944 kb
Host smart-3e566b86-96fd-4e28-854b-fdfc1ea9f902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11500
75864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.1150075864
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.651991420
Short name T850
Test name
Test status
Simulation time 180240781 ps
CPU time 0.89 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:26 PM PDT 24
Peak memory 207048 kb
Host smart-ce4fa98f-62b8-4dc8-b86a-e8a6cb318364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65199
1420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.651991420
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1954183675
Short name T864
Test name
Test status
Simulation time 256425187 ps
CPU time 1.05 seconds
Started Jul 31 05:44:27 PM PDT 24
Finished Jul 31 05:44:28 PM PDT 24
Peak memory 206960 kb
Host smart-dd1e71d7-fc89-4dc2-b7d7-1cc5c450dde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19541
83675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1954183675
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.3652795272
Short name T349
Test name
Test status
Simulation time 5043578597 ps
CPU time 53.53 seconds
Started Jul 31 05:44:21 PM PDT 24
Finished Jul 31 05:45:15 PM PDT 24
Peak memory 216860 kb
Host smart-de15e907-d5da-4790-b2be-6bf53a8f92ac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3652795272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.3652795272
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.4159423632
Short name T1314
Test name
Test status
Simulation time 178972748 ps
CPU time 0.94 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:26 PM PDT 24
Peak memory 206968 kb
Host smart-07412292-8c8f-4075-9cf5-c42789780f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41594
23632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.4159423632
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3754384142
Short name T807
Test name
Test status
Simulation time 174199797 ps
CPU time 0.85 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:25 PM PDT 24
Peak memory 206972 kb
Host smart-e7cac297-3d75-4961-8bcc-78898d3c3ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37543
84142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3754384142
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.1092528280
Short name T2432
Test name
Test status
Simulation time 502991052 ps
CPU time 1.51 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:26 PM PDT 24
Peak memory 206960 kb
Host smart-17adbf33-9834-4de6-ba36-2f13412901b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10925
28280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1092528280
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.295153703
Short name T2789
Test name
Test status
Simulation time 5357594264 ps
CPU time 157.37 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 215396 kb
Host smart-11b0645f-fbda-4cbe-a35b-70f4ee4f9801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29515
3703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.295153703
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.3539352791
Short name T1405
Test name
Test status
Simulation time 1282043233 ps
CPU time 29.53 seconds
Started Jul 31 05:44:19 PM PDT 24
Finished Jul 31 05:44:48 PM PDT 24
Peak memory 207124 kb
Host smart-420821f2-b7a1-4508-9bb3-b0194956dcb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539352791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.3539352791
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.3331659550
Short name T2290
Test name
Test status
Simulation time 69776271 ps
CPU time 0.69 seconds
Started Jul 31 05:44:36 PM PDT 24
Finished Jul 31 05:44:37 PM PDT 24
Peak memory 207020 kb
Host smart-f5b1ba17-edb9-4a84-bfdc-9bc1d25cbf2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3331659550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.3331659550
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.844457390
Short name T818
Test name
Test status
Simulation time 4055470653 ps
CPU time 5.51 seconds
Started Jul 31 05:44:24 PM PDT 24
Finished Jul 31 05:44:29 PM PDT 24
Peak memory 207128 kb
Host smart-ce07518f-0071-48d3-a8a0-7816bbfd61ab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844457390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_ao
n_wake_disconnect.844457390
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3675258603
Short name T1715
Test name
Test status
Simulation time 13451659146 ps
CPU time 15.52 seconds
Started Jul 31 05:44:24 PM PDT 24
Finished Jul 31 05:44:39 PM PDT 24
Peak memory 207220 kb
Host smart-cc7bdb34-1ab4-4545-ad23-1112787dcebe
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675258603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3675258603
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.1344848972
Short name T2820
Test name
Test status
Simulation time 23348896820 ps
CPU time 34.28 seconds
Started Jul 31 05:44:26 PM PDT 24
Finished Jul 31 05:45:00 PM PDT 24
Peak memory 207228 kb
Host smart-1204b3cc-68f8-4d03-9676-b6999600a504
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344848972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.1344848972
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.1130748168
Short name T546
Test name
Test status
Simulation time 176914389 ps
CPU time 0.89 seconds
Started Jul 31 05:44:24 PM PDT 24
Finished Jul 31 05:44:25 PM PDT 24
Peak memory 207000 kb
Host smart-a1087c84-aeb1-47d0-97fc-f458f0ecc920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307
48168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1130748168
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.4213971165
Short name T801
Test name
Test status
Simulation time 143830911 ps
CPU time 0.84 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:26 PM PDT 24
Peak memory 206944 kb
Host smart-3cff3673-2d36-4c61-9968-aac612a07672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42139
71165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.4213971165
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3064827166
Short name T1744
Test name
Test status
Simulation time 165710225 ps
CPU time 0.87 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:26 PM PDT 24
Peak memory 206956 kb
Host smart-21f12429-632c-4632-800b-24e7d3e943e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30648
27166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3064827166
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.325510502
Short name T2634
Test name
Test status
Simulation time 381892093 ps
CPU time 1.35 seconds
Started Jul 31 05:44:24 PM PDT 24
Finished Jul 31 05:44:25 PM PDT 24
Peak memory 206980 kb
Host smart-f7a0c197-8874-46ac-830e-847288c0ee6f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=325510502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.325510502
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1087373689
Short name T1488
Test name
Test status
Simulation time 9705788576 ps
CPU time 20.2 seconds
Started Jul 31 05:44:27 PM PDT 24
Finished Jul 31 05:44:47 PM PDT 24
Peak memory 207208 kb
Host smart-3d8979ab-18a2-46c5-96a8-3b98335f92e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10873
73689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1087373689
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_device_timeout.636446122
Short name T1088
Test name
Test status
Simulation time 2023459512 ps
CPU time 16.9 seconds
Started Jul 31 05:44:26 PM PDT 24
Finished Jul 31 05:44:43 PM PDT 24
Peak memory 207132 kb
Host smart-e0809249-95c2-472d-b8fe-0cfb56232239
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636446122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.636446122
Directory /workspace/29.usbdev_device_timeout/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.4238847922
Short name T2375
Test name
Test status
Simulation time 413610857 ps
CPU time 1.42 seconds
Started Jul 31 05:44:22 PM PDT 24
Finished Jul 31 05:44:23 PM PDT 24
Peak memory 206968 kb
Host smart-93843c3f-a434-4d31-97de-33e334c8d2c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42388
47922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.4238847922
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.2962697815
Short name T1538
Test name
Test status
Simulation time 141748630 ps
CPU time 0.89 seconds
Started Jul 31 05:44:23 PM PDT 24
Finished Jul 31 05:44:24 PM PDT 24
Peak memory 206976 kb
Host smart-679df897-50f2-449c-acb4-0833b4e960a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29626
97815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2962697815
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.3487759306
Short name T904
Test name
Test status
Simulation time 67278363 ps
CPU time 0.74 seconds
Started Jul 31 05:44:24 PM PDT 24
Finished Jul 31 05:44:25 PM PDT 24
Peak memory 206996 kb
Host smart-fef325cc-738d-4448-adee-aa5e78bf733b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34877
59306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.3487759306
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.2972151726
Short name T2701
Test name
Test status
Simulation time 975185062 ps
CPU time 2.54 seconds
Started Jul 31 05:44:23 PM PDT 24
Finished Jul 31 05:44:26 PM PDT 24
Peak memory 207060 kb
Host smart-e96d8dfa-7ff1-40d3-ae5e-f057ebf634ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29721
51726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2972151726
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.92277916
Short name T2482
Test name
Test status
Simulation time 281856875 ps
CPU time 2.25 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:27 PM PDT 24
Peak memory 207040 kb
Host smart-e45d0cf5-0c0b-4bfc-b786-b5c6f71763ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92277
916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.92277916
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.4063790084
Short name T2677
Test name
Test status
Simulation time 231841852 ps
CPU time 1.13 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:26 PM PDT 24
Peak memory 207080 kb
Host smart-d4e8681b-4c64-4f65-b19b-4d06418dfcc3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4063790084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.4063790084
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.744248102
Short name T804
Test name
Test status
Simulation time 151464946 ps
CPU time 0.81 seconds
Started Jul 31 05:44:23 PM PDT 24
Finished Jul 31 05:44:24 PM PDT 24
Peak memory 206964 kb
Host smart-8dc4cd59-2483-4664-bd56-1ec6a80705e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74424
8102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.744248102
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.2083085483
Short name T2380
Test name
Test status
Simulation time 279411856 ps
CPU time 1.16 seconds
Started Jul 31 05:44:22 PM PDT 24
Finished Jul 31 05:44:23 PM PDT 24
Peak memory 206988 kb
Host smart-a8a1c432-4a79-4e29-9bcc-00328e872fa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20830
85483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.2083085483
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.2288206311
Short name T2647
Test name
Test status
Simulation time 5846775916 ps
CPU time 169.76 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 215392 kb
Host smart-a507bf3a-8426-4034-9ed3-bd45b4fe4fbb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2288206311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2288206311
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.66216151
Short name T626
Test name
Test status
Simulation time 11995246715 ps
CPU time 76.03 seconds
Started Jul 31 05:44:23 PM PDT 24
Finished Jul 31 05:45:40 PM PDT 24
Peak memory 207192 kb
Host smart-daa97ed9-a279-4f2e-8a4e-3aa206a6f3f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=66216151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.66216151
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1880815588
Short name T2659
Test name
Test status
Simulation time 237674637 ps
CPU time 1.04 seconds
Started Jul 31 05:44:26 PM PDT 24
Finished Jul 31 05:44:27 PM PDT 24
Peak memory 206972 kb
Host smart-81014bd9-ae5a-449f-a108-72dcd7370acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18808
15588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1880815588
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3340183041
Short name T509
Test name
Test status
Simulation time 23305599269 ps
CPU time 27.61 seconds
Started Jul 31 05:44:23 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 207188 kb
Host smart-b167330a-f02d-42d9-be16-295b0fd382b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33401
83041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3340183041
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.2652635972
Short name T1943
Test name
Test status
Simulation time 3335763569 ps
CPU time 4.9 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 207092 kb
Host smart-c81393b3-48c9-4fdb-94e2-4c97a4221a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26526
35972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.2652635972
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.600893441
Short name T716
Test name
Test status
Simulation time 5403424145 ps
CPU time 41.14 seconds
Started Jul 31 05:44:28 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 217532 kb
Host smart-b74ad6ca-998b-4e19-9704-7c125ed159f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60089
3441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.600893441
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2133429110
Short name T2511
Test name
Test status
Simulation time 6145685876 ps
CPU time 61.18 seconds
Started Jul 31 05:44:29 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 207228 kb
Host smart-6c4c4444-f745-4570-b9de-3f9c12642def
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2133429110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2133429110
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1590003868
Short name T1511
Test name
Test status
Simulation time 232903342 ps
CPU time 1.07 seconds
Started Jul 31 05:44:28 PM PDT 24
Finished Jul 31 05:44:29 PM PDT 24
Peak memory 207004 kb
Host smart-1e58ce7d-0737-4970-a6fc-142256054550
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1590003868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1590003868
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1765509421
Short name T2753
Test name
Test status
Simulation time 224504402 ps
CPU time 0.94 seconds
Started Jul 31 05:44:31 PM PDT 24
Finished Jul 31 05:44:32 PM PDT 24
Peak memory 206976 kb
Host smart-3a388811-04e7-4dfe-8a19-c76f335ea6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17655
09421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1765509421
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.2761049302
Short name T940
Test name
Test status
Simulation time 4635565718 ps
CPU time 37.45 seconds
Started Jul 31 05:44:29 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 216704 kb
Host smart-311af225-fa0d-40aa-9014-c9a19ebee2a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27610
49302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.2761049302
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.2338273437
Short name T2258
Test name
Test status
Simulation time 7248689554 ps
CPU time 213.75 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:48:04 PM PDT 24
Peak memory 215360 kb
Host smart-4c09cf83-89d6-473e-8213-406d9e75df2e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2338273437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.2338273437
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2607030332
Short name T455
Test name
Test status
Simulation time 169626476 ps
CPU time 0.91 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:31 PM PDT 24
Peak memory 207008 kb
Host smart-95354418-c0cc-4692-b388-44dc9bd42522
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2607030332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2607030332
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.2461612273
Short name T2822
Test name
Test status
Simulation time 148663718 ps
CPU time 0.86 seconds
Started Jul 31 05:44:28 PM PDT 24
Finished Jul 31 05:44:29 PM PDT 24
Peak memory 206980 kb
Host smart-a3d164d7-30a0-414c-a060-fad20d03da63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24616
12273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.2461612273
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.3349999439
Short name T2441
Test name
Test status
Simulation time 167621192 ps
CPU time 0.88 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:31 PM PDT 24
Peak memory 207000 kb
Host smart-eda92630-fdda-492f-b36b-449cdd61b7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33499
99439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.3349999439
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.3574337604
Short name T923
Test name
Test status
Simulation time 168384215 ps
CPU time 0.87 seconds
Started Jul 31 05:44:26 PM PDT 24
Finished Jul 31 05:44:27 PM PDT 24
Peak memory 206984 kb
Host smart-b5846e65-c120-40f2-a257-301e0dd5e49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35743
37604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3574337604
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3953745940
Short name T1424
Test name
Test status
Simulation time 160771461 ps
CPU time 0.82 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:31 PM PDT 24
Peak memory 207000 kb
Host smart-5d0994df-5fe7-4d74-b7d9-b142f8e534ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
45940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3953745940
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3159945321
Short name T1617
Test name
Test status
Simulation time 191565829 ps
CPU time 1.01 seconds
Started Jul 31 05:44:35 PM PDT 24
Finished Jul 31 05:44:36 PM PDT 24
Peak memory 206996 kb
Host smart-bab5f4e6-f685-4765-ba05-fa002c51f5bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31599
45321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3159945321
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.968163150
Short name T2437
Test name
Test status
Simulation time 159097877 ps
CPU time 1.01 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:31 PM PDT 24
Peak memory 206984 kb
Host smart-5d132eb3-547f-463d-9dfa-91c4adada0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96816
3150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.968163150
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.2146406749
Short name T1922
Test name
Test status
Simulation time 239000838 ps
CPU time 1.07 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:32 PM PDT 24
Peak memory 207016 kb
Host smart-0df18e28-ca25-4fb7-97a2-1a98b92bf920
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2146406749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2146406749
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2098721571
Short name T527
Test name
Test status
Simulation time 147170100 ps
CPU time 0.88 seconds
Started Jul 31 05:44:34 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 206952 kb
Host smart-118cc967-5db0-40b2-9b19-0279deb7c53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20987
21571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2098721571
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3746710423
Short name T1107
Test name
Test status
Simulation time 32219778 ps
CPU time 0.69 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:30 PM PDT 24
Peak memory 206960 kb
Host smart-8ca3f3ea-c6bb-40fa-9664-229c36e4090a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37467
10423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3746710423
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1773008510
Short name T274
Test name
Test status
Simulation time 8354784031 ps
CPU time 20.77 seconds
Started Jul 31 05:44:32 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 223584 kb
Host smart-1d00b13c-b48a-4dbb-ba70-304caefa5ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17730
08510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1773008510
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.922717723
Short name T2122
Test name
Test status
Simulation time 174787879 ps
CPU time 0.93 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:26 PM PDT 24
Peak memory 207004 kb
Host smart-ae2658a9-4274-4c1b-9153-c040a86ab8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92271
7723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.922717723
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.1475932892
Short name T1128
Test name
Test status
Simulation time 160951211 ps
CPU time 0.86 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:31 PM PDT 24
Peak memory 206924 kb
Host smart-f1a6be73-dbae-4b27-ad87-a75f8b23cbce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14759
32892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.1475932892
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.1711019222
Short name T2458
Test name
Test status
Simulation time 179672427 ps
CPU time 0.95 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:32 PM PDT 24
Peak memory 206992 kb
Host smart-cb1e6487-d504-47b4-baf6-a69a94cd2f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17110
19222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.1711019222
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3724234015
Short name T857
Test name
Test status
Simulation time 183505187 ps
CPU time 0.92 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:31 PM PDT 24
Peak memory 206964 kb
Host smart-ca608b6e-602e-4fad-bf1d-fdad28d4a105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37242
34015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3724234015
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3892156621
Short name T714
Test name
Test status
Simulation time 187478294 ps
CPU time 0.89 seconds
Started Jul 31 05:44:30 PM PDT 24
Finished Jul 31 05:44:31 PM PDT 24
Peak memory 206948 kb
Host smart-35cc939e-714d-4826-b2a9-d9ba60024afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38921
56621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3892156621
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.1990257325
Short name T565
Test name
Test status
Simulation time 176132973 ps
CPU time 0.83 seconds
Started Jul 31 05:44:27 PM PDT 24
Finished Jul 31 05:44:28 PM PDT 24
Peak memory 206948 kb
Host smart-4200a7c6-01a3-4191-9baa-8ebebf9bf78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19902
57325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.1990257325
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2183556654
Short name T2561
Test name
Test status
Simulation time 154668601 ps
CPU time 0.89 seconds
Started Jul 31 05:44:28 PM PDT 24
Finished Jul 31 05:44:29 PM PDT 24
Peak memory 207004 kb
Host smart-52c1d4a1-889b-4c02-8545-6054a7452b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21835
56654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2183556654
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.3819803058
Short name T1684
Test name
Test status
Simulation time 239620940 ps
CPU time 1.07 seconds
Started Jul 31 05:44:26 PM PDT 24
Finished Jul 31 05:44:27 PM PDT 24
Peak memory 206988 kb
Host smart-5c674b1a-3bac-4ca4-9346-0a9d94dd1125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38198
03058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.3819803058
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.1168896560
Short name T2707
Test name
Test status
Simulation time 3770449341 ps
CPU time 107.43 seconds
Started Jul 31 05:44:28 PM PDT 24
Finished Jul 31 05:46:16 PM PDT 24
Peak memory 215388 kb
Host smart-a15ae9b0-412c-4f4e-bae8-aeaac2bd1632
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1168896560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.1168896560
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3131651871
Short name T1163
Test name
Test status
Simulation time 170369644 ps
CPU time 0.82 seconds
Started Jul 31 05:44:29 PM PDT 24
Finished Jul 31 05:44:30 PM PDT 24
Peak memory 206980 kb
Host smart-a4a3b517-7e21-4bb7-8976-6e849762a79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31316
51871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3131651871
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1501110670
Short name T2399
Test name
Test status
Simulation time 184669376 ps
CPU time 0.9 seconds
Started Jul 31 05:44:34 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 206992 kb
Host smart-cae7155a-9045-4bb4-8cba-7d5e4388b203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15011
10670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1501110670
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.3730130135
Short name T1484
Test name
Test status
Simulation time 527101841 ps
CPU time 1.69 seconds
Started Jul 31 05:44:34 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 206988 kb
Host smart-9f6c2bb7-ef6d-4a4c-8582-4632e9f60d6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37301
30135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.3730130135
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.541561209
Short name T746
Test name
Test status
Simulation time 3851174605 ps
CPU time 108.19 seconds
Started Jul 31 05:44:36 PM PDT 24
Finished Jul 31 05:46:24 PM PDT 24
Peak memory 215420 kb
Host smart-32e61092-b969-4b90-90d9-f800113ef360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54156
1209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.541561209
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.4113244391
Short name T2340
Test name
Test status
Simulation time 1071514096 ps
CPU time 9.31 seconds
Started Jul 31 05:44:25 PM PDT 24
Finished Jul 31 05:44:34 PM PDT 24
Peak memory 207044 kb
Host smart-5d6dc22f-a391-494c-b088-e72604b3671f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113244391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.4113244391
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2038504734
Short name T488
Test name
Test status
Simulation time 45517328 ps
CPU time 0.65 seconds
Started Jul 31 05:40:04 PM PDT 24
Finished Jul 31 05:40:05 PM PDT 24
Peak memory 207032 kb
Host smart-63689d11-2ce8-4f07-89bd-165c7aa8c626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2038504734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2038504734
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2915483890
Short name T879
Test name
Test status
Simulation time 4429024070 ps
CPU time 6.21 seconds
Started Jul 31 05:39:46 PM PDT 24
Finished Jul 31 05:39:52 PM PDT 24
Peak memory 207144 kb
Host smart-df26e58c-8195-4ea5-b292-d03a26714078
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915483890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.2915483890
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1915119799
Short name T1461
Test name
Test status
Simulation time 13370195710 ps
CPU time 15.51 seconds
Started Jul 31 05:39:48 PM PDT 24
Finished Jul 31 05:40:03 PM PDT 24
Peak memory 207228 kb
Host smart-4fcdb2c0-ee68-4456-abe3-61b1963fdd44
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915119799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1915119799
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3918953580
Short name T1790
Test name
Test status
Simulation time 23333045858 ps
CPU time 32.01 seconds
Started Jul 31 05:39:48 PM PDT 24
Finished Jul 31 05:40:20 PM PDT 24
Peak memory 207236 kb
Host smart-baf1e88e-3007-4b13-ba0a-91d0d144f2aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918953580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_resume.3918953580
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.3132166292
Short name T377
Test name
Test status
Simulation time 231566545 ps
CPU time 0.95 seconds
Started Jul 31 05:39:48 PM PDT 24
Finished Jul 31 05:39:49 PM PDT 24
Peak memory 206920 kb
Host smart-cb43f175-eb4d-4d35-add5-ab861af3be5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31321
66292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.3132166292
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.542166402
Short name T50
Test name
Test status
Simulation time 173138821 ps
CPU time 0.89 seconds
Started Jul 31 05:39:48 PM PDT 24
Finished Jul 31 05:39:49 PM PDT 24
Peak memory 207016 kb
Host smart-ecc2f41a-5322-46d6-8320-c060d0c13bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54216
6402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.542166402
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.274261177
Short name T55
Test name
Test status
Simulation time 181156394 ps
CPU time 0.86 seconds
Started Jul 31 05:39:46 PM PDT 24
Finished Jul 31 05:39:47 PM PDT 24
Peak memory 206888 kb
Host smart-ead11338-6b9c-401d-91f7-63ad0639ba49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27426
1177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.274261177
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3704108716
Short name T493
Test name
Test status
Simulation time 138853102 ps
CPU time 0.87 seconds
Started Jul 31 05:39:46 PM PDT 24
Finished Jul 31 05:39:47 PM PDT 24
Peak memory 206952 kb
Host smart-73cba5de-c8f1-46ff-a47b-a3fb8eb9bac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37041
08716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3704108716
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1151622713
Short name T1287
Test name
Test status
Simulation time 150912616 ps
CPU time 0.85 seconds
Started Jul 31 05:39:46 PM PDT 24
Finished Jul 31 05:39:47 PM PDT 24
Peak memory 206980 kb
Host smart-ef2332d8-0e1f-44c1-87d7-90bbba427517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11516
22713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1151622713
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2252734121
Short name T2113
Test name
Test status
Simulation time 7296545209 ps
CPU time 15.29 seconds
Started Jul 31 05:39:53 PM PDT 24
Finished Jul 31 05:40:08 PM PDT 24
Peak memory 207200 kb
Host smart-127cad09-6a13-4cfd-9912-3376075103c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
34121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2252734121
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_device_timeout.2374036502
Short name T2795
Test name
Test status
Simulation time 826136359 ps
CPU time 19.29 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:40:10 PM PDT 24
Peak memory 207036 kb
Host smart-def221e1-6442-4156-9fec-face1cc20368
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374036502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.2374036502
Directory /workspace/3.usbdev_device_timeout/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3203561250
Short name T1663
Test name
Test status
Simulation time 362666056 ps
CPU time 1.27 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:39:52 PM PDT 24
Peak memory 206948 kb
Host smart-192c956f-099c-4650-9721-2c5241431644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32035
61250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3203561250
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.604430621
Short name T1847
Test name
Test status
Simulation time 179919631 ps
CPU time 0.88 seconds
Started Jul 31 05:39:52 PM PDT 24
Finished Jul 31 05:39:53 PM PDT 24
Peak memory 206936 kb
Host smart-86ad25c6-e0b9-470b-82aa-cbf5d1a8ba31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60443
0621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.604430621
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1633135999
Short name T1716
Test name
Test status
Simulation time 59186368 ps
CPU time 0.72 seconds
Started Jul 31 05:39:51 PM PDT 24
Finished Jul 31 05:39:51 PM PDT 24
Peak memory 206964 kb
Host smart-41178ec0-02ed-40f7-b988-631dcd31d158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16331
35999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1633135999
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3070215562
Short name T650
Test name
Test status
Simulation time 860059444 ps
CPU time 2.41 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:39:53 PM PDT 24
Peak memory 207068 kb
Host smart-150e68e6-e8b2-478a-ab36-2c8705b566b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30702
15562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3070215562
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1628566142
Short name T1472
Test name
Test status
Simulation time 174167945 ps
CPU time 1.62 seconds
Started Jul 31 05:39:51 PM PDT 24
Finished Jul 31 05:39:52 PM PDT 24
Peak memory 207024 kb
Host smart-10578237-c975-42d7-ac9f-e1f1db09098e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16285
66142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1628566142
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3739274040
Short name T329
Test name
Test status
Simulation time 119199529652 ps
CPU time 188.55 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:42:59 PM PDT 24
Peak memory 207152 kb
Host smart-4ad0939b-fd18-466c-98fb-6d7ca81451c0
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3739274040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3739274040
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.854273173
Short name T1222
Test name
Test status
Simulation time 118057715798 ps
CPU time 185.48 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:42:56 PM PDT 24
Peak memory 207192 kb
Host smart-1b0dab83-d115-43b4-829f-37a42d0b4dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854273173 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.854273173
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.4145304774
Short name T327
Test name
Test status
Simulation time 118102669734 ps
CPU time 185.56 seconds
Started Jul 31 05:39:51 PM PDT 24
Finished Jul 31 05:42:57 PM PDT 24
Peak memory 207152 kb
Host smart-e5309824-2305-4e86-b730-c65f71ba0a1a
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4145304774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.4145304774
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.2209842312
Short name T992
Test name
Test status
Simulation time 83015506390 ps
CPU time 121.45 seconds
Started Jul 31 05:39:53 PM PDT 24
Finished Jul 31 05:41:55 PM PDT 24
Peak memory 207252 kb
Host smart-eed2b8e5-f043-4e22-ae53-b637ae471b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209842312 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.2209842312
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.3701274648
Short name T1335
Test name
Test status
Simulation time 120172046359 ps
CPU time 176.86 seconds
Started Jul 31 05:39:54 PM PDT 24
Finished Jul 31 05:42:51 PM PDT 24
Peak memory 207192 kb
Host smart-1abca91b-75ec-42fc-99be-2d576b30a64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37012
74648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.3701274648
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.2969460284
Short name T439
Test name
Test status
Simulation time 164231363 ps
CPU time 0.91 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:39:51 PM PDT 24
Peak memory 207020 kb
Host smart-a4f98ad2-2a04-4c0c-9814-7809195cfc26
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2969460284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.2969460284
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.421238359
Short name T511
Test name
Test status
Simulation time 142365205 ps
CPU time 0.76 seconds
Started Jul 31 05:39:51 PM PDT 24
Finished Jul 31 05:39:52 PM PDT 24
Peak memory 206992 kb
Host smart-c7961a86-0efc-41f1-8d1b-1de20e8e59f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42123
8359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.421238359
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3112539552
Short name T2832
Test name
Test status
Simulation time 167776211 ps
CPU time 1.01 seconds
Started Jul 31 05:39:52 PM PDT 24
Finished Jul 31 05:39:53 PM PDT 24
Peak memory 206996 kb
Host smart-53c48b46-6044-4ffe-8cfc-d133d0b40f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31125
39552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3112539552
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.309388209
Short name T668
Test name
Test status
Simulation time 9654440461 ps
CPU time 284.49 seconds
Started Jul 31 05:39:53 PM PDT 24
Finished Jul 31 05:44:37 PM PDT 24
Peak memory 215380 kb
Host smart-bc645904-93de-4fb1-ba07-9f8f71bb0d2f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=309388209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.309388209
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.2598148356
Short name T1489
Test name
Test status
Simulation time 7777553828 ps
CPU time 51.43 seconds
Started Jul 31 05:39:54 PM PDT 24
Finished Jul 31 05:40:45 PM PDT 24
Peak memory 207196 kb
Host smart-d5d35e2a-0da7-4617-b07c-7f2b90e6632f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2598148356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.2598148356
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.4101230852
Short name T2268
Test name
Test status
Simulation time 189476885 ps
CPU time 0.94 seconds
Started Jul 31 05:39:53 PM PDT 24
Finished Jul 31 05:39:54 PM PDT 24
Peak memory 206976 kb
Host smart-24b2b183-8c74-404a-b6ef-33eb5014333d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41012
30852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.4101230852
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.2108262138
Short name T2127
Test name
Test status
Simulation time 23319309355 ps
CPU time 35.56 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:40:25 PM PDT 24
Peak memory 207204 kb
Host smart-7aa1af67-4271-4da4-aa46-20baf61425e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21082
62138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.2108262138
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.1814190464
Short name T1206
Test name
Test status
Simulation time 3344363918 ps
CPU time 5.17 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:39:55 PM PDT 24
Peak memory 207128 kb
Host smart-db8c88ca-7f9d-4ba4-a513-e83b2909b860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18141
90464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.1814190464
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2163261768
Short name T1249
Test name
Test status
Simulation time 3589735147 ps
CPU time 115.29 seconds
Started Jul 31 05:39:50 PM PDT 24
Finished Jul 31 05:41:45 PM PDT 24
Peak memory 215440 kb
Host smart-68f13fb3-76ae-4f84-9cc1-a2a4aa271ddc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2163261768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2163261768
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.3775546133
Short name T944
Test name
Test status
Simulation time 236171106 ps
CPU time 1.02 seconds
Started Jul 31 05:39:48 PM PDT 24
Finished Jul 31 05:39:49 PM PDT 24
Peak memory 206996 kb
Host smart-7b9e9387-ab8c-4494-a9e9-d281b9f98094
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3775546133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.3775546133
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.4276192144
Short name T653
Test name
Test status
Simulation time 229301885 ps
CPU time 0.93 seconds
Started Jul 31 05:39:53 PM PDT 24
Finished Jul 31 05:39:54 PM PDT 24
Peak memory 207024 kb
Host smart-edd00e3a-ff73-479a-97ff-5441712e5ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42761
92144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.4276192144
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.732307895
Short name T315
Test name
Test status
Simulation time 6164971575 ps
CPU time 62.81 seconds
Started Jul 31 05:39:52 PM PDT 24
Finished Jul 31 05:40:55 PM PDT 24
Peak memory 215388 kb
Host smart-5c612060-1ec4-4895-b40c-cb7cdd5f2a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73230
7895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.732307895
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.1103989457
Short name T1579
Test name
Test status
Simulation time 4573451081 ps
CPU time 127.82 seconds
Started Jul 31 05:39:52 PM PDT 24
Finished Jul 31 05:42:00 PM PDT 24
Peak memory 215372 kb
Host smart-6ac6ae10-44aa-43a9-9f7b-c4854a84722c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1103989457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.1103989457
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.2930435582
Short name T1378
Test name
Test status
Simulation time 212364405 ps
CPU time 0.97 seconds
Started Jul 31 05:39:52 PM PDT 24
Finished Jul 31 05:39:53 PM PDT 24
Peak memory 206968 kb
Host smart-4a02ecfd-974e-4959-92db-c4cc4cead168
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2930435582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.2930435582
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.4286323382
Short name T2632
Test name
Test status
Simulation time 154936254 ps
CPU time 0.9 seconds
Started Jul 31 05:39:52 PM PDT 24
Finished Jul 31 05:39:53 PM PDT 24
Peak memory 207036 kb
Host smart-b106b53a-ea36-43f5-933b-46bbcedd7df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42863
23382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.4286323382
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3241171831
Short name T123
Test name
Test status
Simulation time 201393687 ps
CPU time 0.99 seconds
Started Jul 31 05:39:55 PM PDT 24
Finished Jul 31 05:39:56 PM PDT 24
Peak memory 206996 kb
Host smart-400c6a73-f134-4a63-a5d2-95be69d72de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32411
71831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3241171831
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2077257961
Short name T888
Test name
Test status
Simulation time 199251568 ps
CPU time 0.95 seconds
Started Jul 31 05:39:53 PM PDT 24
Finished Jul 31 05:39:54 PM PDT 24
Peak memory 206968 kb
Host smart-c8563343-8e35-4559-8b86-3cd6649435a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20772
57961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2077257961
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3841241270
Short name T60
Test name
Test status
Simulation time 146133076 ps
CPU time 0.82 seconds
Started Jul 31 05:39:49 PM PDT 24
Finished Jul 31 05:39:50 PM PDT 24
Peak memory 207020 kb
Host smart-1023b707-918e-426e-9192-daa66c24c0f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38412
41270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3841241270
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3908163330
Short name T741
Test name
Test status
Simulation time 195354137 ps
CPU time 1.06 seconds
Started Jul 31 05:39:54 PM PDT 24
Finished Jul 31 05:39:55 PM PDT 24
Peak memory 206964 kb
Host smart-5c16fff6-6c31-400d-a244-63c49abe372b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39081
63330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3908163330
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.971118724
Short name T729
Test name
Test status
Simulation time 175172340 ps
CPU time 0.92 seconds
Started Jul 31 05:39:48 PM PDT 24
Finished Jul 31 05:39:50 PM PDT 24
Peak memory 206984 kb
Host smart-d065208f-b9ce-450e-8648-f29990bbafd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97111
8724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.971118724
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.2941749230
Short name T1036
Test name
Test status
Simulation time 257966044 ps
CPU time 1.1 seconds
Started Jul 31 05:39:58 PM PDT 24
Finished Jul 31 05:39:59 PM PDT 24
Peak memory 207028 kb
Host smart-a72e6fed-2579-4547-a508-aa01c81b6d93
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2941749230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.2941749230
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3736895718
Short name T1467
Test name
Test status
Simulation time 193147525 ps
CPU time 0.92 seconds
Started Jul 31 05:39:55 PM PDT 24
Finished Jul 31 05:39:56 PM PDT 24
Peak memory 206984 kb
Host smart-5a250e4b-19dc-495b-9d81-1e000a36fb99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37368
95718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3736895718
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1944200256
Short name T1604
Test name
Test status
Simulation time 160295746 ps
CPU time 0.83 seconds
Started Jul 31 05:39:57 PM PDT 24
Finished Jul 31 05:39:58 PM PDT 24
Peak memory 206976 kb
Host smart-2d5c28aa-fe6d-4e49-a2da-53d915c03053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19442
00256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1944200256
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.2266520850
Short name T2618
Test name
Test status
Simulation time 91870134 ps
CPU time 0.75 seconds
Started Jul 31 05:39:59 PM PDT 24
Finished Jul 31 05:40:00 PM PDT 24
Peak memory 207008 kb
Host smart-0441f64c-16c4-4f1f-ab0d-d93bd9b01be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665
20850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.2266520850
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.2945731765
Short name T247
Test name
Test status
Simulation time 16489768421 ps
CPU time 40.04 seconds
Started Jul 31 05:39:56 PM PDT 24
Finished Jul 31 05:40:36 PM PDT 24
Peak memory 215400 kb
Host smart-82a3c32f-324d-4221-b742-5417a9174bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29457
31765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.2945731765
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.2529278424
Short name T1800
Test name
Test status
Simulation time 208938015 ps
CPU time 0.98 seconds
Started Jul 31 05:39:59 PM PDT 24
Finished Jul 31 05:40:00 PM PDT 24
Peak memory 207000 kb
Host smart-52a462c6-7ceb-49b8-9070-7d4509e5989a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25292
78424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.2529278424
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.607251283
Short name T1419
Test name
Test status
Simulation time 220114780 ps
CPU time 0.94 seconds
Started Jul 31 05:39:57 PM PDT 24
Finished Jul 31 05:39:58 PM PDT 24
Peak memory 206972 kb
Host smart-70dd32ab-89d0-4f73-a3fe-32fd8ad94e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60725
1283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.607251283
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.585755555
Short name T1822
Test name
Test status
Simulation time 10103367576 ps
CPU time 69.22 seconds
Started Jul 31 05:39:56 PM PDT 24
Finished Jul 31 05:41:05 PM PDT 24
Peak memory 223556 kb
Host smart-af3cbf14-eedc-497d-aa5d-d8292a57181f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=585755555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.585755555
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.4037191496
Short name T2554
Test name
Test status
Simulation time 12485016834 ps
CPU time 270.83 seconds
Started Jul 31 05:39:58 PM PDT 24
Finished Jul 31 05:44:29 PM PDT 24
Peak memory 215444 kb
Host smart-ef3c38a7-aeea-4fce-a444-9721ef250d56
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037191496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.4037191496
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1753774949
Short name T2438
Test name
Test status
Simulation time 206927038 ps
CPU time 0.97 seconds
Started Jul 31 05:39:55 PM PDT 24
Finished Jul 31 05:39:56 PM PDT 24
Peak memory 206976 kb
Host smart-c9f51249-d568-43c1-af8b-fb35e6048006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17537
74949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1753774949
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2427333829
Short name T669
Test name
Test status
Simulation time 182927300 ps
CPU time 0.87 seconds
Started Jul 31 05:39:58 PM PDT 24
Finished Jul 31 05:39:59 PM PDT 24
Peak memory 206980 kb
Host smart-446eb81c-77f0-4c8a-ae5a-b17829a3bf8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24273
33829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2427333829
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3277228380
Short name T1970
Test name
Test status
Simulation time 177198064 ps
CPU time 0.84 seconds
Started Jul 31 05:40:00 PM PDT 24
Finished Jul 31 05:40:01 PM PDT 24
Peak memory 207000 kb
Host smart-96f7a7df-7a5c-479e-8eb1-8fc0f953406c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32772
28380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3277228380
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2310797217
Short name T29
Test name
Test status
Simulation time 183541146 ps
CPU time 0.9 seconds
Started Jul 31 05:39:58 PM PDT 24
Finished Jul 31 05:39:59 PM PDT 24
Peak memory 207036 kb
Host smart-5f8abd17-efeb-41cf-aaa4-e8bc60fd75e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23107
97217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2310797217
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3246885040
Short name T184
Test name
Test status
Simulation time 1128473764 ps
CPU time 1.91 seconds
Started Jul 31 05:40:03 PM PDT 24
Finished Jul 31 05:40:05 PM PDT 24
Peak memory 224076 kb
Host smart-d395aa37-3712-4af0-b09a-c749c5691c72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3246885040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3246885040
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3248869822
Short name T41
Test name
Test status
Simulation time 428210466 ps
CPU time 1.57 seconds
Started Jul 31 05:39:57 PM PDT 24
Finished Jul 31 05:39:58 PM PDT 24
Peak memory 206976 kb
Host smart-42eb33fc-c5b6-4540-96df-e271f4f02bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32488
69822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3248869822
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1496981106
Short name T2038
Test name
Test status
Simulation time 209095708 ps
CPU time 0.98 seconds
Started Jul 31 05:39:56 PM PDT 24
Finished Jul 31 05:39:57 PM PDT 24
Peak memory 206996 kb
Host smart-4c92493b-8359-4872-b2b8-976140089a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
81106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1496981106
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.4207060143
Short name T1534
Test name
Test status
Simulation time 167854086 ps
CPU time 0.85 seconds
Started Jul 31 05:39:56 PM PDT 24
Finished Jul 31 05:39:57 PM PDT 24
Peak memory 206952 kb
Host smart-01165931-1334-4128-9293-9ab09475caee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42070
60143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.4207060143
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2610670449
Short name T100
Test name
Test status
Simulation time 155561454 ps
CPU time 0.88 seconds
Started Jul 31 05:39:58 PM PDT 24
Finished Jul 31 05:39:59 PM PDT 24
Peak memory 207008 kb
Host smart-f4c97d5a-2f52-4907-bdef-305b99eafe1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26106
70449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2610670449
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2777055745
Short name T2269
Test name
Test status
Simulation time 248519326 ps
CPU time 1.02 seconds
Started Jul 31 05:39:59 PM PDT 24
Finished Jul 31 05:40:00 PM PDT 24
Peak memory 206996 kb
Host smart-d695b57d-6008-42a4-a23d-8a17867f3671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27770
55745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2777055745
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.1367730999
Short name T1699
Test name
Test status
Simulation time 5867597513 ps
CPU time 172.09 seconds
Started Jul 31 05:39:58 PM PDT 24
Finished Jul 31 05:42:50 PM PDT 24
Peak memory 215428 kb
Host smart-a198e901-b7bd-4091-aeed-8f44f1ce7c76
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1367730999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.1367730999
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.490186832
Short name T1611
Test name
Test status
Simulation time 165286480 ps
CPU time 0.88 seconds
Started Jul 31 05:39:58 PM PDT 24
Finished Jul 31 05:39:59 PM PDT 24
Peak memory 206980 kb
Host smart-35dd285a-7a3d-4d44-9b19-1512c7216662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49018
6832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.490186832
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.3479320503
Short name T1399
Test name
Test status
Simulation time 228522955 ps
CPU time 0.92 seconds
Started Jul 31 05:39:58 PM PDT 24
Finished Jul 31 05:39:59 PM PDT 24
Peak memory 207000 kb
Host smart-bd2123d2-5adb-4842-bfc8-86314463b63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34793
20503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.3479320503
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.2692844041
Short name T484
Test name
Test status
Simulation time 1018105638 ps
CPU time 2.35 seconds
Started Jul 31 05:39:56 PM PDT 24
Finished Jul 31 05:39:59 PM PDT 24
Peak memory 207076 kb
Host smart-ac69dd4d-35be-4a19-a0d0-7da41d95f2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26928
44041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2692844041
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.3525923879
Short name T528
Test name
Test status
Simulation time 3653101561 ps
CPU time 110.73 seconds
Started Jul 31 05:39:57 PM PDT 24
Finished Jul 31 05:41:48 PM PDT 24
Peak memory 215388 kb
Host smart-625188dd-3486-4ef2-9372-5cca2b782a96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35259
23879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.3525923879
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.133932792
Short name T2328
Test name
Test status
Simulation time 6377538487 ps
CPU time 40.92 seconds
Started Jul 31 05:39:52 PM PDT 24
Finished Jul 31 05:40:33 PM PDT 24
Peak memory 207256 kb
Host smart-b4d607d4-e3d0-4f4d-b79b-e536c684fe3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133932792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host_
handshake.133932792
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2236697438
Short name T1867
Test name
Test status
Simulation time 65691509 ps
CPU time 0.7 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:44:50 PM PDT 24
Peak memory 207004 kb
Host smart-53f72639-d332-4829-8a48-6688f718c0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2236697438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2236697438
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3855406319
Short name T1120
Test name
Test status
Simulation time 3872188240 ps
CPU time 5.61 seconds
Started Jul 31 05:44:33 PM PDT 24
Finished Jul 31 05:44:39 PM PDT 24
Peak memory 207156 kb
Host smart-b3c0f1b6-093f-45a1-9e97-5567ea54cf24
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855406319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.3855406319
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.2401436631
Short name T13
Test name
Test status
Simulation time 13393178335 ps
CPU time 16.41 seconds
Started Jul 31 05:44:35 PM PDT 24
Finished Jul 31 05:44:52 PM PDT 24
Peak memory 207224 kb
Host smart-fffc080c-4659-45a8-abd5-a5e3fd54bcaa
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401436631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.2401436631
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.2878858305
Short name T887
Test name
Test status
Simulation time 23461663082 ps
CPU time 29.02 seconds
Started Jul 31 05:44:35 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 207216 kb
Host smart-4945ad9b-1881-4009-858e-6de71fe5c0f9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878858305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_resume.2878858305
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1449105268
Short name T2582
Test name
Test status
Simulation time 200116250 ps
CPU time 0.94 seconds
Started Jul 31 05:44:38 PM PDT 24
Finished Jul 31 05:44:39 PM PDT 24
Peak memory 206976 kb
Host smart-635669f4-a271-4ed0-a690-0caee7dcd467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14491
05268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1449105268
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.384523743
Short name T1961
Test name
Test status
Simulation time 150311819 ps
CPU time 0.85 seconds
Started Jul 31 05:44:31 PM PDT 24
Finished Jul 31 05:44:32 PM PDT 24
Peak memory 206960 kb
Host smart-371e60bd-062d-4984-bfb0-1622951528b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38452
3743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.384523743
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.446464043
Short name T405
Test name
Test status
Simulation time 552489962 ps
CPU time 1.73 seconds
Started Jul 31 05:44:34 PM PDT 24
Finished Jul 31 05:44:37 PM PDT 24
Peak memory 207008 kb
Host smart-337a0bd3-4632-437d-a540-c460582effe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44646
4043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.446464043
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2689330420
Short name T2474
Test name
Test status
Simulation time 373267971 ps
CPU time 1.33 seconds
Started Jul 31 05:44:38 PM PDT 24
Finished Jul 31 05:44:39 PM PDT 24
Peak memory 207000 kb
Host smart-aa9a448c-e81d-49eb-a9fd-c3bd75eb12eb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2689330420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2689330420
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_timeout.3390097149
Short name T2818
Test name
Test status
Simulation time 3439577392 ps
CPU time 30.55 seconds
Started Jul 31 05:44:36 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 207192 kb
Host smart-4f701a7e-4a8d-44cb-ac6c-50bd0770f759
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390097149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.3390097149
Directory /workspace/30.usbdev_device_timeout/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.2188453800
Short name T323
Test name
Test status
Simulation time 414035569 ps
CPU time 1.38 seconds
Started Jul 31 05:44:34 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 206960 kb
Host smart-339224c1-87eb-432c-9d57-b3f186d02825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21884
53800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.2188453800
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.923240634
Short name T1782
Test name
Test status
Simulation time 151876308 ps
CPU time 0.96 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:44:42 PM PDT 24
Peak memory 206296 kb
Host smart-bc172a7c-251d-46c5-a27f-889da7a700fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92324
0634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.923240634
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.738072806
Short name T676
Test name
Test status
Simulation time 30804591 ps
CPU time 0.71 seconds
Started Jul 31 05:44:37 PM PDT 24
Finished Jul 31 05:44:38 PM PDT 24
Peak memory 206964 kb
Host smart-518dcb95-b765-4865-820d-87348744c4a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73807
2806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.738072806
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1943692866
Short name T1060
Test name
Test status
Simulation time 807261429 ps
CPU time 2.33 seconds
Started Jul 31 05:44:33 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 207096 kb
Host smart-d7ce8519-5757-4a85-931a-db56b5b329eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19436
92866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1943692866
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1664708484
Short name T1289
Test name
Test status
Simulation time 313027807 ps
CPU time 2.16 seconds
Started Jul 31 05:44:37 PM PDT 24
Finished Jul 31 05:44:39 PM PDT 24
Peak memory 207088 kb
Host smart-b405e674-4389-49c6-9d62-fc6ee2a1708b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16647
08484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1664708484
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.4210887487
Short name T200
Test name
Test status
Simulation time 175966897 ps
CPU time 0.92 seconds
Started Jul 31 05:44:37 PM PDT 24
Finished Jul 31 05:44:38 PM PDT 24
Peak memory 207004 kb
Host smart-35a72c2e-10c0-4d4e-b056-85ef1c746d25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4210887487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.4210887487
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1890035138
Short name T894
Test name
Test status
Simulation time 157645676 ps
CPU time 0.85 seconds
Started Jul 31 05:44:38 PM PDT 24
Finished Jul 31 05:44:39 PM PDT 24
Peak memory 206968 kb
Host smart-3ce69bad-ce79-4841-95d4-38b97d160d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18900
35138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1890035138
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.4076413592
Short name T734
Test name
Test status
Simulation time 184250491 ps
CPU time 0.92 seconds
Started Jul 31 05:44:39 PM PDT 24
Finished Jul 31 05:44:40 PM PDT 24
Peak memory 206992 kb
Host smart-56f5fe1f-7400-45bd-a04c-05d06ac6ef22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40764
13592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.4076413592
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.1044306561
Short name T2250
Test name
Test status
Simulation time 5837852397 ps
CPU time 173.49 seconds
Started Jul 31 05:44:35 PM PDT 24
Finished Jul 31 05:47:28 PM PDT 24
Peak memory 215444 kb
Host smart-c31140b9-c868-4f6e-a1c1-d3e26ecab588
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1044306561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.1044306561
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.2236150891
Short name T1535
Test name
Test status
Simulation time 7942186283 ps
CPU time 53.57 seconds
Started Jul 31 05:44:35 PM PDT 24
Finished Jul 31 05:45:28 PM PDT 24
Peak memory 207156 kb
Host smart-34ced8da-d4ad-4145-b952-d081ce5706fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2236150891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.2236150891
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1016345488
Short name T1170
Test name
Test status
Simulation time 224582988 ps
CPU time 0.96 seconds
Started Jul 31 05:44:31 PM PDT 24
Finished Jul 31 05:44:32 PM PDT 24
Peak memory 206968 kb
Host smart-ae8297fc-866b-4eb3-a9c1-2afb50eb68b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10163
45488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1016345488
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.3103114196
Short name T2708
Test name
Test status
Simulation time 23275592368 ps
CPU time 36.06 seconds
Started Jul 31 05:44:38 PM PDT 24
Finished Jul 31 05:45:14 PM PDT 24
Peak memory 207264 kb
Host smart-796ba50c-f72c-4c41-8be8-ef18f412f6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31031
14196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3103114196
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2252222387
Short name T1698
Test name
Test status
Simulation time 3267070093 ps
CPU time 4.82 seconds
Started Jul 31 05:44:38 PM PDT 24
Finished Jul 31 05:44:43 PM PDT 24
Peak memory 207180 kb
Host smart-9bba47d1-3238-4148-85c2-db6fc7acb228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22522
22387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2252222387
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1289885177
Short name T2095
Test name
Test status
Simulation time 9638287264 ps
CPU time 274.84 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:49:16 PM PDT 24
Peak memory 214768 kb
Host smart-5f3583dc-adf5-4d42-8e12-3596bd9670c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12898
85177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1289885177
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.3286388487
Short name T855
Test name
Test status
Simulation time 7766584698 ps
CPU time 57.53 seconds
Started Jul 31 05:44:34 PM PDT 24
Finished Jul 31 05:45:31 PM PDT 24
Peak memory 207164 kb
Host smart-4ea4aa9d-2f56-46ab-ac22-926088f987f3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3286388487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.3286388487
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.412915460
Short name T1481
Test name
Test status
Simulation time 238030303 ps
CPU time 0.96 seconds
Started Jul 31 05:44:39 PM PDT 24
Finished Jul 31 05:44:40 PM PDT 24
Peak memory 206996 kb
Host smart-35752206-0b3d-4a8b-8f2e-0b8197ca329a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=412915460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.412915460
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2363453434
Short name T1304
Test name
Test status
Simulation time 206791600 ps
CPU time 1 seconds
Started Jul 31 05:44:34 PM PDT 24
Finished Jul 31 05:44:35 PM PDT 24
Peak memory 206948 kb
Host smart-a5998918-9829-4052-a206-0de74d4faf4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23634
53434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2363453434
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1361992617
Short name T550
Test name
Test status
Simulation time 5101991442 ps
CPU time 151.77 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:47:12 PM PDT 24
Peak memory 215412 kb
Host smart-a79f5305-f1c3-4323-8a29-f4d8632a817d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13619
92617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1361992617
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.4195930103
Short name T1228
Test name
Test status
Simulation time 4402465756 ps
CPU time 42.6 seconds
Started Jul 31 05:44:36 PM PDT 24
Finished Jul 31 05:45:19 PM PDT 24
Peak memory 216904 kb
Host smart-e2595ef3-9f29-47b3-a620-296c67ebfad0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4195930103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.4195930103
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1974669426
Short name T2855
Test name
Test status
Simulation time 150974228 ps
CPU time 0.99 seconds
Started Jul 31 05:44:41 PM PDT 24
Finished Jul 31 05:44:42 PM PDT 24
Peak memory 207036 kb
Host smart-f2f1a6e2-bc68-4d69-a082-356db275d873
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1974669426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1974669426
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2431623895
Short name T1436
Test name
Test status
Simulation time 144073525 ps
CPU time 0.83 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:44:41 PM PDT 24
Peak memory 207008 kb
Host smart-f00404d1-228a-46f7-8d4c-89a0a7ade952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24316
23895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2431623895
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.2957880987
Short name T118
Test name
Test status
Simulation time 218318461 ps
CPU time 1 seconds
Started Jul 31 05:44:38 PM PDT 24
Finished Jul 31 05:44:40 PM PDT 24
Peak memory 206988 kb
Host smart-9329dc03-c48f-4792-98e6-d0a87b8cdc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29578
80987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.2957880987
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3202442904
Short name T1338
Test name
Test status
Simulation time 188899141 ps
CPU time 0.92 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:44:41 PM PDT 24
Peak memory 206984 kb
Host smart-9eae64b0-df6c-4e74-8d25-f528450368ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32024
42904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3202442904
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.847710299
Short name T772
Test name
Test status
Simulation time 186620655 ps
CPU time 0.93 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:44:41 PM PDT 24
Peak memory 206996 kb
Host smart-568da084-de41-47fe-8a8d-2d9709f83294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84771
0299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.847710299
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.3098921220
Short name T471
Test name
Test status
Simulation time 183062383 ps
CPU time 0.95 seconds
Started Jul 31 05:44:41 PM PDT 24
Finished Jul 31 05:44:42 PM PDT 24
Peak memory 206976 kb
Host smart-90e0ae15-d395-4205-ab11-28efca9d9782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30989
21220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3098921220
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2538771376
Short name T152
Test name
Test status
Simulation time 145136238 ps
CPU time 0.9 seconds
Started Jul 31 05:44:41 PM PDT 24
Finished Jul 31 05:44:42 PM PDT 24
Peak memory 207000 kb
Host smart-b8c54fca-2626-493e-bee6-f976c0f3d6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25387
71376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2538771376
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.2564399900
Short name T1913
Test name
Test status
Simulation time 303905019 ps
CPU time 1.19 seconds
Started Jul 31 05:44:38 PM PDT 24
Finished Jul 31 05:44:40 PM PDT 24
Peak memory 206996 kb
Host smart-e43eac8e-a3c3-4eb3-bed8-b7c9b4c9c99b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2564399900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.2564399900
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.343101804
Short name T1016
Test name
Test status
Simulation time 146869171 ps
CPU time 0.87 seconds
Started Jul 31 05:44:42 PM PDT 24
Finished Jul 31 05:44:43 PM PDT 24
Peak memory 206948 kb
Host smart-fde632ba-573a-4d09-9844-d2c401fa7f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34310
1804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.343101804
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1303753684
Short name T2320
Test name
Test status
Simulation time 42549516 ps
CPU time 0.72 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:44:41 PM PDT 24
Peak memory 206984 kb
Host smart-e240d0aa-465c-4440-bd9a-23d96256297a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13037
53684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1303753684
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.3724442624
Short name T2558
Test name
Test status
Simulation time 20938210119 ps
CPU time 54.82 seconds
Started Jul 31 05:44:39 PM PDT 24
Finished Jul 31 05:45:34 PM PDT 24
Peak memory 215452 kb
Host smart-21f7e2d6-84ab-4d38-b9eb-50539b3c2497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37244
42624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.3724442624
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1026994972
Short name T45
Test name
Test status
Simulation time 188450758 ps
CPU time 0.86 seconds
Started Jul 31 05:44:42 PM PDT 24
Finished Jul 31 05:44:43 PM PDT 24
Peak memory 206996 kb
Host smart-fd5a419f-d0b4-4394-9472-4e2ffac1a8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10269
94972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1026994972
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2175164272
Short name T1087
Test name
Test status
Simulation time 167423893 ps
CPU time 0.91 seconds
Started Jul 31 05:44:41 PM PDT 24
Finished Jul 31 05:44:42 PM PDT 24
Peak memory 206984 kb
Host smart-e4e4b1aa-7055-4866-9a28-c8ffe6077d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21751
64272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2175164272
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.1958055291
Short name T2412
Test name
Test status
Simulation time 249473078 ps
CPU time 0.99 seconds
Started Jul 31 05:44:41 PM PDT 24
Finished Jul 31 05:44:42 PM PDT 24
Peak memory 206992 kb
Host smart-e5803295-9cb7-4234-ae28-a86b73a1e699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19580
55291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.1958055291
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.408704811
Short name T1475
Test name
Test status
Simulation time 181663296 ps
CPU time 0.91 seconds
Started Jul 31 05:44:42 PM PDT 24
Finished Jul 31 05:44:43 PM PDT 24
Peak memory 206980 kb
Host smart-94ae9c95-7b4f-405e-a5fd-14301a4e256a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40870
4811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.408704811
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.82990635
Short name T2121
Test name
Test status
Simulation time 229130554 ps
CPU time 0.94 seconds
Started Jul 31 05:44:41 PM PDT 24
Finished Jul 31 05:44:42 PM PDT 24
Peak memory 206964 kb
Host smart-e582f590-36c1-4975-9dce-f623c1c76f26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82990
635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.82990635
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.2808538700
Short name T1950
Test name
Test status
Simulation time 164723797 ps
CPU time 0.84 seconds
Started Jul 31 05:44:39 PM PDT 24
Finished Jul 31 05:44:40 PM PDT 24
Peak memory 206960 kb
Host smart-75aa9d51-d2a1-4cb4-9a30-f2a7b62667e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28085
38700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2808538700
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2058560585
Short name T2382
Test name
Test status
Simulation time 163486201 ps
CPU time 0.87 seconds
Started Jul 31 05:44:39 PM PDT 24
Finished Jul 31 05:44:40 PM PDT 24
Peak memory 207004 kb
Host smart-3bf72975-f280-41fc-9e27-be2e0df05756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20585
60585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2058560585
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3731982030
Short name T1454
Test name
Test status
Simulation time 228367294 ps
CPU time 1.02 seconds
Started Jul 31 05:44:41 PM PDT 24
Finished Jul 31 05:44:42 PM PDT 24
Peak memory 206976 kb
Host smart-c5f1e83b-b18b-4efe-a07a-ec8145db99a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37319
82030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3731982030
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2833542987
Short name T1732
Test name
Test status
Simulation time 4253012361 ps
CPU time 129.7 seconds
Started Jul 31 05:44:41 PM PDT 24
Finished Jul 31 05:46:50 PM PDT 24
Peak memory 215368 kb
Host smart-95ab6084-a0c3-4da9-bfb5-24506599af15
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2833542987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2833542987
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.1904155291
Short name T1235
Test name
Test status
Simulation time 190171693 ps
CPU time 0.88 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:44:41 PM PDT 24
Peak memory 206980 kb
Host smart-470e9e29-a26c-43bf-b449-cf8061b6d824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19041
55291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.1904155291
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.4074954397
Short name T2534
Test name
Test status
Simulation time 164313151 ps
CPU time 0.89 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:44:41 PM PDT 24
Peak memory 206988 kb
Host smart-59726ccf-7482-448d-aa05-b684042d72ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40749
54397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.4074954397
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.526605332
Short name T2731
Test name
Test status
Simulation time 582263189 ps
CPU time 1.8 seconds
Started Jul 31 05:44:52 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 206952 kb
Host smart-b00ff165-23d5-4d22-9b45-eb18dbd23fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52660
5332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.526605332
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.678287226
Short name T2864
Test name
Test status
Simulation time 4566034741 ps
CPU time 37.22 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:45:27 PM PDT 24
Peak memory 216600 kb
Host smart-54e179d6-df8a-42df-a171-6daceb9ed2ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67828
7226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.678287226
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.455024605
Short name T526
Test name
Test status
Simulation time 2943410093 ps
CPU time 18.69 seconds
Started Jul 31 05:44:40 PM PDT 24
Finished Jul 31 05:44:59 PM PDT 24
Peak memory 207172 kb
Host smart-187d8186-d2d1-4c29-9dc8-05b9f7a8fa2f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455024605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_host
_handshake.455024605
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2351204722
Short name T794
Test name
Test status
Simulation time 49218157 ps
CPU time 0.7 seconds
Started Jul 31 05:44:54 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 207044 kb
Host smart-d380bfa2-64b9-4b15-a9df-e73231377516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2351204722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2351204722
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3360699176
Short name T1729
Test name
Test status
Simulation time 4342484433 ps
CPU time 6.55 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:44:57 PM PDT 24
Peak memory 207236 kb
Host smart-18b329e8-af36-406b-baa5-40b2e66fdc34
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360699176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.3360699176
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.2883156197
Short name T1741
Test name
Test status
Simulation time 13347191794 ps
CPU time 15.17 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:45:05 PM PDT 24
Peak memory 207228 kb
Host smart-1f50552b-7188-4f47-9fc4-344c5c5ae4da
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883156197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.2883156197
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2804492087
Short name T2834
Test name
Test status
Simulation time 23356191835 ps
CPU time 29.19 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:45:21 PM PDT 24
Peak memory 207188 kb
Host smart-1f458530-ca0c-48a8-aadb-9be20b85f676
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804492087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.2804492087
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1883279669
Short name T1755
Test name
Test status
Simulation time 190635062 ps
CPU time 0.99 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:44:50 PM PDT 24
Peak memory 207008 kb
Host smart-bf3802b0-9918-47c8-89bf-4ac54e774ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18832
79669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1883279669
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.2024303280
Short name T66
Test name
Test status
Simulation time 157046695 ps
CPU time 0.85 seconds
Started Jul 31 05:44:52 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 207028 kb
Host smart-d230ed3c-d141-400a-b8e1-fa7d4ea23c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20243
03280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.2024303280
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1667052504
Short name T1555
Test name
Test status
Simulation time 324504484 ps
CPU time 1.29 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:52 PM PDT 24
Peak memory 206988 kb
Host smart-1d3195ac-8b20-4bcf-8ea8-a0cc4f3796c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16670
52504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1667052504
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.682506718
Short name T1569
Test name
Test status
Simulation time 609282268 ps
CPU time 1.77 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 206996 kb
Host smart-99a862fa-a391-4130-b107-3d2c9273dbf2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=682506718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.682506718
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.828230745
Short name T1664
Test name
Test status
Simulation time 16372234788 ps
CPU time 34.92 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:45:25 PM PDT 24
Peak memory 207208 kb
Host smart-62bebac0-a6d5-4b5c-be53-32377f833118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82823
0745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.828230745
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_device_timeout.3719603054
Short name T1364
Test name
Test status
Simulation time 1164398524 ps
CPU time 26.14 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:45:16 PM PDT 24
Peak memory 207124 kb
Host smart-eba9d8c0-9320-4087-b078-82706f27b028
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719603054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.3719603054
Directory /workspace/31.usbdev_device_timeout/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3357400582
Short name T2504
Test name
Test status
Simulation time 289233866 ps
CPU time 1.14 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:44:52 PM PDT 24
Peak memory 206952 kb
Host smart-ed50cfd2-8546-4ed0-be1d-d60d90c708c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33574
00582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3357400582
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2009868412
Short name T2531
Test name
Test status
Simulation time 159828536 ps
CPU time 0.94 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:52 PM PDT 24
Peak memory 206952 kb
Host smart-784d6b92-4d6c-4bb8-a0d5-43656064ee48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20098
68412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2009868412
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.3203192669
Short name T1176
Test name
Test status
Simulation time 45123294 ps
CPU time 0.73 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 206936 kb
Host smart-e43d1d5e-3bc5-4426-b189-8eb8d0b33be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32031
92669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.3203192669
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.3074232390
Short name T745
Test name
Test status
Simulation time 977456099 ps
CPU time 2.85 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 207188 kb
Host smart-6dc99dc6-5d04-4fd0-b00c-94ce34b1b11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30742
32390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.3074232390
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3293998118
Short name T2194
Test name
Test status
Simulation time 260874594 ps
CPU time 2.02 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 207028 kb
Host smart-5a02a2f7-c8d8-4c71-b12a-c1c0f6c7d89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32939
98118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3293998118
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.2590492045
Short name T1177
Test name
Test status
Simulation time 187912443 ps
CPU time 0.93 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:52 PM PDT 24
Peak memory 207020 kb
Host smart-1a772b1e-4bb5-4ec6-8c0a-84cd857e1db7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2590492045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.2590492045
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3860279577
Short name T1116
Test name
Test status
Simulation time 144015198 ps
CPU time 0.86 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:44:50 PM PDT 24
Peak memory 206920 kb
Host smart-bace914f-596f-4fe8-9f44-e7299f34db1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38602
79577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3860279577
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.1006981014
Short name T2401
Test name
Test status
Simulation time 178682199 ps
CPU time 0.91 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 207012 kb
Host smart-db385859-2a7e-44b5-a933-b89f99f86870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10069
81014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1006981014
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.1587104
Short name T1269
Test name
Test status
Simulation time 6789963410 ps
CPU time 54.82 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:45:45 PM PDT 24
Peak memory 207220 kb
Host smart-919bb7b6-7649-425e-a8cf-ed391cf2c088
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1587104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1587104
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.3914457720
Short name T1632
Test name
Test status
Simulation time 14922702287 ps
CPU time 94.09 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:46:25 PM PDT 24
Peak memory 207140 kb
Host smart-a1636d86-cc49-4d0c-818c-466567fd5a29
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3914457720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.3914457720
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.881866643
Short name T2862
Test name
Test status
Simulation time 182430000 ps
CPU time 0.86 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:52 PM PDT 24
Peak memory 206968 kb
Host smart-5e9b44c8-3387-46c3-91c6-14f2236e4fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88186
6643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.881866643
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.262152014
Short name T1201
Test name
Test status
Simulation time 23323781036 ps
CPU time 28.66 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:45:18 PM PDT 24
Peak memory 207176 kb
Host smart-7a8fe086-4869-41d5-9da0-821686ad5e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26215
2014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.262152014
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.1602406661
Short name T2520
Test name
Test status
Simulation time 3346057026 ps
CPU time 5.27 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 207128 kb
Host smart-8bc5837a-0482-419f-bb96-d962b43b6fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16024
06661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.1602406661
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1910474700
Short name T1971
Test name
Test status
Simulation time 5801341489 ps
CPU time 42.53 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:45:33 PM PDT 24
Peak memory 223552 kb
Host smart-63ec2d78-1561-4efa-87ab-291e2d3a7554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19104
74700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1910474700
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1595538729
Short name T2239
Test name
Test status
Simulation time 4234237440 ps
CPU time 32.55 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 215424 kb
Host smart-df2b1336-6219-446c-a0cf-176c846ffdd9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1595538729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1595538729
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3727287889
Short name T2395
Test name
Test status
Simulation time 249363292 ps
CPU time 1 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:52 PM PDT 24
Peak memory 206992 kb
Host smart-0f63f93c-b6d9-4fe1-bc18-40367cba85b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3727287889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3727287889
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.3772153201
Short name T1745
Test name
Test status
Simulation time 189936456 ps
CPU time 0.93 seconds
Started Jul 31 05:44:46 PM PDT 24
Finished Jul 31 05:44:47 PM PDT 24
Peak memory 206936 kb
Host smart-8aa84f14-2f1a-42c8-80f7-b7c77cfba825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37721
53201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.3772153201
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.2162332997
Short name T2149
Test name
Test status
Simulation time 3394672610 ps
CPU time 29.14 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:45:19 PM PDT 24
Peak memory 216888 kb
Host smart-7b9deb98-c5cc-4645-acab-f31ca97bf359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21623
32997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.2162332997
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3215627047
Short name T1503
Test name
Test status
Simulation time 5631547303 ps
CPU time 164.04 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:47:35 PM PDT 24
Peak memory 215368 kb
Host smart-07b99370-ed29-443b-9b29-e9acdf6b339e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3215627047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3215627047
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.1997275622
Short name T27
Test name
Test status
Simulation time 188638405 ps
CPU time 0.92 seconds
Started Jul 31 05:44:48 PM PDT 24
Finished Jul 31 05:44:49 PM PDT 24
Peak memory 207020 kb
Host smart-611bb8c1-fb86-4e66-96f3-55db13fb1c67
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1997275622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.1997275622
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.939847714
Short name T2705
Test name
Test status
Simulation time 185472113 ps
CPU time 0.91 seconds
Started Jul 31 05:44:47 PM PDT 24
Finished Jul 31 05:44:48 PM PDT 24
Peak memory 206952 kb
Host smart-12346dac-c473-49e7-b3de-9fff2a80854c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93984
7714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.939847714
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.766778141
Short name T121
Test name
Test status
Simulation time 215499050 ps
CPU time 0.99 seconds
Started Jul 31 05:44:52 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 207020 kb
Host smart-5cf28317-93d5-4e11-9895-33853b0b957f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76677
8141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.766778141
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.1094412676
Short name T1704
Test name
Test status
Simulation time 176175203 ps
CPU time 0.86 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 207028 kb
Host smart-880bcf6a-c1f0-4cc6-bdaa-3782aa73cf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944
12676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.1094412676
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1761519166
Short name T1551
Test name
Test status
Simulation time 173447193 ps
CPU time 0.88 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 206992 kb
Host smart-5b44f1bf-293f-41a4-9c23-628ef9cc062a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17615
19166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1761519166
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1626634622
Short name T287
Test name
Test status
Simulation time 233761185 ps
CPU time 0.99 seconds
Started Jul 31 05:44:48 PM PDT 24
Finished Jul 31 05:44:49 PM PDT 24
Peak memory 206972 kb
Host smart-9652e305-f9bc-4fd1-9210-deb09d71a2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16266
34622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1626634622
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3711204051
Short name T2537
Test name
Test status
Simulation time 163451490 ps
CPU time 0.87 seconds
Started Jul 31 05:44:54 PM PDT 24
Finished Jul 31 05:44:55 PM PDT 24
Peak memory 206996 kb
Host smart-ba5d545b-7a20-4f07-a3dd-e22d2cf0371a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37112
04051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3711204051
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3104981634
Short name T495
Test name
Test status
Simulation time 223598815 ps
CPU time 1.05 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 206992 kb
Host smart-904d5188-0328-49c0-8aec-0486826092ca
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3104981634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3104981634
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3561805358
Short name T182
Test name
Test status
Simulation time 142152973 ps
CPU time 0.8 seconds
Started Jul 31 05:44:52 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 206964 kb
Host smart-1e2946f7-fc9f-43bf-b687-ea220f20a79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35618
05358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3561805358
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1866471336
Short name T837
Test name
Test status
Simulation time 40383787 ps
CPU time 0.68 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:44:51 PM PDT 24
Peak memory 206948 kb
Host smart-e2b2a74d-7977-4eeb-9ba6-11514be42d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18664
71336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1866471336
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.1164059093
Short name T2450
Test name
Test status
Simulation time 14286853575 ps
CPU time 37.43 seconds
Started Jul 31 05:44:50 PM PDT 24
Finished Jul 31 05:45:27 PM PDT 24
Peak memory 215500 kb
Host smart-c8db1831-08c0-4437-9599-7337135ea65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11640
59093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.1164059093
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.3103492220
Short name T2108
Test name
Test status
Simulation time 190924367 ps
CPU time 0.94 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 206984 kb
Host smart-d9235a9c-0761-4d5f-ba5c-46e87b023553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31034
92220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.3103492220
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.1125220059
Short name T1181
Test name
Test status
Simulation time 187602325 ps
CPU time 0.93 seconds
Started Jul 31 05:44:47 PM PDT 24
Finished Jul 31 05:44:49 PM PDT 24
Peak memory 207000 kb
Host smart-17fe5dd3-9b71-4fa3-bda3-a42c72e0ac25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11252
20059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.1125220059
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2013611447
Short name T459
Test name
Test status
Simulation time 185036703 ps
CPU time 0.9 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:52 PM PDT 24
Peak memory 206992 kb
Host smart-456511ab-3fa0-4bf7-a47a-d896babf6cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20136
11447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2013611447
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.90397271
Short name T237
Test name
Test status
Simulation time 190353800 ps
CPU time 0.97 seconds
Started Jul 31 05:44:48 PM PDT 24
Finished Jul 31 05:44:49 PM PDT 24
Peak memory 206980 kb
Host smart-413a9757-4487-46ef-bd4b-064105fb4e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90397
271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.90397271
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.4015113193
Short name T542
Test name
Test status
Simulation time 178205492 ps
CPU time 0.87 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:44:50 PM PDT 24
Peak memory 207012 kb
Host smart-04f90047-3f38-4f7a-b811-127148712448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
13193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.4015113193
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.2890977971
Short name T143
Test name
Test status
Simulation time 154708065 ps
CPU time 0.85 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:52 PM PDT 24
Peak memory 206960 kb
Host smart-f8c2efc1-b330-46d6-a746-f3e6834770a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28909
77971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2890977971
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4280645159
Short name T1361
Test name
Test status
Simulation time 166484938 ps
CPU time 0.93 seconds
Started Jul 31 05:44:53 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 207024 kb
Host smart-2b6ba155-2c4d-4a80-81a0-56892597184d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42806
45159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4280645159
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.660527100
Short name T452
Test name
Test status
Simulation time 223996426 ps
CPU time 1.02 seconds
Started Jul 31 05:44:55 PM PDT 24
Finished Jul 31 05:44:56 PM PDT 24
Peak memory 206976 kb
Host smart-5aa63b61-dad1-4d6f-8215-f15d6bada013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66052
7100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.660527100
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.2790242961
Short name T2776
Test name
Test status
Simulation time 4318560139 ps
CPU time 36.83 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:45:26 PM PDT 24
Peak memory 216996 kb
Host smart-8fff8fdd-d40e-4a3b-b912-f406596014fa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2790242961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.2790242961
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.499398788
Short name T2299
Test name
Test status
Simulation time 178371407 ps
CPU time 0.89 seconds
Started Jul 31 05:44:47 PM PDT 24
Finished Jul 31 05:44:48 PM PDT 24
Peak memory 207004 kb
Host smart-e15ae53e-dc5f-45df-9e7c-5f1a0e3f9739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49939
8788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.499398788
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2508870667
Short name T2661
Test name
Test status
Simulation time 164243350 ps
CPU time 0.89 seconds
Started Jul 31 05:44:54 PM PDT 24
Finished Jul 31 05:44:55 PM PDT 24
Peak memory 207000 kb
Host smart-0d69c87c-d5de-426f-975f-83a1194d129c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25088
70667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2508870667
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.3826750514
Short name T841
Test name
Test status
Simulation time 395779004 ps
CPU time 1.3 seconds
Started Jul 31 05:44:52 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 206940 kb
Host smart-a3846e88-267f-4196-a458-cf3e307ab459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38267
50514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.3826750514
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2941241706
Short name T570
Test name
Test status
Simulation time 3950801301 ps
CPU time 37.4 seconds
Started Jul 31 05:44:52 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 216744 kb
Host smart-d6abae15-2ad0-4772-9291-9c63ef0fdc63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29412
41706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2941241706
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.3180409366
Short name T2460
Test name
Test status
Simulation time 3172478477 ps
CPU time 21.46 seconds
Started Jul 31 05:44:46 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 207240 kb
Host smart-431e5f28-2325-4015-85ba-006414f03ba4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180409366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.3180409366
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.2434261014
Short name T1397
Test name
Test status
Simulation time 35019128 ps
CPU time 0.7 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 207012 kb
Host smart-05ad7c2f-e37e-417e-a5ee-012066167f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2434261014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.2434261014
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3927562440
Short name T2784
Test name
Test status
Simulation time 4386190631 ps
CPU time 7.23 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:58 PM PDT 24
Peak memory 207216 kb
Host smart-75afb7d2-2be9-47d6-8bc5-c2749f8c09ed
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927562440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.3927562440
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.1466069061
Short name T934
Test name
Test status
Simulation time 13338607413 ps
CPU time 17.19 seconds
Started Jul 31 05:44:53 PM PDT 24
Finished Jul 31 05:45:10 PM PDT 24
Peak memory 207244 kb
Host smart-32eb3bce-1e82-4e09-b958-fd8db2bbce36
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466069061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.1466069061
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3144903460
Short name T2083
Test name
Test status
Simulation time 23460277397 ps
CPU time 29.41 seconds
Started Jul 31 05:44:54 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 207176 kb
Host smart-3a49dd80-0f2c-4ada-a2ae-4bd665410ead
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144903460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_resume.3144903460
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.359518918
Short name T2100
Test name
Test status
Simulation time 153124794 ps
CPU time 0.82 seconds
Started Jul 31 05:44:49 PM PDT 24
Finished Jul 31 05:44:50 PM PDT 24
Peak memory 206996 kb
Host smart-5802fa5d-ff00-467c-bc1b-1810f527fe59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35951
8918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.359518918
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2087923586
Short name T827
Test name
Test status
Simulation time 140962499 ps
CPU time 0.82 seconds
Started Jul 31 05:44:52 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 206988 kb
Host smart-2788c3da-194d-4bee-8080-72930ad2d7d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20879
23586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2087923586
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.320035322
Short name T89
Test name
Test status
Simulation time 267582578 ps
CPU time 1.11 seconds
Started Jul 31 05:44:54 PM PDT 24
Finished Jul 31 05:44:55 PM PDT 24
Peak memory 206996 kb
Host smart-a218625b-95d9-401c-bc68-9738f366f387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32003
5322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.320035322
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3910157191
Short name T2088
Test name
Test status
Simulation time 1157380757 ps
CPU time 3.43 seconds
Started Jul 31 05:44:51 PM PDT 24
Finished Jul 31 05:44:55 PM PDT 24
Peak memory 207104 kb
Host smart-8493c2e2-9f2e-47e1-b8aa-5a373ae4328c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3910157191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3910157191
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.3160255554
Short name T291
Test name
Test status
Simulation time 9157989247 ps
CPU time 20.63 seconds
Started Jul 31 05:44:55 PM PDT 24
Finished Jul 31 05:45:16 PM PDT 24
Peak memory 207260 kb
Host smart-d94be0fe-b17e-41dd-8d85-4049c5e0082d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31602
55554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3160255554
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_device_timeout.1290796050
Short name T866
Test name
Test status
Simulation time 1949609628 ps
CPU time 13.89 seconds
Started Jul 31 05:44:52 PM PDT 24
Finished Jul 31 05:45:06 PM PDT 24
Peak memory 207136 kb
Host smart-5808f433-c764-45b1-a069-55a1c9ac914a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290796050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.1290796050
Directory /workspace/32.usbdev_device_timeout/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.612032280
Short name T1151
Test name
Test status
Simulation time 369583160 ps
CPU time 1.28 seconds
Started Jul 31 05:44:52 PM PDT 24
Finished Jul 31 05:44:53 PM PDT 24
Peak memory 206964 kb
Host smart-a5826ffb-d49e-46fa-864a-3a092ec37710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61203
2280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.612032280
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3369589558
Short name T1917
Test name
Test status
Simulation time 148640746 ps
CPU time 0.85 seconds
Started Jul 31 05:44:53 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 206964 kb
Host smart-9061f152-523d-481c-8975-96d17aa7d9af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33695
89558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3369589558
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2996583764
Short name T1450
Test name
Test status
Simulation time 46798469 ps
CPU time 0.77 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:45:08 PM PDT 24
Peak memory 206932 kb
Host smart-c9032ad6-bb64-447a-a23a-0bf26f17d8d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29965
83764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2996583764
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2527151603
Short name T2131
Test name
Test status
Simulation time 782856485 ps
CPU time 2.1 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:11 PM PDT 24
Peak memory 207172 kb
Host smart-535b8fda-38d0-456d-8a05-538a8adb4ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25271
51603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2527151603
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.552686569
Short name T174
Test name
Test status
Simulation time 233553882 ps
CPU time 1.95 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:05 PM PDT 24
Peak memory 207060 kb
Host smart-422cdb9c-d8af-489f-941b-7b4cc741dead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55268
6569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.552686569
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.724000082
Short name T356
Test name
Test status
Simulation time 193859775 ps
CPU time 0.97 seconds
Started Jul 31 05:44:57 PM PDT 24
Finished Jul 31 05:44:58 PM PDT 24
Peak memory 206996 kb
Host smart-026603ca-6c30-43f4-a0f1-75e134b36a9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=724000082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.724000082
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2236913984
Short name T2463
Test name
Test status
Simulation time 142935022 ps
CPU time 0.87 seconds
Started Jul 31 05:44:56 PM PDT 24
Finished Jul 31 05:44:57 PM PDT 24
Peak memory 206964 kb
Host smart-94f568c8-f0f9-483e-beed-716608be873a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22369
13984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2236913984
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2202776568
Short name T876
Test name
Test status
Simulation time 220288933 ps
CPU time 0.91 seconds
Started Jul 31 05:44:55 PM PDT 24
Finished Jul 31 05:44:57 PM PDT 24
Peak memory 206988 kb
Host smart-31147c76-4a3b-4915-a4fb-5aff2fe30860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22027
76568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2202776568
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.263403611
Short name T925
Test name
Test status
Simulation time 9217317066 ps
CPU time 89.76 seconds
Started Jul 31 05:44:56 PM PDT 24
Finished Jul 31 05:46:25 PM PDT 24
Peak memory 216520 kb
Host smart-b88eb72a-8b33-411a-b9ea-f35a3e6fdf3e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=263403611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.263403611
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.2934549838
Short name T883
Test name
Test status
Simulation time 10975154083 ps
CPU time 82.79 seconds
Started Jul 31 05:44:55 PM PDT 24
Finished Jul 31 05:46:18 PM PDT 24
Peak memory 207196 kb
Host smart-5c71ac66-a957-42f4-bb82-84fdf22a4e5e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2934549838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.2934549838
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.3110917012
Short name T1007
Test name
Test status
Simulation time 300449024 ps
CPU time 1.07 seconds
Started Jul 31 05:44:56 PM PDT 24
Finished Jul 31 05:44:57 PM PDT 24
Peak memory 207000 kb
Host smart-e1ea54bd-95d6-4cb0-be1a-8ad6074c47a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31109
17012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.3110917012
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2794763757
Short name T719
Test name
Test status
Simulation time 23291082296 ps
CPU time 26.83 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 207148 kb
Host smart-8d47d41c-00b2-48ff-a0e5-1df3cfad710a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27947
63757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2794763757
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3658721900
Short name T1768
Test name
Test status
Simulation time 3296904740 ps
CPU time 5.1 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:14 PM PDT 24
Peak memory 207176 kb
Host smart-b2237cd9-8a3c-47ca-98fc-4370216dabb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36587
21900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3658721900
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.4125071614
Short name T2301
Test name
Test status
Simulation time 9607380146 ps
CPU time 76.48 seconds
Started Jul 31 05:44:57 PM PDT 24
Finished Jul 31 05:46:13 PM PDT 24
Peak memory 217024 kb
Host smart-8ba438f3-7983-481b-bf93-b9248bfb2a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41250
71614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.4125071614
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3356539575
Short name T2544
Test name
Test status
Simulation time 4357548160 ps
CPU time 120.37 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:47:08 PM PDT 24
Peak memory 215404 kb
Host smart-ce4c41e0-5c2f-4762-84c6-49c595fc51c2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3356539575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3356539575
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3021180714
Short name T238
Test name
Test status
Simulation time 245840043 ps
CPU time 0.98 seconds
Started Jul 31 05:44:57 PM PDT 24
Finished Jul 31 05:44:59 PM PDT 24
Peak memory 207008 kb
Host smart-69934133-081d-4c3c-a898-2403b92846db
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3021180714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3021180714
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3732298188
Short name T378
Test name
Test status
Simulation time 197445684 ps
CPU time 1.04 seconds
Started Jul 31 05:44:56 PM PDT 24
Finished Jul 31 05:44:57 PM PDT 24
Peak memory 206988 kb
Host smart-050058ab-857e-48b4-b9ab-cda1ad26ad4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37322
98188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3732298188
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.2160579119
Short name T608
Test name
Test status
Simulation time 5555706337 ps
CPU time 163.74 seconds
Started Jul 31 05:44:55 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 215400 kb
Host smart-f12fd128-fecd-4b10-8c4e-eb9223ad3c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21605
79119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.2160579119
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.2122711041
Short name T1914
Test name
Test status
Simulation time 5554415371 ps
CPU time 165.21 seconds
Started Jul 31 05:44:56 PM PDT 24
Finished Jul 31 05:47:41 PM PDT 24
Peak memory 215400 kb
Host smart-b5c164ea-2dd3-4b68-a4be-7f43e7b9beb6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2122711041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.2122711041
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2262368851
Short name T2620
Test name
Test status
Simulation time 150724900 ps
CPU time 0.83 seconds
Started Jul 31 05:44:57 PM PDT 24
Finished Jul 31 05:44:58 PM PDT 24
Peak memory 207008 kb
Host smart-fed6ad1a-a1bb-4378-b1b5-ed999ce5364a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2262368851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2262368851
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.710061351
Short name T1426
Test name
Test status
Simulation time 146296893 ps
CPU time 0.84 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:10 PM PDT 24
Peak memory 207024 kb
Host smart-84c1dbfb-0c47-4fb3-ab5e-2d23205795a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71006
1351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.710061351
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.1366986060
Short name T114
Test name
Test status
Simulation time 210805886 ps
CPU time 0.98 seconds
Started Jul 31 05:44:55 PM PDT 24
Finished Jul 31 05:44:56 PM PDT 24
Peak memory 207036 kb
Host smart-cb8705b3-8fe3-4155-8f8d-cce554222357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
86060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.1366986060
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.2099780867
Short name T1678
Test name
Test status
Simulation time 220928933 ps
CPU time 0.95 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:45:08 PM PDT 24
Peak memory 207020 kb
Host smart-0cc24f9f-d314-43e6-91c4-e104bd1fe757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20997
80867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2099780867
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2613744992
Short name T1403
Test name
Test status
Simulation time 158055439 ps
CPU time 0.9 seconds
Started Jul 31 05:44:57 PM PDT 24
Finished Jul 31 05:44:58 PM PDT 24
Peak memory 207000 kb
Host smart-c72c0f76-37d9-4010-8964-c80038c0bc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26137
44992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2613744992
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3174384837
Short name T1626
Test name
Test status
Simulation time 172995418 ps
CPU time 0.9 seconds
Started Jul 31 05:44:54 PM PDT 24
Finished Jul 31 05:44:55 PM PDT 24
Peak memory 207024 kb
Host smart-bba32267-2189-4102-9983-9c70efb6fa3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31743
84837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3174384837
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1607990156
Short name T2431
Test name
Test status
Simulation time 161139172 ps
CPU time 0.9 seconds
Started Jul 31 05:44:56 PM PDT 24
Finished Jul 31 05:44:57 PM PDT 24
Peak memory 206980 kb
Host smart-77739955-533a-4013-b621-ca9b3e7a67ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16079
90156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1607990156
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2357384858
Short name T936
Test name
Test status
Simulation time 262218867 ps
CPU time 1.14 seconds
Started Jul 31 05:44:56 PM PDT 24
Finished Jul 31 05:44:58 PM PDT 24
Peak memory 207008 kb
Host smart-f268f968-8128-403d-94a0-b0d774ab9482
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2357384858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2357384858
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2521314284
Short name T1196
Test name
Test status
Simulation time 149088110 ps
CPU time 0.82 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 206800 kb
Host smart-36244bef-36e2-4bf7-b134-08eeff939c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25213
14284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2521314284
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.644055232
Short name T779
Test name
Test status
Simulation time 44255269 ps
CPU time 0.71 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 206860 kb
Host smart-d4f49b82-c209-416b-8a46-8586e32a2348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64405
5232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.644055232
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2767703787
Short name T246
Test name
Test status
Simulation time 22364544340 ps
CPU time 58.5 seconds
Started Jul 31 05:44:56 PM PDT 24
Finished Jul 31 05:45:55 PM PDT 24
Peak memory 215468 kb
Host smart-97e7b262-f0eb-4128-b75e-ba19e7dafe83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27677
03787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2767703787
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.988689318
Short name T2771
Test name
Test status
Simulation time 228225007 ps
CPU time 1.11 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:45:08 PM PDT 24
Peak memory 206968 kb
Host smart-0f0faab7-a3d8-4135-b64d-e3a2da42146c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98868
9318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.988689318
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3670786768
Short name T2070
Test name
Test status
Simulation time 190557460 ps
CPU time 0.93 seconds
Started Jul 31 05:44:55 PM PDT 24
Finished Jul 31 05:44:56 PM PDT 24
Peak memory 206996 kb
Host smart-95dcd673-971c-4e22-a9b1-0db041b8c802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36707
86768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3670786768
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.419176945
Short name T725
Test name
Test status
Simulation time 222979338 ps
CPU time 0.91 seconds
Started Jul 31 05:44:55 PM PDT 24
Finished Jul 31 05:44:56 PM PDT 24
Peak memory 207032 kb
Host smart-4a2c638c-e30d-4c53-9101-fc9ed0a1e38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41917
6945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.419176945
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.210394349
Short name T406
Test name
Test status
Simulation time 220230799 ps
CPU time 0.92 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:45:08 PM PDT 24
Peak memory 207024 kb
Host smart-b75b1260-3f61-4bc0-bae4-a785628d47f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21039
4349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.210394349
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.10506327
Short name T443
Test name
Test status
Simulation time 177844353 ps
CPU time 0.91 seconds
Started Jul 31 05:44:57 PM PDT 24
Finished Jul 31 05:44:58 PM PDT 24
Peak memory 206988 kb
Host smart-6e81a7b4-be14-4775-8e4c-4d585237b3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506
327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.10506327
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2972846677
Short name T2005
Test name
Test status
Simulation time 150442650 ps
CPU time 0.89 seconds
Started Jul 31 05:44:55 PM PDT 24
Finished Jul 31 05:44:57 PM PDT 24
Peak memory 206964 kb
Host smart-de0a9545-27d2-4e17-97d6-f770ccf0f99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29728
46677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2972846677
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.690244657
Short name T548
Test name
Test status
Simulation time 172504330 ps
CPU time 0.88 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 207028 kb
Host smart-42aead3c-2bb3-4e62-80fa-10ddc7f68d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69024
4657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.690244657
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3828196789
Short name T1443
Test name
Test status
Simulation time 261406885 ps
CPU time 1.06 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 207028 kb
Host smart-aa195cb8-3fda-4962-9061-ca9361e02696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38281
96789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3828196789
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.3071740503
Short name T1573
Test name
Test status
Simulation time 4047952053 ps
CPU time 40.5 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:45:48 PM PDT 24
Peak memory 215388 kb
Host smart-70242769-0f3e-4e32-bfb6-f063d73868a0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3071740503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.3071740503
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2892772110
Short name T2823
Test name
Test status
Simulation time 183168506 ps
CPU time 0.93 seconds
Started Jul 31 05:44:57 PM PDT 24
Finished Jul 31 05:44:58 PM PDT 24
Peak memory 206984 kb
Host smart-d7c3c622-1388-4e42-b542-83ab5adf245f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28927
72110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2892772110
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.3577530669
Short name T2236
Test name
Test status
Simulation time 176521810 ps
CPU time 0.85 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 207028 kb
Host smart-f371293f-922e-41a7-a1a2-c956c7223f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35775
30669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.3577530669
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.3410034781
Short name T2023
Test name
Test status
Simulation time 1196739578 ps
CPU time 3.08 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:10 PM PDT 24
Peak memory 207036 kb
Host smart-5ac4ec3a-11ff-49ca-b97b-ac1b4ef35a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34100
34781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.3410034781
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3180560284
Short name T1051
Test name
Test status
Simulation time 4311124949 ps
CPU time 125.54 seconds
Started Jul 31 05:44:56 PM PDT 24
Finished Jul 31 05:47:01 PM PDT 24
Peak memory 215404 kb
Host smart-1eba5e24-27f8-4399-99c1-68b853eb62dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31805
60284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3180560284
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.2135912571
Short name T2390
Test name
Test status
Simulation time 1146267092 ps
CPU time 26.48 seconds
Started Jul 31 05:44:53 PM PDT 24
Finished Jul 31 05:45:20 PM PDT 24
Peak memory 207132 kb
Host smart-8f7a7543-337f-44ca-9e3b-793b2ea34eda
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135912571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.2135912571
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3962137756
Short name T1050
Test name
Test status
Simulation time 47881050 ps
CPU time 0.68 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 207032 kb
Host smart-79cecb2c-3e87-480a-8930-5fa1f367b6fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3962137756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3962137756
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.3107167306
Short name T1584
Test name
Test status
Simulation time 3432442341 ps
CPU time 5.24 seconds
Started Jul 31 05:44:53 PM PDT 24
Finished Jul 31 05:44:58 PM PDT 24
Peak memory 207120 kb
Host smart-e57278d7-2221-42f8-ac2a-c1bf4a798a7c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107167306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_disconnect.3107167306
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3761649579
Short name T8
Test name
Test status
Simulation time 13380900172 ps
CPU time 15.5 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:45:23 PM PDT 24
Peak memory 207196 kb
Host smart-3819b9e5-067c-4543-9ed2-06ae9136a159
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761649579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3761649579
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1228814240
Short name T1630
Test name
Test status
Simulation time 23418468064 ps
CPU time 26.27 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:45:33 PM PDT 24
Peak memory 207164 kb
Host smart-99941296-4d26-4890-9583-9d8941e9b5ed
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228814240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.1228814240
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1805057426
Short name T1348
Test name
Test status
Simulation time 181800795 ps
CPU time 0.97 seconds
Started Jul 31 05:45:01 PM PDT 24
Finished Jul 31 05:45:02 PM PDT 24
Peak memory 206992 kb
Host smart-beb4bcb8-4020-4821-83ae-8661110b9019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18050
57426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1805057426
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.2052243884
Short name T1187
Test name
Test status
Simulation time 149056526 ps
CPU time 0.85 seconds
Started Jul 31 05:45:02 PM PDT 24
Finished Jul 31 05:45:03 PM PDT 24
Peak memory 206936 kb
Host smart-5081aba7-5117-4556-8f0b-aaf0fa529b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20522
43884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.2052243884
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.1838573381
Short name T1829
Test name
Test status
Simulation time 474137111 ps
CPU time 1.63 seconds
Started Jul 31 05:45:02 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 206996 kb
Host smart-eddc39fd-b03e-46ab-8e0a-884734b0a476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18385
73381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.1838573381
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3229802113
Short name T1422
Test name
Test status
Simulation time 434764245 ps
CPU time 1.44 seconds
Started Jul 31 05:45:00 PM PDT 24
Finished Jul 31 05:45:02 PM PDT 24
Peak memory 206996 kb
Host smart-e3c7b3e7-e506-447e-8f6d-8fb6a7d89cd6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3229802113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3229802113
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1729399482
Short name T2697
Test name
Test status
Simulation time 8721932521 ps
CPU time 20.58 seconds
Started Jul 31 05:44:58 PM PDT 24
Finished Jul 31 05:45:19 PM PDT 24
Peak memory 207148 kb
Host smart-89414842-6541-40e7-ad85-0ced25f67096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17293
99482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1729399482
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_device_timeout.79929603
Short name T1813
Test name
Test status
Simulation time 5014803437 ps
CPU time 36.99 seconds
Started Jul 31 05:45:00 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 207200 kb
Host smart-5410933c-7be9-4668-84cc-618671c12ff6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79929603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.79929603
Directory /workspace/33.usbdev_device_timeout/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.3839192951
Short name T1919
Test name
Test status
Simulation time 455643847 ps
CPU time 1.59 seconds
Started Jul 31 05:45:00 PM PDT 24
Finished Jul 31 05:45:02 PM PDT 24
Peak memory 207004 kb
Host smart-3338b1a2-3bf4-4829-a7a6-cbeba1cc8a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38391
92951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.3839192951
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.1264002026
Short name T1966
Test name
Test status
Simulation time 159456448 ps
CPU time 0.82 seconds
Started Jul 31 05:45:00 PM PDT 24
Finished Jul 31 05:45:01 PM PDT 24
Peak memory 206952 kb
Host smart-a51e31c9-f624-4ac1-92fc-25ea54dafd3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12640
02026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1264002026
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1670334985
Short name T2179
Test name
Test status
Simulation time 35726439 ps
CPU time 0.73 seconds
Started Jul 31 05:45:02 PM PDT 24
Finished Jul 31 05:45:03 PM PDT 24
Peak memory 206944 kb
Host smart-825cae22-ad98-42e5-9257-4d92759c6385
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16703
34985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1670334985
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.3748474767
Short name T2003
Test name
Test status
Simulation time 753544856 ps
CPU time 2.23 seconds
Started Jul 31 05:45:01 PM PDT 24
Finished Jul 31 05:45:03 PM PDT 24
Peak memory 207060 kb
Host smart-a87ed7d0-e0e9-4184-ac33-2670971c7921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37484
74767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.3748474767
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2071942719
Short name T2016
Test name
Test status
Simulation time 188407709 ps
CPU time 2.14 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:06 PM PDT 24
Peak memory 207020 kb
Host smart-4dc34dca-17e4-4cc5-a0f6-0495440d81ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20719
42719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2071942719
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3297413060
Short name T2767
Test name
Test status
Simulation time 157607000 ps
CPU time 0.93 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 207024 kb
Host smart-fc824e51-a47d-49b4-abfb-a8d93d60fba1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3297413060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3297413060
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1772555508
Short name T1622
Test name
Test status
Simulation time 138551757 ps
CPU time 0.85 seconds
Started Jul 31 05:45:01 PM PDT 24
Finished Jul 31 05:45:02 PM PDT 24
Peak memory 206968 kb
Host smart-0408b0b7-07b0-4862-893e-a7e4a7f26264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17725
55508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1772555508
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.2002077281
Short name T410
Test name
Test status
Simulation time 171367863 ps
CPU time 0.86 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 206996 kb
Host smart-1cbc09b0-907e-4312-a6da-73902848fd1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20020
77281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2002077281
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.2189760697
Short name T1960
Test name
Test status
Simulation time 8664254566 ps
CPU time 80.47 seconds
Started Jul 31 05:44:58 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 215432 kb
Host smart-ecb1dd60-10c7-4200-b514-d91345deb6b8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2189760697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.2189760697
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.1474129955
Short name T361
Test name
Test status
Simulation time 5047447577 ps
CPU time 33.41 seconds
Started Jul 31 05:45:02 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 207168 kb
Host smart-1c14a103-1d3d-40cc-baa7-34790f74ec28
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1474129955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.1474129955
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2455125794
Short name T2422
Test name
Test status
Simulation time 239129978 ps
CPU time 1 seconds
Started Jul 31 05:44:59 PM PDT 24
Finished Jul 31 05:45:00 PM PDT 24
Peak memory 206972 kb
Host smart-1d547e7f-575d-4a7f-be58-c6ec460a2f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24551
25794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2455125794
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.4066256660
Short name T1083
Test name
Test status
Simulation time 23292589674 ps
CPU time 29.46 seconds
Started Jul 31 05:45:00 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 207228 kb
Host smart-1793abf7-2279-413d-89f5-3831c112afe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40662
56660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.4066256660
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2550463978
Short name T931
Test name
Test status
Simulation time 3286666739 ps
CPU time 5.08 seconds
Started Jul 31 05:45:04 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 207136 kb
Host smart-49aac634-cd52-4ddd-b099-d9b8948f4539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25504
63978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2550463978
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.445729964
Short name T1214
Test name
Test status
Simulation time 5851568600 ps
CPU time 164.55 seconds
Started Jul 31 05:45:02 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 215364 kb
Host smart-17ace986-7a40-4ebb-aff5-129ad7ecf9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44572
9964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.445729964
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.627836410
Short name T1282
Test name
Test status
Simulation time 5560697925 ps
CPU time 58.07 seconds
Started Jul 31 05:45:02 PM PDT 24
Finished Jul 31 05:46:00 PM PDT 24
Peak memory 207244 kb
Host smart-b0c2f902-beb8-4cdc-8bbb-9f1ccf536efd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=627836410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.627836410
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1834734945
Short name T2217
Test name
Test status
Simulation time 275722872 ps
CPU time 1.07 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 206992 kb
Host smart-036ef1b5-9110-4952-83f0-d29880d30641
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1834734945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1834734945
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2678944812
Short name T1428
Test name
Test status
Simulation time 194229248 ps
CPU time 0.95 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 206976 kb
Host smart-6090142f-cefa-4985-a9cc-f88c563c1eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26789
44812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2678944812
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.2278553302
Short name T1931
Test name
Test status
Simulation time 5289207125 ps
CPU time 159.2 seconds
Started Jul 31 05:45:00 PM PDT 24
Finished Jul 31 05:47:40 PM PDT 24
Peak memory 215432 kb
Host smart-24e07603-f29e-4d27-ab09-b3f134a6bda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22785
53302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.2278553302
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1447952274
Short name T1281
Test name
Test status
Simulation time 6163882333 ps
CPU time 55.55 seconds
Started Jul 31 05:45:00 PM PDT 24
Finished Jul 31 05:45:56 PM PDT 24
Peak memory 207168 kb
Host smart-600baf4e-2e02-4195-948e-e8c2198507b4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1447952274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1447952274
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2977513713
Short name T910
Test name
Test status
Simulation time 165615216 ps
CPU time 0.86 seconds
Started Jul 31 05:45:01 PM PDT 24
Finished Jul 31 05:45:02 PM PDT 24
Peak memory 207004 kb
Host smart-695f3f49-aa99-4060-8ee8-4fd7c08e192c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2977513713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2977513713
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.140053378
Short name T2735
Test name
Test status
Simulation time 156884190 ps
CPU time 0.88 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 206984 kb
Host smart-16a3c583-6f3b-49aa-9736-362d82504f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14005
3378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.140053378
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2166381424
Short name T1872
Test name
Test status
Simulation time 236778168 ps
CPU time 0.99 seconds
Started Jul 31 05:45:01 PM PDT 24
Finished Jul 31 05:45:02 PM PDT 24
Peak memory 207020 kb
Host smart-e67d6442-8a05-4e6b-8a0f-08d836a2a24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21663
81424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2166381424
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.1360715213
Short name T1754
Test name
Test status
Simulation time 211402061 ps
CPU time 1.04 seconds
Started Jul 31 05:45:01 PM PDT 24
Finished Jul 31 05:45:02 PM PDT 24
Peak memory 206968 kb
Host smart-2d8ca9c8-20c5-4c20-82b2-cbce21db5189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13607
15213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.1360715213
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2387752439
Short name T2573
Test name
Test status
Simulation time 221892781 ps
CPU time 0.98 seconds
Started Jul 31 05:44:59 PM PDT 24
Finished Jul 31 05:45:00 PM PDT 24
Peak memory 207000 kb
Host smart-9b0d6613-4a6e-423f-a1e2-d7553f749c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23877
52439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2387752439
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1384649075
Short name T2356
Test name
Test status
Simulation time 188188523 ps
CPU time 0.93 seconds
Started Jul 31 05:44:59 PM PDT 24
Finished Jul 31 05:45:00 PM PDT 24
Peak memory 207008 kb
Host smart-0e3e787a-4986-4d26-8a04-3e6fa5f89f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13846
49075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1384649075
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2831167376
Short name T1086
Test name
Test status
Simulation time 172869704 ps
CPU time 0.88 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 206996 kb
Host smart-8c8eb684-688d-41e4-83de-635e18eafa60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28311
67376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2831167376
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.320089092
Short name T373
Test name
Test status
Simulation time 266715673 ps
CPU time 1.05 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 207028 kb
Host smart-aeb9a248-a46c-4ea8-a806-2deb4d84581f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=320089092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.320089092
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.4045105693
Short name T649
Test name
Test status
Simulation time 154748156 ps
CPU time 0.83 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 206976 kb
Host smart-0bf3f9ca-5b9b-4c61-acbe-7ac585376852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40451
05693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.4045105693
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1382522727
Short name T23
Test name
Test status
Simulation time 42744186 ps
CPU time 0.68 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 206960 kb
Host smart-4ed13c6c-c565-4935-b461-0c29db3b18ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13825
22727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1382522727
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3728461188
Short name T2714
Test name
Test status
Simulation time 13432793726 ps
CPU time 31.96 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:40 PM PDT 24
Peak memory 219676 kb
Host smart-696569e3-c896-4a28-8455-1b85284c9593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37284
61188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3728461188
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1012772024
Short name T422
Test name
Test status
Simulation time 168589292 ps
CPU time 0.9 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 206972 kb
Host smart-a9641fc2-50ca-4be6-8206-e22bfceb52c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10127
72024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1012772024
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.2948732214
Short name T2508
Test name
Test status
Simulation time 169179743 ps
CPU time 0.87 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 206980 kb
Host smart-417aa0a4-f24a-46dd-8ad8-104b400c6cb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29487
32214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.2948732214
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.433486711
Short name T2280
Test name
Test status
Simulation time 162427017 ps
CPU time 0.92 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 206976 kb
Host smart-68b03caf-b785-47ee-8b2c-c7c1f343c6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43348
6711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.433486711
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.1992801636
Short name T1470
Test name
Test status
Simulation time 178993331 ps
CPU time 0.91 seconds
Started Jul 31 05:45:05 PM PDT 24
Finished Jul 31 05:45:06 PM PDT 24
Peak memory 206988 kb
Host smart-7be99a0f-2f36-41aa-b66c-40e99000092c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19928
01636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1992801636
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.661685387
Short name T1296
Test name
Test status
Simulation time 144873037 ps
CPU time 0.85 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 206968 kb
Host smart-92079146-1c32-47e4-8aac-29ea62ab4da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66168
5387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.661685387
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.803482796
Short name T142
Test name
Test status
Simulation time 160513491 ps
CPU time 0.87 seconds
Started Jul 31 05:45:03 PM PDT 24
Finished Jul 31 05:45:04 PM PDT 24
Peak memory 206948 kb
Host smart-a3931483-989c-4254-8ee4-f10d27393d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80348
2796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.803482796
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.153507105
Short name T1077
Test name
Test status
Simulation time 181790978 ps
CPU time 0.84 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 206968 kb
Host smart-efcb10ea-e351-41bc-838e-a25af58e8c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15350
7105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.153507105
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.4172577190
Short name T395
Test name
Test status
Simulation time 189041263 ps
CPU time 0.97 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 206992 kb
Host smart-e60419c1-3781-47e7-b84f-474193fc9324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41725
77190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.4172577190
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1705777436
Short name T2523
Test name
Test status
Simulation time 3352498041 ps
CPU time 26.39 seconds
Started Jul 31 05:45:10 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 215372 kb
Host smart-f1eca79a-9b45-488f-9d56-891dc4b37adb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1705777436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1705777436
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2279875619
Short name T967
Test name
Test status
Simulation time 148130587 ps
CPU time 0.93 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 206972 kb
Host smart-06f3252f-867e-4bea-88eb-dac5cdd5d164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22798
75619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2279875619
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.82400302
Short name T2496
Test name
Test status
Simulation time 210340745 ps
CPU time 1.19 seconds
Started Jul 31 05:45:04 PM PDT 24
Finished Jul 31 05:45:05 PM PDT 24
Peak memory 207000 kb
Host smart-23c83ed3-e278-4edb-b85f-68d22e0f2798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82400
302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.82400302
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.2834793831
Short name T2019
Test name
Test status
Simulation time 855166677 ps
CPU time 2.12 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:08 PM PDT 24
Peak memory 207016 kb
Host smart-aac2f4ba-b99a-4499-8bec-410f78af12df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28347
93831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.2834793831
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.872571165
Short name T1824
Test name
Test status
Simulation time 6455738571 ps
CPU time 193.98 seconds
Started Jul 31 05:45:10 PM PDT 24
Finished Jul 31 05:48:24 PM PDT 24
Peak memory 215412 kb
Host smart-16e56eef-8fbf-45c8-8f4b-9dc595aa6220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87257
1165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.872571165
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.1712992810
Short name T1003
Test name
Test status
Simulation time 759662166 ps
CPU time 17 seconds
Started Jul 31 05:45:00 PM PDT 24
Finished Jul 31 05:45:17 PM PDT 24
Peak memory 207084 kb
Host smart-7373b907-26b9-4cbc-8e0f-ac7c185598d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712992810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.1712992810
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.2218221469
Short name T2465
Test name
Test status
Simulation time 36849122 ps
CPU time 0.63 seconds
Started Jul 31 05:45:17 PM PDT 24
Finished Jul 31 05:45:17 PM PDT 24
Peak memory 206572 kb
Host smart-f3c6f899-6f7f-4b37-9355-ef0b28e43c45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2218221469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2218221469
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3322284332
Short name T1788
Test name
Test status
Simulation time 4310845867 ps
CPU time 6.16 seconds
Started Jul 31 05:45:09 PM PDT 24
Finished Jul 31 05:45:15 PM PDT 24
Peak memory 207176 kb
Host smart-809e3a51-26c3-48fd-9052-896b0443a13b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322284332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.3322284332
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.2548445586
Short name T2740
Test name
Test status
Simulation time 13486566703 ps
CPU time 18.24 seconds
Started Jul 31 05:45:05 PM PDT 24
Finished Jul 31 05:45:23 PM PDT 24
Peak memory 207232 kb
Host smart-b96c8a5c-9222-49a3-b916-2ff197306f87
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548445586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.2548445586
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.399283131
Short name T1540
Test name
Test status
Simulation time 23378033656 ps
CPU time 27.24 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 207164 kb
Host smart-ae438e71-c5b6-4fd4-900f-281a619bee5c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399283131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_ao
n_wake_resume.399283131
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2355411991
Short name T2683
Test name
Test status
Simulation time 189142603 ps
CPU time 0.95 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:07 PM PDT 24
Peak memory 207028 kb
Host smart-6bf06bcb-f721-4ef1-957c-37990a587055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554
11991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2355411991
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3778596909
Short name T1619
Test name
Test status
Simulation time 158917903 ps
CPU time 0.86 seconds
Started Jul 31 05:45:05 PM PDT 24
Finished Jul 31 05:45:06 PM PDT 24
Peak memory 206948 kb
Host smart-a760e8b3-8dd2-4cdd-be66-1e5f7175a456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37785
96909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3778596909
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2155910363
Short name T1265
Test name
Test status
Simulation time 309209283 ps
CPU time 1.19 seconds
Started Jul 31 05:45:08 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 206996 kb
Host smart-3d744746-a1ff-499e-b692-76fee6e00352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21559
10363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2155910363
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.2532226513
Short name T973
Test name
Test status
Simulation time 586088551 ps
CPU time 1.78 seconds
Started Jul 31 05:45:04 PM PDT 24
Finished Jul 31 05:45:06 PM PDT 24
Peak memory 206980 kb
Host smart-93737aa7-16f8-480b-adec-27a56a1149d1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2532226513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.2532226513
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.30445871
Short name T292
Test name
Test status
Simulation time 12125530355 ps
CPU time 28.6 seconds
Started Jul 31 05:45:09 PM PDT 24
Finished Jul 31 05:45:38 PM PDT 24
Peak memory 207208 kb
Host smart-9fff05a6-2ab4-4f48-bcf9-f041336830dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30445
871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.30445871
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_device_timeout.4070404210
Short name T457
Test name
Test status
Simulation time 4350869745 ps
CPU time 28.96 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 207248 kb
Host smart-628b33ef-dc8b-4d5c-b334-b3e118b8cc4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070404210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.4070404210
Directory /workspace/34.usbdev_device_timeout/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.4023006281
Short name T1895
Test name
Test status
Simulation time 426390389 ps
CPU time 1.43 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 206940 kb
Host smart-12c8da64-6fd0-4941-8b9c-7ad02b6bbd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40230
06281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.4023006281
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.2979677765
Short name T1349
Test name
Test status
Simulation time 165207157 ps
CPU time 0.88 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:45:08 PM PDT 24
Peak memory 206952 kb
Host smart-afd618b9-9696-4239-b7d9-2f4c11b9a79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29796
77765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2979677765
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3900444309
Short name T1420
Test name
Test status
Simulation time 107918496 ps
CPU time 0.78 seconds
Started Jul 31 05:45:10 PM PDT 24
Finished Jul 31 05:45:11 PM PDT 24
Peak memory 206956 kb
Host smart-e389a200-3cce-46be-b0a3-91b1940a7c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39004
44309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3900444309
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.110299320
Short name T136
Test name
Test status
Simulation time 850441846 ps
CPU time 2.29 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 207132 kb
Host smart-14e000ac-8acc-488e-b6f9-e895c44b3470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11029
9320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.110299320
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.962113050
Short name T1643
Test name
Test status
Simulation time 314125191 ps
CPU time 1.88 seconds
Started Jul 31 05:45:07 PM PDT 24
Finished Jul 31 05:45:09 PM PDT 24
Peak memory 207096 kb
Host smart-1d1f126f-19a4-48cb-8504-6610c78b48bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96211
3050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.962113050
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2764902441
Short name T1357
Test name
Test status
Simulation time 202296954 ps
CPU time 1.05 seconds
Started Jul 31 05:45:15 PM PDT 24
Finished Jul 31 05:45:16 PM PDT 24
Peak memory 207052 kb
Host smart-98caec33-ee2c-4183-ae3b-5dfd3519c8f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2764902441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2764902441
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3862095148
Short name T1313
Test name
Test status
Simulation time 192296143 ps
CPU time 0.9 seconds
Started Jul 31 05:45:13 PM PDT 24
Finished Jul 31 05:45:14 PM PDT 24
Peak memory 206944 kb
Host smart-30e11e4b-6998-40c2-a616-31f91d17b5c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38620
95148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3862095148
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2304834170
Short name T609
Test name
Test status
Simulation time 217283677 ps
CPU time 1 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 206984 kb
Host smart-28d9e3d0-29d9-4d62-9ebc-04b4fac54b85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23048
34170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2304834170
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.3599628451
Short name T784
Test name
Test status
Simulation time 8698774881 ps
CPU time 90.57 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:46:42 PM PDT 24
Peak memory 217084 kb
Host smart-49dc9163-bd72-4d29-b8a9-33d0e946b916
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3599628451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.3599628451
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.171242754
Short name T2853
Test name
Test status
Simulation time 4711875220 ps
CPU time 29.96 seconds
Started Jul 31 05:45:20 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 207208 kb
Host smart-afe00d95-3404-41b9-a91f-ef3366319b47
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=171242754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.171242754
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.418702705
Short name T2212
Test name
Test status
Simulation time 204133814 ps
CPU time 1 seconds
Started Jul 31 05:45:12 PM PDT 24
Finished Jul 31 05:45:13 PM PDT 24
Peak memory 206976 kb
Host smart-ea42549f-7ede-46a9-acf6-bf74290ecb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41870
2705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.418702705
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.3493110710
Short name T1904
Test name
Test status
Simulation time 23317552188 ps
CPU time 28.28 seconds
Started Jul 31 05:45:20 PM PDT 24
Finished Jul 31 05:45:49 PM PDT 24
Peak memory 207224 kb
Host smart-d11d8dfe-d6fa-4aac-bdfb-727f00b4a4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34931
10710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.3493110710
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.514965587
Short name T2773
Test name
Test status
Simulation time 3339816387 ps
CPU time 5.11 seconds
Started Jul 31 05:45:12 PM PDT 24
Finished Jul 31 05:45:17 PM PDT 24
Peak memory 207112 kb
Host smart-302026c1-f7a9-4737-a413-908183aafa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51496
5587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.514965587
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.788376755
Short name T320
Test name
Test status
Simulation time 10383834338 ps
CPU time 77.8 seconds
Started Jul 31 05:45:12 PM PDT 24
Finished Jul 31 05:46:30 PM PDT 24
Peak memory 223488 kb
Host smart-f0136ce6-8b06-4e31-8e38-848b1a2ae6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78837
6755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.788376755
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2353544777
Short name T1861
Test name
Test status
Simulation time 3490632462 ps
CPU time 106.11 seconds
Started Jul 31 05:45:13 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 215408 kb
Host smart-3d0882ce-d9fa-45d1-80a8-4741f119422c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2353544777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2353544777
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1481721392
Short name T1938
Test name
Test status
Simulation time 241476123 ps
CPU time 1.02 seconds
Started Jul 31 05:45:20 PM PDT 24
Finished Jul 31 05:45:21 PM PDT 24
Peak memory 207012 kb
Host smart-35efa501-d2dd-44a8-bf55-e12260008bc6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1481721392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1481721392
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.595943491
Short name T802
Test name
Test status
Simulation time 189255387 ps
CPU time 0.9 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 206996 kb
Host smart-01422413-a786-488b-89d3-7f7fea89ff9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59594
3491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.595943491
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.1679295254
Short name T1044
Test name
Test status
Simulation time 6146097758 ps
CPU time 185.37 seconds
Started Jul 31 05:45:10 PM PDT 24
Finished Jul 31 05:48:16 PM PDT 24
Peak memory 215000 kb
Host smart-8b6a583c-9bb1-432f-8587-e7a2c2103cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16792
95254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.1679295254
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.582484207
Short name T159
Test name
Test status
Simulation time 4533528230 ps
CPU time 133.27 seconds
Started Jul 31 05:45:10 PM PDT 24
Finished Jul 31 05:47:24 PM PDT 24
Peak memory 215376 kb
Host smart-8d06fe34-1d8d-430f-b92c-9a9877d40aaf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=582484207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.582484207
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2382030096
Short name T1525
Test name
Test status
Simulation time 157876099 ps
CPU time 0.85 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 207004 kb
Host smart-40a7809b-4698-4b4a-aace-36909778b132
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2382030096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2382030096
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3777811331
Short name T2092
Test name
Test status
Simulation time 149591925 ps
CPU time 0.89 seconds
Started Jul 31 05:45:20 PM PDT 24
Finished Jul 31 05:45:21 PM PDT 24
Peak memory 207020 kb
Host smart-c69c4009-7f45-4894-9993-163f30a9de61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37778
11331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3777811331
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1096025078
Short name T131
Test name
Test status
Simulation time 197223293 ps
CPU time 1 seconds
Started Jul 31 05:45:12 PM PDT 24
Finished Jul 31 05:45:13 PM PDT 24
Peak memory 207004 kb
Host smart-bf7c0cd1-fcb1-4c82-b24e-961506982a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10960
25078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1096025078
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.2866855078
Short name T362
Test name
Test status
Simulation time 174993920 ps
CPU time 0.87 seconds
Started Jul 31 05:45:13 PM PDT 24
Finished Jul 31 05:45:14 PM PDT 24
Peak memory 206996 kb
Host smart-91e9c86a-25aa-4fe3-b086-f58bce9f2ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28668
55078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2866855078
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.2665841320
Short name T2303
Test name
Test status
Simulation time 167710699 ps
CPU time 0.85 seconds
Started Jul 31 05:45:12 PM PDT 24
Finished Jul 31 05:45:13 PM PDT 24
Peak memory 206996 kb
Host smart-d9316fbd-22ab-4cef-aeeb-ae0971e9da37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26658
41320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.2665841320
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.1480957634
Short name T2560
Test name
Test status
Simulation time 158772089 ps
CPU time 0.84 seconds
Started Jul 31 05:45:12 PM PDT 24
Finished Jul 31 05:45:13 PM PDT 24
Peak memory 207000 kb
Host smart-208178e5-013f-4502-8e7f-41f361f9b697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14809
57634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1480957634
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.1474579102
Short name T154
Test name
Test status
Simulation time 248802739 ps
CPU time 0.95 seconds
Started Jul 31 05:45:20 PM PDT 24
Finished Jul 31 05:45:21 PM PDT 24
Peak memory 207020 kb
Host smart-f1c0176d-408e-4d70-8f8d-1a456e4ca21a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14745
79102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.1474579102
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.3306283165
Short name T535
Test name
Test status
Simulation time 280168515 ps
CPU time 1.13 seconds
Started Jul 31 05:45:13 PM PDT 24
Finished Jul 31 05:45:14 PM PDT 24
Peak memory 206968 kb
Host smart-7790fc5b-cdb1-4c7d-a3f9-9cc2ade05922
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3306283165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.3306283165
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.103629337
Short name T2059
Test name
Test status
Simulation time 191736569 ps
CPU time 0.85 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 206980 kb
Host smart-ca9190dc-648c-4099-bf1f-3c6b315bd20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
9337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.103629337
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1058919066
Short name T677
Test name
Test status
Simulation time 39562332 ps
CPU time 0.71 seconds
Started Jul 31 05:45:12 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 206948 kb
Host smart-6dfd0a02-353a-4ad1-8933-4cc4666ff62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10589
19066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1058919066
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.3012020269
Short name T245
Test name
Test status
Simulation time 8575828321 ps
CPU time 24.78 seconds
Started Jul 31 05:45:13 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 215472 kb
Host smart-1796e2ca-5da0-4ac2-b331-3ff8b4dbee19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30120
20269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.3012020269
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3557527277
Short name T624
Test name
Test status
Simulation time 237878919 ps
CPU time 1.01 seconds
Started Jul 31 05:45:10 PM PDT 24
Finished Jul 31 05:45:11 PM PDT 24
Peak memory 206980 kb
Host smart-6a73a814-fde5-43c9-a622-d22a5e836859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35575
27277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3557527277
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3600143607
Short name T2786
Test name
Test status
Simulation time 183217057 ps
CPU time 0.88 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 206984 kb
Host smart-fc66dccb-5273-43be-a6a4-7893267f5d0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36001
43607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3600143607
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1209657165
Short name T717
Test name
Test status
Simulation time 204440454 ps
CPU time 0.93 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 206964 kb
Host smart-a7ddc11a-013e-44d6-b0c1-7935980a5cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12096
57165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1209657165
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.3853491856
Short name T1389
Test name
Test status
Simulation time 204414319 ps
CPU time 0.99 seconds
Started Jul 31 05:45:10 PM PDT 24
Finished Jul 31 05:45:11 PM PDT 24
Peak memory 207040 kb
Host smart-2c9769d2-60c8-49b9-8f0d-dbee93b251de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38534
91856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.3853491856
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.2897092883
Short name T2655
Test name
Test status
Simulation time 141652926 ps
CPU time 0.8 seconds
Started Jul 31 05:45:10 PM PDT 24
Finished Jul 31 05:45:11 PM PDT 24
Peak memory 206968 kb
Host smart-6ce82d6f-a8e5-4ec8-86b6-264cd67ba3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28970
92883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.2897092883
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.2334652365
Short name T964
Test name
Test status
Simulation time 164176522 ps
CPU time 0.86 seconds
Started Jul 31 05:45:12 PM PDT 24
Finished Jul 31 05:45:13 PM PDT 24
Peak memory 206948 kb
Host smart-a2dbe79a-e1dd-4773-b988-75a09d89dba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23346
52365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.2334652365
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1122993080
Short name T1827
Test name
Test status
Simulation time 198472278 ps
CPU time 0.89 seconds
Started Jul 31 05:45:13 PM PDT 24
Finished Jul 31 05:45:14 PM PDT 24
Peak memory 207004 kb
Host smart-9e259309-fc64-4b87-9c7e-126e6927ad9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11229
93080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1122993080
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.877037382
Short name T1997
Test name
Test status
Simulation time 205080019 ps
CPU time 0.97 seconds
Started Jul 31 05:45:11 PM PDT 24
Finished Jul 31 05:45:12 PM PDT 24
Peak memory 206992 kb
Host smart-97de558e-64b2-4e0b-9695-f60d3d454b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87703
7382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.877037382
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3196783016
Short name T700
Test name
Test status
Simulation time 5894324091 ps
CPU time 48.39 seconds
Started Jul 31 05:45:18 PM PDT 24
Finished Jul 31 05:46:06 PM PDT 24
Peak memory 216636 kb
Host smart-09c504b6-def2-4e16-a57d-18dbd6af2637
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3196783016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3196783016
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1716193326
Short name T2082
Test name
Test status
Simulation time 233101212 ps
CPU time 0.98 seconds
Started Jul 31 05:45:21 PM PDT 24
Finished Jul 31 05:45:22 PM PDT 24
Peak memory 206968 kb
Host smart-c3d3a45a-6871-4787-bbee-5df62eba589e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17161
93326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1716193326
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3200949095
Short name T912
Test name
Test status
Simulation time 199564765 ps
CPU time 0.87 seconds
Started Jul 31 05:45:16 PM PDT 24
Finished Jul 31 05:45:17 PM PDT 24
Peak memory 206992 kb
Host smart-63f2c828-2ecc-421e-85cf-7ae14e5fdc55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32009
49095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3200949095
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.1857134978
Short name T896
Test name
Test status
Simulation time 261703281 ps
CPU time 1.05 seconds
Started Jul 31 05:45:18 PM PDT 24
Finished Jul 31 05:45:19 PM PDT 24
Peak memory 206956 kb
Host smart-e1bbe873-3472-4aca-b57e-e5e6f592f7b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18571
34978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1857134978
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1698569202
Short name T1507
Test name
Test status
Simulation time 2947711105 ps
CPU time 29.07 seconds
Started Jul 31 05:45:22 PM PDT 24
Finished Jul 31 05:45:52 PM PDT 24
Peak memory 215364 kb
Host smart-60e2b514-2f4b-40e3-bd45-35fb0a2c9932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16985
69202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1698569202
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.642174607
Short name T2165
Test name
Test status
Simulation time 601067731 ps
CPU time 4.98 seconds
Started Jul 31 05:45:06 PM PDT 24
Finished Jul 31 05:45:11 PM PDT 24
Peak memory 207108 kb
Host smart-2db9b40a-4e2b-481b-81ed-8f5bec73b585
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642174607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_host
_handshake.642174607
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.1400910635
Short name T404
Test name
Test status
Simulation time 48285484 ps
CPU time 0.67 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 207040 kb
Host smart-ff646278-6c14-4386-9761-bc1c593e4d2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1400910635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1400910635
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3956088276
Short name T587
Test name
Test status
Simulation time 4123542511 ps
CPU time 5.61 seconds
Started Jul 31 05:45:18 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 207128 kb
Host smart-5b813127-0659-47b7-a29a-407ae8f63c47
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956088276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.3956088276
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.1495209131
Short name T1359
Test name
Test status
Simulation time 13412299634 ps
CPU time 16.54 seconds
Started Jul 31 05:45:19 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 207208 kb
Host smart-7dc75b06-d7fb-4aed-9180-0c192a688acd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495209131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.1495209131
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2100511364
Short name T10
Test name
Test status
Simulation time 23289421714 ps
CPU time 27.21 seconds
Started Jul 31 05:45:14 PM PDT 24
Finished Jul 31 05:45:41 PM PDT 24
Peak memory 207196 kb
Host smart-a04d8ee0-9289-4111-b462-08e78558e921
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100511364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_resume.2100511364
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.588390428
Short name T333
Test name
Test status
Simulation time 152547555 ps
CPU time 0.88 seconds
Started Jul 31 05:45:18 PM PDT 24
Finished Jul 31 05:45:19 PM PDT 24
Peak memory 206992 kb
Host smart-e626a6b3-92ba-45f0-bd97-c2058a7aa533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58839
0428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.588390428
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1976757023
Short name T2778
Test name
Test status
Simulation time 144906356 ps
CPU time 0.82 seconds
Started Jul 31 05:45:16 PM PDT 24
Finished Jul 31 05:45:17 PM PDT 24
Peak memory 206940 kb
Host smart-6a53d3e1-b464-4c53-843a-f80d359a5817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19767
57023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1976757023
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.3887595391
Short name T1232
Test name
Test status
Simulation time 475795242 ps
CPU time 1.63 seconds
Started Jul 31 05:45:19 PM PDT 24
Finished Jul 31 05:45:20 PM PDT 24
Peak memory 206968 kb
Host smart-4364adf5-c0ac-4043-bc3b-18b4cb818320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38875
95391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.3887595391
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3393227507
Short name T942
Test name
Test status
Simulation time 253222048 ps
CPU time 1.04 seconds
Started Jul 31 05:45:17 PM PDT 24
Finished Jul 31 05:45:18 PM PDT 24
Peak memory 207000 kb
Host smart-4a5f1b15-6681-4376-9ce9-b4d61993b7f4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3393227507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3393227507
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.2844238903
Short name T169
Test name
Test status
Simulation time 9138803635 ps
CPU time 23.75 seconds
Started Jul 31 05:45:18 PM PDT 24
Finished Jul 31 05:45:42 PM PDT 24
Peak memory 207208 kb
Host smart-64fcdd11-045b-47ee-b3b1-937f9a9f4906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28442
38903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.2844238903
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.1732661867
Short name T2868
Test name
Test status
Simulation time 307084698 ps
CPU time 4.37 seconds
Started Jul 31 05:45:17 PM PDT 24
Finished Jul 31 05:45:21 PM PDT 24
Peak memory 207064 kb
Host smart-3c6fac5f-8e9b-4d17-b27b-b9d92891b982
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732661867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.1732661867
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.3173980722
Short name T1224
Test name
Test status
Simulation time 382332497 ps
CPU time 1.49 seconds
Started Jul 31 05:45:17 PM PDT 24
Finished Jul 31 05:45:19 PM PDT 24
Peak memory 206972 kb
Host smart-1b64e7a4-f8cf-4170-9006-9c3f182bc4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31739
80722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.3173980722
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1456914620
Short name T2177
Test name
Test status
Simulation time 153095052 ps
CPU time 0.91 seconds
Started Jul 31 05:45:22 PM PDT 24
Finished Jul 31 05:45:23 PM PDT 24
Peak memory 206956 kb
Host smart-ff372e83-8070-428d-be38-4e775e6463ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14569
14620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1456914620
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1399742547
Short name T340
Test name
Test status
Simulation time 47090409 ps
CPU time 0.7 seconds
Started Jul 31 05:45:14 PM PDT 24
Finished Jul 31 05:45:15 PM PDT 24
Peak memory 206888 kb
Host smart-ad1d3326-352c-44b6-9944-7f87aa8dbcb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13997
42547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1399742547
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3172429061
Short name T1362
Test name
Test status
Simulation time 923804001 ps
CPU time 2.43 seconds
Started Jul 31 05:45:18 PM PDT 24
Finished Jul 31 05:45:20 PM PDT 24
Peak memory 207108 kb
Host smart-efabb209-575b-474d-a86d-51608f6b9b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31724
29061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3172429061
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1488508185
Short name T2215
Test name
Test status
Simulation time 392689624 ps
CPU time 2.67 seconds
Started Jul 31 05:45:18 PM PDT 24
Finished Jul 31 05:45:21 PM PDT 24
Peak memory 207004 kb
Host smart-b1f40766-12b3-419f-844c-cb1dc0127556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14885
08185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1488508185
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1412859279
Short name T339
Test name
Test status
Simulation time 195187624 ps
CPU time 1.01 seconds
Started Jul 31 05:45:17 PM PDT 24
Finished Jul 31 05:45:18 PM PDT 24
Peak memory 215200 kb
Host smart-75e8b1f2-cd13-4c5d-ad03-686b7289ecd6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1412859279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1412859279
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1070033529
Short name T522
Test name
Test status
Simulation time 137672604 ps
CPU time 0.84 seconds
Started Jul 31 05:45:22 PM PDT 24
Finished Jul 31 05:45:23 PM PDT 24
Peak memory 206964 kb
Host smart-f356415c-c5f0-406f-b51a-7482427036c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10700
33529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1070033529
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2361645146
Short name T972
Test name
Test status
Simulation time 262070508 ps
CPU time 1.09 seconds
Started Jul 31 05:45:17 PM PDT 24
Finished Jul 31 05:45:18 PM PDT 24
Peak memory 206992 kb
Host smart-da28eec6-a5fd-4f29-8786-dba4ce7ffbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23616
45146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2361645146
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3785581608
Short name T2170
Test name
Test status
Simulation time 5664377003 ps
CPU time 45.18 seconds
Started Jul 31 05:45:16 PM PDT 24
Finished Jul 31 05:46:01 PM PDT 24
Peak memory 215444 kb
Host smart-3d81582c-c00a-47e4-983f-cea548f01646
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3785581608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3785581608
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.1307429959
Short name T1855
Test name
Test status
Simulation time 11365143666 ps
CPU time 77.55 seconds
Started Jul 31 05:45:19 PM PDT 24
Finished Jul 31 05:46:37 PM PDT 24
Peak memory 207196 kb
Host smart-098745e0-4f15-47e3-bfa3-232c6e3f020e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1307429959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.1307429959
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.4183730704
Short name T2568
Test name
Test status
Simulation time 198536422 ps
CPU time 0.89 seconds
Started Jul 31 05:45:17 PM PDT 24
Finished Jul 31 05:45:18 PM PDT 24
Peak memory 207004 kb
Host smart-395f5032-5d6e-4b04-9a64-46786d0d86f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41837
30704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.4183730704
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.4054658755
Short name T1567
Test name
Test status
Simulation time 23285276922 ps
CPU time 27.68 seconds
Started Jul 31 05:45:18 PM PDT 24
Finished Jul 31 05:45:46 PM PDT 24
Peak memory 207264 kb
Host smart-7b780f87-d67b-4d11-8c75-49c4e5090367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40546
58755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.4054658755
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.3926422469
Short name T2588
Test name
Test status
Simulation time 3365107442 ps
CPU time 5.32 seconds
Started Jul 31 05:45:16 PM PDT 24
Finished Jul 31 05:45:21 PM PDT 24
Peak memory 207124 kb
Host smart-cce6db4e-3646-482b-adf1-f24b6064e27c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39264
22469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.3926422469
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2559710720
Short name T1499
Test name
Test status
Simulation time 8588179161 ps
CPU time 87.4 seconds
Started Jul 31 05:45:20 PM PDT 24
Finished Jul 31 05:46:47 PM PDT 24
Peak memory 217308 kb
Host smart-358025d4-95b6-4263-a117-0ab858ccfead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25597
10720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2559710720
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.198657043
Short name T1954
Test name
Test status
Simulation time 7028081151 ps
CPU time 220.6 seconds
Started Jul 31 05:45:26 PM PDT 24
Finished Jul 31 05:49:07 PM PDT 24
Peak memory 215432 kb
Host smart-c9c781a2-47be-424c-81d6-63788617f422
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=198657043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.198657043
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3861416963
Short name T2033
Test name
Test status
Simulation time 279423287 ps
CPU time 1.13 seconds
Started Jul 31 05:45:20 PM PDT 24
Finished Jul 31 05:45:22 PM PDT 24
Peak memory 207012 kb
Host smart-5d9de851-a02c-4658-9a22-899eeeb39590
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3861416963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3861416963
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1032130857
Short name T501
Test name
Test status
Simulation time 199449426 ps
CPU time 0.94 seconds
Started Jul 31 05:45:24 PM PDT 24
Finished Jul 31 05:45:25 PM PDT 24
Peak memory 207036 kb
Host smart-50835879-7d9a-4f65-90bc-1b3d69d11477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10321
30857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1032130857
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.1170453420
Short name T2481
Test name
Test status
Simulation time 3726778057 ps
CPU time 112.44 seconds
Started Jul 31 05:45:23 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 215396 kb
Host smart-67b7fcb9-dd54-4f19-b2cb-25aefb9f2153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11704
53420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.1170453420
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2461444323
Short name T1595
Test name
Test status
Simulation time 6798332196 ps
CPU time 69.25 seconds
Started Jul 31 05:45:24 PM PDT 24
Finished Jul 31 05:46:33 PM PDT 24
Peak memory 207240 kb
Host smart-493d3b64-f90e-4907-8e32-4485ba1639b2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2461444323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2461444323
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3051208122
Short name T2228
Test name
Test status
Simulation time 208430657 ps
CPU time 0.95 seconds
Started Jul 31 05:45:22 PM PDT 24
Finished Jul 31 05:45:23 PM PDT 24
Peak memory 206984 kb
Host smart-da3ffb43-d26b-4cd3-94ce-50b6f3b726ca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3051208122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3051208122
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.4198247323
Short name T2787
Test name
Test status
Simulation time 151121238 ps
CPU time 0.83 seconds
Started Jul 31 05:45:27 PM PDT 24
Finished Jul 31 05:45:28 PM PDT 24
Peak memory 207052 kb
Host smart-88859667-6631-4ec3-80af-60612c91732d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41982
47323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.4198247323
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2577496701
Short name T106
Test name
Test status
Simulation time 202366317 ps
CPU time 1.01 seconds
Started Jul 31 05:45:22 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 207020 kb
Host smart-3784a0b2-4d1d-4beb-881c-baba9cad907f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25774
96701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2577496701
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.647231554
Short name T1427
Test name
Test status
Simulation time 181606108 ps
CPU time 0.92 seconds
Started Jul 31 05:45:23 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 206980 kb
Host smart-6aa82946-5cb3-46ff-9af3-0699892f8583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64723
1554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.647231554
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1726793286
Short name T2728
Test name
Test status
Simulation time 194953926 ps
CPU time 0.96 seconds
Started Jul 31 05:45:22 PM PDT 24
Finished Jul 31 05:45:23 PM PDT 24
Peak memory 206976 kb
Host smart-da0e0b7d-6f0a-45a5-af8a-96cdb33553e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17267
93286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1726793286
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3748878625
Short name T2032
Test name
Test status
Simulation time 171067713 ps
CPU time 0.91 seconds
Started Jul 31 05:45:23 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 206992 kb
Host smart-b9f54c50-9ce5-40f2-bdeb-7154fc4c06cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37488
78625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3748878625
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3580009200
Short name T2545
Test name
Test status
Simulation time 213699743 ps
CPU time 0.92 seconds
Started Jul 31 05:45:22 PM PDT 24
Finished Jul 31 05:45:23 PM PDT 24
Peak memory 206996 kb
Host smart-593b84e0-67a4-4ebb-8cb3-c7046e473f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35800
09200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3580009200
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.4267320209
Short name T2797
Test name
Test status
Simulation time 187009188 ps
CPU time 0.92 seconds
Started Jul 31 05:45:23 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 207024 kb
Host smart-f130bd8d-d2b5-485f-844a-bb333478dec9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4267320209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.4267320209
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.640128090
Short name T1019
Test name
Test status
Simulation time 149517559 ps
CPU time 0.87 seconds
Started Jul 31 05:45:23 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 206952 kb
Host smart-51f48de1-5566-4d09-87e3-5704173d31b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64012
8090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.640128090
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.826832891
Short name T1303
Test name
Test status
Simulation time 67054903 ps
CPU time 0.75 seconds
Started Jul 31 05:45:21 PM PDT 24
Finished Jul 31 05:45:21 PM PDT 24
Peak memory 206932 kb
Host smart-d666620f-6688-4438-ae4c-fd19396f8293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82683
2891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.826832891
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.83396860
Short name T2452
Test name
Test status
Simulation time 9276520879 ps
CPU time 23.7 seconds
Started Jul 31 05:45:21 PM PDT 24
Finished Jul 31 05:45:45 PM PDT 24
Peak memory 215448 kb
Host smart-f7076d3d-ffb4-46b5-b564-a68a02c433d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83396
860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.83396860
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3760529475
Short name T956
Test name
Test status
Simulation time 181846723 ps
CPU time 0.91 seconds
Started Jul 31 05:45:22 PM PDT 24
Finished Jul 31 05:45:23 PM PDT 24
Peak memory 206996 kb
Host smart-31800092-2966-41b1-8e8c-c321147139ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37605
29475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3760529475
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.4208738436
Short name T2782
Test name
Test status
Simulation time 268411715 ps
CPU time 1.05 seconds
Started Jul 31 05:45:20 PM PDT 24
Finished Jul 31 05:45:22 PM PDT 24
Peak memory 206960 kb
Host smart-0d557055-2949-4a6a-8030-63c68029aeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42087
38436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.4208738436
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.4272156340
Short name T2712
Test name
Test status
Simulation time 216406697 ps
CPU time 0.98 seconds
Started Jul 31 05:45:26 PM PDT 24
Finished Jul 31 05:45:27 PM PDT 24
Peak memory 206984 kb
Host smart-c8583e1c-67cf-4b3b-bafe-2e9ccc3998dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42721
56340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.4272156340
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.7971709
Short name T2867
Test name
Test status
Simulation time 196223292 ps
CPU time 0.92 seconds
Started Jul 31 05:45:24 PM PDT 24
Finished Jul 31 05:45:25 PM PDT 24
Peak memory 207032 kb
Host smart-f976e46a-5ac9-48d5-bb2f-191445a0ff44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79717
09 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.7971709
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2028063403
Short name T1400
Test name
Test status
Simulation time 224502332 ps
CPU time 0.96 seconds
Started Jul 31 05:45:23 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 206968 kb
Host smart-dda5382b-3b17-4eb3-9dad-4ee1114c9106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20280
63403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2028063403
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.3222870562
Short name T1860
Test name
Test status
Simulation time 212997854 ps
CPU time 0.92 seconds
Started Jul 31 05:45:23 PM PDT 24
Finished Jul 31 05:45:24 PM PDT 24
Peak memory 206964 kb
Host smart-676ae6e5-2ee5-447d-845e-6a8dfa79043b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32228
70562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3222870562
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3719479144
Short name T2091
Test name
Test status
Simulation time 149240551 ps
CPU time 0.85 seconds
Started Jul 31 05:45:24 PM PDT 24
Finished Jul 31 05:45:25 PM PDT 24
Peak memory 206924 kb
Host smart-fb2aa3a0-a627-44d6-be1e-5631e5897a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
79144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3719479144
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1588194091
Short name T2403
Test name
Test status
Simulation time 251556558 ps
CPU time 1.01 seconds
Started Jul 31 05:45:26 PM PDT 24
Finished Jul 31 05:45:28 PM PDT 24
Peak memory 206608 kb
Host smart-96c348c5-1490-4c42-b1f9-cf927eae5d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15881
94091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1588194091
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1954912842
Short name T1757
Test name
Test status
Simulation time 5553981390 ps
CPU time 168.93 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:48:18 PM PDT 24
Peak memory 215384 kb
Host smart-a446f6b3-702d-4523-93b0-58d28677977f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1954912842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1954912842
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.3980502939
Short name T1073
Test name
Test status
Simulation time 148647820 ps
CPU time 0.86 seconds
Started Jul 31 05:45:30 PM PDT 24
Finished Jul 31 05:45:31 PM PDT 24
Peak memory 207040 kb
Host smart-46d4b781-be44-41ba-b62d-f9ccb6d0d29b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39805
02939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.3980502939
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.1428967559
Short name T1345
Test name
Test status
Simulation time 189967338 ps
CPU time 0.92 seconds
Started Jul 31 05:45:26 PM PDT 24
Finished Jul 31 05:45:27 PM PDT 24
Peak memory 206980 kb
Host smart-b54f663b-21ae-4c92-93ad-640a276d697d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14289
67559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.1428967559
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2998575467
Short name T566
Test name
Test status
Simulation time 753268732 ps
CPU time 2.1 seconds
Started Jul 31 05:45:32 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 206960 kb
Host smart-7f0c8a1c-b634-4e8e-9610-d3b408efb6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29985
75467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2998575467
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2986469966
Short name T619
Test name
Test status
Simulation time 3394927148 ps
CPU time 105.18 seconds
Started Jul 31 05:45:30 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 215372 kb
Host smart-d0bd083b-d55a-4edc-86a6-7c1d93bfe824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29864
69966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2986469966
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.3623957977
Short name T2480
Test name
Test status
Simulation time 2555904563 ps
CPU time 18.51 seconds
Started Jul 31 05:45:17 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 207240 kb
Host smart-05f0fbda-d752-4952-9eef-7f23dbfcba0f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623957977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.3623957977
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2393567650
Short name T900
Test name
Test status
Simulation time 36187389 ps
CPU time 0.72 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 206996 kb
Host smart-1b8a81fb-80ac-4067-a2ee-b099dedd15aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2393567650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2393567650
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.2838649232
Short name T466
Test name
Test status
Simulation time 4210920626 ps
CPU time 5.94 seconds
Started Jul 31 05:45:30 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 207132 kb
Host smart-83b4b1f9-7aa1-46a2-82f0-20019c283084
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838649232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_disconnect.2838649232
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2950574164
Short name T1274
Test name
Test status
Simulation time 13332388980 ps
CPU time 19.96 seconds
Started Jul 31 05:45:32 PM PDT 24
Finished Jul 31 05:45:52 PM PDT 24
Peak memory 207232 kb
Host smart-3a77ed8b-6295-4d3f-911c-42af01a785c5
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950574164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2950574164
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.2957574185
Short name T1147
Test name
Test status
Simulation time 23352983479 ps
CPU time 33.64 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:46:02 PM PDT 24
Peak memory 207216 kb
Host smart-9d56b2a6-4815-47d4-a2e2-ea0fb3461725
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957574185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.2957574185
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3429834747
Short name T796
Test name
Test status
Simulation time 178929797 ps
CPU time 0.93 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 206992 kb
Host smart-5d8c84ca-0c38-43c4-b3c9-42092be5e5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34298
34747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3429834747
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3786049824
Short name T172
Test name
Test status
Simulation time 157391951 ps
CPU time 0.88 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 206964 kb
Host smart-09a61745-1980-4826-8e04-db165b617ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37860
49824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3786049824
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.971158831
Short name T1171
Test name
Test status
Simulation time 411472763 ps
CPU time 1.61 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:45:38 PM PDT 24
Peak memory 206976 kb
Host smart-f2681a79-06d2-4e88-a965-fa9db4789ca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97115
8831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.971158831
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2102869829
Short name T906
Test name
Test status
Simulation time 1219070901 ps
CPU time 3.06 seconds
Started Jul 31 05:45:27 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 207104 kb
Host smart-9bf5ac23-6605-436c-8651-06dfaa71ad12
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2102869829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2102869829
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2010830750
Short name T1739
Test name
Test status
Simulation time 15609136701 ps
CPU time 34.06 seconds
Started Jul 31 05:45:31 PM PDT 24
Finished Jul 31 05:46:05 PM PDT 24
Peak memory 207204 kb
Host smart-e3f43b8f-7b98-4122-b88c-4de3ec9d58fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20108
30750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2010830750
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_device_timeout.2652165505
Short name T1883
Test name
Test status
Simulation time 4914513179 ps
CPU time 35.58 seconds
Started Jul 31 05:45:32 PM PDT 24
Finished Jul 31 05:46:08 PM PDT 24
Peak memory 207244 kb
Host smart-a9104933-ec0c-4059-a4cd-653a1c2edcd2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652165505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.2652165505
Directory /workspace/36.usbdev_device_timeout/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.1498743305
Short name T280
Test name
Test status
Simulation time 467179701 ps
CPU time 1.64 seconds
Started Jul 31 05:45:28 PM PDT 24
Finished Jul 31 05:45:29 PM PDT 24
Peak memory 206952 kb
Host smart-3971bfea-8b90-4b6a-9383-cbd57b4be6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14987
43305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.1498743305
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2287349758
Short name T2814
Test name
Test status
Simulation time 161310600 ps
CPU time 0.86 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 206960 kb
Host smart-1ab4b512-4ac6-408e-8631-2b8173e1c526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22873
49758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2287349758
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1308983539
Short name T1658
Test name
Test status
Simulation time 36428695 ps
CPU time 0.71 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 206964 kb
Host smart-81bf6be8-5415-4368-81df-47ec07ecef55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13089
83539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1308983539
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.519615483
Short name T2793
Test name
Test status
Simulation time 954366487 ps
CPU time 3.05 seconds
Started Jul 31 05:45:28 PM PDT 24
Finished Jul 31 05:45:31 PM PDT 24
Peak memory 207116 kb
Host smart-0fd135bf-d162-46fc-a0dc-40f8e1a3e87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51961
5483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.519615483
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.3650228713
Short name T1020
Test name
Test status
Simulation time 164710984 ps
CPU time 1.81 seconds
Started Jul 31 05:45:32 PM PDT 24
Finished Jul 31 05:45:34 PM PDT 24
Peak memory 207044 kb
Host smart-45141c2c-d536-4237-a3c8-ca87835ee832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36502
28713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.3650228713
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.822642677
Short name T874
Test name
Test status
Simulation time 237381133 ps
CPU time 1.01 seconds
Started Jul 31 05:45:27 PM PDT 24
Finished Jul 31 05:45:28 PM PDT 24
Peak memory 207036 kb
Host smart-a8c520fc-ed63-4292-a831-2d55b879e0de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=822642677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.822642677
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.2411469244
Short name T1242
Test name
Test status
Simulation time 158591888 ps
CPU time 0.84 seconds
Started Jul 31 05:45:30 PM PDT 24
Finished Jul 31 05:45:31 PM PDT 24
Peak memory 206968 kb
Host smart-292275a0-67ca-4afa-a53b-53dc06031d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24114
69244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.2411469244
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3719080915
Short name T1605
Test name
Test status
Simulation time 191295770 ps
CPU time 0.94 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 207020 kb
Host smart-00beb374-a660-4a58-aaf0-0c5b05ea6bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190
80915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3719080915
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.55992668
Short name T739
Test name
Test status
Simulation time 6360363548 ps
CPU time 46.17 seconds
Started Jul 31 05:45:30 PM PDT 24
Finished Jul 31 05:46:16 PM PDT 24
Peak memory 215348 kb
Host smart-3d189fa9-54b6-4bd0-acb1-5649e5d5944d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=55992668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.55992668
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2996139507
Short name T1286
Test name
Test status
Simulation time 3740799992 ps
CPU time 22.9 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:52 PM PDT 24
Peak memory 207188 kb
Host smart-c1c972c5-8f4c-4193-935b-027ec376c337
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2996139507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2996139507
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.4080539379
Short name T790
Test name
Test status
Simulation time 172110740 ps
CPU time 0.93 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 206968 kb
Host smart-cf47b978-4954-4deb-98d7-7548d5ddf8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40805
39379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.4080539379
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.831684077
Short name T2341
Test name
Test status
Simulation time 23382734052 ps
CPU time 27.44 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:57 PM PDT 24
Peak memory 207184 kb
Host smart-2d2e0c40-f137-451b-877a-36e98103becc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83168
4077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.831684077
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2963541089
Short name T1165
Test name
Test status
Simulation time 3407574435 ps
CPU time 5.62 seconds
Started Jul 31 05:45:27 PM PDT 24
Finished Jul 31 05:45:33 PM PDT 24
Peak memory 207104 kb
Host smart-c1598566-76a3-44ac-a91d-6c90591a52ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29635
41089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2963541089
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.1686966154
Short name T1067
Test name
Test status
Simulation time 7806393373 ps
CPU time 59.09 seconds
Started Jul 31 05:45:27 PM PDT 24
Finished Jul 31 05:46:26 PM PDT 24
Peak memory 217428 kb
Host smart-bfd64a06-bcc9-4eb6-b51b-157c37d530a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869
66154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.1686966154
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1883580073
Short name T2226
Test name
Test status
Simulation time 4257725472 ps
CPU time 42.07 seconds
Started Jul 31 05:45:27 PM PDT 24
Finished Jul 31 05:46:09 PM PDT 24
Peak memory 207212 kb
Host smart-c03e0406-1051-42ee-a84a-2ed14e8b2bd5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1883580073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1883580073
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.3444703549
Short name T1034
Test name
Test status
Simulation time 236022012 ps
CPU time 0.99 seconds
Started Jul 31 05:45:32 PM PDT 24
Finished Jul 31 05:45:33 PM PDT 24
Peak memory 207000 kb
Host smart-38041395-54c6-43cc-bdd7-68a04b432058
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3444703549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3444703549
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.2092652267
Short name T2674
Test name
Test status
Simulation time 260120328 ps
CPU time 0.97 seconds
Started Jul 31 05:45:30 PM PDT 24
Finished Jul 31 05:45:32 PM PDT 24
Peak memory 206992 kb
Host smart-3a45a326-0b55-4024-b994-72872ce208c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20926
52267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.2092652267
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2840753212
Short name T1462
Test name
Test status
Simulation time 7079288722 ps
CPU time 77.06 seconds
Started Jul 31 05:45:25 PM PDT 24
Finished Jul 31 05:46:43 PM PDT 24
Peak memory 216776 kb
Host smart-367d6c6d-130d-4c25-a317-18775c35427c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28407
53212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2840753212
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1718117302
Short name T1256
Test name
Test status
Simulation time 4243771734 ps
CPU time 122.82 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 215428 kb
Host smart-f01d52e7-9bf8-4652-8b74-59c82efe18ac
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1718117302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1718117302
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.511830887
Short name T1856
Test name
Test status
Simulation time 157041973 ps
CPU time 0.86 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:45:34 PM PDT 24
Peak memory 207000 kb
Host smart-ba6a6854-fde6-47d0-afad-6eb24423c46c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=511830887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.511830887
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1991094151
Short name T1097
Test name
Test status
Simulation time 184582018 ps
CPU time 0.9 seconds
Started Jul 31 05:45:28 PM PDT 24
Finished Jul 31 05:45:29 PM PDT 24
Peak memory 207016 kb
Host smart-ab0e9dad-ee46-4363-82d6-96cfc03be327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19910
94151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1991094151
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.972973593
Short name T2817
Test name
Test status
Simulation time 230114658 ps
CPU time 0.98 seconds
Started Jul 31 05:45:28 PM PDT 24
Finished Jul 31 05:45:29 PM PDT 24
Peak memory 206996 kb
Host smart-56b33c7b-1563-46f9-be8f-4f02a7f5a3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97297
3593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.972973593
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.3090589166
Short name T3
Test name
Test status
Simulation time 167332198 ps
CPU time 0.91 seconds
Started Jul 31 05:45:28 PM PDT 24
Finished Jul 31 05:45:29 PM PDT 24
Peak memory 206992 kb
Host smart-f10104d2-588b-475f-99fe-726bd7f596f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30905
89166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3090589166
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1111088638
Short name T2689
Test name
Test status
Simulation time 212532201 ps
CPU time 0.99 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 206992 kb
Host smart-aa2b2133-eaa4-451d-bee0-8c8a04907c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11110
88638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1111088638
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3682543554
Short name T1093
Test name
Test status
Simulation time 161101383 ps
CPU time 0.86 seconds
Started Jul 31 05:45:29 PM PDT 24
Finished Jul 31 05:45:30 PM PDT 24
Peak memory 206980 kb
Host smart-62a4f372-ff68-4679-a668-aecc1438547b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36825
43554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3682543554
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2844145547
Short name T1416
Test name
Test status
Simulation time 163656417 ps
CPU time 0.84 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 206992 kb
Host smart-eb7b3083-bcdf-4734-bcc7-491860c55bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28441
45547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2844145547
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.584694288
Short name T1775
Test name
Test status
Simulation time 211770237 ps
CPU time 1.04 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 207000 kb
Host smart-b9be6c4b-78e1-4b08-a393-fcd9b2c54312
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=584694288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.584694288
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1102854927
Short name T2587
Test name
Test status
Simulation time 139972006 ps
CPU time 0.84 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 206960 kb
Host smart-623a07f7-39b3-4d37-9aa2-1fb0b128eaed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11028
54927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1102854927
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.1518276931
Short name T564
Test name
Test status
Simulation time 38523913 ps
CPU time 0.68 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:45:34 PM PDT 24
Peak memory 206960 kb
Host smart-d6224791-2b14-4b6e-93e0-e21539346462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15182
76931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.1518276931
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3528025969
Short name T2576
Test name
Test status
Simulation time 6366460468 ps
CPU time 15.73 seconds
Started Jul 31 05:45:35 PM PDT 24
Finished Jul 31 05:45:51 PM PDT 24
Peak memory 215488 kb
Host smart-e4afc984-d94e-4ab6-8037-29afa695cb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280
25969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3528025969
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.1326032053
Short name T1383
Test name
Test status
Simulation time 195348936 ps
CPU time 0.96 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 206972 kb
Host smart-fee0af29-744c-4acc-be9d-7bfe53190d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13260
32053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.1326032053
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.1801111705
Short name T2281
Test name
Test status
Simulation time 242781572 ps
CPU time 1.03 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:45:34 PM PDT 24
Peak memory 206968 kb
Host smart-4057b590-0cfb-4992-af60-dabaf5395113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18011
11705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1801111705
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.4045287052
Short name T2389
Test name
Test status
Simulation time 254819727 ps
CPU time 1.01 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 206980 kb
Host smart-78a7d00e-bf88-4b3d-ae48-30ee02494770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40452
87052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.4045287052
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3979199247
Short name T91
Test name
Test status
Simulation time 180737750 ps
CPU time 0.94 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 206996 kb
Host smart-911aa832-272a-4fbf-984b-f27b7edcb415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39791
99247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3979199247
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3831934508
Short name T1239
Test name
Test status
Simulation time 202807255 ps
CPU time 0.87 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 206940 kb
Host smart-ddbef651-da57-4eeb-8aca-614465394f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38319
34508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3831934508
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.1698628736
Short name T2763
Test name
Test status
Simulation time 148810983 ps
CPU time 0.87 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 206948 kb
Host smart-ead1c5a6-66b3-4e68-8c61-2bb456177711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16986
28736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.1698628736
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.545170294
Short name T826
Test name
Test status
Simulation time 216838755 ps
CPU time 0.97 seconds
Started Jul 31 05:45:35 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 207004 kb
Host smart-62668e30-d549-4d48-b251-c8ebe4359f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54517
0294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.545170294
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.1463450736
Short name T1893
Test name
Test status
Simulation time 206540039 ps
CPU time 0.96 seconds
Started Jul 31 05:45:32 PM PDT 24
Finished Jul 31 05:45:33 PM PDT 24
Peak memory 207008 kb
Host smart-9749117f-8fe1-49c3-8abb-4b57c988cdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14634
50736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.1463450736
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.1723442655
Short name T4
Test name
Test status
Simulation time 4326213417 ps
CPU time 44.01 seconds
Started Jul 31 05:45:39 PM PDT 24
Finished Jul 31 05:46:24 PM PDT 24
Peak memory 216620 kb
Host smart-23f84574-996e-414e-9597-fa9b623a5609
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1723442655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.1723442655
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1875416634
Short name T1493
Test name
Test status
Simulation time 150411971 ps
CPU time 0.85 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 207020 kb
Host smart-36ecd6bd-379a-4628-b72a-50bd6808ce10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18754
16634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1875416634
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.703325314
Short name T288
Test name
Test status
Simulation time 147834478 ps
CPU time 0.81 seconds
Started Jul 31 05:45:31 PM PDT 24
Finished Jul 31 05:45:32 PM PDT 24
Peak memory 206948 kb
Host smart-9879b838-cfeb-4e1d-b32e-f37ff544e84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70332
5314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.703325314
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.2519502042
Short name T2275
Test name
Test status
Simulation time 1040935045 ps
CPU time 2.51 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 207104 kb
Host smart-19e616bf-7d52-439c-a653-a14a673f5d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25195
02042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.2519502042
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.4102502844
Short name T1189
Test name
Test status
Simulation time 6822964089 ps
CPU time 70.74 seconds
Started Jul 31 05:45:38 PM PDT 24
Finished Jul 31 05:46:49 PM PDT 24
Peak memory 207280 kb
Host smart-9db91239-daed-4255-8041-e24d27055aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41025
02844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.4102502844
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.2129835351
Short name T2650
Test name
Test status
Simulation time 1300242723 ps
CPU time 30.22 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:46:03 PM PDT 24
Peak memory 207092 kb
Host smart-57379800-8fe6-4443-9650-45a772fca3f8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129835351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.2129835351
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3400473945
Short name T1410
Test name
Test status
Simulation time 46934898 ps
CPU time 0.7 seconds
Started Jul 31 05:45:47 PM PDT 24
Finished Jul 31 05:45:48 PM PDT 24
Peak memory 207016 kb
Host smart-1a5afb7b-67d4-4562-8cd8-f43822f18fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3400473945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3400473945
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1691208324
Short name T1756
Test name
Test status
Simulation time 3738198198 ps
CPU time 5.69 seconds
Started Jul 31 05:45:30 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 207160 kb
Host smart-9d1ae4b8-aa60-4895-8f05-0cc407605f54
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691208324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.1691208324
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.3222594012
Short name T2306
Test name
Test status
Simulation time 13302969708 ps
CPU time 15.74 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:45:49 PM PDT 24
Peak memory 207208 kb
Host smart-957ff4a8-1347-4c4a-84c2-87f2177f13eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222594012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.3222594012
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.845324073
Short name T2443
Test name
Test status
Simulation time 23328702845 ps
CPU time 29.81 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:46:03 PM PDT 24
Peak memory 207192 kb
Host smart-6027a114-0345-4ac9-b6c7-c87e24d4ca5b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845324073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_resume.845324073
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.1668809724
Short name T661
Test name
Test status
Simulation time 147509422 ps
CPU time 0.89 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 207012 kb
Host smart-e82ace00-7e61-40da-bd97-9ba580557909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16688
09724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1668809724
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.804608731
Short name T843
Test name
Test status
Simulation time 151232183 ps
CPU time 0.78 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 206964 kb
Host smart-852031f0-37f1-4131-b28b-bd93c9648953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80460
8731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.804608731
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.127268316
Short name T1471
Test name
Test status
Simulation time 247227362 ps
CPU time 1.16 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 206992 kb
Host smart-d3d1e5a3-ea76-49f2-9747-7e5916e3829a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
8316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.127268316
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.1746142318
Short name T1640
Test name
Test status
Simulation time 525137493 ps
CPU time 1.64 seconds
Started Jul 31 05:45:38 PM PDT 24
Finished Jul 31 05:45:39 PM PDT 24
Peak memory 207032 kb
Host smart-d00fac2a-404b-4a70-ae4d-f8a90057c269
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1746142318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1746142318
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_timeout.4032397487
Short name T2448
Test name
Test status
Simulation time 2244721581 ps
CPU time 14.45 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:45:48 PM PDT 24
Peak memory 207148 kb
Host smart-908056b4-ae26-4a1b-a4b1-9c15133369c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032397487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.4032397487
Directory /workspace/37.usbdev_device_timeout/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.1335108355
Short name T2672
Test name
Test status
Simulation time 310449046 ps
CPU time 1.31 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 206952 kb
Host smart-e037d97c-0e09-411b-94cd-762b331860a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13351
08355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.1335108355
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2809640024
Short name T1469
Test name
Test status
Simulation time 147268285 ps
CPU time 0.89 seconds
Started Jul 31 05:45:44 PM PDT 24
Finished Jul 31 05:45:45 PM PDT 24
Peak memory 207012 kb
Host smart-b20ae227-c33e-425c-8da6-c253e0052853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28096
40024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2809640024
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2564284149
Short name T1095
Test name
Test status
Simulation time 35060373 ps
CPU time 0.72 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:35 PM PDT 24
Peak memory 206952 kb
Host smart-b62ebc81-a510-4417-878f-57c07803ea56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25642
84149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2564284149
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.3527490093
Short name T1989
Test name
Test status
Simulation time 877618379 ps
CPU time 2.27 seconds
Started Jul 31 05:45:32 PM PDT 24
Finished Jul 31 05:45:34 PM PDT 24
Peak memory 207056 kb
Host smart-41eaf221-4014-4cde-ab91-f5162022d426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35274
90093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.3527490093
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1801014326
Short name T2066
Test name
Test status
Simulation time 213495161 ps
CPU time 1.38 seconds
Started Jul 31 05:45:37 PM PDT 24
Finished Jul 31 05:45:39 PM PDT 24
Peak memory 207136 kb
Host smart-10fd4840-30df-4093-bbd6-9a033d9957ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18010
14326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1801014326
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2290247638
Short name T2500
Test name
Test status
Simulation time 192208731 ps
CPU time 0.97 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:45:34 PM PDT 24
Peak memory 215308 kb
Host smart-c0e6ca73-c08f-4625-bd8c-61228bf47fdc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2290247638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2290247638
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.3362746966
Short name T588
Test name
Test status
Simulation time 140825938 ps
CPU time 0.81 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 206952 kb
Host smart-3fec9f27-eb9b-4de6-86de-8cf03018a686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33627
46966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3362746966
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.518514465
Short name T1656
Test name
Test status
Simulation time 231935788 ps
CPU time 1.03 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 206964 kb
Host smart-e466fa8c-c4d9-4035-895d-0c84012fa6cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51851
4465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.518514465
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.4211086808
Short name T2349
Test name
Test status
Simulation time 8161128102 ps
CPU time 86.07 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:47:01 PM PDT 24
Peak memory 215356 kb
Host smart-e976041a-a21f-4e93-b35f-7572d4c5991d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4211086808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.4211086808
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1199078960
Short name T205
Test name
Test status
Simulation time 215159585 ps
CPU time 0.94 seconds
Started Jul 31 05:45:37 PM PDT 24
Finished Jul 31 05:45:38 PM PDT 24
Peak memory 206980 kb
Host smart-8600b26d-0c05-4b2c-a3ce-203832ed50d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11990
78960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1199078960
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2651182133
Short name T738
Test name
Test status
Simulation time 23337845545 ps
CPU time 31.9 seconds
Started Jul 31 05:45:34 PM PDT 24
Finished Jul 31 05:46:06 PM PDT 24
Peak memory 207160 kb
Host smart-e1345be0-1b42-40a4-a85e-649d039baa97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26511
82133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2651182133
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3306385021
Short name T803
Test name
Test status
Simulation time 3371395303 ps
CPU time 5.21 seconds
Started Jul 31 05:45:35 PM PDT 24
Finished Jul 31 05:45:40 PM PDT 24
Peak memory 207204 kb
Host smart-b0cdb583-cd8c-4c17-ba97-338ab427e48a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33063
85021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3306385021
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.168691501
Short name T2830
Test name
Test status
Simulation time 7618555587 ps
CPU time 77.78 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:46:54 PM PDT 24
Peak memory 217076 kb
Host smart-95fc7875-c4b0-40ac-b389-2586f34daa7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869
1501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.168691501
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.1037676155
Short name T1312
Test name
Test status
Simulation time 3206857825 ps
CPU time 97.81 seconds
Started Jul 31 05:45:33 PM PDT 24
Finished Jul 31 05:47:11 PM PDT 24
Peak memory 215384 kb
Host smart-b793ca1e-478b-4938-b9e0-66921e4ea08e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1037676155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.1037676155
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1683345350
Short name T2845
Test name
Test status
Simulation time 300772650 ps
CPU time 1.11 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:45:38 PM PDT 24
Peak memory 207004 kb
Host smart-51eae7d7-8b0a-4e95-af92-2d7a32cb11a4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1683345350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1683345350
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3422573427
Short name T1969
Test name
Test status
Simulation time 221618865 ps
CPU time 0.94 seconds
Started Jul 31 05:45:32 PM PDT 24
Finished Jul 31 05:45:33 PM PDT 24
Peak memory 207004 kb
Host smart-45852114-0ed7-4d4d-924f-34dc5ae9b8f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34225
73427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3422573427
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.3867754327
Short name T823
Test name
Test status
Simulation time 4826211965 ps
CPU time 146.82 seconds
Started Jul 31 05:45:42 PM PDT 24
Finished Jul 31 05:48:09 PM PDT 24
Peak memory 215400 kb
Host smart-f583eff8-893d-406d-a3bc-ef923e7ad9e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38677
54327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.3867754327
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2546961885
Short name T905
Test name
Test status
Simulation time 6939069311 ps
CPU time 72.48 seconds
Started Jul 31 05:45:37 PM PDT 24
Finished Jul 31 05:46:49 PM PDT 24
Peak memory 207252 kb
Host smart-35fdf300-5dd8-4f4f-b75a-c49a94eabbd5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2546961885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2546961885
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3199213789
Short name T413
Test name
Test status
Simulation time 189857677 ps
CPU time 1.04 seconds
Started Jul 31 05:45:39 PM PDT 24
Finished Jul 31 05:45:40 PM PDT 24
Peak memory 207008 kb
Host smart-4c167ab4-9b6c-4dde-8f21-4f3d50ce6606
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3199213789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3199213789
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.806701286
Short name T1175
Test name
Test status
Simulation time 141786409 ps
CPU time 0.89 seconds
Started Jul 31 05:45:40 PM PDT 24
Finished Jul 31 05:45:41 PM PDT 24
Peak memory 206996 kb
Host smart-35e71b98-3d04-4442-beea-83247bde2d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80670
1286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.806701286
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2099947689
Short name T2597
Test name
Test status
Simulation time 282011425 ps
CPU time 1.04 seconds
Started Jul 31 05:45:41 PM PDT 24
Finished Jul 31 05:45:42 PM PDT 24
Peak memory 207012 kb
Host smart-d61b5d7a-357c-40bb-bf25-26d9eaf25abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20999
47689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2099947689
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1422416035
Short name T1220
Test name
Test status
Simulation time 173686159 ps
CPU time 0.9 seconds
Started Jul 31 05:45:40 PM PDT 24
Finished Jul 31 05:45:40 PM PDT 24
Peak memory 207044 kb
Host smart-511f5c9d-a9d9-4417-8754-d70f10e7a5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14224
16035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1422416035
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.714886693
Short name T2321
Test name
Test status
Simulation time 193046535 ps
CPU time 0.9 seconds
Started Jul 31 05:45:38 PM PDT 24
Finished Jul 31 05:45:39 PM PDT 24
Peak memory 207000 kb
Host smart-f79e1fde-45f4-443a-9699-9b6feae9c548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71488
6693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.714886693
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2505531383
Short name T2050
Test name
Test status
Simulation time 182102123 ps
CPU time 0.87 seconds
Started Jul 31 05:45:38 PM PDT 24
Finished Jul 31 05:45:39 PM PDT 24
Peak memory 207036 kb
Host smart-3a363d50-814e-4f45-beee-208a8d9b6233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25055
31383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2505531383
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1385982911
Short name T1672
Test name
Test status
Simulation time 152289928 ps
CPU time 0.82 seconds
Started Jul 31 05:45:40 PM PDT 24
Finished Jul 31 05:45:41 PM PDT 24
Peak memory 206992 kb
Host smart-f1580edc-1c3d-4301-85dd-bfa1075c2bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13859
82911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1385982911
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1714117722
Short name T2548
Test name
Test status
Simulation time 206555176 ps
CPU time 1.04 seconds
Started Jul 31 05:45:38 PM PDT 24
Finished Jul 31 05:45:39 PM PDT 24
Peak memory 207008 kb
Host smart-6e8759d8-87b6-441d-b9fd-a81e241b700d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1714117722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1714117722
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.4244953287
Short name T1031
Test name
Test status
Simulation time 146318707 ps
CPU time 0.86 seconds
Started Jul 31 05:45:40 PM PDT 24
Finished Jul 31 05:45:41 PM PDT 24
Peak memory 206948 kb
Host smart-2a5b2e81-3dfb-4917-b41c-dad710aaa8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42449
53287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.4244953287
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1484784136
Short name T201
Test name
Test status
Simulation time 37550619 ps
CPU time 0.66 seconds
Started Jul 31 05:45:35 PM PDT 24
Finished Jul 31 05:45:36 PM PDT 24
Peak memory 206936 kb
Host smart-075a7b9d-901b-4619-afa4-afe5cdc06400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14847
84136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1484784136
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.755164084
Short name T2152
Test name
Test status
Simulation time 22477454089 ps
CPU time 57.79 seconds
Started Jul 31 05:45:40 PM PDT 24
Finished Jul 31 05:46:38 PM PDT 24
Peak memory 215436 kb
Host smart-4e57908f-00f0-443b-bda9-fdd0f8959c2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75516
4084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.755164084
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3309335967
Short name T2311
Test name
Test status
Simulation time 178070906 ps
CPU time 0.93 seconds
Started Jul 31 05:45:40 PM PDT 24
Finished Jul 31 05:45:41 PM PDT 24
Peak memory 206996 kb
Host smart-afb9b921-018f-4331-889e-22024776deb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33093
35967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3309335967
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1088356892
Short name T1011
Test name
Test status
Simulation time 212016113 ps
CPU time 0.96 seconds
Started Jul 31 05:45:38 PM PDT 24
Finished Jul 31 05:45:39 PM PDT 24
Peak memory 206960 kb
Host smart-aa3c7fc7-df02-462c-a816-795f0ea9ab41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
56892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1088356892
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.1229331422
Short name T559
Test name
Test status
Simulation time 173608375 ps
CPU time 0.87 seconds
Started Jul 31 05:45:36 PM PDT 24
Finished Jul 31 05:45:37 PM PDT 24
Peak memory 206916 kb
Host smart-2c23ad8e-d304-4119-b3eb-9c5f32bfe200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12293
31422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.1229331422
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.1672893067
Short name T2426
Test name
Test status
Simulation time 191279932 ps
CPU time 1.04 seconds
Started Jul 31 05:45:38 PM PDT 24
Finished Jul 31 05:45:39 PM PDT 24
Peak memory 206996 kb
Host smart-c2dac664-62a1-474c-ae58-66cac0a80172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16728
93067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1672893067
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.1744568360
Short name T1894
Test name
Test status
Simulation time 193093632 ps
CPU time 0.92 seconds
Started Jul 31 05:45:42 PM PDT 24
Finished Jul 31 05:45:43 PM PDT 24
Peak memory 206992 kb
Host smart-eacd97e3-7853-4225-8f76-106ddcf3ae44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17445
68360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1744568360
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.1142726026
Short name T539
Test name
Test status
Simulation time 152192600 ps
CPU time 0.8 seconds
Started Jul 31 05:45:41 PM PDT 24
Finished Jul 31 05:45:42 PM PDT 24
Peak memory 206948 kb
Host smart-03d22b1e-75d0-4d5d-a5f8-dad7da6f605c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11427
26026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.1142726026
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.863841346
Short name T689
Test name
Test status
Simulation time 147372220 ps
CPU time 0.82 seconds
Started Jul 31 05:45:44 PM PDT 24
Finished Jul 31 05:45:45 PM PDT 24
Peak memory 206968 kb
Host smart-2726bac5-da84-4c75-8eed-5ccb3011bf97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86384
1346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.863841346
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2495193338
Short name T1158
Test name
Test status
Simulation time 215638856 ps
CPU time 1.02 seconds
Started Jul 31 05:45:39 PM PDT 24
Finished Jul 31 05:45:40 PM PDT 24
Peak memory 206996 kb
Host smart-d7765320-ffbe-4706-bfe3-a2894f1d8a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24951
93338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2495193338
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3112475965
Short name T2464
Test name
Test status
Simulation time 4589531729 ps
CPU time 139.83 seconds
Started Jul 31 05:45:40 PM PDT 24
Finished Jul 31 05:48:00 PM PDT 24
Peak memory 215372 kb
Host smart-8abff642-411f-482a-adac-b2d2f7fd6715
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3112475965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3112475965
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.3626188293
Short name T1435
Test name
Test status
Simulation time 142839805 ps
CPU time 0.87 seconds
Started Jul 31 05:45:42 PM PDT 24
Finished Jul 31 05:45:43 PM PDT 24
Peak memory 206996 kb
Host smart-4218e1a8-e0b9-4742-9ae3-6e0d0b5488d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36261
88293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.3626188293
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1773990419
Short name T1683
Test name
Test status
Simulation time 149970948 ps
CPU time 0.82 seconds
Started Jul 31 05:45:45 PM PDT 24
Finished Jul 31 05:45:46 PM PDT 24
Peak memory 207032 kb
Host smart-06fa7841-3b13-47a5-884c-d5d7ab983b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739
90419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1773990419
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.3068258944
Short name T2156
Test name
Test status
Simulation time 1161450683 ps
CPU time 3.02 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:45:49 PM PDT 24
Peak memory 207104 kb
Host smart-002c69ac-b6c0-4f10-a5ed-bb37a81ba1d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30682
58944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.3068258944
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.1382844618
Short name T602
Test name
Test status
Simulation time 4279855793 ps
CPU time 45.16 seconds
Started Jul 31 05:45:45 PM PDT 24
Finished Jul 31 05:46:30 PM PDT 24
Peak memory 216688 kb
Host smart-63dbdbfb-79bf-4455-98fd-083e08a5b50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13828
44618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1382844618
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.1375665551
Short name T456
Test name
Test status
Simulation time 7040500327 ps
CPU time 44.58 seconds
Started Jul 31 05:45:38 PM PDT 24
Finished Jul 31 05:46:22 PM PDT 24
Peak memory 207280 kb
Host smart-7e46b932-ca4e-44b0-9022-eee695692866
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375665551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_hos
t_handshake.1375665551
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.4292585917
Short name T2148
Test name
Test status
Simulation time 53588279 ps
CPU time 0.71 seconds
Started Jul 31 05:45:53 PM PDT 24
Finished Jul 31 05:45:54 PM PDT 24
Peak memory 207004 kb
Host smart-3bc427ed-a1ce-4dbf-b81b-0226bfadf52b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4292585917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.4292585917
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.761005004
Short name T1169
Test name
Test status
Simulation time 3866505998 ps
CPU time 5.46 seconds
Started Jul 31 05:45:45 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 207100 kb
Host smart-d0b15789-7729-4b41-a07e-ca740a4f1d2b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761005004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_disconnect.761005004
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1656758862
Short name T2562
Test name
Test status
Simulation time 13414218208 ps
CPU time 16.2 seconds
Started Jul 31 05:45:45 PM PDT 24
Finished Jul 31 05:46:01 PM PDT 24
Peak memory 207228 kb
Host smart-85613b82-97b3-4399-a22b-499311652f54
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656758862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1656758862
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.2040269175
Short name T2692
Test name
Test status
Simulation time 23350976259 ps
CPU time 28.01 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:46:14 PM PDT 24
Peak memory 207184 kb
Host smart-b629706a-44e5-4b05-8b52-da4bfe7cf56c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040269175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_resume.2040269175
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2140144654
Short name T2172
Test name
Test status
Simulation time 167576627 ps
CPU time 0.84 seconds
Started Jul 31 05:45:43 PM PDT 24
Finished Jul 31 05:45:44 PM PDT 24
Peak memory 207000 kb
Host smart-d42d6675-9ac6-41ed-b900-d722c1663138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21401
44654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2140144654
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1948864209
Short name T2725
Test name
Test status
Simulation time 152575660 ps
CPU time 0.81 seconds
Started Jul 31 05:45:48 PM PDT 24
Finished Jul 31 05:45:49 PM PDT 24
Peak memory 206948 kb
Host smart-52cecde8-4eab-4a5c-8b27-9688a418a839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19488
64209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1948864209
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.873760270
Short name T994
Test name
Test status
Simulation time 240472697 ps
CPU time 1.05 seconds
Started Jul 31 05:45:43 PM PDT 24
Finished Jul 31 05:45:45 PM PDT 24
Peak memory 207008 kb
Host smart-9d4121f4-26cf-4c7f-a0d2-4ea82dcc211d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87376
0270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.873760270
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3705570758
Short name T937
Test name
Test status
Simulation time 817807437 ps
CPU time 2.16 seconds
Started Jul 31 05:45:43 PM PDT 24
Finished Jul 31 05:45:46 PM PDT 24
Peak memory 207148 kb
Host smart-feea73fc-bd14-4713-893a-cc453fa0f83a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3705570758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3705570758
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_timeout.2963929471
Short name T2227
Test name
Test status
Simulation time 2921372282 ps
CPU time 24.87 seconds
Started Jul 31 05:45:45 PM PDT 24
Finished Jul 31 05:46:10 PM PDT 24
Peak memory 207184 kb
Host smart-92608db8-cfc5-407b-a358-a3c71dc74d31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963929471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.2963929471
Directory /workspace/38.usbdev_device_timeout/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.1908319705
Short name T2309
Test name
Test status
Simulation time 398198827 ps
CPU time 1.41 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:45:47 PM PDT 24
Peak memory 206960 kb
Host smart-491867e6-0c97-45a9-9539-789fbb403e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19083
19705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.1908319705
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3318062782
Short name T2802
Test name
Test status
Simulation time 177646071 ps
CPU time 0.89 seconds
Started Jul 31 05:45:43 PM PDT 24
Finished Jul 31 05:45:44 PM PDT 24
Peak memory 207008 kb
Host smart-7e233861-476a-4eba-97f2-c82b194a970d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33180
62782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3318062782
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3978205384
Short name T2155
Test name
Test status
Simulation time 98085304 ps
CPU time 0.74 seconds
Started Jul 31 05:45:47 PM PDT 24
Finished Jul 31 05:45:48 PM PDT 24
Peak memory 206948 kb
Host smart-e106bfce-4276-491b-9598-2024dff6c173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39782
05384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3978205384
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2551956477
Short name T759
Test name
Test status
Simulation time 701416014 ps
CPU time 2.08 seconds
Started Jul 31 05:45:44 PM PDT 24
Finished Jul 31 05:45:46 PM PDT 24
Peak memory 207120 kb
Host smart-29037616-bed0-429c-8290-8d4d2e3fabe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25519
56477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2551956477
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2154983254
Short name T1765
Test name
Test status
Simulation time 208753346 ps
CPU time 2.49 seconds
Started Jul 31 05:45:57 PM PDT 24
Finished Jul 31 05:46:00 PM PDT 24
Peak memory 207040 kb
Host smart-c39c82b2-e285-4b83-9e31-694633d2d105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21549
83254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2154983254
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3985587321
Short name T1236
Test name
Test status
Simulation time 255220600 ps
CPU time 1.2 seconds
Started Jul 31 05:45:44 PM PDT 24
Finished Jul 31 05:45:45 PM PDT 24
Peak memory 207064 kb
Host smart-ba1afc0a-10c2-4179-914c-bb3149521c49
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3985587321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3985587321
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1872060642
Short name T2522
Test name
Test status
Simulation time 142865117 ps
CPU time 0.82 seconds
Started Jul 31 05:45:42 PM PDT 24
Finished Jul 31 05:45:43 PM PDT 24
Peak memory 206956 kb
Host smart-9c374d2c-85fb-4c93-81c5-424fd86dddf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18720
60642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1872060642
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.1355771244
Short name T2043
Test name
Test status
Simulation time 196591572 ps
CPU time 0.91 seconds
Started Jul 31 05:45:47 PM PDT 24
Finished Jul 31 05:45:48 PM PDT 24
Peak memory 206996 kb
Host smart-7869d1c2-003d-498a-9834-79433585d8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13557
71244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.1355771244
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1321673455
Short name T1137
Test name
Test status
Simulation time 9064653794 ps
CPU time 274.23 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:50:24 PM PDT 24
Peak memory 215404 kb
Host smart-bf547f85-1a6e-4788-aa41-c353aa207de1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1321673455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1321673455
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.929089898
Short name T538
Test name
Test status
Simulation time 229981693 ps
CPU time 1.05 seconds
Started Jul 31 05:46:01 PM PDT 24
Finished Jul 31 05:46:02 PM PDT 24
Peak memory 207008 kb
Host smart-f647c7a2-5a9a-4971-b92b-8c87f9e777e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92908
9898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.929089898
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1884194144
Short name T2469
Test name
Test status
Simulation time 23340762254 ps
CPU time 28.66 seconds
Started Jul 31 05:45:44 PM PDT 24
Finished Jul 31 05:46:13 PM PDT 24
Peak memory 207164 kb
Host smart-bc0d06d5-fbfa-4819-a300-3c2885fadf71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18841
94144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1884194144
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3487018898
Short name T1185
Test name
Test status
Simulation time 3334087903 ps
CPU time 5.02 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:45:51 PM PDT 24
Peak memory 207140 kb
Host smart-1b802fed-bd1e-43c4-ac99-e264d527ea7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34870
18898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3487018898
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.3015941900
Short name T2200
Test name
Test status
Simulation time 5359790455 ps
CPU time 43.6 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:46:33 PM PDT 24
Peak memory 217432 kb
Host smart-b2073983-9959-4b56-b595-a9627c357ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30159
41900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.3015941900
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2897232113
Short name T449
Test name
Test status
Simulation time 4607562067 ps
CPU time 38.61 seconds
Started Jul 31 05:45:45 PM PDT 24
Finished Jul 31 05:46:23 PM PDT 24
Peak memory 207256 kb
Host smart-2124d6c7-ade4-41f2-85d6-d6f93f0680a5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2897232113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2897232113
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1719525425
Short name T971
Test name
Test status
Simulation time 259055365 ps
CPU time 1 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:45:47 PM PDT 24
Peak memory 207008 kb
Host smart-7343bd31-18e7-4038-b58e-327f0830b224
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1719525425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1719525425
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3017370899
Short name T2261
Test name
Test status
Simulation time 193908297 ps
CPU time 0.94 seconds
Started Jul 31 05:45:45 PM PDT 24
Finished Jul 31 05:45:46 PM PDT 24
Peak memory 206980 kb
Host smart-2e3dd3f7-4c5b-43a7-867b-783f6776f566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173
70899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3017370899
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3327516838
Short name T1356
Test name
Test status
Simulation time 6157055003 ps
CPU time 171.64 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:48:37 PM PDT 24
Peak memory 215436 kb
Host smart-b8476285-ad59-48cc-888a-043864aac248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33275
16838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3327516838
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.3102494475
Short name T2368
Test name
Test status
Simulation time 3401260942 ps
CPU time 36.71 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:46:25 PM PDT 24
Peak memory 215428 kb
Host smart-b587f6ef-c24b-4103-a79b-4b02029a41c5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3102494475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.3102494475
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2106856205
Short name T1061
Test name
Test status
Simulation time 175503689 ps
CPU time 0.9 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:45:47 PM PDT 24
Peak memory 207024 kb
Host smart-70b4800f-e2e7-4675-b101-c97219e861c2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2106856205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2106856205
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3685600367
Short name T2359
Test name
Test status
Simulation time 160720181 ps
CPU time 0.91 seconds
Started Jul 31 05:45:48 PM PDT 24
Finished Jul 31 05:45:49 PM PDT 24
Peak memory 206996 kb
Host smart-9bba7b75-ffe9-4419-9282-52ccb3bfac67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36856
00367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3685600367
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1219060086
Short name T126
Test name
Test status
Simulation time 200054369 ps
CPU time 0.98 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:45:51 PM PDT 24
Peak memory 206968 kb
Host smart-de7e2d33-cafb-48ff-8a90-4a98853fad4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12190
60086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1219060086
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.2673366362
Short name T396
Test name
Test status
Simulation time 211939514 ps
CPU time 0.97 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 207004 kb
Host smart-f5fd10a4-3cc0-4f25-8ae8-3a8105b67a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26733
66362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.2673366362
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.198117012
Short name T2543
Test name
Test status
Simulation time 169722484 ps
CPU time 0.93 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:45:47 PM PDT 24
Peak memory 206972 kb
Host smart-232810f3-b272-4f3e-8139-b19d0ec32504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19811
7012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.198117012
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.3504531279
Short name T1334
Test name
Test status
Simulation time 166007100 ps
CPU time 0.87 seconds
Started Jul 31 05:45:48 PM PDT 24
Finished Jul 31 05:45:49 PM PDT 24
Peak memory 207000 kb
Host smart-5b59ad19-4cac-4cdc-a6cd-f9627ede57ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35045
31279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.3504531279
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2093098032
Short name T1421
Test name
Test status
Simulation time 151678298 ps
CPU time 1.02 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 206988 kb
Host smart-a9f17e8e-9ac3-4ff9-82b2-5234cbc01069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20930
98032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2093098032
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3016927173
Short name T2022
Test name
Test status
Simulation time 225831926 ps
CPU time 0.96 seconds
Started Jul 31 05:45:48 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 207012 kb
Host smart-aa9de8d3-dac3-40ab-a81f-5ada0b5eb327
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3016927173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3016927173
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.421719216
Short name T1654
Test name
Test status
Simulation time 155431606 ps
CPU time 0.84 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 206992 kb
Host smart-9b150034-515f-4fdd-b1df-d69514c4d60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42171
9216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.421719216
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.1624109184
Short name T1996
Test name
Test status
Simulation time 34020179 ps
CPU time 0.67 seconds
Started Jul 31 05:45:43 PM PDT 24
Finished Jul 31 05:45:44 PM PDT 24
Peak memory 206932 kb
Host smart-0c813d97-5e3e-4625-aeef-0c8561b3bd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16241
09184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.1624109184
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.3271186087
Short name T1372
Test name
Test status
Simulation time 21992036627 ps
CPU time 54.89 seconds
Started Jul 31 05:45:47 PM PDT 24
Finished Jul 31 05:46:43 PM PDT 24
Peak memory 219860 kb
Host smart-c2fb04c9-590a-48b4-9242-4bd6f2f638d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32711
86087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.3271186087
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2436976871
Short name T2449
Test name
Test status
Simulation time 194625603 ps
CPU time 0.96 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 206984 kb
Host smart-745e7683-6ee2-4e47-920b-4b08f5b92362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24369
76871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2436976871
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.629633474
Short name T2846
Test name
Test status
Simulation time 266173401 ps
CPU time 1.03 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 206988 kb
Host smart-e8617e45-1830-4d83-9720-265ad1aa2f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62963
3474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.629633474
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.1101012141
Short name T2064
Test name
Test status
Simulation time 216819387 ps
CPU time 0.99 seconds
Started Jul 31 05:45:48 PM PDT 24
Finished Jul 31 05:45:49 PM PDT 24
Peak memory 206980 kb
Host smart-594fc6ad-f8a5-43c6-8bda-eca6458cab41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11010
12141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.1101012141
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3986457382
Short name T2670
Test name
Test status
Simulation time 275280248 ps
CPU time 1.05 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:45:47 PM PDT 24
Peak memory 206992 kb
Host smart-c3ff3fa5-605d-4136-a8c1-c4c614cd322e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39864
57382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3986457382
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.363363494
Short name T1390
Test name
Test status
Simulation time 192894533 ps
CPU time 0.9 seconds
Started Jul 31 05:45:42 PM PDT 24
Finished Jul 31 05:45:43 PM PDT 24
Peak memory 207004 kb
Host smart-5e58a069-19f3-4a27-bd49-3fb512a4f77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36336
3494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.363363494
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3654454793
Short name T1021
Test name
Test status
Simulation time 149254210 ps
CPU time 0.86 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:45:47 PM PDT 24
Peak memory 206940 kb
Host smart-45340a12-eb8a-43ad-b863-c8d765f441ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544
54793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3654454793
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3501700539
Short name T2519
Test name
Test status
Simulation time 150282855 ps
CPU time 0.86 seconds
Started Jul 31 05:45:43 PM PDT 24
Finished Jul 31 05:45:44 PM PDT 24
Peak memory 207004 kb
Host smart-217d9554-6b6c-43a8-adc3-e9c4dc2618fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35017
00539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3501700539
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.1879524771
Short name T2206
Test name
Test status
Simulation time 187722596 ps
CPU time 0.99 seconds
Started Jul 31 05:45:46 PM PDT 24
Finished Jul 31 05:45:47 PM PDT 24
Peak memory 206968 kb
Host smart-5ca97939-e1da-4a88-8411-37a922ecb3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18795
24771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.1879524771
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.766364912
Short name T1415
Test name
Test status
Simulation time 4178619663 ps
CPU time 41.93 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:46:31 PM PDT 24
Peak memory 215328 kb
Host smart-1f74a841-c0dd-4e1b-9a40-6b39e5555dbc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=766364912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.766364912
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.851281862
Short name T2799
Test name
Test status
Simulation time 173960727 ps
CPU time 0.88 seconds
Started Jul 31 05:45:52 PM PDT 24
Finished Jul 31 05:45:53 PM PDT 24
Peak memory 206976 kb
Host smart-2bf955a5-1d14-4526-8c66-7ada8ab2b19c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85128
1862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.851281862
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.4093234939
Short name T61
Test name
Test status
Simulation time 188120035 ps
CPU time 0.87 seconds
Started Jul 31 05:45:54 PM PDT 24
Finished Jul 31 05:45:55 PM PDT 24
Peak memory 206984 kb
Host smart-9be818fe-c872-4d0b-8931-34b0c5288393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40932
34939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.4093234939
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.409948160
Short name T2039
Test name
Test status
Simulation time 762260141 ps
CPU time 1.93 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:45:51 PM PDT 24
Peak memory 206968 kb
Host smart-2126ae3b-cf88-4776-99e1-f7ff1a978e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994
8160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.409948160
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.3990153181
Short name T1069
Test name
Test status
Simulation time 5690851781 ps
CPU time 56.54 seconds
Started Jul 31 05:45:51 PM PDT 24
Finished Jul 31 05:46:48 PM PDT 24
Peak memory 207192 kb
Host smart-ffecae6e-822b-494e-a88f-87ece32e3d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39901
53181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.3990153181
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.2843033878
Short name T673
Test name
Test status
Simulation time 3406439722 ps
CPU time 32.63 seconds
Started Jul 31 05:45:47 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 207252 kb
Host smart-ffd1eacc-2bad-483f-bbfa-a99085f8fea3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843033878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_hos
t_handshake.2843033878
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.2261473867
Short name T979
Test name
Test status
Simulation time 56064007 ps
CPU time 0.65 seconds
Started Jul 31 05:45:58 PM PDT 24
Finished Jul 31 05:45:59 PM PDT 24
Peak memory 207020 kb
Host smart-eb290e27-360f-4cf8-90f1-fdbf9bb15383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2261473867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.2261473867
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.2361851563
Short name T1865
Test name
Test status
Simulation time 4168940032 ps
CPU time 5.49 seconds
Started Jul 31 05:45:54 PM PDT 24
Finished Jul 31 05:45:59 PM PDT 24
Peak memory 207172 kb
Host smart-a1c9dc6d-14bb-4983-826a-f08907a219f9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361851563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_disconnect.2361851563
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.3100238823
Short name T1022
Test name
Test status
Simulation time 13498526857 ps
CPU time 16.63 seconds
Started Jul 31 05:45:53 PM PDT 24
Finished Jul 31 05:46:10 PM PDT 24
Peak memory 207240 kb
Host smart-2fe6a70c-025f-4350-8be1-02ac76b200bf
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100238823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.3100238823
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3611451333
Short name T2126
Test name
Test status
Simulation time 23410016563 ps
CPU time 32.04 seconds
Started Jul 31 05:45:50 PM PDT 24
Finished Jul 31 05:46:22 PM PDT 24
Peak memory 207200 kb
Host smart-a6fe26db-619b-404f-829a-383ee7d675bf
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611451333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_a
on_wake_resume.3611451333
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.37889053
Short name T593
Test name
Test status
Simulation time 198346734 ps
CPU time 0.97 seconds
Started Jul 31 05:45:50 PM PDT 24
Finished Jul 31 05:45:51 PM PDT 24
Peak memory 207008 kb
Host smart-7ae9cfce-e9a3-42d9-ba04-a8ee65140bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37889
053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.37889053
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1987927606
Short name T1213
Test name
Test status
Simulation time 146293816 ps
CPU time 0.89 seconds
Started Jul 31 05:45:53 PM PDT 24
Finished Jul 31 05:45:54 PM PDT 24
Peak memory 206968 kb
Host smart-38ebb672-47c8-42cc-8249-3f93a712acad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19879
27606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1987927606
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1088619053
Short name T1384
Test name
Test status
Simulation time 271982397 ps
CPU time 1.09 seconds
Started Jul 31 05:45:47 PM PDT 24
Finished Jul 31 05:45:49 PM PDT 24
Peak memory 207016 kb
Host smart-70c27845-82e3-40f1-8640-41bb7386b168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10886
19053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1088619053
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1344013994
Short name T2384
Test name
Test status
Simulation time 831161065 ps
CPU time 2.64 seconds
Started Jul 31 05:45:52 PM PDT 24
Finished Jul 31 05:45:55 PM PDT 24
Peak memory 207056 kb
Host smart-2957574d-6843-4d2a-bc38-7a0d3fc0425a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1344013994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1344013994
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.3638536371
Short name T161
Test name
Test status
Simulation time 17521771064 ps
CPU time 42.03 seconds
Started Jul 31 05:45:50 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 207208 kb
Host smart-332bce44-a9dd-4861-b696-cc1ebf0f1db8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36385
36371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.3638536371
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_device_timeout.4039822810
Short name T2525
Test name
Test status
Simulation time 4977461652 ps
CPU time 33.93 seconds
Started Jul 31 05:45:50 PM PDT 24
Finished Jul 31 05:46:24 PM PDT 24
Peak memory 207180 kb
Host smart-458cb8d8-1e16-42ab-bcc7-f6ed8f37e5ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039822810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.4039822810
Directory /workspace/39.usbdev_device_timeout/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2720608378
Short name T975
Test name
Test status
Simulation time 457125096 ps
CPU time 1.48 seconds
Started Jul 31 05:45:53 PM PDT 24
Finished Jul 31 05:45:55 PM PDT 24
Peak memory 206936 kb
Host smart-78a63c91-d638-47c8-93f9-6fec98aa82c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27206
08378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2720608378
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.1144847745
Short name T785
Test name
Test status
Simulation time 132333520 ps
CPU time 0.83 seconds
Started Jul 31 05:45:52 PM PDT 24
Finished Jul 31 05:45:53 PM PDT 24
Peak memory 206936 kb
Host smart-6e5fb007-4b04-4eaf-b36b-f672f596c9de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11448
47745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1144847745
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.677476412
Short name T709
Test name
Test status
Simulation time 45870482 ps
CPU time 0.7 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:45:50 PM PDT 24
Peak memory 206944 kb
Host smart-4cf0f2af-c0c4-4187-97ce-1eac3469fcc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67747
6412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.677476412
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.8718068
Short name T1733
Test name
Test status
Simulation time 585497302 ps
CPU time 1.91 seconds
Started Jul 31 05:45:53 PM PDT 24
Finished Jul 31 05:45:55 PM PDT 24
Peak memory 207124 kb
Host smart-8959ed65-6a81-4d61-a1ce-450fec2e50bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87180
68 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.8718068
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.421815879
Short name T1557
Test name
Test status
Simulation time 207198868 ps
CPU time 2.33 seconds
Started Jul 31 05:45:51 PM PDT 24
Finished Jul 31 05:45:54 PM PDT 24
Peak memory 207044 kb
Host smart-6364b133-5685-4a48-a58c-1b2c797cde8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42181
5879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.421815879
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.3295156698
Short name T389
Test name
Test status
Simulation time 208290839 ps
CPU time 0.94 seconds
Started Jul 31 05:45:53 PM PDT 24
Finished Jul 31 05:45:54 PM PDT 24
Peak memory 207004 kb
Host smart-7c857de6-a979-4463-abdc-2dc5ddb80aec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3295156698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.3295156698
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2812435682
Short name T2506
Test name
Test status
Simulation time 143423093 ps
CPU time 0.8 seconds
Started Jul 31 05:45:52 PM PDT 24
Finished Jul 31 05:45:52 PM PDT 24
Peak memory 206948 kb
Host smart-7f55fd14-ce44-4404-a41e-20817606c0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28124
35682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2812435682
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.1354179688
Short name T2502
Test name
Test status
Simulation time 275984613 ps
CPU time 1.06 seconds
Started Jul 31 05:45:50 PM PDT 24
Finished Jul 31 05:45:51 PM PDT 24
Peak memory 206996 kb
Host smart-bcf5d2c9-1c33-4f1e-8e9a-987bc9f21680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13541
79688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1354179688
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.833555680
Short name T736
Test name
Test status
Simulation time 6150803774 ps
CPU time 187.25 seconds
Started Jul 31 05:45:52 PM PDT 24
Finished Jul 31 05:48:59 PM PDT 24
Peak memory 215424 kb
Host smart-1d45c3bb-3520-49b4-8502-50ae7836dff7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=833555680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.833555680
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.2208128709
Short name T998
Test name
Test status
Simulation time 7821283956 ps
CPU time 103.54 seconds
Started Jul 31 05:45:52 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 207172 kb
Host smart-d1a00d30-ca66-4832-8ccf-12667f94a9a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2208128709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.2208128709
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2586967494
Short name T2861
Test name
Test status
Simulation time 198564687 ps
CPU time 0.92 seconds
Started Jul 31 05:45:51 PM PDT 24
Finished Jul 31 05:45:52 PM PDT 24
Peak memory 207000 kb
Host smart-35fdb486-d2a4-4b13-837c-faa0d70d9d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25869
67494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2586967494
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.2043997985
Short name T1814
Test name
Test status
Simulation time 23315022866 ps
CPU time 28.7 seconds
Started Jul 31 05:45:54 PM PDT 24
Finished Jul 31 05:46:22 PM PDT 24
Peak memory 207180 kb
Host smart-2e21dde3-d893-4c94-a2f7-1988273eb4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20439
97985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.2043997985
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1671575525
Short name T1759
Test name
Test status
Simulation time 3283723921 ps
CPU time 5.11 seconds
Started Jul 31 05:45:52 PM PDT 24
Finished Jul 31 05:45:57 PM PDT 24
Peak memory 207120 kb
Host smart-3b352b5d-2fd1-49c6-9ee5-6a952b2769a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16715
75525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1671575525
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.4290546030
Short name T1665
Test name
Test status
Simulation time 9599654047 ps
CPU time 280.74 seconds
Started Jul 31 05:45:58 PM PDT 24
Finished Jul 31 05:50:39 PM PDT 24
Peak memory 215416 kb
Host smart-c8d4a0c3-8fc4-4f91-b4fc-19c0b02ddaa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42905
46030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.4290546030
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2767574026
Short name T241
Test name
Test status
Simulation time 3602782920 ps
CPU time 28.06 seconds
Started Jul 31 05:45:49 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 215380 kb
Host smart-3a1a0183-23ed-4e9f-a852-e7e78692dcc3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2767574026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2767574026
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.4059672832
Short name T2491
Test name
Test status
Simulation time 251292627 ps
CPU time 1.03 seconds
Started Jul 31 05:45:50 PM PDT 24
Finished Jul 31 05:45:51 PM PDT 24
Peak memory 206996 kb
Host smart-06417cc1-785f-43f1-95c7-eabc6bc226a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4059672832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.4059672832
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.4008371887
Short name T204
Test name
Test status
Simulation time 186443030 ps
CPU time 0.93 seconds
Started Jul 31 05:45:51 PM PDT 24
Finished Jul 31 05:45:52 PM PDT 24
Peak memory 206984 kb
Host smart-520f589f-30c2-47b2-b6c7-a7dab9d9b6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40083
71887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.4008371887
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.1011920440
Short name T1140
Test name
Test status
Simulation time 4626285496 ps
CPU time 46.67 seconds
Started Jul 31 05:45:53 PM PDT 24
Finished Jul 31 05:46:40 PM PDT 24
Peak memory 216900 kb
Host smart-40066ff5-2c10-45dc-a6ba-86f3e400bbb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10119
20440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.1011920440
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3418996166
Short name T1850
Test name
Test status
Simulation time 7072875341 ps
CPU time 73.48 seconds
Started Jul 31 05:45:54 PM PDT 24
Finished Jul 31 05:47:07 PM PDT 24
Peak memory 207236 kb
Host smart-5832e3a7-84f7-4869-bdb3-9461e704df39
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3418996166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3418996166
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.3304276354
Short name T1026
Test name
Test status
Simulation time 169780441 ps
CPU time 0.87 seconds
Started Jul 31 05:45:54 PM PDT 24
Finished Jul 31 05:45:55 PM PDT 24
Peak memory 207020 kb
Host smart-35f59643-e2b5-4ad2-b96b-1b618fecc966
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3304276354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3304276354
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3967113797
Short name T1072
Test name
Test status
Simulation time 161918918 ps
CPU time 0.87 seconds
Started Jul 31 05:45:52 PM PDT 24
Finished Jul 31 05:45:53 PM PDT 24
Peak memory 206964 kb
Host smart-62a27d40-9ede-4517-a8a9-40d6030d2066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39671
13797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3967113797
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.2865319387
Short name T2636
Test name
Test status
Simulation time 204131305 ps
CPU time 0.95 seconds
Started Jul 31 05:45:59 PM PDT 24
Finished Jul 31 05:46:00 PM PDT 24
Peak memory 207000 kb
Host smart-d71303fc-511f-4f5c-adda-0cf635d1f89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28653
19387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.2865319387
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.3347541623
Short name T419
Test name
Test status
Simulation time 225317146 ps
CPU time 1.03 seconds
Started Jul 31 05:45:55 PM PDT 24
Finished Jul 31 05:45:56 PM PDT 24
Peak memory 206988 kb
Host smart-2782eef3-a7d3-4a2d-9c15-6dc028c77e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475
41623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.3347541623
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.3128739318
Short name T1629
Test name
Test status
Simulation time 170436499 ps
CPU time 0.9 seconds
Started Jul 31 05:45:56 PM PDT 24
Finished Jul 31 05:45:57 PM PDT 24
Peak memory 207000 kb
Host smart-06383378-082b-4e2c-9b3e-ffa06b6921d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31287
39318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3128739318
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3606098401
Short name T952
Test name
Test status
Simulation time 174297374 ps
CPU time 0.88 seconds
Started Jul 31 05:45:54 PM PDT 24
Finished Jul 31 05:45:55 PM PDT 24
Peak memory 207060 kb
Host smart-1c8c9667-e9e1-4cf7-9b40-5d201ab13b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36060
98401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3606098401
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3286204388
Short name T1263
Test name
Test status
Simulation time 152605472 ps
CPU time 0.82 seconds
Started Jul 31 05:45:56 PM PDT 24
Finished Jul 31 05:45:57 PM PDT 24
Peak memory 206968 kb
Host smart-ee7ee623-a99e-4400-91b5-fe8d1bf869d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32862
04388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3286204388
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3865958446
Short name T438
Test name
Test status
Simulation time 248071662 ps
CPU time 1.08 seconds
Started Jul 31 05:45:55 PM PDT 24
Finished Jul 31 05:45:56 PM PDT 24
Peak memory 207040 kb
Host smart-821e086d-5a23-4e71-817a-a9a279412650
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3865958446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3865958446
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2239384708
Short name T469
Test name
Test status
Simulation time 167395301 ps
CPU time 0.9 seconds
Started Jul 31 05:45:58 PM PDT 24
Finished Jul 31 05:45:59 PM PDT 24
Peak memory 206920 kb
Host smart-0bd97dd9-6635-4260-80de-0220a6b7dbe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22393
84708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2239384708
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1820474716
Short name T753
Test name
Test status
Simulation time 40706167 ps
CPU time 0.66 seconds
Started Jul 31 05:45:59 PM PDT 24
Finished Jul 31 05:46:00 PM PDT 24
Peak memory 206948 kb
Host smart-5d14429f-e682-4177-9d7f-3ec2ed87749d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18204
74716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1820474716
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3652692885
Short name T251
Test name
Test status
Simulation time 17844045962 ps
CPU time 46.38 seconds
Started Jul 31 05:45:57 PM PDT 24
Finished Jul 31 05:46:44 PM PDT 24
Peak memory 215400 kb
Host smart-070abd26-61fe-4c94-ae44-6ad165094741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36526
92885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3652692885
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2275641869
Short name T1084
Test name
Test status
Simulation time 163348413 ps
CPU time 0.83 seconds
Started Jul 31 05:45:54 PM PDT 24
Finished Jul 31 05:45:54 PM PDT 24
Peak memory 206968 kb
Host smart-2095500c-bb84-4d59-898f-b755fd2d9828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22756
41869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2275641869
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.4125574161
Short name T2336
Test name
Test status
Simulation time 210391868 ps
CPU time 0.93 seconds
Started Jul 31 05:45:57 PM PDT 24
Finished Jul 31 05:45:58 PM PDT 24
Peak memory 206980 kb
Host smart-5999f159-50ef-41c0-b2a8-60223f8ef2f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41255
74161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.4125574161
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.4024068925
Short name T2671
Test name
Test status
Simulation time 205984213 ps
CPU time 0.94 seconds
Started Jul 31 05:46:02 PM PDT 24
Finished Jul 31 05:46:03 PM PDT 24
Peak memory 206992 kb
Host smart-c4d929c0-cd2f-4be7-b4fd-9514845b0ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40240
68925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.4024068925
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2565417402
Short name T1180
Test name
Test status
Simulation time 202489035 ps
CPU time 1.02 seconds
Started Jul 31 05:45:55 PM PDT 24
Finished Jul 31 05:45:57 PM PDT 24
Peak memory 206980 kb
Host smart-70685736-28a4-408b-acf1-ffb1a6bf8727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25654
17402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2565417402
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3219564211
Short name T1686
Test name
Test status
Simulation time 165389946 ps
CPU time 0.88 seconds
Started Jul 31 05:45:57 PM PDT 24
Finished Jul 31 05:45:58 PM PDT 24
Peak memory 206996 kb
Host smart-ba0a0f58-f8bb-48e6-b1ec-1dc5040c3268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32195
64211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3219564211
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1235475172
Short name T1038
Test name
Test status
Simulation time 165248037 ps
CPU time 0.82 seconds
Started Jul 31 05:45:59 PM PDT 24
Finished Jul 31 05:46:00 PM PDT 24
Peak memory 206952 kb
Host smart-b3192f97-5d4d-46a6-8a40-101b56eb3fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12354
75172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1235475172
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.472586817
Short name T2263
Test name
Test status
Simulation time 156560878 ps
CPU time 0.87 seconds
Started Jul 31 05:45:55 PM PDT 24
Finished Jul 31 05:45:56 PM PDT 24
Peak memory 206992 kb
Host smart-9d95fdb5-0bbd-4010-863c-651ab830bc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47258
6817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.472586817
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3376365698
Short name T1195
Test name
Test status
Simulation time 251309515 ps
CPU time 1.09 seconds
Started Jul 31 05:45:56 PM PDT 24
Finished Jul 31 05:45:58 PM PDT 24
Peak memory 206984 kb
Host smart-c7c010a9-d1a2-4403-b909-936a26264abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33763
65698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3376365698
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3549333543
Short name T543
Test name
Test status
Simulation time 5313670195 ps
CPU time 153.46 seconds
Started Jul 31 05:45:56 PM PDT 24
Finished Jul 31 05:48:29 PM PDT 24
Peak memory 215400 kb
Host smart-c648a347-636c-49d6-acf9-d6aa79f01d33
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3549333543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3549333543
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.2509101737
Short name T1882
Test name
Test status
Simulation time 237590152 ps
CPU time 1.04 seconds
Started Jul 31 05:45:57 PM PDT 24
Finished Jul 31 05:45:58 PM PDT 24
Peak memory 206964 kb
Host smart-4cddb1bb-aa86-4bea-94cb-22a356c346cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25091
01737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.2509101737
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1649104534
Short name T1575
Test name
Test status
Simulation time 166958819 ps
CPU time 0.89 seconds
Started Jul 31 05:45:56 PM PDT 24
Finished Jul 31 05:45:57 PM PDT 24
Peak memory 206924 kb
Host smart-e730565e-c4e0-49a0-8378-589b249a0299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16491
04534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1649104534
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.560085022
Short name T1480
Test name
Test status
Simulation time 1011821664 ps
CPU time 2.6 seconds
Started Jul 31 05:45:58 PM PDT 24
Finished Jul 31 05:46:00 PM PDT 24
Peak memory 207068 kb
Host smart-85039b39-9c81-4f8c-95bb-dd9c087caa48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56008
5022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.560085022
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.135111508
Short name T2104
Test name
Test status
Simulation time 6048830728 ps
CPU time 60.36 seconds
Started Jul 31 05:45:55 PM PDT 24
Finished Jul 31 05:46:55 PM PDT 24
Peak memory 207268 kb
Host smart-7d72bae7-4c78-4aa1-ac58-b61b44c0aee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13511
1508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.135111508
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.198592760
Short name T907
Test name
Test status
Simulation time 6138844491 ps
CPU time 40.8 seconds
Started Jul 31 05:45:54 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 207248 kb
Host smart-f06a4939-259d-4e40-b245-93bd86f6b50f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198592760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_host
_handshake.198592760
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.2580151001
Short name T764
Test name
Test status
Simulation time 34891647 ps
CPU time 0.63 seconds
Started Jul 31 05:40:15 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 207020 kb
Host smart-73a1c1f8-2c9e-4fb3-b969-1def387871d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2580151001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2580151001
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2331024873
Short name T1713
Test name
Test status
Simulation time 3998252377 ps
CPU time 5.89 seconds
Started Jul 31 05:40:03 PM PDT 24
Finished Jul 31 05:40:09 PM PDT 24
Peak memory 207124 kb
Host smart-63dec336-fc0c-4b94-91b0-2138fdc0de95
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331024873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.2331024873
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.3660493504
Short name T516
Test name
Test status
Simulation time 13334653744 ps
CPU time 15.26 seconds
Started Jul 31 05:40:04 PM PDT 24
Finished Jul 31 05:40:19 PM PDT 24
Peak memory 207200 kb
Host smart-5edd86ac-c524-4844-8ab6-bbcc59793e4f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660493504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3660493504
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2284030951
Short name T1948
Test name
Test status
Simulation time 23342084086 ps
CPU time 27.31 seconds
Started Jul 31 05:40:04 PM PDT 24
Finished Jul 31 05:40:31 PM PDT 24
Peak memory 207240 kb
Host smart-55e057cc-15ff-4644-85ef-e10ee234d0b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284030951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.2284030951
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1542512433
Short name T1835
Test name
Test status
Simulation time 207261867 ps
CPU time 0.91 seconds
Started Jul 31 05:40:07 PM PDT 24
Finished Jul 31 05:40:08 PM PDT 24
Peak memory 207044 kb
Host smart-12dc91d3-67d3-42eb-a42a-285acae29d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15425
12433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1542512433
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.480268814
Short name T48
Test name
Test status
Simulation time 179200792 ps
CPU time 0.99 seconds
Started Jul 31 05:40:01 PM PDT 24
Finished Jul 31 05:40:02 PM PDT 24
Peak memory 206964 kb
Host smart-2eeefd40-fc1b-4301-b6e8-3b145236ada4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48026
8814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.480268814
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.636292122
Short name T57
Test name
Test status
Simulation time 161303103 ps
CPU time 1 seconds
Started Jul 31 05:40:02 PM PDT 24
Finished Jul 31 05:40:03 PM PDT 24
Peak memory 206992 kb
Host smart-7b93ecf3-34aa-4d15-9ae5-d2617592ec4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63629
2122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.636292122
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.4147098633
Short name T941
Test name
Test status
Simulation time 143698235 ps
CPU time 0.79 seconds
Started Jul 31 05:40:03 PM PDT 24
Finished Jul 31 05:40:04 PM PDT 24
Peak memory 206964 kb
Host smart-1551349c-eb77-4a35-ae58-8bf7dd8776f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41470
98633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.4147098633
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.994841976
Short name T2624
Test name
Test status
Simulation time 442418374 ps
CPU time 1.6 seconds
Started Jul 31 05:40:07 PM PDT 24
Finished Jul 31 05:40:09 PM PDT 24
Peak memory 206980 kb
Host smart-23af9443-4ffc-49ee-922b-d4aaa54d4524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99484
1976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.994841976
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.818827604
Short name T1809
Test name
Test status
Simulation time 908864015 ps
CPU time 2.33 seconds
Started Jul 31 05:40:04 PM PDT 24
Finished Jul 31 05:40:06 PM PDT 24
Peak memory 207068 kb
Host smart-7f4e3b1b-d15a-4e39-bd58-7bc4f32dfa0c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=818827604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.818827604
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2416409766
Short name T1212
Test name
Test status
Simulation time 19816776121 ps
CPU time 43.39 seconds
Started Jul 31 05:40:07 PM PDT 24
Finished Jul 31 05:40:50 PM PDT 24
Peak memory 207272 kb
Host smart-351e52e9-e372-4f1b-856d-f22945c43618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24164
09766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2416409766
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_device_timeout.1307072075
Short name T2604
Test name
Test status
Simulation time 840668460 ps
CPU time 5.48 seconds
Started Jul 31 05:40:03 PM PDT 24
Finished Jul 31 05:40:09 PM PDT 24
Peak memory 207088 kb
Host smart-47300ba0-d1ca-453c-ac9b-0bf41dda7ef3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307072075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.1307072075
Directory /workspace/4.usbdev_device_timeout/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.3040811682
Short name T2361
Test name
Test status
Simulation time 354434519 ps
CPU time 1.28 seconds
Started Jul 31 05:40:03 PM PDT 24
Finished Jul 31 05:40:05 PM PDT 24
Peak memory 206948 kb
Host smart-90a702d9-282b-4475-ad1b-54e51b208f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30408
11682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.3040811682
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.4062593141
Short name T777
Test name
Test status
Simulation time 142292054 ps
CPU time 0.95 seconds
Started Jul 31 05:40:04 PM PDT 24
Finished Jul 31 05:40:05 PM PDT 24
Peak memory 206936 kb
Host smart-20662b4f-3802-424d-8cc0-49431bfd9a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40625
93141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.4062593141
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.599246048
Short name T766
Test name
Test status
Simulation time 40848670 ps
CPU time 0.81 seconds
Started Jul 31 05:40:02 PM PDT 24
Finished Jul 31 05:40:03 PM PDT 24
Peak memory 206944 kb
Host smart-c16ccd71-3c22-4314-a58b-c338fab45d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59924
6048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.599246048
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.104947932
Short name T695
Test name
Test status
Simulation time 960269329 ps
CPU time 2.58 seconds
Started Jul 31 05:40:00 PM PDT 24
Finished Jul 31 05:40:03 PM PDT 24
Peak memory 207128 kb
Host smart-f77615d4-d208-48df-ac89-765635beb458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10494
7932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.104947932
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3919622696
Short name T2357
Test name
Test status
Simulation time 178150468 ps
CPU time 2.12 seconds
Started Jul 31 05:40:01 PM PDT 24
Finished Jul 31 05:40:03 PM PDT 24
Peak memory 207016 kb
Host smart-27c46b64-bb86-42d0-8990-6e7b7a3a3736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39196
22696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3919622696
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2085968235
Short name T330
Test name
Test status
Simulation time 107245575294 ps
CPU time 175.34 seconds
Started Jul 31 05:40:04 PM PDT 24
Finished Jul 31 05:43:00 PM PDT 24
Peak memory 207184 kb
Host smart-d16cd6ef-818c-4701-8b79-c0844bcb890d
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2085968235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2085968235
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.1629461395
Short name T2244
Test name
Test status
Simulation time 103425102923 ps
CPU time 184.15 seconds
Started Jul 31 05:40:04 PM PDT 24
Finished Jul 31 05:43:08 PM PDT 24
Peak memory 207156 kb
Host smart-ae890266-ea07-40db-ad26-0ec1e83d9a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629461395 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.1629461395
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.3028823196
Short name T821
Test name
Test status
Simulation time 105094930987 ps
CPU time 177.52 seconds
Started Jul 31 05:40:01 PM PDT 24
Finished Jul 31 05:42:58 PM PDT 24
Peak memory 207192 kb
Host smart-8a19fcf9-0730-4efa-84fa-7a24e87b27ac
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3028823196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.3028823196
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.2591187530
Short name T1518
Test name
Test status
Simulation time 98113963599 ps
CPU time 182.63 seconds
Started Jul 31 05:40:05 PM PDT 24
Finished Jul 31 05:43:08 PM PDT 24
Peak memory 207212 kb
Host smart-ecfc7582-feca-4e03-b8a3-0a24705082f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591187530 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.2591187530
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.4161794530
Short name T902
Test name
Test status
Simulation time 93131013433 ps
CPU time 139.79 seconds
Started Jul 31 05:40:04 PM PDT 24
Finished Jul 31 05:42:24 PM PDT 24
Peak memory 207228 kb
Host smart-d5f2196a-8a11-4f76-9c8d-c71c8dcddc50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617
94530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.4161794530
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.458256995
Short name T2729
Test name
Test status
Simulation time 226761336 ps
CPU time 1.14 seconds
Started Jul 31 05:40:03 PM PDT 24
Finished Jul 31 05:40:05 PM PDT 24
Peak memory 215276 kb
Host smart-3571b216-cbd5-48d8-a130-41eed2b4fc7b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=458256995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.458256995
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1842265412
Short name T2493
Test name
Test status
Simulation time 143745480 ps
CPU time 0.8 seconds
Started Jul 31 05:40:01 PM PDT 24
Finished Jul 31 05:40:02 PM PDT 24
Peak memory 206932 kb
Host smart-be20600d-39f1-45b9-b18a-b681c54ef3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422
65412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1842265412
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3039410724
Short name T1603
Test name
Test status
Simulation time 253509729 ps
CPU time 1.06 seconds
Started Jul 31 05:40:03 PM PDT 24
Finished Jul 31 05:40:04 PM PDT 24
Peak memory 207016 kb
Host smart-f0307d94-f5c8-451a-8fe8-7b46cd02bfd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30394
10724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3039410724
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.4174793787
Short name T79
Test name
Test status
Simulation time 4905424911 ps
CPU time 53.77 seconds
Started Jul 31 05:40:02 PM PDT 24
Finished Jul 31 05:40:56 PM PDT 24
Peak memory 216880 kb
Host smart-1a6c91d0-ea6e-4296-a70e-accaa54e728f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4174793787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.4174793787
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.696843587
Short name T788
Test name
Test status
Simulation time 7523580481 ps
CPU time 87.11 seconds
Started Jul 31 05:40:03 PM PDT 24
Finished Jul 31 05:41:30 PM PDT 24
Peak memory 207196 kb
Host smart-e69df49a-3d5c-4cfa-bacc-51f09007ed46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=696843587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.696843587
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.281709746
Short name T54
Test name
Test status
Simulation time 177618310 ps
CPU time 0.96 seconds
Started Jul 31 05:40:10 PM PDT 24
Finished Jul 31 05:40:11 PM PDT 24
Peak memory 206992 kb
Host smart-6d7850f0-ce0f-4305-9ab1-c348149c5933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28170
9746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.281709746
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.161759574
Short name T365
Test name
Test status
Simulation time 23330569817 ps
CPU time 26.15 seconds
Started Jul 31 05:40:06 PM PDT 24
Finished Jul 31 05:40:32 PM PDT 24
Peak memory 207208 kb
Host smart-846b1ea5-936a-4b57-9fbb-4e909211cb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16175
9574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.161759574
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.365968783
Short name T348
Test name
Test status
Simulation time 3295188944 ps
CPU time 4.75 seconds
Started Jul 31 05:40:09 PM PDT 24
Finished Jul 31 05:40:14 PM PDT 24
Peak memory 207152 kb
Host smart-21630cc0-6ceb-40a6-bb98-82124bc4b8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36596
8783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.365968783
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.293953711
Short name T2730
Test name
Test status
Simulation time 10241164150 ps
CPU time 73.31 seconds
Started Jul 31 05:40:09 PM PDT 24
Finished Jul 31 05:41:22 PM PDT 24
Peak memory 217116 kb
Host smart-9c61f285-dbfc-4db2-9016-0018db5ee884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29395
3711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.293953711
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2131910611
Short name T1701
Test name
Test status
Simulation time 6540082945 ps
CPU time 187.56 seconds
Started Jul 31 05:40:10 PM PDT 24
Finished Jul 31 05:43:18 PM PDT 24
Peak memory 215372 kb
Host smart-e10b2415-e805-470a-b027-4151f36128bb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2131910611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2131910611
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.4010921838
Short name T489
Test name
Test status
Simulation time 246249367 ps
CPU time 1 seconds
Started Jul 31 05:40:08 PM PDT 24
Finished Jul 31 05:40:09 PM PDT 24
Peak memory 207000 kb
Host smart-99c1aa8b-9126-43f4-9d8c-54efb067a88e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4010921838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.4010921838
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1507040070
Short name T1884
Test name
Test status
Simulation time 186149725 ps
CPU time 0.92 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:16 PM PDT 24
Peak memory 207000 kb
Host smart-456b5c63-6320-479a-9db5-e36b22af34ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15070
40070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1507040070
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2013974990
Short name T1323
Test name
Test status
Simulation time 5468283791 ps
CPU time 155.67 seconds
Started Jul 31 05:40:15 PM PDT 24
Finished Jul 31 05:42:50 PM PDT 24
Peak memory 215356 kb
Host smart-ecd7984d-97a1-4c55-aa40-9103bc531929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20139
74990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2013974990
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.773928628
Short name T1241
Test name
Test status
Simulation time 3768207666 ps
CPU time 104.9 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 215388 kb
Host smart-16ed5d20-8819-40ec-9081-80ffbd2e246a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=773928628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.773928628
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.3809525892
Short name T1414
Test name
Test status
Simulation time 156960810 ps
CPU time 0.86 seconds
Started Jul 31 05:40:11 PM PDT 24
Finished Jul 31 05:40:12 PM PDT 24
Peak memory 207000 kb
Host smart-f57bf1ed-e8fb-432a-81f6-46a59b304133
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3809525892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.3809525892
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1832908498
Short name T1418
Test name
Test status
Simulation time 146852183 ps
CPU time 0.87 seconds
Started Jul 31 05:40:09 PM PDT 24
Finished Jul 31 05:40:10 PM PDT 24
Peak memory 207008 kb
Host smart-b96f3df3-0826-4399-8bf1-210ed953f5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18329
08498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1832908498
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2980376998
Short name T2785
Test name
Test status
Simulation time 190943145 ps
CPU time 0.91 seconds
Started Jul 31 05:40:09 PM PDT 24
Finished Jul 31 05:40:10 PM PDT 24
Peak memory 206996 kb
Host smart-05a26f10-e67a-42a6-85c0-b67d7222c11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29803
76998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2980376998
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2322189903
Short name T2611
Test name
Test status
Simulation time 192583235 ps
CPU time 0.93 seconds
Started Jul 31 05:40:08 PM PDT 24
Finished Jul 31 05:40:10 PM PDT 24
Peak memory 206920 kb
Host smart-b406558b-21f6-4dd3-8f4e-ddf570495c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23221
89903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2322189903
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1227093595
Short name T955
Test name
Test status
Simulation time 179181226 ps
CPU time 0.9 seconds
Started Jul 31 05:40:09 PM PDT 24
Finished Jul 31 05:40:10 PM PDT 24
Peak memory 207048 kb
Host smart-7d98d4b9-8428-43ff-baf6-a8550f6b070f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12270
93595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1227093595
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.3134224338
Short name T774
Test name
Test status
Simulation time 182215345 ps
CPU time 0.92 seconds
Started Jul 31 05:40:10 PM PDT 24
Finished Jul 31 05:40:11 PM PDT 24
Peak memory 207000 kb
Host smart-71dc9f6d-a4d2-461f-aef8-5e8cdb618496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31342
24338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3134224338
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.3568410849
Short name T1747
Test name
Test status
Simulation time 157098956 ps
CPU time 0.88 seconds
Started Jul 31 05:40:10 PM PDT 24
Finished Jul 31 05:40:11 PM PDT 24
Peak memory 207036 kb
Host smart-9e88ce6c-1092-4e8f-8b2b-61926fa9a2c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35684
10849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.3568410849
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.987396183
Short name T2617
Test name
Test status
Simulation time 225386893 ps
CPU time 1.01 seconds
Started Jul 31 05:40:08 PM PDT 24
Finished Jul 31 05:40:09 PM PDT 24
Peak memory 207024 kb
Host smart-9399f518-0dce-47d1-9855-7eb618733383
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=987396183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.987396183
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.738040345
Short name T145
Test name
Test status
Simulation time 186145736 ps
CPU time 1.02 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 207000 kb
Host smart-fcdd4fe9-b383-4a4c-a5bc-33c0e635403b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73804
0345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.738040345
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.4216410162
Short name T1367
Test name
Test status
Simulation time 148470875 ps
CPU time 0.82 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 206964 kb
Host smart-85aabdd7-b9b4-44db-9a50-4b3bea148833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42164
10162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.4216410162
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3379110783
Short name T1841
Test name
Test status
Simulation time 35891308 ps
CPU time 0.7 seconds
Started Jul 31 05:40:10 PM PDT 24
Finished Jul 31 05:40:11 PM PDT 24
Peak memory 206948 kb
Host smart-1b128052-7a81-4238-905e-038b661a57e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33791
10783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3379110783
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.2060287690
Short name T1048
Test name
Test status
Simulation time 9768245362 ps
CPU time 25.81 seconds
Started Jul 31 05:40:07 PM PDT 24
Finished Jul 31 05:40:33 PM PDT 24
Peak memory 220108 kb
Host smart-434e462d-200d-4c13-8d33-986b06a0a133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20602
87690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.2060287690
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1622803660
Short name T2629
Test name
Test status
Simulation time 184209022 ps
CPU time 0.89 seconds
Started Jul 31 05:40:13 PM PDT 24
Finished Jul 31 05:40:14 PM PDT 24
Peak memory 206996 kb
Host smart-832c8b7a-8aa8-4dda-b508-8f0004177570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
03660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1622803660
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1442765207
Short name T1386
Test name
Test status
Simulation time 197216097 ps
CPU time 0.94 seconds
Started Jul 31 05:40:10 PM PDT 24
Finished Jul 31 05:40:11 PM PDT 24
Peak memory 206984 kb
Host smart-d18be2a4-4f3e-439d-85fa-64b96460a39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14427
65207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1442765207
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.813887826
Short name T2051
Test name
Test status
Simulation time 8992927259 ps
CPU time 250.66 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:44:25 PM PDT 24
Peak memory 215400 kb
Host smart-4efc624a-a478-4932-8d18-2fe84271fe5c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=813887826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.813887826
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2144751038
Short name T163
Test name
Test status
Simulation time 17592671389 ps
CPU time 152.9 seconds
Started Jul 31 05:40:08 PM PDT 24
Finished Jul 31 05:42:41 PM PDT 24
Peak memory 218704 kb
Host smart-6a782629-bd83-4d72-bee8-7e8585809563
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2144751038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2144751038
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1113612058
Short name T2270
Test name
Test status
Simulation time 6614176581 ps
CPU time 96.85 seconds
Started Jul 31 05:40:07 PM PDT 24
Finished Jul 31 05:41:44 PM PDT 24
Peak memory 215364 kb
Host smart-1ba1d5fa-89ee-4732-8a1f-85826d1c27f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113612058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1113612058
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.337507339
Short name T743
Test name
Test status
Simulation time 179704934 ps
CPU time 0.87 seconds
Started Jul 31 05:40:13 PM PDT 24
Finished Jul 31 05:40:14 PM PDT 24
Peak memory 206996 kb
Host smart-b330c9c5-73fe-4e38-8f29-81263a3f6ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33750
7339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.337507339
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3129099245
Short name T1793
Test name
Test status
Simulation time 212364090 ps
CPU time 1.07 seconds
Started Jul 31 05:40:11 PM PDT 24
Finished Jul 31 05:40:12 PM PDT 24
Peak memory 206988 kb
Host smart-6e2982c5-061a-4760-b5a3-119d7e03da55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31290
99245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3129099245
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.1882662848
Short name T203
Test name
Test status
Simulation time 224961400 ps
CPU time 0.94 seconds
Started Jul 31 05:40:07 PM PDT 24
Finished Jul 31 05:40:08 PM PDT 24
Peak memory 206968 kb
Host smart-bbb6d2b9-50b5-447c-960f-0c144707180b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18826
62848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.1882662848
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.404463973
Short name T71
Test name
Test status
Simulation time 201908100 ps
CPU time 0.92 seconds
Started Jul 31 05:40:10 PM PDT 24
Finished Jul 31 05:40:11 PM PDT 24
Peak memory 207028 kb
Host smart-ad9f39b1-f12b-4e65-9b21-6d3ef16febec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40446
3973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.404463973
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.1857244857
Short name T197
Test name
Test status
Simulation time 634208107 ps
CPU time 1.62 seconds
Started Jul 31 05:40:13 PM PDT 24
Finished Jul 31 05:40:14 PM PDT 24
Peak memory 224056 kb
Host smart-024ebf3c-b30d-44d5-bdb9-b68ee028a657
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1857244857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.1857244857
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.4202259461
Short name T1930
Test name
Test status
Simulation time 429926745 ps
CPU time 1.45 seconds
Started Jul 31 05:40:10 PM PDT 24
Finished Jul 31 05:40:12 PM PDT 24
Peak memory 206964 kb
Host smart-f81ad76a-a5ec-425f-9fb7-9e92d9e0a14a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42022
59461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.4202259461
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.522052662
Short name T2515
Test name
Test status
Simulation time 303003564 ps
CPU time 1.06 seconds
Started Jul 31 05:40:09 PM PDT 24
Finished Jul 31 05:40:10 PM PDT 24
Peak memory 206988 kb
Host smart-15313a47-362f-43d6-885b-c741119306b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52205
2662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.522052662
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1766685485
Short name T436
Test name
Test status
Simulation time 173988200 ps
CPU time 0.85 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 206968 kb
Host smart-364953f2-be09-485c-a706-451fcbd52168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17666
85485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1766685485
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2788689068
Short name T1963
Test name
Test status
Simulation time 144475878 ps
CPU time 0.86 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 207020 kb
Host smart-f67ef9fe-56b4-4191-a87c-4c1a7887353b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27886
89068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2788689068
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3206787728
Short name T1892
Test name
Test status
Simulation time 203926835 ps
CPU time 1 seconds
Started Jul 31 05:40:15 PM PDT 24
Finished Jul 31 05:40:16 PM PDT 24
Peak memory 206992 kb
Host smart-bae16cb0-bf9b-49b0-9d7f-508e46c78409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32067
87728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3206787728
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3362846334
Short name T2713
Test name
Test status
Simulation time 5111332839 ps
CPU time 42.57 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:57 PM PDT 24
Peak memory 216712 kb
Host smart-7a6b18fe-b1a6-44c5-9b0f-ccbaea0c4b77
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3362846334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3362846334
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.4230753659
Short name T554
Test name
Test status
Simulation time 154383974 ps
CPU time 0.89 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 207024 kb
Host smart-9b360b57-30f7-466f-b19d-70a32bcb0b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42307
53659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.4230753659
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1469726940
Short name T2333
Test name
Test status
Simulation time 179374091 ps
CPU time 0.92 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 207036 kb
Host smart-8272d6de-27a4-47b0-904d-391a6dfee36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14697
26940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1469726940
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.1033773896
Short name T2680
Test name
Test status
Simulation time 702500733 ps
CPU time 1.86 seconds
Started Jul 31 05:40:21 PM PDT 24
Finished Jul 31 05:40:23 PM PDT 24
Peak memory 206968 kb
Host smart-a20d87ce-d49b-4e7a-b4cb-4d5ac74d5317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10337
73896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.1033773896
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.2146542439
Short name T1004
Test name
Test status
Simulation time 6165043789 ps
CPU time 185.57 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:43:19 PM PDT 24
Peak memory 215464 kb
Host smart-a80ca987-206f-4742-8c7e-0f9c926ea7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21465
42439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2146542439
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.133023470
Short name T69
Test name
Test status
Simulation time 9983656779 ps
CPU time 273.23 seconds
Started Jul 31 05:40:21 PM PDT 24
Finished Jul 31 05:44:54 PM PDT 24
Peak memory 215440 kb
Host smart-f947bae9-7b2c-493c-af04-e2ab2e274c8c
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133023470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.133023470
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.2028928086
Short name T2732
Test name
Test status
Simulation time 5250509958 ps
CPU time 45.49 seconds
Started Jul 31 05:40:03 PM PDT 24
Finished Jul 31 05:40:49 PM PDT 24
Peak memory 207268 kb
Host smart-a872400d-3d7c-4ea4-a979-ce6335158527
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028928086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host
_handshake.2028928086
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.1305693000
Short name T732
Test name
Test status
Simulation time 38032986 ps
CPU time 0.65 seconds
Started Jul 31 05:46:10 PM PDT 24
Finished Jul 31 05:46:11 PM PDT 24
Peak memory 206980 kb
Host smart-376801f2-7342-4d54-9481-7e4455af8499
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1305693000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.1305693000
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3873024113
Short name T771
Test name
Test status
Simulation time 4210047996 ps
CPU time 6.5 seconds
Started Jul 31 05:45:57 PM PDT 24
Finished Jul 31 05:46:03 PM PDT 24
Peak memory 207184 kb
Host smart-075ee99d-353b-4570-8a0e-81f2f362dd3d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873024113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.3873024113
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1802035080
Short name T688
Test name
Test status
Simulation time 13369197857 ps
CPU time 16.15 seconds
Started Jul 31 05:45:57 PM PDT 24
Finished Jul 31 05:46:13 PM PDT 24
Peak memory 207192 kb
Host smart-7c849cd5-7244-4c05-a8a5-52ec44d7414e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802035080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1802035080
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.4172477292
Short name T1840
Test name
Test status
Simulation time 23322116634 ps
CPU time 31.6 seconds
Started Jul 31 05:45:59 PM PDT 24
Finished Jul 31 05:46:30 PM PDT 24
Peak memory 207216 kb
Host smart-eb1e06ea-8814-4881-ad18-649aa5c7405c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172477292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.4172477292
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.911479513
Short name T504
Test name
Test status
Simulation time 162941348 ps
CPU time 0.94 seconds
Started Jul 31 05:46:00 PM PDT 24
Finished Jul 31 05:46:01 PM PDT 24
Peak memory 206984 kb
Host smart-020fe4fa-62a8-4338-9ab5-a4fb355dd846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91147
9513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.911479513
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.156903580
Short name T1896
Test name
Test status
Simulation time 196578201 ps
CPU time 0.88 seconds
Started Jul 31 05:45:59 PM PDT 24
Finished Jul 31 05:46:00 PM PDT 24
Peak memory 206960 kb
Host smart-b77efc48-f945-4461-aad0-f340921f12e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15690
3580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.156903580
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.2348962121
Short name T1810
Test name
Test status
Simulation time 527338284 ps
CPU time 1.65 seconds
Started Jul 31 05:45:55 PM PDT 24
Finished Jul 31 05:45:57 PM PDT 24
Peak memory 207036 kb
Host smart-02f3f14c-ecb4-40fe-91b9-6c38f28089d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23489
62121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.2348962121
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.1265250667
Short name T2346
Test name
Test status
Simulation time 381952404 ps
CPU time 1.27 seconds
Started Jul 31 05:45:56 PM PDT 24
Finished Jul 31 05:45:58 PM PDT 24
Peak memory 206968 kb
Host smart-9d3a58cc-0bbd-4779-9690-93bf01613ea8
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1265250667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.1265250667
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.561584962
Short name T2811
Test name
Test status
Simulation time 8581876554 ps
CPU time 20.86 seconds
Started Jul 31 05:45:58 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 207216 kb
Host smart-608f66c5-fd56-4d01-a2f0-59589a51cf5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56158
4962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.561584962
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_device_timeout.2522666648
Short name T1172
Test name
Test status
Simulation time 2045368089 ps
CPU time 16.9 seconds
Started Jul 31 05:45:58 PM PDT 24
Finished Jul 31 05:46:15 PM PDT 24
Peak memory 207076 kb
Host smart-8f79f97b-a9a2-4179-a5d0-fc6f54c9ef0f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522666648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.2522666648
Directory /workspace/40.usbdev_device_timeout/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.639572568
Short name T2673
Test name
Test status
Simulation time 535203303 ps
CPU time 1.68 seconds
Started Jul 31 05:46:03 PM PDT 24
Finished Jul 31 05:46:05 PM PDT 24
Peak memory 206976 kb
Host smart-626f89f5-a9f1-4fd7-9ef2-dc4abe55f5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63957
2568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.639572568
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.469654695
Short name T869
Test name
Test status
Simulation time 151515946 ps
CPU time 0.88 seconds
Started Jul 31 05:46:07 PM PDT 24
Finished Jul 31 05:46:08 PM PDT 24
Peak memory 206936 kb
Host smart-f67b2625-e0ac-493c-8ace-719bf3b612df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46965
4695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.469654695
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.199032252
Short name T1618
Test name
Test status
Simulation time 39999323 ps
CPU time 0.73 seconds
Started Jul 31 05:46:04 PM PDT 24
Finished Jul 31 05:46:05 PM PDT 24
Peak memory 206956 kb
Host smart-7a6d9c57-2f0c-4795-b73e-314d6d74cf5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19903
2252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.199032252
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.4273028409
Short name T1113
Test name
Test status
Simulation time 829622865 ps
CPU time 2.45 seconds
Started Jul 31 05:46:02 PM PDT 24
Finished Jul 31 05:46:05 PM PDT 24
Peak memory 207080 kb
Host smart-5ca8d4cb-cc3b-4335-b872-cca0d1a3408e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42730
28409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.4273028409
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3517052055
Short name T1737
Test name
Test status
Simulation time 160624487 ps
CPU time 1.59 seconds
Started Jul 31 05:46:04 PM PDT 24
Finished Jul 31 05:46:05 PM PDT 24
Peak memory 207056 kb
Host smart-fe5cf6a2-5aad-4c84-b9ae-05f4ac1ef0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35170
52055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3517052055
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.439514538
Short name T1104
Test name
Test status
Simulation time 240468548 ps
CPU time 1.25 seconds
Started Jul 31 05:45:59 PM PDT 24
Finished Jul 31 05:46:01 PM PDT 24
Peak memory 215280 kb
Host smart-0eab3107-582b-455c-b691-c8ec74f148f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=439514538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.439514538
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.4194092238
Short name T1341
Test name
Test status
Simulation time 146690517 ps
CPU time 0.89 seconds
Started Jul 31 05:46:05 PM PDT 24
Finished Jul 31 05:46:06 PM PDT 24
Peak memory 206864 kb
Host smart-513f19a9-0b4c-40f5-a8bf-bd272cfc1290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41940
92238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.4194092238
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.204062252
Short name T786
Test name
Test status
Simulation time 206501647 ps
CPU time 0.95 seconds
Started Jul 31 05:46:02 PM PDT 24
Finished Jul 31 05:46:03 PM PDT 24
Peak memory 206972 kb
Host smart-57ce0d00-397a-46f9-9701-e164a423011c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20406
2252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.204062252
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2457561638
Short name T20
Test name
Test status
Simulation time 10004819641 ps
CPU time 293.63 seconds
Started Jul 31 05:46:02 PM PDT 24
Finished Jul 31 05:50:56 PM PDT 24
Peak memory 215412 kb
Host smart-762dc186-41a9-4d07-b9e8-693fcf2f9cde
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2457561638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2457561638
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.2492054777
Short name T2097
Test name
Test status
Simulation time 12429262081 ps
CPU time 160.71 seconds
Started Jul 31 05:46:02 PM PDT 24
Finished Jul 31 05:48:42 PM PDT 24
Peak memory 207172 kb
Host smart-b585f94d-6b3c-4e9e-be7a-ebbe11c528a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2492054777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.2492054777
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.1203099189
Short name T1712
Test name
Test status
Simulation time 172771740 ps
CPU time 0.87 seconds
Started Jul 31 05:46:08 PM PDT 24
Finished Jul 31 05:46:09 PM PDT 24
Peak memory 206964 kb
Host smart-7eb02026-d26e-4fcf-85ce-88e527652521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12030
99189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1203099189
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3427891769
Short name T477
Test name
Test status
Simulation time 23348567366 ps
CPU time 30.83 seconds
Started Jul 31 05:46:08 PM PDT 24
Finished Jul 31 05:46:39 PM PDT 24
Peak memory 207188 kb
Host smart-f5f42e83-6545-48ea-afde-fa7800181ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34278
91769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3427891769
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2166086751
Short name T2133
Test name
Test status
Simulation time 3308908981 ps
CPU time 5.09 seconds
Started Jul 31 05:46:10 PM PDT 24
Finished Jul 31 05:46:15 PM PDT 24
Peak memory 207148 kb
Host smart-a74b2a0f-3810-4d9b-9764-159d459ad1d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21660
86751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2166086751
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.874843448
Short name T2347
Test name
Test status
Simulation time 7262384732 ps
CPU time 50.79 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:47:07 PM PDT 24
Peak memory 223564 kb
Host smart-e9b2a657-3494-4441-919b-77d62a561752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87484
3448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.874843448
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2676959371
Short name T1903
Test name
Test status
Simulation time 6561891110 ps
CPU time 51.42 seconds
Started Jul 31 05:46:02 PM PDT 24
Finished Jul 31 05:46:53 PM PDT 24
Peak memory 207176 kb
Host smart-8fca1203-2cea-4f8e-88b5-3384c3b1be65
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2676959371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2676959371
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2200556507
Short name T638
Test name
Test status
Simulation time 243927401 ps
CPU time 1.11 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 207028 kb
Host smart-7558848b-4926-4bbe-b8fd-2c4125f094a3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2200556507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2200556507
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1608838436
Short name T332
Test name
Test status
Simulation time 223550872 ps
CPU time 1.03 seconds
Started Jul 31 05:46:02 PM PDT 24
Finished Jul 31 05:46:04 PM PDT 24
Peak memory 206944 kb
Host smart-3f3dc99a-7903-4871-82ec-39f25d47e631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16088
38436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1608838436
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.874329837
Short name T2721
Test name
Test status
Simulation time 5665897710 ps
CPU time 58.61 seconds
Started Jul 31 05:46:03 PM PDT 24
Finished Jul 31 05:47:02 PM PDT 24
Peak memory 216780 kb
Host smart-dda06791-7f8e-414f-b468-4e9ccd186793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87432
9837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.874329837
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.4219125914
Short name T708
Test name
Test status
Simulation time 7399204561 ps
CPU time 75.4 seconds
Started Jul 31 05:46:01 PM PDT 24
Finished Jul 31 05:47:17 PM PDT 24
Peak memory 207204 kb
Host smart-1f422cc0-fe89-4a1d-a4f2-c6e4260b1815
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4219125914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.4219125914
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.870414940
Short name T1433
Test name
Test status
Simulation time 193759158 ps
CPU time 0.91 seconds
Started Jul 31 05:46:17 PM PDT 24
Finished Jul 31 05:46:18 PM PDT 24
Peak memory 206996 kb
Host smart-927a68d6-f0af-42cd-861a-796d9a47e40c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=870414940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.870414940
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3672233907
Short name T2542
Test name
Test status
Simulation time 168511259 ps
CPU time 0.85 seconds
Started Jul 31 05:46:04 PM PDT 24
Finished Jul 31 05:46:05 PM PDT 24
Peak memory 206984 kb
Host smart-64db857a-dc79-46e1-a957-62ad04cf2889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36722
33907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3672233907
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1378346361
Short name T1079
Test name
Test status
Simulation time 264104234 ps
CPU time 1.05 seconds
Started Jul 31 05:46:10 PM PDT 24
Finished Jul 31 05:46:12 PM PDT 24
Peak memory 206992 kb
Host smart-02f8081a-ae08-41f6-b0bf-9e7b04e195c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13783
46361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1378346361
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1374049403
Short name T2124
Test name
Test status
Simulation time 158834672 ps
CPU time 0.9 seconds
Started Jul 31 05:46:03 PM PDT 24
Finished Jul 31 05:46:04 PM PDT 24
Peak memory 207000 kb
Host smart-ecf8def1-0345-47e3-9a91-d18547120f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13740
49403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1374049403
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.804245445
Short name T1823
Test name
Test status
Simulation time 185919209 ps
CPU time 0.89 seconds
Started Jul 31 05:46:11 PM PDT 24
Finished Jul 31 05:46:12 PM PDT 24
Peak memory 206996 kb
Host smart-e1224657-c21c-432a-a643-22552cdca4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80424
5445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.804245445
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.239902677
Short name T982
Test name
Test status
Simulation time 223498453 ps
CPU time 0.91 seconds
Started Jul 31 05:46:11 PM PDT 24
Finished Jul 31 05:46:12 PM PDT 24
Peak memory 207020 kb
Host smart-2397bef1-c0ef-45ed-a769-64a30208d65a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990
2677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.239902677
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.80123059
Short name T1706
Test name
Test status
Simulation time 146628249 ps
CPU time 0.81 seconds
Started Jul 31 05:46:04 PM PDT 24
Finished Jul 31 05:46:05 PM PDT 24
Peak memory 206988 kb
Host smart-9a064bd8-f6b4-49cb-8261-67fc355cdd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80123
059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.80123059
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.652205792
Short name T2682
Test name
Test status
Simulation time 226933304 ps
CPU time 1.07 seconds
Started Jul 31 05:46:03 PM PDT 24
Finished Jul 31 05:46:04 PM PDT 24
Peak memory 206980 kb
Host smart-c279124d-801e-454b-aa87-0a1bdce77630
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=652205792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.652205792
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.608657025
Short name T1114
Test name
Test status
Simulation time 147572893 ps
CPU time 0.83 seconds
Started Jul 31 05:46:07 PM PDT 24
Finished Jul 31 05:46:07 PM PDT 24
Peak memory 207004 kb
Host smart-49551e33-8906-4894-a273-e6a5948c1f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60865
7025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.608657025
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3535618613
Short name T1071
Test name
Test status
Simulation time 45350174 ps
CPU time 0.69 seconds
Started Jul 31 05:46:06 PM PDT 24
Finished Jul 31 05:46:07 PM PDT 24
Peak memory 206984 kb
Host smart-a3711924-58ba-41e8-adb9-89813020f625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35356
18613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3535618613
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2851951143
Short name T2034
Test name
Test status
Simulation time 18090771251 ps
CPU time 49.55 seconds
Started Jul 31 05:46:05 PM PDT 24
Finished Jul 31 05:46:55 PM PDT 24
Peak memory 215452 kb
Host smart-58c5c2e6-437e-4650-ae53-6cb8567eed82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28519
51143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2851951143
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.1315323892
Short name T2014
Test name
Test status
Simulation time 195364083 ps
CPU time 0.96 seconds
Started Jul 31 05:46:02 PM PDT 24
Finished Jul 31 05:46:03 PM PDT 24
Peak memory 206980 kb
Host smart-880008e4-ff01-413f-8604-baf759743ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13153
23892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1315323892
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.3880027514
Short name T2486
Test name
Test status
Simulation time 176061663 ps
CPU time 0.93 seconds
Started Jul 31 05:46:05 PM PDT 24
Finished Jul 31 05:46:06 PM PDT 24
Peak memory 206920 kb
Host smart-378f17d3-86bd-4900-b904-fac5ea2b9cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38800
27514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.3880027514
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.402155059
Short name T2678
Test name
Test status
Simulation time 196451377 ps
CPU time 0.91 seconds
Started Jul 31 05:46:09 PM PDT 24
Finished Jul 31 05:46:10 PM PDT 24
Peak memory 206972 kb
Host smart-7b265b52-8973-454e-baeb-bfd17ba67c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40215
5059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.402155059
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.268763417
Short name T563
Test name
Test status
Simulation time 157926703 ps
CPU time 0.89 seconds
Started Jul 31 05:46:11 PM PDT 24
Finished Jul 31 05:46:12 PM PDT 24
Peak memory 206976 kb
Host smart-2c8030a5-e169-4efd-8982-ed7b5a615d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26876
3417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.268763417
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2938120200
Short name T214
Test name
Test status
Simulation time 151858306 ps
CPU time 0.87 seconds
Started Jul 31 05:46:12 PM PDT 24
Finished Jul 31 05:46:13 PM PDT 24
Peak memory 206960 kb
Host smart-23a7f102-d665-4033-8632-a1118bdadbd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
20200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2938120200
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.3546544235
Short name T2302
Test name
Test status
Simulation time 156874420 ps
CPU time 0.84 seconds
Started Jul 31 05:46:14 PM PDT 24
Finished Jul 31 05:46:15 PM PDT 24
Peak memory 206976 kb
Host smart-4f9f002a-b2e2-46ed-ac3d-db03489bb13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35465
44235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.3546544235
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2433709112
Short name T2532
Test name
Test status
Simulation time 180880201 ps
CPU time 0.85 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 206988 kb
Host smart-af02fadf-4745-478a-99be-e7bf2b4ff638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24337
09112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2433709112
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1012034344
Short name T1379
Test name
Test status
Simulation time 220888519 ps
CPU time 1 seconds
Started Jul 31 05:46:14 PM PDT 24
Finished Jul 31 05:46:15 PM PDT 24
Peak memory 207008 kb
Host smart-0b06edf6-a8d5-441d-815a-546ef7802a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10120
34344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1012034344
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.607156929
Short name T2398
Test name
Test status
Simulation time 5915934852 ps
CPU time 178.91 seconds
Started Jul 31 05:46:10 PM PDT 24
Finished Jul 31 05:49:09 PM PDT 24
Peak memory 215428 kb
Host smart-fdcfb8ab-5650-4412-a3de-ebfc8388c886
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=607156929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.607156929
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1169140701
Short name T616
Test name
Test status
Simulation time 170808808 ps
CPU time 0.93 seconds
Started Jul 31 05:46:12 PM PDT 24
Finished Jul 31 05:46:14 PM PDT 24
Peak memory 207036 kb
Host smart-34470ffe-5483-486a-bed1-bd9d04633018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11691
40701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1169140701
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.1204112926
Short name T954
Test name
Test status
Simulation time 182534403 ps
CPU time 0.92 seconds
Started Jul 31 05:46:17 PM PDT 24
Finished Jul 31 05:46:18 PM PDT 24
Peak memory 206972 kb
Host smart-f79a193b-9adb-46e0-b409-37cfe73e9555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12041
12926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1204112926
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.3443275417
Short name T1054
Test name
Test status
Simulation time 503043544 ps
CPU time 1.47 seconds
Started Jul 31 05:46:21 PM PDT 24
Finished Jul 31 05:46:23 PM PDT 24
Peak memory 206968 kb
Host smart-ffe3df7a-4fab-4873-8a0d-a91a40479648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34432
75417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.3443275417
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.3549282291
Short name T2202
Test name
Test status
Simulation time 5082749852 ps
CPU time 145.04 seconds
Started Jul 31 05:46:08 PM PDT 24
Finished Jul 31 05:48:33 PM PDT 24
Peak memory 215420 kb
Host smart-2ca4d65f-c9ca-4f70-b5b0-d6cee791c763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35492
82291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.3549282291
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.960238614
Short name T1873
Test name
Test status
Simulation time 1380235584 ps
CPU time 9.01 seconds
Started Jul 31 05:46:07 PM PDT 24
Finished Jul 31 05:46:16 PM PDT 24
Peak memory 207112 kb
Host smart-e13adb81-9335-48d6-8ab1-3ad8801a99c5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960238614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_host
_handshake.960238614
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1002791252
Short name T1394
Test name
Test status
Simulation time 36151658 ps
CPU time 0.69 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 207036 kb
Host smart-7a62daf2-0d9e-46f2-b2f2-2f47ebe04c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1002791252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1002791252
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2642182638
Short name T696
Test name
Test status
Simulation time 4215904627 ps
CPU time 6.17 seconds
Started Jul 31 05:46:07 PM PDT 24
Finished Jul 31 05:46:13 PM PDT 24
Peak memory 207160 kb
Host smart-5a29035f-6eb3-4c57-b7c0-f197e15caca8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642182638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.2642182638
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.171409808
Short name T451
Test name
Test status
Simulation time 13493597785 ps
CPU time 16 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 207248 kb
Host smart-b1569728-a3b9-47d2-8397-c97d5523de2f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=171409808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.171409808
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.1948051033
Short name T1074
Test name
Test status
Simulation time 23341952218 ps
CPU time 27.63 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:44 PM PDT 24
Peak memory 207176 kb
Host smart-b95da5f3-10e7-4fc3-9678-f4af3f5bf6be
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948051033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.1948051033
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3165377150
Short name T2410
Test name
Test status
Simulation time 210001329 ps
CPU time 0.96 seconds
Started Jul 31 05:46:10 PM PDT 24
Finished Jul 31 05:46:11 PM PDT 24
Peak memory 207056 kb
Host smart-41aed066-d466-411d-a30b-a4a1120ad03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31653
77150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3165377150
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.3170995905
Short name T316
Test name
Test status
Simulation time 147125274 ps
CPU time 0.85 seconds
Started Jul 31 05:46:09 PM PDT 24
Finished Jul 31 05:46:10 PM PDT 24
Peak memory 206948 kb
Host smart-c7c9fa53-dddd-40cd-a4e1-6b86ed1d7654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31709
95905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.3170995905
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.1624946061
Short name T1275
Test name
Test status
Simulation time 501785943 ps
CPU time 1.67 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 207016 kb
Host smart-cf7def12-1036-4ede-bb7b-03c7dc918630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16249
46061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1624946061
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.2498039634
Short name T1928
Test name
Test status
Simulation time 471757652 ps
CPU time 1.54 seconds
Started Jul 31 05:46:10 PM PDT 24
Finished Jul 31 05:46:12 PM PDT 24
Peak memory 206996 kb
Host smart-7c80ae82-c40e-4c48-8adb-00149e50acad
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2498039634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.2498039634
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1893370776
Short name T1552
Test name
Test status
Simulation time 20166804665 ps
CPU time 42.45 seconds
Started Jul 31 05:46:09 PM PDT 24
Finished Jul 31 05:46:51 PM PDT 24
Peak memory 207256 kb
Host smart-f51172d8-532d-467e-a81c-cbde06c212b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18933
70776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1893370776
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_device_timeout.2158347903
Short name T1425
Test name
Test status
Simulation time 2520716891 ps
CPU time 22.25 seconds
Started Jul 31 05:46:14 PM PDT 24
Finished Jul 31 05:46:37 PM PDT 24
Peak memory 207216 kb
Host smart-0ba00d45-0e28-4583-8554-0d7f3744bd9f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158347903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.2158347903
Directory /workspace/41.usbdev_device_timeout/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.218580345
Short name T75
Test name
Test status
Simulation time 403586408 ps
CPU time 1.36 seconds
Started Jul 31 05:46:08 PM PDT 24
Finished Jul 31 05:46:09 PM PDT 24
Peak memory 206964 kb
Host smart-fc732f6c-7644-4192-9d39-dd2542f33eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21858
0345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.218580345
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.3225226996
Short name T631
Test name
Test status
Simulation time 156403660 ps
CPU time 0.86 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 206996 kb
Host smart-bbe683da-30ec-4737-b009-9c076176942e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32252
26996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.3225226996
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.4024533185
Short name T1315
Test name
Test status
Simulation time 71082130 ps
CPU time 0.75 seconds
Started Jul 31 05:46:13 PM PDT 24
Finished Jul 31 05:46:14 PM PDT 24
Peak memory 206956 kb
Host smart-a5b38cf1-9c00-4461-a6ae-6379ef284ee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40245
33185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.4024533185
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3191182462
Short name T2154
Test name
Test status
Simulation time 933162755 ps
CPU time 2.87 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 207052 kb
Host smart-b7ce599e-3c57-49a1-8149-d09871274f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31911
82462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3191182462
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3957394197
Short name T1217
Test name
Test status
Simulation time 273987310 ps
CPU time 1.86 seconds
Started Jul 31 05:46:09 PM PDT 24
Finished Jul 31 05:46:11 PM PDT 24
Peak memory 207116 kb
Host smart-7c0ea5ef-0c5f-4164-82c5-5924593b47d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
94197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3957394197
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.2292654938
Short name T2608
Test name
Test status
Simulation time 207165001 ps
CPU time 1.13 seconds
Started Jul 31 05:46:14 PM PDT 24
Finished Jul 31 05:46:16 PM PDT 24
Peak memory 207076 kb
Host smart-972190e2-d3a1-4340-9fca-55ab67f63949
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2292654938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.2292654938
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.673443458
Short name T1449
Test name
Test status
Simulation time 134080920 ps
CPU time 0.84 seconds
Started Jul 31 05:46:10 PM PDT 24
Finished Jul 31 05:46:11 PM PDT 24
Peak memory 206940 kb
Host smart-dda7840f-9180-494b-9d1a-3361ff470960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67344
3458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.673443458
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3169071323
Short name T336
Test name
Test status
Simulation time 167653321 ps
CPU time 0.91 seconds
Started Jul 31 05:46:09 PM PDT 24
Finished Jul 31 05:46:10 PM PDT 24
Peak memory 207016 kb
Host smart-f3ed80d3-560e-4bf9-97db-67df9cb4d792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31690
71323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3169071323
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.1938103557
Short name T1949
Test name
Test status
Simulation time 5403359680 ps
CPU time 41.89 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 215444 kb
Host smart-2fdc676d-2b7d-43a3-b580-3342b360bec6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1938103557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.1938103557
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.1849593046
Short name T2703
Test name
Test status
Simulation time 8461869786 ps
CPU time 55.66 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:47:10 PM PDT 24
Peak memory 207208 kb
Host smart-5255c8c8-fcac-4d4c-b9dc-3e646719c63c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1849593046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.1849593046
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.154302816
Short name T1124
Test name
Test status
Simulation time 191561558 ps
CPU time 0.89 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:46:16 PM PDT 24
Peak memory 206988 kb
Host smart-612819df-f54b-415a-86aa-78388f148e86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15430
2816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.154302816
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.1332041320
Short name T2203
Test name
Test status
Simulation time 23331685185 ps
CPU time 27.6 seconds
Started Jul 31 05:46:12 PM PDT 24
Finished Jul 31 05:46:40 PM PDT 24
Peak memory 207196 kb
Host smart-945d0c66-8d6e-4384-86ed-b6b624906741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13320
41320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1332041320
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2970337258
Short name T2589
Test name
Test status
Simulation time 3300922278 ps
CPU time 4.9 seconds
Started Jul 31 05:46:14 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 207156 kb
Host smart-c001d61d-615f-4dc1-b91b-c81ddc0f3e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29703
37258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2970337258
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.887156364
Short name T1789
Test name
Test status
Simulation time 8662587448 ps
CPU time 250.34 seconds
Started Jul 31 05:46:10 PM PDT 24
Finished Jul 31 05:50:21 PM PDT 24
Peak memory 215400 kb
Host smart-a8329966-d447-4f3b-a467-606d687a7f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88715
6364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.887156364
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.1930024144
Short name T891
Test name
Test status
Simulation time 2944375824 ps
CPU time 84.56 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 215388 kb
Host smart-3fa8d27f-0783-4d53-ad9c-23256aba3eff
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1930024144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.1930024144
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1354729702
Short name T2490
Test name
Test status
Simulation time 265350955 ps
CPU time 1 seconds
Started Jul 31 05:46:14 PM PDT 24
Finished Jul 31 05:46:15 PM PDT 24
Peak memory 206988 kb
Host smart-6b87aafb-8ce0-4efc-84af-8c4c51c1c8bc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1354729702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1354729702
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1444012701
Short name T2790
Test name
Test status
Simulation time 195003033 ps
CPU time 0.91 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 207012 kb
Host smart-2a2ad888-ca25-4808-be85-a021d4f33018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
12701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1444012701
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.3736453996
Short name T1976
Test name
Test status
Simulation time 5130811312 ps
CPU time 59.01 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 216748 kb
Host smart-a04cd016-2486-437e-ac21-b51206c72815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37364
53996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.3736453996
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2145173792
Short name T2757
Test name
Test status
Simulation time 5903433480 ps
CPU time 182.35 seconds
Started Jul 31 05:46:14 PM PDT 24
Finished Jul 31 05:49:17 PM PDT 24
Peak memory 215388 kb
Host smart-38c9ff74-1bf1-46e4-b05c-bf428ac44354
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2145173792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2145173792
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.4286019662
Short name T811
Test name
Test status
Simulation time 150582594 ps
CPU time 0.86 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 207004 kb
Host smart-b6dc6b74-be9c-46df-8357-727d0f74943e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4286019662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.4286019662
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1983490611
Short name T414
Test name
Test status
Simulation time 216451873 ps
CPU time 0.92 seconds
Started Jul 31 05:46:23 PM PDT 24
Finished Jul 31 05:46:24 PM PDT 24
Peak memory 207008 kb
Host smart-2f64bf6f-06c7-4c3a-9f76-466dea8ce16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19834
90611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1983490611
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.3254728711
Short name T116
Test name
Test status
Simulation time 236288657 ps
CPU time 1.04 seconds
Started Jul 31 05:46:19 PM PDT 24
Finished Jul 31 05:46:20 PM PDT 24
Peak memory 207020 kb
Host smart-71a9ee9b-d5ee-400a-bd04-d637d5d0cef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32547
28711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3254728711
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.743033478
Short name T1937
Test name
Test status
Simulation time 186772928 ps
CPU time 0.91 seconds
Started Jul 31 05:46:13 PM PDT 24
Finished Jul 31 05:46:14 PM PDT 24
Peak memory 206980 kb
Host smart-fb352611-5de8-4c6f-a52f-fe0935594314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74303
3478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.743033478
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3661553111
Short name T313
Test name
Test status
Simulation time 169927646 ps
CPU time 0.95 seconds
Started Jul 31 05:46:17 PM PDT 24
Finished Jul 31 05:46:18 PM PDT 24
Peak memory 206972 kb
Host smart-afe28176-cac2-448e-b86b-bb35a50fbc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36615
53111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3661553111
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.122357388
Short name T851
Test name
Test status
Simulation time 209667083 ps
CPU time 0.95 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 206968 kb
Host smart-b9ece032-053c-4aea-a8d6-1431e6901f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12235
7388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.122357388
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3965054422
Short name T162
Test name
Test status
Simulation time 165328905 ps
CPU time 0.89 seconds
Started Jul 31 05:46:12 PM PDT 24
Finished Jul 31 05:46:13 PM PDT 24
Peak memory 206984 kb
Host smart-41e7f385-cb12-4b5a-95fc-2a47d86e1551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39650
54422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3965054422
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2396490962
Short name T2344
Test name
Test status
Simulation time 282047680 ps
CPU time 1.09 seconds
Started Jul 31 05:46:13 PM PDT 24
Finished Jul 31 05:46:14 PM PDT 24
Peak memory 206980 kb
Host smart-124193b1-a82a-47f2-a8f1-c6a3babf0f58
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2396490962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2396490962
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.4011300107
Short name T697
Test name
Test status
Simulation time 146689598 ps
CPU time 0.83 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 206988 kb
Host smart-fbee9d68-65be-4bf7-8253-b99e0a526516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40113
00107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.4011300107
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.592202988
Short name T1006
Test name
Test status
Simulation time 107970091 ps
CPU time 0.81 seconds
Started Jul 31 05:46:10 PM PDT 24
Finished Jul 31 05:46:11 PM PDT 24
Peak memory 206952 kb
Host smart-fbb13eb9-a1c8-4279-a6c8-13b626f886cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59220
2988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.592202988
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.3475281359
Short name T1923
Test name
Test status
Simulation time 6187341287 ps
CPU time 16.06 seconds
Started Jul 31 05:46:13 PM PDT 24
Finished Jul 31 05:46:29 PM PDT 24
Peak memory 215396 kb
Host smart-6964327a-860f-4736-9957-d768eedd7f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34752
81359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.3475281359
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.592137750
Short name T1483
Test name
Test status
Simulation time 180305642 ps
CPU time 0.92 seconds
Started Jul 31 05:46:13 PM PDT 24
Finished Jul 31 05:46:14 PM PDT 24
Peak memory 206976 kb
Host smart-9e9c4bf9-734b-46b1-a83f-699db41f497f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59213
7750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.592137750
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3335697548
Short name T2004
Test name
Test status
Simulation time 247752079 ps
CPU time 1.04 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:46:16 PM PDT 24
Peak memory 207016 kb
Host smart-a4b8c598-60e7-42ef-9b2c-3fc733ed3ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33356
97548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3335697548
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.860979721
Short name T1144
Test name
Test status
Simulation time 222925648 ps
CPU time 1.01 seconds
Started Jul 31 05:46:19 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 206988 kb
Host smart-a97932dd-91e3-46e7-b249-1ae512e148db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86097
9721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.860979721
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.712494616
Short name T928
Test name
Test status
Simulation time 149837545 ps
CPU time 0.83 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 206968 kb
Host smart-e6bce385-60f8-4359-bb8a-dacd1f037711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71249
4616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.712494616
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1930883520
Short name T1527
Test name
Test status
Simulation time 181927377 ps
CPU time 0.85 seconds
Started Jul 31 05:46:21 PM PDT 24
Finished Jul 31 05:46:22 PM PDT 24
Peak memory 206996 kb
Host smart-605d1d3b-586b-4f4f-aa21-4a3137a35196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19308
83520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1930883520
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1644106880
Short name T893
Test name
Test status
Simulation time 165824829 ps
CPU time 0.93 seconds
Started Jul 31 05:46:12 PM PDT 24
Finished Jul 31 05:46:13 PM PDT 24
Peak memory 206948 kb
Host smart-b715da73-bfd6-454f-944d-bc6cdbf96ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16441
06880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1644106880
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2926407266
Short name T711
Test name
Test status
Simulation time 151529365 ps
CPU time 0.82 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 207036 kb
Host smart-2d485a88-234c-483d-805e-1d67bea179cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29264
07266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2926407266
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.389754564
Short name T1192
Test name
Test status
Simulation time 271403166 ps
CPU time 1.2 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 206996 kb
Host smart-55a73fff-5c49-48b6-81a7-ccd1d073b9fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38975
4564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.389754564
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.4069309484
Short name T540
Test name
Test status
Simulation time 2889485624 ps
CPU time 88.01 seconds
Started Jul 31 05:46:14 PM PDT 24
Finished Jul 31 05:47:42 PM PDT 24
Peak memory 215364 kb
Host smart-03d41489-8d02-4f8c-95f7-d450b7103e8f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4069309484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.4069309484
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.584370460
Short name T2783
Test name
Test status
Simulation time 162926565 ps
CPU time 0.89 seconds
Started Jul 31 05:46:23 PM PDT 24
Finished Jul 31 05:46:24 PM PDT 24
Peak memory 206964 kb
Host smart-3aae3768-6b4f-4cfc-ba48-4eb78fa9ce29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58437
0460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.584370460
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.4292391514
Short name T1815
Test name
Test status
Simulation time 180419151 ps
CPU time 0.92 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 206996 kb
Host smart-483256cb-4e65-4a3b-86b0-19c070e47d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42923
91514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.4292391514
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.1041499097
Short name T1648
Test name
Test status
Simulation time 556660130 ps
CPU time 1.6 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 206968 kb
Host smart-4d7b86ac-128e-4551-93ba-7d96596a6e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10414
99097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.1041499097
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2750794231
Short name T1154
Test name
Test status
Simulation time 4424632467 ps
CPU time 43.1 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 215376 kb
Host smart-34ce1a1b-d88f-4ba3-a7cf-3fea85c7aec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27507
94231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2750794231
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.3210324541
Short name T2017
Test name
Test status
Simulation time 550596505 ps
CPU time 11.61 seconds
Started Jul 31 05:46:07 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 207120 kb
Host smart-c35694e1-136e-49aa-b5c5-fda3dac80e9d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210324541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.3210324541
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.1912462468
Short name T2081
Test name
Test status
Simulation time 45658600 ps
CPU time 0.67 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 207012 kb
Host smart-d42579d1-6bda-4db4-a8b4-5ac5673feeda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1912462468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.1912462468
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2694302736
Short name T765
Test name
Test status
Simulation time 4469272027 ps
CPU time 6.73 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:46:22 PM PDT 24
Peak memory 206832 kb
Host smart-d21ccfd2-0f8e-456f-99e9-3308126a887c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694302736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_disconnect.2694302736
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.625354266
Short name T2514
Test name
Test status
Simulation time 13358545922 ps
CPU time 16.56 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:46:41 PM PDT 24
Peak memory 207224 kb
Host smart-114d56db-9e01-4b46-8752-127470511c3d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=625354266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.625354266
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.183117484
Short name T685
Test name
Test status
Simulation time 23335689152 ps
CPU time 32.1 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:46:47 PM PDT 24
Peak memory 207216 kb
Host smart-1d6278b9-b674-46e0-9f53-a0cd91b40788
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183117484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_ao
n_wake_resume.183117484
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.4118930791
Short name T1043
Test name
Test status
Simulation time 185821611 ps
CPU time 0.93 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 207024 kb
Host smart-50590fa7-fa60-4975-acbc-2cc8ab821294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41189
30791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.4118930791
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.1406649097
Short name T1344
Test name
Test status
Simulation time 153783730 ps
CPU time 0.86 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:46:16 PM PDT 24
Peak memory 206960 kb
Host smart-04f1b92a-f03e-4f21-94d8-d41871100aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14066
49097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.1406649097
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2558475520
Short name T2445
Test name
Test status
Simulation time 199202496 ps
CPU time 1.03 seconds
Started Jul 31 05:46:13 PM PDT 24
Finished Jul 31 05:46:14 PM PDT 24
Peak memory 206936 kb
Host smart-26f28f86-beac-46d8-831e-0935967a0481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25584
75520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2558475520
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3403662284
Short name T556
Test name
Test status
Simulation time 679836281 ps
CPU time 2.04 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 206968 kb
Host smart-bbbc17c1-de1a-4ea4-81d3-c0b5457907c7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3403662284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3403662284
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.763933674
Short name T2466
Test name
Test status
Simulation time 19523559878 ps
CPU time 46.25 seconds
Started Jul 31 05:46:13 PM PDT 24
Finished Jul 31 05:47:00 PM PDT 24
Peak memory 207220 kb
Host smart-22dbe413-68b4-4672-8b7a-30541672956d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76393
3674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.763933674
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_device_timeout.242168483
Short name T342
Test name
Test status
Simulation time 1322810020 ps
CPU time 30.07 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:46:50 PM PDT 24
Peak memory 207104 kb
Host smart-36b8505b-b01c-4d4a-a813-9f8236b302b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242168483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.242168483
Directory /workspace/42.usbdev_device_timeout/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3838219157
Short name T1371
Test name
Test status
Simulation time 377353364 ps
CPU time 1.5 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:20 PM PDT 24
Peak memory 206968 kb
Host smart-dd4c8421-ffd1-4215-a16f-b556f05156b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38382
19157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3838219157
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.2091505353
Short name T2569
Test name
Test status
Simulation time 138964099 ps
CPU time 0.88 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 206940 kb
Host smart-60be40a6-27f1-446f-89ef-eddcced1a5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20915
05353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.2091505353
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.961083558
Short name T502
Test name
Test status
Simulation time 32885863 ps
CPU time 0.69 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 206960 kb
Host smart-1ab2f14b-94de-4615-8a1c-d1c2c0005d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96108
3558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.961083558
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2976074953
Short name T1404
Test name
Test status
Simulation time 760234994 ps
CPU time 2.15 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:18 PM PDT 24
Peak memory 207044 kb
Host smart-27993212-1b59-41e0-9419-0b552f6fc166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29760
74953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2976074953
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.236023667
Short name T948
Test name
Test status
Simulation time 273891545 ps
CPU time 1.43 seconds
Started Jul 31 05:46:15 PM PDT 24
Finished Jul 31 05:46:16 PM PDT 24
Peak memory 207044 kb
Host smart-b879acfd-ddec-4b14-b258-22a5f441d05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602
3667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.236023667
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.316951704
Short name T1040
Test name
Test status
Simulation time 225528808 ps
CPU time 1.18 seconds
Started Jul 31 05:46:21 PM PDT 24
Finished Jul 31 05:46:22 PM PDT 24
Peak memory 215284 kb
Host smart-e31758e8-f8d3-44df-9fab-759650d36c26
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=316951704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.316951704
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.652156393
Short name T693
Test name
Test status
Simulation time 139785729 ps
CPU time 0.81 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 206592 kb
Host smart-d72a92bb-a4f9-4d31-a91b-bae3aa57f5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65215
6393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.652156393
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2070972320
Short name T2711
Test name
Test status
Simulation time 221074172 ps
CPU time 1.02 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 207024 kb
Host smart-33968a62-63c6-46ba-a51e-f48b0c1057b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20709
72320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2070972320
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.1128046466
Short name T2865
Test name
Test status
Simulation time 6176699029 ps
CPU time 45.53 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:47:06 PM PDT 24
Peak memory 215436 kb
Host smart-f11d8912-e376-442b-b3a6-0216db0365bd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1128046466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.1128046466
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.631935928
Short name T1651
Test name
Test status
Simulation time 12762779954 ps
CPU time 101.03 seconds
Started Jul 31 05:46:19 PM PDT 24
Finished Jul 31 05:48:01 PM PDT 24
Peak memory 207100 kb
Host smart-b3c872a1-cc55-42f0-bb95-8f7ddd1770ee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=631935928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.631935928
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.1393603323
Short name T2627
Test name
Test status
Simulation time 206235897 ps
CPU time 0.91 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:17 PM PDT 24
Peak memory 206624 kb
Host smart-e7c988ed-a018-4bd7-82c4-6a0a64c558b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13936
03323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1393603323
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.3772202195
Short name T867
Test name
Test status
Simulation time 23313656387 ps
CPU time 28.96 seconds
Started Jul 31 05:46:13 PM PDT 24
Finished Jul 31 05:46:43 PM PDT 24
Peak memory 207108 kb
Host smart-86365e7d-5fee-41c8-bdd3-47986397c338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37722
02195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3772202195
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1613060269
Short name T2813
Test name
Test status
Simulation time 3294576221 ps
CPU time 5.06 seconds
Started Jul 31 05:46:19 PM PDT 24
Finished Jul 31 05:46:24 PM PDT 24
Peak memory 207172 kb
Host smart-d928cd88-e19a-40f9-bc1e-6913ac3072d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16130
60269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1613060269
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.886592175
Short name T1375
Test name
Test status
Simulation time 7012944675 ps
CPU time 202.74 seconds
Started Jul 31 05:46:23 PM PDT 24
Finished Jul 31 05:49:46 PM PDT 24
Peak memory 215440 kb
Host smart-9c4fdec3-0769-4b86-8f04-aa8aa8dbf8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88659
2175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.886592175
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3201882055
Short name T1374
Test name
Test status
Simulation time 5449060773 ps
CPU time 55.08 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:47:13 PM PDT 24
Peak memory 207160 kb
Host smart-b4428d98-be7d-46bf-a750-b943c966db06
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3201882055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3201882055
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.938627803
Short name T1322
Test name
Test status
Simulation time 242226659 ps
CPU time 1.03 seconds
Started Jul 31 05:46:26 PM PDT 24
Finished Jul 31 05:46:27 PM PDT 24
Peak memory 206996 kb
Host smart-a23ee79d-3b14-4b39-ab74-c151a6250be9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=938627803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.938627803
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1975922110
Short name T1023
Test name
Test status
Simulation time 187083382 ps
CPU time 0.99 seconds
Started Jul 31 05:46:19 PM PDT 24
Finished Jul 31 05:46:20 PM PDT 24
Peak memory 206964 kb
Host smart-3bee8695-8585-4828-b2b9-04b188a3b890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19759
22110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1975922110
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.992520755
Short name T815
Test name
Test status
Simulation time 5243760907 ps
CPU time 41.41 seconds
Started Jul 31 05:46:22 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 215304 kb
Host smart-a346a79d-b570-43f9-8d14-a2ff4a348202
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99252
0755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.992520755
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3157909651
Short name T2120
Test name
Test status
Simulation time 5498100564 ps
CPU time 163.55 seconds
Started Jul 31 05:46:21 PM PDT 24
Finished Jul 31 05:49:05 PM PDT 24
Peak memory 215440 kb
Host smart-7591ed12-9941-4b8a-a5db-05f96e900f82
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3157909651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3157909651
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.4002212225
Short name T2596
Test name
Test status
Simulation time 156279863 ps
CPU time 0.92 seconds
Started Jul 31 05:46:19 PM PDT 24
Finished Jul 31 05:46:20 PM PDT 24
Peak memory 207044 kb
Host smart-873fbecb-35d6-4357-b634-7f272792bc9f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4002212225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.4002212225
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.25327625
Short name T2054
Test name
Test status
Simulation time 147283603 ps
CPU time 0.84 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 206980 kb
Host smart-b83ff468-c97b-4831-8134-b8f09ee11f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25327
625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.25327625
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.516520474
Short name T134
Test name
Test status
Simulation time 266864951 ps
CPU time 1.06 seconds
Started Jul 31 05:46:21 PM PDT 24
Finished Jul 31 05:46:23 PM PDT 24
Peak memory 206968 kb
Host smart-4a4fde85-77a5-4ded-8854-b26f2005299a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51652
0474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.516520474
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.231675590
Short name T354
Test name
Test status
Simulation time 175391060 ps
CPU time 0.89 seconds
Started Jul 31 05:46:30 PM PDT 24
Finished Jul 31 05:46:31 PM PDT 24
Peak memory 207028 kb
Host smart-e90284af-723b-416e-9035-48f933462d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
5590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.231675590
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2120473284
Short name T2129
Test name
Test status
Simulation time 193890374 ps
CPU time 0.87 seconds
Started Jul 31 05:46:21 PM PDT 24
Finished Jul 31 05:46:22 PM PDT 24
Peak memory 206964 kb
Host smart-70ec91b1-4c2b-4738-97e8-f977fd7899fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21204
73284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2120473284
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4276037838
Short name T476
Test name
Test status
Simulation time 175792125 ps
CPU time 0.91 seconds
Started Jul 31 05:46:25 PM PDT 24
Finished Jul 31 05:46:26 PM PDT 24
Peak memory 206996 kb
Host smart-ab933cfc-b999-4b0c-8c41-7cc1f10ff606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42760
37838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4276037838
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.4021214834
Short name T1110
Test name
Test status
Simulation time 190653328 ps
CPU time 0.95 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 206988 kb
Host smart-00a2600c-55b4-486c-add3-26580612c615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40212
14834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.4021214834
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.83504001
Short name T1660
Test name
Test status
Simulation time 209805066 ps
CPU time 1.06 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 207012 kb
Host smart-af2c0430-c2e7-4862-9d93-f5555872feee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=83504001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.83504001
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.999320986
Short name T2495
Test name
Test status
Simulation time 184421995 ps
CPU time 0.86 seconds
Started Jul 31 05:46:17 PM PDT 24
Finished Jul 31 05:46:18 PM PDT 24
Peak memory 206960 kb
Host smart-cd498301-c331-4fb1-b1b8-bcfc3edfc76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99932
0986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.999320986
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1027446207
Short name T2030
Test name
Test status
Simulation time 60735922 ps
CPU time 0.71 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 206948 kb
Host smart-25893a5c-123a-4616-a81a-2e9b9b766bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10274
46207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1027446207
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4254625248
Short name T770
Test name
Test status
Simulation time 15244126945 ps
CPU time 36.15 seconds
Started Jul 31 05:46:26 PM PDT 24
Finished Jul 31 05:47:02 PM PDT 24
Peak memory 215436 kb
Host smart-308a538e-89dc-4467-ad4f-d44f57f57794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42546
25248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4254625248
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.2923067829
Short name T561
Test name
Test status
Simulation time 239741330 ps
CPU time 0.98 seconds
Started Jul 31 05:46:19 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 206992 kb
Host smart-79113aa8-e4dc-47cd-a076-8a85379cdeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29230
67829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2923067829
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.918991448
Short name T22
Test name
Test status
Simulation time 194877203 ps
CPU time 0.87 seconds
Started Jul 31 05:46:22 PM PDT 24
Finished Jul 31 05:46:24 PM PDT 24
Peak memory 206996 kb
Host smart-43039673-ebf3-4b96-9535-225ef250f277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91899
1448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.918991448
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.973181993
Short name T1197
Test name
Test status
Simulation time 216852739 ps
CPU time 1.01 seconds
Started Jul 31 05:46:19 PM PDT 24
Finished Jul 31 05:46:20 PM PDT 24
Peak memory 206984 kb
Host smart-e7d085df-97e3-433b-bf83-fcc687d051f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97318
1993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.973181993
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3220151856
Short name T2614
Test name
Test status
Simulation time 208364158 ps
CPU time 1.02 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:20 PM PDT 24
Peak memory 206984 kb
Host smart-03c70e6a-d541-4395-8d3d-b39067d9533b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32201
51856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3220151856
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2935048629
Short name T68
Test name
Test status
Simulation time 229726695 ps
CPU time 0.96 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 206996 kb
Host smart-20ec7f10-fda4-4927-8dbb-0dd179c00764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29350
48629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2935048629
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.1692011447
Short name T473
Test name
Test status
Simulation time 192695206 ps
CPU time 0.92 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 206960 kb
Host smart-c5234f9b-cb3d-4661-a291-ae21c9f28355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16920
11447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.1692011447
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1703067830
Short name T1149
Test name
Test status
Simulation time 156954865 ps
CPU time 0.88 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:46:25 PM PDT 24
Peak memory 207000 kb
Host smart-24265c72-a891-43af-908e-df2899111aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17030
67830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1703067830
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3464771177
Short name T2400
Test name
Test status
Simulation time 260209145 ps
CPU time 1.08 seconds
Started Jul 31 05:46:20 PM PDT 24
Finished Jul 31 05:46:21 PM PDT 24
Peak memory 207060 kb
Host smart-0d09b514-9ecc-4785-94cf-1f2d81795baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34647
71177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3464771177
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.3328590123
Short name T146
Test name
Test status
Simulation time 4378498300 ps
CPU time 136.22 seconds
Started Jul 31 05:46:25 PM PDT 24
Finished Jul 31 05:48:41 PM PDT 24
Peak memory 215440 kb
Host smart-33a2d5d0-a00d-4609-b99a-44cc96ba48a2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3328590123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.3328590123
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.4037544671
Short name T2726
Test name
Test status
Simulation time 195222315 ps
CPU time 0.89 seconds
Started Jul 31 05:46:23 PM PDT 24
Finished Jul 31 05:46:24 PM PDT 24
Peak memory 207016 kb
Host smart-14787053-80e4-44bf-a06c-652b344a4115
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40375
44671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.4037544671
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.368538427
Short name T2111
Test name
Test status
Simulation time 184374631 ps
CPU time 0.94 seconds
Started Jul 31 05:46:18 PM PDT 24
Finished Jul 31 05:46:19 PM PDT 24
Peak memory 206984 kb
Host smart-4b339830-e499-4fb6-b746-3e5e590e220b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36853
8427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.368538427
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.2843281824
Short name T2418
Test name
Test status
Simulation time 1333467967 ps
CPU time 2.95 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:46:27 PM PDT 24
Peak memory 207048 kb
Host smart-690af5d4-0fc5-4bb4-b45b-bbe5178b7be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28432
81824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2843281824
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.503841260
Short name T1750
Test name
Test status
Simulation time 4485508788 ps
CPU time 43.52 seconds
Started Jul 31 05:46:25 PM PDT 24
Finished Jul 31 05:47:08 PM PDT 24
Peak memory 207216 kb
Host smart-54e0ebfe-92df-4163-9b11-bc6f630803a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50384
1260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.503841260
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.1686823122
Short name T2722
Test name
Test status
Simulation time 2638657664 ps
CPU time 18.23 seconds
Started Jul 31 05:46:16 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 206832 kb
Host smart-e38ef635-426b-4f01-b8cf-b71057e6f981
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686823122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.1686823122
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.463217036
Short name T2509
Test name
Test status
Simulation time 62171524 ps
CPU time 0.69 seconds
Started Jul 31 05:46:30 PM PDT 24
Finished Jul 31 05:46:31 PM PDT 24
Peak memory 207036 kb
Host smart-53e10779-b1a5-4611-918f-fc6e65d344b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=463217036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.463217036
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.44052033
Short name T2189
Test name
Test status
Simulation time 3443475868 ps
CPU time 5.08 seconds
Started Jul 31 05:46:26 PM PDT 24
Finished Jul 31 05:46:31 PM PDT 24
Peak memory 207116 kb
Host smart-a25fd4a6-2205-4228-a3c4-b0e40f66a2b4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44052033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon
_wake_disconnect.44052033
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3084114321
Short name T1522
Test name
Test status
Simulation time 13346078257 ps
CPU time 15.02 seconds
Started Jul 31 05:46:26 PM PDT 24
Finished Jul 31 05:46:41 PM PDT 24
Peak memory 207208 kb
Host smart-73805d26-021b-4fec-b93d-97c570df1e39
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084114321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3084114321
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.94325042
Short name T1168
Test name
Test status
Simulation time 23357851833 ps
CPU time 27.5 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:46:52 PM PDT 24
Peak memory 207240 kb
Host smart-1f2e2048-1df3-4028-85e2-3d15621d669a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94325042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon
_wake_resume.94325042
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.755702701
Short name T393
Test name
Test status
Simulation time 166990862 ps
CPU time 0.85 seconds
Started Jul 31 05:46:25 PM PDT 24
Finished Jul 31 05:46:26 PM PDT 24
Peak memory 207020 kb
Host smart-492871b4-a578-40de-bf7d-055571e9a28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75570
2701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.755702701
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.590841584
Short name T2821
Test name
Test status
Simulation time 162372221 ps
CPU time 0.83 seconds
Started Jul 31 05:46:21 PM PDT 24
Finished Jul 31 05:46:22 PM PDT 24
Peak memory 206952 kb
Host smart-c61cd58b-393d-406b-9b4e-90603f84e444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59084
1584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.590841584
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3691993221
Short name T1766
Test name
Test status
Simulation time 429213365 ps
CPU time 1.53 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:33 PM PDT 24
Peak memory 207020 kb
Host smart-e6a320a8-4af8-4618-9337-2505c1109808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36919
93221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3691993221
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3682418079
Short name T1059
Test name
Test status
Simulation time 394967665 ps
CPU time 1.39 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:46:25 PM PDT 24
Peak memory 206976 kb
Host smart-86df159d-b1c9-4bea-8654-872999a09c7d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3682418079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3682418079
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.1819865536
Short name T83
Test name
Test status
Simulation time 15894544037 ps
CPU time 35.08 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 207192 kb
Host smart-59e7ae88-9f92-4b36-8c4c-5c75518ee737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18198
65536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.1819865536
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_device_timeout.2835581066
Short name T1277
Test name
Test status
Simulation time 1412905533 ps
CPU time 33.5 seconds
Started Jul 31 05:46:32 PM PDT 24
Finished Jul 31 05:47:06 PM PDT 24
Peak memory 207064 kb
Host smart-3f6db126-7328-40db-afab-1460fae070a8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835581066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.2835581066
Directory /workspace/43.usbdev_device_timeout/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3108359053
Short name T789
Test name
Test status
Simulation time 490269412 ps
CPU time 1.85 seconds
Started Jul 31 05:46:21 PM PDT 24
Finished Jul 31 05:46:23 PM PDT 24
Peak memory 206968 kb
Host smart-e256946f-3212-4646-b0cc-fb285ccea19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31083
59053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3108359053
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1903672443
Short name T1636
Test name
Test status
Simulation time 141320808 ps
CPU time 0.79 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:46:25 PM PDT 24
Peak memory 206960 kb
Host smart-b5f6b9e7-1c2e-4107-a70c-ed32f6ea4a0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19036
72443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1903672443
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1604711711
Short name T1888
Test name
Test status
Simulation time 60817432 ps
CPU time 0.72 seconds
Started Jul 31 05:46:28 PM PDT 24
Finished Jul 31 05:46:29 PM PDT 24
Peak memory 206928 kb
Host smart-df6d20b0-a027-48bc-88be-e3e36be2b498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16047
11711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1604711711
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.1695708640
Short name T2218
Test name
Test status
Simulation time 944229020 ps
CPU time 2.51 seconds
Started Jul 31 05:46:25 PM PDT 24
Finished Jul 31 05:46:27 PM PDT 24
Peak memory 207048 kb
Host smart-e7bb7088-965b-4f5a-b009-fc0dce563bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957
08640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1695708640
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.4273867067
Short name T2234
Test name
Test status
Simulation time 294547020 ps
CPU time 2.14 seconds
Started Jul 31 05:46:27 PM PDT 24
Finished Jul 31 05:46:29 PM PDT 24
Peak memory 207068 kb
Host smart-d4e8a72d-e251-4214-baea-c6b1342ea388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42738
67067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.4273867067
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.994278683
Short name T2211
Test name
Test status
Simulation time 184178108 ps
CPU time 1.04 seconds
Started Jul 31 05:46:25 PM PDT 24
Finished Jul 31 05:46:26 PM PDT 24
Peak memory 207084 kb
Host smart-35814a73-d050-4ab3-a72d-eb0a6e414010
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=994278683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.994278683
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.71909736
Short name T2109
Test name
Test status
Simulation time 199016070 ps
CPU time 0.89 seconds
Started Jul 31 05:46:29 PM PDT 24
Finished Jul 31 05:46:30 PM PDT 24
Peak memory 206976 kb
Host smart-42e9ab0d-ab3c-4c0c-9295-554665c4cded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71909
736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.71909736
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3594836303
Short name T2807
Test name
Test status
Simulation time 176935647 ps
CPU time 0.92 seconds
Started Jul 31 05:46:26 PM PDT 24
Finished Jul 31 05:46:27 PM PDT 24
Peak memory 206984 kb
Host smart-c713074a-a615-4ad7-bcb5-f57d0e1a9892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35948
36303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3594836303
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.4222229551
Short name T1921
Test name
Test status
Simulation time 5627496089 ps
CPU time 64.55 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 216868 kb
Host smart-99e2d1c0-ba5f-4793-8462-db6b8619ce61
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4222229551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.4222229551
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.586089977
Short name T1972
Test name
Test status
Simulation time 203039863 ps
CPU time 0.96 seconds
Started Jul 31 05:46:21 PM PDT 24
Finished Jul 31 05:46:23 PM PDT 24
Peak memory 206996 kb
Host smart-3cac3f6b-a8cf-4501-94e3-9c10977d5747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58608
9977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.586089977
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.450203251
Short name T1032
Test name
Test status
Simulation time 23300764463 ps
CPU time 29.3 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:46:54 PM PDT 24
Peak memory 207208 kb
Host smart-11ecec2b-e6b0-4042-8d92-7066ee1f79cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45020
3251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.450203251
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.1524812511
Short name T1920
Test name
Test status
Simulation time 3303550489 ps
CPU time 4.79 seconds
Started Jul 31 05:46:29 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 207116 kb
Host smart-8be7f91c-f0e9-45cb-b6e9-3b5cc0dd48c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15248
12511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1524812511
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.109280967
Short name T1105
Test name
Test status
Simulation time 8013066921 ps
CPU time 224.76 seconds
Started Jul 31 05:46:25 PM PDT 24
Finished Jul 31 05:50:10 PM PDT 24
Peak memory 215480 kb
Host smart-a51bfc38-74db-4012-888a-e7f63c7441ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10928
0967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.109280967
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1842674851
Short name T965
Test name
Test status
Simulation time 5843214738 ps
CPU time 172.23 seconds
Started Jul 31 05:46:30 PM PDT 24
Finished Jul 31 05:49:23 PM PDT 24
Peak memory 215436 kb
Host smart-5cede34e-668e-4adc-a5e1-f8af932aceeb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1842674851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1842674851
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2125349206
Short name T2662
Test name
Test status
Simulation time 253001110 ps
CPU time 1.05 seconds
Started Jul 31 05:46:26 PM PDT 24
Finished Jul 31 05:46:27 PM PDT 24
Peak memory 207016 kb
Host smart-83193f78-36e0-48e2-98d2-57ac61b64d91
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2125349206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2125349206
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3816046568
Short name T1673
Test name
Test status
Simulation time 188950464 ps
CPU time 1.04 seconds
Started Jul 31 05:46:22 PM PDT 24
Finished Jul 31 05:46:23 PM PDT 24
Peak memory 206976 kb
Host smart-0cf3d63d-9e77-4caa-b0dc-bb808edfb639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38160
46568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3816046568
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2110234715
Short name T1674
Test name
Test status
Simulation time 4765038103 ps
CPU time 37.84 seconds
Started Jul 31 05:46:26 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 216780 kb
Host smart-c1bd5b4a-8629-4ea0-a88e-4bc0e49924d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21102
34715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2110234715
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.51261517
Short name T1317
Test name
Test status
Simulation time 4884961754 ps
CPU time 48.56 seconds
Started Jul 31 05:46:27 PM PDT 24
Finished Jul 31 05:47:16 PM PDT 24
Peak memory 216924 kb
Host smart-42cd21b9-32ed-4bf0-95ac-7d01660c94f7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=51261517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.51261517
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.4228486194
Short name T2759
Test name
Test status
Simulation time 180381944 ps
CPU time 0.89 seconds
Started Jul 31 05:46:27 PM PDT 24
Finished Jul 31 05:46:28 PM PDT 24
Peak memory 206996 kb
Host smart-ed8ac364-6ae4-4ca7-8c04-c7b278f41b84
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4228486194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.4228486194
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.3200562316
Short name T2011
Test name
Test status
Simulation time 146271002 ps
CPU time 0.82 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 207016 kb
Host smart-e1720ccf-9063-4265-93bd-ea202becbde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32005
62316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.3200562316
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2488781420
Short name T2666
Test name
Test status
Simulation time 214672142 ps
CPU time 0.94 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 207012 kb
Host smart-9a7b8f35-1658-4f9c-af67-5ac2f361ff3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24887
81420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2488781420
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2988989577
Short name T2233
Test name
Test status
Simulation time 145633577 ps
CPU time 0.87 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:42 PM PDT 24
Peak memory 207000 kb
Host smart-0a8864ef-ed6f-4108-b6b2-be8369a6de99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29889
89577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2988989577
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.3554258943
Short name T2223
Test name
Test status
Simulation time 173654117 ps
CPU time 0.87 seconds
Started Jul 31 05:46:29 PM PDT 24
Finished Jul 31 05:46:30 PM PDT 24
Peak memory 206968 kb
Host smart-665839ef-680e-439b-a847-9eeaf3c63a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
58943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.3554258943
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2257105901
Short name T667
Test name
Test status
Simulation time 174016467 ps
CPU time 0.91 seconds
Started Jul 31 05:46:30 PM PDT 24
Finished Jul 31 05:46:31 PM PDT 24
Peak memory 206996 kb
Host smart-1410dc63-eafa-4fc9-83a5-189ef7d00b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22571
05901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2257105901
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1234401215
Short name T2058
Test name
Test status
Simulation time 163538801 ps
CPU time 0.86 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 206972 kb
Host smart-926bc100-99f7-4f41-9a07-abddd93f79c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12344
01215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1234401215
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.4004851223
Short name T2230
Test name
Test status
Simulation time 292832546 ps
CPU time 1.18 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 206972 kb
Host smart-db461860-a8f4-4c61-a37c-e4a55906ce65
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4004851223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.4004851223
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2798094045
Short name T2653
Test name
Test status
Simulation time 147941018 ps
CPU time 0.87 seconds
Started Jul 31 05:46:37 PM PDT 24
Finished Jul 31 05:46:38 PM PDT 24
Peak memory 207012 kb
Host smart-ff370373-282c-477a-a5ad-29013edf74fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27980
94045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2798094045
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.1658158015
Short name T614
Test name
Test status
Simulation time 49841674 ps
CPU time 0.69 seconds
Started Jul 31 05:46:29 PM PDT 24
Finished Jul 31 05:46:30 PM PDT 24
Peak memory 206948 kb
Host smart-da63c7cc-1442-4b0d-803f-9df488c94954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16581
58015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1658158015
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.949199564
Short name T1620
Test name
Test status
Simulation time 19728859166 ps
CPU time 53.52 seconds
Started Jul 31 05:46:32 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 219896 kb
Host smart-0f0088b5-7706-4a7d-b62a-40865ac6bfa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94919
9564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.949199564
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.3781011505
Short name T1731
Test name
Test status
Simulation time 176117947 ps
CPU time 0.91 seconds
Started Jul 31 05:46:35 PM PDT 24
Finished Jul 31 05:46:36 PM PDT 24
Peak memory 206968 kb
Host smart-f1c074ff-0a5f-4781-9dce-a8b33bb16df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37810
11505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3781011505
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.2174090438
Short name T1130
Test name
Test status
Simulation time 181302365 ps
CPU time 0.91 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 207008 kb
Host smart-feafef4c-5b20-4ca9-883b-f8a46a86f566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21740
90438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.2174090438
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.3886540611
Short name T1778
Test name
Test status
Simulation time 206889638 ps
CPU time 0.93 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 206984 kb
Host smart-ffbd000c-2c7d-4ed3-b668-9cff8001d663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38865
40611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.3886540611
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.3196174871
Short name T589
Test name
Test status
Simulation time 184676483 ps
CPU time 0.91 seconds
Started Jul 31 05:46:34 PM PDT 24
Finished Jul 31 05:46:35 PM PDT 24
Peak memory 206980 kb
Host smart-06d594d9-598b-4787-8a83-f863beb56116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31961
74871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.3196174871
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.399058638
Short name T2142
Test name
Test status
Simulation time 176385842 ps
CPU time 0.88 seconds
Started Jul 31 05:46:29 PM PDT 24
Finished Jul 31 05:46:30 PM PDT 24
Peak memory 206976 kb
Host smart-abc48f5e-7850-49c0-8d08-e501b25abea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39905
8638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.399058638
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.845288814
Short name T1777
Test name
Test status
Simulation time 181775523 ps
CPU time 0.88 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 206952 kb
Host smart-8bc35934-853b-43f6-97df-989e9734f63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84528
8814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.845288814
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3994684588
Short name T1318
Test name
Test status
Simulation time 189387909 ps
CPU time 0.94 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 207008 kb
Host smart-1c035ad1-170b-42e2-8b9c-467f8715e791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39946
84588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3994684588
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.3750240467
Short name T1722
Test name
Test status
Simulation time 298893563 ps
CPU time 1.1 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 206888 kb
Host smart-585c1166-f9b9-42a7-9c4e-1d61d1e6c844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37502
40467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.3750240467
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.2576425912
Short name T1941
Test name
Test status
Simulation time 6172164206 ps
CPU time 178.72 seconds
Started Jul 31 05:46:32 PM PDT 24
Finished Jul 31 05:49:31 PM PDT 24
Peak memory 215408 kb
Host smart-57eee72f-92de-4c4b-9a76-e89bdebcfd24
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2576425912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.2576425912
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1350990215
Short name T1309
Test name
Test status
Simulation time 194827276 ps
CPU time 0.87 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 206900 kb
Host smart-a1b46e3f-0c7b-42ef-9e83-6b1454839c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13509
90215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1350990215
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3787823710
Short name T521
Test name
Test status
Simulation time 155705825 ps
CPU time 0.83 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 206988 kb
Host smart-949c60d7-7a3b-40cb-af24-122106cddc3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37878
23710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3787823710
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1967668763
Short name T1545
Test name
Test status
Simulation time 1064792430 ps
CPU time 2.73 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:36 PM PDT 24
Peak memory 207044 kb
Host smart-087a2f4b-5172-4616-91e3-f741214ac21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19676
68763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1967668763
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1082998859
Short name T643
Test name
Test status
Simulation time 5723013618 ps
CPU time 44.52 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 207236 kb
Host smart-830dc814-450a-47b6-8942-13f3a7b3094b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10829
98859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1082998859
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.3131228253
Short name T2414
Test name
Test status
Simulation time 717927860 ps
CPU time 14.91 seconds
Started Jul 31 05:46:24 PM PDT 24
Finished Jul 31 05:46:39 PM PDT 24
Peak memory 207060 kb
Host smart-55d1792d-ac6b-48c3-9f71-b07b12992732
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131228253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.3131228253
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.1341061344
Short name T177
Test name
Test status
Simulation time 76933390 ps
CPU time 0.69 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:42 PM PDT 24
Peak memory 207024 kb
Host smart-9fc9225b-82d9-4d9d-bb6b-ee5beb4b26ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1341061344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.1341061344
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.4028897654
Short name T2594
Test name
Test status
Simulation time 4335230327 ps
CPU time 7.2 seconds
Started Jul 31 05:46:37 PM PDT 24
Finished Jul 31 05:46:44 PM PDT 24
Peak memory 207188 kb
Host smart-c0d149be-3e19-4239-b638-2bb932b0eb9e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028897654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.4028897654
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1091759282
Short name T2354
Test name
Test status
Simulation time 13394120977 ps
CPU time 16.8 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 207236 kb
Host smart-9461f45a-ba8c-4042-b36e-10e28bce903f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091759282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1091759282
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.202194450
Short name T1946
Test name
Test status
Simulation time 23391005980 ps
CPU time 26.48 seconds
Started Jul 31 05:46:32 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 207232 kb
Host smart-791515fa-e645-492f-8d47-59d9cbc5109c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202194450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_ao
n_wake_resume.202194450
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.2860420673
Short name T1871
Test name
Test status
Simulation time 189045038 ps
CPU time 0.92 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 206980 kb
Host smart-ea23a739-7065-4027-98a2-717378a4e317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28604
20673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.2860420673
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1141407486
Short name T1526
Test name
Test status
Simulation time 149517071 ps
CPU time 0.91 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 206964 kb
Host smart-3231325b-35e9-4297-82da-82416c49e90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11414
07486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1141407486
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.4046887565
Short name T2079
Test name
Test status
Simulation time 292414847 ps
CPU time 1.19 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 206996 kb
Host smart-45cecfe8-4b31-4819-99ca-7c20bd509b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40468
87565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.4046887565
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.4193694540
Short name T78
Test name
Test status
Simulation time 546272329 ps
CPU time 1.66 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:35 PM PDT 24
Peak memory 207028 kb
Host smart-ccebda5a-8d2f-442c-a206-072ddaa3c2a3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4193694540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.4193694540
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3531073736
Short name T2633
Test name
Test status
Simulation time 10094140281 ps
CPU time 25.97 seconds
Started Jul 31 05:46:29 PM PDT 24
Finished Jul 31 05:46:55 PM PDT 24
Peak memory 207172 kb
Host smart-373aba49-350f-4480-b4c4-73972f3693f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35310
73736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3531073736
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_device_timeout.4007045547
Short name T983
Test name
Test status
Simulation time 1690584662 ps
CPU time 39.61 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 207032 kb
Host smart-ac8c276d-3e00-4e59-9835-f85dc83d4e0b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007045547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.4007045547
Directory /workspace/44.usbdev_device_timeout/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.4253310019
Short name T2313
Test name
Test status
Simulation time 377108269 ps
CPU time 1.3 seconds
Started Jul 31 05:46:34 PM PDT 24
Finished Jul 31 05:46:36 PM PDT 24
Peak memory 206956 kb
Host smart-14597e10-2d04-4806-ba83-b66fa88fbbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42533
10019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.4253310019
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.492746768
Short name T1591
Test name
Test status
Simulation time 137255389 ps
CPU time 0.78 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:46:45 PM PDT 24
Peak memory 206944 kb
Host smart-76caa84a-46a4-460c-ab73-5d72d12ce723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49274
6768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.492746768
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.3995581921
Short name T2566
Test name
Test status
Simulation time 44528657 ps
CPU time 0.68 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:32 PM PDT 24
Peak memory 206948 kb
Host smart-19aaa425-382a-462f-92b5-bbe1ca0755eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39955
81921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.3995581921
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.279705230
Short name T411
Test name
Test status
Simulation time 935631356 ps
CPU time 2.55 seconds
Started Jul 31 05:46:31 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 207128 kb
Host smart-524ea683-ea53-4868-a259-8e645114fae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27970
5230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.279705230
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.42574575
Short name T2552
Test name
Test status
Simulation time 167470873 ps
CPU time 1.93 seconds
Started Jul 31 05:46:32 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 207132 kb
Host smart-f261419a-558a-4278-a5d1-f400673d6aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42574
575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.42574575
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.3745786731
Short name T2638
Test name
Test status
Simulation time 186261353 ps
CPU time 1.03 seconds
Started Jul 31 05:46:35 PM PDT 24
Finished Jul 31 05:46:37 PM PDT 24
Peak memory 215252 kb
Host smart-d12e5b61-54d7-424d-a6f5-772f130612d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3745786731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3745786731
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.488919464
Short name T595
Test name
Test status
Simulation time 155025934 ps
CPU time 0.82 seconds
Started Jul 31 05:46:36 PM PDT 24
Finished Jul 31 05:46:37 PM PDT 24
Peak memory 206948 kb
Host smart-ced6018d-e704-47cd-9878-9b57e6934492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48891
9464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.488919464
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3593736038
Short name T1828
Test name
Test status
Simulation time 169162337 ps
CPU time 0.97 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:46:45 PM PDT 24
Peak memory 206952 kb
Host smart-888d6650-d2ea-433d-8e1c-8cb5318962eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35937
36038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3593736038
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.2497488516
Short name T1156
Test name
Test status
Simulation time 5416744005 ps
CPU time 42.69 seconds
Started Jul 31 05:46:35 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 215432 kb
Host smart-45061397-557d-472a-b1c5-a86c8300e156
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2497488516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.2497488516
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3700398930
Short name T2007
Test name
Test status
Simulation time 12226615373 ps
CPU time 78.33 seconds
Started Jul 31 05:46:36 PM PDT 24
Finished Jul 31 05:47:54 PM PDT 24
Peak memory 207172 kb
Host smart-ade96cfb-20af-48fb-8945-4ba5a2d74cc8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3700398930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3700398930
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.973915352
Short name T324
Test name
Test status
Simulation time 221729828 ps
CPU time 0.95 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 206996 kb
Host smart-8a009e7e-00eb-4ab1-918c-a895fb17f7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97391
5352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.973915352
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1288357053
Short name T718
Test name
Test status
Simulation time 23275104524 ps
CPU time 30.85 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:47:17 PM PDT 24
Peak memory 207184 kb
Host smart-caf5c2f9-b5a6-4f06-9f56-ed56c0aa0c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12883
57053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1288357053
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1590784756
Short name T599
Test name
Test status
Simulation time 3310802340 ps
CPU time 5.36 seconds
Started Jul 31 05:46:34 PM PDT 24
Finished Jul 31 05:46:39 PM PDT 24
Peak memory 207124 kb
Host smart-53d9390b-8bb1-40aa-937b-d07d3893072c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15907
84756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1590784756
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.665707194
Short name T1825
Test name
Test status
Simulation time 10589436824 ps
CPU time 77.35 seconds
Started Jul 31 05:46:34 PM PDT 24
Finished Jul 31 05:47:51 PM PDT 24
Peak memory 217076 kb
Host smart-8fde487b-7c41-477d-a37e-fd2fedcf4d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66570
7194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.665707194
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.178054977
Short name T400
Test name
Test status
Simulation time 7766665232 ps
CPU time 75.99 seconds
Started Jul 31 05:46:38 PM PDT 24
Finished Jul 31 05:47:54 PM PDT 24
Peak memory 207180 kb
Host smart-b7fb3f65-bdc6-4cb9-ac72-9c24fd3cd119
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=178054977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.178054977
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.2697906620
Short name T382
Test name
Test status
Simulation time 297147126 ps
CPU time 1.02 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 207008 kb
Host smart-da707b24-3e09-405a-9aa2-c4dca37392fa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2697906620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2697906620
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1730283717
Short name T1370
Test name
Test status
Simulation time 201434557 ps
CPU time 1.08 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 207012 kb
Host smart-ba57f866-eff6-4ac3-ace8-513ae447986b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17302
83717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1730283717
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1827581708
Short name T2065
Test name
Test status
Simulation time 3803074837 ps
CPU time 110.42 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:48:34 PM PDT 24
Peak memory 215280 kb
Host smart-290a8405-34cd-4ec1-946f-b87aca56ef31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18275
81708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1827581708
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.3298952936
Short name T1868
Test name
Test status
Simulation time 5350401371 ps
CPU time 43.47 seconds
Started Jul 31 05:46:36 PM PDT 24
Finished Jul 31 05:47:19 PM PDT 24
Peak memory 215404 kb
Host smart-17a8d0e7-78d7-4237-910a-0f0c7dcbca23
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3298952936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.3298952936
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1800654395
Short name T1094
Test name
Test status
Simulation time 207320890 ps
CPU time 1.02 seconds
Started Jul 31 05:46:33 PM PDT 24
Finished Jul 31 05:46:34 PM PDT 24
Peak memory 206988 kb
Host smart-716b1463-91f5-42db-b248-56103f4abb40
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1800654395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1800654395
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2477834651
Short name T1164
Test name
Test status
Simulation time 195734232 ps
CPU time 0.9 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:42 PM PDT 24
Peak memory 206988 kb
Host smart-0d03cb8e-c44b-4c9a-9849-de62f5bb5bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24778
34651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2477834651
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.1165245161
Short name T109
Test name
Test status
Simulation time 186421265 ps
CPU time 0.91 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:46:47 PM PDT 24
Peak memory 206996 kb
Host smart-4316f89d-0b83-4184-b737-b6d49fcd3261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11652
45161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.1165245161
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2603206660
Short name T2187
Test name
Test status
Simulation time 177449200 ps
CPU time 0.93 seconds
Started Jul 31 05:46:34 PM PDT 24
Finished Jul 31 05:46:35 PM PDT 24
Peak memory 207032 kb
Host smart-aed1c3d6-ead6-498a-9b51-11b24f5be373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26032
06660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2603206660
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3015134058
Short name T950
Test name
Test status
Simulation time 163318455 ps
CPU time 0.83 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:46:45 PM PDT 24
Peak memory 206944 kb
Host smart-0cec272f-286e-4093-8081-ab70c0e5c77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30151
34058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3015134058
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.2973952204
Short name T594
Test name
Test status
Simulation time 150081938 ps
CPU time 0.91 seconds
Started Jul 31 05:46:34 PM PDT 24
Finished Jul 31 05:46:35 PM PDT 24
Peak memory 206988 kb
Host smart-a54d0c2f-8e68-4141-b601-154145653584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29739
52204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2973952204
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.1805812945
Short name T2006
Test name
Test status
Simulation time 164763812 ps
CPU time 0.9 seconds
Started Jul 31 05:46:35 PM PDT 24
Finished Jul 31 05:46:36 PM PDT 24
Peak memory 206992 kb
Host smart-740bfc79-3751-4ff4-8a24-098a8f13bec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18058
12945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1805812945
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.7799556
Short name T2259
Test name
Test status
Simulation time 198221935 ps
CPU time 0.98 seconds
Started Jul 31 05:46:36 PM PDT 24
Finished Jul 31 05:46:37 PM PDT 24
Peak memory 206964 kb
Host smart-1fa6de59-784f-4dd8-8eb3-7c9999ae17bf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=7799556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.7799556
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.250151157
Short name T1432
Test name
Test status
Simulation time 144257345 ps
CPU time 0.88 seconds
Started Jul 31 05:46:35 PM PDT 24
Finished Jul 31 05:46:36 PM PDT 24
Peak memory 206980 kb
Host smart-35eeee0c-ec6d-4c5f-bfa9-c0c0f7059189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25015
1157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.250151157
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1252828121
Short name T31
Test name
Test status
Simulation time 70629866 ps
CPU time 0.74 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:46:45 PM PDT 24
Peak memory 206912 kb
Host smart-6096ce0d-63d7-4c61-ae00-a506f96120ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12528
28121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1252828121
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.1036285227
Short name T1423
Test name
Test status
Simulation time 14227309709 ps
CPU time 36.81 seconds
Started Jul 31 05:46:43 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 215384 kb
Host smart-6aed5c83-2119-4eeb-8a57-a65a6c2234bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
85227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.1036285227
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2879385344
Short name T572
Test name
Test status
Simulation time 220738527 ps
CPU time 0.95 seconds
Started Jul 31 05:46:36 PM PDT 24
Finished Jul 31 05:46:37 PM PDT 24
Peak memory 207048 kb
Host smart-759e7c4b-5fed-4e49-a402-15111d6d555d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28793
85344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2879385344
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.806085916
Short name T2026
Test name
Test status
Simulation time 224531938 ps
CPU time 0.96 seconds
Started Jul 31 05:46:38 PM PDT 24
Finished Jul 31 05:46:39 PM PDT 24
Peak memory 206968 kb
Host smart-dc0dfe4c-fffc-4f34-b4ba-70f94d704811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80608
5916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.806085916
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.810754245
Short name T2279
Test name
Test status
Simulation time 244529483 ps
CPU time 1.02 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:46:47 PM PDT 24
Peak memory 206972 kb
Host smart-71d81d0b-a7d8-49ae-b2db-d0383ae56795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81075
4245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.810754245
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.3222777601
Short name T2348
Test name
Test status
Simulation time 179604506 ps
CPU time 0.88 seconds
Started Jul 31 05:46:34 PM PDT 24
Finished Jul 31 05:46:35 PM PDT 24
Peak memory 206992 kb
Host smart-e60eee8e-0a8e-439f-bf05-f5dbb43f7c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32227
77601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.3222777601
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2325488503
Short name T1288
Test name
Test status
Simulation time 160405093 ps
CPU time 0.85 seconds
Started Jul 31 05:46:34 PM PDT 24
Finished Jul 31 05:46:35 PM PDT 24
Peak memory 207004 kb
Host smart-6dcaa17c-3aa8-42fd-a43b-788111106880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23254
88503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2325488503
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.305211616
Short name T1680
Test name
Test status
Simulation time 161585612 ps
CPU time 0.83 seconds
Started Jul 31 05:46:35 PM PDT 24
Finished Jul 31 05:46:36 PM PDT 24
Peak memory 206964 kb
Host smart-8c4d4a66-7e68-4940-ad65-45f62d202646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30521
1616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.305211616
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1302125509
Short name T1520
Test name
Test status
Simulation time 154484123 ps
CPU time 0.81 seconds
Started Jul 31 05:46:36 PM PDT 24
Finished Jul 31 05:46:37 PM PDT 24
Peak memory 206968 kb
Host smart-f7940be4-8a6f-4c02-ab1d-5d9f3d4667d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13021
25509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1302125509
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.3272220633
Short name T1940
Test name
Test status
Simulation time 274977074 ps
CPU time 1.1 seconds
Started Jul 31 05:46:35 PM PDT 24
Finished Jul 31 05:46:36 PM PDT 24
Peak memory 206972 kb
Host smart-de8b6cec-fca2-4508-b19d-c3e749519e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32722
20633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.3272220633
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.3963107559
Short name T1295
Test name
Test status
Simulation time 6390458995 ps
CPU time 180.39 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:49:44 PM PDT 24
Peak memory 215356 kb
Host smart-0d96d36b-a854-4c79-9f24-cebb6c6a9c3e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3963107559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3963107559
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3226907967
Short name T289
Test name
Test status
Simulation time 175353194 ps
CPU time 0.89 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:46:45 PM PDT 24
Peak memory 206980 kb
Host smart-f9b19215-7c72-4303-b11c-b1a216a54d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32269
07967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3226907967
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.3771961126
Short name T2530
Test name
Test status
Simulation time 178017314 ps
CPU time 0.87 seconds
Started Jul 31 05:46:42 PM PDT 24
Finished Jul 31 05:46:43 PM PDT 24
Peak memory 207044 kb
Host smart-cce72fbf-9a54-4af4-967e-b1c048356413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37719
61126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.3771961126
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.3320259430
Short name T1497
Test name
Test status
Simulation time 443421205 ps
CPU time 1.43 seconds
Started Jul 31 05:46:40 PM PDT 24
Finished Jul 31 05:46:41 PM PDT 24
Peak memory 206960 kb
Host smart-ad89caba-1149-477c-b301-52e5c1b903c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33202
59430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.3320259430
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.2885840823
Short name T1387
Test name
Test status
Simulation time 5421219489 ps
CPU time 54.48 seconds
Started Jul 31 05:46:36 PM PDT 24
Finished Jul 31 05:47:30 PM PDT 24
Peak memory 216860 kb
Host smart-ae097d1f-aa55-4495-b72f-fa087e4b7ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28858
40823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.2885840823
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.669017924
Short name T929
Test name
Test status
Simulation time 841402016 ps
CPU time 18.57 seconds
Started Jul 31 05:46:32 PM PDT 24
Finished Jul 31 05:46:51 PM PDT 24
Peak memory 207128 kb
Host smart-cc3cbcda-c5b6-4327-99b1-3968c3126ade
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669017924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_host
_handshake.669017924
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.2201344072
Short name T352
Test name
Test status
Simulation time 73390456 ps
CPU time 0.69 seconds
Started Jul 31 05:46:51 PM PDT 24
Finished Jul 31 05:46:52 PM PDT 24
Peak memory 207076 kb
Host smart-347b06c2-75ce-4276-acdc-037ff16fd88f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2201344072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.2201344072
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1250257153
Short name T1012
Test name
Test status
Simulation time 3900025916 ps
CPU time 5.47 seconds
Started Jul 31 05:46:36 PM PDT 24
Finished Jul 31 05:46:41 PM PDT 24
Peak memory 207160 kb
Host smart-79b8daee-38e5-454c-b79b-fda0162ff2df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250257153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.1250257153
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.2521557040
Short name T644
Test name
Test status
Simulation time 13331369692 ps
CPU time 16.95 seconds
Started Jul 31 05:46:42 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 207228 kb
Host smart-1ee13d49-fc31-4060-90f6-d2b55f4ad21e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521557040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.2521557040
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.33774743
Short name T1875
Test name
Test status
Simulation time 23427127012 ps
CPU time 29.38 seconds
Started Jul 31 05:46:39 PM PDT 24
Finished Jul 31 05:47:08 PM PDT 24
Peak memory 207192 kb
Host smart-1ddba9aa-2641-4d84-a733-7642c3c0bcf2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33774743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon
_wake_resume.33774743
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3421967274
Short name T2037
Test name
Test status
Simulation time 155547357 ps
CPU time 0.87 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:46:45 PM PDT 24
Peak memory 207016 kb
Host smart-97c78891-52e6-453f-ba9d-861034e70586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34219
67274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3421967274
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1487850471
Short name T2221
Test name
Test status
Simulation time 145025198 ps
CPU time 0.82 seconds
Started Jul 31 05:46:40 PM PDT 24
Finished Jul 31 05:46:41 PM PDT 24
Peak memory 206964 kb
Host smart-dbcd35b9-7dc8-4a7d-aa34-19a2a66b9cd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14878
50471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1487850471
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.3352204142
Short name T2442
Test name
Test status
Simulation time 297635627 ps
CPU time 1.27 seconds
Started Jul 31 05:46:42 PM PDT 24
Finished Jul 31 05:46:43 PM PDT 24
Peak memory 206996 kb
Host smart-77446625-854b-40a6-aeb0-56e57818cc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33522
04142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3352204142
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.4293707765
Short name T2193
Test name
Test status
Simulation time 926822892 ps
CPU time 2.83 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:44 PM PDT 24
Peak memory 207132 kb
Host smart-180ca42d-63c6-4b30-b908-a5576993badb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4293707765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.4293707765
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.518060806
Short name T158
Test name
Test status
Simulation time 22647172931 ps
CPU time 51.95 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:47:34 PM PDT 24
Peak memory 207192 kb
Host smart-828b24ef-187b-4e80-88ef-c5d5400e04de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51806
0806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.518060806
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_device_timeout.117198618
Short name T2741
Test name
Test status
Simulation time 715124729 ps
CPU time 15.22 seconds
Started Jul 31 05:46:43 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 207116 kb
Host smart-12ce9a8b-b8e6-4814-b72f-8e2ba96bbc9e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117198618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.117198618
Directory /workspace/45.usbdev_device_timeout/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3820903664
Short name T529
Test name
Test status
Simulation time 384235613 ps
CPU time 1.4 seconds
Started Jul 31 05:46:40 PM PDT 24
Finished Jul 31 05:46:42 PM PDT 24
Peak memory 206964 kb
Host smart-914cd236-5b9c-4117-b4fc-d8a6d0ed78d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38209
03664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3820903664
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2641563015
Short name T2369
Test name
Test status
Simulation time 170294753 ps
CPU time 0.89 seconds
Started Jul 31 05:46:50 PM PDT 24
Finished Jul 31 05:46:51 PM PDT 24
Peak memory 206928 kb
Host smart-84519bfd-65db-4987-9cb0-d29ef421a786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26415
63015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2641563015
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2227281183
Short name T2806
Test name
Test status
Simulation time 60370329 ps
CPU time 0.76 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:42 PM PDT 24
Peak memory 206944 kb
Host smart-060ed0c7-ea68-4baf-9ab9-8eabb3992071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22272
81183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2227281183
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.2259455845
Short name T1606
Test name
Test status
Simulation time 851998583 ps
CPU time 2.22 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:43 PM PDT 24
Peak memory 207128 kb
Host smart-f7c83159-b379-4928-a073-ba57328e4820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22594
55845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.2259455845
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.530842869
Short name T1947
Test name
Test status
Simulation time 165509384 ps
CPU time 1.97 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:43 PM PDT 24
Peak memory 207028 kb
Host smart-14adccde-a9a1-4709-83f5-9f80bccc994c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53084
2869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.530842869
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.1884171978
Short name T2322
Test name
Test status
Simulation time 222270080 ps
CPU time 1.16 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:42 PM PDT 24
Peak memory 207096 kb
Host smart-db49565c-1780-4f6c-a689-a8147865abb2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1884171978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1884171978
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1502210425
Short name T968
Test name
Test status
Simulation time 165947122 ps
CPU time 0.88 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:42 PM PDT 24
Peak memory 206952 kb
Host smart-de18a4c7-36ec-4345-9c8c-71495db16fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15022
10425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1502210425
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2964328186
Short name T2607
Test name
Test status
Simulation time 198582772 ps
CPU time 0.92 seconds
Started Jul 31 05:46:41 PM PDT 24
Finished Jul 31 05:46:42 PM PDT 24
Peak memory 207000 kb
Host smart-04004b5a-9fa5-42bf-81d3-25f047ca493a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29643
28186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2964328186
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.10837944
Short name T2746
Test name
Test status
Simulation time 7810829653 ps
CPU time 61.04 seconds
Started Jul 31 05:46:38 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 215420 kb
Host smart-ef7f1f7e-6c25-41fa-9c5a-abe0789af274
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=10837944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.10837944
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2673402319
Short name T2621
Test name
Test status
Simulation time 179269354 ps
CPU time 0.88 seconds
Started Jul 31 05:46:49 PM PDT 24
Finished Jul 31 05:46:50 PM PDT 24
Peak memory 206964 kb
Host smart-e582b887-e22f-40ec-af2c-fbc91745fd3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26734
02319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2673402319
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2483076437
Short name T1915
Test name
Test status
Simulation time 23284370790 ps
CPU time 28.52 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 207172 kb
Host smart-5b501bbb-d63d-448b-97ea-4c1a3bc3caf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24830
76437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2483076437
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3814747574
Short name T1995
Test name
Test status
Simulation time 3370038533 ps
CPU time 4.98 seconds
Started Jul 31 05:46:48 PM PDT 24
Finished Jul 31 05:46:53 PM PDT 24
Peak memory 207144 kb
Host smart-596acc49-4cff-44f1-bee4-3e99e8f42231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38147
47574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3814747574
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.1406432106
Short name T1329
Test name
Test status
Simulation time 9059962032 ps
CPU time 86.2 seconds
Started Jul 31 05:46:49 PM PDT 24
Finished Jul 31 05:48:16 PM PDT 24
Peak memory 223512 kb
Host smart-2ad00419-3d8c-4905-ad48-fc41afeb6f67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14064
32106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1406432106
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3230699826
Short name T985
Test name
Test status
Simulation time 5923825428 ps
CPU time 46.05 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 207240 kb
Host smart-1fa05e81-9ae9-407a-9d5a-a77b1cf38af5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3230699826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3230699826
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.2354506162
Short name T384
Test name
Test status
Simulation time 313489041 ps
CPU time 1.13 seconds
Started Jul 31 05:46:48 PM PDT 24
Finished Jul 31 05:46:49 PM PDT 24
Peak memory 207008 kb
Host smart-2a0c9e19-dd1c-4317-b138-6e940c42791a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2354506162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.2354506162
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.4187989297
Short name T702
Test name
Test status
Simulation time 210855934 ps
CPU time 0.99 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:46:45 PM PDT 24
Peak memory 207016 kb
Host smart-8992014a-1442-47ff-8f9b-4971fa0b1cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41879
89297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.4187989297
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2069583139
Short name T149
Test name
Test status
Simulation time 3659798354 ps
CPU time 37.94 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:47:24 PM PDT 24
Peak memory 215408 kb
Host smart-ad49ccd4-3c2e-4eed-b4d2-d045619e49a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20695
83139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2069583139
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.472160287
Short name T1832
Test name
Test status
Simulation time 5007565079 ps
CPU time 37.72 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:47:24 PM PDT 24
Peak memory 207208 kb
Host smart-2c19b698-8e87-4abc-8353-2461d5808616
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=472160287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.472160287
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3646946201
Short name T1767
Test name
Test status
Simulation time 175291924 ps
CPU time 0.94 seconds
Started Jul 31 05:46:47 PM PDT 24
Finished Jul 31 05:46:48 PM PDT 24
Peak memory 206988 kb
Host smart-2b2d2b33-c13a-497a-995a-6222a1df311a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3646946201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3646946201
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.1470102141
Short name T598
Test name
Test status
Simulation time 167067046 ps
CPU time 0.88 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:46:47 PM PDT 24
Peak memory 206988 kb
Host smart-710ea321-ed66-49c4-86e2-cc1c605b1f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14701
02141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1470102141
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1709192648
Short name T1337
Test name
Test status
Simulation time 202684227 ps
CPU time 0.95 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:46:47 PM PDT 24
Peak memory 207016 kb
Host smart-c270c682-eb5f-43e3-87dd-231ce1fb817f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17091
92648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1709192648
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.3646958551
Short name T1726
Test name
Test status
Simulation time 196838023 ps
CPU time 0.91 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:46:47 PM PDT 24
Peak memory 206992 kb
Host smart-a85b91e9-ada2-4177-ba64-3987c1af940b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36469
58551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3646958551
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.462312985
Short name T776
Test name
Test status
Simulation time 189361569 ps
CPU time 0.92 seconds
Started Jul 31 05:46:51 PM PDT 24
Finished Jul 31 05:46:52 PM PDT 24
Peak memory 206972 kb
Host smart-c3a1d50b-b6cc-47c4-8a09-b4efafae577a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46231
2985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.462312985
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1725386897
Short name T1328
Test name
Test status
Simulation time 164819444 ps
CPU time 0.88 seconds
Started Jul 31 05:46:47 PM PDT 24
Finished Jul 31 05:46:48 PM PDT 24
Peak memory 206776 kb
Host smart-4b936c66-b975-41ba-ab7d-e30f385d8592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17253
86897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1725386897
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2231918118
Short name T1138
Test name
Test status
Simulation time 161680338 ps
CPU time 0.86 seconds
Started Jul 31 05:46:48 PM PDT 24
Finished Jul 31 05:46:49 PM PDT 24
Peak memory 206964 kb
Host smart-f240acf4-b7ee-4e5b-99b4-bda14af08291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22319
18118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2231918118
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.3861020479
Short name T1662
Test name
Test status
Simulation time 232362208 ps
CPU time 1.02 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:46:47 PM PDT 24
Peak memory 207008 kb
Host smart-b75a64ed-f1c2-4912-ae79-7ed1291d745b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3861020479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3861020479
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.478685360
Short name T2719
Test name
Test status
Simulation time 149979845 ps
CPU time 0.89 seconds
Started Jul 31 05:46:48 PM PDT 24
Finished Jul 31 05:46:49 PM PDT 24
Peak memory 206932 kb
Host smart-84d6d8bb-767b-44eb-850b-3f7479e4494d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47868
5360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.478685360
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3023296264
Short name T852
Test name
Test status
Simulation time 65357110 ps
CPU time 0.72 seconds
Started Jul 31 05:46:47 PM PDT 24
Finished Jul 31 05:46:48 PM PDT 24
Peak memory 206956 kb
Host smart-c1dff21e-0fe5-45d3-b45e-f05dbc53a134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30232
96264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3023296264
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2976083239
Short name T1898
Test name
Test status
Simulation time 21404495183 ps
CPU time 53.84 seconds
Started Jul 31 05:46:45 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 215436 kb
Host smart-c5a7eb72-ec37-451e-9c0b-e1fe0baf8b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29760
83239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2976083239
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.2951439661
Short name T930
Test name
Test status
Simulation time 183948567 ps
CPU time 0.9 seconds
Started Jul 31 05:46:51 PM PDT 24
Finished Jul 31 05:46:52 PM PDT 24
Peak memory 206968 kb
Host smart-7df351f2-cad9-4537-8393-e3c153128010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29514
39661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2951439661
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.3797787494
Short name T2685
Test name
Test status
Simulation time 320307869 ps
CPU time 1.16 seconds
Started Jul 31 05:46:50 PM PDT 24
Finished Jul 31 05:46:51 PM PDT 24
Peak memory 206996 kb
Host smart-96c1765e-763b-4843-bb91-e3d7bfb73c93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37977
87494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3797787494
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.586380163
Short name T632
Test name
Test status
Simulation time 256295473 ps
CPU time 1 seconds
Started Jul 31 05:46:47 PM PDT 24
Finished Jul 31 05:46:48 PM PDT 24
Peak memory 206844 kb
Host smart-6578bd27-968f-4546-b1b5-9aeafdf07d5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58638
0163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.586380163
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.1624195264
Short name T2188
Test name
Test status
Simulation time 215980864 ps
CPU time 0.89 seconds
Started Jul 31 05:46:46 PM PDT 24
Finished Jul 31 05:46:46 PM PDT 24
Peak memory 206984 kb
Host smart-8f5338d8-31c7-4018-96cb-836bb9cafece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16241
95264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.1624195264
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2071523359
Short name T2840
Test name
Test status
Simulation time 180122164 ps
CPU time 0.84 seconds
Started Jul 31 05:46:43 PM PDT 24
Finished Jul 31 05:46:44 PM PDT 24
Peak memory 207024 kb
Host smart-250a8b0d-72b8-4e84-bff1-899f6fa70b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715
23359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2071523359
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1259963733
Short name T408
Test name
Test status
Simulation time 147546348 ps
CPU time 0.88 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:46:45 PM PDT 24
Peak memory 206960 kb
Host smart-5b866037-3108-4937-86c6-4f86ab6078ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12599
63733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1259963733
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2017281314
Short name T2010
Test name
Test status
Simulation time 150090277 ps
CPU time 0.86 seconds
Started Jul 31 05:46:47 PM PDT 24
Finished Jul 31 05:46:48 PM PDT 24
Peak memory 207008 kb
Host smart-4f07656b-0ece-484f-b3e8-ced418b633ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20172
81314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2017281314
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.486241333
Short name T1958
Test name
Test status
Simulation time 219503364 ps
CPU time 1.08 seconds
Started Jul 31 05:46:52 PM PDT 24
Finished Jul 31 05:46:53 PM PDT 24
Peak memory 206960 kb
Host smart-09c51b28-8439-49eb-8ba6-0ca884a8386d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48624
1333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.486241333
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.113626110
Short name T1393
Test name
Test status
Simulation time 6312963270 ps
CPU time 49.41 seconds
Started Jul 31 05:46:54 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 215352 kb
Host smart-5ebb4343-a320-44e9-a4bb-7d57e3c93e43
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=113626110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.113626110
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2604731788
Short name T1808
Test name
Test status
Simulation time 147935019 ps
CPU time 0.83 seconds
Started Jul 31 05:46:54 PM PDT 24
Finished Jul 31 05:46:55 PM PDT 24
Peak memory 206968 kb
Host smart-186dfc6a-47a3-4857-ab13-f990aa16de5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26047
31788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2604731788
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.3851796859
Short name T1787
Test name
Test status
Simulation time 203492194 ps
CPU time 1 seconds
Started Jul 31 05:46:55 PM PDT 24
Finished Jul 31 05:46:56 PM PDT 24
Peak memory 206964 kb
Host smart-6913b341-2dff-4e4c-837b-eab6713fa7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38517
96859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.3851796859
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.2216984393
Short name T726
Test name
Test status
Simulation time 1241431020 ps
CPU time 3.27 seconds
Started Jul 31 05:46:53 PM PDT 24
Finished Jul 31 05:46:57 PM PDT 24
Peak memory 207044 kb
Host smart-926ac780-f4d5-40cb-8b00-b66d7b093792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22169
84393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.2216984393
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.872054581
Short name T512
Test name
Test status
Simulation time 5369969526 ps
CPU time 55.66 seconds
Started Jul 31 05:46:52 PM PDT 24
Finished Jul 31 05:47:47 PM PDT 24
Peak memory 216896 kb
Host smart-7112166c-2b55-47f4-aca3-38a8b5a12650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87205
4581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.872054581
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.2082944612
Short name T959
Test name
Test status
Simulation time 146933258 ps
CPU time 0.86 seconds
Started Jul 31 05:46:44 PM PDT 24
Finished Jul 31 05:46:45 PM PDT 24
Peak memory 206996 kb
Host smart-7e3bb612-b26d-4eff-8161-e4d2d81cc0b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082944612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.2082944612
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.793932994
Short name T1542
Test name
Test status
Simulation time 54267287 ps
CPU time 0.71 seconds
Started Jul 31 05:47:18 PM PDT 24
Finished Jul 31 05:47:19 PM PDT 24
Peak memory 207040 kb
Host smart-98664a62-c2a8-472d-ab7b-4aa2fea48661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=793932994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.793932994
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.4072196970
Short name T2153
Test name
Test status
Simulation time 3945367789 ps
CPU time 5.42 seconds
Started Jul 31 05:46:52 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 207156 kb
Host smart-d63f3806-39f8-4dab-b953-f41ea341d40b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072196970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_disconnect.4072196970
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.256830644
Short name T2819
Test name
Test status
Simulation time 13399099546 ps
CPU time 15.08 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:17 PM PDT 24
Peak memory 207192 kb
Host smart-2a4a2aa2-80db-4b5e-b07c-938d2f43d4d6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=256830644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.256830644
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.1993644806
Short name T1877
Test name
Test status
Simulation time 23464716964 ps
CPU time 29.44 seconds
Started Jul 31 05:46:53 PM PDT 24
Finished Jul 31 05:47:23 PM PDT 24
Peak memory 207196 kb
Host smart-8386901f-5559-4b8d-8f58-26d2f1156dc3
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993644806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.1993644806
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3000084589
Short name T2635
Test name
Test status
Simulation time 158235309 ps
CPU time 0.89 seconds
Started Jul 31 05:46:51 PM PDT 24
Finished Jul 31 05:46:52 PM PDT 24
Peak memory 206988 kb
Host smart-f21db616-8d34-4b37-965c-67611991576c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30000
84589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3000084589
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1473265941
Short name T933
Test name
Test status
Simulation time 151411493 ps
CPU time 0.85 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 206928 kb
Host smart-644ec262-488e-4366-9b1e-0e0a8bd4fad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14732
65941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1473265941
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.4122337776
Short name T1082
Test name
Test status
Simulation time 334077011 ps
CPU time 1.3 seconds
Started Jul 31 05:46:52 PM PDT 24
Finished Jul 31 05:46:53 PM PDT 24
Peak memory 206996 kb
Host smart-2cf58022-4aba-4a61-b3e6-f4b1df4ae8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41223
37776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.4122337776
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3740014390
Short name T77
Test name
Test status
Simulation time 500491442 ps
CPU time 1.51 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 206960 kb
Host smart-1580f892-82f6-4c86-9c0d-c7ce200e9676
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3740014390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3740014390
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.3734999394
Short name T1900
Test name
Test status
Simulation time 18718754336 ps
CPU time 37.58 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:39 PM PDT 24
Peak memory 207220 kb
Host smart-0c972565-c83e-4595-bb76-4facaf25b73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37349
99394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.3734999394
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_device_timeout.3936292205
Short name T627
Test name
Test status
Simulation time 1944495735 ps
CPU time 14.02 seconds
Started Jul 31 05:46:52 PM PDT 24
Finished Jul 31 05:47:06 PM PDT 24
Peak memory 207044 kb
Host smart-144a9a33-1eca-45b7-804a-92da4c217ac5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936292205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.3936292205
Directory /workspace/46.usbdev_device_timeout/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.2204013328
Short name T1601
Test name
Test status
Simulation time 388971202 ps
CPU time 1.43 seconds
Started Jul 31 05:46:48 PM PDT 24
Finished Jul 31 05:46:49 PM PDT 24
Peak memory 206952 kb
Host smart-7324ddec-da8b-4b6f-b887-fa1e473f00fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
13328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.2204013328
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.1357151322
Short name T1468
Test name
Test status
Simulation time 155443473 ps
CPU time 0.85 seconds
Started Jul 31 05:46:51 PM PDT 24
Finished Jul 31 05:46:52 PM PDT 24
Peak memory 207004 kb
Host smart-63b5f2ef-9091-4caa-a453-e9d30c300755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13571
51322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.1357151322
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1599111287
Short name T497
Test name
Test status
Simulation time 34665790 ps
CPU time 0.75 seconds
Started Jul 31 05:46:51 PM PDT 24
Finished Jul 31 05:46:52 PM PDT 24
Peak memory 206944 kb
Host smart-037c0027-06de-487e-90a2-8dab72c98def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15991
11287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1599111287
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.84727196
Short name T901
Test name
Test status
Simulation time 760444599 ps
CPU time 2.21 seconds
Started Jul 31 05:46:53 PM PDT 24
Finished Jul 31 05:46:55 PM PDT 24
Peak memory 207116 kb
Host smart-fe57d21d-8f75-4c97-9e2f-da1f42e8afd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84727
196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.84727196
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.1928304953
Short name T607
Test name
Test status
Simulation time 247998016 ps
CPU time 2.45 seconds
Started Jul 31 05:46:55 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 207028 kb
Host smart-b718145d-ada4-4457-ad45-9d1734c5e813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19283
04953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1928304953
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.47159900
Short name T1445
Test name
Test status
Simulation time 181504345 ps
CPU time 0.99 seconds
Started Jul 31 05:46:53 PM PDT 24
Finished Jul 31 05:46:54 PM PDT 24
Peak memory 207096 kb
Host smart-950b7cf5-ac41-4d51-ba75-42c1078acdf7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=47159900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.47159900
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.1241690222
Short name T421
Test name
Test status
Simulation time 146433460 ps
CPU time 0.8 seconds
Started Jul 31 05:46:52 PM PDT 24
Finished Jul 31 05:46:53 PM PDT 24
Peak memory 206984 kb
Host smart-9937f8d7-de75-4486-b60a-d43701269ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12416
90222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.1241690222
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.2325782588
Short name T918
Test name
Test status
Simulation time 194964269 ps
CPU time 0.96 seconds
Started Jul 31 05:46:54 PM PDT 24
Finished Jul 31 05:46:55 PM PDT 24
Peak memory 207044 kb
Host smart-d12a6e92-dfb4-471d-90c5-d8ed8b61d56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23257
82588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.2325782588
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.1286509489
Short name T2235
Test name
Test status
Simulation time 6801634403 ps
CPU time 66.85 seconds
Started Jul 31 05:46:51 PM PDT 24
Finished Jul 31 05:47:58 PM PDT 24
Peak memory 215392 kb
Host smart-dcf969f1-632d-4bf1-a5b4-0ae31f6d694f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1286509489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.1286509489
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.3424938486
Short name T2603
Test name
Test status
Simulation time 5266048328 ps
CPU time 38.88 seconds
Started Jul 31 05:46:54 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 207168 kb
Host smart-322071f2-908f-4d3f-97c6-25aef7652d39
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3424938486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.3424938486
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2970641323
Short name T206
Test name
Test status
Simulation time 206353471 ps
CPU time 0.97 seconds
Started Jul 31 05:46:51 PM PDT 24
Finished Jul 31 05:46:52 PM PDT 24
Peak memory 206992 kb
Host smart-8902ac80-bb72-4e53-ad27-ab86b47d458f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29706
41323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2970641323
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2428351501
Short name T1798
Test name
Test status
Simulation time 23289044209 ps
CPU time 25.44 seconds
Started Jul 31 05:46:53 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 207172 kb
Host smart-252af514-82eb-425c-a1fe-aff1b1968d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24283
51501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2428351501
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.1460854581
Short name T880
Test name
Test status
Simulation time 3291704320 ps
CPU time 4.89 seconds
Started Jul 31 05:46:55 PM PDT 24
Finished Jul 31 05:47:00 PM PDT 24
Peak memory 207112 kb
Host smart-6c226765-2178-42ed-9abf-79e8c9983ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14608
54581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1460854581
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1787136491
Short name T1234
Test name
Test status
Simulation time 7539837239 ps
CPU time 70.43 seconds
Started Jul 31 05:46:55 PM PDT 24
Finished Jul 31 05:48:05 PM PDT 24
Peak memory 216596 kb
Host smart-2a70b006-b07d-49d2-91d0-8c746038d139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17871
36491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1787136491
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3758496103
Short name T338
Test name
Test status
Simulation time 4116255442 ps
CPU time 29.38 seconds
Started Jul 31 05:46:48 PM PDT 24
Finished Jul 31 05:47:17 PM PDT 24
Peak memory 215412 kb
Host smart-78f686d7-cc0e-4a2d-97fd-51ee230775f1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3758496103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3758496103
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1248995189
Short name T2762
Test name
Test status
Simulation time 253449744 ps
CPU time 1.04 seconds
Started Jul 31 05:46:59 PM PDT 24
Finished Jul 31 05:47:00 PM PDT 24
Peak memory 207012 kb
Host smart-812f6e50-d5ea-444f-9120-057a7258cb33
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1248995189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1248995189
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.992225248
Short name T977
Test name
Test status
Simulation time 190724358 ps
CPU time 0.96 seconds
Started Jul 31 05:46:55 PM PDT 24
Finished Jul 31 05:46:56 PM PDT 24
Peak memory 207008 kb
Host smart-2bee1484-e100-43d2-a584-c1eae10f6c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99222
5248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.992225248
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2740391608
Short name T1901
Test name
Test status
Simulation time 6076891480 ps
CPU time 48.49 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:49 PM PDT 24
Peak memory 215424 kb
Host smart-d6f2a6ac-e826-4698-ae13-266bf6462764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27403
91608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2740391608
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.48264040
Short name T1215
Test name
Test status
Simulation time 4847024494 ps
CPU time 39.37 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:40 PM PDT 24
Peak memory 215436 kb
Host smart-08a53fd9-62a5-43a0-8321-597e4e88b615
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=48264040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.48264040
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.2093640441
Short name T1975
Test name
Test status
Simulation time 153657963 ps
CPU time 0.85 seconds
Started Jul 31 05:46:57 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 206988 kb
Host smart-686682fc-70b0-4ec7-a9ed-44e8fdbb59b2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2093640441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.2093640441
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.806889716
Short name T1310
Test name
Test status
Simulation time 174091362 ps
CPU time 0.87 seconds
Started Jul 31 05:47:28 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 207004 kb
Host smart-751fb6fd-b804-4544-a035-0faffc92ff84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80688
9716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.806889716
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3696533667
Short name T113
Test name
Test status
Simulation time 212915041 ps
CPU time 0.94 seconds
Started Jul 31 05:46:58 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 207032 kb
Host smart-cef3fbf1-8b20-48d2-a5ab-1bd4cc8cbaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36965
33667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3696533667
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.521146184
Short name T1055
Test name
Test status
Simulation time 172173545 ps
CPU time 0.86 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:01 PM PDT 24
Peak memory 207024 kb
Host smart-b320a4fe-bdc9-4090-8c02-119626266c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52114
6184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.521146184
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.1665962553
Short name T2428
Test name
Test status
Simulation time 183628728 ps
CPU time 0.87 seconds
Started Jul 31 05:46:59 PM PDT 24
Finished Jul 31 05:47:00 PM PDT 24
Peak memory 207024 kb
Host smart-45b4d89e-04e4-4abd-ba03-9d726ee028c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16659
62553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.1665962553
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1751589643
Short name T1248
Test name
Test status
Simulation time 238275421 ps
CPU time 0.99 seconds
Started Jul 31 05:46:57 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 207000 kb
Host smart-0aa86967-917d-4681-a3d6-c12eb0d5e125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17515
89643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1751589643
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.914520306
Short name T1294
Test name
Test status
Simulation time 166094938 ps
CPU time 0.9 seconds
Started Jul 31 05:46:57 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 207052 kb
Host smart-78d9c626-ab7e-404f-8dbb-842b86e5a7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91452
0306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.914520306
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3115249592
Short name T2613
Test name
Test status
Simulation time 215272649 ps
CPU time 1.09 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:01 PM PDT 24
Peak memory 206992 kb
Host smart-7b71b8ab-5934-47c3-9c47-cc0111a0d7e5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3115249592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3115249592
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.1075867381
Short name T1102
Test name
Test status
Simulation time 138459376 ps
CPU time 0.87 seconds
Started Jul 31 05:46:57 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 206976 kb
Host smart-28e3cdbb-9ed3-4706-a435-1ece6f01f88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10758
67381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.1075867381
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3995893480
Short name T24
Test name
Test status
Simulation time 27627893 ps
CPU time 0.66 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:17 PM PDT 24
Peak memory 206976 kb
Host smart-4230463f-08f0-4060-b48d-de8226c179fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39958
93480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3995893480
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3874919887
Short name T236
Test name
Test status
Simulation time 9790876570 ps
CPU time 25.71 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:26 PM PDT 24
Peak memory 215388 kb
Host smart-0a6d01c9-1855-4d7e-8593-7c721117af87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38749
19887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3874919887
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.4135161697
Short name T2099
Test name
Test status
Simulation time 178850212 ps
CPU time 0.89 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:01 PM PDT 24
Peak memory 206988 kb
Host smart-b62c78fe-f00a-4d76-a4f8-378d84734472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41351
61697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.4135161697
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.3103720087
Short name T398
Test name
Test status
Simulation time 224956549 ps
CPU time 1.03 seconds
Started Jul 31 05:46:53 PM PDT 24
Finished Jul 31 05:46:54 PM PDT 24
Peak memory 206920 kb
Host smart-fb040280-4c10-4b1b-add2-bea478586d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31037
20087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.3103720087
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.13209647
Short name T2089
Test name
Test status
Simulation time 186482920 ps
CPU time 0.91 seconds
Started Jul 31 05:46:58 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 207024 kb
Host smart-65103ca6-ddb7-4eb8-89ad-975fb892462a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13209
647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.13209647
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.4205157816
Short name T2021
Test name
Test status
Simulation time 189212764 ps
CPU time 0.96 seconds
Started Jul 31 05:46:59 PM PDT 24
Finished Jul 31 05:47:00 PM PDT 24
Peak memory 206992 kb
Host smart-ecc7fdaf-da96-4f1c-be80-d6ebb264fa0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42051
57816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.4205157816
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.178956567
Short name T2470
Test name
Test status
Simulation time 131705000 ps
CPU time 0.8 seconds
Started Jul 31 05:46:58 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 206980 kb
Host smart-0bbf6673-00e1-4c19-aac5-a964757f73f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17895
6567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.178956567
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3917441309
Short name T2453
Test name
Test status
Simulation time 165686766 ps
CPU time 0.83 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 206784 kb
Host smart-d01f70ff-1a3f-4e00-a7f7-260359f60b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39174
41309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3917441309
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.117635995
Short name T1962
Test name
Test status
Simulation time 188733844 ps
CPU time 0.94 seconds
Started Jul 31 05:46:59 PM PDT 24
Finished Jul 31 05:47:00 PM PDT 24
Peak memory 206996 kb
Host smart-30dc90fe-6de0-4092-9efc-0e2f8dd7c036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11763
5995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.117635995
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2851428716
Short name T1017
Test name
Test status
Simulation time 262732583 ps
CPU time 1.07 seconds
Started Jul 31 05:46:58 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 206988 kb
Host smart-e4086398-c7de-4ef0-85f2-e29e03dcca14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28514
28716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2851428716
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.867508365
Short name T1366
Test name
Test status
Simulation time 5919709197 ps
CPU time 167.84 seconds
Started Jul 31 05:46:56 PM PDT 24
Finished Jul 31 05:49:44 PM PDT 24
Peak memory 215380 kb
Host smart-2b0f057e-feea-44a4-868f-f82916740583
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=867508365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.867508365
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.1500857315
Short name T1826
Test name
Test status
Simulation time 189491245 ps
CPU time 0.92 seconds
Started Jul 31 05:46:56 PM PDT 24
Finished Jul 31 05:46:57 PM PDT 24
Peak memory 207040 kb
Host smart-7bb53191-f257-4c1e-a916-a48d838f6110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15008
57315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.1500857315
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.3503802051
Short name T1521
Test name
Test status
Simulation time 212559962 ps
CPU time 0.92 seconds
Started Jul 31 05:46:56 PM PDT 24
Finished Jul 31 05:46:57 PM PDT 24
Peak memory 206984 kb
Host smart-bc7d16d4-0365-4c5d-aaf2-05f2006605b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35038
02051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.3503802051
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.881902685
Short name T1204
Test name
Test status
Simulation time 269246504 ps
CPU time 1.03 seconds
Started Jul 31 05:46:58 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 206952 kb
Host smart-31dbd42c-4471-4c7f-a051-3a0e2c8f30b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88190
2685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.881902685
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.1756899746
Short name T2724
Test name
Test status
Simulation time 5403416106 ps
CPU time 41.56 seconds
Started Jul 31 05:46:57 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 215436 kb
Host smart-f12edc2d-dee8-4e31-adf5-1fefb82b6b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17568
99746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1756899746
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.2239753475
Short name T2381
Test name
Test status
Simulation time 7898553745 ps
CPU time 54.62 seconds
Started Jul 31 05:46:50 PM PDT 24
Finished Jul 31 05:47:45 PM PDT 24
Peak memory 207220 kb
Host smart-5abd7c0c-b140-49dd-9db4-2ee1d4eecc2c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239753475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.2239753475
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.2278280322
Short name T2628
Test name
Test status
Simulation time 49315675 ps
CPU time 0.69 seconds
Started Jul 31 05:47:03 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 207008 kb
Host smart-727af31d-93cf-4d71-8dec-4721247f4b36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2278280322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.2278280322
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.496006616
Short name T1851
Test name
Test status
Simulation time 4061598083 ps
CPU time 7.08 seconds
Started Jul 31 05:46:59 PM PDT 24
Finished Jul 31 05:47:07 PM PDT 24
Peak memory 207140 kb
Host smart-68af9eab-f871-45ac-a576-3e696e846ffd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496006616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ao
n_wake_disconnect.496006616
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.560044409
Short name T16
Test name
Test status
Simulation time 13391419441 ps
CPU time 16.18 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:23 PM PDT 24
Peak memory 207188 kb
Host smart-58e1c796-8e78-4258-83d5-47f7bd32c1f0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=560044409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.560044409
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.2665475249
Short name T1216
Test name
Test status
Simulation time 23351618463 ps
CPU time 27.63 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:28 PM PDT 24
Peak memory 207176 kb
Host smart-e2173385-f3f4-4a18-802b-c4fd778a9bc1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665475249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_a
on_wake_resume.2665475249
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2090728040
Short name T1150
Test name
Test status
Simulation time 169492451 ps
CPU time 0.92 seconds
Started Jul 31 05:47:18 PM PDT 24
Finished Jul 31 05:47:19 PM PDT 24
Peak memory 207032 kb
Host smart-ece85b3d-6059-4d19-86ef-6185bfecb503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20907
28040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2090728040
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.3555049223
Short name T2282
Test name
Test status
Simulation time 139782721 ps
CPU time 0.87 seconds
Started Jul 31 05:47:26 PM PDT 24
Finished Jul 31 05:47:27 PM PDT 24
Peak memory 206980 kb
Host smart-86ef0ef8-f23f-4948-a2bf-e5a3d6c350b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35550
49223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.3555049223
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.23885211
Short name T2681
Test name
Test status
Simulation time 221232317 ps
CPU time 1.08 seconds
Started Jul 31 05:47:01 PM PDT 24
Finished Jul 31 05:47:02 PM PDT 24
Peak memory 206984 kb
Host smart-7d7730a0-56cc-45e8-9761-df4f35dca328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23885
211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.23885211
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.2780042097
Short name T2457
Test name
Test status
Simulation time 402757756 ps
CPU time 1.38 seconds
Started Jul 31 05:46:57 PM PDT 24
Finished Jul 31 05:46:58 PM PDT 24
Peak memory 206628 kb
Host smart-2534d7de-a569-4d9e-948e-70d1ddac0f6b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2780042097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.2780042097
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.1579814428
Short name T281
Test name
Test status
Simulation time 9254828240 ps
CPU time 19.45 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 207240 kb
Host smart-76b7c8aa-1c1b-42f4-bf48-54c046925db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15798
14428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.1579814428
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_device_timeout.2202685123
Short name T798
Test name
Test status
Simulation time 989726351 ps
CPU time 22.8 seconds
Started Jul 31 05:46:59 PM PDT 24
Finished Jul 31 05:47:22 PM PDT 24
Peak memory 207020 kb
Host smart-edc1c1c8-ba34-452d-9021-265546b7ef78
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202685123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.2202685123
Directory /workspace/47.usbdev_device_timeout/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.3646259348
Short name T2420
Test name
Test status
Simulation time 349427174 ps
CPU time 1.34 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:02 PM PDT 24
Peak memory 206952 kb
Host smart-f7c52249-7659-4875-a9de-9597580eff68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36462
59348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.3646259348
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3058195856
Short name T2214
Test name
Test status
Simulation time 134223277 ps
CPU time 0.84 seconds
Started Jul 31 05:46:58 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 206964 kb
Host smart-c7984939-82ff-4e71-9abd-3cff52681ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30581
95856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3058195856
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.3593865518
Short name T1118
Test name
Test status
Simulation time 77316456 ps
CPU time 0.74 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:01 PM PDT 24
Peak memory 206956 kb
Host smart-09e95865-c605-4cd9-8eb0-f328b95e5197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35938
65518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.3593865518
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.3215491421
Short name T1453
Test name
Test status
Simulation time 870944187 ps
CPU time 2.28 seconds
Started Jul 31 05:46:57 PM PDT 24
Finished Jul 31 05:47:00 PM PDT 24
Peak memory 207032 kb
Host smart-d4bca753-a048-4c8b-9069-7a036718f94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32154
91421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.3215491421
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.1671318802
Short name T175
Test name
Test status
Simulation time 170231110 ps
CPU time 2.09 seconds
Started Jul 31 05:46:57 PM PDT 24
Finished Jul 31 05:46:59 PM PDT 24
Peak memory 207044 kb
Host smart-b8c3bc86-ddc8-4707-b126-a39269852f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16713
18802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.1671318802
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2901836309
Short name T2559
Test name
Test status
Simulation time 198344463 ps
CPU time 1.11 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 215312 kb
Host smart-992e98fa-a991-4092-877c-22721b87130a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2901836309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2901836309
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.4250186239
Short name T2586
Test name
Test status
Simulation time 140917350 ps
CPU time 0.79 seconds
Started Jul 31 05:46:55 PM PDT 24
Finished Jul 31 05:46:56 PM PDT 24
Peak memory 206952 kb
Host smart-43759171-bd11-4a05-a681-2b581029cada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42501
86239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.4250186239
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.218829981
Short name T1325
Test name
Test status
Simulation time 233858940 ps
CPU time 1.01 seconds
Started Jul 31 05:47:16 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 207016 kb
Host smart-4ad25c56-b2e3-4109-ae03-b0eb7c6ed61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21882
9981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.218829981
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.3401953596
Short name T2378
Test name
Test status
Simulation time 10137157352 ps
CPU time 82.51 seconds
Started Jul 31 05:46:56 PM PDT 24
Finished Jul 31 05:48:19 PM PDT 24
Peak memory 215392 kb
Host smart-90f5b491-71a4-4cd7-9569-702a1072d689
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3401953596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3401953596
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.356007906
Short name T1671
Test name
Test status
Simulation time 9042820203 ps
CPU time 62.22 seconds
Started Jul 31 05:46:57 PM PDT 24
Finished Jul 31 05:47:59 PM PDT 24
Peak memory 206808 kb
Host smart-20c4a68f-1eaa-4329-9611-064a16137ad3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=356007906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.356007906
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3402405170
Short name T1264
Test name
Test status
Simulation time 217863117 ps
CPU time 0.98 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 206796 kb
Host smart-b2ea8d78-b89d-4e70-8701-5267b5bcfde3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34024
05170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3402405170
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.3218440412
Short name T1700
Test name
Test status
Simulation time 23310843875 ps
CPU time 33.94 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:35 PM PDT 24
Peak memory 207160 kb
Host smart-7307762f-bc20-4c4c-b1fe-3815cc6e69da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32184
40412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.3218440412
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.4213679512
Short name T578
Test name
Test status
Simulation time 3316854830 ps
CPU time 4.77 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 207148 kb
Host smart-e7125a3c-df5f-4cbc-8f95-d9f1641a7169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42136
79512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.4213679512
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3268566578
Short name T1839
Test name
Test status
Simulation time 8623511115 ps
CPU time 67.78 seconds
Started Jul 31 05:46:58 PM PDT 24
Finished Jul 31 05:48:06 PM PDT 24
Peak memory 217324 kb
Host smart-52921345-a877-402f-9170-9c107dd52cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32685
66578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3268566578
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2839916056
Short name T1456
Test name
Test status
Simulation time 5224867824 ps
CPU time 40.74 seconds
Started Jul 31 05:47:27 PM PDT 24
Finished Jul 31 05:48:08 PM PDT 24
Peak memory 207244 kb
Host smart-e8617767-f622-40ca-8b0c-a36024337a0f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2839916056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2839916056
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3958234359
Short name T2057
Test name
Test status
Simulation time 241871805 ps
CPU time 1.01 seconds
Started Jul 31 05:46:56 PM PDT 24
Finished Jul 31 05:46:57 PM PDT 24
Peak memory 207004 kb
Host smart-28c437d1-16bc-4ed5-8e06-10fbc7109706
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3958234359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3958234359
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2175811897
Short name T544
Test name
Test status
Simulation time 242458133 ps
CPU time 1.02 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 207004 kb
Host smart-6f2d036b-0cc3-4442-8a88-b00720891a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21758
11897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2175811897
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2682374088
Short name T635
Test name
Test status
Simulation time 4298908200 ps
CPU time 30.56 seconds
Started Jul 31 05:47:18 PM PDT 24
Finished Jul 31 05:47:48 PM PDT 24
Peak memory 215464 kb
Host smart-abae41fb-2da8-4004-82f5-14ca6f5f5417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26823
74088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2682374088
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.462982431
Short name T731
Test name
Test status
Simulation time 6669006887 ps
CPU time 64.68 seconds
Started Jul 31 05:46:59 PM PDT 24
Finished Jul 31 05:48:04 PM PDT 24
Peak memory 207248 kb
Host smart-2ca68aa1-e228-40ab-8cac-275d8861182a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=462982431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.462982431
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.166846721
Short name T1391
Test name
Test status
Simulation time 160404348 ps
CPU time 0.89 seconds
Started Jul 31 05:47:16 PM PDT 24
Finished Jul 31 05:47:17 PM PDT 24
Peak memory 207020 kb
Host smart-806cf666-31f0-40c3-91ad-4c90dacb6b43
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=166846721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.166846721
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.4031639345
Short name T334
Test name
Test status
Simulation time 193112329 ps
CPU time 0.88 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 207056 kb
Host smart-09370a85-efef-4c6e-9290-01377f0806d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40316
39345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.4031639345
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.4197529138
Short name T107
Test name
Test status
Simulation time 257994633 ps
CPU time 0.98 seconds
Started Jul 31 05:47:03 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 207012 kb
Host smart-b7b7e99e-f311-47c7-a43c-33136334b34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41975
29138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4197529138
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3753430285
Short name T243
Test name
Test status
Simulation time 156506425 ps
CPU time 0.95 seconds
Started Jul 31 05:47:01 PM PDT 24
Finished Jul 31 05:47:02 PM PDT 24
Peak memory 206992 kb
Host smart-cc682804-f9e2-4760-8acf-5c57ba4f1940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37534
30285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3753430285
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.859538229
Short name T2256
Test name
Test status
Simulation time 164844397 ps
CPU time 0.87 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:01 PM PDT 24
Peak memory 206984 kb
Host smart-06e94068-b6cc-4e89-a990-d1d25a2b37b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85953
8229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.859538229
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.637893542
Short name T499
Test name
Test status
Simulation time 157247383 ps
CPU time 0.88 seconds
Started Jul 31 05:47:03 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 206968 kb
Host smart-35b713f3-f7af-4cd2-ab59-90ba16f333cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63789
3542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.637893542
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.3769340336
Short name T1532
Test name
Test status
Simulation time 199028428 ps
CPU time 0.87 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 206976 kb
Host smart-e29f56ec-2de8-4f71-a3b4-6d3dedceaa69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37693
40336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.3769340336
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.2039133379
Short name T2477
Test name
Test status
Simulation time 226810114 ps
CPU time 1.08 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 207000 kb
Host smart-243ae571-70b6-4e77-afa4-ca0f8223dd3b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2039133379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.2039133379
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.568528275
Short name T1758
Test name
Test status
Simulation time 155192645 ps
CPU time 0.83 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 206952 kb
Host smart-5bbf7b48-c23c-476e-b91f-0e649127d398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56852
8275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.568528275
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2721047840
Short name T1881
Test name
Test status
Simulation time 51250935 ps
CPU time 0.72 seconds
Started Jul 31 05:47:03 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 206948 kb
Host smart-75324400-ebf4-4025-8425-d0cabc658c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27210
47840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2721047840
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.2772458928
Short name T2700
Test name
Test status
Simulation time 17680203719 ps
CPU time 45.07 seconds
Started Jul 31 05:47:01 PM PDT 24
Finished Jul 31 05:47:46 PM PDT 24
Peak memory 215392 kb
Host smart-733515e7-3748-4dfc-a865-c922a9e565c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27724
58928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2772458928
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.577178046
Short name T576
Test name
Test status
Simulation time 224565585 ps
CPU time 1.04 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 206996 kb
Host smart-9906ad9c-9c2e-42ef-add7-fc62a056a6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57717
8046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.577178046
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.148674530
Short name T898
Test name
Test status
Simulation time 218499385 ps
CPU time 0.98 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 206960 kb
Host smart-bb32540d-8651-46f3-bd3d-c41c552fb548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14867
4530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.148674530
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.2443863818
Short name T430
Test name
Test status
Simulation time 162337416 ps
CPU time 1 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 206988 kb
Host smart-fc7f2b87-fb05-417d-943b-14d660363e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24438
63818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.2443863818
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3191417918
Short name T2761
Test name
Test status
Simulation time 213094758 ps
CPU time 0.95 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 207024 kb
Host smart-c3b29344-a6cf-4150-9da0-ccf1e14673a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31914
17918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3191417918
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.3840230376
Short name T1718
Test name
Test status
Simulation time 136778897 ps
CPU time 0.79 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 206968 kb
Host smart-e3f2335b-4252-42c4-808b-b1b5bb121e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38402
30376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.3840230376
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3217610832
Short name T1159
Test name
Test status
Simulation time 144925743 ps
CPU time 0.87 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 206960 kb
Host smart-d1928af2-2921-418c-9ec4-7fe1df753d5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32176
10832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3217610832
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1109542734
Short name T285
Test name
Test status
Simulation time 150270376 ps
CPU time 0.88 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 207012 kb
Host smart-f1eb4777-8b60-47e1-83eb-3cb9147bf3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11095
42734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1109542734
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1899504475
Short name T2571
Test name
Test status
Simulation time 236233670 ps
CPU time 1 seconds
Started Jul 31 05:47:03 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 206980 kb
Host smart-092f8319-79ac-4e48-bf98-33b7e3a9049a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18995
04475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1899504475
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.183855400
Short name T680
Test name
Test status
Simulation time 5221015745 ps
CPU time 142.66 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:49:27 PM PDT 24
Peak memory 215368 kb
Host smart-94b56569-c60b-4da0-905c-0f0055a012ac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=183855400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.183855400
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.811198298
Short name T2249
Test name
Test status
Simulation time 155470477 ps
CPU time 0.89 seconds
Started Jul 31 05:47:05 PM PDT 24
Finished Jul 31 05:47:06 PM PDT 24
Peak memory 207004 kb
Host smart-84c39d8d-fc56-42e7-991e-fadc8f44c11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81119
8298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.811198298
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3654936384
Short name T2157
Test name
Test status
Simulation time 211612222 ps
CPU time 0.9 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 206984 kb
Host smart-06f3e10c-fb5f-45d0-a10f-f0578f3f3faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36549
36384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3654936384
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.3844531404
Short name T1327
Test name
Test status
Simulation time 482058986 ps
CPU time 1.6 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:06 PM PDT 24
Peak memory 206968 kb
Host smart-fd5b7c11-5b70-4b73-a2d0-f9ac1bf97ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38445
31404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.3844531404
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.971057844
Short name T1889
Test name
Test status
Simulation time 3252195146 ps
CPU time 23.82 seconds
Started Jul 31 05:47:05 PM PDT 24
Finished Jul 31 05:47:29 PM PDT 24
Peak memory 216880 kb
Host smart-d22fb197-3e4c-4e08-a70a-07a48e00f910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97105
7844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.971057844
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.803030948
Short name T2151
Test name
Test status
Simulation time 299371602 ps
CPU time 4.52 seconds
Started Jul 31 05:47:00 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 207056 kb
Host smart-1357ca25-519f-4a99-9dfb-f0781851472a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803030948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_host
_handshake.803030948
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3722999812
Short name T385
Test name
Test status
Simulation time 51812204 ps
CPU time 0.74 seconds
Started Jul 31 05:47:18 PM PDT 24
Finished Jul 31 05:47:19 PM PDT 24
Peak memory 207020 kb
Host smart-0b05ac04-fa51-469f-a982-5bc96a3fd486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3722999812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3722999812
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1690703028
Short name T15
Test name
Test status
Simulation time 4049588657 ps
CPU time 5.87 seconds
Started Jul 31 05:46:59 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 207156 kb
Host smart-2a91847b-bbbe-4b3c-a66b-034528c98366
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690703028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.1690703028
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3338225024
Short name T1106
Test name
Test status
Simulation time 13396603827 ps
CPU time 15.58 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 207224 kb
Host smart-b76e1721-4290-4ace-ab22-c9e6436e38fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338225024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3338225024
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.1393399238
Short name T1354
Test name
Test status
Simulation time 23394541379 ps
CPU time 32.32 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:36 PM PDT 24
Peak memory 207256 kb
Host smart-d71eef62-06f0-4092-ba07-ced508d3a0b4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393399238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.1393399238
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1615721316
Short name T1028
Test name
Test status
Simulation time 156797184 ps
CPU time 0.85 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 207020 kb
Host smart-fd7f4ef6-07d4-49d9-b37f-9426f5a9264b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16157
21316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1615721316
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.309273880
Short name T1190
Test name
Test status
Simulation time 149725101 ps
CPU time 0.85 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 206968 kb
Host smart-de815810-c80b-4427-9599-8acba51021fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30927
3880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.309273880
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.3959282460
Short name T1655
Test name
Test status
Simulation time 510968602 ps
CPU time 1.82 seconds
Started Jul 31 05:47:03 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 207004 kb
Host smart-74772cc8-9d24-4b05-9c64-8fddad44c26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39592
82460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.3959282460
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1819363608
Short name T990
Test name
Test status
Simulation time 317862307 ps
CPU time 1.2 seconds
Started Jul 31 05:47:02 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 206996 kb
Host smart-4d0b71d7-a61d-467d-979d-2a3301024c06
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1819363608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1819363608
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.274042242
Short name T1752
Test name
Test status
Simulation time 13608285980 ps
CPU time 31.42 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:35 PM PDT 24
Peak memory 207240 kb
Host smart-039d63bc-baba-4eb3-8f25-4c4ed2549cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27404
2242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.274042242
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_device_timeout.1580529446
Short name T1440
Test name
Test status
Simulation time 1271715553 ps
CPU time 29.78 seconds
Started Jul 31 05:47:03 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 207120 kb
Host smart-20467ed3-36e2-40cb-9467-04f085c73e56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580529446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.1580529446
Directory /workspace/48.usbdev_device_timeout/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.513648766
Short name T1260
Test name
Test status
Simulation time 464102321 ps
CPU time 1.5 seconds
Started Jul 31 05:47:03 PM PDT 24
Finished Jul 31 05:47:05 PM PDT 24
Peak memory 206960 kb
Host smart-32dfe89e-a65f-4472-86b0-6cb7f13b9991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51364
8766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.513648766
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.174814231
Short name T2161
Test name
Test status
Simulation time 157908024 ps
CPU time 0.85 seconds
Started Jul 31 05:47:03 PM PDT 24
Finished Jul 31 05:47:04 PM PDT 24
Peak memory 206956 kb
Host smart-df6099d5-fcca-4f2f-9e71-677405138b9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17481
4231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.174814231
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.4018215706
Short name T2610
Test name
Test status
Simulation time 61302049 ps
CPU time 0.74 seconds
Started Jul 31 05:47:01 PM PDT 24
Finished Jul 31 05:47:02 PM PDT 24
Peak memory 206936 kb
Host smart-2f0cf1c8-608c-489a-9b52-82123af55c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40182
15706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.4018215706
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.4102920297
Short name T2695
Test name
Test status
Simulation time 754194973 ps
CPU time 2.1 seconds
Started Jul 31 05:47:01 PM PDT 24
Finished Jul 31 05:47:03 PM PDT 24
Peak memory 207128 kb
Host smart-628135bc-0a7d-46c1-86ec-55c30ecec66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41029
20297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.4102920297
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3522917958
Short name T868
Test name
Test status
Simulation time 179936951 ps
CPU time 1.9 seconds
Started Jul 31 05:47:04 PM PDT 24
Finished Jul 31 05:47:06 PM PDT 24
Peak memory 207040 kb
Host smart-c12bd63b-56d5-40ae-a93f-4826e382a71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35229
17958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3522917958
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.4254792387
Short name T2093
Test name
Test status
Simulation time 187225500 ps
CPU time 0.99 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 207092 kb
Host smart-99c7b829-45fa-4891-b67b-ecc3b75ec9ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4254792387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.4254792387
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2416896073
Short name T2166
Test name
Test status
Simulation time 136747328 ps
CPU time 0.84 seconds
Started Jul 31 05:47:14 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 206944 kb
Host smart-457d9b4d-a8a1-43d4-9596-b76ee15fff1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24168
96073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2416896073
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.4266683214
Short name T242
Test name
Test status
Simulation time 220454609 ps
CPU time 0.92 seconds
Started Jul 31 05:47:07 PM PDT 24
Finished Jul 31 05:47:08 PM PDT 24
Peak memory 206992 kb
Host smart-fa495495-3668-49df-98a8-4d1518d1f8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42666
83214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4266683214
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.2638836272
Short name T2134
Test name
Test status
Simulation time 6970383457 ps
CPU time 60.5 seconds
Started Jul 31 05:47:12 PM PDT 24
Finished Jul 31 05:48:12 PM PDT 24
Peak memory 207160 kb
Host smart-5c9c48c9-fe23-484a-87a4-7fe4d9996de8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2638836272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.2638836272
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.2881694074
Short name T1862
Test name
Test status
Simulation time 6696056516 ps
CPU time 92.23 seconds
Started Jul 31 05:47:09 PM PDT 24
Finished Jul 31 05:48:41 PM PDT 24
Peak memory 207228 kb
Host smart-75019ebe-b5e2-49e1-ad2a-0e9e334e80f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2881694074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.2881694074
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2734206647
Short name T1459
Test name
Test status
Simulation time 242709139 ps
CPU time 1.01 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 206992 kb
Host smart-a01565f2-dd64-47ab-8fe5-9b0daaa75778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27342
06647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2734206647
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.1800215998
Short name T1255
Test name
Test status
Simulation time 23302624246 ps
CPU time 33.99 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:53 PM PDT 24
Peak memory 207180 kb
Host smart-1514a359-8c26-4436-b24e-59a8ee1d7a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18002
15998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.1800215998
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.4117319408
Short name T1133
Test name
Test status
Simulation time 3308360578 ps
CPU time 5.15 seconds
Started Jul 31 05:47:11 PM PDT 24
Finished Jul 31 05:47:17 PM PDT 24
Peak memory 207116 kb
Host smart-120223fc-4f56-4c66-9ef1-d1e46be61923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41173
19408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.4117319408
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.499940441
Short name T1820
Test name
Test status
Simulation time 5882255815 ps
CPU time 57.05 seconds
Started Jul 31 05:47:08 PM PDT 24
Finished Jul 31 05:48:05 PM PDT 24
Peak memory 217304 kb
Host smart-1dd89289-a463-4080-ac31-6403f298ceba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49994
0441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.499940441
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.631297390
Short name T483
Test name
Test status
Simulation time 7016622814 ps
CPU time 204.35 seconds
Started Jul 31 05:47:06 PM PDT 24
Finished Jul 31 05:50:31 PM PDT 24
Peak memory 215408 kb
Host smart-7b2dac8d-0815-4206-8fe3-02bcd164e9dc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=631297390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.631297390
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2155001912
Short name T450
Test name
Test status
Simulation time 274866084 ps
CPU time 1 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 207000 kb
Host smart-45f6be4b-b879-4b6c-879f-7433f3d94939
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2155001912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2155001912
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.980564043
Short name T366
Test name
Test status
Simulation time 213952069 ps
CPU time 0.94 seconds
Started Jul 31 05:47:10 PM PDT 24
Finished Jul 31 05:47:11 PM PDT 24
Peak memory 206980 kb
Host smart-27f57971-8598-4f13-a1e7-2aa51ee36365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98056
4043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.980564043
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3520806309
Short name T1157
Test name
Test status
Simulation time 5649768906 ps
CPU time 174.61 seconds
Started Jul 31 05:47:12 PM PDT 24
Finished Jul 31 05:50:07 PM PDT 24
Peak memory 215344 kb
Host smart-9c21da64-0fd6-4602-88a2-c41198d72f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35208
06309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3520806309
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.3261310315
Short name T1845
Test name
Test status
Simulation time 7603434666 ps
CPU time 224.89 seconds
Started Jul 31 05:47:09 PM PDT 24
Finished Jul 31 05:50:54 PM PDT 24
Peak memory 215372 kb
Host smart-0759b510-cac5-47ff-80a4-6fc9c595937f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3261310315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.3261310315
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1096839427
Short name T2293
Test name
Test status
Simulation time 169441298 ps
CPU time 0.86 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 206992 kb
Host smart-9b1b5f33-475b-48f2-8f56-dfff6aaa46da
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1096839427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1096839427
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.4177744158
Short name T1005
Test name
Test status
Simulation time 146615171 ps
CPU time 0.85 seconds
Started Jul 31 05:47:12 PM PDT 24
Finished Jul 31 05:47:13 PM PDT 24
Peak memory 207016 kb
Host smart-53a5787c-9df6-4808-ab44-04629954962d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41777
44158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.4177744158
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.2441606741
Short name T124
Test name
Test status
Simulation time 178044619 ps
CPU time 0.91 seconds
Started Jul 31 05:47:09 PM PDT 24
Finished Jul 31 05:47:10 PM PDT 24
Peak memory 207012 kb
Host smart-b89a8365-41b2-4185-ae8b-b7fa43732269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24416
06741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2441606741
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.105389882
Short name T2528
Test name
Test status
Simulation time 160442335 ps
CPU time 0.89 seconds
Started Jul 31 05:47:12 PM PDT 24
Finished Jul 31 05:47:13 PM PDT 24
Peak memory 206996 kb
Host smart-3147c4ba-85be-4099-af24-a641a355fe2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10538
9882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.105389882
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1031443230
Short name T2716
Test name
Test status
Simulation time 173376197 ps
CPU time 0.94 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:47:22 PM PDT 24
Peak memory 206972 kb
Host smart-f599db22-1618-4914-b9c7-cdf21fc32768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10314
43230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1031443230
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.1992147247
Short name T103
Test name
Test status
Simulation time 208296845 ps
CPU time 0.92 seconds
Started Jul 31 05:47:09 PM PDT 24
Finished Jul 31 05:47:10 PM PDT 24
Peak memory 206992 kb
Host smart-4ae0ceb4-b2a3-4475-b632-f24c2f94ca2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19921
47247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.1992147247
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2983233050
Short name T2373
Test name
Test status
Simulation time 152946521 ps
CPU time 0.85 seconds
Started Jul 31 05:47:12 PM PDT 24
Finished Jul 31 05:47:13 PM PDT 24
Peak memory 206992 kb
Host smart-6c393f82-df07-4718-8b64-9004f701a878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29832
33050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2983233050
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1243919547
Short name T1332
Test name
Test status
Simulation time 245824559 ps
CPU time 1.09 seconds
Started Jul 31 05:47:09 PM PDT 24
Finished Jul 31 05:47:10 PM PDT 24
Peak memory 206964 kb
Host smart-15a328d8-dca7-41a7-a025-ce6568dac8f4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1243919547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1243919547
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.4128141380
Short name T1252
Test name
Test status
Simulation time 147123818 ps
CPU time 0.84 seconds
Started Jul 31 05:47:11 PM PDT 24
Finished Jul 31 05:47:12 PM PDT 24
Peak memory 206956 kb
Host smart-ce0fd373-8b28-4ef3-9b67-8d253dd72492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
41380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.4128141380
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.219938985
Short name T1321
Test name
Test status
Simulation time 46617160 ps
CPU time 0.77 seconds
Started Jul 31 05:47:10 PM PDT 24
Finished Jul 31 05:47:11 PM PDT 24
Peak memory 206928 kb
Host smart-1194a0db-a1d2-4e74-8289-97b982326ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21993
8985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.219938985
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3963483602
Short name T2143
Test name
Test status
Simulation time 18713671263 ps
CPU time 47.86 seconds
Started Jul 31 05:47:09 PM PDT 24
Finished Jul 31 05:47:57 PM PDT 24
Peak memory 215388 kb
Host smart-191fc2d8-6f7a-47bd-b0f0-96337fd24e46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39634
83602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3963483602
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.4267591806
Short name T1406
Test name
Test status
Simulation time 190160469 ps
CPU time 0.96 seconds
Started Jul 31 05:47:12 PM PDT 24
Finished Jul 31 05:47:13 PM PDT 24
Peak memory 206996 kb
Host smart-92fac894-4988-44b7-922b-a64b2a21cb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42675
91806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.4267591806
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3548936278
Short name T1219
Test name
Test status
Simulation time 218759679 ps
CPU time 0.95 seconds
Started Jul 31 05:47:12 PM PDT 24
Finished Jul 31 05:47:13 PM PDT 24
Peak memory 206944 kb
Host smart-0ee45fa0-d6fe-473b-a657-85839b57f24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35489
36278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3548936278
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1690499020
Short name T1796
Test name
Test status
Simulation time 246129630 ps
CPU time 1.02 seconds
Started Jul 31 05:47:13 PM PDT 24
Finished Jul 31 05:47:14 PM PDT 24
Peak memory 206984 kb
Host smart-d8677bfe-935c-42d5-b07e-50ceb661e67f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16904
99020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1690499020
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3829182951
Short name T1458
Test name
Test status
Simulation time 198617180 ps
CPU time 0.9 seconds
Started Jul 31 05:47:23 PM PDT 24
Finished Jul 31 05:47:24 PM PDT 24
Peak memory 207000 kb
Host smart-7df3900d-5c0a-46db-9958-310c807224e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38291
82951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3829182951
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2793883686
Short name T834
Test name
Test status
Simulation time 155531923 ps
CPU time 0.91 seconds
Started Jul 31 05:47:13 PM PDT 24
Finished Jul 31 05:47:14 PM PDT 24
Peak memory 207036 kb
Host smart-11ea1b9b-aa03-429e-91ec-94ba4cd03c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938
83686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2793883686
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.1772546238
Short name T1696
Test name
Test status
Simulation time 160303320 ps
CPU time 0.85 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 206940 kb
Host smart-08854261-1ce1-4061-9b22-696b851d2834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17725
46238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.1772546238
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.1960511338
Short name T2405
Test name
Test status
Simulation time 152845885 ps
CPU time 0.83 seconds
Started Jul 31 05:47:15 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 206992 kb
Host smart-11a2b782-e3cd-4fc1-a0f1-104961f7aac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19605
11338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.1960511338
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.1910510361
Short name T672
Test name
Test status
Simulation time 229708077 ps
CPU time 1.02 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:19 PM PDT 24
Peak memory 206996 kb
Host smart-72377e52-2f76-49bd-bdb4-04e1c2d34178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
10361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.1910510361
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.2969238874
Short name T2660
Test name
Test status
Simulation time 5337466161 ps
CPU time 158.52 seconds
Started Jul 31 05:47:15 PM PDT 24
Finished Jul 31 05:49:54 PM PDT 24
Peak memory 215384 kb
Host smart-9a3a85bb-e518-4299-94ce-9ccdf61bce11
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2969238874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.2969238874
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2616019835
Short name T2169
Test name
Test status
Simulation time 163101943 ps
CPU time 0.87 seconds
Started Jul 31 05:47:14 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 207000 kb
Host smart-24cfb549-6bee-4393-9c57-a45a030237d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26160
19835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2616019835
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2906789313
Short name T642
Test name
Test status
Simulation time 172369921 ps
CPU time 0.89 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 206980 kb
Host smart-bcddde5b-ed90-48d4-afa3-e6676690d72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29067
89313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2906789313
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.286766416
Short name T1942
Test name
Test status
Simulation time 560603216 ps
CPU time 1.67 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 206940 kb
Host smart-05212f5f-1d1f-4e4b-9b2b-4c794164cc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28676
6416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.286766416
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.3968980363
Short name T1833
Test name
Test status
Simulation time 7398336339 ps
CPU time 204.63 seconds
Started Jul 31 05:47:22 PM PDT 24
Finished Jul 31 05:50:46 PM PDT 24
Peak memory 215412 kb
Host smart-fcb1ca3e-50f5-4529-8d89-1f57f33f6441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39689
80363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3968980363
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.3605053300
Short name T654
Test name
Test status
Simulation time 2003689579 ps
CPU time 17.5 seconds
Started Jul 31 05:47:01 PM PDT 24
Finished Jul 31 05:47:19 PM PDT 24
Peak memory 207112 kb
Host smart-114cc2cb-fd07-45e7-b0d2-afbf0b2b94ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605053300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.3605053300
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.2395972308
Short name T1859
Test name
Test status
Simulation time 53666207 ps
CPU time 0.69 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 207020 kb
Host smart-8d554977-2f4b-4022-a627-eda492027346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2395972308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.2395972308
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.2399867479
Short name T244
Test name
Test status
Simulation time 3682519616 ps
CPU time 5.65 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:23 PM PDT 24
Peak memory 207160 kb
Host smart-77377d83-2a7b-43e8-a396-a74b999cd02f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399867479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.2399867479
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1984095210
Short name T1645
Test name
Test status
Simulation time 13535454584 ps
CPU time 17.15 seconds
Started Jul 31 05:47:16 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 207236 kb
Host smart-11f6d84a-4c8d-4b7e-92c3-a9e39495a116
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984095210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1984095210
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1021019045
Short name T1380
Test name
Test status
Simulation time 23386059053 ps
CPU time 30.87 seconds
Started Jul 31 05:47:23 PM PDT 24
Finished Jul 31 05:47:54 PM PDT 24
Peak memory 207192 kb
Host smart-76fee3f6-83e5-49a8-8b2a-5e7e4354d879
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021019045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.1021019045
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4052441531
Short name T2639
Test name
Test status
Simulation time 158440587 ps
CPU time 0.88 seconds
Started Jul 31 05:47:18 PM PDT 24
Finished Jul 31 05:47:19 PM PDT 24
Peak memory 206984 kb
Host smart-50273d91-8723-48ef-a77d-72f40081dae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40524
41531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4052441531
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1088392270
Short name T1723
Test name
Test status
Simulation time 146770584 ps
CPU time 0.86 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 206952 kb
Host smart-5da7ed2a-d5dd-4b98-a0a7-38d63322cae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
92270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1088392270
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2216087110
Short name T2276
Test name
Test status
Simulation time 649920418 ps
CPU time 2.1 seconds
Started Jul 31 05:47:20 PM PDT 24
Finished Jul 31 05:47:22 PM PDT 24
Peak memory 207064 kb
Host smart-d2e703f0-bfb6-466b-81bf-3f4652ce175f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22160
87110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2216087110
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.246846599
Short name T2002
Test name
Test status
Simulation time 1281437528 ps
CPU time 3.1 seconds
Started Jul 31 05:47:14 PM PDT 24
Finished Jul 31 05:47:17 PM PDT 24
Peak memory 207048 kb
Host smart-cf62cdc1-9b15-441e-ade3-6df030a68e41
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=246846599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.246846599
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.2038111933
Short name T2574
Test name
Test status
Simulation time 9190032676 ps
CPU time 21.78 seconds
Started Jul 31 05:47:16 PM PDT 24
Finished Jul 31 05:47:38 PM PDT 24
Peak memory 207176 kb
Host smart-6eaa83b0-0644-47e0-a7f0-5864aab920a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20381
11933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2038111933
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_device_timeout.1355112549
Short name T2756
Test name
Test status
Simulation time 3887975180 ps
CPU time 32.33 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:47:54 PM PDT 24
Peak memory 207224 kb
Host smart-523dd403-7fec-4bbd-bf24-da98d48c544a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355112549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.1355112549
Directory /workspace/49.usbdev_device_timeout/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.4007666937
Short name T1596
Test name
Test status
Simulation time 424402802 ps
CPU time 1.35 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 206968 kb
Host smart-c3516cdd-565c-410d-afb4-2fe9cb24844c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40076
66937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.4007666937
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2844263223
Short name T2668
Test name
Test status
Simulation time 143101301 ps
CPU time 0.8 seconds
Started Jul 31 05:47:15 PM PDT 24
Finished Jul 31 05:47:16 PM PDT 24
Peak memory 206968 kb
Host smart-fb2539c7-9060-4ac6-bfc4-5d4bbb9eb6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28442
63223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2844263223
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.103760765
Short name T2222
Test name
Test status
Simulation time 35754680 ps
CPU time 0.71 seconds
Started Jul 31 05:47:14 PM PDT 24
Finished Jul 31 05:47:14 PM PDT 24
Peak memory 206960 kb
Host smart-1ea35c02-7748-4610-9f53-8466e7d12a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10376
0765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.103760765
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.1963296855
Short name T1271
Test name
Test status
Simulation time 824946302 ps
CPU time 2.22 seconds
Started Jul 31 05:47:23 PM PDT 24
Finished Jul 31 05:47:25 PM PDT 24
Peak memory 207072 kb
Host smart-c3614f37-fcf2-4386-bea6-461380d0bd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19632
96855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.1963296855
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.787809970
Short name T1262
Test name
Test status
Simulation time 282608997 ps
CPU time 1.46 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 207072 kb
Host smart-1ff5df42-525f-4c5d-a43d-d96a855ee991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78780
9970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.787809970
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1392807299
Short name T1524
Test name
Test status
Simulation time 160124087 ps
CPU time 0.89 seconds
Started Jul 31 05:47:15 PM PDT 24
Finished Jul 31 05:47:16 PM PDT 24
Peak memory 206984 kb
Host smart-acda678f-fd2a-45a0-b2f6-c97b786dfdde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1392807299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1392807299
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3920300557
Short name T2371
Test name
Test status
Simulation time 130699088 ps
CPU time 0.89 seconds
Started Jul 31 05:47:13 PM PDT 24
Finished Jul 31 05:47:14 PM PDT 24
Peak memory 207016 kb
Host smart-2a05ff9b-6b61-438b-821f-3f0e660f9fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39203
00557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3920300557
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.2552838636
Short name T1853
Test name
Test status
Simulation time 237256953 ps
CPU time 1.08 seconds
Started Jul 31 05:47:20 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 206992 kb
Host smart-8c4eb14d-3da6-4ebe-9832-80fe27538aa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25528
38636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2552838636
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.2712459989
Short name T2339
Test name
Test status
Simulation time 5466765993 ps
CPU time 41.62 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:58 PM PDT 24
Peak memory 216968 kb
Host smart-bcc5884c-3b3f-473e-8243-dafcece7878c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2712459989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.2712459989
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.2028575360
Short name T1273
Test name
Test status
Simulation time 8726472957 ps
CPU time 121.92 seconds
Started Jul 31 05:47:16 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 207160 kb
Host smart-91468f27-66db-4096-ba1e-9e86a46b0783
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2028575360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.2028575360
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1491867199
Short name T1912
Test name
Test status
Simulation time 237062264 ps
CPU time 0.98 seconds
Started Jul 31 05:47:23 PM PDT 24
Finished Jul 31 05:47:24 PM PDT 24
Peak memory 206952 kb
Host smart-0fc48537-76e6-48df-8188-dbfdc54b2715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14918
67199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1491867199
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.4173342024
Short name T1979
Test name
Test status
Simulation time 23339721155 ps
CPU time 28.14 seconds
Started Jul 31 05:47:15 PM PDT 24
Finished Jul 31 05:47:43 PM PDT 24
Peak memory 207220 kb
Host smart-c05187e9-6d78-4e57-ae04-dec08b7df864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41733
42024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.4173342024
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.1524738264
Short name T2182
Test name
Test status
Simulation time 3280701975 ps
CPU time 4.72 seconds
Started Jul 31 05:47:16 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 207152 kb
Host smart-b2632ba8-566e-447a-b5fb-5cee86033e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15247
38264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1524738264
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.3782716113
Short name T1068
Test name
Test status
Simulation time 5868352869 ps
CPU time 57.37 seconds
Started Jul 31 05:47:23 PM PDT 24
Finished Jul 31 05:48:21 PM PDT 24
Peak memory 223552 kb
Host smart-96794293-7525-4ea1-8e8d-cfd9b099a11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37827
16113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3782716113
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.223239915
Short name T1852
Test name
Test status
Simulation time 4483266349 ps
CPU time 131.06 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:49:33 PM PDT 24
Peak memory 215388 kb
Host smart-9286a24f-07dc-45b2-a34d-8892d8cb0c5b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=223239915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.223239915
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1923790587
Short name T2246
Test name
Test status
Simulation time 280977965 ps
CPU time 1.1 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 207028 kb
Host smart-b0c92f6d-1126-4a4a-b4d5-9643c07500cd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1923790587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1923790587
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2148456344
Short name T2417
Test name
Test status
Simulation time 239041443 ps
CPU time 0.97 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:47:22 PM PDT 24
Peak memory 206984 kb
Host smart-e3a97944-13de-483c-870b-3802ba285d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21484
56344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2148456344
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.1389714381
Short name T1772
Test name
Test status
Simulation time 4233433775 ps
CPU time 124.55 seconds
Started Jul 31 05:47:14 PM PDT 24
Finished Jul 31 05:49:18 PM PDT 24
Peak memory 215372 kb
Host smart-cac810b0-06d0-4263-bd52-a4c1f7505528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13897
14381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.1389714381
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.500430176
Short name T350
Test name
Test status
Simulation time 4603670351 ps
CPU time 49.11 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 216956 kb
Host smart-f5d66bea-7033-4635-a860-29a4f7692912
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=500430176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.500430176
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.504159959
Short name T2224
Test name
Test status
Simulation time 156083744 ps
CPU time 0.86 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:47:22 PM PDT 24
Peak memory 207004 kb
Host smart-92f43d48-c577-4bd5-80cf-76403e5407e7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=504159959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.504159959
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.537897588
Short name T1783
Test name
Test status
Simulation time 175665287 ps
CPU time 0.88 seconds
Started Jul 31 05:47:18 PM PDT 24
Finished Jul 31 05:47:19 PM PDT 24
Peak memory 207000 kb
Host smart-cbb70943-eacb-4e4b-a1d3-2d955fe51728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53789
7588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.537897588
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1953396765
Short name T128
Test name
Test status
Simulation time 223836982 ps
CPU time 0.97 seconds
Started Jul 31 05:47:24 PM PDT 24
Finished Jul 31 05:47:25 PM PDT 24
Peak memory 207008 kb
Host smart-b8676f7d-b07d-4769-8cbc-7075c13582cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19533
96765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1953396765
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.4282384022
Short name T553
Test name
Test status
Simulation time 185431273 ps
CPU time 0.86 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 206980 kb
Host smart-67918333-50ec-41fb-ba68-cef1b0266b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42823
84022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.4282384022
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2132309533
Short name T1924
Test name
Test status
Simulation time 244920214 ps
CPU time 1.05 seconds
Started Jul 31 05:47:20 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 207056 kb
Host smart-f33447df-9c04-4f25-884b-108ed52aee40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21323
09533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2132309533
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.815886296
Short name T1836
Test name
Test status
Simulation time 149486183 ps
CPU time 0.83 seconds
Started Jul 31 05:47:14 PM PDT 24
Finished Jul 31 05:47:15 PM PDT 24
Peak memory 207000 kb
Host smart-3de5decb-3892-442f-a9a7-91c7cb506c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81588
6296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.815886296
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3905933002
Short name T453
Test name
Test status
Simulation time 232413907 ps
CPU time 1.01 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:18 PM PDT 24
Peak memory 207000 kb
Host smart-b45fb4ae-a83d-40c1-826f-037981562b92
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3905933002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3905933002
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.4174486325
Short name T2526
Test name
Test status
Simulation time 167278191 ps
CPU time 0.86 seconds
Started Jul 31 05:47:15 PM PDT 24
Finished Jul 31 05:47:16 PM PDT 24
Peak memory 207000 kb
Host smart-f4dcce42-4c5e-4db5-8dcb-9ecb24234b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41744
86325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.4174486325
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3515201610
Short name T2686
Test name
Test status
Simulation time 65986324 ps
CPU time 0.75 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 206968 kb
Host smart-7eae4e1b-08fa-4990-8c01-b386b582f773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35152
01610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3515201610
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.549130923
Short name T2337
Test name
Test status
Simulation time 21980474181 ps
CPU time 56.09 seconds
Started Jul 31 05:47:15 PM PDT 24
Finished Jul 31 05:48:11 PM PDT 24
Peak memory 215404 kb
Host smart-2bc3564d-0b68-4dde-8924-8a5c687996f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54913
0923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.549130923
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3526785288
Short name T1568
Test name
Test status
Simulation time 222469300 ps
CPU time 0.96 seconds
Started Jul 31 05:47:22 PM PDT 24
Finished Jul 31 05:47:23 PM PDT 24
Peak memory 206992 kb
Host smart-31b46f0b-79b5-4d1b-8006-ed040306da68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35267
85288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3526785288
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.992043987
Short name T606
Test name
Test status
Simulation time 235433442 ps
CPU time 1 seconds
Started Jul 31 05:47:20 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 206968 kb
Host smart-674e563d-0f65-4af5-bc12-2548cba39293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99204
3987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.992043987
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.2592682806
Short name T2564
Test name
Test status
Simulation time 216849360 ps
CPU time 0.89 seconds
Started Jul 31 05:47:20 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 206992 kb
Host smart-31b8b725-6551-4024-a7cb-0c96facf93d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25926
82806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.2592682806
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.1564196619
Short name T2754
Test name
Test status
Simulation time 197371223 ps
CPU time 0.91 seconds
Started Jul 31 05:47:21 PM PDT 24
Finished Jul 31 05:47:22 PM PDT 24
Peak memory 206628 kb
Host smart-582e3d6a-6c22-43fd-ae31-651c186e389a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15641
96619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1564196619
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3643192298
Short name T1305
Test name
Test status
Simulation time 169553565 ps
CPU time 0.85 seconds
Started Jul 31 05:47:24 PM PDT 24
Finished Jul 31 05:47:25 PM PDT 24
Peak memory 206988 kb
Host smart-cda66eea-e9f2-4c67-a7dd-a5fcb5eefa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36431
92298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3643192298
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.63681494
Short name T984
Test name
Test status
Simulation time 142703604 ps
CPU time 0.83 seconds
Started Jul 31 05:47:20 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 206980 kb
Host smart-ee43db87-8a83-4f6c-9a04-968fc5ceb876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63681
494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.63681494
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.586172369
Short name T2335
Test name
Test status
Simulation time 150680839 ps
CPU time 0.88 seconds
Started Jul 31 05:47:16 PM PDT 24
Finished Jul 31 05:47:17 PM PDT 24
Peak memory 206920 kb
Host smart-5d2721e3-51b1-44f2-b7f1-55c821454d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58617
2369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.586172369
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3382834277
Short name T727
Test name
Test status
Simulation time 222762094 ps
CPU time 0.91 seconds
Started Jul 31 05:47:18 PM PDT 24
Finished Jul 31 05:47:19 PM PDT 24
Peak memory 206808 kb
Host smart-35b93694-042b-4333-809d-4177ea749d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33828
34277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3382834277
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.650594137
Short name T337
Test name
Test status
Simulation time 5942102687 ps
CPU time 48.76 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:48:07 PM PDT 24
Peak memory 216592 kb
Host smart-8979067b-5c9c-44d4-b4a5-d027d6627fbc
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=650594137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.650594137
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3884595886
Short name T1646
Test name
Test status
Simulation time 178345053 ps
CPU time 0.84 seconds
Started Jul 31 05:47:20 PM PDT 24
Finished Jul 31 05:47:21 PM PDT 24
Peak memory 206980 kb
Host smart-a084b870-c3cd-4681-8031-1341e04da4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38845
95886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3884595886
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.4129010343
Short name T2494
Test name
Test status
Simulation time 227098381 ps
CPU time 0.93 seconds
Started Jul 31 05:47:19 PM PDT 24
Finished Jul 31 05:47:20 PM PDT 24
Peak memory 207000 kb
Host smart-f7fe2571-9882-4ec6-86e7-12f9df242a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41290
10343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.4129010343
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.331988179
Short name T1014
Test name
Test status
Simulation time 432093642 ps
CPU time 1.34 seconds
Started Jul 31 05:47:26 PM PDT 24
Finished Jul 31 05:47:28 PM PDT 24
Peak memory 206992 kb
Host smart-8bf91d3d-5fd2-488d-b919-15ddd9853c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198
8179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.331988179
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1348351524
Short name T1460
Test name
Test status
Simulation time 4545544658 ps
CPU time 35.67 seconds
Started Jul 31 05:47:18 PM PDT 24
Finished Jul 31 05:47:54 PM PDT 24
Peak memory 207200 kb
Host smart-acfc8735-1736-4032-b87b-7dd94ef1f61d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13483
51524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1348351524
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.1248036414
Short name T2087
Test name
Test status
Simulation time 2911644046 ps
CPU time 27.82 seconds
Started Jul 31 05:47:17 PM PDT 24
Finished Jul 31 05:47:45 PM PDT 24
Peak memory 207212 kb
Host smart-a7085ea4-fc5b-498e-a14a-2b33fb0065f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248036414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.1248036414
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.1974685872
Short name T1056
Test name
Test status
Simulation time 40842715 ps
CPU time 0.68 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:40:26 PM PDT 24
Peak memory 207036 kb
Host smart-de0d20b1-3648-492a-8668-117c4a741706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1974685872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.1974685872
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.3245266412
Short name T1408
Test name
Test status
Simulation time 4278348681 ps
CPU time 6.03 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:20 PM PDT 24
Peak memory 207140 kb
Host smart-a9eb77c2-ce17-4f6a-ae17-a5c3b587c177
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245266412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.3245266412
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.1102487905
Short name T1407
Test name
Test status
Simulation time 13365505799 ps
CPU time 15.23 seconds
Started Jul 31 05:40:21 PM PDT 24
Finished Jul 31 05:40:37 PM PDT 24
Peak memory 207232 kb
Host smart-20da6faa-8a3b-48ad-a120-eff17f9323fd
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102487905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.1102487905
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3500774500
Short name T2658
Test name
Test status
Simulation time 23450761840 ps
CPU time 27.98 seconds
Started Jul 31 05:40:12 PM PDT 24
Finished Jul 31 05:40:40 PM PDT 24
Peak memory 207188 kb
Host smart-33a4dd32-e91e-47ff-ad3e-f9df991e707f
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500774500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.3500774500
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1611259355
Short name T448
Test name
Test status
Simulation time 188005987 ps
CPU time 1.01 seconds
Started Jul 31 05:40:13 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 207000 kb
Host smart-af5a9662-1ef0-440a-b216-8f777b2aaf3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16112
59355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1611259355
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3151323484
Short name T1631
Test name
Test status
Simulation time 149798427 ps
CPU time 0.86 seconds
Started Jul 31 05:40:17 PM PDT 24
Finished Jul 31 05:40:18 PM PDT 24
Peak memory 206960 kb
Host smart-1518e9f4-154b-4625-a263-eff259529801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31513
23484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3151323484
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3694829438
Short name T2565
Test name
Test status
Simulation time 304047222 ps
CPU time 1.19 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 206996 kb
Host smart-b20049bd-ab05-4cf8-b85c-b17deefa4a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
29438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3694829438
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2950241147
Short name T1761
Test name
Test status
Simulation time 774185181 ps
CPU time 2.18 seconds
Started Jul 31 05:40:13 PM PDT 24
Finished Jul 31 05:40:16 PM PDT 24
Peak memory 207100 kb
Host smart-ee70c011-1358-4f67-b14d-be739aaf2f1c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2950241147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2950241147
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1606773251
Short name T1935
Test name
Test status
Simulation time 22255387873 ps
CPU time 48.5 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:41:02 PM PDT 24
Peak memory 207172 kb
Host smart-962c0cd3-ab89-4dcf-888f-3c2381f1f7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16067
73251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1606773251
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_device_timeout.443439990
Short name T2866
Test name
Test status
Simulation time 224263267 ps
CPU time 0.92 seconds
Started Jul 31 05:40:14 PM PDT 24
Finished Jul 31 05:40:15 PM PDT 24
Peak memory 206708 kb
Host smart-19e3b670-293a-4a30-a822-7215026a12e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443439990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.443439990
Directory /workspace/5.usbdev_device_timeout/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1914157029
Short name T637
Test name
Test status
Simulation time 396800849 ps
CPU time 1.54 seconds
Started Jul 31 05:40:17 PM PDT 24
Finished Jul 31 05:40:19 PM PDT 24
Peak memory 206976 kb
Host smart-3d8829d4-7e51-47a3-bae4-f4b92dbc82b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19141
57029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1914157029
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1155901901
Short name T2040
Test name
Test status
Simulation time 166457679 ps
CPU time 0.83 seconds
Started Jul 31 05:40:17 PM PDT 24
Finished Jul 31 05:40:18 PM PDT 24
Peak memory 206948 kb
Host smart-6c763271-ed38-4abb-909c-e187374e40f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11559
01901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1155901901
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1237810734
Short name T423
Test name
Test status
Simulation time 40940090 ps
CPU time 0.71 seconds
Started Jul 31 05:40:18 PM PDT 24
Finished Jul 31 05:40:19 PM PDT 24
Peak memory 206944 kb
Host smart-2bdcbf28-f920-4583-864f-36d0b57cb472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12378
10734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1237810734
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.2704584213
Short name T1964
Test name
Test status
Simulation time 949249123 ps
CPU time 2.77 seconds
Started Jul 31 05:40:22 PM PDT 24
Finished Jul 31 05:40:25 PM PDT 24
Peak memory 207048 kb
Host smart-119a4db2-0f16-4efa-960b-7a25b198b52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27045
84213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.2704584213
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1823311611
Short name T463
Test name
Test status
Simulation time 168850963 ps
CPU time 1.74 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:40:28 PM PDT 24
Peak memory 207040 kb
Host smart-3d346fab-09cd-40f5-bafd-082fa04fe29e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18233
11611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1823311611
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.2294623520
Short name T1139
Test name
Test status
Simulation time 195574739 ps
CPU time 1.12 seconds
Started Jul 31 05:40:20 PM PDT 24
Finished Jul 31 05:40:21 PM PDT 24
Peak memory 207056 kb
Host smart-ae953bb1-6bab-4cab-8998-87ce5cf17894
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2294623520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.2294623520
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2881533177
Short name T2163
Test name
Test status
Simulation time 141973121 ps
CPU time 0.85 seconds
Started Jul 31 05:40:18 PM PDT 24
Finished Jul 31 05:40:18 PM PDT 24
Peak memory 206952 kb
Host smart-0f7df88a-1362-4004-93b0-b5a4ad759fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28815
33177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2881533177
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3752461138
Short name T1053
Test name
Test status
Simulation time 228111278 ps
CPU time 1.04 seconds
Started Jul 31 05:40:19 PM PDT 24
Finished Jul 31 05:40:21 PM PDT 24
Peak memory 206964 kb
Host smart-3ede5b2c-ed12-46c8-b226-ab61942299b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37524
61138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3752461138
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.3530373195
Short name T1864
Test name
Test status
Simulation time 7514173080 ps
CPU time 59.75 seconds
Started Jul 31 05:40:17 PM PDT 24
Finished Jul 31 05:41:17 PM PDT 24
Peak memory 216776 kb
Host smart-f944d5e7-90f0-433b-a13d-cd1b65b84325
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3530373195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3530373195
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.594580848
Short name T707
Test name
Test status
Simulation time 12583456452 ps
CPU time 79.93 seconds
Started Jul 31 05:40:17 PM PDT 24
Finished Jul 31 05:41:37 PM PDT 24
Peak memory 207156 kb
Host smart-6c3bfa91-b742-4557-bfd4-0a9de303c825
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=594580848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.594580848
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.2379152791
Short name T1267
Test name
Test status
Simulation time 200947538 ps
CPU time 1 seconds
Started Jul 31 05:40:17 PM PDT 24
Finished Jul 31 05:40:18 PM PDT 24
Peak memory 206996 kb
Host smart-3a1ef651-9fb7-4224-9c01-87ebdb61dd3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
52791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.2379152791
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.3208499253
Short name T791
Test name
Test status
Simulation time 23264459384 ps
CPU time 32.08 seconds
Started Jul 31 05:40:21 PM PDT 24
Finished Jul 31 05:40:53 PM PDT 24
Peak memory 207168 kb
Host smart-afa2ea47-5d93-4f1a-8cf1-b6860a0be149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32084
99253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.3208499253
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1266526964
Short name T1202
Test name
Test status
Simulation time 3355356092 ps
CPU time 5.46 seconds
Started Jul 31 05:40:17 PM PDT 24
Finished Jul 31 05:40:23 PM PDT 24
Peak memory 207156 kb
Host smart-a9cb445f-18d9-4de4-bf38-0ad52ea86dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12665
26964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1266526964
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1783477000
Short name T2376
Test name
Test status
Simulation time 9178341012 ps
CPU time 265.8 seconds
Started Jul 31 05:40:19 PM PDT 24
Finished Jul 31 05:44:45 PM PDT 24
Peak memory 215404 kb
Host smart-b99b40f9-0062-4c9a-ae4a-21dd4656254a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17834
77000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1783477000
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2753477629
Short name T926
Test name
Test status
Simulation time 4485721997 ps
CPU time 132.94 seconds
Started Jul 31 05:40:19 PM PDT 24
Finished Jul 31 05:42:32 PM PDT 24
Peak memory 215372 kb
Host smart-7ad6c69e-e05c-453c-bbab-e1ee5436c843
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2753477629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2753477629
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2805080587
Short name T2710
Test name
Test status
Simulation time 238956845 ps
CPU time 1.04 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:40:27 PM PDT 24
Peak memory 207020 kb
Host smart-28b64e3d-af2b-4cbf-94ff-ac9444e6fb52
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2805080587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2805080587
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.2929236920
Short name T1625
Test name
Test status
Simulation time 268789968 ps
CPU time 1.02 seconds
Started Jul 31 05:40:19 PM PDT 24
Finished Jul 31 05:40:20 PM PDT 24
Peak memory 206976 kb
Host smart-e824532f-cf77-47bd-a1ad-9252617bdd58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292
36920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2929236920
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1391412577
Short name T1709
Test name
Test status
Simulation time 4973971881 ps
CPU time 47.98 seconds
Started Jul 31 05:40:20 PM PDT 24
Finished Jul 31 05:41:08 PM PDT 24
Peak memory 216668 kb
Host smart-c55ea817-5661-4461-97f7-0697ebc0c297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13914
12577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1391412577
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.29951131
Short name T2248
Test name
Test status
Simulation time 4265748548 ps
CPU time 126.37 seconds
Started Jul 31 05:40:20 PM PDT 24
Finished Jul 31 05:42:27 PM PDT 24
Peak memory 223244 kb
Host smart-cf13a8b0-b9f5-4788-885c-1c9450950742
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=29951131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.29951131
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2942056543
Short name T2213
Test name
Test status
Simulation time 161889283 ps
CPU time 0.88 seconds
Started Jul 31 05:40:20 PM PDT 24
Finished Jul 31 05:40:21 PM PDT 24
Peak memory 206992 kb
Host smart-553fce61-0efb-4f75-aa21-96fc789f4399
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2942056543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2942056543
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.466164573
Short name T2159
Test name
Test status
Simulation time 158151845 ps
CPU time 0.86 seconds
Started Jul 31 05:40:18 PM PDT 24
Finished Jul 31 05:40:19 PM PDT 24
Peak memory 207032 kb
Host smart-fd5f4bf3-6f50-4da4-8e61-6fbd0a9c814c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46616
4573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.466164573
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3676417657
Short name T112
Test name
Test status
Simulation time 227722912 ps
CPU time 0.96 seconds
Started Jul 31 05:40:21 PM PDT 24
Finished Jul 31 05:40:22 PM PDT 24
Peak memory 206992 kb
Host smart-6da26934-59f2-4b9c-b866-6796f74d33ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36764
17657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3676417657
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1807059093
Short name T760
Test name
Test status
Simulation time 188193045 ps
CPU time 0.97 seconds
Started Jul 31 05:40:23 PM PDT 24
Finished Jul 31 05:40:24 PM PDT 24
Peak memory 206992 kb
Host smart-51bbbfba-b36b-427f-98b1-34379354fa37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18070
59093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1807059093
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.744153395
Short name T2069
Test name
Test status
Simulation time 224616697 ps
CPU time 0.98 seconds
Started Jul 31 05:40:22 PM PDT 24
Finished Jul 31 05:40:23 PM PDT 24
Peak memory 206972 kb
Host smart-6f26bd0e-89cf-4328-9ce2-642ffcf2fbc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74415
3395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.744153395
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3567970419
Short name T2352
Test name
Test status
Simulation time 168262728 ps
CPU time 0.96 seconds
Started Jul 31 05:40:23 PM PDT 24
Finished Jul 31 05:40:24 PM PDT 24
Peak memory 206964 kb
Host smart-7e2dfab3-b3ad-4307-aba9-9458083614ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35679
70419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3567970419
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3903279376
Short name T2752
Test name
Test status
Simulation time 158529242 ps
CPU time 0.85 seconds
Started Jul 31 05:40:18 PM PDT 24
Finished Jul 31 05:40:19 PM PDT 24
Peak memory 206996 kb
Host smart-bccfb1ba-ef58-4e71-9229-3f114803d9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39032
79376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3903279376
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.841943103
Short name T2000
Test name
Test status
Simulation time 266186625 ps
CPU time 1.03 seconds
Started Jul 31 05:40:21 PM PDT 24
Finished Jul 31 05:40:22 PM PDT 24
Peak memory 206976 kb
Host smart-fa3a8ea1-a585-464a-a170-7b57b8d8d1b9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=841943103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.841943103
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.306154954
Short name T2743
Test name
Test status
Simulation time 197012948 ps
CPU time 0.93 seconds
Started Jul 31 05:40:20 PM PDT 24
Finished Jul 31 05:40:21 PM PDT 24
Peak memory 206956 kb
Host smart-4c58cef9-0643-4a5b-a14b-ebb4ccaa9577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30615
4954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.306154954
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4116687019
Short name T2053
Test name
Test status
Simulation time 18560689401 ps
CPU time 45.06 seconds
Started Jul 31 05:40:20 PM PDT 24
Finished Jul 31 05:41:05 PM PDT 24
Peak memory 223572 kb
Host smart-4737bbc5-66b9-4232-8cf5-c95442649f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41166
87019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4116687019
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2005824323
Short name T870
Test name
Test status
Simulation time 200600254 ps
CPU time 0.92 seconds
Started Jul 31 05:40:18 PM PDT 24
Finished Jul 31 05:40:19 PM PDT 24
Peak memory 206976 kb
Host smart-28b8a082-7d6e-4514-816c-2e4fd2bbdf13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20058
24323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2005824323
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1816650772
Short name T1448
Test name
Test status
Simulation time 232199367 ps
CPU time 0.94 seconds
Started Jul 31 05:40:20 PM PDT 24
Finished Jul 31 05:40:21 PM PDT 24
Peak memory 206956 kb
Host smart-25a0a207-1ac1-4526-9613-00ae80cf16f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18166
50772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1816650772
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2552373147
Short name T1880
Test name
Test status
Simulation time 13699541691 ps
CPU time 279.07 seconds
Started Jul 31 05:40:27 PM PDT 24
Finished Jul 31 05:45:06 PM PDT 24
Peak memory 215432 kb
Host smart-4a20f1a1-b8b5-4f38-a14b-2cc954550284
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552373147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2552373147
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.913643812
Short name T157
Test name
Test status
Simulation time 10487591349 ps
CPU time 71.23 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:41:38 PM PDT 24
Peak memory 223496 kb
Host smart-5335e3a0-ecac-4f8a-8836-963348e08bc0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=913643812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.913643812
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.1539043263
Short name T2831
Test name
Test status
Simulation time 12015211760 ps
CPU time 101.16 seconds
Started Jul 31 05:40:27 PM PDT 24
Finished Jul 31 05:42:08 PM PDT 24
Peak memory 217044 kb
Host smart-34d9747d-ff09-40cb-86b4-e2ea1b5643b7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539043263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.1539043263
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.98855881
Short name T2123
Test name
Test status
Simulation time 226591098 ps
CPU time 1.07 seconds
Started Jul 31 05:40:24 PM PDT 24
Finished Jul 31 05:40:25 PM PDT 24
Peak memory 207012 kb
Host smart-777c8c70-6399-4d10-be0f-64192f973bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98855
881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.98855881
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.735260313
Short name T1302
Test name
Test status
Simulation time 223774947 ps
CPU time 0.94 seconds
Started Jul 31 05:40:28 PM PDT 24
Finished Jul 31 05:40:29 PM PDT 24
Peak memory 206992 kb
Host smart-c5277867-d794-418c-aca5-2ee6eaa9c6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73526
0313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.735260313
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1299534869
Short name T2488
Test name
Test status
Simulation time 157562981 ps
CPU time 0.81 seconds
Started Jul 31 05:40:24 PM PDT 24
Finished Jul 31 05:40:25 PM PDT 24
Peak memory 206940 kb
Host smart-b1cb2678-a281-4dcc-ae51-1ad457539428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12995
34869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1299534869
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.3439839668
Short name T386
Test name
Test status
Simulation time 149709708 ps
CPU time 0.84 seconds
Started Jul 31 05:40:28 PM PDT 24
Finished Jul 31 05:40:29 PM PDT 24
Peak memory 206948 kb
Host smart-bc934625-a90c-43b3-a8e2-635516a0c7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34398
39668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3439839668
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1670142560
Short name T2265
Test name
Test status
Simulation time 162795757 ps
CPU time 0.89 seconds
Started Jul 31 05:40:24 PM PDT 24
Finished Jul 31 05:40:25 PM PDT 24
Peak memory 206976 kb
Host smart-3ecab5df-6a63-40f8-995a-300d679ed2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16701
42560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1670142560
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2650819834
Short name T987
Test name
Test status
Simulation time 223990536 ps
CPU time 1.03 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:40:27 PM PDT 24
Peak memory 206964 kb
Host smart-1ae765b1-c171-4ce2-bf74-0818c62df26d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26508
19834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2650819834
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.3856472072
Short name T1298
Test name
Test status
Simulation time 3374188294 ps
CPU time 96.66 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:42:03 PM PDT 24
Peak memory 215356 kb
Host smart-628750fc-e11c-4612-90d2-be88570410d6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3856472072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.3856472072
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2324289331
Short name T712
Test name
Test status
Simulation time 191621937 ps
CPU time 0.9 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:40:27 PM PDT 24
Peak memory 206984 kb
Host smart-16721780-9e99-4735-8ef6-294d6c293800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23242
89331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2324289331
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.3835049795
Short name T2402
Test name
Test status
Simulation time 218933146 ps
CPU time 0.9 seconds
Started Jul 31 05:40:25 PM PDT 24
Finished Jul 31 05:40:26 PM PDT 24
Peak memory 206968 kb
Host smart-eec5c8ed-0895-4cd0-8a52-eee21174f2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38350
49795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.3835049795
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2094692848
Short name T440
Test name
Test status
Simulation time 1059947884 ps
CPU time 2.48 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:40:29 PM PDT 24
Peak memory 207088 kb
Host smart-d819e6e1-c53f-4e26-b146-64511a8987e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946
92848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2094692848
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.2237531102
Short name T1109
Test name
Test status
Simulation time 4131268235 ps
CPU time 123.27 seconds
Started Jul 31 05:40:27 PM PDT 24
Finished Jul 31 05:42:31 PM PDT 24
Peak memory 215440 kb
Host smart-e7379136-9855-474f-88bd-087871d99133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22375
31102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.2237531102
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.3629012688
Short name T1983
Test name
Test status
Simulation time 4368844582 ps
CPU time 29.48 seconds
Started Jul 31 05:40:21 PM PDT 24
Finished Jul 31 05:40:51 PM PDT 24
Peak memory 207224 kb
Host smart-aa20e2e7-093d-491f-99c1-3d946a9442d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629012688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host
_handshake.3629012688
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.776040616
Short name T1355
Test name
Test status
Simulation time 34676970 ps
CPU time 0.7 seconds
Started Jul 31 05:40:40 PM PDT 24
Finished Jul 31 05:40:41 PM PDT 24
Peak memory 207036 kb
Host smart-5847a88e-d46c-4ffb-aa14-403f7d888e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=776040616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.776040616
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.1028210451
Short name T647
Test name
Test status
Simulation time 4200314002 ps
CPU time 5.91 seconds
Started Jul 31 05:40:23 PM PDT 24
Finished Jul 31 05:40:29 PM PDT 24
Peak memory 207132 kb
Host smart-b67b0d09-7728-47d8-b78b-10e582fee474
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028210451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_disconnect.1028210451
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.154183910
Short name T1807
Test name
Test status
Simulation time 13438409466 ps
CPU time 15.83 seconds
Started Jul 31 05:40:25 PM PDT 24
Finished Jul 31 05:40:41 PM PDT 24
Peak memory 207212 kb
Host smart-11a923ae-8bb3-4991-b207-193ac5a27c7d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=154183910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.154183910
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1018728468
Short name T1340
Test name
Test status
Simulation time 23401897938 ps
CPU time 31.34 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:40:58 PM PDT 24
Peak memory 207192 kb
Host smart-b8ce330a-d3f0-40a6-8e95-42ae28d29b3e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018728468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.1018728468
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.625130432
Short name T1821
Test name
Test status
Simulation time 187468820 ps
CPU time 0.93 seconds
Started Jul 31 05:40:25 PM PDT 24
Finished Jul 31 05:40:26 PM PDT 24
Peak memory 206992 kb
Host smart-71b1c767-4ab0-432c-9492-4daa95c0cf04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62513
0432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.625130432
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1052907655
Short name T1272
Test name
Test status
Simulation time 170756705 ps
CPU time 0.85 seconds
Started Jul 31 05:40:28 PM PDT 24
Finished Jul 31 05:40:29 PM PDT 24
Peak memory 206960 kb
Host smart-cc189235-b927-45b2-a5ca-37ec5c22e265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10529
07655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1052907655
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.1602484160
Short name T2074
Test name
Test status
Simulation time 163762784 ps
CPU time 0.88 seconds
Started Jul 31 05:40:24 PM PDT 24
Finished Jul 31 05:40:25 PM PDT 24
Peak memory 206980 kb
Host smart-c092bd82-d827-459c-b1bb-c87b6414e573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16024
84160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.1602484160
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2684027985
Short name T1452
Test name
Test status
Simulation time 882958909 ps
CPU time 2.48 seconds
Started Jul 31 05:40:26 PM PDT 24
Finished Jul 31 05:40:28 PM PDT 24
Peak memory 207144 kb
Host smart-634d586d-52f2-4c2f-b591-f08ffa9c60be
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2684027985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2684027985
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3316702069
Short name T1988
Test name
Test status
Simulation time 9488430315 ps
CPU time 25.01 seconds
Started Jul 31 05:40:28 PM PDT 24
Finished Jul 31 05:40:54 PM PDT 24
Peak memory 207196 kb
Host smart-1cd6a80d-ed64-4866-9e42-819e82cfeae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33167
02069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3316702069
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_device_timeout.1483877710
Short name T2468
Test name
Test status
Simulation time 2040863933 ps
CPU time 17.87 seconds
Started Jul 31 05:40:24 PM PDT 24
Finished Jul 31 05:40:42 PM PDT 24
Peak memory 207048 kb
Host smart-4ba141a9-9a56-46a6-b443-241b8dac8fee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483877710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.1483877710
Directory /workspace/6.usbdev_device_timeout/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.577543204
Short name T1786
Test name
Test status
Simulation time 435087614 ps
CPU time 1.49 seconds
Started Jul 31 05:40:24 PM PDT 24
Finished Jul 31 05:40:26 PM PDT 24
Peak memory 206964 kb
Host smart-6cefb11b-9947-4f86-aabd-5a606ff4ebe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57754
3204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.577543204
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3006075974
Short name T1693
Test name
Test status
Simulation time 141071283 ps
CPU time 0.84 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:33 PM PDT 24
Peak memory 206960 kb
Host smart-2fe22ce9-eab6-48a0-b038-9b601c9ab3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30060
75974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3006075974
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.1231503811
Short name T658
Test name
Test status
Simulation time 92867841 ps
CPU time 0.79 seconds
Started Jul 31 05:40:33 PM PDT 24
Finished Jul 31 05:40:34 PM PDT 24
Peak memory 206976 kb
Host smart-efe63c4a-0b86-46ae-956f-b4d19da7dc37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12315
03811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.1231503811
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.3574920259
Short name T2329
Test name
Test status
Simulation time 999626808 ps
CPU time 2.64 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:35 PM PDT 24
Peak memory 207148 kb
Host smart-e0fa4131-0652-47f4-899f-d65fca27b4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35749
20259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3574920259
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3914209385
Short name T2363
Test name
Test status
Simulation time 161722253 ps
CPU time 1.33 seconds
Started Jul 31 05:40:33 PM PDT 24
Finished Jul 31 05:40:35 PM PDT 24
Peak memory 207076 kb
Host smart-fe3ce09d-ad12-4e99-a9ce-33e373ced9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39142
09385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3914209385
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.2832223992
Short name T2198
Test name
Test status
Simulation time 235772731 ps
CPU time 1.19 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:33 PM PDT 24
Peak memory 215292 kb
Host smart-a38dc10b-b030-4460-87a6-88ccf0275c05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2832223992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2832223992
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.1208564961
Short name T2429
Test name
Test status
Simulation time 145209197 ps
CPU time 0.86 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:33 PM PDT 24
Peak memory 206936 kb
Host smart-26e71736-3ec1-45d2-bda9-4b1c929e75f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
64961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.1208564961
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.1706984941
Short name T584
Test name
Test status
Simulation time 243119679 ps
CPU time 1.02 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:34 PM PDT 24
Peak memory 207020 kb
Host smart-c9cbee80-c06b-4597-a5ca-47425e0034e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17069
84941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.1706984941
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.2537205759
Short name T1791
Test name
Test status
Simulation time 5854791342 ps
CPU time 46.04 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:41:18 PM PDT 24
Peak memory 215440 kb
Host smart-88a6d9f6-1179-4277-b23e-f56163e4a179
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2537205759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.2537205759
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.1020246055
Short name T2798
Test name
Test status
Simulation time 13449041770 ps
CPU time 89.13 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:42:01 PM PDT 24
Peak memory 207144 kb
Host smart-f1a3d0f5-6bc0-4781-a2da-5ad46773cf00
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1020246055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.1020246055
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.4251621099
Short name T418
Test name
Test status
Simulation time 177862522 ps
CPU time 0.9 seconds
Started Jul 31 05:40:33 PM PDT 24
Finished Jul 31 05:40:34 PM PDT 24
Peak memory 206972 kb
Host smart-b957e210-2a50-4d25-aa96-d73d1a4143e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42516
21099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.4251621099
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.3627760414
Short name T706
Test name
Test status
Simulation time 23271157437 ps
CPU time 31.07 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:41:03 PM PDT 24
Peak memory 207144 kb
Host smart-791a351f-7193-43d5-ba0e-1591635889be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36277
60414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.3627760414
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.2336057777
Short name T383
Test name
Test status
Simulation time 3357233900 ps
CPU time 4.78 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:37 PM PDT 24
Peak memory 207128 kb
Host smart-9c6a0733-9249-4c21-bad6-2dcea666651d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23360
57777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.2336057777
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.1962447216
Short name T1563
Test name
Test status
Simulation time 7984653509 ps
CPU time 216.78 seconds
Started Jul 31 05:40:30 PM PDT 24
Finished Jul 31 05:44:07 PM PDT 24
Peak memory 215352 kb
Host smart-b42f22ee-02e3-409a-abde-c41cef52e615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19624
47216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1962447216
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.2606859326
Short name T1413
Test name
Test status
Simulation time 4072872209 ps
CPU time 29.02 seconds
Started Jul 31 05:40:29 PM PDT 24
Finished Jul 31 05:40:58 PM PDT 24
Peak memory 207260 kb
Host smart-c0000bd5-60e1-496b-98da-f9cebd1e4a8b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2606859326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2606859326
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.2109811938
Short name T678
Test name
Test status
Simulation time 244405455 ps
CPU time 1.11 seconds
Started Jul 31 05:40:30 PM PDT 24
Finished Jul 31 05:40:31 PM PDT 24
Peak memory 207032 kb
Host smart-46a8d999-4481-49d8-8582-2c85380ebdfd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2109811938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.2109811938
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.4234243663
Short name T2175
Test name
Test status
Simulation time 230686737 ps
CPU time 0.98 seconds
Started Jul 31 05:40:31 PM PDT 24
Finished Jul 31 05:40:32 PM PDT 24
Peak memory 206940 kb
Host smart-e9f4e24a-724f-4b87-933c-b6646becf4df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42342
43663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.4234243663
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.1313270035
Short name T724
Test name
Test status
Simulation time 6118164107 ps
CPU time 170.37 seconds
Started Jul 31 05:40:34 PM PDT 24
Finished Jul 31 05:43:25 PM PDT 24
Peak memory 215384 kb
Host smart-a5f2e0c5-34c9-458a-b073-0fc22250673e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13132
70035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.1313270035
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.624669742
Short name T1635
Test name
Test status
Simulation time 4786236014 ps
CPU time 53.72 seconds
Started Jul 31 05:40:29 PM PDT 24
Finished Jul 31 05:41:23 PM PDT 24
Peak memory 207232 kb
Host smart-b874a356-d914-492b-8027-4fa235ebfaa2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=624669742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.624669742
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.4061104531
Short name T582
Test name
Test status
Simulation time 160222984 ps
CPU time 0.88 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:33 PM PDT 24
Peak memory 206992 kb
Host smart-c106baef-5890-4d66-8c02-9a4e6460c050
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4061104531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.4061104531
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.4164983081
Short name T705
Test name
Test status
Simulation time 148841407 ps
CPU time 0.84 seconds
Started Jul 31 05:40:31 PM PDT 24
Finished Jul 31 05:40:32 PM PDT 24
Peak memory 206976 kb
Host smart-df53cae6-e4a9-4223-bb9d-8246e47bdc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41649
83081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.4164983081
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3146237475
Short name T119
Test name
Test status
Simulation time 193248332 ps
CPU time 0.98 seconds
Started Jul 31 05:40:31 PM PDT 24
Finished Jul 31 05:40:32 PM PDT 24
Peak memory 206956 kb
Host smart-978c2664-ea6d-42d7-9cef-a79c7deb6595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31462
37475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3146237475
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2407304763
Short name T1548
Test name
Test status
Simulation time 167090180 ps
CPU time 0.93 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:34 PM PDT 24
Peak memory 206984 kb
Host smart-8aea7889-5091-44ee-8c7f-9d22391e9d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
04763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2407304763
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.397422550
Short name T520
Test name
Test status
Simulation time 163029788 ps
CPU time 0.86 seconds
Started Jul 31 05:40:31 PM PDT 24
Finished Jul 31 05:40:32 PM PDT 24
Peak memory 206996 kb
Host smart-4ad83d31-f5eb-40c0-bad8-96df344b8f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39742
2550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.397422550
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.411897914
Short name T1184
Test name
Test status
Simulation time 180954724 ps
CPU time 0.89 seconds
Started Jul 31 05:40:30 PM PDT 24
Finished Jul 31 05:40:30 PM PDT 24
Peak memory 207032 kb
Host smart-4967131b-185d-4b53-8495-ff6f1306fb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41189
7914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.411897914
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.828096468
Short name T167
Test name
Test status
Simulation time 155804635 ps
CPU time 0.88 seconds
Started Jul 31 05:40:31 PM PDT 24
Finished Jul 31 05:40:32 PM PDT 24
Peak memory 206980 kb
Host smart-954786d5-27c8-4a7e-9520-78ec1d1c42f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82809
6468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.828096468
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.554948163
Short name T838
Test name
Test status
Simulation time 222046240 ps
CPU time 0.99 seconds
Started Jul 31 05:40:29 PM PDT 24
Finished Jul 31 05:40:30 PM PDT 24
Peak memory 207016 kb
Host smart-76145127-ff04-4517-95ba-baf76ce14baf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=554948163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.554948163
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.1714250462
Short name T908
Test name
Test status
Simulation time 163902207 ps
CPU time 0.85 seconds
Started Jul 31 05:40:34 PM PDT 24
Finished Jul 31 05:40:35 PM PDT 24
Peak memory 206944 kb
Host smart-92ea5063-1c10-4dfa-9ae9-0397b2acaac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17142
50462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.1714250462
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.4272548570
Short name T2656
Test name
Test status
Simulation time 39419269 ps
CPU time 0.7 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:33 PM PDT 24
Peak memory 206916 kb
Host smart-15e3387e-868d-477c-9f1f-6a8930be9d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42725
48570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.4272548570
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.2035897013
Short name T271
Test name
Test status
Simulation time 19964648531 ps
CPU time 48.35 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:41:20 PM PDT 24
Peak memory 215476 kb
Host smart-d97790ed-5740-4057-acd1-bb9ad56a1c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20358
97013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.2035897013
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.903931032
Short name T713
Test name
Test status
Simulation time 175173248 ps
CPU time 0.89 seconds
Started Jul 31 05:40:32 PM PDT 24
Finished Jul 31 05:40:33 PM PDT 24
Peak memory 206972 kb
Host smart-fd9f9f62-02e8-4d8f-be84-cc607d8d7bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90393
1032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.903931032
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.4043665954
Short name T370
Test name
Test status
Simulation time 231578292 ps
CPU time 1.03 seconds
Started Jul 31 05:40:40 PM PDT 24
Finished Jul 31 05:40:41 PM PDT 24
Peak memory 206972 kb
Host smart-13df8d9b-6db7-4c56-baf1-e94e6019f328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436
65954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.4043665954
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.653924563
Short name T155
Test name
Test status
Simulation time 11197132461 ps
CPU time 82.13 seconds
Started Jul 31 05:40:36 PM PDT 24
Finished Jul 31 05:41:58 PM PDT 24
Peak memory 218200 kb
Host smart-bc9494b3-4a36-44f4-9b38-5e16d4f86622
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=653924563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.653924563
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.1526839535
Short name T1906
Test name
Test status
Simulation time 13299637831 ps
CPU time 111.42 seconds
Started Jul 31 05:40:38 PM PDT 24
Finished Jul 31 05:42:30 PM PDT 24
Peak memory 223580 kb
Host smart-ad2a3b91-54dd-4a53-bb61-291329a54cdb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1526839535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.1526839535
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.225568607
Short name T1705
Test name
Test status
Simulation time 24028800361 ps
CPU time 206.7 seconds
Started Jul 31 05:40:39 PM PDT 24
Finished Jul 31 05:44:05 PM PDT 24
Peak memory 223484 kb
Host smart-a57ff773-7393-4b1c-bbb6-2f9c9520191a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=225568607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.225568607
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.3099943895
Short name T2622
Test name
Test status
Simulation time 256285685 ps
CPU time 1.06 seconds
Started Jul 31 05:40:37 PM PDT 24
Finished Jul 31 05:40:38 PM PDT 24
Peak memory 207000 kb
Host smart-3d5abaa2-9db3-4dd2-9f0d-66f68aa92c24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30999
43895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.3099943895
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1864848898
Short name T364
Test name
Test status
Simulation time 166278256 ps
CPU time 0.92 seconds
Started Jul 31 05:40:40 PM PDT 24
Finished Jul 31 05:40:41 PM PDT 24
Peak memory 206544 kb
Host smart-fd1d9ef7-a54b-4fe3-9da0-6c86f30fb571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648
48898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1864848898
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.2407650193
Short name T1046
Test name
Test status
Simulation time 214458486 ps
CPU time 0.89 seconds
Started Jul 31 05:40:38 PM PDT 24
Finished Jul 31 05:40:39 PM PDT 24
Peak memory 206968 kb
Host smart-ecef9ab1-33a9-405f-bd2e-4ad0ce03b4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24076
50193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.2407650193
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1983551160
Short name T1985
Test name
Test status
Simulation time 163858915 ps
CPU time 0.86 seconds
Started Jul 31 05:40:37 PM PDT 24
Finished Jul 31 05:40:38 PM PDT 24
Peak memory 206944 kb
Host smart-1f1f4614-373e-4cd9-af93-e25eb1104d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19835
51160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1983551160
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.2497123421
Short name T2602
Test name
Test status
Simulation time 160147572 ps
CPU time 0.89 seconds
Started Jul 31 05:40:39 PM PDT 24
Finished Jul 31 05:40:40 PM PDT 24
Peak memory 206968 kb
Host smart-5cd2fad9-d4b8-4676-81c8-7c315c97993d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24971
23421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.2497123421
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1473953433
Short name T2020
Test name
Test status
Simulation time 231676582 ps
CPU time 1.05 seconds
Started Jul 31 05:40:37 PM PDT 24
Finished Jul 31 05:40:38 PM PDT 24
Peak memory 206980 kb
Host smart-96147206-310d-4408-976c-f83a1ee918ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
53433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1473953433
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2649605333
Short name T2810
Test name
Test status
Simulation time 5904838641 ps
CPU time 165.05 seconds
Started Jul 31 05:40:37 PM PDT 24
Finished Jul 31 05:43:22 PM PDT 24
Peak memory 215364 kb
Host smart-3d28db06-9738-4c24-b1e0-342af6ff1488
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2649605333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2649605333
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.447477721
Short name T1974
Test name
Test status
Simulation time 176179583 ps
CPU time 0.87 seconds
Started Jul 31 05:40:39 PM PDT 24
Finished Jul 31 05:40:40 PM PDT 24
Peak memory 206944 kb
Host smart-fb01d302-ef44-4c90-9e9e-ac3f21c84d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44747
7721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.447477721
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.2782639055
Short name T2292
Test name
Test status
Simulation time 157316056 ps
CPU time 0.88 seconds
Started Jul 31 05:40:39 PM PDT 24
Finished Jul 31 05:40:40 PM PDT 24
Peak memory 206992 kb
Host smart-4cc011b9-d7ae-43f8-aab7-6c9860fbd615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27826
39055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.2782639055
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.2095878140
Short name T433
Test name
Test status
Simulation time 1101949035 ps
CPU time 2.84 seconds
Started Jul 31 05:40:39 PM PDT 24
Finished Jul 31 05:40:42 PM PDT 24
Peak memory 207092 kb
Host smart-290ccace-a88a-4555-b6d8-e2f1311f3513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20958
78140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.2095878140
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.1159358066
Short name T1346
Test name
Test status
Simulation time 5571730539 ps
CPU time 57.04 seconds
Started Jul 31 05:40:35 PM PDT 24
Finished Jul 31 05:41:32 PM PDT 24
Peak memory 207216 kb
Host smart-37033eaa-4254-4c13-906d-0355062c19cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11593
58066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.1159358066
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.1326945331
Short name T1039
Test name
Test status
Simulation time 2582363460 ps
CPU time 17.74 seconds
Started Jul 31 05:40:24 PM PDT 24
Finished Jul 31 05:40:41 PM PDT 24
Peak memory 207248 kb
Host smart-c57114dd-967f-455c-b040-8e7213a4b58f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326945331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.1326945331
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.4248838675
Short name T829
Test name
Test status
Simulation time 44653327 ps
CPU time 0.65 seconds
Started Jul 31 05:40:55 PM PDT 24
Finished Jul 31 05:40:56 PM PDT 24
Peak memory 207028 kb
Host smart-e4c56e55-ec90-4ef8-a7b6-54f5cf68cbda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4248838675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.4248838675
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3384670601
Short name T2643
Test name
Test status
Simulation time 3831678223 ps
CPU time 5.77 seconds
Started Jul 31 05:40:36 PM PDT 24
Finished Jul 31 05:40:42 PM PDT 24
Peak memory 207140 kb
Host smart-9b590975-8dfa-482f-b19b-a1964004a01b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384670601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.3384670601
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3653135247
Short name T1785
Test name
Test status
Simulation time 13352432749 ps
CPU time 19.52 seconds
Started Jul 31 05:40:40 PM PDT 24
Finished Jul 31 05:41:00 PM PDT 24
Peak memory 207224 kb
Host smart-a326f794-aee0-4e16-9d08-61d6b098cb07
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653135247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3653135247
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.548344573
Short name T1211
Test name
Test status
Simulation time 23400659297 ps
CPU time 28.2 seconds
Started Jul 31 05:40:40 PM PDT 24
Finished Jul 31 05:41:08 PM PDT 24
Peak memory 207204 kb
Host smart-8eb4fbcf-5a1b-4b01-8a2b-b2830098c90b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548344573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon
_wake_resume.548344573
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3084119461
Short name T2090
Test name
Test status
Simulation time 164260491 ps
CPU time 0.91 seconds
Started Jul 31 05:40:37 PM PDT 24
Finished Jul 31 05:40:38 PM PDT 24
Peak memory 206992 kb
Host smart-4212c638-3624-4c38-b2f3-1deb610b3c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30841
19461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3084119461
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.781831342
Short name T1085
Test name
Test status
Simulation time 217548934 ps
CPU time 0.92 seconds
Started Jul 31 05:40:39 PM PDT 24
Finished Jul 31 05:40:40 PM PDT 24
Peak memory 206964 kb
Host smart-10865213-92af-4a79-b72a-b0a8160ecf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78183
1342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.781831342
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.59717805
Short name T2273
Test name
Test status
Simulation time 187709257 ps
CPU time 0.99 seconds
Started Jul 31 05:40:38 PM PDT 24
Finished Jul 31 05:40:39 PM PDT 24
Peak memory 206980 kb
Host smart-637e13f0-0b60-4e87-8f87-3de47df2941a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59717
805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.59717805
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3495532767
Short name T2028
Test name
Test status
Simulation time 732829813 ps
CPU time 1.95 seconds
Started Jul 31 05:40:36 PM PDT 24
Finished Jul 31 05:40:38 PM PDT 24
Peak memory 207004 kb
Host smart-1c3a647f-cc7b-4ba0-b131-abec54b33085
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3495532767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3495532767
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2374193820
Short name T2047
Test name
Test status
Simulation time 7142803599 ps
CPU time 15.87 seconds
Started Jul 31 05:40:39 PM PDT 24
Finished Jul 31 05:40:55 PM PDT 24
Peak memory 207156 kb
Host smart-d5ecf3dc-fe59-432c-96cf-e0c627823624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23741
93820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2374193820
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_device_timeout.447156456
Short name T1738
Test name
Test status
Simulation time 1097700710 ps
CPU time 9.27 seconds
Started Jul 31 05:40:46 PM PDT 24
Finished Jul 31 05:40:55 PM PDT 24
Peak memory 207128 kb
Host smart-cee2b150-96ce-4ce5-9ca4-4a9b3668a092
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447156456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.447156456
Directory /workspace/7.usbdev_device_timeout/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.702827770
Short name T1669
Test name
Test status
Simulation time 424620319 ps
CPU time 1.53 seconds
Started Jul 31 05:40:42 PM PDT 24
Finished Jul 31 05:40:44 PM PDT 24
Peak memory 207020 kb
Host smart-264f715f-fa71-4ef7-ad00-3e204111b788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70282
7770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.702827770
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2948768627
Short name T1336
Test name
Test status
Simulation time 149319641 ps
CPU time 0.81 seconds
Started Jul 31 05:40:43 PM PDT 24
Finished Jul 31 05:40:43 PM PDT 24
Peak memory 206940 kb
Host smart-f9791ca0-50f5-4954-9529-f4c1a4c9c9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29487
68627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2948768627
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2720124994
Short name T1769
Test name
Test status
Simulation time 53981111 ps
CPU time 0.77 seconds
Started Jul 31 05:40:45 PM PDT 24
Finished Jul 31 05:40:46 PM PDT 24
Peak memory 206992 kb
Host smart-46c4e23f-8514-4c16-aa31-aab8b4d602e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27201
24994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2720124994
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1690543094
Short name T2844
Test name
Test status
Simulation time 954938795 ps
CPU time 2.47 seconds
Started Jul 31 05:40:44 PM PDT 24
Finished Jul 31 05:40:46 PM PDT 24
Peak memory 206772 kb
Host smart-0304e5aa-5cf1-496a-ad65-5321b55e86af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16905
43094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1690543094
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1935769639
Short name T2350
Test name
Test status
Simulation time 182714642 ps
CPU time 2.32 seconds
Started Jul 31 05:40:42 PM PDT 24
Finished Jul 31 05:40:44 PM PDT 24
Peak memory 207108 kb
Host smart-d322e279-126b-4045-ab52-d42062bdefe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19357
69639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1935769639
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.1348816248
Short name T778
Test name
Test status
Simulation time 257595712 ps
CPU time 1.15 seconds
Started Jul 31 05:40:42 PM PDT 24
Finished Jul 31 05:40:44 PM PDT 24
Peak memory 215296 kb
Host smart-4b0de4cc-73b9-478e-98b5-e9040c88669e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1348816248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.1348816248
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1477818577
Short name T2404
Test name
Test status
Simulation time 157171925 ps
CPU time 0.84 seconds
Started Jul 31 05:40:45 PM PDT 24
Finished Jul 31 05:40:46 PM PDT 24
Peak memory 206992 kb
Host smart-a9721ddd-cfa1-45be-ba6e-9faf5225cf84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14778
18577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1477818577
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.1532310988
Short name T480
Test name
Test status
Simulation time 201205408 ps
CPU time 0.9 seconds
Started Jul 31 05:40:43 PM PDT 24
Finished Jul 31 05:40:44 PM PDT 24
Peak memory 206976 kb
Host smart-5ad82139-2fd0-4ac9-b5b0-e2c342918c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15323
10988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.1532310988
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.544390278
Short name T660
Test name
Test status
Simulation time 8173727689 ps
CPU time 82.12 seconds
Started Jul 31 05:40:41 PM PDT 24
Finished Jul 31 05:42:03 PM PDT 24
Peak memory 216784 kb
Host smart-37331050-1ad5-42f0-a5ec-044e56ae7aa2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=544390278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.544390278
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.2995863242
Short name T498
Test name
Test status
Simulation time 6627217105 ps
CPU time 76.32 seconds
Started Jul 31 05:40:43 PM PDT 24
Finished Jul 31 05:41:59 PM PDT 24
Peak memory 207148 kb
Host smart-efdf0116-d04d-434b-abca-b3b735362e8c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2995863242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2995863242
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2641574893
Short name T1161
Test name
Test status
Simulation time 191744817 ps
CPU time 1.02 seconds
Started Jul 31 05:40:44 PM PDT 24
Finished Jul 31 05:40:45 PM PDT 24
Peak memory 207008 kb
Host smart-4e02a8fd-832f-4b95-9011-1995444e297b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26415
74893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2641574893
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2903130915
Short name T2825
Test name
Test status
Simulation time 23297582388 ps
CPU time 27.49 seconds
Started Jul 31 05:40:44 PM PDT 24
Finished Jul 31 05:41:11 PM PDT 24
Peak memory 206904 kb
Host smart-5c3f10e7-a2af-473e-95ff-2065ae001590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29031
30915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2903130915
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.413554857
Short name T541
Test name
Test status
Simulation time 3310552732 ps
CPU time 5.47 seconds
Started Jul 31 05:40:43 PM PDT 24
Finished Jul 31 05:40:49 PM PDT 24
Peak memory 207140 kb
Host smart-97f4fb97-2cf3-403e-ac85-773862ce6f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41355
4857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.413554857
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.202573424
Short name T319
Test name
Test status
Simulation time 7778025337 ps
CPU time 235.43 seconds
Started Jul 31 05:40:44 PM PDT 24
Finished Jul 31 05:44:40 PM PDT 24
Peak memory 215440 kb
Host smart-9d11927f-aecf-4d53-8c9a-23e7b7bfcc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20257
3424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.202573424
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.767735195
Short name T2183
Test name
Test status
Simulation time 2926074656 ps
CPU time 91.74 seconds
Started Jul 31 05:40:41 PM PDT 24
Finished Jul 31 05:42:13 PM PDT 24
Peak memory 215384 kb
Host smart-c499b636-e6a6-418f-a786-96b8c80c018d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=767735195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.767735195
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.1338823642
Short name T1293
Test name
Test status
Simulation time 238324611 ps
CPU time 0.94 seconds
Started Jul 31 05:40:41 PM PDT 24
Finished Jul 31 05:40:42 PM PDT 24
Peak memory 207000 kb
Host smart-e52916d0-61b3-4d25-97ed-7499a9d68e12
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1338823642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.1338823642
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3719473329
Short name T761
Test name
Test status
Simulation time 203852258 ps
CPU time 0.95 seconds
Started Jul 31 05:40:44 PM PDT 24
Finished Jul 31 05:40:45 PM PDT 24
Peak memory 206984 kb
Host smart-1ccd2832-29c6-4a55-b88a-be71a597c2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
73329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3719473329
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.3952741796
Short name T2462
Test name
Test status
Simulation time 4619063006 ps
CPU time 36.09 seconds
Started Jul 31 05:40:40 PM PDT 24
Finished Jul 31 05:41:17 PM PDT 24
Peak memory 215432 kb
Host smart-c895405b-b850-4b02-9843-544497fb1e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39527
41796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.3952741796
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1558934646
Short name T694
Test name
Test status
Simulation time 6449469912 ps
CPU time 51.32 seconds
Started Jul 31 05:40:44 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 207228 kb
Host smart-cdf81113-f9c7-4b0c-bf74-4e764ae3ddc8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1558934646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1558934646
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.18645884
Short name T536
Test name
Test status
Simulation time 152567237 ps
CPU time 0.87 seconds
Started Jul 31 05:40:42 PM PDT 24
Finished Jul 31 05:40:43 PM PDT 24
Peak memory 207036 kb
Host smart-da263094-b9a2-44c1-b8b3-96df9c53d8c3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=18645884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.18645884
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3178670639
Short name T847
Test name
Test status
Simulation time 159054553 ps
CPU time 0.91 seconds
Started Jul 31 05:40:42 PM PDT 24
Finished Jul 31 05:40:43 PM PDT 24
Peak memory 207032 kb
Host smart-e2a8ef78-cf6c-4cf5-8653-376e4963ab52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31786
70639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3178670639
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2251590411
Short name T947
Test name
Test status
Simulation time 233665451 ps
CPU time 0.93 seconds
Started Jul 31 05:40:45 PM PDT 24
Finished Jul 31 05:40:46 PM PDT 24
Peak memory 206980 kb
Host smart-bbf71b3f-2366-4d1a-86c2-ed18eb4b7fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22515
90411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2251590411
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.2250087095
Short name T102
Test name
Test status
Simulation time 167228078 ps
CPU time 0.84 seconds
Started Jul 31 05:40:47 PM PDT 24
Finished Jul 31 05:40:48 PM PDT 24
Peak memory 206968 kb
Host smart-e64cdc58-45e2-4ab0-915f-2946214946ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22500
87095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.2250087095
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2519363300
Short name T1299
Test name
Test status
Simulation time 247868576 ps
CPU time 1.03 seconds
Started Jul 31 05:40:47 PM PDT 24
Finished Jul 31 05:40:48 PM PDT 24
Peak memory 206988 kb
Host smart-90498295-8188-4328-9c3e-838e0ded1420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25193
63300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2519363300
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.58738419
Short name T1953
Test name
Test status
Simulation time 184908405 ps
CPU time 0.9 seconds
Started Jul 31 05:40:50 PM PDT 24
Finished Jul 31 05:40:51 PM PDT 24
Peak memory 206960 kb
Host smart-a13b7ee5-93ea-43bf-99e7-8aae28e60148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58738
419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.58738419
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2163844005
Short name T532
Test name
Test status
Simulation time 151860027 ps
CPU time 0.81 seconds
Started Jul 31 05:40:48 PM PDT 24
Finished Jul 31 05:40:49 PM PDT 24
Peak memory 206984 kb
Host smart-d10f151e-92fc-4813-a19a-9a422d2cec65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21638
44005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2163844005
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2146270148
Short name T2267
Test name
Test status
Simulation time 268048927 ps
CPU time 1.09 seconds
Started Jul 31 05:40:45 PM PDT 24
Finished Jul 31 05:40:46 PM PDT 24
Peak memory 206964 kb
Host smart-aec14236-1077-4ca2-a463-2f4333d92111
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2146270148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2146270148
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.936872786
Short name T2049
Test name
Test status
Simulation time 149144643 ps
CPU time 0.82 seconds
Started Jul 31 05:40:47 PM PDT 24
Finished Jul 31 05:40:48 PM PDT 24
Peak memory 206992 kb
Host smart-9bef0c89-0176-4e66-9e36-23c95460e0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93687
2786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.936872786
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.778033076
Short name T2585
Test name
Test status
Simulation time 77924238 ps
CPU time 0.76 seconds
Started Jul 31 05:41:01 PM PDT 24
Finished Jul 31 05:41:02 PM PDT 24
Peak memory 206924 kb
Host smart-e7575ed6-c32d-4f55-b007-9d1a8d7e4caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77803
3076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.778033076
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.564642073
Short name T1598
Test name
Test status
Simulation time 17320706598 ps
CPU time 45.88 seconds
Started Jul 31 05:40:47 PM PDT 24
Finished Jul 31 05:41:33 PM PDT 24
Peak memory 215384 kb
Host smart-94e9c0ee-3c0f-4db4-a849-c6867d467f92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56464
2073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.564642073
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1451687819
Short name T980
Test name
Test status
Simulation time 186115465 ps
CPU time 0.92 seconds
Started Jul 31 05:41:00 PM PDT 24
Finished Jul 31 05:41:01 PM PDT 24
Peak memory 206936 kb
Host smart-75e70c94-abb6-4df6-8cf6-c3a00d102565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14516
87819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1451687819
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4115812959
Short name T1627
Test name
Test status
Simulation time 194219723 ps
CPU time 0.95 seconds
Started Jul 31 05:41:00 PM PDT 24
Finished Jul 31 05:41:01 PM PDT 24
Peak memory 206936 kb
Host smart-91adbe3a-335a-4676-81ae-2728e216dfb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41158
12959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4115812959
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1103381150
Short name T153
Test name
Test status
Simulation time 13593603140 ps
CPU time 80.59 seconds
Started Jul 31 05:40:47 PM PDT 24
Finished Jul 31 05:42:07 PM PDT 24
Peak memory 223420 kb
Host smart-6022d6d5-733c-4aed-ae68-33749f2c5ea7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103381150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1103381150
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.508405784
Short name T2241
Test name
Test status
Simulation time 11477054818 ps
CPU time 219.88 seconds
Started Jul 31 05:40:49 PM PDT 24
Finished Jul 31 05:44:29 PM PDT 24
Peak memory 215456 kb
Host smart-db876b32-2e15-49d9-b902-840e1dacf187
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=508405784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.508405784
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.2190555778
Short name T645
Test name
Test status
Simulation time 233808319 ps
CPU time 1 seconds
Started Jul 31 05:41:00 PM PDT 24
Finished Jul 31 05:41:02 PM PDT 24
Peak memory 206960 kb
Host smart-01848ee4-061b-4aec-be76-0ec3fef4d391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21905
55778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.2190555778
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.21949334
Short name T1259
Test name
Test status
Simulation time 194100130 ps
CPU time 0.94 seconds
Started Jul 31 05:41:02 PM PDT 24
Finished Jul 31 05:41:03 PM PDT 24
Peak memory 206964 kb
Host smart-ddb9adb4-d302-443b-927e-146542b41c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21949
334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.21949334
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.505070314
Short name T2772
Test name
Test status
Simulation time 172494965 ps
CPU time 0.84 seconds
Started Jul 31 05:40:45 PM PDT 24
Finished Jul 31 05:40:46 PM PDT 24
Peak memory 206936 kb
Host smart-7c8fd3e2-b314-4aa9-a6e3-760b9b53d017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50507
0314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.505070314
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.4083422908
Short name T2140
Test name
Test status
Simulation time 146907212 ps
CPU time 0.87 seconds
Started Jul 31 05:41:00 PM PDT 24
Finished Jul 31 05:41:01 PM PDT 24
Peak memory 206884 kb
Host smart-3a751a9d-e825-4adc-b1d1-0e486f9f72a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40834
22908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.4083422908
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2259901670
Short name T1844
Test name
Test status
Simulation time 182872388 ps
CPU time 0.88 seconds
Started Jul 31 05:40:47 PM PDT 24
Finished Jul 31 05:40:48 PM PDT 24
Peak memory 206988 kb
Host smart-a7744c31-6ecc-4a88-9d9c-43d39f60733b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22599
01670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2259901670
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3410489600
Short name T1639
Test name
Test status
Simulation time 238585557 ps
CPU time 1.01 seconds
Started Jul 31 05:41:00 PM PDT 24
Finished Jul 31 05:41:02 PM PDT 24
Peak memory 206956 kb
Host smart-9487df57-1bc4-4ad9-aa95-20d0f42df017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34104
89600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3410489600
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1093440654
Short name T519
Test name
Test status
Simulation time 5096113524 ps
CPU time 51.7 seconds
Started Jul 31 05:40:48 PM PDT 24
Finished Jul 31 05:41:40 PM PDT 24
Peak memory 216652 kb
Host smart-f4d856ac-119b-4689-911f-d8d7f95abc44
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1093440654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1093440654
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.147790915
Short name T1585
Test name
Test status
Simulation time 191429015 ps
CPU time 0.92 seconds
Started Jul 31 05:40:45 PM PDT 24
Finished Jul 31 05:40:47 PM PDT 24
Peak memory 206996 kb
Host smart-6ebbcf3d-94ea-4480-9cf8-1bd2e116679a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14779
0915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.147790915
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.3927534808
Short name T2654
Test name
Test status
Simulation time 191824244 ps
CPU time 0.92 seconds
Started Jul 31 05:41:00 PM PDT 24
Finished Jul 31 05:41:01 PM PDT 24
Peak memory 206960 kb
Host smart-3bbd12cf-7a20-434e-a78d-7edd6deecaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39275
34808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.3927534808
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3242122963
Short name T927
Test name
Test status
Simulation time 1023984558 ps
CPU time 2.75 seconds
Started Jul 31 05:40:46 PM PDT 24
Finished Jul 31 05:40:49 PM PDT 24
Peak memory 207036 kb
Host smart-e3e4cad1-1897-4423-a51a-137f18287b8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32421
22963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3242122963
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.459516110
Short name T1543
Test name
Test status
Simulation time 5155869501 ps
CPU time 52.42 seconds
Started Jul 31 05:40:45 PM PDT 24
Finished Jul 31 05:41:38 PM PDT 24
Peak memory 216936 kb
Host smart-0918806d-a446-4d5f-b040-2dc0aea8861b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45951
6110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.459516110
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.2515490646
Short name T1479
Test name
Test status
Simulation time 617872234 ps
CPU time 4.79 seconds
Started Jul 31 05:40:42 PM PDT 24
Finished Jul 31 05:40:47 PM PDT 24
Peak memory 207092 kb
Host smart-dd5b9240-0575-4a10-92fb-8469f281ad98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515490646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host
_handshake.2515490646
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1585344541
Short name T2833
Test name
Test status
Simulation time 90314273 ps
CPU time 0.72 seconds
Started Jul 31 05:41:07 PM PDT 24
Finished Jul 31 05:41:08 PM PDT 24
Peak memory 207012 kb
Host smart-8acbb6da-422b-4a7f-a2b0-a5acd4a038f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1585344541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1585344541
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1134294220
Short name T14
Test name
Test status
Simulation time 3873164445 ps
CPU time 5.79 seconds
Started Jul 31 05:40:53 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 207144 kb
Host smart-c97ecfb9-16cb-4e12-a10c-fd41d043939c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134294220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.1134294220
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.815831483
Short name T1801
Test name
Test status
Simulation time 13321812365 ps
CPU time 15.3 seconds
Started Jul 31 05:40:54 PM PDT 24
Finished Jul 31 05:41:09 PM PDT 24
Peak memory 207228 kb
Host smart-6731e201-ae02-4f5b-8c06-f39b2435962d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=815831483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.815831483
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.3954607075
Short name T783
Test name
Test status
Simulation time 23339273568 ps
CPU time 27.19 seconds
Started Jul 31 05:40:55 PM PDT 24
Finished Jul 31 05:41:22 PM PDT 24
Peak memory 207208 kb
Host smart-8c87e6b2-4927-4e5f-9dff-ba4b6380b48b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954607075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_resume.3954607075
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1370112101
Short name T670
Test name
Test status
Simulation time 160913079 ps
CPU time 0.83 seconds
Started Jul 31 05:40:54 PM PDT 24
Finished Jul 31 05:40:55 PM PDT 24
Peak memory 207032 kb
Host smart-5d2145bc-21df-4806-a93d-3a77cfd40ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13701
12101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1370112101
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3626838571
Short name T612
Test name
Test status
Simulation time 175344025 ps
CPU time 0.87 seconds
Started Jul 31 05:40:56 PM PDT 24
Finished Jul 31 05:40:57 PM PDT 24
Peak memory 206964 kb
Host smart-c1ad2d28-11aa-48a9-9678-a2076adffbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36268
38571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3626838571
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2119679354
Short name T1539
Test name
Test status
Simulation time 587823772 ps
CPU time 1.94 seconds
Started Jul 31 05:40:53 PM PDT 24
Finished Jul 31 05:40:55 PM PDT 24
Peak memory 207028 kb
Host smart-750fd1a3-0b7d-4c87-91b1-97c082019c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21196
79354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2119679354
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.585840727
Short name T754
Test name
Test status
Simulation time 541717792 ps
CPU time 1.64 seconds
Started Jul 31 05:40:53 PM PDT 24
Finished Jul 31 05:40:54 PM PDT 24
Peak memory 206984 kb
Host smart-3c2eebcb-152f-48c3-8886-ffcbd2695aba
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=585840727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.585840727
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.3529802121
Short name T2391
Test name
Test status
Simulation time 17878771531 ps
CPU time 36.37 seconds
Started Jul 31 05:40:52 PM PDT 24
Finished Jul 31 05:41:29 PM PDT 24
Peak memory 207196 kb
Host smart-5f0fb3ca-e314-4356-9d08-f95908826992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35298
02121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.3529802121
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_device_timeout.17500402
Short name T962
Test name
Test status
Simulation time 615044786 ps
CPU time 5.21 seconds
Started Jul 31 05:40:54 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 207092 kb
Host smart-be0b69bc-e9af-4e02-81cc-6d3182b625fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17500402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.17500402
Directory /workspace/8.usbdev_device_timeout/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.4215862443
Short name T314
Test name
Test status
Simulation time 471787841 ps
CPU time 1.53 seconds
Started Jul 31 05:40:57 PM PDT 24
Finished Jul 31 05:40:58 PM PDT 24
Peak memory 206968 kb
Host smart-afd20044-c0a8-4686-baf2-df0aa3e4ba33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42158
62443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.4215862443
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.2232295319
Short name T683
Test name
Test status
Simulation time 146047129 ps
CPU time 0.83 seconds
Started Jul 31 05:40:53 PM PDT 24
Finished Jul 31 05:40:54 PM PDT 24
Peak memory 206976 kb
Host smart-1cf72e67-2310-4e7b-9614-31296111d4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22322
95319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.2232295319
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.1891015262
Short name T2027
Test name
Test status
Simulation time 113644258 ps
CPU time 0.76 seconds
Started Jul 31 05:40:53 PM PDT 24
Finished Jul 31 05:40:54 PM PDT 24
Peak memory 206960 kb
Host smart-9839333c-76ef-48c9-b0f5-74e02daf0612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18910
15262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1891015262
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1752805376
Short name T577
Test name
Test status
Simulation time 1014055046 ps
CPU time 2.77 seconds
Started Jul 31 05:41:02 PM PDT 24
Finished Jul 31 05:41:05 PM PDT 24
Peak memory 207072 kb
Host smart-4490ddf8-e1f2-420e-ab0f-72882f81007c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528
05376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1752805376
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.2331198671
Short name T747
Test name
Test status
Simulation time 269630327 ps
CPU time 2.32 seconds
Started Jul 31 05:41:03 PM PDT 24
Finished Jul 31 05:41:05 PM PDT 24
Peak memory 207008 kb
Host smart-d216c7eb-63bd-47c3-819b-27a1f5e917c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23311
98671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2331198671
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1924639711
Short name T2436
Test name
Test status
Simulation time 241611778 ps
CPU time 1.18 seconds
Started Jul 31 05:40:55 PM PDT 24
Finished Jul 31 05:40:56 PM PDT 24
Peak memory 216300 kb
Host smart-bf105b82-244c-461c-8497-6a96792d0834
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1924639711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1924639711
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2581972859
Short name T530
Test name
Test status
Simulation time 148482792 ps
CPU time 0.84 seconds
Started Jul 31 05:40:56 PM PDT 24
Finished Jul 31 05:40:57 PM PDT 24
Peak memory 206948 kb
Host smart-463375c0-4fd1-488b-91fc-73c1c793a415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25819
72859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2581972859
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.580507562
Short name T999
Test name
Test status
Simulation time 245270552 ps
CPU time 1 seconds
Started Jul 31 05:40:53 PM PDT 24
Finished Jul 31 05:40:54 PM PDT 24
Peak memory 206980 kb
Host smart-eab35321-68be-4aac-9818-4b5f2a89fd4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58050
7562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.580507562
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.3889358629
Short name T1174
Test name
Test status
Simulation time 9200326008 ps
CPU time 68.66 seconds
Started Jul 31 05:40:55 PM PDT 24
Finished Jul 31 05:42:04 PM PDT 24
Peak memory 215388 kb
Host smart-af167fb2-b778-4315-ab54-f1fa70eafd30
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3889358629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.3889358629
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.3351193269
Short name T2720
Test name
Test status
Simulation time 3511838091 ps
CPU time 25.2 seconds
Started Jul 31 05:40:54 PM PDT 24
Finished Jul 31 05:41:19 PM PDT 24
Peak memory 207208 kb
Host smart-5e9b2113-ace4-45d1-abf1-7769733889de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3351193269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.3351193269
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.3128309460
Short name T368
Test name
Test status
Simulation time 278514912 ps
CPU time 0.99 seconds
Started Jul 31 05:40:53 PM PDT 24
Finished Jul 31 05:40:54 PM PDT 24
Peak memory 207000 kb
Host smart-e3300d70-664a-4172-93b5-0471a0af96ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31283
09460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3128309460
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2093433796
Short name T863
Test name
Test status
Simulation time 23371156729 ps
CPU time 28.31 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:41:26 PM PDT 24
Peak memory 207180 kb
Host smart-a9f97a93-630d-42bf-8982-50952223f691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20934
33796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2093433796
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.24237470
Short name T1486
Test name
Test status
Simulation time 3271721013 ps
CPU time 5.52 seconds
Started Jul 31 05:41:00 PM PDT 24
Finished Jul 31 05:41:05 PM PDT 24
Peak memory 207140 kb
Host smart-6caf67ed-ca7e-4477-91ce-90f93e75150f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24237
470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.24237470
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3047348606
Short name T1065
Test name
Test status
Simulation time 9887820964 ps
CPU time 285.16 seconds
Started Jul 31 05:40:59 PM PDT 24
Finished Jul 31 05:45:44 PM PDT 24
Peak memory 215416 kb
Host smart-d92adf33-7016-4e60-a5eb-1073e5ba64b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30473
48606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3047348606
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.3757007304
Short name T1000
Test name
Test status
Simulation time 6218226526 ps
CPU time 49.49 seconds
Started Jul 31 05:41:00 PM PDT 24
Finished Jul 31 05:41:50 PM PDT 24
Peak memory 207224 kb
Host smart-abe62cf1-78cb-4bb6-8c1b-158a3eb57664
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3757007304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.3757007304
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1041831418
Short name T1580
Test name
Test status
Simulation time 259092449 ps
CPU time 1.04 seconds
Started Jul 31 05:40:55 PM PDT 24
Finished Jul 31 05:40:57 PM PDT 24
Peak memory 206968 kb
Host smart-2b3700a5-237e-4c16-8462-9564d6ed6fb7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1041831418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1041831418
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2564828303
Short name T1870
Test name
Test status
Simulation time 234453140 ps
CPU time 1 seconds
Started Jul 31 05:40:57 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 206988 kb
Host smart-65053af4-fc0c-43ac-bb45-1962bf694793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25648
28303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2564828303
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2434722695
Short name T2360
Test name
Test status
Simulation time 5242344708 ps
CPU time 50.92 seconds
Started Jul 31 05:40:57 PM PDT 24
Finished Jul 31 05:41:48 PM PDT 24
Peak memory 217020 kb
Host smart-cf888a50-4090-4e2b-8763-ecfb5a71aeea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24347
22695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2434722695
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2702784050
Short name T2856
Test name
Test status
Simulation time 4070522960 ps
CPU time 119.67 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:42:58 PM PDT 24
Peak memory 215392 kb
Host smart-24bc1d68-fb04-469d-9a90-8ecbd8dc68ea
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2702784050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2702784050
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3186859294
Short name T2323
Test name
Test status
Simulation time 154004870 ps
CPU time 0.89 seconds
Started Jul 31 05:40:57 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 207016 kb
Host smart-ecb25222-7b2d-4e02-8d96-a322f37be703
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3186859294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3186859294
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.2442428484
Short name T2308
Test name
Test status
Simulation time 153415193 ps
CPU time 0.89 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 207048 kb
Host smart-0760bc10-7d44-4af8-83ce-84c5f81c3698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24424
28484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.2442428484
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3390710276
Short name T104
Test name
Test status
Simulation time 244100216 ps
CPU time 1.01 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 206964 kb
Host smart-5641e1f6-6499-4bd0-881b-88043e7ecb86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33907
10276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3390710276
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.1505722778
Short name T897
Test name
Test status
Simulation time 190867354 ps
CPU time 0.98 seconds
Started Jul 31 05:41:02 PM PDT 24
Finished Jul 31 05:41:03 PM PDT 24
Peak memory 206988 kb
Host smart-062200a6-3cc6-4671-94f5-e8f749df57d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15057
22778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1505722778
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1275832443
Short name T531
Test name
Test status
Simulation time 204474045 ps
CPU time 0.94 seconds
Started Jul 31 05:41:01 PM PDT 24
Finished Jul 31 05:41:02 PM PDT 24
Peak memory 206996 kb
Host smart-e5984f8c-f7ef-4d5e-9649-55c960bc341f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12758
32443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1275832443
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.1576892114
Short name T949
Test name
Test status
Simulation time 171492724 ps
CPU time 0.86 seconds
Started Jul 31 05:40:59 PM PDT 24
Finished Jul 31 05:41:00 PM PDT 24
Peak memory 206988 kb
Host smart-a0a4d071-a041-4f06-8955-0fcf1882bd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15768
92114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1576892114
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1399690399
Short name T1590
Test name
Test status
Simulation time 159891912 ps
CPU time 0.88 seconds
Started Jul 31 05:40:59 PM PDT 24
Finished Jul 31 05:41:00 PM PDT 24
Peak memory 206996 kb
Host smart-8f4dbee9-525f-4362-8cf8-91d682b029e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13996
90399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1399690399
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3195083691
Short name T634
Test name
Test status
Simulation time 221660277 ps
CPU time 0.94 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 207020 kb
Host smart-5854d7be-1b68-4cfd-ae8c-996750fc4d7e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3195083691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3195083691
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3071785037
Short name T472
Test name
Test status
Simulation time 146874463 ps
CPU time 0.83 seconds
Started Jul 31 05:40:57 PM PDT 24
Finished Jul 31 05:40:58 PM PDT 24
Peak memory 206960 kb
Host smart-5bf498fe-e806-4600-955a-57b29dac6fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30717
85037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3071785037
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.3614191850
Short name T819
Test name
Test status
Simulation time 29419935 ps
CPU time 0.68 seconds
Started Jul 31 05:41:01 PM PDT 24
Finished Jul 31 05:41:02 PM PDT 24
Peak memory 206944 kb
Host smart-061be0d4-d685-47c3-b41e-4f2615ddaf66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36141
91850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3614191850
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.952349951
Short name T1697
Test name
Test status
Simulation time 22199448732 ps
CPU time 65.76 seconds
Started Jul 31 05:41:01 PM PDT 24
Finished Jul 31 05:42:07 PM PDT 24
Peak memory 215468 kb
Host smart-3382998b-f915-4d13-bb69-6fbc718cd1f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95234
9951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.952349951
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.893183586
Short name T470
Test name
Test status
Simulation time 199872921 ps
CPU time 0.95 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 206988 kb
Host smart-7339481b-c11a-4885-bc26-4080001e6a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89318
3586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.893183586
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.733672599
Short name T140
Test name
Test status
Simulation time 187486531 ps
CPU time 0.93 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 207036 kb
Host smart-0f10824e-6921-4490-96e2-919e7fe3b4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73367
2599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.733672599
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3849822330
Short name T151
Test name
Test status
Simulation time 9323744523 ps
CPU time 66.08 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:42:04 PM PDT 24
Peak memory 223560 kb
Host smart-202ca2bd-1e6e-4a1a-aff7-ad4f8f7d4064
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849822330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3849822330
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.3713000588
Short name T2119
Test name
Test status
Simulation time 9232796529 ps
CPU time 72.83 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:42:11 PM PDT 24
Peak memory 223492 kb
Host smart-b2354312-888a-4508-848d-d3dedca815de
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3713000588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3713000588
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.1179927548
Short name T1992
Test name
Test status
Simulation time 15546632748 ps
CPU time 114.82 seconds
Started Jul 31 05:40:57 PM PDT 24
Finished Jul 31 05:42:52 PM PDT 24
Peak memory 217256 kb
Host smart-ccc17374-2acc-48b9-a3f2-2e3c2b23b18c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179927548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.1179927548
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1104995029
Short name T508
Test name
Test status
Simulation time 155358998 ps
CPU time 0.81 seconds
Started Jul 31 05:40:58 PM PDT 24
Finished Jul 31 05:40:59 PM PDT 24
Peak memory 206976 kb
Host smart-d9b9fbca-5270-4c34-981e-bb72ffe10409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11049
95029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1104995029
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.4205016284
Short name T344
Test name
Test status
Simulation time 189492356 ps
CPU time 0.95 seconds
Started Jul 31 05:41:02 PM PDT 24
Finished Jul 31 05:41:03 PM PDT 24
Peak memory 206992 kb
Host smart-b0cd92e8-1216-40ec-b3e3-0e38de98871d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42050
16284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.4205016284
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.836693832
Short name T415
Test name
Test status
Simulation time 179348532 ps
CPU time 0.87 seconds
Started Jul 31 05:40:59 PM PDT 24
Finished Jul 31 05:41:00 PM PDT 24
Peak memory 207004 kb
Host smart-c3a4a582-a589-475a-a0fd-2f43e2263d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83669
3832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.836693832
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.339167564
Short name T2409
Test name
Test status
Simulation time 149865122 ps
CPU time 0.86 seconds
Started Jul 31 05:40:59 PM PDT 24
Finished Jul 31 05:41:00 PM PDT 24
Peak memory 206952 kb
Host smart-2236e795-0198-44c6-9b2d-9265721cf62a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33916
7564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.339167564
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.564614583
Short name T1749
Test name
Test status
Simulation time 180580471 ps
CPU time 0.92 seconds
Started Jul 31 05:41:02 PM PDT 24
Finished Jul 31 05:41:03 PM PDT 24
Peak memory 207000 kb
Host smart-86cda5fd-bed1-40f6-92f5-d7e9b059747a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56461
4583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.564614583
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.1343171312
Short name T2184
Test name
Test status
Simulation time 252230575 ps
CPU time 1.14 seconds
Started Jul 31 05:41:00 PM PDT 24
Finished Jul 31 05:41:01 PM PDT 24
Peak memory 206996 kb
Host smart-02222ce1-84e2-493b-937f-e3dbda7dabf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13431
71312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.1343171312
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3695575453
Short name T1692
Test name
Test status
Simulation time 5194164091 ps
CPU time 43.39 seconds
Started Jul 31 05:40:59 PM PDT 24
Finished Jul 31 05:41:43 PM PDT 24
Peak memory 216592 kb
Host smart-b988eb77-7d65-47ed-b24b-7a084028143e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3695575453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3695575453
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2088070484
Short name T1041
Test name
Test status
Simulation time 184887915 ps
CPU time 0.96 seconds
Started Jul 31 05:41:08 PM PDT 24
Finished Jul 31 05:41:09 PM PDT 24
Peak memory 207012 kb
Host smart-bca32bef-280d-4360-b0b2-38c064b347de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20880
70484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2088070484
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1774904376
Short name T2001
Test name
Test status
Simulation time 170216866 ps
CPU time 0.92 seconds
Started Jul 31 05:41:06 PM PDT 24
Finished Jul 31 05:41:07 PM PDT 24
Peak memory 206988 kb
Host smart-fa544b15-0c75-4a2a-a624-923397e5693a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17749
04376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1774904376
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2261174021
Short name T2147
Test name
Test status
Simulation time 331913989 ps
CPU time 1.23 seconds
Started Jul 31 05:41:04 PM PDT 24
Finished Jul 31 05:41:06 PM PDT 24
Peak memory 206976 kb
Host smart-5dcdfde0-7edd-4aab-8811-ba0d3f61c877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22611
74021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2261174021
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2609538517
Short name T976
Test name
Test status
Simulation time 3281147571 ps
CPU time 30.04 seconds
Started Jul 31 05:41:03 PM PDT 24
Finished Jul 31 05:41:33 PM PDT 24
Peak memory 216600 kb
Host smart-1efae1e5-baaf-4a57-8b85-c5ccdc12e220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26095
38517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2609538517
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.4027217457
Short name T2078
Test name
Test status
Simulation time 5199922649 ps
CPU time 43.76 seconds
Started Jul 31 05:40:55 PM PDT 24
Finished Jul 31 05:41:39 PM PDT 24
Peak memory 207272 kb
Host smart-8f97a5b3-bf61-4c45-b526-4eed38da664c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027217457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.4027217457
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.1361949120
Short name T2698
Test name
Test status
Simulation time 65024801 ps
CPU time 0.67 seconds
Started Jul 31 05:41:17 PM PDT 24
Finished Jul 31 05:41:18 PM PDT 24
Peak memory 207020 kb
Host smart-ae626778-788a-4975-a025-1a985fcbf6fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1361949120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1361949120
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.893742914
Short name T1550
Test name
Test status
Simulation time 3888203172 ps
CPU time 6.01 seconds
Started Jul 31 05:41:04 PM PDT 24
Finished Jul 31 05:41:10 PM PDT 24
Peak memory 207116 kb
Host smart-e598f184-a82c-4e67-acd3-03bf29f60b96
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893742914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon
_wake_disconnect.893742914
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.657176492
Short name T835
Test name
Test status
Simulation time 23437321143 ps
CPU time 26.56 seconds
Started Jul 31 05:41:08 PM PDT 24
Finished Jul 31 05:41:35 PM PDT 24
Peak memory 206836 kb
Host smart-33b18788-8397-4b8e-8c2e-e7ffa85a4777
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657176492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon
_wake_resume.657176492
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1484051506
Short name T2843
Test name
Test status
Simulation time 213260572 ps
CPU time 1 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:41:12 PM PDT 24
Peak memory 206976 kb
Host smart-ab4fdef0-b0b7-45aa-bb65-e66998ccd597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14840
51506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1484051506
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.584143413
Short name T1519
Test name
Test status
Simulation time 203400340 ps
CPU time 0.91 seconds
Started Jul 31 05:41:09 PM PDT 24
Finished Jul 31 05:41:10 PM PDT 24
Peak memory 206596 kb
Host smart-d40f2f0d-fa25-4e95-b126-5fa6b9a8cce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58414
3413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.584143413
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2594426095
Short name T1278
Test name
Test status
Simulation time 353175678 ps
CPU time 1.29 seconds
Started Jul 31 05:41:12 PM PDT 24
Finished Jul 31 05:41:13 PM PDT 24
Peak memory 206604 kb
Host smart-877eb6f1-8e40-4b7e-ba9a-eea7aca58722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25944
26095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2594426095
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.434988773
Short name T2045
Test name
Test status
Simulation time 337224881 ps
CPU time 1.2 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:41:12 PM PDT 24
Peak memory 206996 kb
Host smart-e36e3647-db2d-4f6d-84e4-88bb401248e0
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=434988773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.434988773
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1917388006
Short name T2779
Test name
Test status
Simulation time 21444195998 ps
CPU time 43.03 seconds
Started Jul 31 05:41:05 PM PDT 24
Finished Jul 31 05:41:48 PM PDT 24
Peak memory 207232 kb
Host smart-077ba940-06be-4973-be4c-1b2b938fd22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19173
88006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1917388006
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_device_timeout.2113815824
Short name T2507
Test name
Test status
Simulation time 1393146250 ps
CPU time 33.64 seconds
Started Jul 31 05:41:05 PM PDT 24
Finished Jul 31 05:41:38 PM PDT 24
Peak memory 207112 kb
Host smart-8aaa1b5b-bc15-407a-af4f-0ddc0e1d8cb7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113815824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.2113815824
Directory /workspace/9.usbdev_device_timeout/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.4045444541
Short name T723
Test name
Test status
Simulation time 487046680 ps
CPU time 1.42 seconds
Started Jul 31 05:41:05 PM PDT 24
Finished Jul 31 05:41:07 PM PDT 24
Peak memory 206964 kb
Host smart-a38c883a-b4a3-4f74-a2fd-bb900b993fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40454
44541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.4045444541
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1013747742
Short name T640
Test name
Test status
Simulation time 194962979 ps
CPU time 0.93 seconds
Started Jul 31 05:41:05 PM PDT 24
Finished Jul 31 05:41:06 PM PDT 24
Peak memory 206948 kb
Host smart-a2aae87c-7e75-4d41-beab-bd2031d00d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10137
47742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1013747742
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.3505773099
Short name T2584
Test name
Test status
Simulation time 73504105 ps
CPU time 0.73 seconds
Started Jul 31 05:41:08 PM PDT 24
Finished Jul 31 05:41:09 PM PDT 24
Peak memory 206568 kb
Host smart-b0a377c1-2c53-4c25-8832-98ee15763dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35057
73099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.3505773099
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3096216010
Short name T1339
Test name
Test status
Simulation time 928922111 ps
CPU time 2.5 seconds
Started Jul 31 05:41:04 PM PDT 24
Finished Jul 31 05:41:07 PM PDT 24
Peak memory 207120 kb
Host smart-70fc2403-5fe5-489b-b3a2-550aafb29edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30962
16010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3096216010
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.453271366
Short name T2072
Test name
Test status
Simulation time 157866655 ps
CPU time 1.65 seconds
Started Jul 31 05:41:04 PM PDT 24
Finished Jul 31 05:41:06 PM PDT 24
Peak memory 207088 kb
Host smart-59fe69c9-a00d-4820-8971-c43ed6afb410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45327
1366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.453271366
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2014981961
Short name T86
Test name
Test status
Simulation time 239272630 ps
CPU time 1.32 seconds
Started Jul 31 05:41:06 PM PDT 24
Finished Jul 31 05:41:07 PM PDT 24
Peak memory 215252 kb
Host smart-9f05e58e-03e4-4a62-bf26-1b212bef3f68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2014981961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2014981961
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.118349278
Short name T444
Test name
Test status
Simulation time 154985131 ps
CPU time 0.89 seconds
Started Jul 31 05:41:07 PM PDT 24
Finished Jul 31 05:41:08 PM PDT 24
Peak memory 206956 kb
Host smart-e9e03d2b-7027-4430-862f-0538227118d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11834
9278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.118349278
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2397059382
Short name T346
Test name
Test status
Simulation time 205258231 ps
CPU time 1.03 seconds
Started Jul 31 05:41:13 PM PDT 24
Finished Jul 31 05:41:14 PM PDT 24
Peak memory 206996 kb
Host smart-08b4c14a-b4d6-44f9-845d-7983572ebd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23970
59382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2397059382
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.904280340
Short name T2433
Test name
Test status
Simulation time 6596266390 ps
CPU time 197.4 seconds
Started Jul 31 05:41:04 PM PDT 24
Finished Jul 31 05:44:22 PM PDT 24
Peak memory 215404 kb
Host smart-b9e7e5d3-aa96-4b74-83b5-1c41d8e2d6f6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=904280340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.904280340
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.2058958218
Short name T2549
Test name
Test status
Simulation time 10710635975 ps
CPU time 126.27 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:43:17 PM PDT 24
Peak memory 207204 kb
Host smart-97edd107-efb5-4695-a850-365288b41aab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2058958218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.2058958218
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.3734065921
Short name T1025
Test name
Test status
Simulation time 232839984 ps
CPU time 0.97 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:41:12 PM PDT 24
Peak memory 207036 kb
Host smart-ec36fbf8-8908-45f2-831b-c28c6a83432a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37340
65921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3734065921
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.2802903335
Short name T2413
Test name
Test status
Simulation time 23311090598 ps
CPU time 30.67 seconds
Started Jul 31 05:41:10 PM PDT 24
Finished Jul 31 05:41:41 PM PDT 24
Peak memory 207164 kb
Host smart-0ade7dee-ef64-4c59-bb33-11ef39f66bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28029
03335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.2802903335
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.1183683330
Short name T1649
Test name
Test status
Simulation time 3302272835 ps
CPU time 5.06 seconds
Started Jul 31 05:41:09 PM PDT 24
Finished Jul 31 05:41:14 PM PDT 24
Peak memory 207120 kb
Host smart-5f444f3e-263f-4852-9659-807921aee870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11836
83330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1183683330
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3924774578
Short name T2324
Test name
Test status
Simulation time 9375436742 ps
CPU time 74.21 seconds
Started Jul 31 05:41:10 PM PDT 24
Finished Jul 31 05:42:25 PM PDT 24
Peak memory 217420 kb
Host smart-2e536b68-4d2b-4144-901a-88ba18de1f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39247
74578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3924774578
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.1165422280
Short name T2110
Test name
Test status
Simulation time 4244288133 ps
CPU time 43.59 seconds
Started Jul 31 05:41:09 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 207236 kb
Host smart-78a3a72a-4e3a-431a-914a-046cb73d4088
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1165422280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.1165422280
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3531985749
Short name T657
Test name
Test status
Simulation time 257532775 ps
CPU time 1 seconds
Started Jul 31 05:41:09 PM PDT 24
Finished Jul 31 05:41:10 PM PDT 24
Peak memory 207016 kb
Host smart-662fd8fe-dfae-40ef-962d-2f4610426f71
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3531985749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3531985749
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.20320816
Short name T2102
Test name
Test status
Simulation time 223417883 ps
CPU time 0.96 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:41:12 PM PDT 24
Peak memory 206980 kb
Host smart-b4ffebed-dc54-4583-b661-5f9335f85809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20320
816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.20320816
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.1396176994
Short name T1690
Test name
Test status
Simulation time 4206972932 ps
CPU time 34.48 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:41:45 PM PDT 24
Peak memory 216964 kb
Host smart-e9c633b0-4722-46eb-ab99-27a29d612cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13961
76994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.1396176994
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3501627491
Short name T1933
Test name
Test status
Simulation time 7509778051 ps
CPU time 56.33 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:42:08 PM PDT 24
Peak memory 207208 kb
Host smart-8b1a9c8e-3a1e-4df2-a6ce-32145f7f6802
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3501627491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3501627491
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3774358963
Short name T1198
Test name
Test status
Simulation time 207911371 ps
CPU time 0.97 seconds
Started Jul 31 05:41:10 PM PDT 24
Finished Jul 31 05:41:11 PM PDT 24
Peak memory 207004 kb
Host smart-6939b044-e709-4f70-ae40-a3ebb10c97aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3774358963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3774358963
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1419488425
Short name T1910
Test name
Test status
Simulation time 183024180 ps
CPU time 0.88 seconds
Started Jul 31 05:41:09 PM PDT 24
Finished Jul 31 05:41:10 PM PDT 24
Peak memory 206936 kb
Host smart-960a60dc-6f56-4d37-932b-d204747052fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14194
88425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1419488425
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.2711425706
Short name T2232
Test name
Test status
Simulation time 188665005 ps
CPU time 0.91 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:41:12 PM PDT 24
Peak memory 206996 kb
Host smart-1def07c7-f553-4fd0-bee1-2f84d3155c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27114
25706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.2711425706
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.3443924041
Short name T1078
Test name
Test status
Simulation time 215486928 ps
CPU time 1.03 seconds
Started Jul 31 05:41:10 PM PDT 24
Finished Jul 31 05:41:11 PM PDT 24
Peak memory 206988 kb
Host smart-d3028619-d59f-4428-9f2d-a2e1bf477974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34439
24041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.3443924041
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.551855186
Short name T2657
Test name
Test status
Simulation time 200494404 ps
CPU time 0.91 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:41:12 PM PDT 24
Peak memory 207004 kb
Host smart-49ebb972-3b71-449b-a4d2-734be8e11cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55185
5186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.551855186
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.4257609816
Short name T1516
Test name
Test status
Simulation time 155079964 ps
CPU time 0.87 seconds
Started Jul 31 05:41:07 PM PDT 24
Finished Jul 31 05:41:08 PM PDT 24
Peak memory 207000 kb
Host smart-de27379e-37b7-4a2f-9d15-e0852a98a037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42576
09816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.4257609816
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1132565771
Short name T1098
Test name
Test status
Simulation time 174419750 ps
CPU time 0.89 seconds
Started Jul 31 05:41:13 PM PDT 24
Finished Jul 31 05:41:14 PM PDT 24
Peak memory 206988 kb
Host smart-e30a967b-c418-4424-8083-5ce32de5fb8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11325
65771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1132565771
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.486147764
Short name T1002
Test name
Test status
Simulation time 218289238 ps
CPU time 1.08 seconds
Started Jul 31 05:41:10 PM PDT 24
Finished Jul 31 05:41:11 PM PDT 24
Peak memory 207004 kb
Host smart-1650867e-8403-440c-9631-0959e5010c01
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=486147764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.486147764
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.421825438
Short name T1434
Test name
Test status
Simulation time 142567980 ps
CPU time 0.8 seconds
Started Jul 31 05:41:10 PM PDT 24
Finished Jul 31 05:41:11 PM PDT 24
Peak memory 206932 kb
Host smart-da9baae3-c8a4-49e4-9fd1-032d625bb867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42182
5438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.421825438
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2939377652
Short name T2687
Test name
Test status
Simulation time 32894096 ps
CPU time 0.69 seconds
Started Jul 31 05:41:09 PM PDT 24
Finished Jul 31 05:41:10 PM PDT 24
Peak memory 206940 kb
Host smart-031834ca-1556-4b11-b563-52d75c5cb672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29393
77652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2939377652
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3534592585
Short name T1537
Test name
Test status
Simulation time 16412309065 ps
CPU time 42.05 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:41:53 PM PDT 24
Peak memory 215500 kb
Host smart-d0aae89a-6bea-4dc1-a2f6-dc66c3ba000f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35345
92585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3534592585
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.2298254033
Short name T46
Test name
Test status
Simulation time 172173030 ps
CPU time 0.88 seconds
Started Jul 31 05:41:10 PM PDT 24
Finished Jul 31 05:41:11 PM PDT 24
Peak memory 206996 kb
Host smart-b4801665-95b0-4fdc-9ae5-4f2dbb7105d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22982
54033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.2298254033
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.4058122159
Short name T1978
Test name
Test status
Simulation time 206124238 ps
CPU time 0.93 seconds
Started Jul 31 05:41:10 PM PDT 24
Finished Jul 31 05:41:11 PM PDT 24
Peak memory 206940 kb
Host smart-f00e42cf-ed14-4eeb-8189-7eb781f12e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40581
22159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.4058122159
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2437000591
Short name T604
Test name
Test status
Simulation time 4796638534 ps
CPU time 37.1 seconds
Started Jul 31 05:41:09 PM PDT 24
Finished Jul 31 05:41:47 PM PDT 24
Peak memory 223608 kb
Host smart-dffb9521-4800-4354-97a6-31101b04a794
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2437000591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2437000591
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.4155430288
Short name T682
Test name
Test status
Simulation time 15848568029 ps
CPU time 382.2 seconds
Started Jul 31 05:41:11 PM PDT 24
Finished Jul 31 05:47:33 PM PDT 24
Peak memory 215464 kb
Host smart-ae9b2256-58b4-4cd6-aa4b-50538943f84d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155430288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.4155430288
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3535555463
Short name T2325
Test name
Test status
Simulation time 173922438 ps
CPU time 0.91 seconds
Started Jul 31 05:41:09 PM PDT 24
Finished Jul 31 05:41:10 PM PDT 24
Peak memory 206984 kb
Host smart-b836f5a5-5f56-4622-b20f-086caf8e1420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35355
55463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3535555463
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3356581980
Short name T2590
Test name
Test status
Simulation time 186125328 ps
CPU time 0.9 seconds
Started Jul 31 05:41:09 PM PDT 24
Finished Jul 31 05:41:10 PM PDT 24
Peak memory 206992 kb
Host smart-9ad7db94-50d9-412e-a3b5-24efe481a787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33565
81980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3356581980
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2927993631
Short name T40
Test name
Test status
Simulation time 182374643 ps
CPU time 0.93 seconds
Started Jul 31 05:41:12 PM PDT 24
Finished Jul 31 05:41:13 PM PDT 24
Peak memory 207012 kb
Host smart-16237151-8a72-4014-81cb-d8c2de973c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29279
93631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2927993631
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.382056256
Short name T1991
Test name
Test status
Simulation time 183479311 ps
CPU time 0.9 seconds
Started Jul 31 05:41:12 PM PDT 24
Finished Jul 31 05:41:13 PM PDT 24
Peak memory 206956 kb
Host smart-d17f0fba-f996-4e5a-a470-18a95b4312bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38205
6256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.382056256
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1355881987
Short name T101
Test name
Test status
Simulation time 157927973 ps
CPU time 0.88 seconds
Started Jul 31 05:41:17 PM PDT 24
Finished Jul 31 05:41:18 PM PDT 24
Peak memory 207020 kb
Host smart-2c5b15e6-5a13-4f81-99c5-670106e539ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13558
81987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1355881987
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3736969990
Short name T1194
Test name
Test status
Simulation time 175817794 ps
CPU time 0.9 seconds
Started Jul 31 05:41:17 PM PDT 24
Finished Jul 31 05:41:18 PM PDT 24
Peak memory 206992 kb
Host smart-8d8df66e-3c29-4198-a744-ebc2a0477246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37369
69990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3736969990
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.4181070261
Short name T2406
Test name
Test status
Simulation time 5443710946 ps
CPU time 166.64 seconds
Started Jul 31 05:41:15 PM PDT 24
Finished Jul 31 05:44:02 PM PDT 24
Peak memory 215424 kb
Host smart-93d03997-c47b-42e6-b81d-6aa5d066c1a2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4181070261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.4181070261
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.908799229
Short name T1794
Test name
Test status
Simulation time 196672868 ps
CPU time 0.91 seconds
Started Jul 31 05:41:16 PM PDT 24
Finished Jul 31 05:41:17 PM PDT 24
Peak memory 207024 kb
Host smart-bf860071-8645-4806-8c1c-9c8200c90477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90879
9229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.908799229
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.1501429822
Short name T1261
Test name
Test status
Simulation time 204644547 ps
CPU time 0.99 seconds
Started Jul 31 05:41:15 PM PDT 24
Finished Jul 31 05:41:17 PM PDT 24
Peak memory 206980 kb
Host smart-ab3c9815-d249-40e2-b9a3-08516119ebe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15014
29822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.1501429822
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.4122353290
Short name T2684
Test name
Test status
Simulation time 914404765 ps
CPU time 2.44 seconds
Started Jul 31 05:41:17 PM PDT 24
Finished Jul 31 05:41:19 PM PDT 24
Peak memory 207100 kb
Host smart-9650ea2b-86c9-4b93-a7b5-590d65f3fb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41223
53290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.4122353290
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2660986389
Short name T2167
Test name
Test status
Simulation time 4399020014 ps
CPU time 42.56 seconds
Started Jul 31 05:41:15 PM PDT 24
Finished Jul 31 05:41:57 PM PDT 24
Peak memory 215400 kb
Host smart-c864ead0-eb57-4b2c-b3a3-1b26887cd001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26609
86389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2660986389
Directory /workspace/9.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.45537796
Short name T1141
Test name
Test status
Simulation time 850843819 ps
CPU time 19.27 seconds
Started Jul 31 05:41:12 PM PDT 24
Finished Jul 31 05:41:31 PM PDT 24
Peak memory 206680 kb
Host smart-fade1b8a-8e56-405e-9751-a344cfd7ff2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45537796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host_h
andshake.45537796
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest
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