Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	166420	1		T1	2		T2	3		T3	2
all_values[1]	166420	1		T1	2		T2	3		T3	2
all_values[2]	166420	1		T1	2		T2	3		T3	2
all_values[3]	166420	1		T1	2		T2	3		T3	2
all_values[4]	166420	1		T1	2		T2	3		T3	2
all_values[5]	166420	1		T1	2		T2	3		T3	2
all_values[6]	166420	1		T1	2		T2	3		T3	2
all_values[7]	166420	1		T1	2		T2	3		T3	2
all_values[8]	166420	1		T1	2		T2	3		T3	2
all_values[9]	166420	1		T1	2		T2	3		T3	2
all_values[10]	166420	1		T1	2		T2	3		T3	2
all_values[11]	166420	1		T1	2		T2	3		T3	2
all_values[12]	166420	1		T1	2		T2	3		T3	2
all_values[13]	166420	1		T1	2		T2	3		T3	2
all_values[14]	166420	1		T1	2		T2	3		T3	2
all_values[15]	166420	1		T1	2		T2	3		T3	2
all_values[16]	166420	1		T1	2		T2	3		T3	2
all_values[17]	166420	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5318465	1		T1	64		T2	96		T3	62
auto[1]	6975	1		T3	2		T11	3		T18	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4569481	1		T1	61		T2	78		T3	58
auto[1]	755959	1		T1	3		T2	18		T3	6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	141315	1		T1	2		T3	2		T10	3
all_values[0]	auto[0]	auto[1]	24261	1		T2	3		T10	1		T12	2
all_values[0]	auto[1]	auto[0]	740	1		T18	3		T29	3		T30	3
all_values[0]	auto[1]	auto[1]	104	1		T304	1		T305	1		T306	1
all_values[1]	auto[0]	auto[0]	163628	1		T1	2		T3	2		T10	4
all_values[1]	auto[0]	auto[1]	1594	1		T2	3		T4	2		T16	2
all_values[1]	auto[1]	auto[0]	425	1		T11	2		T26	1		T32	2
all_values[1]	auto[1]	auto[1]	773	1		T11	1		T26	1		T32	1
all_values[2]	auto[0]	auto[0]	3509	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	162650	1		T1	1		T2	2		T3	1
all_values[2]	auto[1]	auto[0]	127	1		T27	1		T28	1		T49	1
all_values[2]	auto[1]	auto[1]	134	1		T27	1		T28	1		T49	1
all_values[3]	auto[0]	auto[0]	164507	1		T1	2		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	284	1		T4	1		T16	1		T50	1
all_values[3]	auto[1]	auto[0]	1570	1		T51	1483		T134	2		T136	3
all_values[3]	auto[1]	auto[1]	59	1		T51	1		T134	1		T297	3
all_values[4]	auto[0]	auto[0]	3488	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	162777	1		T1	1		T2	2		T3	1
all_values[4]	auto[1]	auto[0]	88	1		T52	1		T137	2		T134	2
all_values[4]	auto[1]	auto[1]	67	1		T52	1		T137	3		T135	2
all_values[5]	auto[0]	auto[0]	166119	1		T1	2		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	116	1		T4	1		T26	1		T44	1
all_values[5]	auto[1]	auto[0]	109	1		T137	3		T134	3		T135	1
all_values[5]	auto[1]	auto[1]	76	1		T137	2		T134	3		T135	2
all_values[6]	auto[0]	auto[0]	166147	1		T1	2		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	105	1		T4	1		T44	1		T45	1
all_values[6]	auto[1]	auto[0]	113	1		T137	2		T134	3		T136	3
all_values[6]	auto[1]	auto[1]	55	1		T137	2		T135	1		T273	3
all_values[7]	auto[0]	auto[0]	114560	1		T1	2		T3	2		T4	2
all_values[7]	auto[0]	auto[1]	51693	1		T2	3		T10	4		T11	3
all_values[7]	auto[1]	auto[0]	112	1		T33	1		T34	1		T35	1
all_values[7]	auto[1]	auto[1]	55	1		T33	1		T34	1		T35	1
all_values[8]	auto[0]	auto[0]	165694	1		T1	2		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	44	1		T137	1		T136	1		T296	2
all_values[8]	auto[1]	auto[0]	592	1		T39	10		T37	10		T38	10
all_values[8]	auto[1]	auto[1]	90	1		T37	1		T38	1		T42	1
all_values[9]	auto[0]	auto[0]	166169	1		T1	2		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	45	1		T137	1		T134	1		T135	1
all_values[9]	auto[1]	auto[0]	132	1		T46	3		T47	3		T48	3
all_values[9]	auto[1]	auto[1]	74	1		T46	2		T47	2		T48	2
all_values[10]	auto[0]	auto[0]	165951	1		T1	2		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	313	1		T14	1		T17	1		T19	1
all_values[10]	auto[1]	auto[0]	91	1		T137	2		T134	4		T135	4
all_values[10]	auto[1]	auto[1]	65	1		T137	2		T134	2		T136	4
all_values[11]	auto[0]	auto[0]	166048	1		T1	2		T2	3		T10	4
all_values[11]	auto[0]	auto[1]	124	1		T57	1		T60	1		T61	1
all_values[11]	auto[1]	auto[0]	146	1		T3	1		T58	1		T59	1
all_values[11]	auto[1]	auto[1]	102	1		T3	1		T58	1		T59	1
all_values[12]	auto[0]	auto[0]	166175	1		T1	2		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	74	1		T64	1		T66	1		T67	1
all_values[12]	auto[1]	auto[0]	121	1		T62	2		T63	2		T65	2
all_values[12]	auto[1]	auto[1]	50	1		T62	1		T63	1		T65	1
all_values[13]	auto[0]	auto[0]	166116	1		T1	2		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	68	1		T64	1		T66	1		T67	1
all_values[13]	auto[1]	auto[0]	135	1		T57	1		T60	1		T61	1
all_values[13]	auto[1]	auto[1]	101	1		T57	1		T60	1		T61	1
all_values[14]	auto[0]	auto[0]	32406	1		T1	2		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	133840	1		T4	1		T5	1		T14	1
all_values[14]	auto[1]	auto[0]	113	1		T137	3		T134	2		T135	1
all_values[14]	auto[1]	auto[1]	61	1		T137	1		T134	2		T135	2
all_values[15]	auto[0]	auto[0]	3581	1		T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	162664	1		T1	1		T2	2		T3	1
all_values[15]	auto[1]	auto[0]	100	1		T137	1		T134	2		T135	2
all_values[15]	auto[1]	auto[1]	75	1		T134	1		T135	2		T136	2
all_values[16]	auto[0]	auto[0]	165781	1		T1	2		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	467	1		T17	1		T19	1		T53	1
all_values[16]	auto[1]	auto[0]	102	1		T54	4		T55	4		T56	4
all_values[16]	auto[1]	auto[1]	70	1		T54	4		T55	4		T56	4
all_values[17]	auto[0]	auto[0]	113499	1		T1	2		T4	2		T5	2
all_values[17]	auto[0]	auto[1]	52773	1		T2	3		T3	2		T10	4
all_values[17]	auto[1]	auto[0]	92	1		T43	1		T134	2		T135	2
all_values[17]	auto[1]	auto[1]	56	1		T43	1		T134	2		T135	1