Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	109082	1		T1	15		T2	1		T10	1
auto[1]	41129	1		T2	1		T4	55		T11	1

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	28070	1		T5	2		T16	5		T20	2
max_len_m1	684	1		T4	2		T16	1		T50	4
max_len_m2	773	1		T4	4		T16	3		T50	5
max_len_m3	719	1		T4	2		T5	2		T16	2
five	994	1		T16	8		T17	1		T50	7
four	1020	1		T4	2		T5	2		T16	6
three	628	1		T16	8		T50	3		T36	1
one	760	1		T16	8		T50	6		T233	25
zero	10473	1		T2	2		T14	19		T16	115

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23137	1		T5	1		T16	5		T20	1
max_len	auto[1]	4933	1		T5	1		T20	1		T6	91
max_len_m1	auto[0]	477	1		T4	1		T16	1		T50	4
max_len_m1	auto[1]	207	1		T4	1		T81	1		T44	1
max_len_m2	auto[0]	514	1		T4	2		T16	3		T50	5
max_len_m2	auto[1]	259	1		T4	2		T202	1		T153	1
max_len_m3	auto[0]	490	1		T4	1		T5	1		T16	2
max_len_m3	auto[1]	229	1		T4	1		T5	1		T19	1
five	auto[0]	525	1		T16	5		T17	1		T50	5
five	auto[1]	469	1		T16	3		T50	2		T81	1
four	auto[0]	534	1		T4	1		T5	1		T16	4
four	auto[1]	486	1		T4	1		T5	1		T16	2
three	auto[0]	305	1		T16	2		T50	2		T36	1
three	auto[1]	323	1		T16	6		T50	1		T233	12
one	auto[0]	348	1		T16	1		T50	2		T233	9
one	auto[1]	412	1		T16	7		T50	4		T233	16
zero	auto[0]	483	1		T2	1		T16	3		T50	4
zero	auto[1]	9990	1		T2	1		T14	19		T16	112