Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
56.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	96	48	48	50.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	48	48	50.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	63397	1		T2	1		T10	1		T4	55
auto[1]	36029	1		T2	1		T4	55		T11	1

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	8074	1		T16	36		T17	2		T19	1
endpoints[0x1]	8669	1		T2	2		T16	33		T17	6
endpoints[0x2]	10270	1		T10	1		T5	20		T16	29
endpoints[0x3]	7628	1		T13	1		T15	1		T16	28
endpoints[0x4]	7087	1		T11	2		T12	1		T5	20
endpoints[0x5]	6783	1		T5	20		T16	35		T17	3
endpoints[0x6]	6613	1		T4	22		T5	20		T16	35
endpoints[0x7]	7103	1		T4	22		T5	20		T14	19
endpoints[0x8]	9733	1		T4	22		T16	40		T17	5
endpoints[0x9]	8315	1		T4	22		T16	25		T17	4
endpoints[0xa]	8398	1		T4	22		T16	29		T17	2
endpoints[0xb]	10753	1		T16	27		T17	1		T19	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	45682	1		T4	50		T5	50		T14	6
data0	53733	1		T2	2		T10	1		T4	60

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	48	48	50.00	48

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	48

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	endpoints[0x0]	2114	1		T16	10		T19	1		T50	9
data1	auto[0]	endpoints[0x1]	2304	1		T16	6		T17	1		T50	9
data1	auto[0]	endpoints[0x2]	3261	1		T5	5		T16	7		T50	9
data1	auto[0]	endpoints[0x3]	1868	1		T16	7		T17	1		T50	9
data1	auto[0]	endpoints[0x4]	1710	1		T5	4		T16	8		T50	6
data1	auto[0]	endpoints[0x5]	1643	1		T5	5		T16	8		T17	1
data1	auto[0]	endpoints[0x6]	1366	1		T4	5		T5	5		T16	8
data1	auto[0]	endpoints[0x7]	1650	1		T4	4		T5	3		T16	6
data1	auto[0]	endpoints[0x8]	3002	1		T4	5		T16	10		T17	1
data1	auto[0]	endpoints[0x9]	2312	1		T4	5		T16	7		T17	1
data1	auto[0]	endpoints[0xa]	2274	1		T4	5		T16	4		T17	1
data1	auto[0]	endpoints[0xb]	3398	1		T16	5		T17	1		T50	6
data1	auto[1]	endpoints[0x0]	1561	1		T16	7		T17	2		T50	9
data1	auto[1]	endpoints[0x1]	1687	1		T16	10		T17	1		T50	6
data1	auto[1]	endpoints[0x2]	1553	1		T5	5		T16	7		T17	1
data1	auto[1]	endpoints[0x3]	1578	1		T16	7		T17	1		T19	1
data1	auto[1]	endpoints[0x4]	1490	1		T5	6		T16	9		T19	1
data1	auto[1]	endpoints[0x5]	1456	1		T5	5		T16	9		T17	1
data1	auto[1]	endpoints[0x6]	1639	1		T4	5		T5	5		T16	9
data1	auto[1]	endpoints[0x7]	1535	1		T4	6		T5	7		T14	6
data1	auto[1]	endpoints[0x8]	1491	1		T4	5		T16	9		T50	9
data1	auto[1]	endpoints[0x9]	1599	1		T4	5		T16	5		T17	2
data1	auto[1]	endpoints[0xa]	1548	1		T4	5		T16	10		T19	2
data1	auto[1]	endpoints[0xb]	1643	1		T16	8		T19	1		T50	10
data0	auto[0]	endpoints[0x0]	2980	1		T16	11		T50	10		T201	4
data0	auto[0]	endpoints[0x1]	3200	1		T2	1		T16	7		T17	1
data0	auto[0]	endpoints[0x2]	4011	1		T10	1		T5	5		T16	8
data0	auto[0]	endpoints[0x3]	2690	1		T13	1		T15	1		T16	7
data0	auto[0]	endpoints[0x4]	2495	1		T11	1		T12	1		T5	6
data0	auto[0]	endpoints[0x5]	2317	1		T5	5		T16	9		T18	1
data0	auto[0]	endpoints[0x6]	2079	1		T4	6		T5	5		T16	8
data0	auto[0]	endpoints[0x7]	2487	1		T4	7		T5	7		T16	6
data0	auto[0]	endpoints[0x8]	3814	1		T4	6		T16	11		T17	3
data0	auto[0]	endpoints[0x9]	3022	1		T4	6		T16	8		T17	1
data0	auto[0]	endpoints[0xa]	3142	1		T4	6		T16	5		T17	1
data0	auto[0]	endpoints[0xb]	4247	1		T16	5		T50	7		T70	515
data0	auto[1]	endpoints[0x0]	1418	1		T16	8		T50	9		T53	5
data0	auto[1]	endpoints[0x1]	1478	1		T2	1		T16	10		T17	3
data0	auto[1]	endpoints[0x2]	1445	1		T5	5		T16	7		T17	1
data0	auto[1]	endpoints[0x3]	1490	1		T16	7		T17	3		T20	1
data0	auto[1]	endpoints[0x4]	1390	1		T11	1		T5	4		T16	10
data0	auto[1]	endpoints[0x5]	1365	1		T5	5		T16	9		T17	1
data0	auto[1]	endpoints[0x6]	1529	1		T4	6		T5	5		T16	10
data0	auto[1]	endpoints[0x7]	1431	1		T4	5		T5	3		T14	13
data0	auto[1]	endpoints[0x8]	1426	1		T4	6		T16	10		T17	1
data0	auto[1]	endpoints[0x9]	1382	1		T4	6		T16	5		T50	11
data0	auto[1]	endpoints[0xa]	1431	1		T4	6		T16	10		T50	11
data0	auto[1]	endpoints[0xb]	1464	1		T16	9		T50	11		T201	3