Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	6	10	62.50

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	6	10	62.50	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6216	1		T1	1		T53	219		T161	1
auto[1]	47229	1		T1	2		T2	1		T4	60

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	47935	1		T1	2		T2	1		T4	60
auto[1]	5510	1		T1	1		T6	112		T79	1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	48753	1		T1	2		T2	1		T4	60
auto[1]	4692	1		T1	1		T78	1		T53	160

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	304	1		T204	7		T285	2		T286	3
pkt_types[PidTypeInToken]	53141	1		T1	3		T2	1		T4	60

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	6	10	62.50	6

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	*	[auto[0]]	[auto[1]]	--	--	2
[ignore_pre[PidTypePre]]	*	[auto[1]]	*	--	--	4

Covered bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

139

1

T204

3

T287

4

T288

7

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

165

1

T204

4

T285

2

T286

3

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3686

1

T53

145

T73

1

T289

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2282

1

T1

1

T53

74

T161

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

56

1

T73

1

T290

1

T291

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

53

1

T73

2

T292

2

T293

1

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

39353

1

T1

1

T2

1

T4

60

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2310

1

T78

1

T53

86

T289

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

5354

1

T1

1

T6

112

T79

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

47

1

T292

1

T294

1

T295

1