Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.46	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	1	10	90.91
Crosses	54	39	15	27.78

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	1	2	66.67	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	39	15	27.78	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19325	1		T4	55		T5	50		T81	37
solo	70443	1		T1	11		T2	1		T3	1
empty	2171	1		T12	1		T13	1		T15	1

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	19366	1		T4	55		T5	50		T81	37
solo	30741	1		T1	10		T12	1		T13	1
empty	41900	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
out	70751	1		T1	7		T2	1		T3	1
setup	21391	1		T1	4		T4	4		T12	1

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_rx

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
full	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
solo	40	1		T36	2		T37	1		T38	1
empty	76752	1		T1	11		T2	1		T3	1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	39	15	27.78	39

Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER
[full]	[full]	[full , solo]	*	--	--	4
[full]	[solo]	*	*	--	--	6
[full]	[empty]	[full]	*	--	--	2
[solo]	[full]	[full , solo]	*	--	--	4
[solo]	[solo]	[full]	*	--	--	2
[solo]	[empty]	[full]	*	--	--	2
[empty]	[full , solo]	[full , solo]	*	--	--	8
[empty]	[empty]	[full , solo]	*	--	--	4

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER
[full]	[empty]	[solo , empty]	[out]	--	--	2
[solo]	[full]	[empty]	[setup]	0	1	1
[solo]	[empty]	[solo , empty]	[out]	--	--	2
[empty]	[full , solo]	[empty]	[setup]	--	--	2

Covered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	full	empty	out	14835	1		T4	51		T5	40		T81	37
full	full	empty	setup	4469	1		T4	4		T5	10		T201	11
full	empty	solo	setup	9	1		T37	1		T276	1		T277	1
full	empty	empty	setup	6	1		T278	1		T279	1		T280	1
solo	full	empty	out	5	1		T36	1		T40	1		T41	1
solo	solo	solo	out	5	1		T36	1		T40	1		T41	1
solo	solo	solo	setup	5	1		T36	1		T40	1		T41	1
solo	solo	empty	out	8297	1		T1	6		T53	237		T161	1
solo	solo	empty	setup	8505	1		T1	4		T53	239		T161	3
solo	empty	solo	setup	1	1		T278	1		-	-		-	-
solo	empty	empty	setup	545	1		T12	1		T13	1		T15	1
empty	full	empty	out	4	1		T281	1		T282	1		T283	1
empty	solo	empty	out	39855	1		T1	1		T2	1		T3	1
empty	empty	empty	out	143	1		T54	1		T55	1		T51	140
empty	empty	empty	setup	50	1		T30	1		T154	1		T284	1