Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	166420	1		T1	2		T2	3		T3	2
all_pins[1]	166420	1		T1	2		T2	3		T3	2
all_pins[2]	166420	1		T1	2		T2	3		T3	2
all_pins[3]	166420	1		T1	2		T2	3		T3	2
all_pins[4]	166420	1		T1	2		T2	3		T3	2
all_pins[5]	166420	1		T1	2		T2	3		T3	2
all_pins[6]	166420	1		T1	2		T2	3		T3	2
all_pins[7]	166420	1		T1	2		T2	3		T3	2
all_pins[8]	166420	1		T1	2		T2	3		T3	2
all_pins[9]	166420	1		T1	2		T2	3		T3	2
all_pins[10]	166420	1		T1	2		T2	3		T3	2
all_pins[11]	166420	1		T1	2		T2	3		T3	2
all_pins[12]	166420	1		T1	2		T2	3		T3	2
all_pins[13]	166420	1		T1	2		T2	3		T3	2
all_pins[14]	166420	1		T1	2		T2	3		T3	2
all_pins[15]	166420	1		T1	2		T2	3		T3	2
all_pins[16]	166420	1		T1	2		T2	3		T3	2
all_pins[17]	166420	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5323373	1		T1	64		T2	96		T3	63
values[0x1]	2067	1		T3	1		T11	1		T26	1
transitions[0x0=>0x1]	1801	1		T3	1		T11	1		T26	1
transitions[0x1=>0x0]	1801	1		T3	1		T11	1		T26	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	166316	1		T1	2		T2	3		T3	2
all_pins[0]	values[0x1]	104	1		T304	1		T305	1		T306	1
all_pins[0]	transitions[0x0=>0x1]	91	1		T304	1		T305	1		T306	1
all_pins[0]	transitions[0x1=>0x0]	760	1		T11	1		T26	1		T32	1
all_pins[1]	values[0x0]	165647	1		T1	2		T2	3		T3	2
all_pins[1]	values[0x1]	773	1		T11	1		T26	1		T32	1
all_pins[1]	transitions[0x0=>0x1]	762	1		T11	1		T26	1		T32	1
all_pins[1]	transitions[0x1=>0x0]	123	1		T27	1		T28	1		T49	1
all_pins[2]	values[0x0]	166286	1		T1	2		T2	3		T3	2
all_pins[2]	values[0x1]	134	1		T27	1		T28	1		T49	1
all_pins[2]	transitions[0x0=>0x1]	114	1		T27	1		T28	1		T49	1
all_pins[2]	transitions[0x1=>0x0]	39	1		T51	1		T298	1		T300	3
all_pins[3]	values[0x0]	166361	1		T1	2		T2	3		T3	2
all_pins[3]	values[0x1]	59	1		T51	1		T134	1		T297	3
all_pins[3]	transitions[0x0=>0x1]	47	1		T51	1		T134	1		T297	3
all_pins[3]	transitions[0x1=>0x0]	55	1		T52	1		T137	3		T135	2
all_pins[4]	values[0x0]	166353	1		T1	2		T2	3		T3	2
all_pins[4]	values[0x1]	67	1		T52	1		T137	3		T135	2
all_pins[4]	transitions[0x0=>0x1]	47	1		T52	1		T137	2		T136	1
all_pins[4]	transitions[0x1=>0x0]	56	1		T137	1		T134	3		T136	3
all_pins[5]	values[0x0]	166344	1		T1	2		T2	3		T3	2
all_pins[5]	values[0x1]	76	1		T137	2		T134	3		T135	2
all_pins[5]	transitions[0x0=>0x1]	52	1		T137	2		T134	3		T135	2
all_pins[5]	transitions[0x1=>0x0]	31	1		T137	2		T135	1		T273	1
all_pins[6]	values[0x0]	166365	1		T1	2		T2	3		T3	2
all_pins[6]	values[0x1]	55	1		T137	2		T135	1		T273	3
all_pins[6]	transitions[0x0=>0x1]	43	1		T137	2		T135	1		T273	1
all_pins[6]	transitions[0x1=>0x0]	43	1		T33	1		T34	1		T35	1
all_pins[7]	values[0x0]	166365	1		T1	2		T2	3		T3	2
all_pins[7]	values[0x1]	55	1		T33	1		T34	1		T35	1
all_pins[7]	transitions[0x0=>0x1]	37	1		T33	1		T34	1		T35	1
all_pins[7]	transitions[0x1=>0x0]	72	1		T37	1		T38	1		T42	1
all_pins[8]	values[0x0]	166330	1		T1	2		T2	3		T3	2
all_pins[8]	values[0x1]	90	1		T37	1		T38	1		T42	1
all_pins[8]	transitions[0x0=>0x1]	77	1		T37	1		T38	1		T42	1
all_pins[8]	transitions[0x1=>0x0]	61	1		T46	2		T47	2		T48	2
all_pins[9]	values[0x0]	166346	1		T1	2		T2	3		T3	2
all_pins[9]	values[0x1]	74	1		T46	2		T47	2		T48	2
all_pins[9]	transitions[0x0=>0x1]	58	1		T46	2		T47	2		T48	2
all_pins[9]	transitions[0x1=>0x0]	49	1		T134	2		T136	1		T296	4
all_pins[10]	values[0x0]	166355	1		T1	2		T2	3		T3	2
all_pins[10]	values[0x1]	65	1		T137	2		T134	2		T136	4
all_pins[10]	transitions[0x0=>0x1]	56	1		T137	2		T134	2		T136	3
all_pins[10]	transitions[0x1=>0x0]	93	1		T3	1		T58	1		T59	1
all_pins[11]	values[0x0]	166318	1		T1	2		T2	3		T3	1
all_pins[11]	values[0x1]	102	1		T3	1		T58	1		T59	1
all_pins[11]	transitions[0x0=>0x1]	91	1		T3	1		T58	1		T59	1
all_pins[11]	transitions[0x1=>0x0]	39	1		T62	1		T63	1		T65	1
all_pins[12]	values[0x0]	166370	1		T1	2		T2	3		T3	2
all_pins[12]	values[0x1]	50	1		T62	1		T63	1		T65	1
all_pins[12]	transitions[0x0=>0x1]	38	1		T62	1		T63	1		T65	1
all_pins[12]	transitions[0x1=>0x0]	89	1		T57	1		T60	1		T61	1
all_pins[13]	values[0x0]	166319	1		T1	2		T2	3		T3	2
all_pins[13]	values[0x1]	101	1		T57	1		T60	1		T61	1
all_pins[13]	transitions[0x0=>0x1]	84	1		T57	1		T60	1		T61	1
all_pins[13]	transitions[0x1=>0x0]	44	1		T134	2		T135	2		T136	2
all_pins[14]	values[0x0]	166359	1		T1	2		T2	3		T3	2
all_pins[14]	values[0x1]	61	1		T137	1		T134	2		T135	2
all_pins[14]	transitions[0x0=>0x1]	35	1		T137	1		T134	1		T136	2
all_pins[14]	transitions[0x1=>0x0]	49	1		T298	1		T273	3		T301	2
all_pins[15]	values[0x0]	166345	1		T1	2		T2	3		T3	2
all_pins[15]	values[0x1]	75	1		T134	1		T135	2		T136	2
all_pins[15]	transitions[0x0=>0x1]	57	1		T134	1		T135	2		T136	2
all_pins[15]	transitions[0x1=>0x0]	52	1		T54	4		T55	4		T56	4
all_pins[16]	values[0x0]	166350	1		T1	2		T2	3		T3	2
all_pins[16]	values[0x1]	70	1		T54	4		T55	4		T56	4
all_pins[16]	transitions[0x0=>0x1]	56	1		T54	4		T55	4		T56	4
all_pins[16]	transitions[0x1=>0x0]	42	1		T43	1		T134	1		T135	1
all_pins[17]	values[0x0]	166364	1		T1	2		T2	3		T3	2
all_pins[17]	values[0x1]	56	1		T43	1		T134	2		T135	1
all_pins[17]	transitions[0x0=>0x1]	56	1		T43	1		T134	2		T135	1