Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4535	1		T53	113		T161	1		T152	14
invalid_ep[0xd]	4419	1		T1	2		T53	95		T73	2
invalid_ep[0xe]	4514	1		T1	1		T53	121		T161	1
invalid_ep[0xf]	4501	1		T53	117		T73	3		T152	5
endpoints[0x0]	12306	1		T16	36		T17	2		T19	1
endpoints[0x1]	12637	1		T1	2		T2	2		T16	33
endpoints[0x2]	14182	1		T1	2		T3	1		T10	1
endpoints[0x3]	12193	1		T1	1		T13	1		T15	1
endpoints[0x4]	11213	1		T1	1		T11	2		T12	1
endpoints[0x5]	11125	1		T1	3		T5	21		T16	35
endpoints[0x6]	10785	1		T1	1		T4	23		T5	21
endpoints[0x7]	10892	1		T1	1		T4	23		T5	21
endpoints[0x8]	13717	1		T1	1		T4	23		T16	40
endpoints[0x9]	12438	1		T4	23		T16	25		T17	4
endpoints[0xa]	11956	1		T4	23		T16	29		T17	2
endpoints[0xb]	15095	1		T1	3		T16	27		T17	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	21391	1		T1	4		T4	4		T12	1
pkt_types[PidTypeOutToken]	70751	1		T1	7		T2	1		T3	1
pkt_types[PidTypeInToken]	57098	1		T1	3		T2	1		T4	60

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1023	1		T53	31		T74	12		T76	17
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1030	1		T53	28		T73	1		T74	9
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1006	1		T53	28		T311	1		T74	9
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1019	1		T53	32		T73	2		T74	7
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1451	1		T53	32		T161	1		T201	4
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1570	1		T53	32		T201	3		T44	5
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1359	1		T53	29		T161	1		T73	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1460	1		T1	1		T13	1		T15	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1410	1		T12	1		T5	5		T53	28
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1347	1		T1	3		T18	1		T53	27
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1430	1		T53	24		T29	1		T152	2
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1431	1		T4	4		T5	5		T53	28
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1442	1		T53	33		T203	5		T204	5
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1508	1		T53	27		T289	1		T30	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1441	1		T53	29		T43	1		T153	2
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1464	1		T53	36		T161	1		T201	2
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1516	1		T53	31		T161	1		T152	14
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1461	1		T1	1		T53	22		T152	7
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1519	1		T1	1		T53	38		T161	1
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1510	1		T53	32		T152	5		T153	3
pkt_types[PidTypeOutToken]	endpoints[0x0]	5196	1		T16	21		T19	1		T50	19
pkt_types[PidTypeOutToken]	endpoints[0x1]	5456	1		T1	1		T2	1		T16	13
pkt_types[PidTypeOutToken]	endpoints[0x2]	7494	1		T3	1		T10	1		T5	10
pkt_types[PidTypeOutToken]	endpoints[0x3]	4729	1		T16	14		T17	2		T20	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	4343	1		T11	1		T5	5		T16	17
pkt_types[PidTypeOutToken]	endpoints[0x5]	4330	1		T5	10		T16	17		T17	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	3516	1		T4	11		T5	10		T16	16
pkt_types[PidTypeOutToken]	endpoints[0x7]	4193	1		T1	1		T4	7		T5	5
pkt_types[PidTypeOutToken]	endpoints[0x8]	6910	1		T1	1		T4	11		T16	21
pkt_types[PidTypeOutToken]	endpoints[0x9]	5450	1		T4	11		T16	15		T17	2
pkt_types[PidTypeOutToken]	endpoints[0xa]	5413	1		T4	11		T16	9		T17	2
pkt_types[PidTypeOutToken]	endpoints[0xb]	7715	1		T1	2		T16	10		T17	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1002	1		T53	21		T74	16		T76	22
pkt_types[PidTypeInToken]	invalid_ep[0xd]	952	1		T53	18		T73	1		T74	9
pkt_types[PidTypeInToken]	invalid_ep[0xe]	978	1		T53	21		T74	8		T76	24
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1025	1		T53	30		T73	1		T74	13
pkt_types[PidTypeInToken]	endpoints[0x0]	4515	1		T16	15		T17	2		T50	18
pkt_types[PidTypeInToken]	endpoints[0x1]	4487	1		T1	1		T2	1		T16	20
pkt_types[PidTypeInToken]	endpoints[0x2]	4258	1		T1	1		T5	11		T16	14
pkt_types[PidTypeInToken]	endpoints[0x3]	4911	1		T16	14		T17	4		T19	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4297	1		T1	1		T11	1		T5	11
pkt_types[PidTypeInToken]	endpoints[0x5]	4322	1		T5	11		T16	18		T17	2
pkt_types[PidTypeInToken]	endpoints[0x6]	4735	1		T4	12		T5	11		T16	19
pkt_types[PidTypeInToken]	endpoints[0x7]	4175	1		T4	12		T5	11		T14	19
pkt_types[PidTypeInToken]	endpoints[0x8]	4286	1		T4	12		T16	19		T17	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4341	1		T4	12		T16	10		T17	2
pkt_types[PidTypeInToken]	endpoints[0xa]	4008	1		T4	12		T16	20		T19	2
pkt_types[PidTypeInToken]	endpoints[0xb]	4806	1		T16	17		T19	1		T50	21