Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T137	4		T134	7		T135	4
all_values[1]	269	1		T137	4		T134	7		T135	4
all_values[2]	269	1		T137	4		T134	7		T135	4
all_values[3]	269	1		T137	4		T134	7		T135	4
all_values[4]	269	1		T137	4		T134	7		T135	4
all_values[5]	269	1		T137	4		T134	7		T135	4
all_values[6]	269	1		T137	4		T134	7		T135	4
all_values[7]	269	1		T137	4		T134	7		T135	4
all_values[8]	269	1		T137	4		T134	7		T135	4
all_values[9]	269	1		T137	4		T134	7		T135	4
all_values[10]	269	1		T137	4		T134	7		T135	4
all_values[11]	269	1		T137	4		T134	7		T135	4
all_values[12]	269	1		T137	4		T134	7		T135	4
all_values[13]	269	1		T137	4		T134	7		T135	4
all_values[14]	269	1		T137	4		T134	7		T135	4
all_values[15]	269	1		T137	4		T134	7		T135	4
all_values[16]	269	1		T137	4		T134	7		T135	4
all_values[17]	269	1		T137	4		T134	7		T135	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6339	1		T137	104		T134	163		T135	86
auto[1]	2269	1		T137	24		T134	61		T135	42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5984	1		T137	91		T134	145		T135	83
auto[1]	2624	1		T137	37		T134	79		T135	45

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5214	1		T137	83		T134	121		T135	70
auto[1]	3394	1		T137	45		T134	103		T135	58

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	83	1		T137	1		T134	3		T135	2
all_values[0]	auto[0]	auto[1]	auto[0]	84	1		T137	1		T136	4		T296	2
all_values[0]	auto[1]	auto[0]	auto[1]	47	1		T134	1		T135	2		T136	1
all_values[0]	auto[1]	auto[1]	auto[1]	55	1		T137	2		T134	3		T297	1
all_values[1]	auto[0]	auto[0]	auto[0]	93	1		T137	2		T134	2		T296	1
all_values[1]	auto[0]	auto[1]	auto[0]	74	1		T134	2		T135	3		T136	4
all_values[1]	auto[1]	auto[0]	auto[1]	56	1		T137	2		T134	1		T296	1
all_values[1]	auto[1]	auto[1]	auto[1]	46	1		T134	2		T135	1		T136	3
all_values[2]	auto[0]	auto[0]	auto[0]	43	1		T134	1		T136	1		T296	2
all_values[2]	auto[0]	auto[0]	auto[1]	41	1		T134	1		T135	1		T136	2
all_values[2]	auto[0]	auto[1]	auto[0]	31	1		T137	1		T136	1		T273	1
all_values[2]	auto[0]	auto[1]	auto[1]	45	1		T137	1		T134	2		T297	2
all_values[2]	auto[1]	auto[0]	auto[1]	61	1		T137	1		T135	1		T296	1
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T137	1		T134	3		T135	2
all_values[3]	auto[0]	auto[0]	auto[0]	65	1		T137	3		T134	1		T135	2
all_values[3]	auto[0]	auto[0]	auto[1]	29	1		T298	2		T273	2		T299	1
all_values[3]	auto[0]	auto[1]	auto[0]	44	1		T134	1		T136	2		T296	2
all_values[3]	auto[0]	auto[1]	auto[1]	26	1		T134	1		T297	1		T300	3
all_values[3]	auto[1]	auto[0]	auto[1]	69	1		T137	1		T134	2		T135	2
all_values[3]	auto[1]	auto[1]	auto[1]	36	1		T134	2		T136	1		T297	1
all_values[4]	auto[0]	auto[0]	auto[0]	56	1		T137	1		T134	1		T136	2
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T134	1		T136	1		T296	1
all_values[4]	auto[0]	auto[1]	auto[0]	39	1		T134	3		T135	1		T298	2
all_values[4]	auto[0]	auto[1]	auto[1]	27	1		T137	2		T135	1		T273	1
all_values[4]	auto[1]	auto[0]	auto[1]	53	1		T134	1		T136	3		T296	1
all_values[4]	auto[1]	auto[1]	auto[1]	63	1		T137	1		T134	1		T135	2
all_values[5]	auto[0]	auto[0]	auto[0]	67	1		T135	2		T136	1		T297	4
all_values[5]	auto[0]	auto[0]	auto[1]	18	1		T134	1		T296	1		T298	1
all_values[5]	auto[0]	auto[1]	auto[0]	51	1		T137	2		T134	1		T136	3
all_values[5]	auto[0]	auto[1]	auto[1]	35	1		T137	1		T135	1		T136	1
all_values[5]	auto[1]	auto[0]	auto[1]	45	1		T137	1		T134	2		T296	1
all_values[5]	auto[1]	auto[1]	auto[1]	53	1		T134	3		T135	1		T136	2
all_values[6]	auto[0]	auto[0]	auto[0]	67	1		T137	2		T136	1		T297	2
all_values[6]	auto[0]	auto[0]	auto[1]	20	1		T134	2		T135	1		T136	2
all_values[6]	auto[0]	auto[1]	auto[0]	51	1		T134	1		T136	2		T296	2
all_values[6]	auto[0]	auto[1]	auto[1]	26	1		T137	1		T273	2		T299	1
all_values[6]	auto[1]	auto[0]	auto[1]	55	1		T137	1		T134	3		T135	1
all_values[6]	auto[1]	auto[1]	auto[1]	50	1		T134	1		T135	2		T136	1
all_values[7]	auto[0]	auto[0]	auto[0]	82	1		T137	3		T134	3		T136	4
all_values[7]	auto[0]	auto[1]	auto[0]	77	1		T134	2		T135	2		T136	1
all_values[7]	auto[1]	auto[0]	auto[1]	59	1		T137	1		T134	2		T136	1
all_values[7]	auto[1]	auto[1]	auto[1]	51	1		T135	2		T136	1		T296	1
all_values[8]	auto[0]	auto[0]	auto[0]	90	1		T137	1		T134	2		T136	3
all_values[8]	auto[0]	auto[1]	auto[0]	72	1		T137	1		T134	2		T135	2
all_values[8]	auto[1]	auto[0]	auto[1]	60	1		T137	1		T134	1		T136	1
all_values[8]	auto[1]	auto[1]	auto[1]	47	1		T137	1		T134	2		T135	2
all_values[9]	auto[0]	auto[0]	auto[0]	57	1		T134	4		T296	2		T297	3
all_values[9]	auto[0]	auto[0]	auto[1]	24	1		T137	1		T134	1		T298	3
all_values[9]	auto[0]	auto[1]	auto[0]	67	1		T134	1		T135	2		T296	2
all_values[9]	auto[0]	auto[1]	auto[1]	29	1		T137	1		T136	4		T273	1
all_values[9]	auto[1]	auto[0]	auto[1]	45	1		T137	2		T134	1		T136	1
all_values[9]	auto[1]	auto[1]	auto[1]	47	1		T135	2		T136	2		T273	2
all_values[10]	auto[0]	auto[0]	auto[0]	49	1		T137	1		T134	1		T297	2
all_values[10]	auto[0]	auto[0]	auto[1]	33	1		T136	1		T297	1		T273	1
all_values[10]	auto[0]	auto[1]	auto[0]	44	1		T137	1		T134	3		T135	3
all_values[10]	auto[0]	auto[1]	auto[1]	22	1		T137	1		T134	1		T136	2
all_values[10]	auto[1]	auto[0]	auto[1]	54	1		T134	1		T136	1		T297	1
all_values[10]	auto[1]	auto[1]	auto[1]	67	1		T137	1		T134	1		T135	1
all_values[11]	auto[0]	auto[0]	auto[0]	66	1		T137	4		T296	3		T297	1
all_values[11]	auto[0]	auto[0]	auto[1]	25	1		T134	1		T136	2		T297	1
all_values[11]	auto[0]	auto[1]	auto[0]	52	1		T136	1		T273	1		T301	2
all_values[11]	auto[0]	auto[1]	auto[1]	23	1		T134	2		T135	2		T298	1
all_values[11]	auto[1]	auto[0]	auto[1]	59	1		T134	1		T135	2		T136	1
all_values[11]	auto[1]	auto[1]	auto[1]	44	1		T134	3		T136	3		T297	1
all_values[12]	auto[0]	auto[0]	auto[0]	67	1		T137	4		T134	1		T135	2
all_values[12]	auto[0]	auto[0]	auto[1]	34	1		T134	2		T135	1		T136	1
all_values[12]	auto[0]	auto[1]	auto[0]	52	1		T134	1		T298	2		T273	2
all_values[12]	auto[0]	auto[1]	auto[1]	15	1		T134	1		T274	1		T302	1
all_values[12]	auto[1]	auto[0]	auto[1]	59	1		T134	2		T135	1		T136	3
all_values[12]	auto[1]	auto[1]	auto[1]	42	1		T136	3		T298	1		T301	1
all_values[13]	auto[0]	auto[0]	auto[0]	65	1		T134	1		T296	1		T297	2
all_values[13]	auto[0]	auto[0]	auto[1]	28	1		T137	1		T134	1		T135	1
all_values[13]	auto[0]	auto[1]	auto[0]	38	1		T134	1		T135	1		T136	1
all_values[13]	auto[0]	auto[1]	auto[1]	25	1		T136	1		T273	1		T274	1
all_values[13]	auto[1]	auto[0]	auto[1]	62	1		T137	1		T134	4		T135	1
all_values[13]	auto[1]	auto[1]	auto[1]	51	1		T137	2		T135	1		T136	4
all_values[14]	auto[0]	auto[0]	auto[0]	55	1		T137	1		T136	1		T297	1
all_values[14]	auto[0]	auto[0]	auto[1]	20	1		T134	2		T136	1		T296	1
all_values[14]	auto[0]	auto[1]	auto[0]	65	1		T137	2		T134	1		T296	2
all_values[14]	auto[0]	auto[1]	auto[1]	33	1		T135	1		T136	3		T299	1
all_values[14]	auto[1]	auto[0]	auto[1]	56	1		T135	2		T136	1		T296	1
all_values[14]	auto[1]	auto[1]	auto[1]	40	1		T137	1		T134	4		T135	1
all_values[15]	auto[0]	auto[0]	auto[0]	63	1		T137	2		T134	1		T136	2
all_values[15]	auto[0]	auto[0]	auto[1]	15	1		T296	1		T299	1		T303	1
all_values[15]	auto[0]	auto[1]	auto[0]	43	1		T134	1		T136	2		T297	2
all_values[15]	auto[0]	auto[1]	auto[1]	33	1		T135	1		T136	1		T273	1
all_values[15]	auto[1]	auto[0]	auto[1]	53	1		T137	2		T134	3		T135	2
all_values[15]	auto[1]	auto[1]	auto[1]	62	1		T134	2		T135	1		T136	1
all_values[16]	auto[0]	auto[0]	auto[0]	71	1		T134	1		T135	2		T136	3
all_values[16]	auto[0]	auto[0]	auto[1]	25	1		T137	1		T134	3		T296	1
all_values[16]	auto[0]	auto[1]	auto[0]	40	1		T297	1		T298	1		T273	1
all_values[16]	auto[0]	auto[1]	auto[1]	24	1		T136	1		T298	2		T300	2
all_values[16]	auto[1]	auto[0]	auto[1]	53	1		T137	3		T134	1		T136	1
all_values[16]	auto[1]	auto[1]	auto[1]	56	1		T134	2		T135	2		T136	2
all_values[17]	auto[0]	auto[0]	auto[0]	82	1		T137	2		T134	2		T135	2
all_values[17]	auto[0]	auto[1]	auto[0]	73	1		T134	3		T135	1		T136	2
all_values[17]	auto[1]	auto[0]	auto[1]	63	1		T137	2		T136	2		T296	2
all_values[17]	auto[1]	auto[1]	auto[1]	51	1		T134	2		T135	1		T136	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal