Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.77	96.67	93.20	96.59	79.69	95.77	97.36	90.14

Total test records in report: 3014

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html | tests63.html

T3001	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3197502450			Aug 01 05:44:17 PM PDT 24	Aug 01 05:44:19 PM PDT 24	82712883 ps
T3002	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2732120457			Aug 01 05:44:27 PM PDT 24	Aug 01 05:44:28 PM PDT 24	75022202 ps
T3003	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3557438719			Aug 01 05:44:25 PM PDT 24	Aug 01 05:44:34 PM PDT 24	1353603757 ps
T3004	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1909091241			Aug 01 05:43:45 PM PDT 24	Aug 01 05:43:46 PM PDT 24	60655093 ps
T3005	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.4262407855			Aug 01 05:44:51 PM PDT 24	Aug 01 05:44:52 PM PDT 24	64896081 ps
T3006	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.259515258			Aug 01 05:44:32 PM PDT 24	Aug 01 05:44:37 PM PDT 24	514390580 ps
T3007	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1051808900			Aug 01 05:44:18 PM PDT 24	Aug 01 05:44:19 PM PDT 24	43171781 ps
T3008	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.21274371			Aug 01 05:44:48 PM PDT 24	Aug 01 05:44:50 PM PDT 24	123974624 ps
T3009	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3828599986			Aug 01 05:45:42 PM PDT 24	Aug 01 05:45:44 PM PDT 24	72972722 ps
T3010	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1135280346			Aug 01 05:43:45 PM PDT 24	Aug 01 05:43:47 PM PDT 24	211029188 ps
T3011	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3074982568			Aug 01 05:44:10 PM PDT 24	Aug 01 05:44:13 PM PDT 24	337527578 ps
T3012	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1876797390			Aug 01 05:45:42 PM PDT 24	Aug 01 05:45:44 PM PDT 24	87926020 ps
T3013	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4115542143			Aug 01 05:45:47 PM PDT 24	Aug 01 05:45:50 PM PDT 24	202616810 ps
T3014	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2887042323			Aug 01 05:44:49 PM PDT 24	Aug 01 05:44:50 PM PDT 24	102317101 ps

Test location	/workspace/coverage/default/5.usbdev_rand_suspends.4194373463
Short name	T4
Test name
Test status
Simulation time	10824355159 ps
CPU time	213.93 seconds
Started	Aug 01 06:12:11 PM PDT 24
Finished	Aug 01 06:15:45 PM PDT 24
Peak memory	217952 kb
Host	smart-5fec8a86-9e85-44a0-b624-e05cb64966c9
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194373463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.4194373463
Directory	/workspace/5.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/151.usbdev_endpoint_types.1820392347
Short name	T1
Test name
Test status
Simulation time	653148947 ps
CPU time	1.84 seconds
Started	Aug 01 06:20:23 PM PDT 24
Finished	Aug 01 06:20:25 PM PDT 24
Peak memory	206876 kb
Host	smart-101864c1-75c8-480a-81d6-b9e764b91c83
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1820392347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.1820392347
Directory	/workspace/151.usbdev_endpoint_types/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.197660729
Short name	T136
Test name
Test status
Simulation time	69059185 ps
CPU time	0.81 seconds
Started	Aug 01 05:44:50 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	206492 kb
Host	smart-d16322fe-4240-4095-8af7-746036f66361
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=197660729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.197660729
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/default/37.usbdev_data_toggle_restore.1379132429
Short name	T17
Test name
Test status
Simulation time	1323519113 ps
CPU time	3.31 seconds
Started	Aug 01 06:18:03 PM PDT 24
Finished	Aug 01 06:18:07 PM PDT 24
Peak memory	207120 kb
Host	smart-7de873a2-e312-4495-a620-651809a092ef
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1379132429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1379132429
Directory	/workspace/37.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/9.usbdev_link_suspend.1345723399
Short name	T26
Test name
Test status
Simulation time	11296145147 ps
CPU time	14.38 seconds
Started	Aug 01 06:13:06 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	207156 kb
Host	smart-500b7720-c4f8-4097-9bfd-44fff3fc6eda
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13457 23399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.1345723399
Directory	/workspace/9.usbdev_link_suspend/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2004062887
Short name	T107
Test name
Test status
Simulation time	1043785723 ps
CPU time	4.9 seconds
Started	Aug 01 05:45:42 PM PDT 24
Finished	Aug 01 05:45:47 PM PDT 24
Peak memory	204176 kb
Host	smart-7848b19d-b521-492a-95f1-5afe13e788de
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2004062887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2004062887
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/26.usbdev_device_address.1274146351
Short name	T53
Test name
Test status
Simulation time	54683591705 ps
CPU time	79.58 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:17:30 PM PDT 24
Peak memory	207112 kb
Host	smart-2d86399c-8412-4819-a1b4-fc6871e1b3c1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12741 46351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1274146351
Directory	/workspace/26.usbdev_device_address/latest

Test location	/workspace/coverage/default/19.usbdev_link_suspend.1031361575
Short name	T98
Test name
Test status
Simulation time	4389053978 ps
CPU time	5.63 seconds
Started	Aug 01 06:15:18 PM PDT 24
Finished	Aug 01 06:15:24 PM PDT 24
Peak memory	215348 kb
Host	smart-d6155b73-cd94-4521-aec1-e48c6c9b6d10
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10313 61575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1031361575
Directory	/workspace/19.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/29.usbdev_pkt_buffer.469591663
Short name	T233
Test name
Test status
Simulation time	22475205722 ps
CPU time	57.36 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:17:49 PM PDT 24
Peak memory	219440 kb
Host	smart-1862df5b-5760-4d3f-ac1c-657bf4502b8d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46959 1663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.469591663
Directory	/workspace/29.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/5.usbdev_max_usb_traffic.3821640556
Short name	T155
Test name
Test status
Simulation time	2859579501 ps
CPU time	21.56 seconds
Started	Aug 01 06:12:07 PM PDT 24
Finished	Aug 01 06:12:29 PM PDT 24
Peak memory	223496 kb
Host	smart-6d0b4b76-229e-4058-8563-83152d8c8515
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3821640556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.3821640556
Directory	/workspace/5.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/0.usbdev_sec_cm.2996550407
Short name	T123
Test name
Test status
Simulation time	235784103 ps
CPU time	1.02 seconds
Started	Aug 01 06:10:51 PM PDT 24
Finished	Aug 01 06:10:52 PM PDT 24
Peak memory	222688 kb
Host	smart-1c07e33e-ace4-4c76-9cf1-2a5b60a44bb4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2996550407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2996550407
Directory	/workspace/0.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3452349189
Short name	T111
Test name
Test status
Simulation time	307787913 ps
CPU time	1.13 seconds
Started	Aug 01 06:10:54 PM PDT 24
Finished	Aug 01 06:10:55 PM PDT 24
Peak memory	206944 kb
Host	smart-ecd86714-ef7d-4f65-9c20-4e12e521d7fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34523 49189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3452349189
Directory	/workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location	/workspace/coverage/default/15.usbdev_phy_pins_sense.482493393
Short name	T7
Test name
Test status
Simulation time	46152870 ps
CPU time	0.7 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:14:30 PM PDT 24
Peak memory	206912 kb
Host	smart-d7b9dd0b-27d3-408e-b336-cb5a3b71b69b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48249 3393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.482493393
Directory	/workspace/15.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.650556785
Short name	T238
Test name
Test status
Simulation time	380015472 ps
CPU time	3.65 seconds
Started	Aug 01 05:44:18 PM PDT 24
Finished	Aug 01 05:44:22 PM PDT 24
Peak memory	219624 kb
Host	smart-e7e3aa11-c2f8-43df-9f5b-ce602277dc33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=650556785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.650556785
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.3259495586
Short name	T299
Test name
Test status
Simulation time	71769225 ps
CPU time	0.81 seconds
Started	Aug 01 05:44:17 PM PDT 24
Finished	Aug 01 05:44:18 PM PDT 24
Peak memory	206400 kb
Host	smart-064d1dbb-42ff-4c90-8172-42e7ba2bbe2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3259495586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3259495586
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/default/22.usbdev_disconnected.3104539573
Short name	T610
Test name
Test status
Simulation time	137742718 ps
CPU time	0.85 seconds
Started	Aug 01 06:15:57 PM PDT 24
Finished	Aug 01 06:15:58 PM PDT 24
Peak memory	206900 kb
Host	smart-f2600233-f57e-412d-90f7-16aadc66a07e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31045 39573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.3104539573
Directory	/workspace/22.usbdev_disconnected/latest

Test location	/workspace/coverage/default/46.usbdev_iso_retraction.535148635
Short name	T6
Test name
Test status
Simulation time	8166264884 ps
CPU time	53.24 seconds
Started	Aug 01 06:19:27 PM PDT 24
Finished	Aug 01 06:20:20 PM PDT 24
Peak memory	207160 kb
Host	smart-c6ab7287-50dc-4a0f-9f7a-d1f5159f3a2f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=535148635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.535148635
Directory	/workspace/46.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/45.usbdev_link_suspend.2564300252
Short name	T754
Test name
Test status
Simulation time	9279482499 ps
CPU time	14.34 seconds
Started	Aug 01 06:19:13 PM PDT 24
Finished	Aug 01 06:19:27 PM PDT 24
Peak memory	207096 kb
Host	smart-f157612c-a94e-4644-b4ba-ff86107ead19
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25643 00252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2564300252
Directory	/workspace/45.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/39.usbdev_device_address.787316605
Short name	T361
Test name
Test status
Simulation time	53951072230 ps
CPU time	83.92 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:19:39 PM PDT 24
Peak memory	207180 kb
Host	smart-d3403790-c09e-442d-8dc5-6f57b55299f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78731 6605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.787316605
Directory	/workspace/39.usbdev_device_address/latest

Test location	/workspace/coverage/default/0.usbdev_resume_link_active.1680053292
Short name	T95
Test name
Test status
Simulation time	20167280614 ps
CPU time	28.09 seconds
Started	Aug 01 06:10:51 PM PDT 24
Finished	Aug 01 06:11:19 PM PDT 24
Peak memory	206984 kb
Host	smart-a95fa009-071f-4408-a4ac-80deb17488de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16800 53292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.1680053292
Directory	/workspace/0.usbdev_resume_link_active/latest

Test location	/workspace/coverage/default/10.usbdev_link_suspend.317869174
Short name	T96
Test name
Test status
Simulation time	6249916231 ps
CPU time	10.11 seconds
Started	Aug 01 06:13:22 PM PDT 24
Finished	Aug 01 06:13:32 PM PDT 24
Peak memory	215144 kb
Host	smart-3f3311b5-fcfb-4f07-9792-5d6ba95c91e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31786 9174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.317869174
Directory	/workspace/10.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/15.usbdev_bitstuff_err.1013927336
Short name	T624
Test name
Test status
Simulation time	200339162 ps
CPU time	0.94 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:16 PM PDT 24
Peak memory	206904 kb
Host	smart-43af8b84-38ba-4cbb-93b1-58e0f7bd6338
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10139 27336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1013927336
Directory	/workspace/15.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2528938289
Short name	T253
Test name
Test status
Simulation time	85302271 ps
CPU time	2.3 seconds
Started	Aug 01 05:44:08 PM PDT 24
Finished	Aug 01 05:44:11 PM PDT 24
Peak memory	214868 kb
Host	smart-30efc7f5-993d-4fff-aeb0-5827b5d2db8f
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2528938289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2528938289
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/default/28.usbdev_rx_full.2199525670
Short name	T278
Test name
Test status
Simulation time	277424318 ps
CPU time	1.12 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206900 kb
Host	smart-702ca71a-d905-4118-9965-12371d1867eb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21995 25670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.2199525670
Directory	/workspace/28.usbdev_rx_full/latest

Test location	/workspace/coverage/default/110.usbdev_endpoint_types.1855623525
Short name	T336
Test name
Test status
Simulation time	679508282 ps
CPU time	1.57 seconds
Started	Aug 01 06:20:09 PM PDT 24
Finished	Aug 01 06:20:11 PM PDT 24
Peak memory	206832 kb
Host	smart-c5402fd6-9f6e-4d9c-8b1b-adf7c7bf22fd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1855623525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.1855623525
Directory	/workspace/110.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/64.usbdev_endpoint_types.3180170204
Short name	T291
Test name
Test status
Simulation time	1099223964 ps
CPU time	2.05 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206936 kb
Host	smart-af72f614-a16c-40a2-91ec-e2a8368c4c30
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3180170204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.3180170204
Directory	/workspace/64.usbdev_endpoint_types/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.2470614855
Short name	T134
Test name
Test status
Simulation time	53501371 ps
CPU time	0.76 seconds
Started	Aug 01 05:44:31 PM PDT 24
Finished	Aug 01 05:44:31 PM PDT 24
Peak memory	206436 kb
Host	smart-06a68319-a99f-45f9-bf48-296455d7386e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2470614855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2470614855
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/default/43.usbdev_endpoint_types.1405046688
Short name	T396
Test name
Test status
Simulation time	586121138 ps
CPU time	1.56 seconds
Started	Aug 01 06:19:02 PM PDT 24
Finished	Aug 01 06:19:04 PM PDT 24
Peak memory	206916 kb
Host	smart-1307d589-a1d4-4861-ba08-14f0ea3b6a50
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1405046688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.1405046688
Directory	/workspace/43.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/14.usbdev_device_address.713194189
Short name	T76
Test name
Test status
Simulation time	39698928453 ps
CPU time	60.41 seconds
Started	Aug 01 06:14:06 PM PDT 24
Finished	Aug 01 06:15:07 PM PDT 24
Peak memory	207168 kb
Host	smart-8223c6c1-d99f-473d-9d2c-d5266b85b56e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71319 4189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.713194189
Directory	/workspace/14.usbdev_device_address/latest

Test location	/workspace/coverage/default/4.usbdev_rx_crc_err.658432646
Short name	T3
Test name
Test status
Simulation time	176340383 ps
CPU time	0.9 seconds
Started	Aug 01 06:12:02 PM PDT 24
Finished	Aug 01 06:12:03 PM PDT 24
Peak memory	206896 kb
Host	smart-9a2d1556-f022-4078-a6b9-736a6702ac61
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65843 2646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.658432646
Directory	/workspace/4.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/28.usbdev_phy_config_pinflip.3393196545
Short name	T112
Test name
Test status
Simulation time	219568073 ps
CPU time	0.95 seconds
Started	Aug 01 06:16:35 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206948 kb
Host	smart-f79c54c6-4325-4007-9728-16962a3f4c7f
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3393196545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3393196545
Directory	/workspace/28.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/127.usbdev_endpoint_types.120357926
Short name	T389
Test name
Test status
Simulation time	792235352 ps
CPU time	1.85 seconds
Started	Aug 01 06:20:22 PM PDT 24
Finished	Aug 01 06:20:24 PM PDT 24
Peak memory	206832 kb
Host	smart-8f21d6ac-1cbf-4bac-a43c-08b08d5248bc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=120357926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.120357926
Directory	/workspace/127.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/122.usbdev_endpoint_types.222712690
Short name	T386
Test name
Test status
Simulation time	480288544 ps
CPU time	1.42 seconds
Started	Aug 01 06:20:06 PM PDT 24
Finished	Aug 01 06:20:07 PM PDT 24
Peak memory	206908 kb
Host	smart-45d25bed-4fbd-4b6f-a3eb-fd8b80cfe0ef
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=222712690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.222712690
Directory	/workspace/122.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/56.usbdev_endpoint_types.775462159
Short name	T388
Test name
Test status
Simulation time	694591742 ps
CPU time	1.75 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206896 kb
Host	smart-1e14eb33-e435-4bd3-bb16-c894eeda5253
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=775462159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.775462159
Directory	/workspace/56.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/15.usbdev_endpoint_types.2600211244
Short name	T345
Test name
Test status
Simulation time	993739998 ps
CPU time	1.91 seconds
Started	Aug 01 06:14:14 PM PDT 24
Finished	Aug 01 06:14:16 PM PDT 24
Peak memory	206896 kb
Host	smart-eb314687-c8fe-436e-8993-a0f5476a1b7c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2600211244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.2600211244
Directory	/workspace/15.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/163.usbdev_endpoint_types.1119873487
Short name	T338
Test name
Test status
Simulation time	642053536 ps
CPU time	1.67 seconds
Started	Aug 01 06:20:15 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	206880 kb
Host	smart-11201cf4-dde3-446a-9cfe-0fbb6126eb00
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1119873487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.1119873487
Directory	/workspace/163.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/30.usbdev_endpoint_types.4101342363
Short name	T356
Test name
Test status
Simulation time	761587162 ps
CPU time	1.8 seconds
Started	Aug 01 06:16:49 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206920 kb
Host	smart-e163522a-9c6a-40ec-81a9-0a72c62f18fa
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4101342363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.4101342363
Directory	/workspace/30.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/2.usbdev_setup_priority.3072993452
Short name	T36
Test name
Test status
Simulation time	384278403 ps
CPU time	1.32 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	206944 kb
Host	smart-61bf365c-4bbd-4bc5-8e76-50322b62d738
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30729 93452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3072993452
Directory	/workspace/2.usbdev_setup_priority/latest

Test location	/workspace/coverage/default/4.usbdev_stress_usb_traffic.1853508497
Short name	T66
Test name
Test status
Simulation time	12552932365 ps
CPU time	267.77 seconds
Started	Aug 01 06:12:08 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	215348 kb
Host	smart-8eae44fe-87e5-46d3-b4f5-cd71f625569a
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad _crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853508497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1853508497
Directory	/workspace/4.usbdev_stress_usb_traffic/latest

Test location	/workspace/coverage/default/139.usbdev_endpoint_types.1329939884
Short name	T400
Test name
Test status
Simulation time	590709675 ps
CPU time	1.62 seconds
Started	Aug 01 06:20:01 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206896 kb
Host	smart-6d2b70b2-84a7-4696-93a6-fa4a7bd35265
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1329939884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.1329939884
Directory	/workspace/139.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/2.usbdev_endpoint_types.3901025941
Short name	T320
Test name
Test status
Simulation time	523515072 ps
CPU time	1.57 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:11:24 PM PDT 24
Peak memory	206900 kb
Host	smart-eea862f1-af14-4bd2-9be8-768a2c976455
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3901025941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.3901025941
Directory	/workspace/2.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/46.usbdev_endpoint_types.714411352
Short name	T2280
Test name
Test status
Simulation time	632035745 ps
CPU time	1.68 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:46 PM PDT 24
Peak memory	206916 kb
Host	smart-82bdd099-66cc-4ff8-85ba-19c47eeb1733
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=714411352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.714411352
Directory	/workspace/46.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/16.usbdev_low_speed_traffic.2698813326
Short name	T204
Test name
Test status
Simulation time	4732155231 ps
CPU time	136.54 seconds
Started	Aug 01 06:14:33 PM PDT 24
Finished	Aug 01 06:16:49 PM PDT 24
Peak memory	215372 kb
Host	smart-bcffe6ad-74e2-4d9f-9b74-f8ab5cc583b6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26988 13326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2698813326
Directory	/workspace/16.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/109.usbdev_endpoint_types.3362725392
Short name	T2483
Test name
Test status
Simulation time	493513852 ps
CPU time	1.46 seconds
Started	Aug 01 06:20:07 PM PDT 24
Finished	Aug 01 06:20:09 PM PDT 24
Peak memory	206920 kb
Host	smart-99ca5913-799b-40df-83e7-a06cd9a1419f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3362725392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.3362725392
Directory	/workspace/109.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/135.usbdev_endpoint_types.1488782354
Short name	T323
Test name
Test status
Simulation time	752056651 ps
CPU time	1.93 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206900 kb
Host	smart-47d0193f-9f59-43ff-b478-0e6a1c72181f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1488782354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.1488782354
Directory	/workspace/135.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/180.usbdev_endpoint_types.172494380
Short name	T327
Test name
Test status
Simulation time	683705160 ps
CPU time	1.71 seconds
Started	Aug 01 06:20:28 PM PDT 24
Finished	Aug 01 06:20:30 PM PDT 24
Peak memory	206976 kb
Host	smart-549fa476-8e6d-4e95-aebf-99ae11293e42
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=172494380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.172494380
Directory	/workspace/180.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/44.usbdev_endpoint_types.534670481
Short name	T432
Test name
Test status
Simulation time	749248329 ps
CPU time	1.71 seconds
Started	Aug 01 06:19:00 PM PDT 24
Finished	Aug 01 06:19:02 PM PDT 24
Peak memory	206956 kb
Host	smart-ec92bd4c-dfef-47c8-b3f7-200c670fd40b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=534670481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.534670481
Directory	/workspace/44.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/8.usbdev_rand_bus_resets.3442070980
Short name	T209
Test name
Test status
Simulation time	5183091654 ps
CPU time	44.91 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:54 PM PDT 24
Peak memory	218488 kb
Host	smart-142e08b4-0add-431b-a108-eedd223b1747
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442070980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.3442070980
Directory	/workspace/8.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/16.usbdev_alert_test.2801648209
Short name	T595
Test name
Test status
Simulation time	56696829 ps
CPU time	0.69 seconds
Started	Aug 01 06:14:47 PM PDT 24
Finished	Aug 01 06:14:47 PM PDT 24
Peak memory	206952 kb
Host	smart-9f2dccf1-1d1e-4bf8-a616-f2508520a0e7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2801648209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2801648209
Directory	/workspace/16.usbdev_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2038830682
Short name	T443
Test name
Test status
Simulation time	1104869622 ps
CPU time	4.59 seconds
Started	Aug 01 05:44:20 PM PDT 24
Finished	Aug 01 05:44:25 PM PDT 24
Peak memory	206688 kb
Host	smart-99f88057-ff58-4b9e-89be-5278b0c4fec3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2038830682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2038830682
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/0.usbdev_pkt_received.3731836481
Short name	T145
Test name
Test status
Simulation time	171509822 ps
CPU time	0.93 seconds
Started	Aug 01 06:10:52 PM PDT 24
Finished	Aug 01 06:10:53 PM PDT 24
Peak memory	206944 kb
Host	smart-c8e1a64a-75f5-4928-aa97-0a1aa21572de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37318 36481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.3731836481
Directory	/workspace/0.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/107.usbdev_endpoint_types.2117458745
Short name	T362
Test name
Test status
Simulation time	646745091 ps
CPU time	1.46 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206912 kb
Host	smart-179eec86-6b5c-4f66-8b77-36c43b59008b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2117458745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.2117458745
Directory	/workspace/107.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/148.usbdev_endpoint_types.2259144816
Short name	T414
Test name
Test status
Simulation time	519406588 ps
CPU time	1.61 seconds
Started	Aug 01 06:20:22 PM PDT 24
Finished	Aug 01 06:20:24 PM PDT 24
Peak memory	206880 kb
Host	smart-4c508a0a-031e-4a98-8398-297bbf2bcf79
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2259144816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.2259144816
Directory	/workspace/148.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/169.usbdev_endpoint_types.2312502170
Short name	T384
Test name
Test status
Simulation time	637797739 ps
CPU time	1.61 seconds
Started	Aug 01 06:20:33 PM PDT 24
Finished	Aug 01 06:20:35 PM PDT 24
Peak memory	206896 kb
Host	smart-4b8d12b9-d5f9-42fa-9a1b-b80b1cd92f31
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2312502170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.2312502170
Directory	/workspace/169.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/174.usbdev_endpoint_types.4072317942
Short name	T374
Test name
Test status
Simulation time	536069758 ps
CPU time	1.59 seconds
Started	Aug 01 06:20:24 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206892 kb
Host	smart-9b145d7f-f3fc-451d-a164-51e4f20cc61d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4072317942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.4072317942
Directory	/workspace/174.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/31.usbdev_endpoint_types.1810452021
Short name	T407
Test name
Test status
Simulation time	587245298 ps
CPU time	1.57 seconds
Started	Aug 01 06:17:00 PM PDT 24
Finished	Aug 01 06:17:02 PM PDT 24
Peak memory	206924 kb
Host	smart-ac09da4d-e050-4db2-904b-52ad72c637d5
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1810452021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.1810452021
Directory	/workspace/31.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/4.usbdev_freq_loclk.262020326
Short name	T70
Test name
Test status
Simulation time	113136129743 ps
CPU time	182.21 seconds
Started	Aug 01 06:11:43 PM PDT 24
Finished	Aug 01 06:14:46 PM PDT 24
Peak memory	207212 kb
Host	smart-3ab9e727-98b0-453b-86b0-32f0fecb4510
User	root
Command	/workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=262020326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.262020326
Directory	/workspace/4.usbdev_freq_loclk/latest

Test location	/workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.449686906
Short name	T54
Test name
Test status
Simulation time	463070168 ps
CPU time	1.34 seconds
Started	Aug 01 06:10:38 PM PDT 24
Finished	Aug 01 06:10:40 PM PDT 24
Peak memory	206956 kb
Host	smart-f4bc23bc-de0d-40b4-829f-35daeaa1ae61
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44968 6906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.449686906
Directory	/workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3214395470
Short name	T133
Test name
Test status
Simulation time	106194658 ps
CPU time	0.91 seconds
Started	Aug 01 05:43:43 PM PDT 24
Finished	Aug 01 05:43:44 PM PDT 24
Peak memory	206652 kb
Host	smart-26c66208-0d91-46bc-a4d4-6d1aeb202a9c
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3214395470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3214395470
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.2977665445
Short name	T242
Test name
Test status
Simulation time	721268480 ps
CPU time	4.96 seconds
Started	Aug 01 05:44:31 PM PDT 24
Finished	Aug 01 05:44:36 PM PDT 24
Peak memory	206780 kb
Host	smart-cb81af00-3c8a-4e4d-8001-aef262a39b53
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2977665445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.2977665445
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.179588566
Short name	T105
Test name
Test status
Simulation time	144435179 ps
CPU time	3.29 seconds
Started	Aug 01 05:43:46 PM PDT 24
Finished	Aug 01 05:43:49 PM PDT 24
Peak memory	206808 kb
Host	smart-ce41c59e-6328-4372-be0f-23845d056170
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=179588566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.179588566
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/default/0.usbdev_av_overflow.3424669869
Short name	T46
Test name
Test status
Simulation time	150643405 ps
CPU time	0.86 seconds
Started	Aug 01 06:10:38 PM PDT 24
Finished	Aug 01 06:10:39 PM PDT 24
Peak memory	206896 kb
Host	smart-b1a5caf1-b45b-4204-bcc3-422e2fcf9720
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34246 69869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3424669869
Directory	/workspace/0.usbdev_av_overflow/latest

Test location	/workspace/coverage/default/24.usbdev_invalid_sync.4000886635
Short name	T153
Test name
Test status
Simulation time	3234474281 ps
CPU time	31.33 seconds
Started	Aug 01 06:15:51 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	217700 kb
Host	smart-793cd076-893d-424c-934d-5213efe5771f
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4000886635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.4000886635
Directory	/workspace/24.usbdev_invalid_sync/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.4249073860
Short name	T135
Test name
Test status
Simulation time	43742266 ps
CPU time	0.72 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:39 PM PDT 24
Peak memory	206432 kb
Host	smart-14c3acb8-9ac4-4a2b-a0af-772a8bcff653
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4249073860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.4249073860
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/default/147.usbdev_endpoint_types.1466689534
Short name	T416
Test name
Test status
Simulation time	616673651 ps
CPU time	1.73 seconds
Started	Aug 01 06:20:18 PM PDT 24
Finished	Aug 01 06:20:20 PM PDT 24
Peak memory	206876 kb
Host	smart-aa1ec98d-f0b4-4987-99fb-90dd7ee1c02e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1466689534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.1466689534
Directory	/workspace/147.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/158.usbdev_endpoint_types.3513946098
Short name	T355
Test name
Test status
Simulation time	508239377 ps
CPU time	1.37 seconds
Started	Aug 01 06:20:09 PM PDT 24
Finished	Aug 01 06:20:10 PM PDT 24
Peak memory	206928 kb
Host	smart-ced5f8f7-cb5d-4b0c-97ec-d1598cf3f6ff
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3513946098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.3513946098
Directory	/workspace/158.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/162.usbdev_endpoint_types.2410565731
Short name	T359
Test name
Test status
Simulation time	286352927 ps
CPU time	1.13 seconds
Started	Aug 01 06:20:32 PM PDT 24
Finished	Aug 01 06:20:34 PM PDT 24
Peak memory	206872 kb
Host	smart-43d39ab7-42ab-42ca-8d9e-b43bf1a5844a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2410565731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.2410565731
Directory	/workspace/162.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/166.usbdev_endpoint_types.172344721
Short name	T294
Test name
Test status
Simulation time	701035017 ps
CPU time	1.81 seconds
Started	Aug 01 06:20:22 PM PDT 24
Finished	Aug 01 06:20:23 PM PDT 24
Peak memory	206932 kb
Host	smart-554d6cb0-31fb-4afa-824e-3a7c0b04ac0c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=172344721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.172344721
Directory	/workspace/166.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/171.usbdev_endpoint_types.3537650200
Short name	T309
Test name
Test status
Simulation time	650386150 ps
CPU time	1.57 seconds
Started	Aug 01 06:20:23 PM PDT 24
Finished	Aug 01 06:20:24 PM PDT 24
Peak memory	206940 kb
Host	smart-63764daa-9998-4852-8bde-826c6e0ccc48
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3537650200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.3537650200
Directory	/workspace/171.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/178.usbdev_endpoint_types.1483071862
Short name	T365
Test name
Test status
Simulation time	477254250 ps
CPU time	1.23 seconds
Started	Aug 01 06:20:19 PM PDT 24
Finished	Aug 01 06:20:21 PM PDT 24
Peak memory	206932 kb
Host	smart-fa663d09-47d6-49e7-b0eb-6a066398575f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1483071862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.1483071862
Directory	/workspace/178.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/1.usbdev_stress_usb_traffic.3526089811
Short name	T72
Test name
Test status
Simulation time	9223946233 ps
CPU time	55.24 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:12:17 PM PDT 24
Peak memory	219272 kb
Host	smart-b05c7e79-b1bb-4655-9fcd-8b6b6acdefe8
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad _crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526089811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.3526089811
Directory	/workspace/1.usbdev_stress_usb_traffic/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.2584940509
Short name	T2955
Test name
Test status
Simulation time	358854322 ps
CPU time	4.53 seconds
Started	Aug 01 05:44:01 PM PDT 24
Finished	Aug 01 05:44:06 PM PDT 24
Peak memory	215072 kb
Host	smart-1a3c1f5b-d68f-4b17-b24e-019bae44b3a9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2584940509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.2584940509
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/default/49.usbdev_phy_pins_sense.3470722675
Short name	T9
Test name
Test status
Simulation time	58579931 ps
CPU time	0.75 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206948 kb
Host	smart-9c2c021b-28ac-48b9-9fd7-7694aad1848b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34707 22675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3470722675
Directory	/workspace/49.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.866340748
Short name	T127
Test name
Test status
Simulation time	66918795 ps
CPU time	0.92 seconds
Started	Aug 01 05:44:01 PM PDT 24
Finished	Aug 01 05:44:02 PM PDT 24
Peak memory	206552 kb
Host	smart-764361a4-785a-4a67-847f-45dce1fb7a34
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=866340748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.866340748
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3516567896
Short name	T110
Test name
Test status
Simulation time	319485412 ps
CPU time	2.69 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:41 PM PDT 24
Peak memory	206744 kb
Host	smart-8f45b7ae-9bc2-453a-ae1b-af6a44f21dca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3516567896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3516567896
Directory	/workspace/16.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/0.usbdev_dpi_config_host.516908374
Short name	T470
Test name
Test status
Simulation time	5109210703 ps
CPU time	146.89 seconds
Started	Aug 01 06:10:39 PM PDT 24
Finished	Aug 01 06:13:06 PM PDT 24
Peak memory	207112 kb
Host	smart-c2863bf4-9075-410d-8c29-e68efa2567e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51690 8374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.516908374
Directory	/workspace/0.usbdev_dpi_config_host/latest

Test location	/workspace/coverage/default/0.usbdev_freq_loclk.3581946671
Short name	T472
Test name
Test status
Simulation time	81107137335 ps
CPU time	131.83 seconds
Started	Aug 01 06:10:36 PM PDT 24
Finished	Aug 01 06:12:47 PM PDT 24
Peak memory	207208 kb
Host	smart-a6044a65-174b-4824-8ba6-01372de3ec27
User	root
Command	/workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3581946671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3581946671
Directory	/workspace/0.usbdev_freq_loclk/latest

Test location	/workspace/coverage/default/0.usbdev_rx_full.3110866504
Short name	T2644
Test name
Test status
Simulation time	361726531 ps
CPU time	1.33 seconds
Started	Aug 01 06:10:47 PM PDT 24
Finished	Aug 01 06:10:48 PM PDT 24
Peak memory	206952 kb
Host	smart-ef91998b-bf34-45da-b18e-ae6ffc06d98f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31108 66504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.3110866504
Directory	/workspace/0.usbdev_rx_full/latest

Test location	/workspace/coverage/default/10.usbdev_rx_full.2911171149
Short name	T2581
Test name
Test status
Simulation time	266224447 ps
CPU time	1.15 seconds
Started	Aug 01 06:13:31 PM PDT 24
Finished	Aug 01 06:13:32 PM PDT 24
Peak memory	206948 kb
Host	smart-bfb2233e-517f-4236-b6fd-b01cec59e04c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29111 71149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.2911171149
Directory	/workspace/10.usbdev_rx_full/latest

Test location	/workspace/coverage/default/120.usbdev_endpoint_types.2232617296
Short name	T2680
Test name
Test status
Simulation time	421847566 ps
CPU time	1.28 seconds
Started	Aug 01 06:20:12 PM PDT 24
Finished	Aug 01 06:20:13 PM PDT 24
Peak memory	206912 kb
Host	smart-064d27e0-6716-4377-96fb-a7aee632d293
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2232617296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.2232617296
Directory	/workspace/120.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/13.usbdev_setup_trans_ignored.2288558051
Short name	T909
Test name
Test status
Simulation time	170956906 ps
CPU time	0.89 seconds
Started	Aug 01 06:14:02 PM PDT 24
Finished	Aug 01 06:14:03 PM PDT 24
Peak memory	206952 kb
Host	smart-5fbc8804-c83b-4163-9815-dbea0a4efa87
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22885 58051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.2288558051
Directory	/workspace/13.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/131.usbdev_endpoint_types.3739642921
Short name	T433
Test name
Test status
Simulation time	350553572 ps
CPU time	1.13 seconds
Started	Aug 01 06:20:19 PM PDT 24
Finished	Aug 01 06:20:20 PM PDT 24
Peak memory	206832 kb
Host	smart-555a719e-2c25-4afe-bd29-a137a5896c1f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3739642921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.3739642921
Directory	/workspace/131.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/140.usbdev_endpoint_types.934082868
Short name	T440
Test name
Test status
Simulation time	252965646 ps
CPU time	0.99 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:01 PM PDT 24
Peak memory	206940 kb
Host	smart-6f4f67de-d7cc-47ad-ba99-eafdf9309ecd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=934082868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.934082868
Directory	/workspace/140.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/152.usbdev_endpoint_types.979318423
Short name	T2113
Test name
Test status
Simulation time	704609496 ps
CPU time	1.66 seconds
Started	Aug 01 06:20:22 PM PDT 24
Finished	Aug 01 06:20:24 PM PDT 24
Peak memory	206916 kb
Host	smart-ab719b4b-46cb-4337-a7ae-6f604e31a3dd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=979318423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.979318423
Directory	/workspace/152.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/16.usbdev_stall_priority_over_nak.1820459403
Short name	T792
Test name
Test status
Simulation time	208351721 ps
CPU time	0.95 seconds
Started	Aug 01 06:14:31 PM PDT 24
Finished	Aug 01 06:14:32 PM PDT 24
Peak memory	206960 kb
Host	smart-ab19ded4-0304-4c8a-b33a-f0cc11cd4694
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18204 59403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1820459403
Directory	/workspace/16.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/167.usbdev_endpoint_types.4193192363
Short name	T406
Test name
Test status
Simulation time	334013467 ps
CPU time	1.15 seconds
Started	Aug 01 06:20:24 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206932 kb
Host	smart-9d6c1211-01b2-40c0-b438-84c5eabc1ed8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4193192363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.4193192363
Directory	/workspace/167.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/186.usbdev_endpoint_types.171406844
Short name	T343
Test name
Test status
Simulation time	499420150 ps
CPU time	1.42 seconds
Started	Aug 01 06:20:24 PM PDT 24
Finished	Aug 01 06:20:25 PM PDT 24
Peak memory	206852 kb
Host	smart-8da17de8-c196-4c4f-a77e-559c20f81d46
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=171406844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.171406844
Directory	/workspace/186.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/24.usbdev_spurious_pids_ignored.3290724991
Short name	T462
Test name
Test status
Simulation time	3756475067 ps
CPU time	30.56 seconds
Started	Aug 01 06:15:59 PM PDT 24
Finished	Aug 01 06:16:30 PM PDT 24
Peak memory	207168 kb
Host	smart-fe23344b-d1b6-49d8-a1ce-1928e8eebbff
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3290724991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3290724991
Directory	/workspace/24.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/25.usbdev_low_speed_traffic.3174388048
Short name	T2003
Test name
Test status
Simulation time	2993051254 ps
CPU time	29.5 seconds
Started	Aug 01 06:16:06 PM PDT 24
Finished	Aug 01 06:16:35 PM PDT 24
Peak memory	223516 kb
Host	smart-41e1f241-b409-4f6d-a37d-4f69308ab298
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31743 88048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3174388048
Directory	/workspace/25.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/3.usbdev_freq_phase.2707740697
Short name	T465
Test name
Test status
Simulation time	91170421828 ps
CPU time	146.47 seconds
Started	Aug 01 06:11:30 PM PDT 24
Finished	Aug 01 06:13:56 PM PDT 24
Peak memory	207148 kb
Host	smart-d16997be-b2d9-49ea-b3cf-0c745020bf15
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27077 40697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2707740697
Directory	/workspace/3.usbdev_freq_phase/latest

Test location	/workspace/coverage/default/96.usbdev_endpoint_types.4083829491
Short name	T437
Test name
Test status
Simulation time	782279824 ps
CPU time	1.85 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206940 kb
Host	smart-dbb8eb3c-a90c-4b46-9efc-4a294ceb9bfd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4083829491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.4083829491
Directory	/workspace/96.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2818160038
Short name	T705
Test name
Test status
Simulation time	134999003 ps
CPU time	0.78 seconds
Started	Aug 01 06:10:44 PM PDT 24
Finished	Aug 01 06:10:45 PM PDT 24
Peak memory	206928 kb
Host	smart-c57e23c1-52a5-4ae4-abac-5dac3de37f9f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28181 60038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2818160038
Directory	/workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/14.usbdev_nak_trans.4081644439
Short name	T198
Test name
Test status
Simulation time	197877242 ps
CPU time	0.94 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:17 PM PDT 24
Peak memory	206964 kb
Host	smart-dc1536cf-6594-4681-8e2a-95824741e6ce
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40816 44439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.4081644439
Directory	/workspace/14.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/9.usbdev_rand_bus_resets.2728002360
Short name	T214
Test name
Test status
Simulation time	3642574150 ps
CPU time	23.52 seconds
Started	Aug 01 06:13:10 PM PDT 24
Finished	Aug 01 06:13:34 PM PDT 24
Peak memory	215404 kb
Host	smart-92eb4ad9-a892-4e62-8c79-ca645f5f0b22
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728002360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2728002360
Directory	/workspace/9.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/0.usbdev_av_empty.3636944005
Short name	T43
Test name
Test status
Simulation time	161331990 ps
CPU time	0.82 seconds
Started	Aug 01 06:10:43 PM PDT 24
Finished	Aug 01 06:10:44 PM PDT 24
Peak memory	206944 kb
Host	smart-c002f084-4909-477a-912d-a1a8c97e2d1e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36369 44005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3636944005
Directory	/workspace/0.usbdev_av_empty/latest

Test location	/workspace/coverage/default/0.usbdev_host_lost.4172714727
Short name	T51
Test name
Test status
Simulation time	4159090592 ps
CPU time	10.06 seconds
Started	Aug 01 06:10:36 PM PDT 24
Finished	Aug 01 06:10:47 PM PDT 24
Peak memory	207200 kb
Host	smart-465e8779-8983-477d-bcd7-55416081cc9a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41727 14727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.4172714727
Directory	/workspace/0.usbdev_host_lost/latest

Test location	/workspace/coverage/default/0.usbdev_link_reset.782571264
Short name	T52
Test name
Test status
Simulation time	169223619 ps
CPU time	0.88 seconds
Started	Aug 01 06:10:44 PM PDT 24
Finished	Aug 01 06:10:45 PM PDT 24
Peak memory	206928 kb
Host	smart-ebd9f8f4-0df4-49e5-b4d6-88fd7d4acd51
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78257 1264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.782571264
Directory	/workspace/0.usbdev_link_reset/latest

Test location	/workspace/coverage/default/0.usbdev_rx_pid_err.2960505688
Short name	T2605
Test name
Test status
Simulation time	176959629 ps
CPU time	0.88 seconds
Started	Aug 01 06:10:54 PM PDT 24
Finished	Aug 01 06:10:55 PM PDT 24
Peak memory	206972 kb
Host	smart-f0c34d07-4754-4b85-872f-432baaf4d154
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29605 05688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2960505688
Directory	/workspace/0.usbdev_rx_pid_err/latest

Test location	/workspace/coverage/default/1.usbdev_av_empty.3125955709
Short name	T35
Test name
Test status
Simulation time	171356241 ps
CPU time	0.85 seconds
Started	Aug 01 06:10:51 PM PDT 24
Finished	Aug 01 06:10:52 PM PDT 24
Peak memory	206960 kb
Host	smart-366a7d5e-be79-492f-835f-a4806be334e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31259 55709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.3125955709
Directory	/workspace/1.usbdev_av_empty/latest

Test location	/workspace/coverage/default/0.usbdev_nak_trans.1162370851
Short name	T2188
Test name
Test status
Simulation time	208975816 ps
CPU time	0.94 seconds
Started	Aug 01 06:10:51 PM PDT 24
Finished	Aug 01 06:10:52 PM PDT 24
Peak memory	206952 kb
Host	smart-fd976a4d-637f-45ee-ad38-0000635044cd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11623 70851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1162370851
Directory	/workspace/0.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.4210356403
Short name	T218
Test name
Test status
Simulation time	170257106 ps
CPU time	0.86 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:10:49 PM PDT 24
Peak memory	206956 kb
Host	smart-d488bc5f-eeab-4ec3-9106-1bd5e2753fca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42103 56403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.4210356403
Directory	/workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location	/workspace/coverage/default/1.usbdev_device_timeout.437348354
Short name	T552
Test name
Test status
Simulation time	3800313984 ps
CPU time	25.29 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:11:30 PM PDT 24
Peak memory	207164 kb
Host	smart-ee562f64-267e-4692-8279-3f01530eb2da
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437348354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.437348354
Directory	/workspace/1.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/1.usbdev_nak_trans.1373727855
Short name	T2305
Test name
Test status
Simulation time	229747411 ps
CPU time	1 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:05 PM PDT 24
Peak memory	206948 kb
Host	smart-a0611511-6034-4ccd-af06-e0801698a7cd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13737 27855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1373727855
Directory	/workspace/1.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/10.usbdev_nak_trans.2920656806
Short name	T182
Test name
Test status
Simulation time	190830379 ps
CPU time	0.95 seconds
Started	Aug 01 06:13:23 PM PDT 24
Finished	Aug 01 06:13:24 PM PDT 24
Peak memory	206980 kb
Host	smart-820e4407-f00c-4b3f-82c9-40b19d75ed21
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29206 56806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2920656806
Directory	/workspace/10.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/11.usbdev_nak_trans.2905335980
Short name	T189
Test name
Test status
Simulation time	183506673 ps
CPU time	0.93 seconds
Started	Aug 01 06:13:40 PM PDT 24
Finished	Aug 01 06:13:42 PM PDT 24
Peak memory	206944 kb
Host	smart-4b269d8c-1ed6-41af-bbc0-20c25ee992d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29053 35980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2905335980
Directory	/workspace/11.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/12.usbdev_nak_trans.1111850132
Short name	T2577
Test name
Test status
Simulation time	202659777 ps
CPU time	0.97 seconds
Started	Aug 01 06:13:45 PM PDT 24
Finished	Aug 01 06:13:46 PM PDT 24
Peak memory	206932 kb
Host	smart-ec2e6aad-f554-4378-a88c-dacdf3fc62b5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11118 50132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1111850132
Directory	/workspace/12.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/13.usbdev_fifo_rst.4276192270
Short name	T550
Test name
Test status
Simulation time	371731358 ps
CPU time	2.8 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	207368 kb
Host	smart-3ec0d99e-bbd0-4734-8c1c-7f746e7d046b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42761 92270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.4276192270
Directory	/workspace/13.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/15.usbdev_device_address.2383967625
Short name	T213
Test name
Test status
Simulation time	51870621402 ps
CPU time	82.91 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:15:40 PM PDT 24
Peak memory	207188 kb
Host	smart-47dabef2-2a67-4f87-86a0-ac7314dd07ec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23839 67625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2383967625
Directory	/workspace/15.usbdev_device_address/latest

Test location	/workspace/coverage/default/15.usbdev_nak_trans.2801011465
Short name	T2313
Test name
Test status
Simulation time	282763371 ps
CPU time	1.12 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	206956 kb
Host	smart-8c109cfe-df7d-41d2-947f-db8d832fc5aa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28010 11465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.2801011465
Directory	/workspace/15.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/2.usbdev_stress_usb_traffic.1439184371
Short name	T67
Test name
Test status
Simulation time	9156364774 ps
CPU time	248.99 seconds
Started	Aug 01 06:11:31 PM PDT 24
Finished	Aug 01 06:15:40 PM PDT 24
Peak memory	217824 kb
Host	smart-2af32b22-d663-4639-8d68-cf2690703560
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad _crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439184371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1439184371
Directory	/workspace/2.usbdev_stress_usb_traffic/latest

Test location	/workspace/coverage/default/20.usbdev_nak_trans.2809411647
Short name	T187
Test name
Test status
Simulation time	212948243 ps
CPU time	0.89 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	206912 kb
Host	smart-31a6f0ff-5ee7-475e-9894-8961afc4c52b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28094 11647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2809411647
Directory	/workspace/20.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/21.usbdev_nak_trans.935013498
Short name	T193
Test name
Test status
Simulation time	205223171 ps
CPU time	1 seconds
Started	Aug 01 06:15:34 PM PDT 24
Finished	Aug 01 06:15:35 PM PDT 24
Peak memory	206952 kb
Host	smart-8eeb49a8-2c1c-4ae6-ae3b-3bae4a6177a2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93501 3498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.935013498
Directory	/workspace/21.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/24.usbdev_nak_trans.365310790
Short name	T173
Test name
Test status
Simulation time	243027117 ps
CPU time	1.02 seconds
Started	Aug 01 06:15:59 PM PDT 24
Finished	Aug 01 06:16:00 PM PDT 24
Peak memory	206968 kb
Host	smart-2c2e1e8d-bc48-4a8b-9b74-714eee8c0407
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36531 0790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.365310790
Directory	/workspace/24.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/25.usbdev_nak_trans.3022582729
Short name	T172
Test name
Test status
Simulation time	218703145 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:05 PM PDT 24
Finished	Aug 01 06:16:06 PM PDT 24
Peak memory	206952 kb
Host	smart-956e1d81-f509-4926-bb36-f1fbc2f30b29
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30225 82729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3022582729
Directory	/workspace/25.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/27.usbdev_endpoint_types.863926054
Short name	T77
Test name
Test status
Simulation time	877451742 ps
CPU time	1.98 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:25 PM PDT 24
Peak memory	206952 kb
Host	smart-57005ef6-58bd-4e2f-962d-2cf908cb138a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=863926054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.863926054
Directory	/workspace/27.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/4.usbdev_rand_bus_disconnects.3803720391
Short name	T223
Test name
Test status
Simulation time	4056626556 ps
CPU time	26.13 seconds
Started	Aug 01 06:12:01 PM PDT 24
Finished	Aug 01 06:12:27 PM PDT 24
Peak memory	223496 kb
Host	smart-d33e430e-d2da-424e-bacc-835a9253a962
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803720391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3803720391
Directory	/workspace/4.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/42.usbdev_nak_trans.1477108529
Short name	T197
Test name
Test status
Simulation time	202823078 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206956 kb
Host	smart-bc1e31d2-947c-4d1b-b0e0-cd20c1eb887b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14771 08529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1477108529
Directory	/workspace/42.usbdev_nak_trans/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3998079075
Short name	T259
Test name
Test status
Simulation time	773659487 ps
CPU time	4.9 seconds
Started	Aug 01 05:43:43 PM PDT 24
Finished	Aug 01 05:43:48 PM PDT 24
Peak memory	206876 kb
Host	smart-43b0b6ab-4d43-4a95-a9d3-067550fd697b
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3998079075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3998079075
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2695535468
Short name	T2981
Test name
Test status
Simulation time	166262790 ps
CPU time	2.6 seconds
Started	Aug 01 05:43:45 PM PDT 24
Finished	Aug 01 05:43:48 PM PDT 24
Peak memory	215012 kb
Host	smart-c6546818-a55f-463b-995f-ced69c68da99
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695535468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde v_csr_mem_rw_with_rand_reset.2695535468
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1899826002
Short name	T108
Test name
Test status
Simulation time	115572004 ps
CPU time	1.09 seconds
Started	Aug 01 05:43:42 PM PDT 24
Finished	Aug 01 05:43:43 PM PDT 24
Peak memory	206604 kb
Host	smart-ab714a93-bd9e-4947-a773-40438d8695f6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1899826002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1899826002
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1909091241
Short name	T3004
Test name
Test status
Simulation time	60655093 ps
CPU time	0.72 seconds
Started	Aug 01 05:43:45 PM PDT 24
Finished	Aug 01 05:43:46 PM PDT 24
Peak memory	206448 kb
Host	smart-12bcce6f-764f-440c-90c5-c0124782ed08
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1909091241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1909091241
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2701930332
Short name	T260
Test name
Test status
Simulation time	59691851 ps
CPU time	1.32 seconds
Started	Aug 01 05:43:46 PM PDT 24
Finished	Aug 01 05:43:48 PM PDT 24
Peak memory	206732 kb
Host	smart-779dcb7f-2b06-47c2-b0c1-d479df3d274c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2701930332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2701930332
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.368405274
Short name	T2906
Test name
Test status
Simulation time	337142940 ps
CPU time	2.72 seconds
Started	Aug 01 05:43:43 PM PDT 24
Finished	Aug 01 05:43:46 PM PDT 24
Peak memory	206684 kb
Host	smart-26146ce8-cec9-4a2b-b199-0218fc5e8464
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=368405274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.368405274
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1135280346
Short name	T3010
Test name
Test status
Simulation time	211029188 ps
CPU time	1.59 seconds
Started	Aug 01 05:43:45 PM PDT 24
Finished	Aug 01 05:43:47 PM PDT 24
Peak memory	206708 kb
Host	smart-c73be135-36cc-4e53-ba83-edea431b5f20
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1135280346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1135280346
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2094744007
Short name	T2908
Test name
Test status
Simulation time	125349803 ps
CPU time	1.62 seconds
Started	Aug 01 05:43:40 PM PDT 24
Finished	Aug 01 05:43:42 PM PDT 24
Peak memory	206684 kb
Host	smart-c63e6866-4928-4138-a923-e764ff43d72c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2094744007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2094744007
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.183918296
Short name	T275
Test name
Test status
Simulation time	584674043 ps
CPU time	3.06 seconds
Started	Aug 01 05:43:44 PM PDT 24
Finished	Aug 01 05:43:47 PM PDT 24
Peak memory	206780 kb
Host	smart-185c001b-aad0-4fd8-bf20-06f603681638
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=183918296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.183918296
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2405660480
Short name	T2985
Test name
Test status
Simulation time	102496310 ps
CPU time	2 seconds
Started	Aug 01 05:44:27 PM PDT 24
Finished	Aug 01 05:44:29 PM PDT 24
Peak memory	206864 kb
Host	smart-295db353-03c9-4dad-a5bb-c788bfdd24d7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2405660480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2405660480
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2855470025
Short name	T2989
Test name
Test status
Simulation time	274330118 ps
CPU time	4.5 seconds
Started	Aug 01 05:44:01 PM PDT 24
Finished	Aug 01 05:44:06 PM PDT 24
Peak memory	206740 kb
Host	smart-96fd2b96-df1e-4d33-a832-b0a21a4f0f93
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2855470025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2855470025
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1067733683
Short name	T2952
Test name
Test status
Simulation time	117400584 ps
CPU time	1.26 seconds
Started	Aug 01 05:44:01 PM PDT 24
Finished	Aug 01 05:44:02 PM PDT 24
Peak memory	214764 kb
Host	smart-bd6f66b9-bb8a-4811-9e87-5b8d61a459ea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067733683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde v_csr_mem_rw_with_rand_reset.1067733683
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.360836433
Short name	T261
Test name
Test status
Simulation time	151492356 ps
CPU time	1.15 seconds
Started	Aug 01 05:43:59 PM PDT 24
Finished	Aug 01 05:44:00 PM PDT 24
Peak memory	206496 kb
Host	smart-3b0fbc9c-9f89-4c94-ab9d-3073b1cfb091
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=360836433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.360836433
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.3727326052
Short name	T2995
Test name
Test status
Simulation time	54385256 ps
CPU time	0.76 seconds
Started	Aug 01 05:43:43 PM PDT 24
Finished	Aug 01 05:43:44 PM PDT 24
Peak memory	206472 kb
Host	smart-1911454d-3b1d-4b14-a2cf-631540905e32
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3727326052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3727326052
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2116177372
Short name	T255
Test name
Test status
Simulation time	118006164 ps
CPU time	1.47 seconds
Started	Aug 01 05:43:45 PM PDT 24
Finished	Aug 01 05:43:46 PM PDT 24
Peak memory	206708 kb
Host	smart-6b9ea559-a091-4fae-ab75-d890b5255935
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2116177372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2116177372
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3559392125
Short name	T2929
Test name
Test status
Simulation time	164973256 ps
CPU time	3.99 seconds
Started	Aug 01 05:43:44 PM PDT 24
Finished	Aug 01 05:43:48 PM PDT 24
Peak memory	206644 kb
Host	smart-c44a88c1-804c-40c2-9cb3-4a84957593c1
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3559392125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3559392125
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2964735093
Short name	T2914
Test name
Test status
Simulation time	274556587 ps
CPU time	1.63 seconds
Started	Aug 01 05:43:59 PM PDT 24
Finished	Aug 01 05:44:01 PM PDT 24
Peak memory	206868 kb
Host	smart-21ec63d5-068e-490d-938d-991e7d3d219c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2964735093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2964735093
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.95564114
Short name	T237
Test name
Test status
Simulation time	223729836 ps
CPU time	2.42 seconds
Started	Aug 01 05:43:41 PM PDT 24
Finished	Aug 01 05:43:44 PM PDT 24
Peak memory	206760 kb
Host	smart-be55b0c9-5b8f-4c02-8dc1-5e8ec622c43d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=95564114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.95564114
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3019214806
Short name	T444
Test name
Test status
Simulation time	901187698 ps
CPU time	5.38 seconds
Started	Aug 01 05:43:45 PM PDT 24
Finished	Aug 01 05:43:50 PM PDT 24
Peak memory	206812 kb
Host	smart-3ee2abde-2139-4b74-beff-4e69da3bdd33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3019214806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3019214806
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1539529934
Short name	T246
Test name
Test status
Simulation time	123642001 ps
CPU time	1.68 seconds
Started	Aug 01 05:44:29 PM PDT 24
Finished	Aug 01 05:44:31 PM PDT 24
Peak memory	223220 kb
Host	smart-560a7544-d97f-49a1-9e37-c085906064b1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539529934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd ev_csr_mem_rw_with_rand_reset.1539529934
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2732120457
Short name	T3002
Test name
Test status
Simulation time	75022202 ps
CPU time	1.05 seconds
Started	Aug 01 05:44:27 PM PDT 24
Finished	Aug 01 05:44:28 PM PDT 24
Peak memory	206584 kb
Host	smart-59ed649f-d5ea-4799-97b2-c2f479def770
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2732120457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2732120457
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.445569093
Short name	T2974
Test name
Test status
Simulation time	46738082 ps
CPU time	0.8 seconds
Started	Aug 01 05:45:48 PM PDT 24
Finished	Aug 01 05:45:49 PM PDT 24
Peak memory	206080 kb
Host	smart-e130bb87-c147-49f4-aafa-754a886de796
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=445569093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.445569093
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.46967755
Short name	T266
Test name
Test status
Simulation time	211982199 ps
CPU time	1.64 seconds
Started	Aug 01 05:45:48 PM PDT 24
Finished	Aug 01 05:45:50 PM PDT 24
Peak memory	205244 kb
Host	smart-2a869185-8d40-414f-a5e5-d3e931aaa234
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=46967755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.46967755
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1700851573
Short name	T241
Test name
Test status
Simulation time	148045272 ps
CPU time	2.11 seconds
Started	Aug 01 05:44:29 PM PDT 24
Finished	Aug 01 05:44:31 PM PDT 24
Peak memory	206860 kb
Host	smart-83f71912-264e-47f0-83e6-6621322fac92
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1700851573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1700851573
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1328105017
Short name	T100
Test name
Test status
Simulation time	833102305 ps
CPU time	4.63 seconds
Started	Aug 01 05:44:29 PM PDT 24
Finished	Aug 01 05:44:34 PM PDT 24
Peak memory	206732 kb
Host	smart-c0997818-9f75-4f4c-8d3e-5ba9a0fc0ceb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1328105017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1328105017
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1678229685
Short name	T109
Test name
Test status
Simulation time	109209740 ps
CPU time	1.11 seconds
Started	Aug 01 05:45:58 PM PDT 24
Finished	Aug 01 05:45:59 PM PDT 24
Peak memory	214640 kb
Host	smart-085d0b57-c779-4b6a-a60b-0daf7726bda3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678229685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.1678229685
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1724860923
Short name	T2924
Test name
Test status
Simulation time	43368698 ps
CPU time	0.97 seconds
Started	Aug 01 05:44:28 PM PDT 24
Finished	Aug 01 05:44:30 PM PDT 24
Peak memory	206440 kb
Host	smart-c8444990-7f09-4e12-b9ab-566fefd4d0b3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1724860923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1724860923
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.1950404986
Short name	T267
Test name
Test status
Simulation time	445374363 ps
CPU time	1.77 seconds
Started	Aug 01 05:45:47 PM PDT 24
Finished	Aug 01 05:45:50 PM PDT 24
Peak memory	203808 kb
Host	smart-5b2b9b45-a96c-4087-ba9e-a55d8d0bb065
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1950404986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.1950404986
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1990818694
Short name	T2998
Test name
Test status
Simulation time	163001612 ps
CPU time	2.2 seconds
Started	Aug 01 05:45:47 PM PDT 24
Finished	Aug 01 05:45:50 PM PDT 24
Peak memory	204004 kb
Host	smart-2f877163-bb8f-4375-9730-8189e575c038
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1990818694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1990818694
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.259515258
Short name	T3006
Test name
Test status
Simulation time	514390580 ps
CPU time	4.22 seconds
Started	Aug 01 05:44:32 PM PDT 24
Finished	Aug 01 05:44:37 PM PDT 24
Peak memory	206704 kb
Host	smart-f9553d22-8ae4-4aeb-b9aa-7a69e76c728e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=259515258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.259515258
Directory	/workspace/11.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3744564147
Short name	T2994
Test name
Test status
Simulation time	62846163 ps
CPU time	1.53 seconds
Started	Aug 01 05:44:30 PM PDT 24
Finished	Aug 01 05:44:32 PM PDT 24
Peak memory	214940 kb
Host	smart-77a04517-3a79-42c8-b146-c3d01cc4a1ee
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744564147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd ev_csr_mem_rw_with_rand_reset.3744564147
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3343160206
Short name	T258
Test name
Test status
Simulation time	57964457 ps
CPU time	0.96 seconds
Started	Aug 01 05:45:48 PM PDT 24
Finished	Aug 01 05:45:49 PM PDT 24
Peak memory	205092 kb
Host	smart-980d3ce8-7e7b-4d7a-9c8f-6fcf33049e6c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3343160206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3343160206
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1559068870
Short name	T2937
Test name
Test status
Simulation time	80849081 ps
CPU time	0.83 seconds
Started	Aug 01 05:45:47 PM PDT 24
Finished	Aug 01 05:45:49 PM PDT 24
Peak memory	203684 kb
Host	smart-43280412-f1c8-47c1-b2ad-b5d04c316130
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1559068870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1559068870
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1836019595
Short name	T2948
Test name
Test status
Simulation time	191551396 ps
CPU time	1.19 seconds
Started	Aug 01 05:44:28 PM PDT 24
Finished	Aug 01 05:44:30 PM PDT 24
Peak memory	206904 kb
Host	smart-90fa8b9d-f5e2-4327-96c1-6cca7bd3be02
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1836019595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1836019595
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.3688976687
Short name	T2935
Test name
Test status
Simulation time	85225320 ps
CPU time	2.3 seconds
Started	Aug 01 05:44:31 PM PDT 24
Finished	Aug 01 05:44:33 PM PDT 24
Peak memory	223132 kb
Host	smart-e67c1b87-d3b2-4198-8fee-4f9c729e6e9c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3688976687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.3688976687
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3948329160
Short name	T2982
Test name
Test status
Simulation time	104279319 ps
CPU time	1.26 seconds
Started	Aug 01 05:44:31 PM PDT 24
Finished	Aug 01 05:44:32 PM PDT 24
Peak memory	214988 kb
Host	smart-5eb1fd24-2eca-4622-8653-2f0587120dc0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948329160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.3948329160
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3849370026
Short name	T257
Test name
Test status
Simulation time	60166887 ps
CPU time	1.07 seconds
Started	Aug 01 05:45:47 PM PDT 24
Finished	Aug 01 05:45:49 PM PDT 24
Peak memory	203820 kb
Host	smart-302753e3-bc91-4452-a6ad-f3b17d271402
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3849370026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3849370026
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.141620395
Short name	T2947
Test name
Test status
Simulation time	48901485 ps
CPU time	0.68 seconds
Started	Aug 01 05:45:57 PM PDT 24
Finished	Aug 01 05:45:58 PM PDT 24
Peak memory	206404 kb
Host	smart-d1c54a16-272e-4628-9b3c-1d06dc22e99d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=141620395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.141620395
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3433242909
Short name	T2912
Test name
Test status
Simulation time	186236219 ps
CPU time	1.17 seconds
Started	Aug 01 05:45:47 PM PDT 24
Finished	Aug 01 05:45:49 PM PDT 24
Peak memory	203524 kb
Host	smart-3a2ecc9a-ab2b-49b8-a9d8-aac2bdd43e23
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3433242909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3433242909
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4115542143
Short name	T3013
Test name
Test status
Simulation time	202616810 ps
CPU time	2.34 seconds
Started	Aug 01 05:45:47 PM PDT 24
Finished	Aug 01 05:45:50 PM PDT 24
Peak memory	204740 kb
Host	smart-b5b8dede-cdeb-4893-9e88-bb2c080dca20
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4115542143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4115542143
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.2585455955
Short name	T447
Test name
Test status
Simulation time	637706374 ps
CPU time	4.12 seconds
Started	Aug 01 05:44:31 PM PDT 24
Finished	Aug 01 05:44:35 PM PDT 24
Peak memory	206816 kb
Host	smart-3c4f5e01-09e4-4a55-af9e-a33a3f9902c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2585455955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.2585455955
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.4063623448
Short name	T2944
Test name
Test status
Simulation time	111676941 ps
CPU time	1.27 seconds
Started	Aug 01 05:44:32 PM PDT 24
Finished	Aug 01 05:44:33 PM PDT 24
Peak memory	215020 kb
Host	smart-e69b424e-62dc-4f09-8db8-c9d3c8ecdc6b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063623448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd ev_csr_mem_rw_with_rand_reset.4063623448
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.4126964456
Short name	T2963
Test name
Test status
Simulation time	77978219 ps
CPU time	0.89 seconds
Started	Aug 01 05:44:33 PM PDT 24
Finished	Aug 01 05:44:34 PM PDT 24
Peak memory	206588 kb
Host	smart-3270b0af-1f30-44f7-8d6c-4e5e06dc6f46
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4126964456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.4126964456
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.1972426956
Short name	T3000
Test name
Test status
Simulation time	95678677 ps
CPU time	0.8 seconds
Started	Aug 01 05:44:34 PM PDT 24
Finished	Aug 01 05:44:35 PM PDT 24
Peak memory	206480 kb
Host	smart-5e60fe47-9d18-4faa-9785-5f88da8698f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1972426956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1972426956
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1876797390
Short name	T3012
Test name
Test status
Simulation time	87926020 ps
CPU time	1.46 seconds
Started	Aug 01 05:45:42 PM PDT 24
Finished	Aug 01 05:45:44 PM PDT 24
Peak memory	204488 kb
Host	smart-e5250567-26b8-47e8-a38e-5bfb1d892877
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1876797390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1876797390
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2882914344
Short name	T2932
Test name
Test status
Simulation time	194768411 ps
CPU time	1.62 seconds
Started	Aug 01 05:45:57 PM PDT 24
Finished	Aug 01 05:45:59 PM PDT 24
Peak memory	206724 kb
Host	smart-51d29cbe-7192-4e2b-9d70-51b9ef9e0cd3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2882914344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2882914344
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1962036457
Short name	T2943
Test name
Test status
Simulation time	103543315 ps
CPU time	1.75 seconds
Started	Aug 01 05:44:31 PM PDT 24
Finished	Aug 01 05:44:33 PM PDT 24
Peak memory	215056 kb
Host	smart-0dd9619d-7562-48a1-98ed-6ffbff094bea
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962036457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd ev_csr_mem_rw_with_rand_reset.1962036457
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3828599986
Short name	T3009
Test name
Test status
Simulation time	72972722 ps
CPU time	1.01 seconds
Started	Aug 01 05:45:42 PM PDT 24
Finished	Aug 01 05:45:44 PM PDT 24
Peak memory	204832 kb
Host	smart-1bb9dbdc-4f2c-4128-8601-fdefcc73eb43
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3828599986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3828599986
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.3585910588
Short name	T2960
Test name
Test status
Simulation time	58730971 ps
CPU time	0.72 seconds
Started	Aug 01 05:45:42 PM PDT 24
Finished	Aug 01 05:45:43 PM PDT 24
Peak memory	203936 kb
Host	smart-a9b2f044-65a1-4cfc-809e-1743a304dc06
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3585910588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3585910588
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1050526115
Short name	T2972
Test name
Test status
Simulation time	236571120 ps
CPU time	1.61 seconds
Started	Aug 01 05:45:42 PM PDT 24
Finished	Aug 01 05:45:44 PM PDT 24
Peak memory	206008 kb
Host	smart-2565d7b6-6cc1-4fd9-a8d2-7d93f01fb741
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1050526115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.1050526115
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3491525226
Short name	T2984
Test name
Test status
Simulation time	308576828 ps
CPU time	3.35 seconds
Started	Aug 01 05:45:43 PM PDT 24
Finished	Aug 01 05:45:46 PM PDT 24
Peak memory	219232 kb
Host	smart-dcd85756-9d33-453f-9589-16ec5b0c669a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3491525226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3491525226
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2765759763
Short name	T2934
Test name
Test status
Simulation time	393407436 ps
CPU time	2.81 seconds
Started	Aug 01 05:44:30 PM PDT 24
Finished	Aug 01 05:44:33 PM PDT 24
Peak memory	206704 kb
Host	smart-d5131450-d942-405b-816b-149cc24102d6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2765759763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2765759763
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.826993591
Short name	T2956
Test name
Test status
Simulation time	88392634 ps
CPU time	2.47 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:41 PM PDT 24
Peak memory	215016 kb
Host	smart-9f363812-71a7-496a-9030-876deeedca08
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826993591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde v_csr_mem_rw_with_rand_reset.826993591
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3276167968
Short name	T2978
Test name
Test status
Simulation time	48735120 ps
CPU time	0.84 seconds
Started	Aug 01 05:44:39 PM PDT 24
Finished	Aug 01 05:44:40 PM PDT 24
Peak memory	206588 kb
Host	smart-661a2581-cb38-4554-8c07-42d743ecf4ee
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3276167968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3276167968
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.683522629
Short name	T2922
Test name
Test status
Simulation time	94646056 ps
CPU time	1.47 seconds
Started	Aug 01 05:44:39 PM PDT 24
Finished	Aug 01 05:44:41 PM PDT 24
Peak memory	206792 kb
Host	smart-0e485614-7710-4139-9c47-c10d08a481df
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=683522629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.683522629
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1695749150
Short name	T2909
Test name
Test status
Simulation time	83912591 ps
CPU time	2.35 seconds
Started	Aug 01 05:45:42 PM PDT 24
Finished	Aug 01 05:45:45 PM PDT 24
Peak memory	204320 kb
Host	smart-7758546e-bd7c-489e-b1f5-d8b021418088
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1695749150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1695749150
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2229061860
Short name	T2973
Test name
Test status
Simulation time	115567553 ps
CPU time	2.52 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:41 PM PDT 24
Peak memory	214940 kb
Host	smart-4a9c10e3-f9ac-4767-ae9b-773f1aac26e0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229061860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.2229061860
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.634755245
Short name	T2980
Test name
Test status
Simulation time	55496543 ps
CPU time	0.83 seconds
Started	Aug 01 05:44:37 PM PDT 24
Finished	Aug 01 05:44:38 PM PDT 24
Peak memory	206648 kb
Host	smart-5e49b693-6c4d-478d-bb5d-51fb6fe0db02
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=634755245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.634755245
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.273976945
Short name	T2933
Test name
Test status
Simulation time	40780891 ps
CPU time	0.73 seconds
Started	Aug 01 05:44:37 PM PDT 24
Finished	Aug 01 05:44:38 PM PDT 24
Peak memory	206440 kb
Host	smart-eddc0a32-ccc5-4e87-940c-16198952f666
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=273976945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.273976945
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1980979137
Short name	T229
Test name
Test status
Simulation time	165695009 ps
CPU time	1.3 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:39 PM PDT 24
Peak memory	206828 kb
Host	smart-3ace8283-143c-446d-aa06-6bf4252d64f4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1980979137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1980979137
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4149932867
Short name	T228
Test name
Test status
Simulation time	202569065 ps
CPU time	2.61 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:41 PM PDT 24
Peak memory	215268 kb
Host	smart-1ef7a8f8-7d1c-4064-9cad-6881e88f4601
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4149932867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.4149932867
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3745041932
Short name	T102
Test name
Test status
Simulation time	412769270 ps
CPU time	2.67 seconds
Started	Aug 01 05:44:39 PM PDT 24
Finished	Aug 01 05:44:41 PM PDT 24
Peak memory	206664 kb
Host	smart-1cbac6b9-b2c0-43bc-ae90-722f61bfba4b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3745041932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3745041932
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1192774185
Short name	T2951
Test name
Test status
Simulation time	138104796 ps
CPU time	1.72 seconds
Started	Aug 01 05:44:39 PM PDT 24
Finished	Aug 01 05:44:41 PM PDT 24
Peak memory	215004 kb
Host	smart-d03fe1d4-5c38-4769-ba09-ac5daabe2d88
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192774185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.1192774185
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1304159168
Short name	T256
Test name
Test status
Simulation time	80746151 ps
CPU time	1.03 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:39 PM PDT 24
Peak memory	206584 kb
Host	smart-d6dfe2c1-59a1-4903-87ec-a02466d31247
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1304159168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1304159168
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.4012126729
Short name	T302
Test name
Test status
Simulation time	38880983 ps
CPU time	0.68 seconds
Started	Aug 01 05:44:40 PM PDT 24
Finished	Aug 01 05:44:41 PM PDT 24
Peak memory	206452 kb
Host	smart-0b7176f1-a899-4785-8260-1f8bdba11afc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4012126729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.4012126729
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3645833675
Short name	T265
Test name
Test status
Simulation time	281657796 ps
CPU time	1.87 seconds
Started	Aug 01 05:44:39 PM PDT 24
Finished	Aug 01 05:44:41 PM PDT 24
Peak memory	206732 kb
Host	smart-b9c581e2-b790-4f12-bb4d-62fc0854c53a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3645833675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3645833675
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3883383873
Short name	T126
Test name
Test status
Simulation time	118801493 ps
CPU time	1.79 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:40 PM PDT 24
Peak memory	206744 kb
Host	smart-45f1d69c-45b5-4564-a580-b38e96eb291a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3883383873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3883383873
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2453307876
Short name	T272
Test name
Test status
Simulation time	886469213 ps
CPU time	4.69 seconds
Started	Aug 01 05:44:39 PM PDT 24
Finished	Aug 01 05:44:44 PM PDT 24
Peak memory	206856 kb
Host	smart-c1e3eab1-af2b-44fa-a8b0-852c06d55e32
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2453307876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2453307876
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3995607994
Short name	T2977
Test name
Test status
Simulation time	64063577 ps
CPU time	1.48 seconds
Started	Aug 01 05:44:49 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	214996 kb
Host	smart-e3472fc6-cc8d-410a-b59c-db6abe50fccb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995607994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd ev_csr_mem_rw_with_rand_reset.3995607994
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.285724932
Short name	T2926
Test name
Test status
Simulation time	66688070 ps
CPU time	0.86 seconds
Started	Aug 01 05:44:50 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	206572 kb
Host	smart-aa050729-7bf9-4527-bb8b-1428af3c1605
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=285724932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.285724932
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2873961845
Short name	T2999
Test name
Test status
Simulation time	44227192 ps
CPU time	0.72 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:39 PM PDT 24
Peak memory	206396 kb
Host	smart-0f6bb2fa-06ba-4746-9725-531e02ab4f26
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2873961845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2873961845
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.21274371
Short name	T3008
Test name
Test status
Simulation time	123974624 ps
CPU time	1.22 seconds
Started	Aug 01 05:44:48 PM PDT 24
Finished	Aug 01 05:44:50 PM PDT 24
Peak memory	206708 kb
Host	smart-05d505fb-c9b1-4006-84f5-03fb12f56008
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=21274371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.21274371
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3426166415
Short name	T2964
Test name
Test status
Simulation time	148763574 ps
CPU time	1.84 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:40 PM PDT 24
Peak memory	206816 kb
Host	smart-a3ceee9d-fae6-41d6-9552-8d5138abe282
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3426166415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3426166415
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.2008579795
Short name	T442
Test name
Test status
Simulation time	986012150 ps
CPU time	4.94 seconds
Started	Aug 01 05:44:38 PM PDT 24
Finished	Aug 01 05:44:44 PM PDT 24
Peak memory	206864 kb
Host	smart-be82e811-58ed-41b6-b6b1-05e3ff4bcca0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2008579795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.2008579795
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2130412305
Short name	T2986
Test name
Test status
Simulation time	219103117 ps
CPU time	2.34 seconds
Started	Aug 01 05:44:01 PM PDT 24
Finished	Aug 01 05:44:03 PM PDT 24
Peak memory	206784 kb
Host	smart-965ac6a8-bd69-4a9e-9552-f6e0febb953b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2130412305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2130412305
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.3470126666
Short name	T230
Test name
Test status
Simulation time	760637601 ps
CPU time	4.59 seconds
Started	Aug 01 05:43:57 PM PDT 24
Finished	Aug 01 05:44:02 PM PDT 24
Peak memory	206788 kb
Host	smart-724aa2f9-d68e-4780-b08b-b0f9295f5e50
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3470126666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.3470126666
Directory	/workspace/2.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2372633242
Short name	T103
Test name
Test status
Simulation time	101002431 ps
CPU time	0.95 seconds
Started	Aug 01 05:43:56 PM PDT 24
Finished	Aug 01 05:43:57 PM PDT 24
Peak memory	206524 kb
Host	smart-bb838a76-0281-4908-a171-b3a0ffaa1d1b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2372633242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2372633242
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3292604570
Short name	T2941
Test name
Test status
Simulation time	165461284 ps
CPU time	1.9 seconds
Started	Aug 01 05:44:16 PM PDT 24
Finished	Aug 01 05:44:18 PM PDT 24
Peak memory	215000 kb
Host	smart-b1c3fb68-2ec0-430a-bb9a-07f4847003f5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292604570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde v_csr_mem_rw_with_rand_reset.3292604570
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2717456530
Short name	T104
Test name
Test status
Simulation time	68657621 ps
CPU time	0.96 seconds
Started	Aug 01 05:44:26 PM PDT 24
Finished	Aug 01 05:44:28 PM PDT 24
Peak memory	206576 kb
Host	smart-b7b511e9-41a7-48bb-9f87-f408454512f3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2717456530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2717456530
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3394921858
Short name	T301
Test name
Test status
Simulation time	35583842 ps
CPU time	0.71 seconds
Started	Aug 01 05:43:59 PM PDT 24
Finished	Aug 01 05:44:00 PM PDT 24
Peak memory	206464 kb
Host	smart-968120c6-0e94-4257-bc5b-da25aada1903
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3394921858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3394921858
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3333135916
Short name	T262
Test name
Test status
Simulation time	214642570 ps
CPU time	2.53 seconds
Started	Aug 01 05:44:00 PM PDT 24
Finished	Aug 01 05:44:02 PM PDT 24
Peak memory	215004 kb
Host	smart-8c978536-37b7-44f5-a9c3-db6529d557f3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3333135916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3333135916
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2371983985
Short name	T2958
Test name
Test status
Simulation time	338596688 ps
CPU time	2.61 seconds
Started	Aug 01 05:44:03 PM PDT 24
Finished	Aug 01 05:44:05 PM PDT 24
Peak memory	206576 kb
Host	smart-5deee78d-9a23-4376-a3cb-157117c38e67
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2371983985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2371983985
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.4252177850
Short name	T264
Test name
Test status
Simulation time	124360136 ps
CPU time	1.58 seconds
Started	Aug 01 05:44:00 PM PDT 24
Finished	Aug 01 05:44:02 PM PDT 24
Peak memory	206872 kb
Host	smart-78afb993-0629-4210-b79a-9e4bde8a21f0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4252177850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.4252177850
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.462592565
Short name	T2961
Test name
Test status
Simulation time	128290683 ps
CPU time	1.96 seconds
Started	Aug 01 05:44:25 PM PDT 24
Finished	Aug 01 05:44:27 PM PDT 24
Peak memory	219892 kb
Host	smart-9f29882d-3c30-4a7c-9018-68d2169e16e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=462592565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.462592565
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3391211789
Short name	T2920
Test name
Test status
Simulation time	619659574 ps
CPU time	2.78 seconds
Started	Aug 01 05:43:58 PM PDT 24
Finished	Aug 01 05:44:01 PM PDT 24
Peak memory	206840 kb
Host	smart-66900b27-0fdb-4735-b47e-d16a134df9dc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3391211789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3391211789
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3782933839
Short name	T2939
Test name
Test status
Simulation time	105731368 ps
CPU time	0.79 seconds
Started	Aug 01 05:44:49 PM PDT 24
Finished	Aug 01 05:44:50 PM PDT 24
Peak memory	206512 kb
Host	smart-90eeb7fc-a627-469f-9001-25272970224f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3782933839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3782933839
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.3169635799
Short name	T137
Test name
Test status
Simulation time	83749239 ps
CPU time	0.78 seconds
Started	Aug 01 05:44:50 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	206376 kb
Host	smart-da2649e3-a7cc-47f7-a822-d8b94045aed9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3169635799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3169635799
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.1827663226
Short name	T2942
Test name
Test status
Simulation time	43216887 ps
CPU time	0.72 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206468 kb
Host	smart-5240a8ab-0afa-48cc-98c3-ca25962d839e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1827663226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1827663226
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.381456683
Short name	T2938
Test name
Test status
Simulation time	46070265 ps
CPU time	0.74 seconds
Started	Aug 01 05:44:48 PM PDT 24
Finished	Aug 01 05:44:49 PM PDT 24
Peak memory	206432 kb
Host	smart-c809cea8-4e87-4457-8725-1daa57b4af78
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=381456683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.381456683
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.460773161
Short name	T300
Test name
Test status
Simulation time	30575000 ps
CPU time	0.71 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206460 kb
Host	smart-45de7ab4-2d71-4490-a591-9a408e9c692d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=460773161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.460773161
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.3503938300
Short name	T2990
Test name
Test status
Simulation time	47310540 ps
CPU time	0.69 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206480 kb
Host	smart-2a793068-d2bd-4313-9228-7872432f440e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3503938300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3503938300
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.857224056
Short name	T2965
Test name
Test status
Simulation time	38387928 ps
CPU time	0.7 seconds
Started	Aug 01 05:44:49 PM PDT 24
Finished	Aug 01 05:44:50 PM PDT 24
Peak memory	206400 kb
Host	smart-ae8a31f3-5509-4be2-8b0e-4d5cb08e289d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=857224056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.857224056
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.364384564
Short name	T274
Test name
Test status
Simulation time	32139381 ps
CPU time	0.71 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	206380 kb
Host	smart-5b79d11d-c870-4acb-9d95-6a8caddec6f6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=364384564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.364384564
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.1209924020
Short name	T2945
Test name
Test status
Simulation time	53597935 ps
CPU time	0.74 seconds
Started	Aug 01 05:44:50 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	206460 kb
Host	smart-15f511e8-652c-4415-865e-cb0e693b0c27
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1209924020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.1209924020
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2011804045
Short name	T2953
Test name
Test status
Simulation time	370817736 ps
CPU time	3.43 seconds
Started	Aug 01 05:43:57 PM PDT 24
Finished	Aug 01 05:44:01 PM PDT 24
Peak memory	206788 kb
Host	smart-1b9b98cc-029a-4588-8a3a-c54e4df4fe86
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2011804045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2011804045
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3557438719
Short name	T3003
Test name
Test status
Simulation time	1353603757 ps
CPU time	8.56 seconds
Started	Aug 01 05:44:25 PM PDT 24
Finished	Aug 01 05:44:34 PM PDT 24
Peak memory	206784 kb
Host	smart-dd5c09aa-8226-468e-8d8f-b0fc4b67907c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3557438719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3557438719
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3297059356
Short name	T129
Test name
Test status
Simulation time	82039216 ps
CPU time	0.93 seconds
Started	Aug 01 05:43:58 PM PDT 24
Finished	Aug 01 05:43:59 PM PDT 24
Peak memory	206616 kb
Host	smart-5daef7ac-260e-457a-b6e1-726fe01c40d2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3297059356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3297059356
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.4212262694
Short name	T2916
Test name
Test status
Simulation time	76563934 ps
CPU time	1.18 seconds
Started	Aug 01 05:43:57 PM PDT 24
Finished	Aug 01 05:43:58 PM PDT 24
Peak memory	214744 kb
Host	smart-9df99fc9-1d78-45bc-a6ec-abce0f6aacbc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212262694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde v_csr_mem_rw_with_rand_reset.4212262694
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.739401199
Short name	T254
Test name
Test status
Simulation time	75560297 ps
CPU time	0.83 seconds
Started	Aug 01 05:44:00 PM PDT 24
Finished	Aug 01 05:44:01 PM PDT 24
Peak memory	206544 kb
Host	smart-62463606-a5d5-40b5-9e06-b04af00e22fd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=739401199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.739401199
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3395702201
Short name	T2936
Test name
Test status
Simulation time	91250970 ps
CPU time	0.86 seconds
Started	Aug 01 05:44:00 PM PDT 24
Finished	Aug 01 05:44:02 PM PDT 24
Peak memory	206504 kb
Host	smart-4b131448-aa1a-44cd-8ee2-f2dbb2d2f387
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3395702201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3395702201
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2252711220
Short name	T2988
Test name
Test status
Simulation time	102412284 ps
CPU time	1.41 seconds
Started	Aug 01 05:43:59 PM PDT 24
Finished	Aug 01 05:44:01 PM PDT 24
Peak memory	206716 kb
Host	smart-51ac9751-bf21-4a15-960a-334876719d3c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2252711220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2252711220
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2942898283
Short name	T2919
Test name
Test status
Simulation time	144918014 ps
CPU time	2.38 seconds
Started	Aug 01 05:44:26 PM PDT 24
Finished	Aug 01 05:44:29 PM PDT 24
Peak memory	206644 kb
Host	smart-5c83e94f-c564-4aac-894c-3a9f0e9423ef
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2942898283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2942898283
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2999699509
Short name	T2983
Test name
Test status
Simulation time	103252350 ps
CPU time	1.65 seconds
Started	Aug 01 05:44:04 PM PDT 24
Finished	Aug 01 05:44:06 PM PDT 24
Peak memory	206744 kb
Host	smart-fb64f784-c45a-43b6-86f2-3d2bf8d74964
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2999699509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2999699509
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3227793104
Short name	T231
Test name
Test status
Simulation time	149588458 ps
CPU time	2.1 seconds
Started	Aug 01 05:44:00 PM PDT 24
Finished	Aug 01 05:44:03 PM PDT 24
Peak memory	206848 kb
Host	smart-a7a0f4fa-0f2b-40ec-8208-f9ebdade3ec2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3227793104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3227793104
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.136081102
Short name	T445
Test name
Test status
Simulation time	331192971 ps
CPU time	2.66 seconds
Started	Aug 01 05:43:57 PM PDT 24
Finished	Aug 01 05:44:00 PM PDT 24
Peak memory	207088 kb
Host	smart-3aa97634-5d3e-44d8-9f03-af94e965514e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=136081102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.136081102
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.4113794037
Short name	T2997
Test name
Test status
Simulation time	43205407 ps
CPU time	0.76 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206412 kb
Host	smart-e143e014-1f6a-4806-9dcb-23b7cfb69cd6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4113794037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.4113794037
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.219584497
Short name	T2921
Test name
Test status
Simulation time	68696342 ps
CPU time	0.77 seconds
Started	Aug 01 05:44:50 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	206472 kb
Host	smart-bff6505f-64e3-4109-a42d-4a7ad86fb441
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=219584497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.219584497
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.1004470509
Short name	T2946
Test name
Test status
Simulation time	41868506 ps
CPU time	0.73 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206444 kb
Host	smart-b709ca5f-9280-43ea-986d-38eeabe89077
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1004470509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1004470509
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.3356765310
Short name	T2966
Test name
Test status
Simulation time	106504962 ps
CPU time	0.83 seconds
Started	Aug 01 05:44:52 PM PDT 24
Finished	Aug 01 05:44:53 PM PDT 24
Peak memory	206500 kb
Host	smart-f4d784d3-b18e-4e12-8ba7-dd5ee74ce55a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3356765310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3356765310
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.2697988632
Short name	T2992
Test name
Test status
Simulation time	54730379 ps
CPU time	0.72 seconds
Started	Aug 01 05:44:49 PM PDT 24
Finished	Aug 01 05:44:50 PM PDT 24
Peak memory	206516 kb
Host	smart-fa1193b4-22e4-4c69-95d9-a6d701f96988
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2697988632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2697988632
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.4196141177
Short name	T2918
Test name
Test status
Simulation time	54151371 ps
CPU time	0.73 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206392 kb
Host	smart-367c2dfd-9d74-4006-ba0a-f7cef6da5fa6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4196141177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.4196141177
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.419166040
Short name	T2959
Test name
Test status
Simulation time	58456597 ps
CPU time	0.73 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206460 kb
Host	smart-487f0002-69a8-4a55-9eda-22efeb8ed9ad
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=419166040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.419166040
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3759659311
Short name	T297
Test name
Test status
Simulation time	36084431 ps
CPU time	0.7 seconds
Started	Aug 01 05:44:49 PM PDT 24
Finished	Aug 01 05:44:50 PM PDT 24
Peak memory	206432 kb
Host	smart-cff4ab1b-38cb-4c41-92fe-6021f5a9917a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3759659311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3759659311
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.2048987318
Short name	T2928
Test name
Test status
Simulation time	39081879 ps
CPU time	0.7 seconds
Started	Aug 01 05:44:48 PM PDT 24
Finished	Aug 01 05:44:49 PM PDT 24
Peak memory	206452 kb
Host	smart-8aec7a73-f380-4488-bebc-b77cd609fd5e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2048987318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2048987318
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.3203782051
Short name	T2993
Test name
Test status
Simulation time	42135498 ps
CPU time	0.7 seconds
Started	Aug 01 05:45:56 PM PDT 24
Finished	Aug 01 05:45:56 PM PDT 24
Peak memory	206356 kb
Host	smart-39bc0d73-0f5a-4712-8623-28be0409fc2e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3203782051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3203782051
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2448591321
Short name	T2991
Test name
Test status
Simulation time	215030197 ps
CPU time	3.6 seconds
Started	Aug 01 05:44:08 PM PDT 24
Finished	Aug 01 05:44:12 PM PDT 24
Peak memory	206796 kb
Host	smart-ac65a694-ff3d-4149-9f79-107cf1a7d7fa
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2448591321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2448591321
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3998298705
Short name	T101
Test name
Test status
Simulation time	431479274 ps
CPU time	3.91 seconds
Started	Aug 01 05:44:05 PM PDT 24
Finished	Aug 01 05:44:09 PM PDT 24
Peak memory	206836 kb
Host	smart-4459875b-7b28-4546-917b-683f5963355c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3998298705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3998298705
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3215201114
Short name	T128
Test name
Test status
Simulation time	76771159 ps
CPU time	0.88 seconds
Started	Aug 01 05:44:07 PM PDT 24
Finished	Aug 01 05:44:08 PM PDT 24
Peak memory	206592 kb
Host	smart-05cf3d10-91b9-484f-b1cf-3653a321e030
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3215201114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3215201114
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3033357173
Short name	T2917
Test name
Test status
Simulation time	101342324 ps
CPU time	1.33 seconds
Started	Aug 01 05:44:05 PM PDT 24
Finished	Aug 01 05:44:06 PM PDT 24
Peak memory	215048 kb
Host	smart-4f2fb682-8a52-4207-8a47-56e1784fa504
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033357173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde v_csr_mem_rw_with_rand_reset.3033357173
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2884477332
Short name	T268
Test name
Test status
Simulation time	79129807 ps
CPU time	0.85 seconds
Started	Aug 01 05:44:06 PM PDT 24
Finished	Aug 01 05:44:07 PM PDT 24
Peak memory	206512 kb
Host	smart-1082b2f8-2a73-40c1-a602-bb9f9cd2b563
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2884477332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2884477332
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.4148974642
Short name	T2925
Test name
Test status
Simulation time	33472765 ps
CPU time	0.71 seconds
Started	Aug 01 05:44:06 PM PDT 24
Finished	Aug 01 05:44:07 PM PDT 24
Peak memory	206428 kb
Host	smart-dbf003aa-6537-44dd-9423-b0a20707b423
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4148974642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.4148974642
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.4165150351
Short name	T2968
Test name
Test status
Simulation time	270570062 ps
CPU time	2.41 seconds
Started	Aug 01 05:44:08 PM PDT 24
Finished	Aug 01 05:44:11 PM PDT 24
Peak memory	206724 kb
Host	smart-da7fb45a-3ff1-40c4-b4f4-2ff25c847777
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4165150351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.4165150351
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4136964825
Short name	T2915
Test name
Test status
Simulation time	148391282 ps
CPU time	1.17 seconds
Started	Aug 01 05:44:10 PM PDT 24
Finished	Aug 01 05:44:11 PM PDT 24
Peak memory	206844 kb
Host	smart-b74de3a4-9635-4523-8eaa-6efd8de748ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4136964825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.4136964825
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1836202873
Short name	T2940
Test name
Test status
Simulation time	329264052 ps
CPU time	2.44 seconds
Started	Aug 01 05:44:03 PM PDT 24
Finished	Aug 01 05:44:06 PM PDT 24
Peak memory	206712 kb
Host	smart-ddaf6f23-368b-45b7-b10f-0b3139b2d5b3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1836202873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1836202873
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.3084697147
Short name	T2910
Test name
Test status
Simulation time	48687095 ps
CPU time	0.77 seconds
Started	Aug 01 05:44:50 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	206340 kb
Host	smart-3b15810b-b268-4fd2-b0f4-a7bd1dad2f21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3084697147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.3084697147
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.1558883697
Short name	T2979
Test name
Test status
Simulation time	51487424 ps
CPU time	0.78 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206484 kb
Host	smart-43144259-a5e4-42df-a4ea-bd1378f4cc30
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1558883697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1558883697
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.3977429580
Short name	T2971
Test name
Test status
Simulation time	73016616 ps
CPU time	0.72 seconds
Started	Aug 01 05:44:52 PM PDT 24
Finished	Aug 01 05:44:53 PM PDT 24
Peak memory	206448 kb
Host	smart-e016ecc5-9ce5-4452-b658-d0a8832f0f77
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3977429580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3977429580
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.2555792394
Short name	T2907
Test name
Test status
Simulation time	95326857 ps
CPU time	0.76 seconds
Started	Aug 01 05:44:48 PM PDT 24
Finished	Aug 01 05:44:49 PM PDT 24
Peak memory	206460 kb
Host	smart-58c37a57-1d11-4c04-8314-bb6dc39f5fd5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2555792394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2555792394
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.2309109004
Short name	T2927
Test name
Test status
Simulation time	84758314 ps
CPU time	0.75 seconds
Started	Aug 01 05:44:50 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	206400 kb
Host	smart-0bcc97f7-1ccb-4811-be4a-bbbae27ae36d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2309109004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2309109004
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1140073277
Short name	T303
Test name
Test status
Simulation time	54524467 ps
CPU time	0.72 seconds
Started	Aug 01 05:44:49 PM PDT 24
Finished	Aug 01 05:44:50 PM PDT 24
Peak memory	206436 kb
Host	smart-bbb674bc-9a5d-4316-b6e7-192c1db9e956
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1140073277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1140073277
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.657131036
Short name	T2976
Test name
Test status
Simulation time	56204673 ps
CPU time	0.77 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206448 kb
Host	smart-b027269a-cfbf-4c28-9c4e-886897ce08ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=657131036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.657131036
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.2887042323
Short name	T3014
Test name
Test status
Simulation time	102317101 ps
CPU time	0.82 seconds
Started	Aug 01 05:44:49 PM PDT 24
Finished	Aug 01 05:44:50 PM PDT 24
Peak memory	206456 kb
Host	smart-a7f641c5-35d4-4a2b-84f6-f28de64520ba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2887042323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2887042323
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.4262407855
Short name	T3005
Test name
Test status
Simulation time	64896081 ps
CPU time	0.7 seconds
Started	Aug 01 05:44:51 PM PDT 24
Finished	Aug 01 05:44:52 PM PDT 24
Peak memory	206480 kb
Host	smart-124b1d15-2410-4a36-a035-9a2e6beb3d9f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4262407855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.4262407855
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.121275361
Short name	T298
Test name
Test status
Simulation time	57227691 ps
CPU time	0.77 seconds
Started	Aug 01 05:44:50 PM PDT 24
Finished	Aug 01 05:44:51 PM PDT 24
Peak memory	206504 kb
Host	smart-17c25021-3984-4fc4-a42f-455ab5f5c783
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=121275361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.121275361
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3585510905
Short name	T2913
Test name
Test status
Simulation time	123213029 ps
CPU time	1.44 seconds
Started	Aug 01 05:44:07 PM PDT 24
Finished	Aug 01 05:44:09 PM PDT 24
Peak memory	214976 kb
Host	smart-7e106e6d-1114-48df-a721-73c190c2bb6d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585510905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde v_csr_mem_rw_with_rand_reset.3585510905
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2260011573
Short name	T2954
Test name
Test status
Simulation time	119019870 ps
CPU time	1.05 seconds
Started	Aug 01 05:44:08 PM PDT 24
Finished	Aug 01 05:44:09 PM PDT 24
Peak memory	206520 kb
Host	smart-534fb905-7e48-485b-924c-abee01b684c5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2260011573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2260011573
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.3142824703
Short name	T296
Test name
Test status
Simulation time	39062641 ps
CPU time	0.72 seconds
Started	Aug 01 05:44:13 PM PDT 24
Finished	Aug 01 05:44:14 PM PDT 24
Peak memory	206468 kb
Host	smart-27f89707-4fd2-4501-b754-4ee4403ad9a4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3142824703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3142824703
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3665534894
Short name	T2911
Test name
Test status
Simulation time	236499831 ps
CPU time	1.79 seconds
Started	Aug 01 05:44:06 PM PDT 24
Finished	Aug 01 05:44:08 PM PDT 24
Peak memory	206836 kb
Host	smart-c53f2a6b-a751-410f-9e6b-e54f12ddcefc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3665534894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3665534894
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3951293913
Short name	T2967
Test name
Test status
Simulation time	315809209 ps
CPU time	3.69 seconds
Started	Aug 01 05:44:06 PM PDT 24
Finished	Aug 01 05:44:10 PM PDT 24
Peak memory	223000 kb
Host	smart-bf76ab56-b5f1-4fdf-9b0e-7b53d3a13168
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3951293913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3951293913
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.204450852
Short name	T106
Test name
Test status
Simulation time	380645384 ps
CPU time	2.7 seconds
Started	Aug 01 05:44:13 PM PDT 24
Finished	Aug 01 05:44:16 PM PDT 24
Peak memory	206800 kb
Host	smart-917ffb6e-6665-45eb-a28d-06c11757b104
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=204450852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.204450852
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2933751429
Short name	T2957
Test name
Test status
Simulation time	215062595 ps
CPU time	2.13 seconds
Started	Aug 01 05:44:19 PM PDT 24
Finished	Aug 01 05:44:21 PM PDT 24
Peak memory	214980 kb
Host	smart-54ae7567-64ec-4116-8a12-bd30ac596cba
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933751429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde v_csr_mem_rw_with_rand_reset.2933751429
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1786994192
Short name	T2930
Test name
Test status
Simulation time	50968594 ps
CPU time	0.94 seconds
Started	Aug 01 05:44:20 PM PDT 24
Finished	Aug 01 05:44:21 PM PDT 24
Peak memory	206552 kb
Host	smart-aa618eab-2b66-4802-9122-a2218aca8226
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1786994192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1786994192
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.2549146849
Short name	T2996
Test name
Test status
Simulation time	101863335 ps
CPU time	0.79 seconds
Started	Aug 01 05:44:04 PM PDT 24
Finished	Aug 01 05:44:05 PM PDT 24
Peak memory	206440 kb
Host	smart-593a9e2b-de7b-4c56-aa98-32c6ce9ea3cf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2549146849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.2549146849
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.331766485
Short name	T263
Test name
Test status
Simulation time	172736254 ps
CPU time	1.71 seconds
Started	Aug 01 05:44:17 PM PDT 24
Finished	Aug 01 05:44:19 PM PDT 24
Peak memory	206812 kb
Host	smart-d5116e45-f542-4582-a21b-77b0b8d90ccd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=331766485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.331766485
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1699107577
Short name	T240
Test name
Test status
Simulation time	205980478 ps
CPU time	2.79 seconds
Started	Aug 01 05:44:15 PM PDT 24
Finished	Aug 01 05:44:17 PM PDT 24
Peak memory	206784 kb
Host	smart-9946e4ba-040b-4fb4-b639-771d1e2a99aa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1699107577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1699107577
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3074982568
Short name	T3011
Test name
Test status
Simulation time	337527578 ps
CPU time	2.61 seconds
Started	Aug 01 05:44:10 PM PDT 24
Finished	Aug 01 05:44:13 PM PDT 24
Peak memory	206808 kb
Host	smart-ba77f742-36c5-4930-a0e9-c42abf1243e9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3074982568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3074982568
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.3197502450
Short name	T3001
Test name
Test status
Simulation time	82712883 ps
CPU time	1.82 seconds
Started	Aug 01 05:44:17 PM PDT 24
Finished	Aug 01 05:44:19 PM PDT 24
Peak memory	214988 kb
Host	smart-645449e8-3d6c-479b-99dd-1101206bc394
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197502450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde v_csr_mem_rw_with_rand_reset.3197502450
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2345121892
Short name	T2975
Test name
Test status
Simulation time	100060802 ps
CPU time	1.16 seconds
Started	Aug 01 05:44:18 PM PDT 24
Finished	Aug 01 05:44:20 PM PDT 24
Peak memory	206584 kb
Host	smart-3aa6c501-237d-44c3-b909-bed6eafd9b7c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2345121892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2345121892
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3148656944
Short name	T2949
Test name
Test status
Simulation time	58894120 ps
CPU time	1.04 seconds
Started	Aug 01 05:44:17 PM PDT 24
Finished	Aug 01 05:44:18 PM PDT 24
Peak memory	206752 kb
Host	smart-65082317-798e-444e-b4c9-94009a4e9b39
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3148656944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3148656944
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1165095826
Short name	T239
Test name
Test status
Simulation time	260589427 ps
CPU time	3.29 seconds
Started	Aug 01 05:44:19 PM PDT 24
Finished	Aug 01 05:44:23 PM PDT 24
Peak memory	223092 kb
Host	smart-d59c230e-8eea-4091-81a4-bc00d41132cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1165095826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1165095826
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3589256026
Short name	T271
Test name
Test status
Simulation time	779854206 ps
CPU time	3.12 seconds
Started	Aug 01 05:44:18 PM PDT 24
Finished	Aug 01 05:44:21 PM PDT 24
Peak memory	206752 kb
Host	smart-a94d0e2f-59f1-4fe9-8803-10b74e12bcf1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3589256026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3589256026
Directory	/workspace/7.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3393318531
Short name	T2970
Test name
Test status
Simulation time	118623553 ps
CPU time	1.37 seconds
Started	Aug 01 05:44:18 PM PDT 24
Finished	Aug 01 05:44:19 PM PDT 24
Peak memory	215052 kb
Host	smart-b104f194-f32f-4354-b403-be0b57470aa5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393318531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde v_csr_mem_rw_with_rand_reset.3393318531
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.497046451
Short name	T2969
Test name
Test status
Simulation time	75835846 ps
CPU time	1.05 seconds
Started	Aug 01 05:44:18 PM PDT 24
Finished	Aug 01 05:44:19 PM PDT 24
Peak memory	206540 kb
Host	smart-03dc30a6-600e-443b-991e-144671e702e9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=497046451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.497046451
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1051808900
Short name	T3007
Test name
Test status
Simulation time	43171781 ps
CPU time	0.75 seconds
Started	Aug 01 05:44:18 PM PDT 24
Finished	Aug 01 05:44:19 PM PDT 24
Peak memory	206412 kb
Host	smart-69c7d685-f5f6-4c0d-9ea5-0b3c7e8061a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1051808900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1051808900
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1530978361
Short name	T2931
Test name
Test status
Simulation time	275335431 ps
CPU time	2.12 seconds
Started	Aug 01 05:44:18 PM PDT 24
Finished	Aug 01 05:44:21 PM PDT 24
Peak memory	206860 kb
Host	smart-9598d0e1-93cc-4d4a-822f-99e9b582343f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1530978361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1530978361
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3489438238
Short name	T2923
Test name
Test status
Simulation time	94867048 ps
CPU time	1.25 seconds
Started	Aug 01 05:44:28 PM PDT 24
Finished	Aug 01 05:44:29 PM PDT 24
Peak memory	214820 kb
Host	smart-d29ff0df-b947-48a3-a4e9-ef81c2748292
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489438238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde v_csr_mem_rw_with_rand_reset.3489438238
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3615272290
Short name	T2962
Test name
Test status
Simulation time	65615232 ps
CPU time	0.89 seconds
Started	Aug 01 05:44:28 PM PDT 24
Finished	Aug 01 05:44:30 PM PDT 24
Peak memory	206484 kb
Host	smart-f99e4091-ac60-46d3-947d-51a79ca460b1
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3615272290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3615272290
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.2473949043
Short name	T273
Test name
Test status
Simulation time	47736507 ps
CPU time	0.73 seconds
Started	Aug 01 05:44:18 PM PDT 24
Finished	Aug 01 05:44:19 PM PDT 24
Peak memory	206448 kb
Host	smart-010b0501-253d-431f-aba6-8ba846f907a5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2473949043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2473949043
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1107597353
Short name	T2950
Test name
Test status
Simulation time	74876700 ps
CPU time	1.08 seconds
Started	Aug 01 05:44:27 PM PDT 24
Finished	Aug 01 05:44:28 PM PDT 24
Peak memory	206768 kb
Host	smart-b168b911-45db-4e49-a467-e9949f817344
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1107597353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1107597353
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3295322947
Short name	T2987
Test name
Test status
Simulation time	190871523 ps
CPU time	1.67 seconds
Started	Aug 01 05:44:20 PM PDT 24
Finished	Aug 01 05:44:22 PM PDT 24
Peak memory	206920 kb
Host	smart-64b8f1c3-e75d-4885-b1f2-0c4d8f9ad392
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3295322947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3295322947
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3289154493
Short name	T446
Test name
Test status
Simulation time	1681319739 ps
CPU time	5.7 seconds
Started	Aug 01 05:44:19 PM PDT 24
Finished	Aug 01 05:44:24 PM PDT 24
Peak memory	207060 kb
Host	smart-6d001b18-6b90-4db2-879a-8fbf8b303e0f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3289154493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3289154493
Directory	/workspace/9.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/default/0.usbdev_alert_test.1935164893
Short name	T1879
Test name
Test status
Simulation time	33915194 ps
CPU time	0.68 seconds
Started	Aug 01 06:10:51 PM PDT 24
Finished	Aug 01 06:10:52 PM PDT 24
Peak memory	206904 kb
Host	smart-a411c4ec-d1dd-479f-aad4-cb3ea67a41de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1935164893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.1935164893
Directory	/workspace/0.usbdev_alert_test/latest

Test location	/workspace/coverage/default/0.usbdev_av_buffer.759151520
Short name	T1997
Test name
Test status
Simulation time	156948489 ps
CPU time	0.92 seconds
Started	Aug 01 06:10:38 PM PDT 24
Finished	Aug 01 06:10:39 PM PDT 24
Peak memory	206944 kb
Host	smart-6e9e73d1-3f00-4b41-be40-f564ed43d52a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75915 1520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.759151520
Directory	/workspace/0.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/0.usbdev_bitstuff_err.192105201
Short name	T1867
Test name
Test status
Simulation time	156197567 ps
CPU time	0.86 seconds
Started	Aug 01 06:10:35 PM PDT 24
Finished	Aug 01 06:10:36 PM PDT 24
Peak memory	206872 kb
Host	smart-275b9e67-c745-45ad-90d2-890d60c1910c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19210 5201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.192105201
Directory	/workspace/0.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/0.usbdev_data_toggle_clear.1869039754
Short name	T1617
Test name
Test status
Simulation time	455212904 ps
CPU time	1.62 seconds
Started	Aug 01 06:10:35 PM PDT 24
Finished	Aug 01 06:10:37 PM PDT 24
Peak memory	206968 kb
Host	smart-35c035fb-5f1e-4688-b4d9-895f78cacaa4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18690 39754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1869039754
Directory	/workspace/0.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/0.usbdev_data_toggle_restore.835489326
Short name	T2302
Test name
Test status
Simulation time	790350042 ps
CPU time	2.39 seconds
Started	Aug 01 06:10:37 PM PDT 24
Finished	Aug 01 06:10:40 PM PDT 24
Peak memory	206968 kb
Host	smart-e0482158-94da-4367-8853-d732ce8d6f27
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=835489326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.835489326
Directory	/workspace/0.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/0.usbdev_device_address.551406139
Short name	T450
Test name
Test status
Simulation time	30374736523 ps
CPU time	53 seconds
Started	Aug 01 06:10:38 PM PDT 24
Finished	Aug 01 06:11:31 PM PDT 24
Peak memory	207184 kb
Host	smart-a0c4a58d-5444-4c22-aa63-4f5263b65b82
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55140 6139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.551406139
Directory	/workspace/0.usbdev_device_address/latest

Test location	/workspace/coverage/default/0.usbdev_device_timeout.3302616144
Short name	T526
Test name
Test status
Simulation time	4912009814 ps
CPU time	34.25 seconds
Started	Aug 01 06:10:34 PM PDT 24
Finished	Aug 01 06:11:08 PM PDT 24
Peak memory	207104 kb
Host	smart-ca4377ca-a081-42c4-b923-c51124b4a543
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302616144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.3302616144
Directory	/workspace/0.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/0.usbdev_disable_endpoint.214739681
Short name	T1711
Test name
Test status
Simulation time	755515209 ps
CPU time	1.84 seconds
Started	Aug 01 06:10:37 PM PDT 24
Finished	Aug 01 06:10:39 PM PDT 24
Peak memory	207156 kb
Host	smart-695c67e7-2009-4603-9811-b1fe5175e042
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21473 9681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.214739681
Directory	/workspace/0.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/0.usbdev_disconnected.784264576
Short name	T2104
Test name
Test status
Simulation time	141756254 ps
CPU time	0.86 seconds
Started	Aug 01 06:10:37 PM PDT 24
Finished	Aug 01 06:10:38 PM PDT 24
Peak memory	206828 kb
Host	smart-8df6091b-0b79-4217-ad34-cef5a1c87d30
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78426 4576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.784264576
Directory	/workspace/0.usbdev_disconnected/latest

Test location	/workspace/coverage/default/0.usbdev_enable.215468111
Short name	T906
Test name
Test status
Simulation time	39032965 ps
CPU time	0.7 seconds
Started	Aug 01 06:10:37 PM PDT 24
Finished	Aug 01 06:10:38 PM PDT 24
Peak memory	206920 kb
Host	smart-a8636a4d-ffd0-4480-89e7-b1165b3a5e66
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21546 8111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.215468111
Directory	/workspace/0.usbdev_enable/latest

Test location	/workspace/coverage/default/0.usbdev_endpoint_access.4294065127
Short name	T2704
Test name
Test status
Simulation time	913536302 ps
CPU time	2.44 seconds
Started	Aug 01 06:10:37 PM PDT 24
Finished	Aug 01 06:10:40 PM PDT 24
Peak memory	207160 kb
Host	smart-bcffc3a8-a594-4840-93fa-eeb60b558aba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42940 65127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.4294065127
Directory	/workspace/0.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/0.usbdev_endpoint_types.2430582179
Short name	T430
Test name
Test status
Simulation time	263130430 ps
CPU time	1.08 seconds
Started	Aug 01 06:10:44 PM PDT 24
Finished	Aug 01 06:10:45 PM PDT 24
Peak memory	206936 kb
Host	smart-2832f977-a80a-4f88-a46a-afb7f338cfa1
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2430582179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.2430582179
Directory	/workspace/0.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/0.usbdev_fifo_rst.1838742208
Short name	T2567
Test name
Test status
Simulation time	254507603 ps
CPU time	1.52 seconds
Started	Aug 01 06:10:37 PM PDT 24
Finished	Aug 01 06:10:39 PM PDT 24
Peak memory	207136 kb
Host	smart-77d78a82-bbb6-479a-9830-c4bf08906b14
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18387 42208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1838742208
Directory	/workspace/0.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/0.usbdev_freq_hiclk.2111414506
Short name	T2248
Test name
Test status
Simulation time	97181086405 ps
CPU time	157.19 seconds
Started	Aug 01 06:10:34 PM PDT 24
Finished	Aug 01 06:13:11 PM PDT 24
Peak memory	207148 kb
Host	smart-788a4dd9-cddd-43ed-a74d-fdcd09853489
User	root
Command	/workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2111414506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2111414506
Directory	/workspace/0.usbdev_freq_hiclk/latest

Test location	/workspace/coverage/default/0.usbdev_freq_hiclk_max.1203139201
Short name	T1898
Test name
Test status
Simulation time	84275559431 ps
CPU time	127.49 seconds
Started	Aug 01 06:10:38 PM PDT 24
Finished	Aug 01 06:12:45 PM PDT 24
Peak memory	207112 kb
Host	smart-cebb95c2-bcf6-42fe-b3bd-57ce2a8196ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203139201 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.1203139201
Directory	/workspace/0.usbdev_freq_hiclk_max/latest

Test location	/workspace/coverage/default/0.usbdev_freq_loclk_max.2236540239
Short name	T2361
Test name
Test status
Simulation time	100244004597 ps
CPU time	186.52 seconds
Started	Aug 01 06:10:37 PM PDT 24
Finished	Aug 01 06:13:43 PM PDT 24
Peak memory	207156 kb
Host	smart-2b38b1d8-93c8-4677-89d4-27ceed0728b7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236540239 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.2236540239
Directory	/workspace/0.usbdev_freq_loclk_max/latest

Test location	/workspace/coverage/default/0.usbdev_freq_phase.2517200106
Short name	T879
Test name
Test status
Simulation time	114133750483 ps
CPU time	198.07 seconds
Started	Aug 01 06:10:39 PM PDT 24
Finished	Aug 01 06:13:57 PM PDT 24
Peak memory	207120 kb
Host	smart-915f84a7-af5d-4dfb-b770-2946071dd206
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25172 00106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2517200106
Directory	/workspace/0.usbdev_freq_phase/latest

Test location	/workspace/coverage/default/0.usbdev_in_iso.3103612617
Short name	T1809
Test name
Test status
Simulation time	228192993 ps
CPU time	1.19 seconds
Started	Aug 01 06:10:38 PM PDT 24
Finished	Aug 01 06:10:40 PM PDT 24
Peak memory	215308 kb
Host	smart-37d4567f-0b05-4796-a400-e0f6ee52b57e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3103612617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.3103612617
Directory	/workspace/0.usbdev_in_iso/latest

Test location	/workspace/coverage/default/0.usbdev_in_stall.273640652
Short name	T2515
Test name
Test status
Simulation time	138982873 ps
CPU time	0.81 seconds
Started	Aug 01 06:10:41 PM PDT 24
Finished	Aug 01 06:10:42 PM PDT 24
Peak memory	206900 kb
Host	smart-25cf6eb7-bf1d-4df9-a2ea-81ad3ae72158
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27364 0652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.273640652
Directory	/workspace/0.usbdev_in_stall/latest

Test location	/workspace/coverage/default/0.usbdev_in_trans.22822704
Short name	T869
Test name
Test status
Simulation time	173250844 ps
CPU time	0.94 seconds
Started	Aug 01 06:10:36 PM PDT 24
Finished	Aug 01 06:10:37 PM PDT 24
Peak memory	206904 kb
Host	smart-1fc822d5-db24-49a7-b316-c680d2806427
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22822 704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.22822704
Directory	/workspace/0.usbdev_in_trans/latest

Test location	/workspace/coverage/default/0.usbdev_invalid_sync.2084172402
Short name	T1354
Test name
Test status
Simulation time	4328092540 ps
CPU time	125.24 seconds
Started	Aug 01 06:10:36 PM PDT 24
Finished	Aug 01 06:12:41 PM PDT 24
Peak memory	215352 kb
Host	smart-62f9f148-605a-4aad-bc4c-a65cb92539a9
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2084172402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.2084172402
Directory	/workspace/0.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/0.usbdev_link_in_err.117890707
Short name	T983
Test name
Test status
Simulation time	161876659 ps
CPU time	0.88 seconds
Started	Aug 01 06:10:38 PM PDT 24
Finished	Aug 01 06:10:39 PM PDT 24
Peak memory	206880 kb
Host	smart-2faf60a9-ab14-47fe-87ff-e12b7b9f74f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11789 0707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.117890707
Directory	/workspace/0.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/0.usbdev_link_out_err.76240820
Short name	T56
Test name
Test status
Simulation time	476113794 ps
CPU time	1.47 seconds
Started	Aug 01 06:10:38 PM PDT 24
Finished	Aug 01 06:10:40 PM PDT 24
Peak memory	206976 kb
Host	smart-c323acec-8443-4b60-8f65-71010a2a08e5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76240 820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.76240820
Directory	/workspace/0.usbdev_link_out_err/latest

Test location	/workspace/coverage/default/0.usbdev_link_suspend.670909660
Short name	T1922
Test name
Test status
Simulation time	10371348915 ps
CPU time	13.05 seconds
Started	Aug 01 06:10:36 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	207004 kb
Host	smart-213beb8d-38c7-4b78-82f5-f267a0f4c746
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67090 9660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.670909660
Directory	/workspace/0.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/0.usbdev_low_speed_traffic.2006218838
Short name	T2128
Test name
Test status
Simulation time	3855730025 ps
CPU time	30.69 seconds
Started	Aug 01 06:10:38 PM PDT 24
Finished	Aug 01 06:11:08 PM PDT 24
Peak memory	217704 kb
Host	smart-29e29a92-4961-4dcf-aa1a-267eaf57b9da
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20062 18838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.2006218838
Directory	/workspace/0.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/0.usbdev_max_inter_pkt_delay.4122555578
Short name	T1863
Test name
Test status
Simulation time	2533402921 ps
CPU time	20.05 seconds
Started	Aug 01 06:10:37 PM PDT 24
Finished	Aug 01 06:10:57 PM PDT 24
Peak memory	217112 kb
Host	smart-13166cb7-3a3c-42b0-af70-f40b504444ae
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4122555578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.4122555578
Directory	/workspace/0.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/0.usbdev_max_length_in_transaction.3357310697
Short name	T1074
Test name
Test status
Simulation time	238918785 ps
CPU time	0.96 seconds
Started	Aug 01 06:10:41 PM PDT 24
Finished	Aug 01 06:10:42 PM PDT 24
Peak memory	206884 kb
Host	smart-e535cb89-0898-4719-a2bd-06b208137121
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3357310697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3357310697
Directory	/workspace/0.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/0.usbdev_max_length_out_transaction.865537160
Short name	T588
Test name
Test status
Simulation time	194068841 ps
CPU time	0.98 seconds
Started	Aug 01 06:10:44 PM PDT 24
Finished	Aug 01 06:10:45 PM PDT 24
Peak memory	206944 kb
Host	smart-6ca5fd93-0875-42ee-bca0-5fa3c1399344
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86553 7160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.865537160
Directory	/workspace/0.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.2377472396
Short name	T2351
Test name
Test status
Simulation time	1875525988 ps
CPU time	19.11 seconds
Started	Aug 01 06:10:37 PM PDT 24
Finished	Aug 01 06:10:56 PM PDT 24
Peak memory	223428 kb
Host	smart-762b5ae4-6234-4322-aa8f-133e4ad763ec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23774 72396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.2377472396
Directory	/workspace/0.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/0.usbdev_max_usb_traffic.3976041506
Short name	T1736
Test name
Test status
Simulation time	3072863036 ps
CPU time	34.85 seconds
Started	Aug 01 06:10:36 PM PDT 24
Finished	Aug 01 06:11:11 PM PDT 24
Peak memory	217920 kb
Host	smart-4970341f-245c-4fee-a1b5-2c8d559835ee
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3976041506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3976041506
Directory	/workspace/0.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/0.usbdev_min_inter_pkt_delay.2518382759
Short name	T1453
Test name
Test status
Simulation time	2336810847 ps
CPU time	18.54 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:11:07 PM PDT 24
Peak memory	223480 kb
Host	smart-1328e84e-5d15-4f2f-b614-2c7a23e59fbc
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2518382759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.2518382759
Directory	/workspace/0.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/0.usbdev_min_length_in_transaction.322868605
Short name	T2131
Test name
Test status
Simulation time	155446323 ps
CPU time	0.89 seconds
Started	Aug 01 06:10:49 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206900 kb
Host	smart-cf3a0d82-b72c-4c9f-a0db-b17abebdb4c7
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=322868605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.322868605
Directory	/workspace/0.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/0.usbdev_min_length_out_transaction.1569841128
Short name	T1084
Test name
Test status
Simulation time	149716203 ps
CPU time	0.81 seconds
Started	Aug 01 06:10:45 PM PDT 24
Finished	Aug 01 06:10:46 PM PDT 24
Peak memory	206952 kb
Host	smart-7e60b65c-2c2b-42f2-908b-4b590a9c3033
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15698 41128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1569841128
Directory	/workspace/0.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3904328559
Short name	T55
Test name
Test status
Simulation time	398996477 ps
CPU time	1.43 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206932 kb
Host	smart-633b6ab0-9293-4a35-9e3d-58ba53f02b5d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39043 28559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3904328559
Directory	/workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location	/workspace/coverage/default/0.usbdev_out_iso.2046924258
Short name	T1681
Test name
Test status
Simulation time	159734527 ps
CPU time	0.87 seconds
Started	Aug 01 06:10:47 PM PDT 24
Finished	Aug 01 06:10:48 PM PDT 24
Peak memory	206944 kb
Host	smart-f62bfe27-0367-487c-a6c6-0292a98ac2c7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20469 24258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2046924258
Directory	/workspace/0.usbdev_out_iso/latest

Test location	/workspace/coverage/default/0.usbdev_out_stall.1921098499
Short name	T1276
Test name
Test status
Simulation time	158751286 ps
CPU time	0.9 seconds
Started	Aug 01 06:10:52 PM PDT 24
Finished	Aug 01 06:10:53 PM PDT 24
Peak memory	206972 kb
Host	smart-0ea5cc17-0431-4998-ba5e-ef92877b54fd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19210 98499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1921098499
Directory	/workspace/0.usbdev_out_stall/latest

Test location	/workspace/coverage/default/0.usbdev_out_trans_nak.2806405021
Short name	T540
Test name
Test status
Simulation time	177116937 ps
CPU time	0.87 seconds
Started	Aug 01 06:10:46 PM PDT 24
Finished	Aug 01 06:10:47 PM PDT 24
Peak memory	206952 kb
Host	smart-c9ecfbdd-2bf9-45aa-90e7-546f6499e60a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064 05021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2806405021
Directory	/workspace/0.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/0.usbdev_pending_in_trans.3329160791
Short name	T924
Test name
Test status
Simulation time	165490481 ps
CPU time	0.9 seconds
Started	Aug 01 06:10:49 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206920 kb
Host	smart-06e7898b-eef6-4dba-bc5a-8cfc584f9d7c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33291 60791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.3329160791
Directory	/workspace/0.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2370999552
Short name	T554
Test name
Test status
Simulation time	177675260 ps
CPU time	0.88 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206924 kb
Host	smart-17e0cc20-ca8c-47fa-8885-e181b46a6f3a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23709 99552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2370999552
Directory	/workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location	/workspace/coverage/default/0.usbdev_phy_config_pinflip.1932772905
Short name	T890
Test name
Test status
Simulation time	241713762 ps
CPU time	1.07 seconds
Started	Aug 01 06:10:49 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206956 kb
Host	smart-91d4b10d-4109-40a7-9ed6-69d70d72e332
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1932772905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.1932772905
Directory	/workspace/0.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1129060989
Short name	T2843
Test name
Test status
Simulation time	231141496 ps
CPU time	1.03 seconds
Started	Aug 01 06:10:51 PM PDT 24
Finished	Aug 01 06:10:52 PM PDT 24
Peak memory	206900 kb
Host	smart-f8444e35-ad46-4a71-998d-caeaaf406d2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11290 60989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1129060989
Directory	/workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location	/workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1833859703
Short name	T2620
Test name
Test status
Simulation time	222629880 ps
CPU time	1.04 seconds
Started	Aug 01 06:10:49 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206960 kb
Host	smart-aedd6582-ebe2-432e-9c78-fef9458dfdb5
User	root
Command	/workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1833859703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1833859703
Directory	/workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location	/workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1989430472
Short name	T130
Test name
Test status
Simulation time	255147866 ps
CPU time	1.14 seconds
Started	Aug 01 06:10:51 PM PDT 24
Finished	Aug 01 06:10:52 PM PDT 24
Peak memory	206920 kb
Host	smart-cf74fbe1-7ebe-46f1-a2bb-5989e0b11d18
User	root
Command	/workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1989430472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1989430472
Directory	/workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location	/workspace/coverage/default/0.usbdev_phy_pins_sense.2476417509
Short name	T1487
Test name
Test status
Simulation time	36023317 ps
CPU time	0.72 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:10:49 PM PDT 24
Peak memory	206920 kb
Host	smart-0bcbb007-63eb-41a6-977f-58e057b88db8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24764 17509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2476417509
Directory	/workspace/0.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/0.usbdev_pkt_buffer.1707441380
Short name	T1945
Test name
Test status
Simulation time	8401344965 ps
CPU time	22.9 seconds
Started	Aug 01 06:10:52 PM PDT 24
Finished	Aug 01 06:11:15 PM PDT 24
Peak memory	215380 kb
Host	smart-a1fc7b60-c76c-438f-9d1b-4fc3a2a1f724
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17074 41380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.1707441380
Directory	/workspace/0.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/0.usbdev_pkt_sent.353631949
Short name	T696
Test name
Test status
Simulation time	249529607 ps
CPU time	1.13 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206900 kb
Host	smart-2186463b-8ee1-458f-946a-703312c75454
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35363 1949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.353631949
Directory	/workspace/0.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/0.usbdev_rand_bus_disconnects.4089433974
Short name	T802
Test name
Test status
Simulation time	6083879476 ps
CPU time	21.76 seconds
Started	Aug 01 06:10:50 PM PDT 24
Finished	Aug 01 06:11:12 PM PDT 24
Peak memory	223540 kb
Host	smart-6eed23f0-2f7d-48b2-b1d8-8b691478c5b8
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089433974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.4089433974
Directory	/workspace/0.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/0.usbdev_rand_bus_resets.2676718676
Short name	T1200
Test name
Test status
Simulation time	2967541502 ps
CPU time	81.49 seconds
Started	Aug 01 06:10:53 PM PDT 24
Finished	Aug 01 06:12:15 PM PDT 24
Peak memory	217804 kb
Host	smart-7fe4ee9a-e2e7-42ad-86a6-68bdfbd4f948
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676718676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2676718676
Directory	/workspace/0.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/0.usbdev_rand_suspends.1785784045
Short name	T1286
Test name
Test status
Simulation time	13707194552 ps
CPU time	292.06 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:15:41 PM PDT 24
Peak memory	215304 kb
Host	smart-99057677-73bc-4162-b623-5f4f4f972d05
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785784045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1785784045
Directory	/workspace/0.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/0.usbdev_random_length_in_transaction.1811905125
Short name	T2584
Test name
Test status
Simulation time	220335901 ps
CPU time	0.99 seconds
Started	Aug 01 06:10:47 PM PDT 24
Finished	Aug 01 06:10:49 PM PDT 24
Peak memory	206980 kb
Host	smart-dbf5c98f-7c73-4211-95ab-afa5ccb6e191
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18119 05125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1811905125
Directory	/workspace/0.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/0.usbdev_random_length_out_transaction.2496071768
Short name	T1174
Test name
Test status
Simulation time	146399154 ps
CPU time	0.87 seconds
Started	Aug 01 06:10:49 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206880 kb
Host	smart-dc7a0047-d3fa-42c4-8ed1-82b3df271559
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960 71768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.2496071768
Directory	/workspace/0.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/0.usbdev_rx_crc_err.665848602
Short name	T1311
Test name
Test status
Simulation time	183657825 ps
CPU time	0.88 seconds
Started	Aug 01 06:10:52 PM PDT 24
Finished	Aug 01 06:10:53 PM PDT 24
Peak memory	206924 kb
Host	smart-ce9dee8a-f755-4aaf-888b-9787ffe5a93c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66584 8602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.665848602
Directory	/workspace/0.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/0.usbdev_setup_priority.1950176736
Short name	T40
Test name
Test status
Simulation time	364048776 ps
CPU time	1.34 seconds
Started	Aug 01 06:10:50 PM PDT 24
Finished	Aug 01 06:10:51 PM PDT 24
Peak memory	206932 kb
Host	smart-81652913-2ac1-481d-8b0b-83b9f2f7809a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19501 76736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1950176736
Directory	/workspace/0.usbdev_setup_priority/latest

Test location	/workspace/coverage/default/0.usbdev_setup_stage.640597503
Short name	T733
Test name
Test status
Simulation time	152981255 ps
CPU time	0.87 seconds
Started	Aug 01 06:10:50 PM PDT 24
Finished	Aug 01 06:10:51 PM PDT 24
Peak memory	206932 kb
Host	smart-df720501-8927-4119-aa4a-28a34f1a1d51
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64059 7503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.640597503
Directory	/workspace/0.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/0.usbdev_setup_trans_ignored.4240149438
Short name	T917
Test name
Test status
Simulation time	172366608 ps
CPU time	0.86 seconds
Started	Aug 01 06:10:52 PM PDT 24
Finished	Aug 01 06:10:53 PM PDT 24
Peak memory	206928 kb
Host	smart-8c22feda-e097-49e7-8426-a48bd994934c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42401 49438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.4240149438
Directory	/workspace/0.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/0.usbdev_smoke.2303312935
Short name	T2775
Test name
Test status
Simulation time	308049656 ps
CPU time	1.14 seconds
Started	Aug 01 06:10:53 PM PDT 24
Finished	Aug 01 06:10:54 PM PDT 24
Peak memory	206952 kb
Host	smart-17bd96ca-2d70-4143-9131-bd5235b73426
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23033 12935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2303312935
Directory	/workspace/0.usbdev_smoke/latest

Test location	/workspace/coverage/default/0.usbdev_spurious_pids_ignored.1568442120
Short name	T1414
Test name
Test status
Simulation time	2532437546 ps
CPU time	25.3 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:11:13 PM PDT 24
Peak memory	215396 kb
Host	smart-8c166516-ae8d-4223-b0a4-35248bcb8e94
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1568442120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1568442120
Directory	/workspace/0.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/0.usbdev_stall_priority_over_nak.2503231209
Short name	T1115
Test name
Test status
Simulation time	198214795 ps
CPU time	0.89 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206960 kb
Host	smart-008b402f-095f-4074-98b2-783bd8def470
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25032 31209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.2503231209
Directory	/workspace/0.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/0.usbdev_stall_trans.3145767274
Short name	T1802
Test name
Test status
Simulation time	163716088 ps
CPU time	0.89 seconds
Started	Aug 01 06:10:51 PM PDT 24
Finished	Aug 01 06:10:52 PM PDT 24
Peak memory	206876 kb
Host	smart-4fe4c12b-f69c-451b-91be-3aba51b2aea9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31457 67274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.3145767274
Directory	/workspace/0.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/0.usbdev_stream_len_max.3391876377
Short name	T2136
Test name
Test status
Simulation time	436708555 ps
CPU time	1.27 seconds
Started	Aug 01 06:10:47 PM PDT 24
Finished	Aug 01 06:10:49 PM PDT 24
Peak memory	207132 kb
Host	smart-51e7a04b-7d18-44d5-bc27-3fa3b1f3f1f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33918 76377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.3391876377
Directory	/workspace/0.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/0.usbdev_streaming_out.755229321
Short name	T1198
Test name
Test status
Simulation time	3408008076 ps
CPU time	95.6 seconds
Started	Aug 01 06:10:49 PM PDT 24
Finished	Aug 01 06:12:25 PM PDT 24
Peak memory	216732 kb
Host	smart-69733647-18d7-45ad-8dc6-be38a8041bb9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75522 9321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.755229321
Directory	/workspace/0.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.2303299935
Short name	T819
Test name
Test status
Simulation time	1567917101 ps
CPU time	13.67 seconds
Started	Aug 01 06:10:41 PM PDT 24
Finished	Aug 01 06:10:55 PM PDT 24
Peak memory	207040 kb
Host	smart-1b17296c-1765-4dfe-8592-f8bf0e5a4abe
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303299935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host _handshake.2303299935
Directory	/workspace/0.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/1.usbdev_alert_test.1523025354
Short name	T1506
Test name
Test status
Simulation time	43931744 ps
CPU time	0.72 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:11:22 PM PDT 24
Peak memory	206976 kb
Host	smart-9e66abe0-6e98-4f50-81fd-41721473428d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1523025354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1523025354
Directory	/workspace/1.usbdev_alert_test/latest

Test location	/workspace/coverage/default/1.usbdev_av_buffer.1122470477
Short name	T1048
Test name
Test status
Simulation time	187209482 ps
CPU time	0.98 seconds
Started	Aug 01 06:10:51 PM PDT 24
Finished	Aug 01 06:10:52 PM PDT 24
Peak memory	206880 kb
Host	smart-b865871c-8fb4-4daa-80e1-664962aaeded
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11224 70477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1122470477
Directory	/workspace/1.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/1.usbdev_av_overflow.101531474
Short name	T2832
Test name
Test status
Simulation time	172277284 ps
CPU time	0.85 seconds
Started	Aug 01 06:10:48 PM PDT 24
Finished	Aug 01 06:10:49 PM PDT 24
Peak memory	206908 kb
Host	smart-0311059d-29c3-4b0f-a92c-e166f0f4633c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10153 1474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.101531474
Directory	/workspace/1.usbdev_av_overflow/latest

Test location	/workspace/coverage/default/1.usbdev_bitstuff_err.1944491396
Short name	T883
Test name
Test status
Simulation time	148597328 ps
CPU time	0.94 seconds
Started	Aug 01 06:10:49 PM PDT 24
Finished	Aug 01 06:10:50 PM PDT 24
Peak memory	206892 kb
Host	smart-88ef4bf2-43ad-4be4-911a-3b7578732d90
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19444 91396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1944491396
Directory	/workspace/1.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/1.usbdev_data_toggle_clear.2082261661
Short name	T1656
Test name
Test status
Simulation time	193947286 ps
CPU time	0.95 seconds
Started	Aug 01 06:10:54 PM PDT 24
Finished	Aug 01 06:10:55 PM PDT 24
Peak memory	206928 kb
Host	smart-9a1a226e-b9d3-42f6-9dc5-822d822a0c3a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822 61661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2082261661
Directory	/workspace/1.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/1.usbdev_data_toggle_restore.3151203930
Short name	T729
Test name
Test status
Simulation time	1104118218 ps
CPU time	2.93 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:07 PM PDT 24
Peak memory	207212 kb
Host	smart-511b4a59-cb41-4453-bd1b-6bd2e02540ea
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3151203930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.3151203930
Directory	/workspace/1.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/1.usbdev_device_address.1060156451
Short name	T2258
Test name
Test status
Simulation time	54754339015 ps
CPU time	97.73 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:12:44 PM PDT 24
Peak memory	207148 kb
Host	smart-43f0eabd-18b1-4658-a835-7ecca26b698d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10601 56451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.1060156451
Directory	/workspace/1.usbdev_device_address/latest

Test location	/workspace/coverage/default/1.usbdev_disable_endpoint.594361938
Short name	T742
Test name
Test status
Simulation time	911094799 ps
CPU time	2 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:11:09 PM PDT 24
Peak memory	206900 kb
Host	smart-9460c878-6545-4fdd-b537-50f1e8b6017f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59436 1938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.594361938
Directory	/workspace/1.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/1.usbdev_disconnected.2374583106
Short name	T2484
Test name
Test status
Simulation time	138764149 ps
CPU time	0.84 seconds
Started	Aug 01 06:11:03 PM PDT 24
Finished	Aug 01 06:11:05 PM PDT 24
Peak memory	206896 kb
Host	smart-81fec2d0-6a1a-421a-991e-b90d8e3f4dac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23745 83106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2374583106
Directory	/workspace/1.usbdev_disconnected/latest

Test location	/workspace/coverage/default/1.usbdev_enable.3276824952
Short name	T534
Test name
Test status
Simulation time	39089272 ps
CPU time	0.72 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:05 PM PDT 24
Peak memory	206920 kb
Host	smart-ac0efc14-9830-47e5-8dac-3095692188fb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32768 24952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3276824952
Directory	/workspace/1.usbdev_enable/latest

Test location	/workspace/coverage/default/1.usbdev_endpoint_access.2610812695
Short name	T1519
Test name
Test status
Simulation time	838198759 ps
CPU time	2.32 seconds
Started	Aug 01 06:11:03 PM PDT 24
Finished	Aug 01 06:11:06 PM PDT 24
Peak memory	207116 kb
Host	smart-b0dd8b59-a4d1-43f8-93fa-f278babc7531
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26108 12695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2610812695
Directory	/workspace/1.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/1.usbdev_endpoint_types.1671533317
Short name	T2057
Test name
Test status
Simulation time	368804849 ps
CPU time	1.17 seconds
Started	Aug 01 06:11:07 PM PDT 24
Finished	Aug 01 06:11:08 PM PDT 24
Peak memory	206976 kb
Host	smart-fd1d35fb-ba4d-44a7-8db8-92385062d497
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1671533317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.1671533317
Directory	/workspace/1.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/1.usbdev_fifo_rst.1549780478
Short name	T2616
Test name
Test status
Simulation time	289778174 ps
CPU time	2.51 seconds
Started	Aug 01 06:11:03 PM PDT 24
Finished	Aug 01 06:11:06 PM PDT 24
Peak memory	207080 kb
Host	smart-6eadaa69-e921-469b-8f5d-16748587101f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15497 80478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1549780478
Directory	/workspace/1.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/1.usbdev_freq_hiclk.146172645
Short name	T1842
Test name
Test status
Simulation time	109179730231 ps
CPU time	206.49 seconds
Started	Aug 01 06:11:02 PM PDT 24
Finished	Aug 01 06:14:29 PM PDT 24
Peak memory	207204 kb
Host	smart-772d1130-8d43-48e9-a310-b33f3dccb9fd
User	root
Command	/workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=146172645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.146172645
Directory	/workspace/1.usbdev_freq_hiclk/latest

Test location	/workspace/coverage/default/1.usbdev_freq_hiclk_max.3821146276
Short name	T1273
Test name
Test status
Simulation time	113112352622 ps
CPU time	174.97 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:14:00 PM PDT 24
Peak memory	207188 kb
Host	smart-7e9e44c3-6014-4d8e-8576-6395861f7a9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821146276 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.3821146276
Directory	/workspace/1.usbdev_freq_hiclk_max/latest

Test location	/workspace/coverage/default/1.usbdev_freq_loclk.3608071189
Short name	T468
Test name
Test status
Simulation time	106134356309 ps
CPU time	160.53 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:13:46 PM PDT 24
Peak memory	207160 kb
Host	smart-4fa98d06-21a1-45a7-a326-aef54b5c9cda
User	root
Command	/workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3608071189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3608071189
Directory	/workspace/1.usbdev_freq_loclk/latest

Test location	/workspace/coverage/default/1.usbdev_freq_loclk_max.1177406199
Short name	T1431
Test name
Test status
Simulation time	94140949250 ps
CPU time	151.45 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:13:36 PM PDT 24
Peak memory	207108 kb
Host	smart-88ec6136-c56b-450c-a0a1-60c08d037675
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177406199 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.1177406199
Directory	/workspace/1.usbdev_freq_loclk_max/latest

Test location	/workspace/coverage/default/1.usbdev_freq_phase.680482654
Short name	T2184
Test name
Test status
Simulation time	105109287039 ps
CPU time	159.02 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:13:43 PM PDT 24
Peak memory	207104 kb
Host	smart-56cbcff6-0d05-45eb-83b0-ca379800c8a9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68048 2654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.680482654
Directory	/workspace/1.usbdev_freq_phase/latest

Test location	/workspace/coverage/default/1.usbdev_in_iso.2262667692
Short name	T2819
Test name
Test status
Simulation time	245226055 ps
CPU time	1.32 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:05 PM PDT 24
Peak memory	215252 kb
Host	smart-c777194c-3af5-4071-9611-f40ca23b8cb7
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2262667692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.2262667692
Directory	/workspace/1.usbdev_in_iso/latest

Test location	/workspace/coverage/default/1.usbdev_in_stall.3190660714
Short name	T2247
Test name
Test status
Simulation time	145749142 ps
CPU time	0.81 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:11:07 PM PDT 24
Peak memory	206848 kb
Host	smart-cc14d86b-0858-4d06-80cc-25354e9f8662
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31906 60714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3190660714
Directory	/workspace/1.usbdev_in_stall/latest

Test location	/workspace/coverage/default/1.usbdev_in_trans.2954299552
Short name	T2032
Test name
Test status
Simulation time	245338044 ps
CPU time	0.99 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:11:07 PM PDT 24
Peak memory	206900 kb
Host	smart-0689d8d7-4b22-43a3-8709-b73666b89f24
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29542 99552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2954299552
Directory	/workspace/1.usbdev_in_trans/latest

Test location	/workspace/coverage/default/1.usbdev_invalid_sync.3769393833
Short name	T2549
Test name
Test status
Simulation time	4450925933 ps
CPU time	128.71 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:13:14 PM PDT 24
Peak memory	215408 kb
Host	smart-887b34a8-d530-4c18-acb9-ee721fb25356
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3769393833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.3769393833
Directory	/workspace/1.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/1.usbdev_iso_retraction.3520871660
Short name	T1255
Test name
Test status
Simulation time	11488431100 ps
CPU time	145.5 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:13:32 PM PDT 24
Peak memory	207096 kb
Host	smart-942ea221-8297-41db-a690-944c3093b5e6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3520871660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3520871660
Directory	/workspace/1.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/1.usbdev_link_in_err.1484272319
Short name	T1764
Test name
Test status
Simulation time	166237293 ps
CPU time	0.87 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:05 PM PDT 24
Peak memory	206952 kb
Host	smart-d3842de2-1d7e-491f-b415-c66a9bd09669
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14842 72319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.1484272319
Directory	/workspace/1.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/1.usbdev_link_suspend.1377928607
Short name	T1653
Test name
Test status
Simulation time	6139121089 ps
CPU time	8.64 seconds
Started	Aug 01 06:11:03 PM PDT 24
Finished	Aug 01 06:11:12 PM PDT 24
Peak memory	215456 kb
Host	smart-79e85565-acb1-46de-b988-65122bc59597
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13779 28607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.1377928607
Directory	/workspace/1.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/1.usbdev_low_speed_traffic.4162130645
Short name	T1937
Test name
Test status
Simulation time	3284858402 ps
CPU time	87.39 seconds
Started	Aug 01 06:11:08 PM PDT 24
Finished	Aug 01 06:12:35 PM PDT 24
Peak memory	217664 kb
Host	smart-794c8985-4b7f-4390-9e17-b1a64bb1ee9a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41621 30645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.4162130645
Directory	/workspace/1.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2112048702
Short name	T1173
Test name
Test status
Simulation time	3076958624 ps
CPU time	83.65 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:12:30 PM PDT 24
Peak memory	223560 kb
Host	smart-89313bec-c899-448d-9891-f7118bf0911d
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2112048702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2112048702
Directory	/workspace/1.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/1.usbdev_max_length_in_transaction.3367612196
Short name	T1814
Test name
Test status
Simulation time	244331112 ps
CPU time	0.95 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:11:07 PM PDT 24
Peak memory	206864 kb
Host	smart-d3519fea-cf11-4bd4-ab89-e60c4a7c7ee7
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3367612196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3367612196
Directory	/workspace/1.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/1.usbdev_max_length_out_transaction.3845945431
Short name	T1252
Test name
Test status
Simulation time	193229157 ps
CPU time	0.95 seconds
Started	Aug 01 06:11:08 PM PDT 24
Finished	Aug 01 06:11:09 PM PDT 24
Peak memory	206972 kb
Host	smart-f90e0df7-7bed-4d1a-a418-690850d3d4cb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38459 45431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.3845945431
Directory	/workspace/1.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.2934005278
Short name	T1081
Test name
Test status
Simulation time	2644467764 ps
CPU time	79.77 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:12:25 PM PDT 24
Peak memory	217148 kb
Host	smart-a7c80bf7-b161-4b7a-b8e4-c65be6741d93
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29340 05278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.2934005278
Directory	/workspace/1.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/1.usbdev_max_usb_traffic.2766706857
Short name	T2466
Test name
Test status
Simulation time	2730597325 ps
CPU time	21.91 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	223460 kb
Host	smart-39c09683-33f1-4983-a801-2f787d8f0b46
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2766706857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2766706857
Directory	/workspace/1.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3454442048
Short name	T2716
Test name
Test status
Simulation time	3288228652 ps
CPU time	26.24 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:11:32 PM PDT 24
Peak memory	215320 kb
Host	smart-22d8fd61-9865-40d5-9726-dca160720752
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3454442048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3454442048
Directory	/workspace/1.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/1.usbdev_min_length_in_transaction.2950396329
Short name	T2737
Test name
Test status
Simulation time	204210470 ps
CPU time	0.94 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:05 PM PDT 24
Peak memory	206944 kb
Host	smart-b69c800d-ceef-40ae-8bb3-69cbb4068838
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2950396329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2950396329
Directory	/workspace/1.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/1.usbdev_min_length_out_transaction.843372205
Short name	T494
Test name
Test status
Simulation time	153964097 ps
CPU time	0.83 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:11:06 PM PDT 24
Peak memory	206952 kb
Host	smart-1061da4e-4043-4c69-910c-6b1ec85f194e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84337 2205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.843372205
Directory	/workspace/1.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/1.usbdev_out_iso.2698101642
Short name	T160
Test name
Test status
Simulation time	165690622 ps
CPU time	0.92 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:11:07 PM PDT 24
Peak memory	206960 kb
Host	smart-5b479e36-7f8c-4826-a5a7-57b7c9bebda1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26981 01642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.2698101642
Directory	/workspace/1.usbdev_out_iso/latest

Test location	/workspace/coverage/default/1.usbdev_out_stall.462049737
Short name	T1233
Test name
Test status
Simulation time	218954834 ps
CPU time	0.95 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:11:08 PM PDT 24
Peak memory	206988 kb
Host	smart-bfd9674a-2417-4f4f-acc1-e8f75f60dfe6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46204 9737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.462049737
Directory	/workspace/1.usbdev_out_stall/latest

Test location	/workspace/coverage/default/1.usbdev_out_trans_nak.3318756504
Short name	T1249
Test name
Test status
Simulation time	198074231 ps
CPU time	0.87 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:11:06 PM PDT 24
Peak memory	206944 kb
Host	smart-5faba6f2-3fd0-4543-ba50-1ca36cd34389
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33187 56504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3318756504
Directory	/workspace/1.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/1.usbdev_pending_in_trans.478203603
Short name	T1042
Test name
Test status
Simulation time	212900784 ps
CPU time	0.97 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:06 PM PDT 24
Peak memory	206932 kb
Host	smart-75b0cbfa-d909-45c4-b484-5619fc39c142
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47820 3603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.478203603
Directory	/workspace/1.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/1.usbdev_phy_config_pinflip.3161660795
Short name	T776
Test name
Test status
Simulation time	210228490 ps
CPU time	0.99 seconds
Started	Aug 01 06:11:03 PM PDT 24
Finished	Aug 01 06:11:04 PM PDT 24
Peak memory	206948 kb
Host	smart-9c925339-f9c8-4bc7-8859-36aa1d403a52
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3161660795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3161660795
Directory	/workspace/1.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3199243263
Short name	T2701
Test name
Test status
Simulation time	221969081 ps
CPU time	1.02 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:11:07 PM PDT 24
Peak memory	206916 kb
Host	smart-8fbbe3d9-d69d-42c6-9f86-d105b9ee11e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31992 43263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3199243263
Directory	/workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location	/workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3930029204
Short name	T1545
Test name
Test status
Simulation time	143972206 ps
CPU time	0.84 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:11:06 PM PDT 24
Peak memory	206904 kb
Host	smart-d7ae0a95-658f-4121-b577-2755b92dfc6c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39300 29204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3930029204
Directory	/workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/1.usbdev_phy_pins_sense.1735710433
Short name	T1247
Test name
Test status
Simulation time	35097989 ps
CPU time	0.66 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:05 PM PDT 24
Peak memory	206884 kb
Host	smart-af1f1d3b-2edb-45cc-88c5-efae9a02d214
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17357 10433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.1735710433
Directory	/workspace/1.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/1.usbdev_pkt_buffer.3018832226
Short name	T2761
Test name
Test status
Simulation time	10055635594 ps
CPU time	27.57 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:11:33 PM PDT 24
Peak memory	219708 kb
Host	smart-c3e68b33-967e-4649-9ae8-2afdd4fc56fd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30188 32226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.3018832226
Directory	/workspace/1.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/1.usbdev_pkt_received.2524557244
Short name	T556
Test name
Test status
Simulation time	229015515 ps
CPU time	0.94 seconds
Started	Aug 01 06:11:06 PM PDT 24
Finished	Aug 01 06:11:08 PM PDT 24
Peak memory	206980 kb
Host	smart-6bd2e58f-5199-49bb-b8f5-580121cb4a69
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25245 57244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.2524557244
Directory	/workspace/1.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/1.usbdev_pkt_sent.3317340801
Short name	T2079
Test name
Test status
Simulation time	201178654 ps
CPU time	0.91 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:11:07 PM PDT 24
Peak memory	206920 kb
Host	smart-58f3ae9e-1fd3-4ebe-b3cf-4cfe4eb9bc1c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33173 40801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.3317340801
Directory	/workspace/1.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/1.usbdev_rand_bus_disconnects.2512877377
Short name	T2093
Test name
Test status
Simulation time	6129813362 ps
CPU time	29.15 seconds
Started	Aug 01 06:11:08 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	218636 kb
Host	smart-d486255b-2efc-44c5-9ef6-17d25f42396f
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512877377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2512877377
Directory	/workspace/1.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/1.usbdev_rand_bus_resets.2587739022
Short name	T686
Test name
Test status
Simulation time	6910447208 ps
CPU time	33.49 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:11:38 PM PDT 24
Peak memory	223460 kb
Host	smart-d47915b0-fa67-43dc-b760-9d5078b53915
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587739022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2587739022
Directory	/workspace/1.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/1.usbdev_rand_suspends.2493072877
Short name	T1873
Test name
Test status
Simulation time	5381777416 ps
CPU time	52.19 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:12:14 PM PDT 24
Peak memory	215352 kb
Host	smart-239825fa-90f7-464b-8134-bba51d44d4b0
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493072877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2493072877
Directory	/workspace/1.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/1.usbdev_random_length_in_transaction.1813939938
Short name	T700
Test name
Test status
Simulation time	179898509 ps
CPU time	0.86 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:05 PM PDT 24
Peak memory	206852 kb
Host	smart-43a9ed19-75ba-4de4-b24b-bfd4d2bdd117
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18139 39938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.1813939938
Directory	/workspace/1.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/1.usbdev_random_length_out_transaction.82199109
Short name	T1947
Test name
Test status
Simulation time	168804947 ps
CPU time	0.92 seconds
Started	Aug 01 06:11:04 PM PDT 24
Finished	Aug 01 06:11:05 PM PDT 24
Peak memory	206936 kb
Host	smart-521b99a4-df27-4787-ae4d-7c3d0ad817d1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82199 109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.82199109
Directory	/workspace/1.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/1.usbdev_rx_crc_err.350918893
Short name	T2162
Test name
Test status
Simulation time	141283240 ps
CPU time	0.84 seconds
Started	Aug 01 06:11:20 PM PDT 24
Finished	Aug 01 06:11:21 PM PDT 24
Peak memory	206888 kb
Host	smart-d7659b49-a307-4d76-873e-6d31dfb81c6e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091 8893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.350918893
Directory	/workspace/1.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/1.usbdev_rx_full.3565768642
Short name	T967
Test name
Test status
Simulation time	312009664 ps
CPU time	1.36 seconds
Started	Aug 01 06:11:20 PM PDT 24
Finished	Aug 01 06:11:21 PM PDT 24
Peak memory	206956 kb
Host	smart-39ecf64e-333e-42da-a96e-abf182e4a4bc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35657 68642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.3565768642
Directory	/workspace/1.usbdev_rx_full/latest

Test location	/workspace/coverage/default/1.usbdev_rx_pid_err.231691691
Short name	T62
Test name
Test status
Simulation time	235233471 ps
CPU time	1.01 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:11:23 PM PDT 24
Peak memory	206964 kb
Host	smart-8038b8e2-2b04-4726-bb25-fedaf63d556a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23169 1691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.231691691
Directory	/workspace/1.usbdev_rx_pid_err/latest

Test location	/workspace/coverage/default/1.usbdev_sec_cm.4108920783
Short name	T125
Test name
Test status
Simulation time	254283592 ps
CPU time	1.14 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:11:24 PM PDT 24
Peak memory	222884 kb
Host	smart-6e06fa16-3a2f-42d0-91c0-694fa50fbea8
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4108920783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.4108920783
Directory	/workspace/1.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/1.usbdev_setup_priority.300346642
Short name	T2181
Test name
Test status
Simulation time	440702113 ps
CPU time	1.51 seconds
Started	Aug 01 06:11:19 PM PDT 24
Finished	Aug 01 06:11:21 PM PDT 24
Peak memory	206892 kb
Host	smart-c334ff3c-d3f2-48a9-ba3d-2f483d546d88
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30034 6642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.300346642
Directory	/workspace/1.usbdev_setup_priority/latest

Test location	/workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.2876428444
Short name	T2084
Test name
Test status
Simulation time	308618862 ps
CPU time	1.12 seconds
Started	Aug 01 06:11:19 PM PDT 24
Finished	Aug 01 06:11:20 PM PDT 24
Peak memory	206924 kb
Host	smart-9a20406b-0069-409d-9ae4-be2e65478b29
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28764 28444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.2876428444
Directory	/workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location	/workspace/coverage/default/1.usbdev_setup_stage.2709844677
Short name	T2122
Test name
Test status
Simulation time	148946284 ps
CPU time	0.85 seconds
Started	Aug 01 06:11:38 PM PDT 24
Finished	Aug 01 06:11:39 PM PDT 24
Peak memory	206900 kb
Host	smart-ebb9fc48-0231-452e-aaa3-42c92c27592c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27098 44677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2709844677
Directory	/workspace/1.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/1.usbdev_setup_trans_ignored.430951164
Short name	T2345
Test name
Test status
Simulation time	159790149 ps
CPU time	0.88 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:11:23 PM PDT 24
Peak memory	207176 kb
Host	smart-152cc507-8347-40b5-9296-f39e7c31b92c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43095 1164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.430951164
Directory	/workspace/1.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/1.usbdev_smoke.1824093090
Short name	T923
Test name
Test status
Simulation time	209206957 ps
CPU time	1.02 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	206952 kb
Host	smart-c2289cb2-f861-4a1d-a2df-a4ae7df6eb62
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18240 93090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.1824093090
Directory	/workspace/1.usbdev_smoke/latest

Test location	/workspace/coverage/default/1.usbdev_spurious_pids_ignored.3085897166
Short name	T1715
Test name
Test status
Simulation time	2906104004 ps
CPU time	21.03 seconds
Started	Aug 01 06:11:20 PM PDT 24
Finished	Aug 01 06:11:41 PM PDT 24
Peak memory	223500 kb
Host	smart-7a78ab47-cf1b-4826-a427-905dbd48f687
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3085897166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.3085897166
Directory	/workspace/1.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/1.usbdev_stall_priority_over_nak.2050082083
Short name	T996
Test name
Test status
Simulation time	172467068 ps
CPU time	0.89 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	206928 kb
Host	smart-a0d6f9d3-104e-466d-80ec-960ee313a6cc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20500 82083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2050082083
Directory	/workspace/1.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/1.usbdev_stall_trans.2102729563
Short name	T1025
Test name
Test status
Simulation time	167310591 ps
CPU time	0.93 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:25 PM PDT 24
Peak memory	206968 kb
Host	smart-9f74d3ca-fd65-4d57-a83f-ca6d79e927d3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21027 29563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.2102729563
Directory	/workspace/1.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/1.usbdev_stream_len_max.4273084095
Short name	T1469
Test name
Test status
Simulation time	684824084 ps
CPU time	2.11 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:11:23 PM PDT 24
Peak memory	206888 kb
Host	smart-e481eef2-0d58-464b-a881-b6081566c905
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42730 84095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.4273084095
Directory	/workspace/1.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/1.usbdev_streaming_out.4257437476
Short name	T2170
Test name
Test status
Simulation time	2569768693 ps
CPU time	74.04 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:12:39 PM PDT 24
Peak memory	215376 kb
Host	smart-ef9457d0-b578-4336-9a2b-08dfd152603d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42574 37476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.4257437476
Directory	/workspace/1.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.3018282202
Short name	T1830
Test name
Test status
Simulation time	326733053 ps
CPU time	4.58 seconds
Started	Aug 01 06:11:05 PM PDT 24
Finished	Aug 01 06:11:10 PM PDT 24
Peak memory	207124 kb
Host	smart-46f5a936-aa57-4b81-ace9-7d2b743daa7f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018282202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host _handshake.3018282202
Directory	/workspace/1.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/10.usbdev_alert_test.469990233
Short name	T2320
Test name
Test status
Simulation time	37654876 ps
CPU time	0.67 seconds
Started	Aug 01 06:13:21 PM PDT 24
Finished	Aug 01 06:13:22 PM PDT 24
Peak memory	206968 kb
Host	smart-9908e914-085b-444a-bcac-e3795993daa5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=469990233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.469990233
Directory	/workspace/10.usbdev_alert_test/latest

Test location	/workspace/coverage/default/10.usbdev_av_buffer.4087285201
Short name	T1869
Test name
Test status
Simulation time	152111541 ps
CPU time	0.85 seconds
Started	Aug 01 06:13:21 PM PDT 24
Finished	Aug 01 06:13:22 PM PDT 24
Peak memory	206896 kb
Host	smart-6c211fea-31ea-4255-9e08-c650f13731a6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40872 85201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.4087285201
Directory	/workspace/10.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/10.usbdev_bitstuff_err.2235569957
Short name	T1123
Test name
Test status
Simulation time	152863331 ps
CPU time	0.88 seconds
Started	Aug 01 06:13:22 PM PDT 24
Finished	Aug 01 06:13:23 PM PDT 24
Peak memory	206720 kb
Host	smart-29ec2e61-8e88-40ce-880d-44139321ad11
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22355 69957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.2235569957
Directory	/workspace/10.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/10.usbdev_data_toggle_clear.2747486182
Short name	T234
Test name
Test status
Simulation time	423748721 ps
CPU time	1.48 seconds
Started	Aug 01 06:13:24 PM PDT 24
Finished	Aug 01 06:13:26 PM PDT 24
Peak memory	206948 kb
Host	smart-a2609b5d-c868-4c3b-821a-12d70be4425f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27474 86182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2747486182
Directory	/workspace/10.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/10.usbdev_data_toggle_restore.1054292598
Short name	T1353
Test name
Test status
Simulation time	414643842 ps
CPU time	1.3 seconds
Started	Aug 01 06:13:23 PM PDT 24
Finished	Aug 01 06:13:24 PM PDT 24
Peak memory	206924 kb
Host	smart-38adce84-72c4-4931-aef0-06d529681b7f
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1054292598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1054292598
Directory	/workspace/10.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/10.usbdev_device_address.1701213145
Short name	T2717
Test name
Test status
Simulation time	31626030905 ps
CPU time	45.33 seconds
Started	Aug 01 06:13:23 PM PDT 24
Finished	Aug 01 06:14:08 PM PDT 24
Peak memory	207092 kb
Host	smart-f3553a03-8abc-44d3-9270-1f2c8ec91b64
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17012 13145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1701213145
Directory	/workspace/10.usbdev_device_address/latest

Test location	/workspace/coverage/default/10.usbdev_device_timeout.627454733
Short name	T586
Test name
Test status
Simulation time	1070056690 ps
CPU time	22.56 seconds
Started	Aug 01 06:13:23 PM PDT 24
Finished	Aug 01 06:13:46 PM PDT 24
Peak memory	207120 kb
Host	smart-67f91a9e-70e8-460f-98a2-0a3207603939
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627454733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.627454733
Directory	/workspace/10.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/10.usbdev_disable_endpoint.3474955822
Short name	T1219
Test name
Test status
Simulation time	863955447 ps
CPU time	1.99 seconds
Started	Aug 01 06:13:24 PM PDT 24
Finished	Aug 01 06:13:26 PM PDT 24
Peak memory	206904 kb
Host	smart-bd20a65b-8f7c-4c0c-881b-2f751aa7de64
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34749 55822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3474955822
Directory	/workspace/10.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/10.usbdev_disconnected.3335393392
Short name	T2537
Test name
Test status
Simulation time	154891780 ps
CPU time	0.83 seconds
Started	Aug 01 06:13:20 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	206920 kb
Host	smart-8744a5ae-bda8-4ff2-ae80-ed38f1890bda
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33353 93392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3335393392
Directory	/workspace/10.usbdev_disconnected/latest

Test location	/workspace/coverage/default/10.usbdev_enable.1864063382
Short name	T867
Test name
Test status
Simulation time	70676936 ps
CPU time	0.73 seconds
Started	Aug 01 06:13:26 PM PDT 24
Finished	Aug 01 06:13:27 PM PDT 24
Peak memory	206896 kb
Host	smart-46acadf7-6793-4149-8f26-ceced5767f86
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18640 63382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.1864063382
Directory	/workspace/10.usbdev_enable/latest

Test location	/workspace/coverage/default/10.usbdev_endpoint_access.1371135237
Short name	T1542
Test name
Test status
Simulation time	865382834 ps
CPU time	2.38 seconds
Started	Aug 01 06:13:23 PM PDT 24
Finished	Aug 01 06:13:26 PM PDT 24
Peak memory	207140 kb
Host	smart-5c87bfcf-48e8-44c6-a7a9-d5627e2992af
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13711 35237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.1371135237
Directory	/workspace/10.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/10.usbdev_endpoint_types.3593035069
Short name	T326
Test name
Test status
Simulation time	779293829 ps
CPU time	1.91 seconds
Started	Aug 01 06:13:22 PM PDT 24
Finished	Aug 01 06:13:24 PM PDT 24
Peak memory	206664 kb
Host	smart-15093c21-ece8-4508-8049-d0a339a0a3b6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3593035069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.3593035069
Directory	/workspace/10.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/10.usbdev_fifo_rst.2866815692
Short name	T2330
Test name
Test status
Simulation time	276724532 ps
CPU time	1.95 seconds
Started	Aug 01 06:13:22 PM PDT 24
Finished	Aug 01 06:13:24 PM PDT 24
Peak memory	206872 kb
Host	smart-4df20a89-d497-434e-a69a-d3b12c3f1975
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28668 15692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2866815692
Directory	/workspace/10.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/10.usbdev_in_iso.274447643
Short name	T1337
Test name
Test status
Simulation time	169798234 ps
CPU time	0.92 seconds
Started	Aug 01 06:13:21 PM PDT 24
Finished	Aug 01 06:13:22 PM PDT 24
Peak memory	206968 kb
Host	smart-7d05fc80-a67c-487b-ae08-8427e9b8e17c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=274447643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.274447643
Directory	/workspace/10.usbdev_in_iso/latest

Test location	/workspace/coverage/default/10.usbdev_in_stall.195032935
Short name	T1333
Test name
Test status
Simulation time	150915787 ps
CPU time	0.85 seconds
Started	Aug 01 06:13:17 PM PDT 24
Finished	Aug 01 06:13:18 PM PDT 24
Peak memory	206876 kb
Host	smart-5a0d0c79-2a18-431f-9ac7-e345c4ba6ae8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19503 2935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.195032935
Directory	/workspace/10.usbdev_in_stall/latest

Test location	/workspace/coverage/default/10.usbdev_in_trans.2624081479
Short name	T32
Test name
Test status
Simulation time	218020104 ps
CPU time	1.04 seconds
Started	Aug 01 06:13:23 PM PDT 24
Finished	Aug 01 06:13:24 PM PDT 24
Peak memory	206920 kb
Host	smart-4747dc0a-fff2-415b-9bfa-fd94156d2c9c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26240 81479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2624081479
Directory	/workspace/10.usbdev_in_trans/latest

Test location	/workspace/coverage/default/10.usbdev_invalid_sync.1576565639
Short name	T2886
Test name
Test status
Simulation time	3622598024 ps
CPU time	29.54 seconds
Started	Aug 01 06:13:21 PM PDT 24
Finished	Aug 01 06:13:50 PM PDT 24
Peak memory	217364 kb
Host	smart-fee13bd0-8c31-4803-9aa5-b532ab92337f
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1576565639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1576565639
Directory	/workspace/10.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/10.usbdev_iso_retraction.3285340950
Short name	T2028
Test name
Test status
Simulation time	12481167181 ps
CPU time	151.87 seconds
Started	Aug 01 06:13:28 PM PDT 24
Finished	Aug 01 06:16:01 PM PDT 24
Peak memory	207096 kb
Host	smart-db95b537-0a2b-4d55-8df1-e11279bfb663
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3285340950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.3285340950
Directory	/workspace/10.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/10.usbdev_link_in_err.3985680582
Short name	T2539
Test name
Test status
Simulation time	226661262 ps
CPU time	1.03 seconds
Started	Aug 01 06:13:29 PM PDT 24
Finished	Aug 01 06:13:30 PM PDT 24
Peak memory	206948 kb
Host	smart-9d7162db-72dc-4702-a0b7-b6522653661b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39856 80582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3985680582
Directory	/workspace/10.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/10.usbdev_low_speed_traffic.784065724
Short name	T453
Test name
Test status
Simulation time	3558970834 ps
CPU time	35.14 seconds
Started	Aug 01 06:13:24 PM PDT 24
Finished	Aug 01 06:13:59 PM PDT 24
Peak memory	223572 kb
Host	smart-b4b4b425-4df6-4f75-844b-8376b4b2d870
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78406 5724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.784065724
Directory	/workspace/10.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/10.usbdev_max_inter_pkt_delay.718239217
Short name	T771
Test name
Test status
Simulation time	4116729690 ps
CPU time	118.53 seconds
Started	Aug 01 06:13:22 PM PDT 24
Finished	Aug 01 06:15:21 PM PDT 24
Peak memory	215364 kb
Host	smart-54968c3f-4040-4918-a3e2-ea62529731ad
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=718239217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.718239217
Directory	/workspace/10.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/10.usbdev_max_length_in_transaction.1639052115
Short name	T2844
Test name
Test status
Simulation time	293312694 ps
CPU time	1.08 seconds
Started	Aug 01 06:13:21 PM PDT 24
Finished	Aug 01 06:13:22 PM PDT 24
Peak memory	206964 kb
Host	smart-7d76e7e4-4e49-4e39-8cc8-7e95dc79d54c
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1639052115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1639052115
Directory	/workspace/10.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/10.usbdev_max_length_out_transaction.469367793
Short name	T2677
Test name
Test status
Simulation time	194564909 ps
CPU time	0.93 seconds
Started	Aug 01 06:13:20 PM PDT 24
Finished	Aug 01 06:13:22 PM PDT 24
Peak memory	206972 kb
Host	smart-b2cbf659-1119-49c8-8d97-6de83d4e81ec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46936 7793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.469367793
Directory	/workspace/10.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.2614282425
Short name	T2847
Test name
Test status
Simulation time	3647730458 ps
CPU time	27.83 seconds
Started	Aug 01 06:13:22 PM PDT 24
Finished	Aug 01 06:13:50 PM PDT 24
Peak memory	223452 kb
Host	smart-4a7b29cd-3edf-43a5-b45c-370f226f719b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26142 82425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.2614282425
Directory	/workspace/10.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/10.usbdev_max_usb_traffic.438171755
Short name	T157
Test name
Test status
Simulation time	2754432911 ps
CPU time	84.09 seconds
Started	Aug 01 06:13:19 PM PDT 24
Finished	Aug 01 06:14:44 PM PDT 24
Peak memory	223484 kb
Host	smart-ae7d45f7-efdf-4161-9a39-1fa8c51a661b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=438171755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.438171755
Directory	/workspace/10.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/10.usbdev_min_inter_pkt_delay.2006489350
Short name	T1626
Test name
Test status
Simulation time	2997813225 ps
CPU time	87.03 seconds
Started	Aug 01 06:13:28 PM PDT 24
Finished	Aug 01 06:14:56 PM PDT 24
Peak memory	216604 kb
Host	smart-9bce417a-8b06-43e8-ac28-1bdbf08f40da
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2006489350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.2006489350
Directory	/workspace/10.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/10.usbdev_min_length_in_transaction.3688730428
Short name	T892
Test name
Test status
Simulation time	153171050 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:24 PM PDT 24
Finished	Aug 01 06:13:25 PM PDT 24
Peak memory	206928 kb
Host	smart-c2675d22-3f69-48c9-a5fc-d5cc4bcbaa32
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3688730428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3688730428
Directory	/workspace/10.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/10.usbdev_min_length_out_transaction.4025527905
Short name	T2348
Test name
Test status
Simulation time	162074608 ps
CPU time	0.89 seconds
Started	Aug 01 06:13:23 PM PDT 24
Finished	Aug 01 06:13:24 PM PDT 24
Peak memory	206988 kb
Host	smart-0cd77181-bf67-45bf-80b8-8076a9c47c00
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40255 27905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.4025527905
Directory	/workspace/10.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/10.usbdev_out_iso.879681010
Short name	T1117
Test name
Test status
Simulation time	163331581 ps
CPU time	0.86 seconds
Started	Aug 01 06:13:21 PM PDT 24
Finished	Aug 01 06:13:22 PM PDT 24
Peak memory	206932 kb
Host	smart-898d8ea2-6670-4a50-9c83-bf7982289151
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87968 1010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.879681010
Directory	/workspace/10.usbdev_out_iso/latest

Test location	/workspace/coverage/default/10.usbdev_out_stall.1063614618
Short name	T1882
Test name
Test status
Simulation time	177105667 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:30 PM PDT 24
Finished	Aug 01 06:13:31 PM PDT 24
Peak memory	206972 kb
Host	smart-6f022c42-7c8d-4963-a83d-9238387466ce
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10636 14618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1063614618
Directory	/workspace/10.usbdev_out_stall/latest

Test location	/workspace/coverage/default/10.usbdev_out_trans_nak.1818021844
Short name	T1883
Test name
Test status
Simulation time	179468071 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:21 PM PDT 24
Finished	Aug 01 06:13:22 PM PDT 24
Peak memory	206956 kb
Host	smart-9ecf9e11-13a4-4f88-a85c-4f6d09603285
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18180 21844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1818021844
Directory	/workspace/10.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/10.usbdev_pending_in_trans.1549292337
Short name	T1948
Test name
Test status
Simulation time	160243541 ps
CPU time	0.84 seconds
Started	Aug 01 06:13:27 PM PDT 24
Finished	Aug 01 06:13:28 PM PDT 24
Peak memory	206928 kb
Host	smart-336bb880-9651-4bfc-9395-b17861f6c16b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492 92337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.1549292337
Directory	/workspace/10.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/10.usbdev_phy_config_pinflip.3695786041
Short name	T2295
Test name
Test status
Simulation time	183760136 ps
CPU time	1 seconds
Started	Aug 01 06:13:20 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	206968 kb
Host	smart-0b616d47-cfb0-4c35-9ee6-1e4bca169304
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3695786041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3695786041
Directory	/workspace/10.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3872106974
Short name	T1675
Test name
Test status
Simulation time	146699956 ps
CPU time	0.81 seconds
Started	Aug 01 06:13:25 PM PDT 24
Finished	Aug 01 06:13:26 PM PDT 24
Peak memory	206904 kb
Host	smart-283d24cd-ba2d-470c-bd19-cca745917da4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38721 06974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3872106974
Directory	/workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/10.usbdev_phy_pins_sense.1322038195
Short name	T995
Test name
Test status
Simulation time	36540627 ps
CPU time	0.67 seconds
Started	Aug 01 06:13:27 PM PDT 24
Finished	Aug 01 06:13:28 PM PDT 24
Peak memory	206872 kb
Host	smart-bcf3cb06-00e7-486e-90fe-66c10a820219
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13220 38195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.1322038195
Directory	/workspace/10.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/10.usbdev_pkt_buffer.1761789525
Short name	T1018
Test name
Test status
Simulation time	15968599173 ps
CPU time	39.92 seconds
Started	Aug 01 06:13:25 PM PDT 24
Finished	Aug 01 06:14:05 PM PDT 24
Peak memory	215424 kb
Host	smart-92f2a227-0ac0-4055-92b2-a376cc74280f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17617 89525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1761789525
Directory	/workspace/10.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/10.usbdev_pkt_received.508199691
Short name	T2724
Test name
Test status
Simulation time	174245361 ps
CPU time	0.92 seconds
Started	Aug 01 06:13:21 PM PDT 24
Finished	Aug 01 06:13:22 PM PDT 24
Peak memory	206916 kb
Host	smart-aa646d54-45f9-42d7-b42d-9a61e7e2bc0a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50819 9691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.508199691
Directory	/workspace/10.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/10.usbdev_pkt_sent.3406466508
Short name	T894
Test name
Test status
Simulation time	197684527 ps
CPU time	0.89 seconds
Started	Aug 01 06:13:24 PM PDT 24
Finished	Aug 01 06:13:25 PM PDT 24
Peak memory	206928 kb
Host	smart-6f7321b4-2d92-4c1e-89c3-3c97111ff840
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34064 66508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3406466508
Directory	/workspace/10.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/10.usbdev_random_length_in_transaction.1797499540
Short name	T1499
Test name
Test status
Simulation time	223837251 ps
CPU time	0.97 seconds
Started	Aug 01 06:13:26 PM PDT 24
Finished	Aug 01 06:13:27 PM PDT 24
Peak memory	206936 kb
Host	smart-42eca487-719e-43cf-9d5a-dacba1cd9387
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17974 99540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1797499540
Directory	/workspace/10.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/10.usbdev_random_length_out_transaction.4036442580
Short name	T1828
Test name
Test status
Simulation time	260761296 ps
CPU time	1 seconds
Started	Aug 01 06:13:20 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	206936 kb
Host	smart-391f37d7-5586-4fab-aa49-c8c01c730e4d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364 42580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.4036442580
Directory	/workspace/10.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/10.usbdev_rx_crc_err.1365972707
Short name	T1633
Test name
Test status
Simulation time	141841111 ps
CPU time	0.82 seconds
Started	Aug 01 06:13:26 PM PDT 24
Finished	Aug 01 06:13:27 PM PDT 24
Peak memory	206916 kb
Host	smart-44e818eb-6ea3-495a-a4f9-f774d94f7764
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13659 72707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1365972707
Directory	/workspace/10.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/10.usbdev_setup_stage.1199793310
Short name	T793
Test name
Test status
Simulation time	155003986 ps
CPU time	0.81 seconds
Started	Aug 01 06:13:20 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	206904 kb
Host	smart-e81e3a00-ecae-4242-83ae-c5ebbbfdccd9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11997 93310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.1199793310
Directory	/workspace/10.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/10.usbdev_setup_trans_ignored.2422871089
Short name	T2291
Test name
Test status
Simulation time	145534441 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:22 PM PDT 24
Finished	Aug 01 06:13:23 PM PDT 24
Peak memory	206956 kb
Host	smart-4f93eb09-a049-4be9-86ec-94a5d2a5d5f3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24228 71089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.2422871089
Directory	/workspace/10.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/10.usbdev_smoke.2164289406
Short name	T2851
Test name
Test status
Simulation time	242792565 ps
CPU time	1.01 seconds
Started	Aug 01 06:13:29 PM PDT 24
Finished	Aug 01 06:13:30 PM PDT 24
Peak memory	206956 kb
Host	smart-dc796736-d38f-4d37-b9c2-8ed3dc3a4e6c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21642 89406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2164289406
Directory	/workspace/10.usbdev_smoke/latest

Test location	/workspace/coverage/default/10.usbdev_spurious_pids_ignored.445683676
Short name	T2455
Test name
Test status
Simulation time	2615094154 ps
CPU time	71.51 seconds
Started	Aug 01 06:13:29 PM PDT 24
Finished	Aug 01 06:14:40 PM PDT 24
Peak memory	216984 kb
Host	smart-92f811ea-d9ba-4ef5-85c9-795a70648574
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=445683676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.445683676
Directory	/workspace/10.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/10.usbdev_stall_priority_over_nak.2303841539
Short name	T1569
Test name
Test status
Simulation time	250551656 ps
CPU time	1.01 seconds
Started	Aug 01 06:13:22 PM PDT 24
Finished	Aug 01 06:13:23 PM PDT 24
Peak memory	206952 kb
Host	smart-e76bc986-9cc3-4a5a-98d4-d0fa3ac2eebd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23038 41539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2303841539
Directory	/workspace/10.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/10.usbdev_stall_trans.3384299681
Short name	T2261
Test name
Test status
Simulation time	143882301 ps
CPU time	0.84 seconds
Started	Aug 01 06:13:29 PM PDT 24
Finished	Aug 01 06:13:30 PM PDT 24
Peak memory	206896 kb
Host	smart-9ca2046c-c289-4be5-8354-d055cc12d983
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33842 99681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.3384299681
Directory	/workspace/10.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/10.usbdev_stream_len_max.3347508752
Short name	T866
Test name
Test status
Simulation time	1195904943 ps
CPU time	2.7 seconds
Started	Aug 01 06:13:29 PM PDT 24
Finished	Aug 01 06:13:32 PM PDT 24
Peak memory	207028 kb
Host	smart-72579559-6535-4f8c-a04f-31aa98fe6847
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475 08752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.3347508752
Directory	/workspace/10.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/10.usbdev_streaming_out.1577804105
Short name	T2494
Test name
Test status
Simulation time	2591791382 ps
CPU time	25.73 seconds
Started	Aug 01 06:13:21 PM PDT 24
Finished	Aug 01 06:13:47 PM PDT 24
Peak memory	216996 kb
Host	smart-3ae60806-4a35-4e03-acf2-5d00ce6ccf7f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15778 04105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.1577804105
Directory	/workspace/10.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.2995397882
Short name	T1517
Test name
Test status
Simulation time	3476800966 ps
CPU time	31.05 seconds
Started	Aug 01 06:13:20 PM PDT 24
Finished	Aug 01 06:13:51 PM PDT 24
Peak memory	207164 kb
Host	smart-59a745ee-d925-458f-9c45-3194507de421
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995397882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos t_handshake.2995397882
Directory	/workspace/10.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/100.usbdev_endpoint_types.3899631601
Short name	T399
Test name
Test status
Simulation time	182423169 ps
CPU time	1 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206940 kb
Host	smart-15c91561-23f9-4c51-a58e-e10cfb4c4095
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3899631601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.3899631601
Directory	/workspace/100.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/101.usbdev_endpoint_types.2159062624
Short name	T2449
Test name
Test status
Simulation time	328715965 ps
CPU time	1.25 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:06 PM PDT 24
Peak memory	206920 kb
Host	smart-418bd2f1-67e8-464e-87b8-ba8a6cd64726
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2159062624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.2159062624
Directory	/workspace/101.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/102.usbdev_endpoint_types.1551688921
Short name	T408
Test name
Test status
Simulation time	231689213 ps
CPU time	1.05 seconds
Started	Aug 01 06:20:16 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	206888 kb
Host	smart-26b8cacf-5ac3-45b1-a081-b534ab677b68
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1551688921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.1551688921
Directory	/workspace/102.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/103.usbdev_endpoint_types.703282266
Short name	T2876
Test name
Test status
Simulation time	370288718 ps
CPU time	1.24 seconds
Started	Aug 01 06:20:25 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206916 kb
Host	smart-0530b49f-b6e8-4a99-ab30-2f86711aa2d9
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=703282266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.703282266
Directory	/workspace/103.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/104.usbdev_endpoint_types.1391691292
Short name	T577
Test name
Test status
Simulation time	184975288 ps
CPU time	0.88 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:06 PM PDT 24
Peak memory	206872 kb
Host	smart-aac30243-86da-4b6f-a30e-9ebd8f722490
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1391691292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.1391691292
Directory	/workspace/104.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/105.usbdev_endpoint_types.903056152
Short name	T402
Test name
Test status
Simulation time	617514094 ps
CPU time	1.54 seconds
Started	Aug 01 06:20:05 PM PDT 24
Finished	Aug 01 06:20:06 PM PDT 24
Peak memory	206872 kb
Host	smart-90e4ba4e-12e3-4f9e-a21c-eb92993af582
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=903056152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.903056152
Directory	/workspace/105.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/106.usbdev_endpoint_types.471195597
Short name	T339
Test name
Test status
Simulation time	840623492 ps
CPU time	1.85 seconds
Started	Aug 01 06:20:07 PM PDT 24
Finished	Aug 01 06:20:09 PM PDT 24
Peak memory	206908 kb
Host	smart-fce48e22-a525-4359-a4a7-d165ff91f1cf
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=471195597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.471195597
Directory	/workspace/106.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/108.usbdev_endpoint_types.484928831
Short name	T398
Test name
Test status
Simulation time	417079741 ps
CPU time	1.27 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206912 kb
Host	smart-06448990-3678-49da-b437-51682d4b7247
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=484928831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.484928831
Directory	/workspace/108.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/11.usbdev_alert_test.1182058598
Short name	T507
Test name
Test status
Simulation time	53580629 ps
CPU time	0.68 seconds
Started	Aug 01 06:13:39 PM PDT 24
Finished	Aug 01 06:13:40 PM PDT 24
Peak memory	206808 kb
Host	smart-7dc69b02-8987-4f98-99c1-74f6076ee671
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1182058598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1182058598
Directory	/workspace/11.usbdev_alert_test/latest

Test location	/workspace/coverage/default/11.usbdev_av_buffer.2581378274
Short name	T1503
Test name
Test status
Simulation time	188236808 ps
CPU time	0.88 seconds
Started	Aug 01 06:13:25 PM PDT 24
Finished	Aug 01 06:13:26 PM PDT 24
Peak memory	206912 kb
Host	smart-2604f841-5025-431c-ab81-5f8d95bffc8f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25813 78274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2581378274
Directory	/workspace/11.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/11.usbdev_bitstuff_err.1439309620
Short name	T2556
Test name
Test status
Simulation time	146906301 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:20 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	206904 kb
Host	smart-3792a21c-c1d5-4b1f-9d18-9e5a83a3574d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14393 09620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1439309620
Directory	/workspace/11.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/11.usbdev_data_toggle_clear.2629841987
Short name	T643
Test name
Test status
Simulation time	489037416 ps
CPU time	1.6 seconds
Started	Aug 01 06:13:28 PM PDT 24
Finished	Aug 01 06:13:30 PM PDT 24
Peak memory	206856 kb
Host	smart-62946ca3-43fe-4fe8-af77-bc2c6f0ba0c8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26298 41987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.2629841987
Directory	/workspace/11.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/11.usbdev_data_toggle_restore.1869618745
Short name	T19
Test name
Test status
Simulation time	753542169 ps
CPU time	2.14 seconds
Started	Aug 01 06:13:32 PM PDT 24
Finished	Aug 01 06:13:34 PM PDT 24
Peak memory	207168 kb
Host	smart-8429d51a-caf9-45b4-921f-2a1825d9efbd
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1869618745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1869618745
Directory	/workspace/11.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/11.usbdev_device_address.439571045
Short name	T455
Test name
Test status
Simulation time	55320654193 ps
CPU time	82.51 seconds
Started	Aug 01 06:13:31 PM PDT 24
Finished	Aug 01 06:14:54 PM PDT 24
Peak memory	207184 kb
Host	smart-4b6ce863-d44f-44bc-b9d1-25be24d9b68f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43957 1045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.439571045
Directory	/workspace/11.usbdev_device_address/latest

Test location	/workspace/coverage/default/11.usbdev_device_timeout.373553791
Short name	T548
Test name
Test status
Simulation time	889140943 ps
CPU time	19.44 seconds
Started	Aug 01 06:13:31 PM PDT 24
Finished	Aug 01 06:13:50 PM PDT 24
Peak memory	207096 kb
Host	smart-3d3e0376-5d25-4713-865f-1b835fdefa83
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373553791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.373553791
Directory	/workspace/11.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/11.usbdev_disable_endpoint.1755030742
Short name	T2525
Test name
Test status
Simulation time	607466293 ps
CPU time	1.49 seconds
Started	Aug 01 06:13:26 PM PDT 24
Finished	Aug 01 06:13:27 PM PDT 24
Peak memory	206884 kb
Host	smart-df0997ce-d571-4bba-8f72-0a08957106b3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17550 30742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1755030742
Directory	/workspace/11.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/11.usbdev_disconnected.497248937
Short name	T2215
Test name
Test status
Simulation time	148058290 ps
CPU time	0.85 seconds
Started	Aug 01 06:13:27 PM PDT 24
Finished	Aug 01 06:13:28 PM PDT 24
Peak memory	206872 kb
Host	smart-e0bc847a-2dd6-409f-ae6a-00e39a59aada
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49724 8937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.497248937
Directory	/workspace/11.usbdev_disconnected/latest

Test location	/workspace/coverage/default/11.usbdev_enable.767042379
Short name	T2517
Test name
Test status
Simulation time	48383454 ps
CPU time	0.71 seconds
Started	Aug 01 06:13:28 PM PDT 24
Finished	Aug 01 06:13:29 PM PDT 24
Peak memory	206888 kb
Host	smart-d371fe4f-674e-4c84-9617-99ed3f482ead
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76704 2379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.767042379
Directory	/workspace/11.usbdev_enable/latest

Test location	/workspace/coverage/default/11.usbdev_endpoint_access.2907175983
Short name	T1474
Test name
Test status
Simulation time	861181999 ps
CPU time	2.19 seconds
Started	Aug 01 06:13:31 PM PDT 24
Finished	Aug 01 06:13:33 PM PDT 24
Peak memory	207124 kb
Host	smart-18879bba-57c5-4a25-8759-a2e13db0684b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29071 75983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2907175983
Directory	/workspace/11.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/11.usbdev_endpoint_types.2398269223
Short name	T385
Test name
Test status
Simulation time	623269335 ps
CPU time	1.66 seconds
Started	Aug 01 06:13:26 PM PDT 24
Finished	Aug 01 06:13:28 PM PDT 24
Peak memory	206920 kb
Host	smart-1226707c-7fb1-4569-bd64-b58682f0db39
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2398269223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.2398269223
Directory	/workspace/11.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/11.usbdev_fifo_rst.4049420349
Short name	T2116
Test name
Test status
Simulation time	185068830 ps
CPU time	2.02 seconds
Started	Aug 01 06:13:28 PM PDT 24
Finished	Aug 01 06:13:31 PM PDT 24
Peak memory	207112 kb
Host	smart-ac61b30b-fd45-470c-89c9-a6464ae2e9b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40494 20349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.4049420349
Directory	/workspace/11.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/11.usbdev_in_iso.3714063027
Short name	T1140
Test name
Test status
Simulation time	218636482 ps
CPU time	1.13 seconds
Started	Aug 01 06:13:25 PM PDT 24
Finished	Aug 01 06:13:27 PM PDT 24
Peak memory	215296 kb
Host	smart-8e8edc97-3fb9-40a6-b7be-359aaf29650d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3714063027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3714063027
Directory	/workspace/11.usbdev_in_iso/latest

Test location	/workspace/coverage/default/11.usbdev_in_stall.768704493
Short name	T911
Test name
Test status
Simulation time	204838555 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:26 PM PDT 24
Finished	Aug 01 06:13:27 PM PDT 24
Peak memory	206920 kb
Host	smart-b546365a-908a-4df7-9563-2497f7e8d9c8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76870 4493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.768704493
Directory	/workspace/11.usbdev_in_stall/latest

Test location	/workspace/coverage/default/11.usbdev_in_trans.501584299
Short name	T2590
Test name
Test status
Simulation time	196961819 ps
CPU time	1.08 seconds
Started	Aug 01 06:13:29 PM PDT 24
Finished	Aug 01 06:13:31 PM PDT 24
Peak memory	206952 kb
Host	smart-0f2cce95-795c-4f86-bd07-2e8c212269c9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50158 4299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.501584299
Directory	/workspace/11.usbdev_in_trans/latest

Test location	/workspace/coverage/default/11.usbdev_invalid_sync.2775221925
Short name	T1889
Test name
Test status
Simulation time	3375421043 ps
CPU time	93.85 seconds
Started	Aug 01 06:13:29 PM PDT 24
Finished	Aug 01 06:15:03 PM PDT 24
Peak memory	217632 kb
Host	smart-166fbad0-ff38-40cb-9b2a-9fb09f49dd46
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2775221925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.2775221925
Directory	/workspace/11.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/11.usbdev_iso_retraction.4027886623
Short name	T250
Test name
Test status
Simulation time	11506154013 ps
CPU time	140.97 seconds
Started	Aug 01 06:13:28 PM PDT 24
Finished	Aug 01 06:15:50 PM PDT 24
Peak memory	207052 kb
Host	smart-67d93671-da35-49ba-8639-69bc845c8780
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4027886623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.4027886623
Directory	/workspace/11.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/11.usbdev_link_in_err.456367833
Short name	T1847
Test name
Test status
Simulation time	248886071 ps
CPU time	1.03 seconds
Started	Aug 01 06:13:31 PM PDT 24
Finished	Aug 01 06:13:32 PM PDT 24
Peak memory	206968 kb
Host	smart-02831fb8-7401-471c-adef-1d378f3b9a24
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45636 7833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.456367833
Directory	/workspace/11.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/11.usbdev_link_suspend.3192224171
Short name	T2798
Test name
Test status
Simulation time	10553238533 ps
CPU time	12.42 seconds
Started	Aug 01 06:13:25 PM PDT 24
Finished	Aug 01 06:13:37 PM PDT 24
Peak memory	207152 kb
Host	smart-5c418650-929b-4a69-b221-006158880eec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31922 24171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3192224171
Directory	/workspace/11.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/11.usbdev_low_speed_traffic.3959056100
Short name	T2260
Test name
Test status
Simulation time	3823704005 ps
CPU time	37.31 seconds
Started	Aug 01 06:13:39 PM PDT 24
Finished	Aug 01 06:14:16 PM PDT 24
Peak memory	223536 kb
Host	smart-d56937bd-bb28-4886-bd0b-a059c9c38991
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39590 56100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3959056100
Directory	/workspace/11.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/11.usbdev_max_inter_pkt_delay.1861935139
Short name	T2244
Test name
Test status
Simulation time	3230923796 ps
CPU time	33.7 seconds
Started	Aug 01 06:13:26 PM PDT 24
Finished	Aug 01 06:14:00 PM PDT 24
Peak memory	215360 kb
Host	smart-b773c40d-b09e-4bdd-a660-218bce268030
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1861935139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.1861935139
Directory	/workspace/11.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/11.usbdev_max_length_in_transaction.2995149843
Short name	T2530
Test name
Test status
Simulation time	240570907 ps
CPU time	1.07 seconds
Started	Aug 01 06:13:48 PM PDT 24
Finished	Aug 01 06:13:49 PM PDT 24
Peak memory	206956 kb
Host	smart-9b18b99c-e137-4d4c-87ed-a5f3a880272d
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2995149843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.2995149843
Directory	/workspace/11.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/11.usbdev_max_length_out_transaction.517476029
Short name	T1525
Test name
Test status
Simulation time	207237426 ps
CPU time	1 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206980 kb
Host	smart-cd41b176-96ac-4db9-8cb8-3d1af2f48efc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51747 6029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.517476029
Directory	/workspace/11.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.410047100
Short name	T865
Test name
Test status
Simulation time	1715663000 ps
CPU time	12.46 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:14:00 PM PDT 24
Peak memory	223444 kb
Host	smart-178cae1b-5a9b-4b0a-8782-800df6454ff3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41004 7100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.410047100
Directory	/workspace/11.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/11.usbdev_max_usb_traffic.3953778126
Short name	T1008
Test name
Test status
Simulation time	2692429070 ps
CPU time	20.35 seconds
Started	Aug 01 06:13:42 PM PDT 24
Finished	Aug 01 06:14:03 PM PDT 24
Peak memory	223472 kb
Host	smart-a1d35f5b-976f-4f67-a293-741cfe885039
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3953778126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3953778126
Directory	/workspace/11.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/11.usbdev_min_inter_pkt_delay.2343944695
Short name	T753
Test name
Test status
Simulation time	1918519693 ps
CPU time	14.08 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	207156 kb
Host	smart-f03ea1f7-ec30-4832-9d43-75e496d95b32
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2343944695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.2343944695
Directory	/workspace/11.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/11.usbdev_min_length_in_transaction.1751238607
Short name	T905
Test name
Test status
Simulation time	153397710 ps
CPU time	0.9 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:49 PM PDT 24
Peak memory	206956 kb
Host	smart-18b5cf01-8143-4715-a525-02fda54953c1
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1751238607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.1751238607
Directory	/workspace/11.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/11.usbdev_min_length_out_transaction.2231896441
Short name	T1294
Test name
Test status
Simulation time	172309906 ps
CPU time	0.93 seconds
Started	Aug 01 06:13:37 PM PDT 24
Finished	Aug 01 06:13:38 PM PDT 24
Peak memory	206948 kb
Host	smart-39c282e2-756c-423c-9703-c5864f76cf33
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22318 96441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2231896441
Directory	/workspace/11.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/11.usbdev_out_iso.2789884901
Short name	T2521
Test name
Test status
Simulation time	181402104 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:40 PM PDT 24
Finished	Aug 01 06:13:41 PM PDT 24
Peak memory	206944 kb
Host	smart-b367db8f-a42e-4fb7-85d6-26b5fdb1c9e4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27898 84901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2789884901
Directory	/workspace/11.usbdev_out_iso/latest

Test location	/workspace/coverage/default/11.usbdev_out_stall.2723335892
Short name	T1581
Test name
Test status
Simulation time	188943539 ps
CPU time	0.9 seconds
Started	Aug 01 06:13:33 PM PDT 24
Finished	Aug 01 06:13:34 PM PDT 24
Peak memory	206944 kb
Host	smart-ae1b253c-bcbb-484a-933e-14effa430734
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233 35892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2723335892
Directory	/workspace/11.usbdev_out_stall/latest

Test location	/workspace/coverage/default/11.usbdev_out_trans_nak.874350083
Short name	T790
Test name
Test status
Simulation time	174977829 ps
CPU time	0.92 seconds
Started	Aug 01 06:13:33 PM PDT 24
Finished	Aug 01 06:13:34 PM PDT 24
Peak memory	206948 kb
Host	smart-2775d34b-b489-4064-8e4d-6e6c3e04cce4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87435 0083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.874350083
Directory	/workspace/11.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/11.usbdev_pending_in_trans.1558317986
Short name	T1110
Test name
Test status
Simulation time	169399943 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:36 PM PDT 24
Finished	Aug 01 06:13:37 PM PDT 24
Peak memory	206896 kb
Host	smart-d178be11-618b-4570-8d9f-a548c1a5e083
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15583 17986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1558317986
Directory	/workspace/11.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/11.usbdev_phy_config_pinflip.2775271475
Short name	T1034
Test name
Test status
Simulation time	248274608 ps
CPU time	1.05 seconds
Started	Aug 01 06:13:34 PM PDT 24
Finished	Aug 01 06:13:35 PM PDT 24
Peak memory	206924 kb
Host	smart-146f6e0d-36b7-429d-aa07-2a05a524a87c
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2775271475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2775271475
Directory	/workspace/11.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.486737294
Short name	T950
Test name
Test status
Simulation time	152733659 ps
CPU time	0.85 seconds
Started	Aug 01 06:13:36 PM PDT 24
Finished	Aug 01 06:13:37 PM PDT 24
Peak memory	206960 kb
Host	smart-1d53cc61-1e6c-4d2d-8ece-9d53090f7080
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48673 7294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.486737294
Directory	/workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/11.usbdev_phy_pins_sense.1055308167
Short name	T2389
Test name
Test status
Simulation time	39740162 ps
CPU time	0.69 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206916 kb
Host	smart-9f323c49-9625-4337-b097-003eed667ac1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10553 08167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1055308167
Directory	/workspace/11.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/11.usbdev_pkt_buffer.526041327
Short name	T2491
Test name
Test status
Simulation time	18781658625 ps
CPU time	49.68 seconds
Started	Aug 01 06:13:35 PM PDT 24
Finished	Aug 01 06:14:25 PM PDT 24
Peak memory	215432 kb
Host	smart-80ca4f76-fd3c-4045-9014-d3f358e30bea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52604 1327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.526041327
Directory	/workspace/11.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/11.usbdev_pkt_received.2212289945
Short name	T973
Test name
Test status
Simulation time	160050136 ps
CPU time	0.94 seconds
Started	Aug 01 06:13:35 PM PDT 24
Finished	Aug 01 06:13:36 PM PDT 24
Peak memory	206944 kb
Host	smart-aba10441-3ccc-470e-b980-1c9900096921
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22122 89945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2212289945
Directory	/workspace/11.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/11.usbdev_pkt_sent.2414578915
Short name	T2700
Test name
Test status
Simulation time	261879965 ps
CPU time	1 seconds
Started	Aug 01 06:13:39 PM PDT 24
Finished	Aug 01 06:13:40 PM PDT 24
Peak memory	206900 kb
Host	smart-de91a379-b168-40ed-82d8-7cd2fc08067f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24145 78915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2414578915
Directory	/workspace/11.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/11.usbdev_random_length_in_transaction.1059778192
Short name	T1807
Test name
Test status
Simulation time	216661856 ps
CPU time	0.94 seconds
Started	Aug 01 06:13:40 PM PDT 24
Finished	Aug 01 06:13:41 PM PDT 24
Peak memory	206932 kb
Host	smart-5f232676-4bf0-4089-8867-bfe00cead4f5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10597 78192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.1059778192
Directory	/workspace/11.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/11.usbdev_random_length_out_transaction.2246583495
Short name	T2481
Test name
Test status
Simulation time	170944226 ps
CPU time	0.86 seconds
Started	Aug 01 06:13:40 PM PDT 24
Finished	Aug 01 06:13:41 PM PDT 24
Peak memory	206928 kb
Host	smart-034961e0-2fa2-4fcc-b2c8-699a9a5892fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22465 83495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2246583495
Directory	/workspace/11.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/11.usbdev_rx_crc_err.1078793405
Short name	T2400
Test name
Test status
Simulation time	141420926 ps
CPU time	0.84 seconds
Started	Aug 01 06:13:40 PM PDT 24
Finished	Aug 01 06:13:41 PM PDT 24
Peak memory	206896 kb
Host	smart-f9a816bc-6b1c-42f3-9edb-39fc46af17b1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10787 93405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.1078793405
Directory	/workspace/11.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/11.usbdev_rx_full.560923624
Short name	T277
Test name
Test status
Simulation time	257605023 ps
CPU time	1.08 seconds
Started	Aug 01 06:13:36 PM PDT 24
Finished	Aug 01 06:13:37 PM PDT 24
Peak memory	206924 kb
Host	smart-88845530-c677-48fd-ba4e-716a7edd9e2b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56092 3624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.560923624
Directory	/workspace/11.usbdev_rx_full/latest

Test location	/workspace/coverage/default/11.usbdev_setup_stage.2316879058
Short name	T2596
Test name
Test status
Simulation time	152414057 ps
CPU time	0.82 seconds
Started	Aug 01 06:13:37 PM PDT 24
Finished	Aug 01 06:13:38 PM PDT 24
Peak memory	206912 kb
Host	smart-ee57b6d5-dd52-49c2-babb-8b87056013e6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23168 79058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.2316879058
Directory	/workspace/11.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/11.usbdev_setup_trans_ignored.2768371156
Short name	T1602
Test name
Test status
Simulation time	230980369 ps
CPU time	0.94 seconds
Started	Aug 01 06:13:33 PM PDT 24
Finished	Aug 01 06:13:34 PM PDT 24
Peak memory	206944 kb
Host	smart-8cab151c-5582-4310-9746-8c446e9819f4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27683 71156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2768371156
Directory	/workspace/11.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/11.usbdev_smoke.4067792329
Short name	T585
Test name
Test status
Simulation time	230738281 ps
CPU time	1 seconds
Started	Aug 01 06:13:37 PM PDT 24
Finished	Aug 01 06:13:39 PM PDT 24
Peak memory	206864 kb
Host	smart-047b11d9-567e-4ea0-98d0-47e8c0515368
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40677 92329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.4067792329
Directory	/workspace/11.usbdev_smoke/latest

Test location	/workspace/coverage/default/11.usbdev_spurious_pids_ignored.3040979265
Short name	T1851
Test name
Test status
Simulation time	2242764459 ps
CPU time	16.19 seconds
Started	Aug 01 06:13:34 PM PDT 24
Finished	Aug 01 06:13:51 PM PDT 24
Peak memory	223488 kb
Host	smart-b3640926-40e7-4a4a-9f4d-1bc4d0b2d2c9
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3040979265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3040979265
Directory	/workspace/11.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/11.usbdev_stall_priority_over_nak.3767704585
Short name	T971
Test name
Test status
Simulation time	203728444 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:40 PM PDT 24
Finished	Aug 01 06:13:41 PM PDT 24
Peak memory	206948 kb
Host	smart-196dc9f2-2035-4214-b916-c76a648224ab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37677 04585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.3767704585
Directory	/workspace/11.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/11.usbdev_stall_trans.3602170841
Short name	T2398
Test name
Test status
Simulation time	191490140 ps
CPU time	0.94 seconds
Started	Aug 01 06:13:34 PM PDT 24
Finished	Aug 01 06:13:35 PM PDT 24
Peak memory	206940 kb
Host	smart-bfd29029-c347-4d3d-9f83-9e99733ecd80
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36021 70841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3602170841
Directory	/workspace/11.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/11.usbdev_stream_len_max.268714193
Short name	T2860
Test name
Test status
Simulation time	705155490 ps
CPU time	1.83 seconds
Started	Aug 01 06:13:38 PM PDT 24
Finished	Aug 01 06:13:40 PM PDT 24
Peak memory	206920 kb
Host	smart-58dd368c-581c-4a08-a041-0e79b05e3342
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26871 4193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.268714193
Directory	/workspace/11.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/11.usbdev_streaming_out.2654107298
Short name	T969
Test name
Test status
Simulation time	3297170802 ps
CPU time	98.06 seconds
Started	Aug 01 06:13:33 PM PDT 24
Finished	Aug 01 06:15:12 PM PDT 24
Peak memory	216760 kb
Host	smart-c167fb06-49ab-4ced-add4-498360a7d872
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26541 07298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2654107298
Directory	/workspace/11.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.3415001627
Short name	T1404
Test name
Test status
Simulation time	7005895738 ps
CPU time	45.21 seconds
Started	Aug 01 06:13:29 PM PDT 24
Finished	Aug 01 06:14:15 PM PDT 24
Peak memory	207176 kb
Host	smart-b7a1569b-de43-4fd4-9268-c5030acc2c71
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415001627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_hos t_handshake.3415001627
Directory	/workspace/11.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/111.usbdev_endpoint_types.2261274370
Short name	T293
Test name
Test status
Simulation time	275150914 ps
CPU time	1.01 seconds
Started	Aug 01 06:20:27 PM PDT 24
Finished	Aug 01 06:20:28 PM PDT 24
Peak memory	206920 kb
Host	smart-2ee3f179-4981-46c6-b2e3-82ea6c0763da
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2261274370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.2261274370
Directory	/workspace/111.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/112.usbdev_endpoint_types.4277679298
Short name	T410
Test name
Test status
Simulation time	172520202 ps
CPU time	0.99 seconds
Started	Aug 01 06:20:06 PM PDT 24
Finished	Aug 01 06:20:07 PM PDT 24
Peak memory	206872 kb
Host	smart-b0136e41-87df-4f42-873e-c6b1346e5edc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4277679298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.4277679298
Directory	/workspace/112.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/113.usbdev_endpoint_types.394593215
Short name	T340
Test name
Test status
Simulation time	315571462 ps
CPU time	1.07 seconds
Started	Aug 01 06:20:06 PM PDT 24
Finished	Aug 01 06:20:07 PM PDT 24
Peak memory	206908 kb
Host	smart-2a472ea2-62e5-496b-a07f-3a6a75b6b179
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=394593215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.394593215
Directory	/workspace/113.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/114.usbdev_endpoint_types.3501342839
Short name	T358
Test name
Test status
Simulation time	695044149 ps
CPU time	1.74 seconds
Started	Aug 01 06:19:57 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206928 kb
Host	smart-c5a5d4b2-0bed-457d-a001-0c8b61ca9a6b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3501342839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.3501342839
Directory	/workspace/114.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/115.usbdev_endpoint_types.2874098949
Short name	T354
Test name
Test status
Simulation time	573895703 ps
CPU time	1.4 seconds
Started	Aug 01 06:20:15 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	206916 kb
Host	smart-27b29619-7793-4163-9877-777f3cae85f5
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2874098949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.2874098949
Directory	/workspace/115.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/116.usbdev_endpoint_types.1430350612
Short name	T321
Test name
Test status
Simulation time	672818598 ps
CPU time	1.54 seconds
Started	Aug 01 06:20:11 PM PDT 24
Finished	Aug 01 06:20:13 PM PDT 24
Peak memory	206924 kb
Host	smart-88e0b076-7cd3-4ae3-ae2f-cd5037a1db81
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1430350612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.1430350612
Directory	/workspace/116.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/117.usbdev_endpoint_types.1558669767
Short name	T420
Test name
Test status
Simulation time	577158089 ps
CPU time	1.51 seconds
Started	Aug 01 06:20:15 PM PDT 24
Finished	Aug 01 06:20:16 PM PDT 24
Peak memory	206916 kb
Host	smart-da9ce27d-25e6-46b1-a150-fa5ff0e805af
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1558669767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.1558669767
Directory	/workspace/117.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/118.usbdev_endpoint_types.2993387575
Short name	T1403
Test name
Test status
Simulation time	329762979 ps
CPU time	1.11 seconds
Started	Aug 01 06:20:16 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	206900 kb
Host	smart-239b8129-f2c5-4025-acf7-720a6acf9601
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2993387575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.2993387575
Directory	/workspace/118.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/119.usbdev_endpoint_types.3964501781
Short name	T429
Test name
Test status
Simulation time	285730703 ps
CPU time	1.04 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	205972 kb
Host	smart-9c2de12a-0ec9-4fe0-9254-dedb5f53bad8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3964501781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.3964501781
Directory	/workspace/119.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/12.usbdev_alert_test.4091016958
Short name	T2802
Test name
Test status
Simulation time	39817613 ps
CPU time	0.73 seconds
Started	Aug 01 06:13:46 PM PDT 24
Finished	Aug 01 06:13:47 PM PDT 24
Peak memory	206992 kb
Host	smart-156af7ac-bb86-41a4-bfa8-018fdfa498e7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=4091016958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.4091016958
Directory	/workspace/12.usbdev_alert_test/latest

Test location	/workspace/coverage/default/12.usbdev_av_buffer.1851143400
Short name	T1331
Test name
Test status
Simulation time	203954768 ps
CPU time	0.94 seconds
Started	Aug 01 06:13:40 PM PDT 24
Finished	Aug 01 06:13:41 PM PDT 24
Peak memory	206944 kb
Host	smart-13b8dd29-cbec-437a-a35c-fab801578ddd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18511 43400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.1851143400
Directory	/workspace/12.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/12.usbdev_bitstuff_err.3025295835
Short name	T2298
Test name
Test status
Simulation time	147181888 ps
CPU time	0.88 seconds
Started	Aug 01 06:13:34 PM PDT 24
Finished	Aug 01 06:13:35 PM PDT 24
Peak memory	206876 kb
Host	smart-20129910-6adc-418e-9f7a-82c47f396923
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30252 95835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.3025295835
Directory	/workspace/12.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/12.usbdev_data_toggle_clear.3759813284
Short name	T1888
Test name
Test status
Simulation time	614364448 ps
CPU time	1.92 seconds
Started	Aug 01 06:13:42 PM PDT 24
Finished	Aug 01 06:13:44 PM PDT 24
Peak memory	207088 kb
Host	smart-587362ec-92c9-495a-82ff-7a74c547e480
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37598 13284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3759813284
Directory	/workspace/12.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/12.usbdev_data_toggle_restore.2346561583
Short name	T1833
Test name
Test status
Simulation time	643687005 ps
CPU time	1.85 seconds
Started	Aug 01 06:13:33 PM PDT 24
Finished	Aug 01 06:13:35 PM PDT 24
Peak memory	206944 kb
Host	smart-19db7ada-9a41-4a5f-8a83-3679065b9c40
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2346561583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.2346561583
Directory	/workspace/12.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/12.usbdev_device_address.1396478351
Short name	T1687
Test name
Test status
Simulation time	59215468091 ps
CPU time	91.31 seconds
Started	Aug 01 06:13:39 PM PDT 24
Finished	Aug 01 06:15:10 PM PDT 24
Peak memory	207012 kb
Host	smart-01a8a9a9-d5c7-4862-ab22-068778fa56ba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13964 78351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1396478351
Directory	/workspace/12.usbdev_device_address/latest

Test location	/workspace/coverage/default/12.usbdev_device_timeout.1000351205
Short name	T657
Test name
Test status
Simulation time	1068299562 ps
CPU time	8.87 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:56 PM PDT 24
Peak memory	207156 kb
Host	smart-48eafff8-ee44-4e8d-ab7c-12ca45b027c7
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000351205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.1000351205
Directory	/workspace/12.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/12.usbdev_disable_endpoint.2558958146
Short name	T605
Test name
Test status
Simulation time	1088891131 ps
CPU time	2.31 seconds
Started	Aug 01 06:13:40 PM PDT 24
Finished	Aug 01 06:13:42 PM PDT 24
Peak memory	206908 kb
Host	smart-5c8b7b50-7c0c-4451-a832-83556dc5b5ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25589 58146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2558958146
Directory	/workspace/12.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/12.usbdev_disconnected.2467682727
Short name	T1017
Test name
Test status
Simulation time	142401471 ps
CPU time	0.88 seconds
Started	Aug 01 06:13:34 PM PDT 24
Finished	Aug 01 06:13:35 PM PDT 24
Peak memory	206908 kb
Host	smart-66dc4e91-726b-4223-80aa-e5052adffa62
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676 82727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2467682727
Directory	/workspace/12.usbdev_disconnected/latest

Test location	/workspace/coverage/default/12.usbdev_enable.1074384823
Short name	T2022
Test name
Test status
Simulation time	75422277 ps
CPU time	0.75 seconds
Started	Aug 01 06:13:35 PM PDT 24
Finished	Aug 01 06:13:36 PM PDT 24
Peak memory	206920 kb
Host	smart-e1b45195-87b5-4846-ace9-91855a37700d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10743 84823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.1074384823
Directory	/workspace/12.usbdev_enable/latest

Test location	/workspace/coverage/default/12.usbdev_endpoint_access.736534895
Short name	T2289
Test name
Test status
Simulation time	875956740 ps
CPU time	2.66 seconds
Started	Aug 01 06:13:37 PM PDT 24
Finished	Aug 01 06:13:40 PM PDT 24
Peak memory	207180 kb
Host	smart-ae6a2752-9b1a-4e25-92b3-2ec4060df437
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73653 4895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.736534895
Directory	/workspace/12.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/12.usbdev_endpoint_types.1843262910
Short name	T424
Test name
Test status
Simulation time	335777347 ps
CPU time	1.15 seconds
Started	Aug 01 06:13:38 PM PDT 24
Finished	Aug 01 06:13:40 PM PDT 24
Peak memory	206916 kb
Host	smart-43e1f7c1-95d1-4e7c-9c78-f162f2137790
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1843262910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.1843262910
Directory	/workspace/12.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/12.usbdev_fifo_rst.145557457
Short name	T1861
Test name
Test status
Simulation time	229693184 ps
CPU time	1.55 seconds
Started	Aug 01 06:13:35 PM PDT 24
Finished	Aug 01 06:13:37 PM PDT 24
Peak memory	207092 kb
Host	smart-148bc364-6ec0-48c0-9e99-58239fcaf4b2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14555 7457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.145557457
Directory	/workspace/12.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/12.usbdev_in_iso.3898201251
Short name	T1775
Test name
Test status
Simulation time	156503357 ps
CPU time	0.94 seconds
Started	Aug 01 06:13:36 PM PDT 24
Finished	Aug 01 06:13:38 PM PDT 24
Peak memory	206972 kb
Host	smart-49995786-b004-4ae6-8eb2-9a937491a310
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3898201251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3898201251
Directory	/workspace/12.usbdev_in_iso/latest

Test location	/workspace/coverage/default/12.usbdev_in_stall.640801271
Short name	T2868
Test name
Test status
Simulation time	191509423 ps
CPU time	0.86 seconds
Started	Aug 01 06:13:42 PM PDT 24
Finished	Aug 01 06:13:43 PM PDT 24
Peak memory	206896 kb
Host	smart-9ee1533a-503e-4508-be10-75f57b1dd8b6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64080 1271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.640801271
Directory	/workspace/12.usbdev_in_stall/latest

Test location	/workspace/coverage/default/12.usbdev_in_trans.1967684118
Short name	T1060
Test name
Test status
Simulation time	220857176 ps
CPU time	0.93 seconds
Started	Aug 01 06:13:38 PM PDT 24
Finished	Aug 01 06:13:39 PM PDT 24
Peak memory	206936 kb
Host	smart-428161e1-69d0-41a3-b021-2a1322d8a30d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19676 84118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1967684118
Directory	/workspace/12.usbdev_in_trans/latest

Test location	/workspace/coverage/default/12.usbdev_invalid_sync.1503037152
Short name	T1547
Test name
Test status
Simulation time	4610689752 ps
CPU time	131.38 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:15:59 PM PDT 24
Peak memory	223468 kb
Host	smart-88c41722-fbda-430f-9af1-ea4273868405
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1503037152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1503037152
Directory	/workspace/12.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/12.usbdev_iso_retraction.4011814290
Short name	T1970
Test name
Test status
Simulation time	11859605773 ps
CPU time	82.61 seconds
Started	Aug 01 06:13:38 PM PDT 24
Finished	Aug 01 06:15:01 PM PDT 24
Peak memory	207132 kb
Host	smart-6c84bd27-9eb8-45cc-af81-a385f4943002
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4011814290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.4011814290
Directory	/workspace/12.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/12.usbdev_link_in_err.3643116799
Short name	T566
Test name
Test status
Simulation time	233712740 ps
CPU time	1.02 seconds
Started	Aug 01 06:13:34 PM PDT 24
Finished	Aug 01 06:13:35 PM PDT 24
Peak memory	206940 kb
Host	smart-c484fa50-f8a9-47d8-9928-be4298594d24
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36431 16799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3643116799
Directory	/workspace/12.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/12.usbdev_link_suspend.2681854641
Short name	T1774
Test name
Test status
Simulation time	9998915241 ps
CPU time	12.15 seconds
Started	Aug 01 06:13:33 PM PDT 24
Finished	Aug 01 06:13:46 PM PDT 24
Peak memory	207176 kb
Host	smart-d006c576-04b9-4437-86bb-b89f00a01fe8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26818 54641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2681854641
Directory	/workspace/12.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/12.usbdev_low_speed_traffic.1332478506
Short name	T962
Test name
Test status
Simulation time	4321951987 ps
CPU time	122.64 seconds
Started	Aug 01 06:13:33 PM PDT 24
Finished	Aug 01 06:15:36 PM PDT 24
Peak memory	223564 kb
Host	smart-245c1199-fc96-4df5-9773-d14aca9cb303
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13324 78506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.1332478506
Directory	/workspace/12.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/12.usbdev_max_inter_pkt_delay.1901231593
Short name	T1573
Test name
Test status
Simulation time	1715807516 ps
CPU time	16.54 seconds
Started	Aug 01 06:13:37 PM PDT 24
Finished	Aug 01 06:13:54 PM PDT 24
Peak memory	216624 kb
Host	smart-3f4414c4-5fb9-4955-b890-72712eb4bceb
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1901231593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.1901231593
Directory	/workspace/12.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/12.usbdev_max_length_in_transaction.2291621665
Short name	T483
Test name
Test status
Simulation time	274522640 ps
CPU time	1.03 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206936 kb
Host	smart-d78c9479-933f-4517-bcc8-d8d0600c0906
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2291621665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.2291621665
Directory	/workspace/12.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/12.usbdev_max_length_out_transaction.2344401655
Short name	T1797
Test name
Test status
Simulation time	198584638 ps
CPU time	1.05 seconds
Started	Aug 01 06:13:40 PM PDT 24
Finished	Aug 01 06:13:41 PM PDT 24
Peak memory	206948 kb
Host	smart-55613154-b0af-455c-a12e-de7fc14cc838
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444 01655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2344401655
Directory	/workspace/12.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.1479253463
Short name	T1264
Test name
Test status
Simulation time	3552775275 ps
CPU time	96.65 seconds
Started	Aug 01 06:13:35 PM PDT 24
Finished	Aug 01 06:15:12 PM PDT 24
Peak memory	223448 kb
Host	smart-c8985fd6-63a2-49a9-bff7-924f77f8536c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14792 53463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.1479253463
Directory	/workspace/12.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/12.usbdev_max_usb_traffic.183870105
Short name	T2141
Test name
Test status
Simulation time	2244632385 ps
CPU time	18.56 seconds
Started	Aug 01 06:13:35 PM PDT 24
Finished	Aug 01 06:13:54 PM PDT 24
Peak memory	223508 kb
Host	smart-34402fb8-4461-428c-9584-30423b76e85a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=183870105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.183870105
Directory	/workspace/12.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1006915736
Short name	T1114
Test name
Test status
Simulation time	2766517439 ps
CPU time	81.92 seconds
Started	Aug 01 06:13:32 PM PDT 24
Finished	Aug 01 06:14:54 PM PDT 24
Peak memory	215336 kb
Host	smart-203100f9-92cd-4e9d-a8c6-7a1346329bb0
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1006915736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1006915736
Directory	/workspace/12.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/12.usbdev_min_length_in_transaction.2835010710
Short name	T2434
Test name
Test status
Simulation time	161268008 ps
CPU time	0.89 seconds
Started	Aug 01 06:13:33 PM PDT 24
Finished	Aug 01 06:13:34 PM PDT 24
Peak memory	206956 kb
Host	smart-c5fca6d2-0d6d-45c9-b73c-5cf1a97cc53f
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2835010710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2835010710
Directory	/workspace/12.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/12.usbdev_min_length_out_transaction.508991532
Short name	T2833
Test name
Test status
Simulation time	179870960 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:46 PM PDT 24
Finished	Aug 01 06:13:47 PM PDT 24
Peak memory	206908 kb
Host	smart-246c809e-3890-45ed-963c-22ee8535e400
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50899 1532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.508991532
Directory	/workspace/12.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/12.usbdev_out_iso.1582627779
Short name	T1829
Test name
Test status
Simulation time	184497959 ps
CPU time	0.92 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206944 kb
Host	smart-84b75f25-fcbb-4e1d-9c38-aedc669fc37c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15826 27779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.1582627779
Directory	/workspace/12.usbdev_out_iso/latest

Test location	/workspace/coverage/default/12.usbdev_out_stall.1214413271
Short name	T2139
Test name
Test status
Simulation time	161751347 ps
CPU time	0.9 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206912 kb
Host	smart-91d096f5-1fef-403d-add4-cb8e0da64522
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12144 13271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1214413271
Directory	/workspace/12.usbdev_out_stall/latest

Test location	/workspace/coverage/default/12.usbdev_out_trans_nak.2771932404
Short name	T985
Test name
Test status
Simulation time	219404703 ps
CPU time	0.9 seconds
Started	Aug 01 06:13:45 PM PDT 24
Finished	Aug 01 06:13:46 PM PDT 24
Peak memory	206932 kb
Host	smart-f17b3c34-21a2-4665-b797-7c9983ccac0d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27719 32404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.2771932404
Directory	/workspace/12.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/12.usbdev_pending_in_trans.725178164
Short name	T225
Test name
Test status
Simulation time	154962339 ps
CPU time	0.84 seconds
Started	Aug 01 06:13:44 PM PDT 24
Finished	Aug 01 06:13:45 PM PDT 24
Peak memory	206972 kb
Host	smart-89d827a6-85d0-4ec8-a2f0-a5afbba95906
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72517 8164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.725178164
Directory	/workspace/12.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/12.usbdev_phy_config_pinflip.2478871545
Short name	T2042
Test name
Test status
Simulation time	190824978 ps
CPU time	0.97 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206912 kb
Host	smart-e8b2f510-aac4-4a85-8ecd-d317363ddaa5
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2478871545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2478871545
Directory	/workspace/12.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2457530865
Short name	T1680
Test name
Test status
Simulation time	145311859 ps
CPU time	0.89 seconds
Started	Aug 01 06:13:48 PM PDT 24
Finished	Aug 01 06:13:49 PM PDT 24
Peak memory	206868 kb
Host	smart-ea82e9be-fd52-4b32-a9c8-915d30542a49
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24575 30865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2457530865
Directory	/workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/12.usbdev_phy_pins_sense.1340303476
Short name	T1763
Test name
Test status
Simulation time	38576497 ps
CPU time	0.7 seconds
Started	Aug 01 06:13:45 PM PDT 24
Finished	Aug 01 06:13:46 PM PDT 24
Peak memory	206908 kb
Host	smart-60aa481b-c4bb-4b48-bb7e-ad8849927ba8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13403 03476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1340303476
Directory	/workspace/12.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/12.usbdev_pkt_buffer.1944663619
Short name	T2354
Test name
Test status
Simulation time	19867480854 ps
CPU time	49.91 seconds
Started	Aug 01 06:13:46 PM PDT 24
Finished	Aug 01 06:14:36 PM PDT 24
Peak memory	215372 kb
Host	smart-7918e01a-9497-442b-bef0-2e1fbc1068aa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19446 63619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1944663619
Directory	/workspace/12.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/12.usbdev_pkt_received.2269637974
Short name	T1772
Test name
Test status
Simulation time	188421133 ps
CPU time	0.92 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206952 kb
Host	smart-06800f77-9a99-4636-ac6d-a7f5f31d028b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22696 37974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2269637974
Directory	/workspace/12.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/12.usbdev_pkt_sent.2547928948
Short name	T1668
Test name
Test status
Simulation time	203685092 ps
CPU time	0.94 seconds
Started	Aug 01 06:13:46 PM PDT 24
Finished	Aug 01 06:13:47 PM PDT 24
Peak memory	206920 kb
Host	smart-57a296a7-699d-462e-89d2-5da526789e6f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25479 28948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2547928948
Directory	/workspace/12.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/12.usbdev_random_length_in_transaction.3986934567
Short name	T1652
Test name
Test status
Simulation time	214489739 ps
CPU time	0.96 seconds
Started	Aug 01 06:13:49 PM PDT 24
Finished	Aug 01 06:13:50 PM PDT 24
Peak memory	206944 kb
Host	smart-858b5b19-e995-43a6-b85a-ae8599b5e4db
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39869 34567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3986934567
Directory	/workspace/12.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/12.usbdev_random_length_out_transaction.157582914
Short name	T2569
Test name
Test status
Simulation time	175803114 ps
CPU time	0.97 seconds
Started	Aug 01 06:13:48 PM PDT 24
Finished	Aug 01 06:13:49 PM PDT 24
Peak memory	206964 kb
Host	smart-a8c5f204-9315-4489-a42d-6b12082317d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15758 2914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.157582914
Directory	/workspace/12.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/12.usbdev_rx_crc_err.299878401
Short name	T1860
Test name
Test status
Simulation time	201066981 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:48 PM PDT 24
Finished	Aug 01 06:13:49 PM PDT 24
Peak memory	206880 kb
Host	smart-9f2adf3d-75a9-445c-b206-5934917188d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29987 8401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.299878401
Directory	/workspace/12.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/12.usbdev_rx_full.1549019267
Short name	T553
Test name
Test status
Simulation time	349402982 ps
CPU time	1.3 seconds
Started	Aug 01 06:13:46 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206800 kb
Host	smart-3b31fd79-6854-4342-b626-33507a59da95
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15490 19267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.1549019267
Directory	/workspace/12.usbdev_rx_full/latest

Test location	/workspace/coverage/default/12.usbdev_setup_stage.2721780883
Short name	T2272
Test name
Test status
Simulation time	157316935 ps
CPU time	0.88 seconds
Started	Aug 01 06:13:45 PM PDT 24
Finished	Aug 01 06:13:46 PM PDT 24
Peak memory	206924 kb
Host	smart-2a68f44c-3a93-4d74-a218-3efee5db49c9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27217 80883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2721780883
Directory	/workspace/12.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/12.usbdev_setup_trans_ignored.1952903589
Short name	T2665
Test name
Test status
Simulation time	153831190 ps
CPU time	0.85 seconds
Started	Aug 01 06:13:49 PM PDT 24
Finished	Aug 01 06:13:50 PM PDT 24
Peak memory	206924 kb
Host	smart-c8b31f6a-13fe-4f66-a493-8814233732e6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19529 03589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1952903589
Directory	/workspace/12.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/12.usbdev_smoke.3887937858
Short name	T1235
Test name
Test status
Simulation time	256930536 ps
CPU time	1.08 seconds
Started	Aug 01 06:13:50 PM PDT 24
Finished	Aug 01 06:13:51 PM PDT 24
Peak memory	206964 kb
Host	smart-4a22001a-6c86-483b-8d73-49d134d90194
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38879 37858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3887937858
Directory	/workspace/12.usbdev_smoke/latest

Test location	/workspace/coverage/default/12.usbdev_spurious_pids_ignored.3608132859
Short name	T2856
Test name
Test status
Simulation time	3090085426 ps
CPU time	82.04 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:15:09 PM PDT 24
Peak memory	223552 kb
Host	smart-03ecb14e-4131-43f9-93ae-e6ffbdc2c792
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3608132859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3608132859
Directory	/workspace/12.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/12.usbdev_stall_priority_over_nak.910754452
Short name	T1036
Test name
Test status
Simulation time	189772435 ps
CPU time	0.86 seconds
Started	Aug 01 06:13:50 PM PDT 24
Finished	Aug 01 06:13:51 PM PDT 24
Peak memory	206968 kb
Host	smart-334a4b84-f302-4a27-87ad-c5a68b6d6e96
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91075 4452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.910754452
Directory	/workspace/12.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/12.usbdev_stall_trans.1499833276
Short name	T2518
Test name
Test status
Simulation time	237936832 ps
CPU time	0.97 seconds
Started	Aug 01 06:13:46 PM PDT 24
Finished	Aug 01 06:13:47 PM PDT 24
Peak memory	206916 kb
Host	smart-16828e41-2330-4787-994e-872ebaa7daff
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14998 33276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1499833276
Directory	/workspace/12.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/12.usbdev_stream_len_max.3816988330
Short name	T1719
Test name
Test status
Simulation time	1005361767 ps
CPU time	2.47 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:50 PM PDT 24
Peak memory	207076 kb
Host	smart-9dad4e35-14be-44a5-838b-e37085583c85
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38169 88330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3816988330
Directory	/workspace/12.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/12.usbdev_streaming_out.363394941
Short name	T2626
Test name
Test status
Simulation time	1883045891 ps
CPU time	19.31 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:14:06 PM PDT 24
Peak memory	216664 kb
Host	smart-21cdbeaa-881b-41bd-aa04-93b8bbb3e29c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36339 4941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.363394941
Directory	/workspace/12.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.1048913973
Short name	T904
Test name
Test status
Simulation time	3062856625 ps
CPU time	24.41 seconds
Started	Aug 01 06:13:43 PM PDT 24
Finished	Aug 01 06:14:08 PM PDT 24
Peak memory	207140 kb
Host	smart-49a6dff2-8bc4-4d48-a281-77ed1a12890d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048913973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos t_handshake.1048913973
Directory	/workspace/12.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/121.usbdev_endpoint_types.316547999
Short name	T368
Test name
Test status
Simulation time	284824458 ps
CPU time	1.04 seconds
Started	Aug 01 06:20:23 PM PDT 24
Finished	Aug 01 06:20:24 PM PDT 24
Peak memory	206836 kb
Host	smart-9fa3ed6d-a65d-4984-8472-45b1d1f2ab15
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=316547999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.316547999
Directory	/workspace/121.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/123.usbdev_endpoint_types.4218432738
Short name	T2838
Test name
Test status
Simulation time	362519869 ps
CPU time	1.15 seconds
Started	Aug 01 06:20:07 PM PDT 24
Finished	Aug 01 06:20:08 PM PDT 24
Peak memory	206908 kb
Host	smart-035c5c10-18ed-4062-93d4-f4cbfbc5270b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4218432738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.4218432738
Directory	/workspace/123.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/124.usbdev_endpoint_types.2628743216
Short name	T2088
Test name
Test status
Simulation time	260440442 ps
CPU time	0.99 seconds
Started	Aug 01 06:20:31 PM PDT 24
Finished	Aug 01 06:20:32 PM PDT 24
Peak memory	206832 kb
Host	smart-a1131595-1fde-4ff4-a41b-166c1dee8c01
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2628743216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.2628743216
Directory	/workspace/124.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/125.usbdev_endpoint_types.4123512545
Short name	T405
Test name
Test status
Simulation time	399834515 ps
CPU time	1.32 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206900 kb
Host	smart-a2ee0bcc-68ea-4e14-8265-946f40698483
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4123512545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.4123512545
Directory	/workspace/125.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/126.usbdev_endpoint_types.508075164
Short name	T349
Test name
Test status
Simulation time	482355680 ps
CPU time	1.42 seconds
Started	Aug 01 06:20:19 PM PDT 24
Finished	Aug 01 06:20:21 PM PDT 24
Peak memory	206832 kb
Host	smart-840e5e12-d029-4427-8e98-3d4e00a48628
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=508075164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.508075164
Directory	/workspace/126.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/128.usbdev_endpoint_types.285930230
Short name	T2651
Test name
Test status
Simulation time	542530203 ps
CPU time	1.45 seconds
Started	Aug 01 06:20:11 PM PDT 24
Finished	Aug 01 06:20:12 PM PDT 24
Peak memory	206832 kb
Host	smart-670d7d41-8aea-4fb2-844d-bb2759e62b72
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=285930230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.285930230
Directory	/workspace/128.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/129.usbdev_endpoint_types.3920301250
Short name	T2450
Test name
Test status
Simulation time	157824466 ps
CPU time	0.84 seconds
Started	Aug 01 06:20:06 PM PDT 24
Finished	Aug 01 06:20:07 PM PDT 24
Peak memory	206908 kb
Host	smart-c7714d2d-7552-460b-8047-998764356b07
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3920301250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.3920301250
Directory	/workspace/129.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/13.usbdev_alert_test.2139754044
Short name	T2053
Test name
Test status
Simulation time	34332100 ps
CPU time	0.68 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206992 kb
Host	smart-25552948-ab21-4f01-bc53-9618e76edc24
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2139754044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.2139754044
Directory	/workspace/13.usbdev_alert_test/latest

Test location	/workspace/coverage/default/13.usbdev_av_buffer.1754685590
Short name	T1068
Test name
Test status
Simulation time	152746111 ps
CPU time	0.85 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206904 kb
Host	smart-75930513-5ed6-48f0-a680-204adac26986
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17546 85590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1754685590
Directory	/workspace/13.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/13.usbdev_bitstuff_err.1374448541
Short name	T2218
Test name
Test status
Simulation time	215005475 ps
CPU time	0.97 seconds
Started	Aug 01 06:13:47 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	206860 kb
Host	smart-31a4564b-f8f3-4dbc-bc92-262f5d573c58
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13744 48541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1374448541
Directory	/workspace/13.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/13.usbdev_data_toggle_clear.4148804118
Short name	T1382
Test name
Test status
Simulation time	148124010 ps
CPU time	0.88 seconds
Started	Aug 01 06:13:46 PM PDT 24
Finished	Aug 01 06:13:47 PM PDT 24
Peak memory	206892 kb
Host	smart-4883b125-78e4-4089-a840-a7260ce4def5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41488 04118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.4148804118
Directory	/workspace/13.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/13.usbdev_data_toggle_restore.193283818
Short name	T2311
Test name
Test status
Simulation time	828244922 ps
CPU time	2.35 seconds
Started	Aug 01 06:13:50 PM PDT 24
Finished	Aug 01 06:13:53 PM PDT 24
Peak memory	207128 kb
Host	smart-b07af013-51c2-498b-b330-10eacc49bed0
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=193283818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.193283818
Directory	/workspace/13.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/13.usbdev_device_address.714942879
Short name	T1220
Test name
Test status
Simulation time	15870336159 ps
CPU time	26.29 seconds
Started	Aug 01 06:13:46 PM PDT 24
Finished	Aug 01 06:14:13 PM PDT 24
Peak memory	207100 kb
Host	smart-8595759a-ab33-43a2-bbc7-5beaad2e31a2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71494 2879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.714942879
Directory	/workspace/13.usbdev_device_address/latest

Test location	/workspace/coverage/default/13.usbdev_device_timeout.2093621497
Short name	T1059
Test name
Test status
Simulation time	1684116664 ps
CPU time	39.23 seconds
Started	Aug 01 06:13:59 PM PDT 24
Finished	Aug 01 06:14:39 PM PDT 24
Peak memory	207072 kb
Host	smart-f319f32f-97da-4656-85c5-a657a3d19a17
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093621497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.2093621497
Directory	/workspace/13.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/13.usbdev_disable_endpoint.713548964
Short name	T2722
Test name
Test status
Simulation time	454125874 ps
CPU time	1.42 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:01 PM PDT 24
Peak memory	206820 kb
Host	smart-76553d18-e97c-4222-ae6b-979473e7e8c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71354 8964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.713548964
Directory	/workspace/13.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/13.usbdev_disconnected.1019325754
Short name	T2437
Test name
Test status
Simulation time	135675097 ps
CPU time	0.83 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206888 kb
Host	smart-24ed7aa2-ded5-49b5-8d17-b6ebd79e6684
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10193 25754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1019325754
Directory	/workspace/13.usbdev_disconnected/latest

Test location	/workspace/coverage/default/13.usbdev_enable.2997463805
Short name	T1163
Test name
Test status
Simulation time	39244733 ps
CPU time	0.77 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	206432 kb
Host	smart-ea7bf27b-ccdb-4e53-ad98-b0233c1fe69e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29974 63805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2997463805
Directory	/workspace/13.usbdev_enable/latest

Test location	/workspace/coverage/default/13.usbdev_endpoint_access.3772447516
Short name	T1685
Test name
Test status
Simulation time	850398722 ps
CPU time	2.82 seconds
Started	Aug 01 06:14:02 PM PDT 24
Finished	Aug 01 06:14:05 PM PDT 24
Peak memory	207176 kb
Host	smart-19481cb1-c090-4c0d-b4e8-78f979a40a85
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37724 47516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.3772447516
Directory	/workspace/13.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/13.usbdev_endpoint_types.1806045885
Short name	T2279
Test name
Test status
Simulation time	162744766 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	206920 kb
Host	smart-f64cd65a-3a50-4ce2-b3a9-52ff74051b56
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1806045885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.1806045885
Directory	/workspace/13.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/13.usbdev_in_iso.1737407953
Short name	T637
Test name
Test status
Simulation time	213769186 ps
CPU time	1.17 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	207088 kb
Host	smart-6ad0f732-fa6e-4fbe-9986-973d5fc4b2d3
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1737407953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1737407953
Directory	/workspace/13.usbdev_in_iso/latest

Test location	/workspace/coverage/default/13.usbdev_in_stall.4201195964
Short name	T587
Test name
Test status
Simulation time	218118031 ps
CPU time	0.95 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:05 PM PDT 24
Peak memory	206884 kb
Host	smart-ffd8bebb-e24f-404b-bc87-854e4a2c2163
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42011 95964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.4201195964
Directory	/workspace/13.usbdev_in_stall/latest

Test location	/workspace/coverage/default/13.usbdev_in_trans.1208784213
Short name	T535
Test name
Test status
Simulation time	174135556 ps
CPU time	0.89 seconds
Started	Aug 01 06:13:58 PM PDT 24
Finished	Aug 01 06:13:59 PM PDT 24
Peak memory	206972 kb
Host	smart-d1dfc617-b2f2-419d-8d2f-7984911afdf3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12087 84213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1208784213
Directory	/workspace/13.usbdev_in_trans/latest

Test location	/workspace/coverage/default/13.usbdev_invalid_sync.1806433511
Short name	T2820
Test name
Test status
Simulation time	3765721918 ps
CPU time	29.31 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:30 PM PDT 24
Peak memory	223528 kb
Host	smart-e86327b0-a83c-43ca-8886-06aed14f3108
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1806433511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.1806433511
Directory	/workspace/13.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/13.usbdev_iso_retraction.3998411022
Short name	T1072
Test name
Test status
Simulation time	8137772909 ps
CPU time	53.48 seconds
Started	Aug 01 06:14:02 PM PDT 24
Finished	Aug 01 06:14:55 PM PDT 24
Peak memory	207156 kb
Host	smart-33b58d69-a5a6-4617-97c6-2ea345932e09
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3998411022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.3998411022
Directory	/workspace/13.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/13.usbdev_link_in_err.3011566120
Short name	T1134
Test name
Test status
Simulation time	222377075 ps
CPU time	1.02 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206944 kb
Host	smart-64dd72bc-5313-4aa4-b3fd-9c5dc496725e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30115 66120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3011566120
Directory	/workspace/13.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/13.usbdev_link_suspend.1612986176
Short name	T2177
Test name
Test status
Simulation time	11372737717 ps
CPU time	14.53 seconds
Started	Aug 01 06:13:59 PM PDT 24
Finished	Aug 01 06:14:13 PM PDT 24
Peak memory	207128 kb
Host	smart-f6cba2ea-960a-41b2-a047-ff6d71eaae56
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16129 86176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1612986176
Directory	/workspace/13.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/13.usbdev_low_speed_traffic.477320105
Short name	T791
Test name
Test status
Simulation time	2446582353 ps
CPU time	24.22 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:27 PM PDT 24
Peak memory	217952 kb
Host	smart-2391eadb-194a-478e-8ae7-f516cbba6dcc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47732 0105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.477320105
Directory	/workspace/13.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/13.usbdev_max_inter_pkt_delay.3518953240
Short name	T521
Test name
Test status
Simulation time	2176960203 ps
CPU time	16.99 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:19 PM PDT 24
Peak memory	207184 kb
Host	smart-ec85b6dc-ff9f-4a8a-84a3-c2611bf4950a
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3518953240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.3518953240
Directory	/workspace/13.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/13.usbdev_max_length_in_transaction.328727913
Short name	T1102
Test name
Test status
Simulation time	281827897 ps
CPU time	1.06 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:05 PM PDT 24
Peak memory	206944 kb
Host	smart-ac5e9d3b-6b47-45e1-ba7c-9bfae9f649c8
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=328727913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.328727913
Directory	/workspace/13.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/13.usbdev_max_length_out_transaction.1615957456
Short name	T497
Test name
Test status
Simulation time	208635471 ps
CPU time	1.06 seconds
Started	Aug 01 06:13:59 PM PDT 24
Finished	Aug 01 06:14:00 PM PDT 24
Peak memory	206976 kb
Host	smart-62bc5a73-e7ba-4dd4-92e3-cf3d6a544959
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16159 57456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1615957456
Directory	/workspace/13.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.2381138311
Short name	T2896
Test name
Test status
Simulation time	2051920369 ps
CPU time	58.28 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:15:01 PM PDT 24
Peak memory	216548 kb
Host	smart-03940e6b-7dc8-40f0-ae37-48c338b1fc40
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23811 38311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.2381138311
Directory	/workspace/13.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/13.usbdev_max_usb_traffic.4092027742
Short name	T2619
Test name
Test status
Simulation time	2634929297 ps
CPU time	23.14 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:24 PM PDT 24
Peak memory	218204 kb
Host	smart-dc5c4de6-b5e2-4948-89ef-a64ddae1f301
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4092027742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.4092027742
Directory	/workspace/13.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/13.usbdev_min_inter_pkt_delay.2591127762
Short name	T2827
Test name
Test status
Simulation time	3470591650 ps
CPU time	27.08 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:27 PM PDT 24
Peak memory	215432 kb
Host	smart-4e351125-ba48-4973-a397-8047be1fff67
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2591127762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2591127762
Directory	/workspace/13.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/13.usbdev_min_length_in_transaction.388276099
Short name	T567
Test name
Test status
Simulation time	166533346 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:01 PM PDT 24
Peak memory	206968 kb
Host	smart-90d8da85-fe45-4fb0-82e4-b44de9c87d75
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=388276099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.388276099
Directory	/workspace/13.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/13.usbdev_min_length_out_transaction.500390877
Short name	T1129
Test name
Test status
Simulation time	146814392 ps
CPU time	0.9 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	206936 kb
Host	smart-b9c61197-3794-4d9c-840e-30741cbc406c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50039 0877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.500390877
Directory	/workspace/13.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/13.usbdev_nak_trans.647038710
Short name	T190
Test name
Test status
Simulation time	198249923 ps
CPU time	0.95 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206968 kb
Host	smart-e6e10023-3c46-4255-a7df-8a9650c28bb8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64703 8710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.647038710
Directory	/workspace/13.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/13.usbdev_out_iso.3190097936
Short name	T764
Test name
Test status
Simulation time	210869809 ps
CPU time	0.95 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	206920 kb
Host	smart-440773e1-f5e7-4209-9f8f-f13b9de07df6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31900 97936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3190097936
Directory	/workspace/13.usbdev_out_iso/latest

Test location	/workspace/coverage/default/13.usbdev_out_stall.824362236
Short name	T1066
Test name
Test status
Simulation time	154259939 ps
CPU time	1.06 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	206944 kb
Host	smart-79692018-1c86-431f-a9c1-5e9cf4962cdc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82436 2236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.824362236
Directory	/workspace/13.usbdev_out_stall/latest

Test location	/workspace/coverage/default/13.usbdev_out_trans_nak.2037825304
Short name	T1637
Test name
Test status
Simulation time	193709946 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:01 PM PDT 24
Peak memory	206944 kb
Host	smart-7dd053ef-8b1a-43c2-b8c0-efe2cbe212c5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20378 25304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2037825304
Directory	/workspace/13.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/13.usbdev_pending_in_trans.1354837825
Short name	T2371
Test name
Test status
Simulation time	152821964 ps
CPU time	0.91 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:03 PM PDT 24
Peak memory	206880 kb
Host	smart-4f69ef3c-e535-42ca-b62e-4cd5748ec731
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13548 37825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.1354837825
Directory	/workspace/13.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/13.usbdev_phy_config_pinflip.3182176856
Short name	T1709
Test name
Test status
Simulation time	217184153 ps
CPU time	1.08 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	206952 kb
Host	smart-5d13d473-c47b-4e06-8a55-208131004d6c
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3182176856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3182176856
Directory	/workspace/13.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.3645261960
Short name	T2138
Test name
Test status
Simulation time	151194601 ps
CPU time	0.81 seconds
Started	Aug 01 06:13:57 PM PDT 24
Finished	Aug 01 06:13:58 PM PDT 24
Peak memory	206928 kb
Host	smart-cc2783fd-49ec-431f-bf1c-f954e8bc692b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36452 61960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.3645261960
Directory	/workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/13.usbdev_phy_pins_sense.2087796635
Short name	T22
Test name
Test status
Simulation time	124744111 ps
CPU time	0.83 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206920 kb
Host	smart-3ebde2c8-d9f3-4061-b6a8-b17f54fd19ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20877 96635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2087796635
Directory	/workspace/13.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/13.usbdev_pkt_buffer.1983113408
Short name	T87
Test name
Test status
Simulation time	14995903525 ps
CPU time	40 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:42 PM PDT 24
Peak memory	219848 kb
Host	smart-46efa0a9-967b-4f6b-a480-182777ba0a89
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19831 13408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1983113408
Directory	/workspace/13.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/13.usbdev_pkt_received.4155526076
Short name	T305
Test name
Test status
Simulation time	204106118 ps
CPU time	0.97 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206924 kb
Host	smart-76c0280d-956d-4be8-930e-e7b7286e33c9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41555 26076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.4155526076
Directory	/workspace/13.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/13.usbdev_pkt_sent.728462041
Short name	T581
Test name
Test status
Simulation time	185015416 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206924 kb
Host	smart-369ae1db-f848-4c90-ae5b-cb22f28c3d88
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72846 2041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.728462041
Directory	/workspace/13.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/13.usbdev_random_length_in_transaction.649015096
Short name	T575
Test name
Test status
Simulation time	192779713 ps
CPU time	0.9 seconds
Started	Aug 01 06:13:59 PM PDT 24
Finished	Aug 01 06:14:00 PM PDT 24
Peak memory	206996 kb
Host	smart-392bc84c-fa2f-4ee0-95b7-663cdcfe69bf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64901 5096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.649015096
Directory	/workspace/13.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/13.usbdev_random_length_out_transaction.2361520578
Short name	T1479
Test name
Test status
Simulation time	181272328 ps
CPU time	0.89 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	206920 kb
Host	smart-8f7f51f0-24ed-448e-827f-3e31039e48d0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23615 20578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2361520578
Directory	/workspace/13.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/13.usbdev_rx_crc_err.1155468746
Short name	T2036
Test name
Test status
Simulation time	227166994 ps
CPU time	0.9 seconds
Started	Aug 01 06:13:59 PM PDT 24
Finished	Aug 01 06:14:00 PM PDT 24
Peak memory	206900 kb
Host	smart-0c02730f-e945-44a3-a6e0-02305fd212f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11554 68746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1155468746
Directory	/workspace/13.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/13.usbdev_rx_full.1864972506
Short name	T1169
Test name
Test status
Simulation time	251758989 ps
CPU time	1.18 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206904 kb
Host	smart-3b3fbd2e-85e7-43de-b0fc-e6e20c99e520
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649 72506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.1864972506
Directory	/workspace/13.usbdev_rx_full/latest

Test location	/workspace/coverage/default/13.usbdev_setup_stage.3681677316
Short name	T504
Test name
Test status
Simulation time	162041240 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:59 PM PDT 24
Finished	Aug 01 06:14:00 PM PDT 24
Peak memory	206924 kb
Host	smart-83ae399f-e152-494a-aa26-bb321c2e8ff4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36816 77316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3681677316
Directory	/workspace/13.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/13.usbdev_smoke.2354242891
Short name	T2033
Test name
Test status
Simulation time	255415460 ps
CPU time	1.08 seconds
Started	Aug 01 06:13:59 PM PDT 24
Finished	Aug 01 06:14:00 PM PDT 24
Peak memory	206964 kb
Host	smart-71d187ea-f258-4808-a4f3-4dc8be064930
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23542 42891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2354242891
Directory	/workspace/13.usbdev_smoke/latest

Test location	/workspace/coverage/default/13.usbdev_spurious_pids_ignored.1989314217
Short name	T2599
Test name
Test status
Simulation time	2533185778 ps
CPU time	25.77 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:27 PM PDT 24
Peak memory	223448 kb
Host	smart-9281f7f1-e107-488a-b340-c1f31b5ed31b
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1989314217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1989314217
Directory	/workspace/13.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/13.usbdev_stall_priority_over_nak.1469451973
Short name	T2440
Test name
Test status
Simulation time	169493857 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206956 kb
Host	smart-c5f8ba8b-1e08-473e-9dc7-6eeae8332f6b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14694 51973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1469451973
Directory	/workspace/13.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/13.usbdev_stall_trans.2710454458
Short name	T1387
Test name
Test status
Simulation time	181285050 ps
CPU time	1 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:01 PM PDT 24
Peak memory	206960 kb
Host	smart-0770e802-19cf-4cb9-9701-add2cb074349
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27104 54458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.2710454458
Directory	/workspace/13.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/13.usbdev_stream_len_max.996518204
Short name	T1613
Test name
Test status
Simulation time	1151644601 ps
CPU time	2.74 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:03 PM PDT 24
Peak memory	207084 kb
Host	smart-b9735d81-a94b-46c6-b3b6-632f8ea51bfe
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99651 8204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.996518204
Directory	/workspace/13.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/13.usbdev_streaming_out.734287661
Short name	T1531
Test name
Test status
Simulation time	2088814717 ps
CPU time	16.33 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:20 PM PDT 24
Peak memory	216968 kb
Host	smart-6bdcaac8-01e6-40c5-8fdd-82b880199ba9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73428 7661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.734287661
Directory	/workspace/13.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.2622532002
Short name	T2167
Test name
Test status
Simulation time	819967573 ps
CPU time	5.37 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:09 PM PDT 24
Peak memory	207144 kb
Host	smart-09649ce9-5f83-400c-a412-11ca8a10d9d1
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622532002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos t_handshake.2622532002
Directory	/workspace/13.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/130.usbdev_endpoint_types.195703267
Short name	T2609
Test name
Test status
Simulation time	283817806 ps
CPU time	1.11 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206920 kb
Host	smart-41a9b3b6-d01f-48af-8ac7-bb74c3d96be9
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=195703267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.195703267
Directory	/workspace/130.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/132.usbdev_endpoint_types.3338005728
Short name	T418
Test name
Test status
Simulation time	519410921 ps
CPU time	1.41 seconds
Started	Aug 01 06:20:19 PM PDT 24
Finished	Aug 01 06:20:21 PM PDT 24
Peak memory	206832 kb
Host	smart-a1a6e8c5-768f-4ed6-af08-d9597a99bfb0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3338005728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.3338005728
Directory	/workspace/132.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/133.usbdev_endpoint_types.1762531070
Short name	T2192
Test name
Test status
Simulation time	150193495 ps
CPU time	0.89 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206900 kb
Host	smart-25333011-1235-447a-bfbf-21f8fc37d70d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1762531070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.1762531070
Directory	/workspace/133.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/134.usbdev_endpoint_types.2383793193
Short name	T2417
Test name
Test status
Simulation time	528068579 ps
CPU time	1.41 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206920 kb
Host	smart-ec8d5e12-fedb-48ad-9a75-e821e796a75d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2383793193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.2383793193
Directory	/workspace/134.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/136.usbdev_endpoint_types.633652788
Short name	T1422
Test name
Test status
Simulation time	165816358 ps
CPU time	0.91 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206900 kb
Host	smart-6dcb4268-00fd-48b8-b1ca-5c52cff1f2d6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=633652788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.633652788
Directory	/workspace/136.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/137.usbdev_endpoint_types.727014445
Short name	T310
Test name
Test status
Simulation time	757446316 ps
CPU time	1.68 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206896 kb
Host	smart-bbc84c1e-e4c6-4569-bef6-0644e3e1fec6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=727014445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.727014445
Directory	/workspace/137.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/138.usbdev_endpoint_types.3535233463
Short name	T290
Test name
Test status
Simulation time	394453519 ps
CPU time	1.18 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206832 kb
Host	smart-639b8660-d873-4b6b-9785-d3c72566ab58
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3535233463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.3535233463
Directory	/workspace/138.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/14.usbdev_alert_test.1256648001
Short name	T2191
Test name
Test status
Simulation time	33909529 ps
CPU time	0.69 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	207004 kb
Host	smart-344573f0-7d8d-43f7-849a-dc8fffba0d71
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1256648001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1256648001
Directory	/workspace/14.usbdev_alert_test/latest

Test location	/workspace/coverage/default/14.usbdev_av_buffer.2471562399
Short name	T579
Test name
Test status
Simulation time	219105362 ps
CPU time	1.03 seconds
Started	Aug 01 06:14:05 PM PDT 24
Finished	Aug 01 06:14:06 PM PDT 24
Peak memory	206964 kb
Host	smart-90a0c532-aa27-432d-a031-cb2383a1603a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24715 62399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2471562399
Directory	/workspace/14.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/14.usbdev_bitstuff_err.1597104790
Short name	T1050
Test name
Test status
Simulation time	235271774 ps
CPU time	1.02 seconds
Started	Aug 01 06:14:06 PM PDT 24
Finished	Aug 01 06:14:07 PM PDT 24
Peak memory	206908 kb
Host	smart-053abeec-805c-4ca8-8f32-55277e12f32e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15971 04790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1597104790
Directory	/workspace/14.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/14.usbdev_data_toggle_clear.123752466
Short name	T2740
Test name
Test status
Simulation time	260365760 ps
CPU time	1.11 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	206976 kb
Host	smart-b2954abc-9c42-4e7b-b4c4-5a658e6f223a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12375 2466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.123752466
Directory	/workspace/14.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/14.usbdev_data_toggle_restore.2238660633
Short name	T1454
Test name
Test status
Simulation time	748324250 ps
CPU time	2.12 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:03 PM PDT 24
Peak memory	207124 kb
Host	smart-6709b282-a3bc-4811-a1b5-644cafcb0f08
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2238660633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2238660633
Directory	/workspace/14.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/14.usbdev_device_timeout.2616181449
Short name	T1497
Test name
Test status
Simulation time	479746298 ps
CPU time	8.32 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:12 PM PDT 24
Peak memory	207116 kb
Host	smart-8d6f89de-5e35-445c-a4a2-811700329aa9
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616181449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.2616181449
Directory	/workspace/14.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/14.usbdev_disable_endpoint.323454779
Short name	T2461
Test name
Test status
Simulation time	617591934 ps
CPU time	1.58 seconds
Started	Aug 01 06:14:00 PM PDT 24
Finished	Aug 01 06:14:02 PM PDT 24
Peak memory	206900 kb
Host	smart-b33a69b3-bdb5-4385-8593-681e98b377a4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32345 4779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.323454779
Directory	/workspace/14.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/14.usbdev_disconnected.783189200
Short name	T1522
Test name
Test status
Simulation time	152591647 ps
CPU time	0.86 seconds
Started	Aug 01 06:14:04 PM PDT 24
Finished	Aug 01 06:14:05 PM PDT 24
Peak memory	206908 kb
Host	smart-bce798c9-b454-464c-8e9b-f8e1a471b1ee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78318 9200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.783189200
Directory	/workspace/14.usbdev_disconnected/latest

Test location	/workspace/coverage/default/14.usbdev_enable.712452617
Short name	T1106
Test name
Test status
Simulation time	52005673 ps
CPU time	0.73 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	206920 kb
Host	smart-a6e69056-627a-41ba-b2c7-a421ab517cb1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71245 2617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.712452617
Directory	/workspace/14.usbdev_enable/latest

Test location	/workspace/coverage/default/14.usbdev_endpoint_access.998572039
Short name	T574
Test name
Test status
Simulation time	884067555 ps
CPU time	2.41 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	207052 kb
Host	smart-8a88c1eb-d359-4230-9bbb-09b1256ce373
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99857 2039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.998572039
Directory	/workspace/14.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/14.usbdev_endpoint_types.1754913998
Short name	T370
Test name
Test status
Simulation time	731140107 ps
CPU time	1.68 seconds
Started	Aug 01 06:14:06 PM PDT 24
Finished	Aug 01 06:14:08 PM PDT 24
Peak memory	206916 kb
Host	smart-dfea72f1-b936-4c47-b17d-80101767b825
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1754913998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.1754913998
Directory	/workspace/14.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/14.usbdev_fifo_rst.2297136724
Short name	T702
Test name
Test status
Simulation time	193417811 ps
CPU time	1.49 seconds
Started	Aug 01 06:13:59 PM PDT 24
Finished	Aug 01 06:14:01 PM PDT 24
Peak memory	207144 kb
Host	smart-0b458fbb-88ce-44c4-a79a-a6a04442ce0a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22971 36724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2297136724
Directory	/workspace/14.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/14.usbdev_in_iso.2521125367
Short name	T1644
Test name
Test status
Simulation time	235072256 ps
CPU time	1.26 seconds
Started	Aug 01 06:14:02 PM PDT 24
Finished	Aug 01 06:14:04 PM PDT 24
Peak memory	215292 kb
Host	smart-2cfe3270-bc48-487a-8132-f10297494eb9
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2521125367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2521125367
Directory	/workspace/14.usbdev_in_iso/latest

Test location	/workspace/coverage/default/14.usbdev_in_stall.1722981424
Short name	T1049
Test name
Test status
Simulation time	163933722 ps
CPU time	0.96 seconds
Started	Aug 01 06:14:01 PM PDT 24
Finished	Aug 01 06:14:03 PM PDT 24
Peak memory	206920 kb
Host	smart-d7113227-b2e0-4872-ba07-1e1e4a9e56bb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17229 81424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1722981424
Directory	/workspace/14.usbdev_in_stall/latest

Test location	/workspace/coverage/default/14.usbdev_in_trans.4120841610
Short name	T2304
Test name
Test status
Simulation time	174293641 ps
CPU time	0.98 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	206936 kb
Host	smart-5c77de54-235a-4066-b9d9-631244e45379
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41208 41610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.4120841610
Directory	/workspace/14.usbdev_in_trans/latest

Test location	/workspace/coverage/default/14.usbdev_invalid_sync.2659982276
Short name	T1592
Test name
Test status
Simulation time	4795223253 ps
CPU time	147.04 seconds
Started	Aug 01 06:14:02 PM PDT 24
Finished	Aug 01 06:16:29 PM PDT 24
Peak memory	217192 kb
Host	smart-d5b25c58-3293-4fc4-b8b5-87ec51c278e1
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2659982276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.2659982276
Directory	/workspace/14.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/14.usbdev_iso_retraction.3348231599
Short name	T1443
Test name
Test status
Simulation time	9013856195 ps
CPU time	111.55 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:16:07 PM PDT 24
Peak memory	207196 kb
Host	smart-6ac17a68-8657-4329-a8f7-7ea4d96c5c10
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3348231599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.3348231599
Directory	/workspace/14.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/14.usbdev_link_in_err.3789105766
Short name	T2759
Test name
Test status
Simulation time	194232597 ps
CPU time	0.91 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	206916 kb
Host	smart-f2ac2129-249b-4237-be6e-fecf93154789
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37891 05766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3789105766
Directory	/workspace/14.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/14.usbdev_link_suspend.3295877560
Short name	T2148
Test name
Test status
Simulation time	9465411701 ps
CPU time	11.08 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:27 PM PDT 24
Peak memory	207172 kb
Host	smart-a3e2ca8f-eaa6-4795-99d1-bd65471a7fb0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958 77560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.3295877560
Directory	/workspace/14.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/14.usbdev_low_speed_traffic.2905698432
Short name	T1194
Test name
Test status
Simulation time	3061580403 ps
CPU time	29.56 seconds
Started	Aug 01 06:14:14 PM PDT 24
Finished	Aug 01 06:14:44 PM PDT 24
Peak memory	223476 kb
Host	smart-1b6ed985-8706-4b48-a707-6491b4ed2007
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29056 98432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.2905698432
Directory	/workspace/14.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/14.usbdev_max_inter_pkt_delay.106216108
Short name	T1560
Test name
Test status
Simulation time	2053076230 ps
CPU time	15.29 seconds
Started	Aug 01 06:14:24 PM PDT 24
Finished	Aug 01 06:14:40 PM PDT 24
Peak memory	223472 kb
Host	smart-e5a13065-a1c4-45bf-a5b5-3e9c4802fc1e
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=106216108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.106216108
Directory	/workspace/14.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/14.usbdev_max_length_in_transaction.3693735432
Short name	T1330
Test name
Test status
Simulation time	283977014 ps
CPU time	1.04 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	206960 kb
Host	smart-7639bf33-5e17-43fe-8f51-a7e2f4de930c
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3693735432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3693735432
Directory	/workspace/14.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/14.usbdev_max_length_out_transaction.2868536256
Short name	T876
Test name
Test status
Simulation time	188823328 ps
CPU time	0.97 seconds
Started	Aug 01 06:14:23 PM PDT 24
Finished	Aug 01 06:14:24 PM PDT 24
Peak memory	207000 kb
Host	smart-29a88fb8-571a-4c45-91fc-1ffd1144e926
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28685 36256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2868536256
Directory	/workspace/14.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.3615147824
Short name	T201
Test name
Test status
Simulation time	2802396492 ps
CPU time	79.2 seconds
Started	Aug 01 06:14:23 PM PDT 24
Finished	Aug 01 06:15:42 PM PDT 24
Peak memory	217280 kb
Host	smart-11cba616-f3c9-4ea7-bb58-666650f5efae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36151 47824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.3615147824
Directory	/workspace/14.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/14.usbdev_max_usb_traffic.3166860157
Short name	T1014
Test name
Test status
Simulation time	2068629157 ps
CPU time	21.78 seconds
Started	Aug 01 06:14:19 PM PDT 24
Finished	Aug 01 06:14:41 PM PDT 24
Peak memory	223488 kb
Host	smart-9cffa723-b6d7-4f2b-86fa-f47c3b6295d2
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3166860157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3166860157
Directory	/workspace/14.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/14.usbdev_min_inter_pkt_delay.587868233
Short name	T2551
Test name
Test status
Simulation time	3843718026 ps
CPU time	37.64 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:53 PM PDT 24
Peak memory	216944 kb
Host	smart-06b9a57c-93c1-4805-96d6-52116f02ad01
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=587868233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.587868233
Directory	/workspace/14.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/14.usbdev_min_length_in_transaction.2047996314
Short name	T478
Test name
Test status
Simulation time	181155095 ps
CPU time	0.86 seconds
Started	Aug 01 06:14:19 PM PDT 24
Finished	Aug 01 06:14:20 PM PDT 24
Peak memory	206956 kb
Host	smart-ea182d41-b0bb-4ee2-a4a2-f3e8fc656acc
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2047996314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2047996314
Directory	/workspace/14.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/14.usbdev_min_length_out_transaction.3140726465
Short name	T1840
Test name
Test status
Simulation time	158071552 ps
CPU time	0.81 seconds
Started	Aug 01 06:14:14 PM PDT 24
Finished	Aug 01 06:14:15 PM PDT 24
Peak memory	206944 kb
Host	smart-82330693-f2e9-4bfa-bd31-75c3a53ae7f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31407 26465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3140726465
Directory	/workspace/14.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/14.usbdev_out_iso.3286832057
Short name	T1001
Test name
Test status
Simulation time	234841948 ps
CPU time	0.99 seconds
Started	Aug 01 06:14:19 PM PDT 24
Finished	Aug 01 06:14:20 PM PDT 24
Peak memory	206948 kb
Host	smart-e39799ae-b8e5-4471-902a-28ccac5b36a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32868 32057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3286832057
Directory	/workspace/14.usbdev_out_iso/latest

Test location	/workspace/coverage/default/14.usbdev_out_stall.1274715762
Short name	T1939
Test name
Test status
Simulation time	167058410 ps
CPU time	0.89 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:16 PM PDT 24
Peak memory	206904 kb
Host	smart-4c8c42f2-f7a6-48da-aa1d-03d19eb7d944
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12747 15762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1274715762
Directory	/workspace/14.usbdev_out_stall/latest

Test location	/workspace/coverage/default/14.usbdev_out_trans_nak.4177830469
Short name	T549
Test name
Test status
Simulation time	152828441 ps
CPU time	0.83 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:17 PM PDT 24
Peak memory	206944 kb
Host	smart-25de0802-f016-4e80-b018-17132a015901
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41778 30469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.4177830469
Directory	/workspace/14.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/14.usbdev_pending_in_trans.202732945
Short name	T931
Test name
Test status
Simulation time	152564561 ps
CPU time	0.98 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	206964 kb
Host	smart-d4b45203-5173-43fe-b697-148b25f79130
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20273 2945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.202732945
Directory	/workspace/14.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/14.usbdev_phy_config_pinflip.1812337730
Short name	T1972
Test name
Test status
Simulation time	248430018 ps
CPU time	1.07 seconds
Started	Aug 01 06:14:14 PM PDT 24
Finished	Aug 01 06:14:16 PM PDT 24
Peak memory	206948 kb
Host	smart-3b0b9927-19e2-4a04-a4eb-fd86285bb417
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1812337730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1812337730
Directory	/workspace/14.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.3342947785
Short name	T121
Test name
Test status
Simulation time	148973419 ps
CPU time	0.85 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	206936 kb
Host	smart-c759d35a-4cc0-49c3-b703-f38bc201b7c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33429 47785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.3342947785
Directory	/workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/14.usbdev_phy_pins_sense.4207468072
Short name	T2746
Test name
Test status
Simulation time	37185684 ps
CPU time	0.68 seconds
Started	Aug 01 06:14:18 PM PDT 24
Finished	Aug 01 06:14:19 PM PDT 24
Peak memory	206908 kb
Host	smart-38d506f9-eab4-403a-98c9-c1ad087c0c56
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42074 68072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.4207468072
Directory	/workspace/14.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/14.usbdev_pkt_buffer.2949921785
Short name	T252
Test name
Test status
Simulation time	10535302894 ps
CPU time	26.59 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	215376 kb
Host	smart-1bd15fb3-cd75-4124-8a11-6b947054f6b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29499 21785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2949921785
Directory	/workspace/14.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/14.usbdev_pkt_received.243155528
Short name	T880
Test name
Test status
Simulation time	169556445 ps
CPU time	0.84 seconds
Started	Aug 01 06:14:13 PM PDT 24
Finished	Aug 01 06:14:15 PM PDT 24
Peak memory	206944 kb
Host	smart-6d87dd0e-9aff-4bbf-9edd-cec124f8f49f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24315 5528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.243155528
Directory	/workspace/14.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/14.usbdev_pkt_sent.3312903776
Short name	T651
Test name
Test status
Simulation time	176908443 ps
CPU time	0.92 seconds
Started	Aug 01 06:14:13 PM PDT 24
Finished	Aug 01 06:14:14 PM PDT 24
Peak memory	206900 kb
Host	smart-631c87d2-f2fd-47a3-8f22-0c4356248ae8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129 03776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3312903776
Directory	/workspace/14.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/14.usbdev_random_length_in_transaction.239301160
Short name	T2343
Test name
Test status
Simulation time	176427085 ps
CPU time	0.89 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:17 PM PDT 24
Peak memory	206924 kb
Host	smart-93ec8635-05e3-47da-a9ac-4d3006dec544
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23930 1160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.239301160
Directory	/workspace/14.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/14.usbdev_random_length_out_transaction.443932029
Short name	T1075
Test name
Test status
Simulation time	163450530 ps
CPU time	0.92 seconds
Started	Aug 01 06:14:19 PM PDT 24
Finished	Aug 01 06:14:20 PM PDT 24
Peak memory	206952 kb
Host	smart-11212ee4-97b1-4fae-b2a0-ae4f0559db26
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44393 2029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.443932029
Directory	/workspace/14.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/14.usbdev_rx_crc_err.2308364515
Short name	T2637
Test name
Test status
Simulation time	146917254 ps
CPU time	0.81 seconds
Started	Aug 01 06:14:14 PM PDT 24
Finished	Aug 01 06:14:15 PM PDT 24
Peak memory	206972 kb
Host	smart-ea4b4241-1dbf-43db-acb8-674f98f920b3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23083 64515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2308364515
Directory	/workspace/14.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/14.usbdev_rx_full.1848660035
Short name	T2161
Test name
Test status
Simulation time	319913701 ps
CPU time	1.24 seconds
Started	Aug 01 06:14:18 PM PDT 24
Finished	Aug 01 06:14:20 PM PDT 24
Peak memory	206944 kb
Host	smart-cd5767ea-2bcf-43e5-8de9-0218066f2ae5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18486 60035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.1848660035
Directory	/workspace/14.usbdev_rx_full/latest

Test location	/workspace/coverage/default/14.usbdev_setup_stage.1519669706
Short name	T2690
Test name
Test status
Simulation time	174466169 ps
CPU time	0.84 seconds
Started	Aug 01 06:14:18 PM PDT 24
Finished	Aug 01 06:14:19 PM PDT 24
Peak memory	206872 kb
Host	smart-7693a2a7-b0e7-4130-a6a5-2673bfe692e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15196 69706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1519669706
Directory	/workspace/14.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/14.usbdev_setup_trans_ignored.1581296257
Short name	T2901
Test name
Test status
Simulation time	174126868 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:19 PM PDT 24
Finished	Aug 01 06:14:20 PM PDT 24
Peak memory	206908 kb
Host	smart-da3d21e4-0d07-465d-99e3-20e76f580e58
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15812 96257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1581296257
Directory	/workspace/14.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/14.usbdev_smoke.4088282473
Short name	T558
Test name
Test status
Simulation time	273006098 ps
CPU time	1.09 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:17 PM PDT 24
Peak memory	206956 kb
Host	smart-a8926269-5d0e-451f-a3cb-798219fbbe5c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40882 82473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4088282473
Directory	/workspace/14.usbdev_smoke/latest

Test location	/workspace/coverage/default/14.usbdev_spurious_pids_ignored.1627882166
Short name	T2660
Test name
Test status
Simulation time	2450198370 ps
CPU time	18.4 seconds
Started	Aug 01 06:14:23 PM PDT 24
Finished	Aug 01 06:14:41 PM PDT 24
Peak memory	223620 kb
Host	smart-b563e482-d7d2-4eb2-98fc-842ba3e88162
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1627882166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1627882166
Directory	/workspace/14.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/14.usbdev_stall_priority_over_nak.2954939736
Short name	T2638
Test name
Test status
Simulation time	151862437 ps
CPU time	0.9 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	206900 kb
Host	smart-7d9936e3-9153-4459-ad7a-e89dd03beddd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29549 39736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2954939736
Directory	/workspace/14.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/14.usbdev_stall_trans.2086690257
Short name	T505
Test name
Test status
Simulation time	175916443 ps
CPU time	0.88 seconds
Started	Aug 01 06:14:14 PM PDT 24
Finished	Aug 01 06:14:15 PM PDT 24
Peak memory	206944 kb
Host	smart-8b286d0c-6ac4-4921-b13e-753fd0971c6a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20866 90257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2086690257
Directory	/workspace/14.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/14.usbdev_stream_len_max.3039557855
Short name	T532
Test name
Test status
Simulation time	1269628880 ps
CPU time	3.2 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:19 PM PDT 24
Peak memory	207120 kb
Host	smart-bd257ab4-5154-4943-9ad0-c61873377271
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30395 57855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.3039557855
Directory	/workspace/14.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/14.usbdev_streaming_out.577434756
Short name	T1058
Test name
Test status
Simulation time	3514733457 ps
CPU time	27.42 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:45 PM PDT 24
Peak memory	215280 kb
Host	smart-f194e477-53df-448e-b7fe-ab985eb0c3c9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57743 4756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.577434756
Directory	/workspace/14.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.2462947598
Short name	T14
Test name
Test status
Simulation time	2008036426 ps
CPU time	47.58 seconds
Started	Aug 01 06:14:03 PM PDT 24
Finished	Aug 01 06:14:51 PM PDT 24
Peak memory	207156 kb
Host	smart-52970e67-32f5-4baf-b66e-9a3ee327c473
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462947598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_hos t_handshake.2462947598
Directory	/workspace/14.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/141.usbdev_endpoint_types.689821654
Short name	T337
Test name
Test status
Simulation time	535866405 ps
CPU time	1.47 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206924 kb
Host	smart-9bcc2c09-b105-4425-9e5d-d38dc1071a48
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=689821654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.689821654
Directory	/workspace/141.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/142.usbdev_endpoint_types.1447424387
Short name	T344
Test name
Test status
Simulation time	626744626 ps
CPU time	1.55 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206904 kb
Host	smart-7580f08c-bfa7-4c5f-bfa4-32e2627cbe03
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1447424387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.1447424387
Directory	/workspace/142.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/143.usbdev_endpoint_types.475747217
Short name	T367
Test name
Test status
Simulation time	465936413 ps
CPU time	1.42 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206908 kb
Host	smart-1d9d5489-b680-40e4-b0e2-5c771529a360
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=475747217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.475747217
Directory	/workspace/143.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/144.usbdev_endpoint_types.2984665100
Short name	T671
Test name
Test status
Simulation time	247078734 ps
CPU time	0.94 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206924 kb
Host	smart-12f9faf4-a85d-40b6-9303-a1915b6b9d0a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2984665100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.2984665100
Directory	/workspace/144.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/145.usbdev_endpoint_types.3274723714
Short name	T2203
Test name
Test status
Simulation time	441943769 ps
CPU time	1.41 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206904 kb
Host	smart-1290232c-35e1-4b39-a7e7-d89e176b38d3
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3274723714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.3274723714
Directory	/workspace/145.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/146.usbdev_endpoint_types.4269206842
Short name	T2674
Test name
Test status
Simulation time	575219791 ps
CPU time	1.74 seconds
Started	Aug 01 06:20:01 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206896 kb
Host	smart-e2aab5d6-5751-4a2b-9de4-b341ecbe27fc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4269206842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.4269206842
Directory	/workspace/146.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/149.usbdev_endpoint_types.3179636506
Short name	T371
Test name
Test status
Simulation time	513666777 ps
CPU time	1.48 seconds
Started	Aug 01 06:20:25 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206924 kb
Host	smart-74e4b7c6-4ea7-4043-be7a-de1aa2cbf119
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3179636506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.3179636506
Directory	/workspace/149.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/15.usbdev_alert_test.1255189586
Short name	T1012
Test name
Test status
Simulation time	44845321 ps
CPU time	0.66 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:14:33 PM PDT 24
Peak memory	206988 kb
Host	smart-352549c5-1642-4c39-97be-9031be410da7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1255189586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.1255189586
Directory	/workspace/15.usbdev_alert_test/latest

Test location	/workspace/coverage/default/15.usbdev_av_buffer.3899569286
Short name	T2788
Test name
Test status
Simulation time	173358906 ps
CPU time	0.86 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	206956 kb
Host	smart-2a47748a-a9bd-4a6b-95aa-379b3bd392ee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38995 69286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3899569286
Directory	/workspace/15.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/15.usbdev_data_toggle_clear.4166164932
Short name	T1526
Test name
Test status
Simulation time	340362939 ps
CPU time	1.25 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:17 PM PDT 24
Peak memory	206924 kb
Host	smart-d2694b9b-dfc4-4425-93bd-9388c99711ff
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661 64932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.4166164932
Directory	/workspace/15.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/15.usbdev_data_toggle_restore.3126777674
Short name	T606
Test name
Test status
Simulation time	1442923045 ps
CPU time	3.39 seconds
Started	Aug 01 06:14:14 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	207140 kb
Host	smart-c6218672-0357-4ca1-a962-45a0f1ea53a7
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3126777674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3126777674
Directory	/workspace/15.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/15.usbdev_device_timeout.1678783615
Short name	T2176
Test name
Test status
Simulation time	5709660258 ps
CPU time	36.01 seconds
Started	Aug 01 06:14:20 PM PDT 24
Finished	Aug 01 06:14:56 PM PDT 24
Peak memory	207140 kb
Host	smart-e846840b-399f-411b-97fe-b7779eb8ba44
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678783615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.1678783615
Directory	/workspace/15.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/15.usbdev_disable_endpoint.1437027128
Short name	T289
Test name
Test status
Simulation time	691948988 ps
CPU time	1.79 seconds
Started	Aug 01 06:14:18 PM PDT 24
Finished	Aug 01 06:14:20 PM PDT 24
Peak memory	206884 kb
Host	smart-50bc019f-0a95-4922-8123-6ab3707133f6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14370 27128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.1437027128
Directory	/workspace/15.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/15.usbdev_disconnected.2718362366
Short name	T599
Test name
Test status
Simulation time	192826138 ps
CPU time	0.92 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:16 PM PDT 24
Peak memory	206916 kb
Host	smart-823d6225-4df6-4b92-8bb1-3869ecd0c320
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27183 62366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2718362366
Directory	/workspace/15.usbdev_disconnected/latest

Test location	/workspace/coverage/default/15.usbdev_enable.389704312
Short name	T513
Test name
Test status
Simulation time	39955405 ps
CPU time	0.72 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:17 PM PDT 24
Peak memory	206920 kb
Host	smart-f994d6f0-a22b-4b29-a2f1-a9b0eebd008d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38970 4312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.389704312
Directory	/workspace/15.usbdev_enable/latest

Test location	/workspace/coverage/default/15.usbdev_endpoint_access.2174674969
Short name	T2327
Test name
Test status
Simulation time	856700084 ps
CPU time	2.22 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:17 PM PDT 24
Peak memory	207400 kb
Host	smart-ef629e02-baff-4302-8453-bfdd54a0407f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21746 74969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.2174674969
Directory	/workspace/15.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/15.usbdev_fifo_rst.1331824812
Short name	T1731
Test name
Test status
Simulation time	245473158 ps
CPU time	2 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:19 PM PDT 24
Peak memory	207072 kb
Host	smart-1272fa45-23a1-40ae-bf62-57d675218776
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13318 24812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.1331824812
Directory	/workspace/15.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/15.usbdev_in_iso.2404090662
Short name	T1603
Test name
Test status
Simulation time	188034277 ps
CPU time	1.02 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:19 PM PDT 24
Peak memory	215284 kb
Host	smart-54110eda-5abf-4b21-9a80-8b21bf49bd21
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2404090662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2404090662
Directory	/workspace/15.usbdev_in_iso/latest

Test location	/workspace/coverage/default/15.usbdev_in_stall.480035389
Short name	T1786
Test name
Test status
Simulation time	163425385 ps
CPU time	0.85 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:16 PM PDT 24
Peak memory	206892 kb
Host	smart-b49c2b49-141d-4945-861e-42338a2cf44d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48003 5389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.480035389
Directory	/workspace/15.usbdev_in_stall/latest

Test location	/workspace/coverage/default/15.usbdev_in_trans.3984741076
Short name	T1528
Test name
Test status
Simulation time	151227044 ps
CPU time	0.99 seconds
Started	Aug 01 06:14:19 PM PDT 24
Finished	Aug 01 06:14:20 PM PDT 24
Peak memory	206920 kb
Host	smart-ed196a29-ff95-4cdd-9e00-52c5553f0859
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39847 41076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3984741076
Directory	/workspace/15.usbdev_in_trans/latest

Test location	/workspace/coverage/default/15.usbdev_invalid_sync.2900575617
Short name	T2841
Test name
Test status
Simulation time	3503455819 ps
CPU time	27.43 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:44 PM PDT 24
Peak memory	216736 kb
Host	smart-3b2ffbc9-32d8-4b3d-9d30-1ae70948652e
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2900575617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.2900575617
Directory	/workspace/15.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/15.usbdev_iso_retraction.1613488054
Short name	T2342
Test name
Test status
Simulation time	12959366969 ps
CPU time	92.14 seconds
Started	Aug 01 06:14:19 PM PDT 24
Finished	Aug 01 06:15:51 PM PDT 24
Peak memory	207108 kb
Host	smart-38292775-1843-463e-b0ae-652ca0fe232e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1613488054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.1613488054
Directory	/workspace/15.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/15.usbdev_link_in_err.2328073258
Short name	T640
Test name
Test status
Simulation time	238712757 ps
CPU time	1.05 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:16 PM PDT 24
Peak memory	206944 kb
Host	smart-e1f6ca03-b5e3-480d-a1e2-d20d02c682ea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23280 73258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2328073258
Directory	/workspace/15.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/15.usbdev_link_suspend.3744984670
Short name	T1766
Test name
Test status
Simulation time	10961422855 ps
CPU time	13.7 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:30 PM PDT 24
Peak memory	207136 kb
Host	smart-fe7beaf6-a255-47bd-8cc8-043000694ade
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37449 84670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3744984670
Directory	/workspace/15.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/15.usbdev_low_speed_traffic.1213138679
Short name	T285
Test name
Test status
Simulation time	4086113213 ps
CPU time	31.48 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:47 PM PDT 24
Peak memory	218040 kb
Host	smart-8d8818b8-8cfb-40cb-93e1-fea73a08b440
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12131 38679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.1213138679
Directory	/workspace/15.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3233730125
Short name	T2254
Test name
Test status
Simulation time	1852320283 ps
CPU time	13.88 seconds
Started	Aug 01 06:14:17 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	207120 kb
Host	smart-2122e578-ff97-49f9-981a-60c2c0c0182c
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3233730125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3233730125
Directory	/workspace/15.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/15.usbdev_max_length_in_transaction.309088734
Short name	T1977
Test name
Test status
Simulation time	248299328 ps
CPU time	1.04 seconds
Started	Aug 01 06:14:16 PM PDT 24
Finished	Aug 01 06:14:18 PM PDT 24
Peak memory	206960 kb
Host	smart-35c40c3d-f983-48aa-9962-c68f118a7b66
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=309088734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.309088734
Directory	/workspace/15.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/15.usbdev_max_length_out_transaction.1882554763
Short name	T622
Test name
Test status
Simulation time	202616445 ps
CPU time	1.04 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:17 PM PDT 24
Peak memory	206972 kb
Host	smart-135fdfb1-3150-4ce9-b30f-191ca4d26f6a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18825 54763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1882554763
Directory	/workspace/15.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.1644940832
Short name	T1778
Test name
Test status
Simulation time	2810173757 ps
CPU time	23.55 seconds
Started	Aug 01 06:14:15 PM PDT 24
Finished	Aug 01 06:14:39 PM PDT 24
Peak memory	223540 kb
Host	smart-5c69cf15-b5e1-4279-b719-134cf8a11afb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16449 40832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.1644940832
Directory	/workspace/15.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/15.usbdev_min_inter_pkt_delay.3008601814
Short name	T1642
Test name
Test status
Simulation time	2247520716 ps
CPU time	23.35 seconds
Started	Aug 01 06:14:18 PM PDT 24
Finished	Aug 01 06:14:42 PM PDT 24
Peak memory	223488 kb
Host	smart-092a1144-910a-4852-be1c-46a60a79018c
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3008601814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.3008601814
Directory	/workspace/15.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/15.usbdev_min_length_in_transaction.1678634985
Short name	T1477
Test name
Test status
Simulation time	150152234 ps
CPU time	0.88 seconds
Started	Aug 01 06:14:14 PM PDT 24
Finished	Aug 01 06:14:15 PM PDT 24
Peak memory	206952 kb
Host	smart-0aa25a2a-4a1b-49e7-955b-0a1d963fa961
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1678634985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1678634985
Directory	/workspace/15.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/15.usbdev_min_length_out_transaction.2756955900
Short name	T475
Test name
Test status
Simulation time	144381392 ps
CPU time	0.88 seconds
Started	Aug 01 06:14:20 PM PDT 24
Finished	Aug 01 06:14:21 PM PDT 24
Peak memory	206928 kb
Host	smart-7eb893cb-af19-4a5c-8d80-77977f0c744c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27569 55900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2756955900
Directory	/workspace/15.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/15.usbdev_out_iso.311849275
Short name	T1900
Test name
Test status
Simulation time	163451979 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:31 PM PDT 24
Finished	Aug 01 06:14:32 PM PDT 24
Peak memory	206928 kb
Host	smart-e0de4a7f-5b9e-4d6b-94af-a3b88e73d4ee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31184 9275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.311849275
Directory	/workspace/15.usbdev_out_iso/latest

Test location	/workspace/coverage/default/15.usbdev_out_stall.1586589612
Short name	T1978
Test name
Test status
Simulation time	150731461 ps
CPU time	0.82 seconds
Started	Aug 01 06:14:27 PM PDT 24
Finished	Aug 01 06:14:27 PM PDT 24
Peak memory	206972 kb
Host	smart-04c8663e-5319-46b8-b2a1-85c3a5caf6bb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15865 89612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1586589612
Directory	/workspace/15.usbdev_out_stall/latest

Test location	/workspace/coverage/default/15.usbdev_out_trans_nak.2329289377
Short name	T1770
Test name
Test status
Simulation time	148981410 ps
CPU time	0.81 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:14:30 PM PDT 24
Peak memory	206848 kb
Host	smart-5d24332b-55df-49fb-b80a-b4642c7146e7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23292 89377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2329289377
Directory	/workspace/15.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/15.usbdev_pending_in_trans.3773823696
Short name	T2591
Test name
Test status
Simulation time	163242640 ps
CPU time	0.86 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206940 kb
Host	smart-72339ec1-f864-48f1-9197-4b40ab97dbc4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37738 23696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3773823696
Directory	/workspace/15.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/15.usbdev_phy_config_pinflip.879117006
Short name	T1557
Test name
Test status
Simulation time	218700362 ps
CPU time	1.03 seconds
Started	Aug 01 06:14:28 PM PDT 24
Finished	Aug 01 06:14:29 PM PDT 24
Peak memory	206940 kb
Host	smart-d4188573-7eb3-4911-9e13-0b068d3f5f0f
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=879117006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.879117006
Directory	/workspace/15.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3133810960
Short name	T1816
Test name
Test status
Simulation time	142552308 ps
CPU time	0.86 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206920 kb
Host	smart-2d3bfe1d-f4a1-4653-82b3-938c09c421a7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31338 10960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3133810960
Directory	/workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/15.usbdev_pkt_buffer.2073694134
Short name	T2040
Test name
Test status
Simulation time	6564486650 ps
CPU time	17.82 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:14:47 PM PDT 24
Peak memory	215404 kb
Host	smart-7987d99a-ab23-498d-b953-20e9a3e9c11f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20736 94134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.2073694134
Directory	/workspace/15.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/15.usbdev_pkt_received.2119575058
Short name	T652
Test name
Test status
Simulation time	207663206 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:14:30 PM PDT 24
Peak memory	206948 kb
Host	smart-bca03745-c191-432e-a1c9-ee35fe7c184f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21195 75058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2119575058
Directory	/workspace/15.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/15.usbdev_pkt_sent.450144057
Short name	T1650
Test name
Test status
Simulation time	214488343 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:14:30 PM PDT 24
Peak memory	206936 kb
Host	smart-706d4194-4fce-4434-8960-afa1aa99fdc2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45014 4057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.450144057
Directory	/workspace/15.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/15.usbdev_random_length_in_transaction.3445099746
Short name	T2195
Test name
Test status
Simulation time	213786693 ps
CPU time	0.91 seconds
Started	Aug 01 06:14:35 PM PDT 24
Finished	Aug 01 06:14:36 PM PDT 24
Peak memory	206908 kb
Host	smart-7dfea29e-1b43-4650-b342-6c5ec962d5ef
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34450 99746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3445099746
Directory	/workspace/15.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/15.usbdev_random_length_out_transaction.1195557068
Short name	T1973
Test name
Test status
Simulation time	153944699 ps
CPU time	0.84 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206968 kb
Host	smart-a456fa3e-160f-470e-b6cf-e1170f85deaf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11955 57068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1195557068
Directory	/workspace/15.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/15.usbdev_rx_crc_err.1337325456
Short name	T2464
Test name
Test status
Simulation time	141163948 ps
CPU time	0.82 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206932 kb
Host	smart-92c5ea73-8968-49ac-9535-50c52d47b9cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13373 25456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1337325456
Directory	/workspace/15.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/15.usbdev_rx_full.191808734
Short name	T2624
Test name
Test status
Simulation time	338105195 ps
CPU time	1.22 seconds
Started	Aug 01 06:14:27 PM PDT 24
Finished	Aug 01 06:14:29 PM PDT 24
Peak memory	206920 kb
Host	smart-e367e3c4-6c26-498d-90c2-570cef622443
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19180 8734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.191808734
Directory	/workspace/15.usbdev_rx_full/latest

Test location	/workspace/coverage/default/15.usbdev_setup_stage.3019460890
Short name	T655
Test name
Test status
Simulation time	165360364 ps
CPU time	0.86 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206872 kb
Host	smart-e58f0662-0374-4756-a37e-5b529989c8c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30194 60890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.3019460890
Directory	/workspace/15.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/15.usbdev_setup_trans_ignored.947610281
Short name	T1225
Test name
Test status
Simulation time	157801193 ps
CPU time	0.85 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206928 kb
Host	smart-9b8f0cd6-3348-4489-8f43-1419b859060b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94761 0281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.947610281
Directory	/workspace/15.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/15.usbdev_smoke.42745214
Short name	T951
Test name
Test status
Simulation time	212805516 ps
CPU time	1 seconds
Started	Aug 01 06:14:27 PM PDT 24
Finished	Aug 01 06:14:28 PM PDT 24
Peak memory	206920 kb
Host	smart-dda76182-a28e-4933-b75a-9971d9bc1616
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42745 214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.42745214
Directory	/workspace/15.usbdev_smoke/latest

Test location	/workspace/coverage/default/15.usbdev_spurious_pids_ignored.3633632682
Short name	T1537
Test name
Test status
Simulation time	2771977134 ps
CPU time	80.35 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:15:49 PM PDT 24
Peak memory	223460 kb
Host	smart-43ffb9b6-823e-4d32-9e2f-5498b28cc4f4
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3633632682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3633632682
Directory	/workspace/15.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/15.usbdev_stall_priority_over_nak.2253150754
Short name	T972
Test name
Test status
Simulation time	167778870 ps
CPU time	0.98 seconds
Started	Aug 01 06:14:28 PM PDT 24
Finished	Aug 01 06:14:30 PM PDT 24
Peak memory	206952 kb
Host	smart-4ebfa5ec-5cb0-4239-946c-1bbf985b6bc8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22531 50754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2253150754
Directory	/workspace/15.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/15.usbdev_stall_trans.388787600
Short name	T1635
Test name
Test status
Simulation time	151224048 ps
CPU time	0.84 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206964 kb
Host	smart-625d8b7b-af1e-464d-a34e-3f7f3f195f3d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38878 7600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.388787600
Directory	/workspace/15.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/15.usbdev_stream_len_max.2240763980
Short name	T1065
Test name
Test status
Simulation time	1381473232 ps
CPU time	3.16 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:14:32 PM PDT 24
Peak memory	207084 kb
Host	smart-dd2e75ef-9e95-49b0-a12a-9c739a5bd7eb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22407 63980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2240763980
Directory	/workspace/15.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/15.usbdev_streaming_out.3378557866
Short name	T824
Test name
Test status
Simulation time	2734003672 ps
CPU time	76.29 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:15:48 PM PDT 24
Peak memory	223540 kb
Host	smart-292036b4-a99f-4b0c-8963-057b2e4e5fb6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33785 57866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3378557866
Directory	/workspace/15.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.182962662
Short name	T2381
Test name
Test status
Simulation time	4902541218 ps
CPU time	34.23 seconds
Started	Aug 01 06:14:19 PM PDT 24
Finished	Aug 01 06:14:54 PM PDT 24
Peak memory	207168 kb
Host	smart-cd150e68-7a6e-4b79-86a0-e0af5373d38f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182962662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_host _handshake.182962662
Directory	/workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/150.usbdev_endpoint_types.3971081019
Short name	T383
Test name
Test status
Simulation time	247436251 ps
CPU time	0.97 seconds
Started	Aug 01 06:20:25 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206924 kb
Host	smart-9ced0704-85af-4aee-ad40-73c382dc24f8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3971081019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.3971081019
Directory	/workspace/150.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/153.usbdev_endpoint_types.631144368
Short name	T419
Test name
Test status
Simulation time	556233602 ps
CPU time	1.44 seconds
Started	Aug 01 06:20:12 PM PDT 24
Finished	Aug 01 06:20:14 PM PDT 24
Peak memory	206920 kb
Host	smart-f07f7bd2-151a-4f13-b118-3f0c0c97e3bb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=631144368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.631144368
Directory	/workspace/153.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/154.usbdev_endpoint_types.1615132573
Short name	T421
Test name
Test status
Simulation time	704952320 ps
CPU time	1.62 seconds
Started	Aug 01 06:20:13 PM PDT 24
Finished	Aug 01 06:20:14 PM PDT 24
Peak memory	206936 kb
Host	smart-e8865f5e-d8b8-4f01-89f3-dda3f2e320ff
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1615132573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.1615132573
Directory	/workspace/154.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/155.usbdev_endpoint_types.93019934
Short name	T376
Test name
Test status
Simulation time	501481529 ps
CPU time	1.49 seconds
Started	Aug 01 06:20:19 PM PDT 24
Finished	Aug 01 06:20:21 PM PDT 24
Peak memory	206900 kb
Host	smart-d2e33d87-aaa2-476e-b8aa-452fb2c30436
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=93019934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.93019934
Directory	/workspace/155.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/156.usbdev_endpoint_types.2926137033
Short name	T2904
Test name
Test status
Simulation time	211459781 ps
CPU time	0.98 seconds
Started	Aug 01 06:20:32 PM PDT 24
Finished	Aug 01 06:20:33 PM PDT 24
Peak memory	206896 kb
Host	smart-5df1bb44-96a0-4189-9249-fb5a4d05a152
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2926137033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.2926137033
Directory	/workspace/156.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/157.usbdev_endpoint_types.1624761866
Short name	T364
Test name
Test status
Simulation time	649979872 ps
CPU time	1.85 seconds
Started	Aug 01 06:20:26 PM PDT 24
Finished	Aug 01 06:20:28 PM PDT 24
Peak memory	206940 kb
Host	smart-d35f6a87-219d-4eef-9a8f-63c9ef7eb4f0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1624761866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.1624761866
Directory	/workspace/157.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/159.usbdev_endpoint_types.360530308
Short name	T333
Test name
Test status
Simulation time	477972267 ps
CPU time	1.46 seconds
Started	Aug 01 06:20:16 PM PDT 24
Finished	Aug 01 06:20:18 PM PDT 24
Peak memory	206924 kb
Host	smart-a26b5101-8b82-4557-96c4-7e906c20c62b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=360530308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.360530308
Directory	/workspace/159.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/16.usbdev_av_buffer.2333344508
Short name	T2505
Test name
Test status
Simulation time	175203269 ps
CPU time	0.9 seconds
Started	Aug 01 06:14:28 PM PDT 24
Finished	Aug 01 06:14:29 PM PDT 24
Peak memory	206956 kb
Host	smart-5b776eea-d003-4566-ac91-c0f743f6d995
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23333 44508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.2333344508
Directory	/workspace/16.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/16.usbdev_bitstuff_err.332742996
Short name	T2233
Test name
Test status
Simulation time	143752617 ps
CPU time	0.83 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206840 kb
Host	smart-f030d873-d7cd-437d-a83f-b2c72448c251
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33274 2996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.332742996
Directory	/workspace/16.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/16.usbdev_data_toggle_clear.3314719984
Short name	T1640
Test name
Test status
Simulation time	302690787 ps
CPU time	1.14 seconds
Started	Aug 01 06:14:31 PM PDT 24
Finished	Aug 01 06:14:32 PM PDT 24
Peak memory	206916 kb
Host	smart-0ad7379b-5eca-4998-9073-2faf278cd3cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33147 19984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.3314719984
Directory	/workspace/16.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/16.usbdev_data_toggle_restore.2430686962
Short name	T2403
Test name
Test status
Simulation time	1612124497 ps
CPU time	3.99 seconds
Started	Aug 01 06:14:31 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	207152 kb
Host	smart-40398ac5-7bc3-4060-8260-c9ecc08c5bdb
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2430686962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.2430686962
Directory	/workspace/16.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/16.usbdev_device_address.3514754768
Short name	T2855
Test name
Test status
Simulation time	16005378632 ps
CPU time	25.86 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:14:58 PM PDT 24
Peak memory	207184 kb
Host	smart-8d05363b-2d9e-4139-b412-8b2fa313c82d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35147 54768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3514754768
Directory	/workspace/16.usbdev_device_address/latest

Test location	/workspace/coverage/default/16.usbdev_device_timeout.624836928
Short name	T656
Test name
Test status
Simulation time	5504980003 ps
CPU time	39.91 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:15:09 PM PDT 24
Peak memory	207156 kb
Host	smart-deb46e68-ae5e-4f0e-9fe6-029054e8d398
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624836928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.624836928
Directory	/workspace/16.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/16.usbdev_disable_endpoint.1093358723
Short name	T308
Test name
Test status
Simulation time	961315184 ps
CPU time	1.97 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206788 kb
Host	smart-1ec81922-7c69-4adf-b554-83aa49f1934b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10933 58723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1093358723
Directory	/workspace/16.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/16.usbdev_disconnected.886346679
Short name	T1553
Test name
Test status
Simulation time	143649944 ps
CPU time	0.81 seconds
Started	Aug 01 06:14:33 PM PDT 24
Finished	Aug 01 06:14:33 PM PDT 24
Peak memory	206896 kb
Host	smart-ad17c35a-194e-4e43-bb73-0fa84be7eb62
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88634 6679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.886346679
Directory	/workspace/16.usbdev_disconnected/latest

Test location	/workspace/coverage/default/16.usbdev_enable.1339320002
Short name	T1069
Test name
Test status
Simulation time	37889458 ps
CPU time	0.72 seconds
Started	Aug 01 06:14:28 PM PDT 24
Finished	Aug 01 06:14:29 PM PDT 24
Peak memory	206868 kb
Host	smart-f9da467d-9d95-45f9-96cb-1e8f570f9952
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13393 20002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1339320002
Directory	/workspace/16.usbdev_enable/latest

Test location	/workspace/coverage/default/16.usbdev_endpoint_access.3276818685
Short name	T1298
Test name
Test status
Simulation time	826079843 ps
CPU time	2.33 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:14:34 PM PDT 24
Peak memory	207140 kb
Host	smart-47184d92-cad9-496a-a411-5ba17737dfc0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32768 18685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3276818685
Directory	/workspace/16.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/16.usbdev_endpoint_types.4106014648
Short name	T379
Test name
Test status
Simulation time	353618299 ps
CPU time	1.16 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:14:33 PM PDT 24
Peak memory	206928 kb
Host	smart-a76eac37-7c09-491c-895e-33fe84c99e60
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4106014648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.4106014648
Directory	/workspace/16.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/16.usbdev_fifo_rst.4066265811
Short name	T1092
Test name
Test status
Simulation time	223279988 ps
CPU time	1.61 seconds
Started	Aug 01 06:14:28 PM PDT 24
Finished	Aug 01 06:14:30 PM PDT 24
Peak memory	207036 kb
Host	smart-26e8da63-cb2a-43d5-9cec-97021e52710a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40662 65811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4066265811
Directory	/workspace/16.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/16.usbdev_in_iso.3024698921
Short name	T1794
Test name
Test status
Simulation time	205199815 ps
CPU time	1.1 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:14:34 PM PDT 24
Peak memory	215284 kb
Host	smart-66e7b382-ee79-4a3f-8c72-a4cab217dbcb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3024698921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3024698921
Directory	/workspace/16.usbdev_in_iso/latest

Test location	/workspace/coverage/default/16.usbdev_in_stall.2139005415
Short name	T2671
Test name
Test status
Simulation time	143811288 ps
CPU time	0.81 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206888 kb
Host	smart-96636230-927a-4d03-976e-d6cda8cbc7c9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21390 05415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2139005415
Directory	/workspace/16.usbdev_in_stall/latest

Test location	/workspace/coverage/default/16.usbdev_in_trans.611087058
Short name	T2115
Test name
Test status
Simulation time	229472554 ps
CPU time	1.02 seconds
Started	Aug 01 06:14:28 PM PDT 24
Finished	Aug 01 06:14:29 PM PDT 24
Peak memory	206952 kb
Host	smart-112740c2-2cad-4263-8931-460a2d07d036
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61108 7058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.611087058
Directory	/workspace/16.usbdev_in_trans/latest

Test location	/workspace/coverage/default/16.usbdev_invalid_sync.1568813547
Short name	T2047
Test name
Test status
Simulation time	3198108688 ps
CPU time	94.3 seconds
Started	Aug 01 06:14:31 PM PDT 24
Finished	Aug 01 06:16:06 PM PDT 24
Peak memory	215352 kb
Host	smart-10352012-391a-4536-ae10-20e88d493548
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1568813547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1568813547
Directory	/workspace/16.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/16.usbdev_iso_retraction.3984959539
Short name	T1435
Test name
Test status
Simulation time	3881752355 ps
CPU time	24.01 seconds
Started	Aug 01 06:14:31 PM PDT 24
Finished	Aug 01 06:14:55 PM PDT 24
Peak memory	207120 kb
Host	smart-8472d8dc-cc38-4586-9b0f-ade2a67bbeb4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3984959539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3984959539
Directory	/workspace/16.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/16.usbdev_link_in_err.2225811342
Short name	T988
Test name
Test status
Simulation time	223284852 ps
CPU time	0.99 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:14:33 PM PDT 24
Peak memory	206892 kb
Host	smart-b9a24070-845a-4875-89b7-7ca888e265e1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22258 11342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2225811342
Directory	/workspace/16.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/16.usbdev_link_suspend.2829886394
Short name	T1185
Test name
Test status
Simulation time	3692124644 ps
CPU time	5.14 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:14:34 PM PDT 24
Peak memory	215420 kb
Host	smart-0b30f58d-b097-4d42-8c4f-716bfcfa9e7f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28298 86394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2829886394
Directory	/workspace/16.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1923406492
Short name	T1695
Test name
Test status
Simulation time	1974221450 ps
CPU time	58.71 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:15:28 PM PDT 24
Peak memory	215300 kb
Host	smart-bbcfa3eb-26b0-4538-ac52-a9c7fa93bb4c
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1923406492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1923406492
Directory	/workspace/16.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/16.usbdev_max_length_in_transaction.980766354
Short name	T1558
Test name
Test status
Simulation time	252394436 ps
CPU time	1.05 seconds
Started	Aug 01 06:14:29 PM PDT 24
Finished	Aug 01 06:14:30 PM PDT 24
Peak memory	206964 kb
Host	smart-e3a82a3b-a34f-483c-9651-30d91aed4629
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=980766354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.980766354
Directory	/workspace/16.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/16.usbdev_max_length_out_transaction.2515727356
Short name	T2497
Test name
Test status
Simulation time	184700351 ps
CPU time	0.94 seconds
Started	Aug 01 06:14:31 PM PDT 24
Finished	Aug 01 06:14:32 PM PDT 24
Peak memory	206936 kb
Host	smart-31fe3a45-9bb3-4a28-be16-e6d87f41ee67
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25157 27356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2515727356
Directory	/workspace/16.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.1484016423
Short name	T1549
Test name
Test status
Simulation time	1963320041 ps
CPU time	14.77 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:45 PM PDT 24
Peak memory	223404 kb
Host	smart-9744496e-5748-4303-95a6-59180960c33a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14840 16423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.1484016423
Directory	/workspace/16.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3669070054
Short name	T2394
Test name
Test status
Simulation time	2413416169 ps
CPU time	69.9 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:15:44 PM PDT 24
Peak memory	216704 kb
Host	smart-f4a6a054-ac45-4aef-88b0-318274797d56
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3669070054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3669070054
Directory	/workspace/16.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/16.usbdev_min_length_in_transaction.1465233434
Short name	T2110
Test name
Test status
Simulation time	157555193 ps
CPU time	0.84 seconds
Started	Aug 01 06:14:35 PM PDT 24
Finished	Aug 01 06:14:36 PM PDT 24
Peak memory	206964 kb
Host	smart-5d9d9bd6-9a2a-4348-af76-e69c685212ca
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1465233434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1465233434
Directory	/workspace/16.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/16.usbdev_min_length_out_transaction.999479441
Short name	T1834
Test name
Test status
Simulation time	142668456 ps
CPU time	0.8 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	206952 kb
Host	smart-bcc9325a-9c6a-46aa-b39b-7e51eb53c11d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99947 9441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.999479441
Directory	/workspace/16.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/16.usbdev_nak_trans.474547477
Short name	T1539
Test name
Test status
Simulation time	203661032 ps
CPU time	0.94 seconds
Started	Aug 01 06:14:33 PM PDT 24
Finished	Aug 01 06:14:34 PM PDT 24
Peak memory	206880 kb
Host	smart-0a151824-feb5-4d9c-8652-b378ce075056
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47454 7477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.474547477
Directory	/workspace/16.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/16.usbdev_out_iso.2084305776
Short name	T2714
Test name
Test status
Simulation time	176313897 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:31 PM PDT 24
Finished	Aug 01 06:14:32 PM PDT 24
Peak memory	206976 kb
Host	smart-ad5666aa-767c-47f4-a587-dffd524835b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20843 05776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2084305776
Directory	/workspace/16.usbdev_out_iso/latest

Test location	/workspace/coverage/default/16.usbdev_out_stall.3528254360
Short name	T1509
Test name
Test status
Simulation time	152700808 ps
CPU time	0.92 seconds
Started	Aug 01 06:14:33 PM PDT 24
Finished	Aug 01 06:14:34 PM PDT 24
Peak memory	206880 kb
Host	smart-d83a9013-3fe9-49dd-9888-2973b2532944
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35282 54360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3528254360
Directory	/workspace/16.usbdev_out_stall/latest

Test location	/workspace/coverage/default/16.usbdev_out_trans_nak.1139793634
Short name	T2118
Test name
Test status
Simulation time	162374482 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	206948 kb
Host	smart-6f262ebe-fa25-400e-be39-c3f0f57172d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11397 93634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1139793634
Directory	/workspace/16.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/16.usbdev_pending_in_trans.975867296
Short name	T1627
Test name
Test status
Simulation time	168953412 ps
CPU time	0.91 seconds
Started	Aug 01 06:14:33 PM PDT 24
Finished	Aug 01 06:14:34 PM PDT 24
Peak memory	206884 kb
Host	smart-f0a2ca07-db64-4dd9-be8b-8f5315be17a7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97586 7296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.975867296
Directory	/workspace/16.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/16.usbdev_phy_config_pinflip.3930137027
Short name	T660
Test name
Test status
Simulation time	209956707 ps
CPU time	0.98 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	206972 kb
Host	smart-32d9aafe-4f77-4142-b6df-2414c517af8c
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3930137027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3930137027
Directory	/workspace/16.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1918789001
Short name	T1563
Test name
Test status
Simulation time	150260935 ps
CPU time	0.82 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	206856 kb
Host	smart-17b8c29d-1430-44c4-8b77-584621dd92bf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19187 89001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1918789001
Directory	/workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/16.usbdev_phy_pins_sense.3162960705
Short name	T2535
Test name
Test status
Simulation time	63739427 ps
CPU time	0.7 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	206912 kb
Host	smart-f5634eb6-8f34-4925-83d9-b2006aef63ed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31629 60705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.3162960705
Directory	/workspace/16.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/16.usbdev_pkt_buffer.1803450395
Short name	T270
Test name
Test status
Simulation time	14510648862 ps
CPU time	35.65 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:15:08 PM PDT 24
Peak memory	215364 kb
Host	smart-1f73c631-7f1a-4770-a0d6-aba8788af792
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18034 50395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1803450395
Directory	/workspace/16.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/16.usbdev_pkt_received.2466651870
Short name	T1730
Test name
Test status
Simulation time	175702431 ps
CPU time	0.9 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	206428 kb
Host	smart-621657fe-5035-46d8-9a34-56ce9bde8718
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24666 51870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.2466651870
Directory	/workspace/16.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/16.usbdev_pkt_sent.470201631
Short name	T2869
Test name
Test status
Simulation time	246305002 ps
CPU time	1.02 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	206936 kb
Host	smart-2aafb362-3bda-46d6-85e4-9b06acd4ad7c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47020 1631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.470201631
Directory	/workspace/16.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/16.usbdev_random_length_in_transaction.1742083048
Short name	T1243
Test name
Test status
Simulation time	246741077 ps
CPU time	0.98 seconds
Started	Aug 01 06:14:35 PM PDT 24
Finished	Aug 01 06:14:36 PM PDT 24
Peak memory	206924 kb
Host	smart-882a7af4-df2c-466a-9211-448b653d793a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17420 83048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1742083048
Directory	/workspace/16.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/16.usbdev_random_length_out_transaction.1459965060
Short name	T1957
Test name
Test status
Simulation time	266046218 ps
CPU time	1.05 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	206964 kb
Host	smart-ac42bdf9-4fd2-4f0c-a308-49ca16e38abc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14599 65060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1459965060
Directory	/workspace/16.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/16.usbdev_rx_crc_err.3455688528
Short name	T1400
Test name
Test status
Simulation time	164351494 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:14:33 PM PDT 24
Peak memory	206968 kb
Host	smart-3de6b013-0652-427b-a2a2-f5e8e017ce7d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34556 88528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3455688528
Directory	/workspace/16.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/16.usbdev_rx_full.1588054130
Short name	T38
Test name
Test status
Simulation time	282135541 ps
CPU time	1.05 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	206960 kb
Host	smart-e2d8294a-eee7-419c-9464-b9ac27b36f47
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15880 54130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.1588054130
Directory	/workspace/16.usbdev_rx_full/latest

Test location	/workspace/coverage/default/16.usbdev_setup_stage.1072956353
Short name	T2480
Test name
Test status
Simulation time	197655521 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:35 PM PDT 24
Finished	Aug 01 06:14:36 PM PDT 24
Peak memory	206888 kb
Host	smart-9f76284d-6b7b-40f0-b10a-3586c59a202b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10729 56353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1072956353
Directory	/workspace/16.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/16.usbdev_setup_trans_ignored.3869932207
Short name	T522
Test name
Test status
Simulation time	214375836 ps
CPU time	0.88 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:35 PM PDT 24
Peak memory	206964 kb
Host	smart-a6651407-4724-475f-879a-3f4bfb388ae7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38699 32207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.3869932207
Directory	/workspace/16.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/16.usbdev_smoke.3493890920
Short name	T676
Test name
Test status
Simulation time	207681515 ps
CPU time	1.03 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:14:33 PM PDT 24
Peak memory	206924 kb
Host	smart-a4246903-97c6-419b-949c-54f3ee324202
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34938 90920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3493890920
Directory	/workspace/16.usbdev_smoke/latest

Test location	/workspace/coverage/default/16.usbdev_spurious_pids_ignored.2394940983
Short name	T1321
Test name
Test status
Simulation time	2433381192 ps
CPU time	22.66 seconds
Started	Aug 01 06:14:34 PM PDT 24
Finished	Aug 01 06:14:57 PM PDT 24
Peak memory	223516 kb
Host	smart-8b62fef9-9553-45d5-a6ea-95513a721008
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2394940983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2394940983
Directory	/workspace/16.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/16.usbdev_stall_trans.3407537769
Short name	T2370
Test name
Test status
Simulation time	193785287 ps
CPU time	0.92 seconds
Started	Aug 01 06:14:35 PM PDT 24
Finished	Aug 01 06:14:36 PM PDT 24
Peak memory	206956 kb
Host	smart-8e984830-1ce2-4739-a652-ccbdf91d6f08
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34075 37769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3407537769
Directory	/workspace/16.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/16.usbdev_stream_len_max.1754241365
Short name	T2143
Test name
Test status
Simulation time	325891869 ps
CPU time	1.28 seconds
Started	Aug 01 06:14:31 PM PDT 24
Finished	Aug 01 06:14:32 PM PDT 24
Peak memory	206904 kb
Host	smart-b3f2789d-ea2b-4612-9500-4e5c84ce9ff4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17542 41365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.1754241365
Directory	/workspace/16.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/16.usbdev_streaming_out.798888455
Short name	T2885
Test name
Test status
Simulation time	2428886032 ps
CPU time	71.24 seconds
Started	Aug 01 06:14:30 PM PDT 24
Finished	Aug 01 06:15:42 PM PDT 24
Peak memory	216700 kb
Host	smart-9a3c5755-5e48-459d-ae5d-2154f6cab94e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79888 8455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.798888455
Directory	/workspace/16.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.4076226777
Short name	T641
Test name
Test status
Simulation time	1298545718 ps
CPU time	30.66 seconds
Started	Aug 01 06:14:32 PM PDT 24
Finished	Aug 01 06:15:03 PM PDT 24
Peak memory	207140 kb
Host	smart-43676945-5242-4c4e-bd2f-d430b7042560
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076226777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_hos t_handshake.4076226777
Directory	/workspace/16.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/160.usbdev_endpoint_types.2295382459
Short name	T1729
Test name
Test status
Simulation time	330247221 ps
CPU time	1.06 seconds
Started	Aug 01 06:20:08 PM PDT 24
Finished	Aug 01 06:20:09 PM PDT 24
Peak memory	206916 kb
Host	smart-66705fe7-3f8f-4ee1-b5e4-fe45239192b3
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2295382459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.2295382459
Directory	/workspace/160.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/161.usbdev_endpoint_types.3879967701
Short name	T1884
Test name
Test status
Simulation time	302208625 ps
CPU time	1.12 seconds
Started	Aug 01 06:20:21 PM PDT 24
Finished	Aug 01 06:20:23 PM PDT 24
Peak memory	206916 kb
Host	smart-5b00a30b-bcca-4bc5-ad40-7ce5ccefaebc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3879967701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.3879967701
Directory	/workspace/161.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/164.usbdev_endpoint_types.4177166541
Short name	T413
Test name
Test status
Simulation time	561842498 ps
CPU time	1.51 seconds
Started	Aug 01 06:20:15 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	206896 kb
Host	smart-090784ca-2fba-4320-8568-4af507cd5035
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4177166541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.4177166541
Directory	/workspace/164.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/165.usbdev_endpoint_types.2380506833
Short name	T319
Test name
Test status
Simulation time	364831611 ps
CPU time	1.28 seconds
Started	Aug 01 06:20:28 PM PDT 24
Finished	Aug 01 06:20:29 PM PDT 24
Peak memory	206920 kb
Host	smart-ec402e26-ebf4-48a7-8eb6-ebff64cdd929
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2380506833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.2380506833
Directory	/workspace/165.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/168.usbdev_endpoint_types.1039093816
Short name	T2548
Test name
Test status
Simulation time	604970315 ps
CPU time	1.56 seconds
Started	Aug 01 06:20:24 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206892 kb
Host	smart-ac9d8a86-79bc-4d91-bea1-c8a3c5b78499
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1039093816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.1039093816
Directory	/workspace/168.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/17.usbdev_alert_test.2206148039
Short name	T2580
Test name
Test status
Simulation time	33080117 ps
CPU time	0.68 seconds
Started	Aug 01 06:14:47 PM PDT 24
Finished	Aug 01 06:14:48 PM PDT 24
Peak memory	206984 kb
Host	smart-e30c0034-70ac-4ee0-bf29-b8690e81a772
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2206148039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.2206148039
Directory	/workspace/17.usbdev_alert_test/latest

Test location	/workspace/coverage/default/17.usbdev_av_buffer.3149078205
Short name	T2156
Test name
Test status
Simulation time	165495431 ps
CPU time	0.88 seconds
Started	Aug 01 06:14:46 PM PDT 24
Finished	Aug 01 06:14:47 PM PDT 24
Peak memory	206968 kb
Host	smart-6d322dda-144c-4d39-a6a7-407d5600bb29
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31490 78205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3149078205
Directory	/workspace/17.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/17.usbdev_bitstuff_err.3533754193
Short name	T2091
Test name
Test status
Simulation time	152596692 ps
CPU time	0.82 seconds
Started	Aug 01 06:14:45 PM PDT 24
Finished	Aug 01 06:14:45 PM PDT 24
Peak memory	206852 kb
Host	smart-13bc84eb-35f5-40b1-ae25-6dc30a546fdd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35337 54193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.3533754193
Directory	/workspace/17.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/17.usbdev_data_toggle_clear.2212498464
Short name	T1607
Test name
Test status
Simulation time	229333455 ps
CPU time	1.02 seconds
Started	Aug 01 06:14:47 PM PDT 24
Finished	Aug 01 06:14:48 PM PDT 24
Peak memory	206928 kb
Host	smart-348f19b9-032c-4597-8e70-d800b4bb7ee8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22124 98464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2212498464
Directory	/workspace/17.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/17.usbdev_data_toggle_restore.205474821
Short name	T2678
Test name
Test status
Simulation time	841988344 ps
CPU time	2.46 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	207116 kb
Host	smart-39555dd2-6499-4b75-ad79-4e5c86860490
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=205474821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.205474821
Directory	/workspace/17.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/17.usbdev_device_address.3358922246
Short name	T1708
Test name
Test status
Simulation time	40860107975 ps
CPU time	61.82 seconds
Started	Aug 01 06:14:45 PM PDT 24
Finished	Aug 01 06:15:46 PM PDT 24
Peak memory	207152 kb
Host	smart-9e223380-7e3a-4dba-9824-adde33f76dee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33589 22246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3358922246
Directory	/workspace/17.usbdev_device_address/latest

Test location	/workspace/coverage/default/17.usbdev_device_timeout.1227435585
Short name	T2751
Test name
Test status
Simulation time	479602962 ps
CPU time	7.75 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:14:49 PM PDT 24
Peak memory	207040 kb
Host	smart-a4f71b48-9ec2-4f9a-a460-7a3fc3568d47
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227435585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.1227435585
Directory	/workspace/17.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/17.usbdev_disable_endpoint.563975284
Short name	T1576
Test name
Test status
Simulation time	954438115 ps
CPU time	2.31 seconds
Started	Aug 01 06:14:43 PM PDT 24
Finished	Aug 01 06:14:45 PM PDT 24
Peak memory	206896 kb
Host	smart-3a1c6bc9-1bbb-45c4-92b7-ad523cf7b031
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56397 5284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.563975284
Directory	/workspace/17.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/17.usbdev_disconnected.3251592053
Short name	T1465
Test name
Test status
Simulation time	183605969 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:47 PM PDT 24
Finished	Aug 01 06:14:48 PM PDT 24
Peak memory	206896 kb
Host	smart-3e669019-4c91-41e8-b60d-10123fbe3caf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32515 92053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3251592053
Directory	/workspace/17.usbdev_disconnected/latest

Test location	/workspace/coverage/default/17.usbdev_enable.2314299035
Short name	T2602
Test name
Test status
Simulation time	27934134 ps
CPU time	0.66 seconds
Started	Aug 01 06:14:42 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	206924 kb
Host	smart-8ccebc7b-015d-4934-bdac-e4bbe3302cca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23142 99035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2314299035
Directory	/workspace/17.usbdev_enable/latest

Test location	/workspace/coverage/default/17.usbdev_endpoint_access.552522069
Short name	T1676
Test name
Test status
Simulation time	882451159 ps
CPU time	2.29 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	207088 kb
Host	smart-5d5d0434-cef4-419e-b47e-7ebed1899ad5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55252 2069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.552522069
Directory	/workspace/17.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/17.usbdev_endpoint_types.2954316708
Short name	T1803
Test name
Test status
Simulation time	150099919 ps
CPU time	0.89 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:14:42 PM PDT 24
Peak memory	206976 kb
Host	smart-543987c9-fcb3-4b99-92f0-e2eba13e8825
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2954316708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.2954316708
Directory	/workspace/17.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/17.usbdev_fifo_rst.966179997
Short name	T1372
Test name
Test status
Simulation time	345526829 ps
CPU time	2.41 seconds
Started	Aug 01 06:14:40 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	207152 kb
Host	smart-cee6d873-2dcc-411c-9be6-77be11929226
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96617 9997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.966179997
Directory	/workspace/17.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/17.usbdev_in_iso.1027270056
Short name	T1108
Test name
Test status
Simulation time	248794307 ps
CPU time	1.13 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:14:42 PM PDT 24
Peak memory	207104 kb
Host	smart-b0e9012f-f63a-43c5-955b-7b8990bb651b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1027270056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1027270056
Directory	/workspace/17.usbdev_in_iso/latest

Test location	/workspace/coverage/default/17.usbdev_in_stall.2413751597
Short name	T977
Test name
Test status
Simulation time	148815819 ps
CPU time	0.83 seconds
Started	Aug 01 06:14:43 PM PDT 24
Finished	Aug 01 06:14:44 PM PDT 24
Peak memory	206904 kb
Host	smart-5d12836b-f079-422f-8e7d-f2f7ec01bdfb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24137 51597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.2413751597
Directory	/workspace/17.usbdev_in_stall/latest

Test location	/workspace/coverage/default/17.usbdev_in_trans.1732253944
Short name	T1614
Test name
Test status
Simulation time	189347130 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:43 PM PDT 24
Finished	Aug 01 06:14:44 PM PDT 24
Peak memory	206964 kb
Host	smart-0d24cb3d-1f0f-46d6-818d-e047b397b8f9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17322 53944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1732253944
Directory	/workspace/17.usbdev_in_trans/latest

Test location	/workspace/coverage/default/17.usbdev_invalid_sync.158084610
Short name	T2852
Test name
Test status
Simulation time	4165777246 ps
CPU time	33.43 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	217780 kb
Host	smart-471a6f72-8fa8-4621-af70-3c5918096cd4
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=158084610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.158084610
Directory	/workspace/17.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/17.usbdev_iso_retraction.208664713
Short name	T1839
Test name
Test status
Simulation time	4804977931 ps
CPU time	30.16 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:15:12 PM PDT 24
Peak memory	207052 kb
Host	smart-3fbde5d2-48c9-44ac-b7a8-b9d16242014b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=208664713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.208664713
Directory	/workspace/17.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/17.usbdev_link_in_err.3683892751
Short name	T1043
Test name
Test status
Simulation time	270915133 ps
CPU time	1 seconds
Started	Aug 01 06:14:49 PM PDT 24
Finished	Aug 01 06:14:50 PM PDT 24
Peak memory	206960 kb
Host	smart-115eb467-4b6c-4283-b5c2-7fb867d17124
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838 92751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3683892751
Directory	/workspace/17.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/17.usbdev_link_suspend.1964357417
Short name	T1212
Test name
Test status
Simulation time	9398167872 ps
CPU time	11.14 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:14:52 PM PDT 24
Peak memory	207152 kb
Host	smart-8cab560a-d11f-4dfb-8cee-cb1970dde7e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19643 57417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1964357417
Directory	/workspace/17.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/17.usbdev_low_speed_traffic.408128986
Short name	T2563
Test name
Test status
Simulation time	3321665350 ps
CPU time	32.01 seconds
Started	Aug 01 06:14:46 PM PDT 24
Finished	Aug 01 06:15:18 PM PDT 24
Peak memory	223572 kb
Host	smart-67c95888-0275-4623-aeca-8cbe875c4eec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40812 8986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.408128986
Directory	/workspace/17.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2051528336
Short name	T847
Test name
Test status
Simulation time	2164822993 ps
CPU time	64.5 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:15:46 PM PDT 24
Peak memory	216760 kb
Host	smart-e041e9ba-637e-4a29-877a-c052c8a667b3
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2051528336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2051528336
Directory	/workspace/17.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/17.usbdev_max_length_in_transaction.1532421363
Short name	T2863
Test name
Test status
Simulation time	276002013 ps
CPU time	1.02 seconds
Started	Aug 01 06:14:49 PM PDT 24
Finished	Aug 01 06:14:50 PM PDT 24
Peak memory	206956 kb
Host	smart-62ad091f-78f8-40c2-b0c4-f299dc1eeddb
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1532421363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1532421363
Directory	/workspace/17.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/17.usbdev_max_length_out_transaction.3246325230
Short name	T501
Test name
Test status
Simulation time	188928079 ps
CPU time	0.97 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:14:42 PM PDT 24
Peak memory	206948 kb
Host	smart-b5b3f374-d1f8-4f34-8712-24600e03ce9b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32463 25230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3246325230
Directory	/workspace/17.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.3778900915
Short name	T1137
Test name
Test status
Simulation time	1921516744 ps
CPU time	52.08 seconds
Started	Aug 01 06:14:47 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	215312 kb
Host	smart-e46580b8-77a5-45b5-a1b2-a3e0644fce0e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37789 00915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.3778900915
Directory	/workspace/17.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2995726786
Short name	T1846
Test name
Test status
Simulation time	1600768792 ps
CPU time	47.46 seconds
Started	Aug 01 06:14:46 PM PDT 24
Finished	Aug 01 06:15:34 PM PDT 24
Peak memory	215284 kb
Host	smart-84751194-2a0c-4ffa-b2d5-a5599de47b4c
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2995726786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2995726786
Directory	/workspace/17.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/17.usbdev_min_length_in_transaction.3509217966
Short name	T814
Test name
Test status
Simulation time	160709253 ps
CPU time	0.83 seconds
Started	Aug 01 06:14:47 PM PDT 24
Finished	Aug 01 06:14:48 PM PDT 24
Peak memory	206956 kb
Host	smart-6ba06185-3b31-4213-a6f2-effd76c9f5be
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3509217966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3509217966
Directory	/workspace/17.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/17.usbdev_min_length_out_transaction.2277239361
Short name	T1164
Test name
Test status
Simulation time	193388109 ps
CPU time	0.9 seconds
Started	Aug 01 06:14:49 PM PDT 24
Finished	Aug 01 06:14:50 PM PDT 24
Peak memory	207176 kb
Host	smart-51572cb9-5817-41e6-8f5c-3b7c7f63f32b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22772 39361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2277239361
Directory	/workspace/17.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/17.usbdev_nak_trans.1612828711
Short name	T180
Test name
Test status
Simulation time	256325135 ps
CPU time	1.01 seconds
Started	Aug 01 06:14:42 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	206956 kb
Host	smart-14834226-46b7-4c35-96a8-e52469981acd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16128 28711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1612828711
Directory	/workspace/17.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/17.usbdev_out_iso.1960959235
Short name	T583
Test name
Test status
Simulation time	196376557 ps
CPU time	0.91 seconds
Started	Aug 01 06:14:43 PM PDT 24
Finished	Aug 01 06:14:44 PM PDT 24
Peak memory	206924 kb
Host	smart-e301a0c0-c49b-45c3-9a5d-362bdf1c267f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19609 59235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.1960959235
Directory	/workspace/17.usbdev_out_iso/latest

Test location	/workspace/coverage/default/17.usbdev_out_stall.1055490253
Short name	T2552
Test name
Test status
Simulation time	184090158 ps
CPU time	0.96 seconds
Started	Aug 01 06:14:44 PM PDT 24
Finished	Aug 01 06:14:45 PM PDT 24
Peak memory	206944 kb
Host	smart-83715f22-e85c-4c10-9fe2-b7241b0c2179
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10554 90253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.1055490253
Directory	/workspace/17.usbdev_out_stall/latest

Test location	/workspace/coverage/default/17.usbdev_out_trans_nak.2360414480
Short name	T1242
Test name
Test status
Simulation time	182688959 ps
CPU time	0.86 seconds
Started	Aug 01 06:14:41 PM PDT 24
Finished	Aug 01 06:14:42 PM PDT 24
Peak memory	206900 kb
Host	smart-704b7881-9530-4a06-b230-450d1ef1ae7c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23604 14480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2360414480
Directory	/workspace/17.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/17.usbdev_pending_in_trans.2059938023
Short name	T224
Test name
Test status
Simulation time	156991990 ps
CPU time	0.83 seconds
Started	Aug 01 06:14:42 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	206956 kb
Host	smart-97bfe613-36a1-4a03-b72a-2558db8d1825
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20599 38023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2059938023
Directory	/workspace/17.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/17.usbdev_phy_config_pinflip.1971137380
Short name	T2463
Test name
Test status
Simulation time	223498338 ps
CPU time	1.04 seconds
Started	Aug 01 06:14:42 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	206964 kb
Host	smart-c77886cb-3b05-450b-85ab-ebb4f714fcd7
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1971137380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1971137380
Directory	/workspace/17.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.18492956
Short name	T1061
Test name
Test status
Simulation time	147922475 ps
CPU time	0.85 seconds
Started	Aug 01 06:14:49 PM PDT 24
Finished	Aug 01 06:14:50 PM PDT 24
Peak memory	206884 kb
Host	smart-e806bbc3-5f08-4906-99dc-6153686dd493
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18492 956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.18492956
Directory	/workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/17.usbdev_phy_pins_sense.3576479465
Short name	T1458
Test name
Test status
Simulation time	39558044 ps
CPU time	0.7 seconds
Started	Aug 01 06:14:46 PM PDT 24
Finished	Aug 01 06:14:47 PM PDT 24
Peak memory	206888 kb
Host	smart-738feba9-8c72-4afb-bf73-07ab0aeeea36
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35764 79465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3576479465
Directory	/workspace/17.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/17.usbdev_pkt_buffer.1198896428
Short name	T2582
Test name
Test status
Simulation time	21498749096 ps
CPU time	52.89 seconds
Started	Aug 01 06:14:38 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	215372 kb
Host	smart-12fed4d9-c4fd-4c41-b2e9-86f2b8ddedc8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11988 96428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.1198896428
Directory	/workspace/17.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/17.usbdev_pkt_received.945439644
Short name	T1543
Test name
Test status
Simulation time	204268967 ps
CPU time	0.91 seconds
Started	Aug 01 06:14:47 PM PDT 24
Finished	Aug 01 06:14:48 PM PDT 24
Peak memory	206940 kb
Host	smart-c3d45a04-47ef-4b7c-8f3b-e0a60cdd80f2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94543 9644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.945439644
Directory	/workspace/17.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/17.usbdev_pkt_sent.3046565170
Short name	T1817
Test name
Test status
Simulation time	159889068 ps
CPU time	0.88 seconds
Started	Aug 01 06:14:46 PM PDT 24
Finished	Aug 01 06:14:47 PM PDT 24
Peak memory	206968 kb
Host	smart-ce44f889-19bc-40c2-a034-b6a1ee4bdd79
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30465 65170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3046565170
Directory	/workspace/17.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/17.usbdev_random_length_in_transaction.776720064
Short name	T2264
Test name
Test status
Simulation time	182593884 ps
CPU time	0.92 seconds
Started	Aug 01 06:14:43 PM PDT 24
Finished	Aug 01 06:14:44 PM PDT 24
Peak memory	206956 kb
Host	smart-93aba9d1-35cf-4caa-ac48-67d2248fee33
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77672 0064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.776720064
Directory	/workspace/17.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/17.usbdev_random_length_out_transaction.1739852565
Short name	T1906
Test name
Test status
Simulation time	154773160 ps
CPU time	0.85 seconds
Started	Aug 01 06:14:48 PM PDT 24
Finished	Aug 01 06:14:49 PM PDT 24
Peak memory	206956 kb
Host	smart-3864e3ab-1f0d-4888-8f57-c4cd852cfc96
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17398 52565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1739852565
Directory	/workspace/17.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/17.usbdev_rx_crc_err.3031012130
Short name	T1202
Test name
Test status
Simulation time	187877724 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:49 PM PDT 24
Finished	Aug 01 06:14:50 PM PDT 24
Peak memory	206964 kb
Host	smart-c58461b6-1000-49b6-bc0e-8e5dac6ffa18
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30310 12130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3031012130
Directory	/workspace/17.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/17.usbdev_rx_full.2717900789
Short name	T786
Test name
Test status
Simulation time	262534247 ps
CPU time	1.14 seconds
Started	Aug 01 06:14:42 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	206944 kb
Host	smart-770c3be8-9d5a-4e77-93e4-09296998bb9b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27179 00789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.2717900789
Directory	/workspace/17.usbdev_rx_full/latest

Test location	/workspace/coverage/default/17.usbdev_setup_stage.1918511039
Short name	T840
Test name
Test status
Simulation time	164939111 ps
CPU time	0.95 seconds
Started	Aug 01 06:14:47 PM PDT 24
Finished	Aug 01 06:14:48 PM PDT 24
Peak memory	206912 kb
Host	smart-530ce6de-468d-4d8c-a95c-36069ce8063f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19185 11039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1918511039
Directory	/workspace/17.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/17.usbdev_setup_trans_ignored.2100086386
Short name	T2246
Test name
Test status
Simulation time	157093651 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:42 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	206920 kb
Host	smart-6425d206-9f4e-4f56-8bf5-a5b69804e45e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21000 86386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2100086386
Directory	/workspace/17.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/17.usbdev_smoke.1708675427
Short name	T2332
Test name
Test status
Simulation time	246458496 ps
CPU time	1.06 seconds
Started	Aug 01 06:14:42 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	206956 kb
Host	smart-460ad05f-57c6-46d8-8934-c17d9270103f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17086 75427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1708675427
Directory	/workspace/17.usbdev_smoke/latest

Test location	/workspace/coverage/default/17.usbdev_spurious_pids_ignored.1191748328
Short name	T1263
Test name
Test status
Simulation time	2446034185 ps
CPU time	25.74 seconds
Started	Aug 01 06:14:46 PM PDT 24
Finished	Aug 01 06:15:11 PM PDT 24
Peak memory	223472 kb
Host	smart-1b3d383f-cb8d-404f-a2b0-aa5485e2c2d9
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1191748328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.1191748328
Directory	/workspace/17.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/17.usbdev_stall_priority_over_nak.1436728382
Short name	T439
Test name
Test status
Simulation time	184003436 ps
CPU time	0.88 seconds
Started	Aug 01 06:14:47 PM PDT 24
Finished	Aug 01 06:14:48 PM PDT 24
Peak memory	206948 kb
Host	smart-bf879c68-2587-4f8f-8b65-ec06dfd1abc1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14367 28382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1436728382
Directory	/workspace/17.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/17.usbdev_stall_trans.3431984236
Short name	T682
Test name
Test status
Simulation time	184239867 ps
CPU time	0.9 seconds
Started	Aug 01 06:14:42 PM PDT 24
Finished	Aug 01 06:14:43 PM PDT 24
Peak memory	206876 kb
Host	smart-5ecbb73b-bae8-489b-99c2-895b3deaefdd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34319 84236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3431984236
Directory	/workspace/17.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/17.usbdev_stream_len_max.4170189117
Short name	T533
Test name
Test status
Simulation time	663591838 ps
CPU time	1.96 seconds
Started	Aug 01 06:14:49 PM PDT 24
Finished	Aug 01 06:14:51 PM PDT 24
Peak memory	206900 kb
Host	smart-338085c0-cb2e-4fc9-937d-9cfa08cc9a22
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41701 89117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.4170189117
Directory	/workspace/17.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/17.usbdev_streaming_out.345751755
Short name	T809
Test name
Test status
Simulation time	3095721027 ps
CPU time	86.13 seconds
Started	Aug 01 06:14:49 PM PDT 24
Finished	Aug 01 06:16:15 PM PDT 24
Peak memory	215324 kb
Host	smart-edd3ae98-2ebf-4d93-a356-35c93b37fbd1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34575 1755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.345751755
Directory	/workspace/17.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.3345622955
Short name	T578
Test name
Test status
Simulation time	1384854065 ps
CPU time	9.49 seconds
Started	Aug 01 06:14:43 PM PDT 24
Finished	Aug 01 06:14:53 PM PDT 24
Peak memory	207132 kb
Host	smart-141b9755-0f15-4026-b543-d78c51d7b2df
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345622955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos t_handshake.3345622955
Directory	/workspace/17.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/170.usbdev_endpoint_types.348398721
Short name	T1245
Test name
Test status
Simulation time	312865904 ps
CPU time	1.08 seconds
Started	Aug 01 06:20:20 PM PDT 24
Finished	Aug 01 06:20:21 PM PDT 24
Peak memory	206872 kb
Host	smart-082d2eed-ecf4-4c57-ba2f-8daf7be7b44a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=348398721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.348398721
Directory	/workspace/170.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/172.usbdev_endpoint_types.1082143350
Short name	T372
Test name
Test status
Simulation time	582144029 ps
CPU time	1.47 seconds
Started	Aug 01 06:20:16 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	206916 kb
Host	smart-6cd752a6-fbdd-4baa-ae3e-e7ccf43f3ec6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1082143350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.1082143350
Directory	/workspace/172.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/173.usbdev_endpoint_types.1857831445
Short name	T377
Test name
Test status
Simulation time	879063513 ps
CPU time	2.12 seconds
Started	Aug 01 06:20:28 PM PDT 24
Finished	Aug 01 06:20:30 PM PDT 24
Peak memory	206932 kb
Host	smart-b0061fb9-162e-49aa-abf8-22c83fffc115
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1857831445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.1857831445
Directory	/workspace/173.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/175.usbdev_endpoint_types.1151034671
Short name	T347
Test name
Test status
Simulation time	972761898 ps
CPU time	1.96 seconds
Started	Aug 01 06:20:27 PM PDT 24
Finished	Aug 01 06:20:29 PM PDT 24
Peak memory	206976 kb
Host	smart-837dbd5d-629c-4625-9a66-376c9a29e6a2
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1151034671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.1151034671
Directory	/workspace/175.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/176.usbdev_endpoint_types.797895261
Short name	T363
Test name
Test status
Simulation time	798540713 ps
CPU time	1.8 seconds
Started	Aug 01 06:20:32 PM PDT 24
Finished	Aug 01 06:20:34 PM PDT 24
Peak memory	206920 kb
Host	smart-d5d0219d-df62-42dd-a1ad-8c02d2457186
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=797895261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.797895261
Directory	/workspace/176.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/177.usbdev_endpoint_types.4198114395
Short name	T387
Test name
Test status
Simulation time	308108360 ps
CPU time	1 seconds
Started	Aug 01 06:20:25 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206832 kb
Host	smart-f17deded-7d75-44a0-aa04-934d416b0ba7
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4198114395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.4198114395
Directory	/workspace/177.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/179.usbdev_endpoint_types.162882667
Short name	T2153
Test name
Test status
Simulation time	187823639 ps
CPU time	0.98 seconds
Started	Aug 01 06:20:25 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206880 kb
Host	smart-29917385-cc19-44e1-9df5-5b0afe76b4e6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=162882667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.162882667
Directory	/workspace/179.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/18.usbdev_alert_test.1540290562
Short name	T1041
Test name
Test status
Simulation time	80152345 ps
CPU time	0.79 seconds
Started	Aug 01 06:15:02 PM PDT 24
Finished	Aug 01 06:15:03 PM PDT 24
Peak memory	206952 kb
Host	smart-bc483a78-0632-41ee-aec7-fba1c8d01af2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1540290562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.1540290562
Directory	/workspace/18.usbdev_alert_test/latest

Test location	/workspace/coverage/default/18.usbdev_av_buffer.2243835804
Short name	T2815
Test name
Test status
Simulation time	153945523 ps
CPU time	0.86 seconds
Started	Aug 01 06:14:46 PM PDT 24
Finished	Aug 01 06:14:47 PM PDT 24
Peak memory	206944 kb
Host	smart-f7cde99d-fa19-41a4-a9f6-e1e0ee2475ab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22438 35804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2243835804
Directory	/workspace/18.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/18.usbdev_bitstuff_err.1884055103
Short name	T2742
Test name
Test status
Simulation time	152063257 ps
CPU time	0.84 seconds
Started	Aug 01 06:14:46 PM PDT 24
Finished	Aug 01 06:14:47 PM PDT 24
Peak memory	206916 kb
Host	smart-ec32ddf9-1f82-4f57-905f-1f348b4420c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18840 55103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1884055103
Directory	/workspace/18.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/18.usbdev_data_toggle_clear.1091637304
Short name	T1275
Test name
Test status
Simulation time	537906259 ps
CPU time	1.77 seconds
Started	Aug 01 06:14:49 PM PDT 24
Finished	Aug 01 06:14:51 PM PDT 24
Peak memory	206976 kb
Host	smart-84b2f8c9-2798-4c1b-a8d7-4dc6cb86deb1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10916 37304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.1091637304
Directory	/workspace/18.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/18.usbdev_data_toggle_restore.1870239581
Short name	T2666
Test name
Test status
Simulation time	437458755 ps
CPU time	1.48 seconds
Started	Aug 01 06:14:46 PM PDT 24
Finished	Aug 01 06:14:48 PM PDT 24
Peak memory	206956 kb
Host	smart-41d02328-7954-408e-9f8e-f35a2f001205
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1870239581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1870239581
Directory	/workspace/18.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/18.usbdev_device_address.1352979838
Short name	T1342
Test name
Test status
Simulation time	51063667755 ps
CPU time	82.98 seconds
Started	Aug 01 06:14:44 PM PDT 24
Finished	Aug 01 06:16:07 PM PDT 24
Peak memory	207116 kb
Host	smart-86283383-f82f-4985-b2d5-0512558a890d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13529 79838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1352979838
Directory	/workspace/18.usbdev_device_address/latest

Test location	/workspace/coverage/default/18.usbdev_device_timeout.2443309453
Short name	T2858
Test name
Test status
Simulation time	836416609 ps
CPU time	5.39 seconds
Started	Aug 01 06:14:43 PM PDT 24
Finished	Aug 01 06:14:48 PM PDT 24
Peak memory	207400 kb
Host	smart-2017e787-d5d6-4c97-ac3e-62c4db293ce7
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443309453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.2443309453
Directory	/workspace/18.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/18.usbdev_disable_endpoint.4192447329
Short name	T737
Test name
Test status
Simulation time	639341087 ps
CPU time	1.57 seconds
Started	Aug 01 06:14:56 PM PDT 24
Finished	Aug 01 06:14:58 PM PDT 24
Peak memory	206920 kb
Host	smart-769421ab-03e8-44f4-a30b-2b4977b888af
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41924 47329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.4192447329
Directory	/workspace/18.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/18.usbdev_disconnected.723423688
Short name	T2625
Test name
Test status
Simulation time	142318677 ps
CPU time	0.82 seconds
Started	Aug 01 06:14:52 PM PDT 24
Finished	Aug 01 06:14:53 PM PDT 24
Peak memory	206884 kb
Host	smart-de58d411-84c0-41ab-8971-ba38e862e286
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72342 3688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.723423688
Directory	/workspace/18.usbdev_disconnected/latest

Test location	/workspace/coverage/default/18.usbdev_enable.2164993159
Short name	T695
Test name
Test status
Simulation time	55308220 ps
CPU time	0.71 seconds
Started	Aug 01 06:14:51 PM PDT 24
Finished	Aug 01 06:14:52 PM PDT 24
Peak memory	206868 kb
Host	smart-1a98b497-66ca-454e-9163-55baf41d2515
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21649 93159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2164993159
Directory	/workspace/18.usbdev_enable/latest

Test location	/workspace/coverage/default/18.usbdev_endpoint_access.733642838
Short name	T1790
Test name
Test status
Simulation time	955173601 ps
CPU time	2.52 seconds
Started	Aug 01 06:14:51 PM PDT 24
Finished	Aug 01 06:14:54 PM PDT 24
Peak memory	207156 kb
Host	smart-720d2d38-0ed6-4ac7-b3ea-380213cfe3bf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73364 2838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.733642838
Directory	/workspace/18.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/18.usbdev_endpoint_types.1252341573
Short name	T318
Test name
Test status
Simulation time	649370408 ps
CPU time	1.67 seconds
Started	Aug 01 06:14:58 PM PDT 24
Finished	Aug 01 06:15:00 PM PDT 24
Peak memory	206924 kb
Host	smart-b44eb7e3-baee-4fed-93f0-4dfaa488562a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1252341573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.1252341573
Directory	/workspace/18.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/18.usbdev_fifo_rst.77138348
Short name	T2632
Test name
Test status
Simulation time	357418682 ps
CPU time	2.16 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:14:57 PM PDT 24
Peak memory	207100 kb
Host	smart-afb2b22f-6ecc-4df9-810f-515531e7c44a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77138 348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.77138348
Directory	/workspace/18.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/18.usbdev_in_iso.984641680
Short name	T756
Test name
Test status
Simulation time	225170879 ps
CPU time	1.14 seconds
Started	Aug 01 06:14:54 PM PDT 24
Finished	Aug 01 06:14:55 PM PDT 24
Peak memory	207100 kb
Host	smart-8388b0ad-048f-4c10-8ac7-4e8d67bd17a4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=984641680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.984641680
Directory	/workspace/18.usbdev_in_iso/latest

Test location	/workspace/coverage/default/18.usbdev_in_stall.1884598677
Short name	T557
Test name
Test status
Simulation time	186865654 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:54 PM PDT 24
Finished	Aug 01 06:14:55 PM PDT 24
Peak memory	206868 kb
Host	smart-30ddaaf5-f83d-40f1-936a-8d50e23c20ac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18845 98677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1884598677
Directory	/workspace/18.usbdev_in_stall/latest

Test location	/workspace/coverage/default/18.usbdev_in_trans.2989198774
Short name	T1956
Test name
Test status
Simulation time	189708000 ps
CPU time	0.94 seconds
Started	Aug 01 06:14:53 PM PDT 24
Finished	Aug 01 06:14:55 PM PDT 24
Peak memory	206948 kb
Host	smart-76e7ccba-1bca-464a-9e02-4a0222e1fea7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29891 98774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2989198774
Directory	/workspace/18.usbdev_in_trans/latest

Test location	/workspace/coverage/default/18.usbdev_invalid_sync.1274129190
Short name	T2731
Test name
Test status
Simulation time	2871726608 ps
CPU time	28.61 seconds
Started	Aug 01 06:14:57 PM PDT 24
Finished	Aug 01 06:15:26 PM PDT 24
Peak memory	223492 kb
Host	smart-1ce59e7a-297c-499c-b2aa-cda3c6790bef
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1274129190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.1274129190
Directory	/workspace/18.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/18.usbdev_link_in_err.1941452892
Short name	T738
Test name
Test status
Simulation time	223964922 ps
CPU time	1 seconds
Started	Aug 01 06:15:04 PM PDT 24
Finished	Aug 01 06:15:05 PM PDT 24
Peak memory	206940 kb
Host	smart-cc1e3ef1-3a38-4821-ac06-23c01a740d1c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19414 52892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.1941452892
Directory	/workspace/18.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/18.usbdev_link_suspend.2081816167
Short name	T2485
Test name
Test status
Simulation time	9118553864 ps
CPU time	12.77 seconds
Started	Aug 01 06:14:52 PM PDT 24
Finished	Aug 01 06:15:05 PM PDT 24
Peak memory	207172 kb
Host	smart-4ae47df1-1c4c-4e54-b439-da2d4f99dc15
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20818 16167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2081816167
Directory	/workspace/18.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/18.usbdev_low_speed_traffic.2043007014
Short name	T997
Test name
Test status
Simulation time	3479774428 ps
CPU time	99.16 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:16:34 PM PDT 24
Peak memory	217768 kb
Host	smart-df3ae971-14b7-429e-967e-bfdf88a26317
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20430 07014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.2043007014
Directory	/workspace/18.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1189217122
Short name	T2881
Test name
Test status
Simulation time	2380605264 ps
CPU time	23.16 seconds
Started	Aug 01 06:15:01 PM PDT 24
Finished	Aug 01 06:15:25 PM PDT 24
Peak memory	223564 kb
Host	smart-81efc4a3-144b-4d7b-abaf-b35a68ddfbd2
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1189217122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1189217122
Directory	/workspace/18.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/18.usbdev_max_length_in_transaction.592856018
Short name	T559
Test name
Test status
Simulation time	234515596 ps
CPU time	1.04 seconds
Started	Aug 01 06:15:03 PM PDT 24
Finished	Aug 01 06:15:04 PM PDT 24
Peak memory	206956 kb
Host	smart-d5d076d8-6173-457f-b52c-27f4a65a8013
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=592856018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.592856018
Directory	/workspace/18.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/18.usbdev_max_length_out_transaction.795638083
Short name	T2097
Test name
Test status
Simulation time	192367510 ps
CPU time	0.96 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:14:56 PM PDT 24
Peak memory	206928 kb
Host	smart-ec2094b6-8b43-4e30-baef-1d272ca81834
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79563 8083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.795638083
Directory	/workspace/18.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.2930588636
Short name	T1615
Test name
Test status
Simulation time	1751683345 ps
CPU time	14.14 seconds
Started	Aug 01 06:14:53 PM PDT 24
Finished	Aug 01 06:15:07 PM PDT 24
Peak memory	223468 kb
Host	smart-d8b3b9fd-7f29-455b-b4e1-8fb042c8cf53
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29305 88636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.2930588636
Directory	/workspace/18.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/18.usbdev_min_inter_pkt_delay.2372995575
Short name	T2472
Test name
Test status
Simulation time	3275601785 ps
CPU time	33.77 seconds
Started	Aug 01 06:14:56 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	215388 kb
Host	smart-e6514179-c267-4c7f-a263-159043964cd1
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2372995575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.2372995575
Directory	/workspace/18.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/18.usbdev_min_length_in_transaction.4014066627
Short name	T834
Test name
Test status
Simulation time	155162842 ps
CPU time	0.85 seconds
Started	Aug 01 06:14:57 PM PDT 24
Finished	Aug 01 06:14:58 PM PDT 24
Peak memory	206952 kb
Host	smart-48db0402-a8c3-4d61-8fba-70bdae072245
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4014066627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.4014066627
Directory	/workspace/18.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/18.usbdev_min_length_out_transaction.2455249679
Short name	T2695
Test name
Test status
Simulation time	206580104 ps
CPU time	0.95 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:14:57 PM PDT 24
Peak memory	206908 kb
Host	smart-1e0a031f-20ea-48b5-be21-f0cc5f15007d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24552 49679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2455249679
Directory	/workspace/18.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/18.usbdev_nak_trans.134619114
Short name	T200
Test name
Test status
Simulation time	184036891 ps
CPU time	0.91 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:14:56 PM PDT 24
Peak memory	206948 kb
Host	smart-7beef673-4fa4-4a20-8652-7a4ef8b04070
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13461 9114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.134619114
Directory	/workspace/18.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/18.usbdev_out_iso.1900530985
Short name	T519
Test name
Test status
Simulation time	183347020 ps
CPU time	0.97 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:14:56 PM PDT 24
Peak memory	206948 kb
Host	smart-a85db2af-bb60-467f-ae52-d1a58d259b3e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19005 30985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.1900530985
Directory	/workspace/18.usbdev_out_iso/latest

Test location	/workspace/coverage/default/18.usbdev_out_stall.2293897549
Short name	T2002
Test name
Test status
Simulation time	223556754 ps
CPU time	0.9 seconds
Started	Aug 01 06:14:57 PM PDT 24
Finished	Aug 01 06:14:58 PM PDT 24
Peak memory	206940 kb
Host	smart-b96211da-ba17-450b-93b5-c3aff3bd6aed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22938 97549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.2293897549
Directory	/workspace/18.usbdev_out_stall/latest

Test location	/workspace/coverage/default/18.usbdev_out_trans_nak.3671325883
Short name	T1261
Test name
Test status
Simulation time	171339469 ps
CPU time	0.85 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:14:56 PM PDT 24
Peak memory	206948 kb
Host	smart-c4309123-2eed-48bf-9a01-3cadbda583e7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36713 25883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3671325883
Directory	/workspace/18.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/18.usbdev_pending_in_trans.83626925
Short name	T2373
Test name
Test status
Simulation time	148418376 ps
CPU time	0.81 seconds
Started	Aug 01 06:14:51 PM PDT 24
Finished	Aug 01 06:14:52 PM PDT 24
Peak memory	206924 kb
Host	smart-de4250b6-40a3-42da-8078-ea59688ff8ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83626 925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.83626925
Directory	/workspace/18.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/18.usbdev_phy_config_pinflip.1140596846
Short name	T2179
Test name
Test status
Simulation time	251291321 ps
CPU time	1.06 seconds
Started	Aug 01 06:14:57 PM PDT 24
Finished	Aug 01 06:14:58 PM PDT 24
Peak memory	206948 kb
Host	smart-cf67b04c-b1ac-4f0a-ae29-9bd25bbd38b8
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1140596846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1140596846
Directory	/workspace/18.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3996424730
Short name	T932
Test name
Test status
Simulation time	151662777 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:57 PM PDT 24
Finished	Aug 01 06:14:58 PM PDT 24
Peak memory	206940 kb
Host	smart-7af62a13-4be4-4709-9e8d-8bd5561ae4db
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39964 24730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3996424730
Directory	/workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/18.usbdev_phy_pins_sense.4233582999
Short name	T2794
Test name
Test status
Simulation time	39988041 ps
CPU time	0.68 seconds
Started	Aug 01 06:14:58 PM PDT 24
Finished	Aug 01 06:14:58 PM PDT 24
Peak memory	206872 kb
Host	smart-dfdd2d74-e54a-467e-9d76-27779317bac5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42335 82999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.4233582999
Directory	/workspace/18.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/18.usbdev_pkt_buffer.150354041
Short name	T2615
Test name
Test status
Simulation time	16551811304 ps
CPU time	45.43 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:15:40 PM PDT 24
Peak memory	223548 kb
Host	smart-4d8c5d10-e5b7-41cc-87f9-563a7584381a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15035 4041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.150354041
Directory	/workspace/18.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/18.usbdev_pkt_received.2040543625
Short name	T2645
Test name
Test status
Simulation time	179176464 ps
CPU time	0.95 seconds
Started	Aug 01 06:15:02 PM PDT 24
Finished	Aug 01 06:15:03 PM PDT 24
Peak memory	206960 kb
Host	smart-11f7eb03-ae5d-4485-9042-de65e8ae6f0f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20405 43625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2040543625
Directory	/workspace/18.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/18.usbdev_pkt_sent.2206516990
Short name	T148
Test name
Test status
Simulation time	223772675 ps
CPU time	1.01 seconds
Started	Aug 01 06:15:04 PM PDT 24
Finished	Aug 01 06:15:05 PM PDT 24
Peak memory	206956 kb
Host	smart-f15bd3f3-106c-41f7-96b3-77644b294021
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22065 16990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2206516990
Directory	/workspace/18.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/18.usbdev_random_length_in_transaction.1767664221
Short name	T1567
Test name
Test status
Simulation time	187639265 ps
CPU time	0.9 seconds
Started	Aug 01 06:14:54 PM PDT 24
Finished	Aug 01 06:14:55 PM PDT 24
Peak memory	207000 kb
Host	smart-3982c4ed-d277-48f4-873b-2619601806f2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17676 64221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.1767664221
Directory	/workspace/18.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/18.usbdev_random_length_out_transaction.2046507530
Short name	T1524
Test name
Test status
Simulation time	202797845 ps
CPU time	0.93 seconds
Started	Aug 01 06:14:59 PM PDT 24
Finished	Aug 01 06:15:00 PM PDT 24
Peak memory	206956 kb
Host	smart-9636659b-79c2-4a68-b48c-19db33b61783
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20465 07530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.2046507530
Directory	/workspace/18.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/18.usbdev_rx_crc_err.629481243
Short name	T2049
Test name
Test status
Simulation time	201117850 ps
CPU time	0.87 seconds
Started	Aug 01 06:14:56 PM PDT 24
Finished	Aug 01 06:14:57 PM PDT 24
Peak memory	206964 kb
Host	smart-f04ce0a3-f769-4eaf-9ae3-9dcf7097b84b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62948 1243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.629481243
Directory	/workspace/18.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/18.usbdev_rx_full.3708996686
Short name	T1744
Test name
Test status
Simulation time	262481692 ps
CPU time	1.13 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:14:57 PM PDT 24
Peak memory	206920 kb
Host	smart-79423231-156d-4255-a547-6954315bdb06
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37089 96686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.3708996686
Directory	/workspace/18.usbdev_rx_full/latest

Test location	/workspace/coverage/default/18.usbdev_setup_stage.3889751943
Short name	T773
Test name
Test status
Simulation time	151100981 ps
CPU time	0.84 seconds
Started	Aug 01 06:14:59 PM PDT 24
Finished	Aug 01 06:15:00 PM PDT 24
Peak memory	206916 kb
Host	smart-e582179a-efe3-45cc-b809-6c6fb03a7cb3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38897 51943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.3889751943
Directory	/workspace/18.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/18.usbdev_setup_trans_ignored.1372241349
Short name	T839
Test name
Test status
Simulation time	162238529 ps
CPU time	0.85 seconds
Started	Aug 01 06:15:02 PM PDT 24
Finished	Aug 01 06:15:03 PM PDT 24
Peak memory	206964 kb
Host	smart-37260a54-0eb8-4e44-a40b-a4336c7b305f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13722 41349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1372241349
Directory	/workspace/18.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/18.usbdev_smoke.1722399329
Short name	T1467
Test name
Test status
Simulation time	230748341 ps
CPU time	0.98 seconds
Started	Aug 01 06:14:54 PM PDT 24
Finished	Aug 01 06:14:55 PM PDT 24
Peak memory	206944 kb
Host	smart-921b18b5-6a41-4a89-a053-4d01dc4ea47a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17223 99329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1722399329
Directory	/workspace/18.usbdev_smoke/latest

Test location	/workspace/coverage/default/18.usbdev_spurious_pids_ignored.1398809057
Short name	T580
Test name
Test status
Simulation time	1511114294 ps
CPU time	41.39 seconds
Started	Aug 01 06:14:57 PM PDT 24
Finished	Aug 01 06:15:38 PM PDT 24
Peak memory	215324 kb
Host	smart-02232f53-4463-4c3f-b27b-f13f2cede219
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1398809057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.1398809057
Directory	/workspace/18.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/18.usbdev_stall_priority_over_nak.154731186
Short name	T1611
Test name
Test status
Simulation time	170570638 ps
CPU time	0.91 seconds
Started	Aug 01 06:14:55 PM PDT 24
Finished	Aug 01 06:14:56 PM PDT 24
Peak memory	206888 kb
Host	smart-67e4040f-ef0a-4de0-b844-84560004d49a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15473 1186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.154731186
Directory	/workspace/18.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/18.usbdev_stall_trans.1165226307
Short name	T1714
Test name
Test status
Simulation time	183244071 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:04 PM PDT 24
Finished	Aug 01 06:15:05 PM PDT 24
Peak memory	206904 kb
Host	smart-4fec01d2-3757-41d9-b7da-69c0de96d171
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11652 26307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.1165226307
Directory	/workspace/18.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/18.usbdev_stream_len_max.2304917063
Short name	T1823
Test name
Test status
Simulation time	1405945171 ps
CPU time	3.54 seconds
Started	Aug 01 06:14:56 PM PDT 24
Finished	Aug 01 06:14:59 PM PDT 24
Peak memory	207128 kb
Host	smart-363343f5-c6e8-45c3-9d13-bdd42a8bf245
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23049 17063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.2304917063
Directory	/workspace/18.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/18.usbdev_streaming_out.2924487256
Short name	T2850
Test name
Test status
Simulation time	2981948207 ps
CPU time	32.94 seconds
Started	Aug 01 06:14:57 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	223460 kb
Host	smart-1908a10d-06e8-49f7-9600-b4530eeef483
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29244 87256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2924487256
Directory	/workspace/18.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.2768018743
Short name	T800
Test name
Test status
Simulation time	3155226046 ps
CPU time	22.97 seconds
Started	Aug 01 06:14:57 PM PDT 24
Finished	Aug 01 06:15:20 PM PDT 24
Peak memory	207180 kb
Host	smart-427ac12a-cc72-4af5-9a98-2e6ab1c952e7
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768018743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos t_handshake.2768018743
Directory	/workspace/18.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/181.usbdev_endpoint_types.3181087838
Short name	T426
Test name
Test status
Simulation time	206714232 ps
CPU time	0.92 seconds
Started	Aug 01 06:20:23 PM PDT 24
Finished	Aug 01 06:20:24 PM PDT 24
Peak memory	206896 kb
Host	smart-bf83691c-2f05-43e4-89c6-a1d42f06a922
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3181087838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.3181087838
Directory	/workspace/181.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/182.usbdev_endpoint_types.303986273
Short name	T1907
Test name
Test status
Simulation time	338469515 ps
CPU time	1.17 seconds
Started	Aug 01 06:20:22 PM PDT 24
Finished	Aug 01 06:20:24 PM PDT 24
Peak memory	206924 kb
Host	smart-3ec3a3f5-434d-45f6-971e-09fbe7f695f7
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=303986273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.303986273
Directory	/workspace/182.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/183.usbdev_endpoint_types.4091649432
Short name	T2607
Test name
Test status
Simulation time	577778291 ps
CPU time	1.37 seconds
Started	Aug 01 06:20:26 PM PDT 24
Finished	Aug 01 06:20:28 PM PDT 24
Peak memory	206888 kb
Host	smart-7443f4c3-33ef-4659-8dfe-6a8960edcd53
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4091649432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.4091649432
Directory	/workspace/183.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/184.usbdev_endpoint_types.2467706425
Short name	T346
Test name
Test status
Simulation time	919162972 ps
CPU time	1.85 seconds
Started	Aug 01 06:20:20 PM PDT 24
Finished	Aug 01 06:20:21 PM PDT 24
Peak memory	206936 kb
Host	smart-9bedf4a3-f07e-48c9-9381-7510d3aa8957
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2467706425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.2467706425
Directory	/workspace/184.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/185.usbdev_endpoint_types.2275578584
Short name	T382
Test name
Test status
Simulation time	737338944 ps
CPU time	1.65 seconds
Started	Aug 01 06:20:30 PM PDT 24
Finished	Aug 01 06:20:32 PM PDT 24
Peak memory	206896 kb
Host	smart-f2e7696e-cddb-4650-b012-985870102ce4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2275578584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.2275578584
Directory	/workspace/185.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/187.usbdev_endpoint_types.523320487
Short name	T73
Test name
Test status
Simulation time	645443744 ps
CPU time	1.57 seconds
Started	Aug 01 06:20:13 PM PDT 24
Finished	Aug 01 06:20:15 PM PDT 24
Peak memory	206856 kb
Host	smart-90770bf3-c03d-4d2a-a32d-d73d0fbf6f73
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=523320487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.523320487
Directory	/workspace/187.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/188.usbdev_endpoint_types.2830912407
Short name	T380
Test name
Test status
Simulation time	452257599 ps
CPU time	1.42 seconds
Started	Aug 01 06:20:19 PM PDT 24
Finished	Aug 01 06:20:20 PM PDT 24
Peak memory	206872 kb
Host	smart-4f940912-6327-4ec1-aae5-45a4513c22ec
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2830912407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.2830912407
Directory	/workspace/188.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/189.usbdev_endpoint_types.2785648152
Short name	T1804
Test name
Test status
Simulation time	737322972 ps
CPU time	1.76 seconds
Started	Aug 01 06:20:25 PM PDT 24
Finished	Aug 01 06:20:27 PM PDT 24
Peak memory	206920 kb
Host	smart-aa56f1c6-6aaa-432c-891f-eed72e683ef8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2785648152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.2785648152
Directory	/workspace/189.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/19.usbdev_alert_test.2216359525
Short name	T1125
Test name
Test status
Simulation time	53270814 ps
CPU time	0.7 seconds
Started	Aug 01 06:15:11 PM PDT 24
Finished	Aug 01 06:15:12 PM PDT 24
Peak memory	206968 kb
Host	smart-33e84de7-dc7d-412e-a0e6-3a7b3d934205
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2216359525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2216359525
Directory	/workspace/19.usbdev_alert_test/latest

Test location	/workspace/coverage/default/19.usbdev_av_buffer.1780551030
Short name	T2531
Test name
Test status
Simulation time	215645859 ps
CPU time	1.01 seconds
Started	Aug 01 06:15:04 PM PDT 24
Finished	Aug 01 06:15:05 PM PDT 24
Peak memory	206944 kb
Host	smart-aa7b4431-9daa-45f2-8206-ed80d60b7ec2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17805 51030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1780551030
Directory	/workspace/19.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/19.usbdev_bitstuff_err.182490616
Short name	T2175
Test name
Test status
Simulation time	139539165 ps
CPU time	0.85 seconds
Started	Aug 01 06:15:05 PM PDT 24
Finished	Aug 01 06:15:06 PM PDT 24
Peak memory	206928 kb
Host	smart-6a153f19-be2f-4d90-a143-9e38c5569dc4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18249 0616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.182490616
Directory	/workspace/19.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/19.usbdev_data_toggle_clear.1864555164
Short name	T1223
Test name
Test status
Simulation time	410863788 ps
CPU time	1.4 seconds
Started	Aug 01 06:15:03 PM PDT 24
Finished	Aug 01 06:15:05 PM PDT 24
Peak memory	206932 kb
Host	smart-c3183d4e-43c2-47a6-9773-f0651cdf211e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18645 55164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1864555164
Directory	/workspace/19.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/19.usbdev_data_toggle_restore.1350949693
Short name	T2202
Test name
Test status
Simulation time	921496114 ps
CPU time	2.34 seconds
Started	Aug 01 06:15:03 PM PDT 24
Finished	Aug 01 06:15:05 PM PDT 24
Peak memory	207128 kb
Host	smart-c0ba284d-8952-402a-8ccd-a6221f9ba3d8
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1350949693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1350949693
Directory	/workspace/19.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/19.usbdev_device_address.1210818410
Short name	T1821
Test name
Test status
Simulation time	22287161775 ps
CPU time	35.03 seconds
Started	Aug 01 06:14:59 PM PDT 24
Finished	Aug 01 06:15:34 PM PDT 24
Peak memory	207188 kb
Host	smart-a4034db4-63d0-4458-942d-3c7b0110d9c0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12108 18410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1210818410
Directory	/workspace/19.usbdev_device_address/latest

Test location	/workspace/coverage/default/19.usbdev_device_timeout.3878133789
Short name	T694
Test name
Test status
Simulation time	658976023 ps
CPU time	5.17 seconds
Started	Aug 01 06:15:02 PM PDT 24
Finished	Aug 01 06:15:08 PM PDT 24
Peak memory	207068 kb
Host	smart-670a7d84-952e-4b7d-95b4-22ee49f0955d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878133789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.3878133789
Directory	/workspace/19.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/19.usbdev_disable_endpoint.3310617243
Short name	T748
Test name
Test status
Simulation time	867306361 ps
CPU time	2.07 seconds
Started	Aug 01 06:15:04 PM PDT 24
Finished	Aug 01 06:15:06 PM PDT 24
Peak memory	206920 kb
Host	smart-8e570190-a322-45ad-94ae-cdcf5a3afe76
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33106 17243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3310617243
Directory	/workspace/19.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/19.usbdev_disconnected.934286698
Short name	T2352
Test name
Test status
Simulation time	184247958 ps
CPU time	0.86 seconds
Started	Aug 01 06:15:04 PM PDT 24
Finished	Aug 01 06:15:05 PM PDT 24
Peak memory	206872 kb
Host	smart-b3b8a9f8-a0f2-4f62-bdb4-c8e3b3476df3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93428 6698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.934286698
Directory	/workspace/19.usbdev_disconnected/latest

Test location	/workspace/coverage/default/19.usbdev_enable.1263205537
Short name	T2376
Test name
Test status
Simulation time	54061343 ps
CPU time	0.81 seconds
Started	Aug 01 06:15:04 PM PDT 24
Finished	Aug 01 06:15:05 PM PDT 24
Peak memory	206908 kb
Host	smart-3e171e2f-148a-4651-9353-12bd9b92f360
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12632 05537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.1263205537
Directory	/workspace/19.usbdev_enable/latest

Test location	/workspace/coverage/default/19.usbdev_endpoint_access.3297812105
Short name	T1181
Test name
Test status
Simulation time	833076506 ps
CPU time	2.37 seconds
Started	Aug 01 06:14:59 PM PDT 24
Finished	Aug 01 06:15:02 PM PDT 24
Peak memory	207144 kb
Host	smart-200fa588-b058-4e28-a142-e415eaefde03
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32978 12105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3297812105
Directory	/workspace/19.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/19.usbdev_endpoint_types.2069762440
Short name	T395
Test name
Test status
Simulation time	287949763 ps
CPU time	1.1 seconds
Started	Aug 01 06:14:57 PM PDT 24
Finished	Aug 01 06:14:59 PM PDT 24
Peak memory	206916 kb
Host	smart-4c4b83bb-bd7b-4898-a53f-1049259fae4e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2069762440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.2069762440
Directory	/workspace/19.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/19.usbdev_fifo_rst.1816965854
Short name	T2025
Test name
Test status
Simulation time	182206466 ps
CPU time	2.18 seconds
Started	Aug 01 06:15:05 PM PDT 24
Finished	Aug 01 06:15:08 PM PDT 24
Peak memory	207156 kb
Host	smart-827ca092-ed3e-428a-b14f-870c54c5988b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18169 65854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1816965854
Directory	/workspace/19.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/19.usbdev_in_iso.2545610689
Short name	T2004
Test name
Test status
Simulation time	304273341 ps
CPU time	1.29 seconds
Started	Aug 01 06:14:58 PM PDT 24
Finished	Aug 01 06:15:00 PM PDT 24
Peak memory	215280 kb
Host	smart-d8f1dfe3-4725-404d-a229-7bf7c4a8f904
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2545610689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2545610689
Directory	/workspace/19.usbdev_in_iso/latest

Test location	/workspace/coverage/default/19.usbdev_in_stall.3958571558
Short name	T2048
Test name
Test status
Simulation time	153966636 ps
CPU time	0.85 seconds
Started	Aug 01 06:14:56 PM PDT 24
Finished	Aug 01 06:14:57 PM PDT 24
Peak memory	206940 kb
Host	smart-77dff773-faab-4e1a-8d75-d87eb630faa8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585 71558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3958571558
Directory	/workspace/19.usbdev_in_stall/latest

Test location	/workspace/coverage/default/19.usbdev_in_trans.1646646912
Short name	T2435
Test name
Test status
Simulation time	187172403 ps
CPU time	0.96 seconds
Started	Aug 01 06:15:03 PM PDT 24
Finished	Aug 01 06:15:04 PM PDT 24
Peak memory	206968 kb
Host	smart-a4cbcbf8-9a7e-4244-bf78-d3e3277d03fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16466 46912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.1646646912
Directory	/workspace/19.usbdev_in_trans/latest

Test location	/workspace/coverage/default/19.usbdev_invalid_sync.2246441698
Short name	T2030
Test name
Test status
Simulation time	2708369739 ps
CPU time	26.04 seconds
Started	Aug 01 06:15:04 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	223540 kb
Host	smart-0e11ae11-edd9-4996-891d-727c97150027
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2246441698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2246441698
Directory	/workspace/19.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/19.usbdev_iso_retraction.2653948136
Short name	T1868
Test name
Test status
Simulation time	13661448908 ps
CPU time	98.24 seconds
Started	Aug 01 06:15:02 PM PDT 24
Finished	Aug 01 06:16:40 PM PDT 24
Peak memory	207124 kb
Host	smart-4ba69332-8ac4-45db-bb17-54a4f62febc4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2653948136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.2653948136
Directory	/workspace/19.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/19.usbdev_link_in_err.311470878
Short name	T2631
Test name
Test status
Simulation time	167751709 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:15 PM PDT 24
Peak memory	206984 kb
Host	smart-dc2dfd30-b1ab-43f5-8abc-b01487f9030f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31147 0878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.311470878
Directory	/workspace/19.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/19.usbdev_low_speed_traffic.4273113162
Short name	T288
Test name
Test status
Simulation time	3826313361 ps
CPU time	112.11 seconds
Started	Aug 01 06:15:10 PM PDT 24
Finished	Aug 01 06:17:03 PM PDT 24
Peak memory	217712 kb
Host	smart-cabb0977-7e1e-4f9e-be81-a79f78af6c7d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42731 13162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.4273113162
Directory	/workspace/19.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2341526773
Short name	T1523
Test name
Test status
Simulation time	1911386050 ps
CPU time	14.79 seconds
Started	Aug 01 06:15:12 PM PDT 24
Finished	Aug 01 06:15:27 PM PDT 24
Peak memory	216164 kb
Host	smart-8d9eedb1-b817-4b6b-8df9-67260c52ab2c
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2341526773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2341526773
Directory	/workspace/19.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/19.usbdev_max_length_in_transaction.345482060
Short name	T2468
Test name
Test status
Simulation time	248547233 ps
CPU time	1.1 seconds
Started	Aug 01 06:15:16 PM PDT 24
Finished	Aug 01 06:15:18 PM PDT 24
Peak memory	206904 kb
Host	smart-75a92efb-97d6-4b5b-bf77-c8eb50b6cb8a
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=345482060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.345482060
Directory	/workspace/19.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/19.usbdev_max_length_out_transaction.2563522284
Short name	T2056
Test name
Test status
Simulation time	262457205 ps
CPU time	1.07 seconds
Started	Aug 01 06:15:11 PM PDT 24
Finished	Aug 01 06:15:12 PM PDT 24
Peak memory	206960 kb
Host	smart-eeedbc9a-ae66-4117-9091-bed11e7c4cdc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25635 22284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2563522284
Directory	/workspace/19.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.1348949381
Short name	T1145
Test name
Test status
Simulation time	2660111026 ps
CPU time	73.5 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:16:29 PM PDT 24
Peak memory	217064 kb
Host	smart-e23c9478-75ac-45b5-bd45-ea4afb28c7cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13489 49381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.1348949381
Directory	/workspace/19.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3599032456
Short name	T1878
Test name
Test status
Simulation time	2948303599 ps
CPU time	22.98 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:37 PM PDT 24
Peak memory	207204 kb
Host	smart-516d93d4-2d09-4510-a009-d4dac0f4d136
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3599032456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3599032456
Directory	/workspace/19.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/19.usbdev_min_length_in_transaction.1038173338
Short name	T1944
Test name
Test status
Simulation time	151416397 ps
CPU time	0.85 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:17 PM PDT 24
Peak memory	206952 kb
Host	smart-92d6b43c-5e71-48ca-9285-2a53f3baa19d
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1038173338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.1038173338
Directory	/workspace/19.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/19.usbdev_min_length_out_transaction.1394417470
Short name	T728
Test name
Test status
Simulation time	144142758 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:16 PM PDT 24
Finished	Aug 01 06:15:17 PM PDT 24
Peak memory	206972 kb
Host	smart-7166a443-b8ff-4e69-a5ad-541002c08d5b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13944 17470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1394417470
Directory	/workspace/19.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/19.usbdev_nak_trans.1750775263
Short name	T176
Test name
Test status
Simulation time	213089012 ps
CPU time	1.02 seconds
Started	Aug 01 06:15:16 PM PDT 24
Finished	Aug 01 06:15:18 PM PDT 24
Peak memory	206968 kb
Host	smart-c0b55623-d595-40d2-8160-d3be1aae8ca5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17507 75263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1750775263
Directory	/workspace/19.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/19.usbdev_out_iso.140002161
Short name	T1643
Test name
Test status
Simulation time	214798723 ps
CPU time	0.96 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206952 kb
Host	smart-752234b0-25ff-48b6-95f9-bd43d7877b45
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14000 2161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.140002161
Directory	/workspace/19.usbdev_out_iso/latest

Test location	/workspace/coverage/default/19.usbdev_out_stall.802252564
Short name	T2024
Test name
Test status
Simulation time	164164272 ps
CPU time	0.86 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:15 PM PDT 24
Peak memory	206936 kb
Host	smart-f1224935-23a3-4e2a-b7e9-09a706371db5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80225 2564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.802252564
Directory	/workspace/19.usbdev_out_stall/latest

Test location	/workspace/coverage/default/19.usbdev_out_trans_nak.3940320518
Short name	T2752
Test name
Test status
Simulation time	172506826 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:16 PM PDT 24
Peak memory	206944 kb
Host	smart-67f4e6e3-d424-45d3-9bc7-4f15003b3977
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39403 20518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.3940320518
Directory	/workspace/19.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/19.usbdev_pending_in_trans.507411759
Short name	T1224
Test name
Test status
Simulation time	196451161 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206976 kb
Host	smart-5c02740b-42c7-4ba1-a5b5-649155de390f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50741 1759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.507411759
Directory	/workspace/19.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/19.usbdev_phy_config_pinflip.3757055435
Short name	T2008
Test name
Test status
Simulation time	228108043 ps
CPU time	1.03 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206944 kb
Host	smart-fee544e7-8145-449b-bf84-8a5f69b119b5
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3757055435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3757055435
Directory	/workspace/19.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.486659565
Short name	T2211
Test name
Test status
Simulation time	144583805 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:17 PM PDT 24
Peak memory	206944 kb
Host	smart-dae5c051-722c-455d-9b35-178f4797e32a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48665 9565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.486659565
Directory	/workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/19.usbdev_phy_pins_sense.1283531576
Short name	T1136
Test name
Test status
Simulation time	42872256 ps
CPU time	0.69 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:17 PM PDT 24
Peak memory	206864 kb
Host	smart-c060c679-7691-43b6-b26a-8a562eba4217
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12835 31576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1283531576
Directory	/workspace/19.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/19.usbdev_pkt_buffer.2635444130
Short name	T50
Test name
Test status
Simulation time	10315872030 ps
CPU time	29.66 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:43 PM PDT 24
Peak memory	215404 kb
Host	smart-a27cf0ec-422e-46d0-9180-e6dc9fb6db33
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26354 44130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2635444130
Directory	/workspace/19.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/19.usbdev_pkt_received.1992365688
Short name	T2783
Test name
Test status
Simulation time	214653266 ps
CPU time	1.06 seconds
Started	Aug 01 06:15:11 PM PDT 24
Finished	Aug 01 06:15:13 PM PDT 24
Peak memory	206920 kb
Host	smart-2e450a47-670e-4363-9d26-878957cb7287
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19923 65688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.1992365688
Directory	/workspace/19.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/19.usbdev_pkt_sent.1628740731
Short name	T2087
Test name
Test status
Simulation time	252710946 ps
CPU time	0.95 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:15 PM PDT 24
Peak memory	206836 kb
Host	smart-ffdc6754-ae57-4f15-92a8-5b78c3f81db5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16287 40731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1628740731
Directory	/workspace/19.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/19.usbdev_random_length_in_transaction.3320119375
Short name	T584
Test name
Test status
Simulation time	249301431 ps
CPU time	1.13 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:15 PM PDT 24
Peak memory	206896 kb
Host	smart-3d289672-8e32-4113-9a76-24585db77d69
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33201 19375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3320119375
Directory	/workspace/19.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/19.usbdev_random_length_out_transaction.4157147054
Short name	T760
Test name
Test status
Simulation time	206744703 ps
CPU time	0.94 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:16 PM PDT 24
Peak memory	206936 kb
Host	smart-329d10b5-ab92-45f0-b04c-f38154721617
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41571 47054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.4157147054
Directory	/workspace/19.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/19.usbdev_rx_crc_err.4081902575
Short name	T1604
Test name
Test status
Simulation time	162339181 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:11 PM PDT 24
Finished	Aug 01 06:15:12 PM PDT 24
Peak memory	206900 kb
Host	smart-282a7b95-aebd-49c4-9d3a-9744b97c27de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40819 02575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.4081902575
Directory	/workspace/19.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/19.usbdev_rx_full.344076733
Short name	T844
Test name
Test status
Simulation time	386749683 ps
CPU time	1.23 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:16 PM PDT 24
Peak memory	206952 kb
Host	smart-5c12350a-9b76-4884-97fd-2d524685ea6a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34407 6733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.344076733
Directory	/workspace/19.usbdev_rx_full/latest

Test location	/workspace/coverage/default/19.usbdev_setup_stage.1017586899
Short name	T1991
Test name
Test status
Simulation time	179452165 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:15 PM PDT 24
Peak memory	206896 kb
Host	smart-7ce064ed-96a1-4633-9074-243beaa516cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10175 86899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1017586899
Directory	/workspace/19.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/19.usbdev_setup_trans_ignored.1798347522
Short name	T2574
Test name
Test status
Simulation time	153166259 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206804 kb
Host	smart-ecf29804-6551-4be5-8286-de199bb249c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17983 47522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1798347522
Directory	/workspace/19.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/19.usbdev_smoke.2497326243
Short name	T1257
Test name
Test status
Simulation time	186992001 ps
CPU time	0.95 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:17 PM PDT 24
Peak memory	206952 kb
Host	smart-5279a00f-9284-4883-a7ab-c0302488486f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24973 26243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2497326243
Directory	/workspace/19.usbdev_smoke/latest

Test location	/workspace/coverage/default/19.usbdev_spurious_pids_ignored.4170333507
Short name	T2611
Test name
Test status
Simulation time	3674185079 ps
CPU time	30.08 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:45 PM PDT 24
Peak memory	223532 kb
Host	smart-7c164d73-f160-4ff0-ba02-30de616b57c8
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4170333507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.4170333507
Directory	/workspace/19.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/19.usbdev_stall_priority_over_nak.807920047
Short name	T1098
Test name
Test status
Simulation time	181516620 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:17 PM PDT 24
Finished	Aug 01 06:15:18 PM PDT 24
Peak memory	206932 kb
Host	smart-14646f20-fd7e-4723-a484-5185ed3b177a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80792 0047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.807920047
Directory	/workspace/19.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/19.usbdev_stall_trans.733763519
Short name	T596
Test name
Test status
Simulation time	170284783 ps
CPU time	0.89 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:17 PM PDT 24
Peak memory	206968 kb
Host	smart-2f397f26-b90e-4bb7-8b57-7eff23fb0510
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73376 3519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.733763519
Directory	/workspace/19.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/19.usbdev_stream_len_max.1787365847
Short name	T916
Test name
Test status
Simulation time	203356982 ps
CPU time	0.95 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206888 kb
Host	smart-f7b8ceaa-c9ee-4734-8d7f-09bfadc06126
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17873 65847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.1787365847
Directory	/workspace/19.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/19.usbdev_streaming_out.597303385
Short name	T2725
Test name
Test status
Simulation time	2472781685 ps
CPU time	25.85 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:40 PM PDT 24
Peak memory	217080 kb
Host	smart-04acb4dc-7eff-4179-894d-d1005c6b4b10
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59730 3385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.597303385
Directory	/workspace/19.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.4071582176
Short name	T698
Test name
Test status
Simulation time	9058350427 ps
CPU time	65.25 seconds
Started	Aug 01 06:15:07 PM PDT 24
Finished	Aug 01 06:16:13 PM PDT 24
Peak memory	207184 kb
Host	smart-053cd2e4-00ca-432c-ad93-4030b7c20f10
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071582176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos t_handshake.4071582176
Directory	/workspace/19.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/190.usbdev_endpoint_types.2633526762
Short name	T415
Test name
Test status
Simulation time	342515130 ps
CPU time	1.23 seconds
Started	Aug 01 06:20:15 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	206928 kb
Host	smart-dcd6f165-1158-4b39-a66c-396daf603f0b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2633526762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.2633526762
Directory	/workspace/190.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/191.usbdev_endpoint_types.3806947055
Short name	T2573
Test name
Test status
Simulation time	279343873 ps
CPU time	1.05 seconds
Started	Aug 01 06:20:23 PM PDT 24
Finished	Aug 01 06:20:24 PM PDT 24
Peak memory	206924 kb
Host	smart-5befed6f-d404-4b98-a4fb-2822363c65b9
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3806947055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.3806947055
Directory	/workspace/191.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/192.usbdev_endpoint_types.890323976
Short name	T378
Test name
Test status
Simulation time	520914950 ps
CPU time	1.4 seconds
Started	Aug 01 06:20:29 PM PDT 24
Finished	Aug 01 06:20:30 PM PDT 24
Peak memory	206940 kb
Host	smart-65fd7ed7-c934-46b7-bcee-0e4ab037594d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=890323976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.890323976
Directory	/workspace/192.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/193.usbdev_endpoint_types.387987421
Short name	T2510
Test name
Test status
Simulation time	169104744 ps
CPU time	0.91 seconds
Started	Aug 01 06:20:26 PM PDT 24
Finished	Aug 01 06:20:27 PM PDT 24
Peak memory	206944 kb
Host	smart-2eeb9cb3-e296-4b31-90d3-6d3f841eeb19
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=387987421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.387987421
Directory	/workspace/193.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/194.usbdev_endpoint_types.3320474656
Short name	T325
Test name
Test status
Simulation time	253178061 ps
CPU time	0.96 seconds
Started	Aug 01 06:20:23 PM PDT 24
Finished	Aug 01 06:20:24 PM PDT 24
Peak memory	206920 kb
Host	smart-f1cd4a86-a9f2-4204-8780-7082ce34fcc2
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3320474656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.3320474656
Directory	/workspace/194.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/195.usbdev_endpoint_types.3674848564
Short name	T2576
Test name
Test status
Simulation time	757632072 ps
CPU time	1.89 seconds
Started	Aug 01 06:20:24 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206896 kb
Host	smart-dc5b8dc2-49e7-4c98-8226-3caba06238e6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3674848564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.3674848564
Directory	/workspace/195.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/196.usbdev_endpoint_types.2802432196
Short name	T2391
Test name
Test status
Simulation time	286510674 ps
CPU time	1.04 seconds
Started	Aug 01 06:20:26 PM PDT 24
Finished	Aug 01 06:20:27 PM PDT 24
Peak memory	206880 kb
Host	smart-f0d36046-32d5-4947-baee-fc823056b3ee
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2802432196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.2802432196
Directory	/workspace/196.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/197.usbdev_endpoint_types.1007608786
Short name	T435
Test name
Test status
Simulation time	453936898 ps
CPU time	1.38 seconds
Started	Aug 01 06:20:32 PM PDT 24
Finished	Aug 01 06:20:33 PM PDT 24
Peak memory	206892 kb
Host	smart-0013fea0-0232-4704-8b53-b3d5057f040b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1007608786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.1007608786
Directory	/workspace/197.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/198.usbdev_endpoint_types.1410870794
Short name	T328
Test name
Test status
Simulation time	323410025 ps
CPU time	1.12 seconds
Started	Aug 01 06:20:32 PM PDT 24
Finished	Aug 01 06:20:33 PM PDT 24
Peak memory	206900 kb
Host	smart-9c0e618f-4657-4e67-8bc1-7b9985e27398
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1410870794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.1410870794
Directory	/workspace/198.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/199.usbdev_endpoint_types.256838430
Short name	T381
Test name
Test status
Simulation time	447477978 ps
CPU time	1.29 seconds
Started	Aug 01 06:20:33 PM PDT 24
Finished	Aug 01 06:20:34 PM PDT 24
Peak memory	206916 kb
Host	smart-0401cea6-428b-4595-b647-d03a9e4b3c83
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=256838430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.256838430
Directory	/workspace/199.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/2.usbdev_alert_test.1311027378
Short name	T118
Test name
Test status
Simulation time	32889050 ps
CPU time	0.67 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:25 PM PDT 24
Peak memory	206920 kb
Host	smart-3bfc9a0b-89f0-43e3-89b3-8beb40fd9b57
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1311027378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.1311027378
Directory	/workspace/2.usbdev_alert_test/latest

Test location	/workspace/coverage/default/2.usbdev_av_buffer.486027960
Short name	T2314
Test name
Test status
Simulation time	173739674 ps
CPU time	0.92 seconds
Started	Aug 01 06:11:19 PM PDT 24
Finished	Aug 01 06:11:20 PM PDT 24
Peak memory	206824 kb
Host	smart-a0def842-46dd-4b69-b456-87f377b62171
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48602 7960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.486027960
Directory	/workspace/2.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/2.usbdev_av_empty.1351862632
Short name	T1550
Test name
Test status
Simulation time	188621855 ps
CPU time	0.93 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:11:22 PM PDT 24
Peak memory	206936 kb
Host	smart-3fe23402-4278-4ed4-a1ec-9eda90afd59b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13518 62632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.1351862632
Directory	/workspace/2.usbdev_av_empty/latest

Test location	/workspace/coverage/default/2.usbdev_av_overflow.1164260895
Short name	T2293
Test name
Test status
Simulation time	159924002 ps
CPU time	0.85 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:11:23 PM PDT 24
Peak memory	206896 kb
Host	smart-00b0ea6e-ef6d-4a1e-b190-be948a29e6b3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11642 60895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1164260895
Directory	/workspace/2.usbdev_av_overflow/latest

Test location	/workspace/coverage/default/2.usbdev_bitstuff_err.4202227035
Short name	T2842
Test name
Test status
Simulation time	159682160 ps
CPU time	0.89 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:11:22 PM PDT 24
Peak memory	206884 kb
Host	smart-158601ef-9b5b-4c61-829f-7883ea31678b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42022 27035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.4202227035
Directory	/workspace/2.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/2.usbdev_data_toggle_clear.837301020
Short name	T1621
Test name
Test status
Simulation time	308925375 ps
CPU time	1.16 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:11:23 PM PDT 24
Peak memory	206972 kb
Host	smart-89d532bd-a8dc-4f7c-aefb-c8db4c29c3a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83730 1020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.837301020
Directory	/workspace/2.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/2.usbdev_data_toggle_restore.1630049589
Short name	T509
Test name
Test status
Simulation time	796076576 ps
CPU time	2.21 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	207120 kb
Host	smart-242fc2af-a3f4-4398-9623-0599e9b0ac79
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1630049589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.1630049589
Directory	/workspace/2.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/2.usbdev_device_address.3124445238
Short name	T151
Test name
Test status
Simulation time	50877902893 ps
CPU time	76.21 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:12:40 PM PDT 24
Peak memory	207184 kb
Host	smart-34c676f6-08b3-444a-950e-32025bda4a6d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31244 45238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3124445238
Directory	/workspace/2.usbdev_device_address/latest

Test location	/workspace/coverage/default/2.usbdev_device_timeout.428801613
Short name	T1230
Test name
Test status
Simulation time	585480620 ps
CPU time	11.63 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	207160 kb
Host	smart-76b1cb27-968c-4c29-878d-935214b56a98
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428801613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.428801613
Directory	/workspace/2.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/2.usbdev_disable_endpoint.2350541733
Short name	T633
Test name
Test status
Simulation time	705574739 ps
CPU time	1.64 seconds
Started	Aug 01 06:11:19 PM PDT 24
Finished	Aug 01 06:11:21 PM PDT 24
Peak memory	206892 kb
Host	smart-a650790c-81f3-4085-b0a0-9e019b69c9ea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23505 41733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2350541733
Directory	/workspace/2.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/2.usbdev_disconnected.887252540
Short name	T732
Test name
Test status
Simulation time	142536654 ps
CPU time	0.85 seconds
Started	Aug 01 06:11:20 PM PDT 24
Finished	Aug 01 06:11:21 PM PDT 24
Peak memory	206892 kb
Host	smart-b081c5ff-8b34-4550-8966-e9423f6c1ad7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88725 2540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.887252540
Directory	/workspace/2.usbdev_disconnected/latest

Test location	/workspace/coverage/default/2.usbdev_enable.2112110493
Short name	T1880
Test name
Test status
Simulation time	40499293 ps
CPU time	0.71 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	206912 kb
Host	smart-b4f6dc6c-0e37-42f6-97f2-d209f4657bd1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21121 10493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2112110493
Directory	/workspace/2.usbdev_enable/latest

Test location	/workspace/coverage/default/2.usbdev_endpoint_access.3800278520
Short name	T2223
Test name
Test status
Simulation time	1028791729 ps
CPU time	2.69 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:11:24 PM PDT 24
Peak memory	207156 kb
Host	smart-a5614856-694c-4f42-a964-e65f3ce86664
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38002 78520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3800278520
Directory	/workspace/2.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/2.usbdev_fifo_rst.3388586792
Short name	T2540
Test name
Test status
Simulation time	255523823 ps
CPU time	1.8 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:11:27 PM PDT 24
Peak memory	207080 kb
Host	smart-b1bb2751-446c-409e-b68e-1a97f8005f64
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33885 86792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3388586792
Directory	/workspace/2.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/2.usbdev_freq_hiclk.1425382590
Short name	T2383
Test name
Test status
Simulation time	94239848698 ps
CPU time	173.76 seconds
Started	Aug 01 06:11:20 PM PDT 24
Finished	Aug 01 06:14:14 PM PDT 24
Peak memory	207144 kb
Host	smart-5bed46a7-3401-41ba-8378-c0fb0551141d
User	root
Command	/workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1425382590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1425382590
Directory	/workspace/2.usbdev_freq_hiclk/latest

Test location	/workspace/coverage/default/2.usbdev_freq_hiclk_max.3893775776
Short name	T1767
Test name
Test status
Simulation time	88064951931 ps
CPU time	141.9 seconds
Started	Aug 01 06:11:20 PM PDT 24
Finished	Aug 01 06:13:42 PM PDT 24
Peak memory	207140 kb
Host	smart-10a3b6a7-0d2e-44ca-8d97-6f4ba96a7d60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893775776 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.3893775776
Directory	/workspace/2.usbdev_freq_hiclk_max/latest

Test location	/workspace/coverage/default/2.usbdev_freq_loclk.2997864896
Short name	T768
Test name
Test status
Simulation time	95159223252 ps
CPU time	151.72 seconds
Started	Aug 01 06:11:20 PM PDT 24
Finished	Aug 01 06:13:52 PM PDT 24
Peak memory	207184 kb
Host	smart-fdddb50e-fe3e-41c6-af85-6d18b16acbcc
User	root
Command	/workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2997864896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.2997864896
Directory	/workspace/2.usbdev_freq_loclk/latest

Test location	/workspace/coverage/default/2.usbdev_freq_loclk_max.3235199602
Short name	T2774
Test name
Test status
Simulation time	114064047517 ps
CPU time	169.82 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:14:14 PM PDT 24
Peak memory	207068 kb
Host	smart-63e8f01c-a3fe-4031-bd05-5299a245c016
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235199602 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.3235199602
Directory	/workspace/2.usbdev_freq_loclk_max/latest

Test location	/workspace/coverage/default/2.usbdev_freq_phase.2027882985
Short name	T2732
Test name
Test status
Simulation time	82129642840 ps
CPU time	135.87 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:13:39 PM PDT 24
Peak memory	207156 kb
Host	smart-ce6c5ca3-0e88-4a8e-8816-47db570eee8f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20278 82985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.2027882985
Directory	/workspace/2.usbdev_freq_phase/latest

Test location	/workspace/coverage/default/2.usbdev_in_iso.2932762203
Short name	T2382
Test name
Test status
Simulation time	197602727 ps
CPU time	1.03 seconds
Started	Aug 01 06:11:20 PM PDT 24
Finished	Aug 01 06:11:21 PM PDT 24
Peak memory	215268 kb
Host	smart-c49e6dec-cd2d-4817-b38b-ae9a4749f8e2
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2932762203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2932762203
Directory	/workspace/2.usbdev_in_iso/latest

Test location	/workspace/coverage/default/2.usbdev_in_stall.610618695
Short name	T2475
Test name
Test status
Simulation time	150180867 ps
CPU time	0.87 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:11:23 PM PDT 24
Peak memory	207156 kb
Host	smart-4ebc3a69-069a-4903-9eb0-c5eecca39a28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61061 8695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.610618695
Directory	/workspace/2.usbdev_in_stall/latest

Test location	/workspace/coverage/default/2.usbdev_in_trans.1463956771
Short name	T537
Test name
Test status
Simulation time	195926149 ps
CPU time	0.97 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:11:23 PM PDT 24
Peak memory	206956 kb
Host	smart-c8ddd4f7-3e9a-4eaf-9a03-25d1b093913a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14639 56771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1463956771
Directory	/workspace/2.usbdev_in_trans/latest

Test location	/workspace/coverage/default/2.usbdev_invalid_sync.610018746
Short name	T152
Test name
Test status
Simulation time	3015459265 ps
CPU time	25.87 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:51 PM PDT 24
Peak memory	217332 kb
Host	smart-fae8646a-4e8f-4c2d-8266-2b8cfd59eca4
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=610018746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.610018746
Directory	/workspace/2.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/2.usbdev_iso_retraction.1518735641
Short name	T662
Test name
Test status
Simulation time	8832846505 ps
CPU time	108.17 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:13:12 PM PDT 24
Peak memory	207104 kb
Host	smart-33462942-ba9b-47a1-896c-1524ea645878
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1518735641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.1518735641
Directory	/workspace/2.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/2.usbdev_link_in_err.352171257
Short name	T2547
Test name
Test status
Simulation time	227281020 ps
CPU time	1 seconds
Started	Aug 01 06:11:19 PM PDT 24
Finished	Aug 01 06:11:20 PM PDT 24
Peak memory	206936 kb
Host	smart-17370e12-c52c-44f1-a777-a7b0ef289406
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35217 1257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.352171257
Directory	/workspace/2.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/2.usbdev_link_suspend.206035409
Short name	T2526
Test name
Test status
Simulation time	10127288378 ps
CPU time	12.19 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	207180 kb
Host	smart-82b33705-24d3-4158-b11c-130e08e6d6ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20603 5409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.206035409
Directory	/workspace/2.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/2.usbdev_low_speed_traffic.3859638214
Short name	T1702
Test name
Test status
Simulation time	2983054024 ps
CPU time	89.89 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:12:55 PM PDT 24
Peak memory	215316 kb
Host	smart-872db22a-1a4b-487f-bf26-2b2e5b0d6962
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38596 38214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3859638214
Directory	/workspace/2.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/2.usbdev_max_inter_pkt_delay.159735859
Short name	T1346
Test name
Test status
Simulation time	1949758383 ps
CPU time	14.42 seconds
Started	Aug 01 06:11:19 PM PDT 24
Finished	Aug 01 06:11:34 PM PDT 24
Peak memory	207092 kb
Host	smart-ac042b63-67c5-4317-91ab-f6535a5a944d
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=159735859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.159735859
Directory	/workspace/2.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/2.usbdev_max_length_in_transaction.864763930
Short name	T232
Test name
Test status
Simulation time	283190223 ps
CPU time	1.04 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:11:24 PM PDT 24
Peak memory	206908 kb
Host	smart-fb24231a-f550-450e-ab36-28237463c899
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=864763930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.864763930
Directory	/workspace/2.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/2.usbdev_max_length_out_transaction.973330197
Short name	T502
Test name
Test status
Simulation time	193673551 ps
CPU time	0.95 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:11:22 PM PDT 24
Peak memory	206948 kb
Host	smart-4e1678dc-ce90-49fe-90e6-300320cd30ce
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97333 0197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.973330197
Directory	/workspace/2.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.562143064
Short name	T2766
Test name
Test status
Simulation time	3017468155 ps
CPU time	87.3 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:12:49 PM PDT 24
Peak memory	217128 kb
Host	smart-1d8ebd71-229b-4fa6-a8f9-7ab49c5f60d7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56214 3064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.562143064
Directory	/workspace/2.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/2.usbdev_max_usb_traffic.495136567
Short name	T1724
Test name
Test status
Simulation time	2657610361 ps
CPU time	77.91 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:12:41 PM PDT 24
Peak memory	223500 kb
Host	smart-e8b05dfe-c734-4045-9b74-fae7a314a053
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=495136567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.495136567
Directory	/workspace/2.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/2.usbdev_min_inter_pkt_delay.3466579834
Short name	T1271
Test name
Test status
Simulation time	2891619457 ps
CPU time	22.36 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:11:46 PM PDT 24
Peak memory	217088 kb
Host	smart-0a1e26e1-0de1-4868-bb38-45cbfd49ebde
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3466579834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.3466579834
Directory	/workspace/2.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/2.usbdev_min_length_in_transaction.3150632251
Short name	T893
Test name
Test status
Simulation time	165048290 ps
CPU time	0.84 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:25 PM PDT 24
Peak memory	206880 kb
Host	smart-dd965f3c-7bc1-4bd0-a694-b64cde165ccb
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3150632251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3150632251
Directory	/workspace/2.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/2.usbdev_min_length_out_transaction.1169327050
Short name	T919
Test name
Test status
Simulation time	162684420 ps
CPU time	0.89 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:11:24 PM PDT 24
Peak memory	206936 kb
Host	smart-d7266fed-f1f9-4339-af09-10e74a01235d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11693 27050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1169327050
Directory	/workspace/2.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/2.usbdev_nak_trans.3050140748
Short name	T2613
Test name
Test status
Simulation time	202009693 ps
CPU time	0.95 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:11:22 PM PDT 24
Peak memory	206940 kb
Host	smart-a6dbc25c-ec2d-4205-95d3-7227805f4118
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30501 40748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3050140748
Directory	/workspace/2.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/2.usbdev_out_iso.678212207
Short name	T2729
Test name
Test status
Simulation time	225626057 ps
CPU time	0.92 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:11:24 PM PDT 24
Peak memory	206964 kb
Host	smart-d5baf0c3-d7ac-4589-8cd4-46c8a44ab229
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67821 2207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.678212207
Directory	/workspace/2.usbdev_out_iso/latest

Test location	/workspace/coverage/default/2.usbdev_out_stall.3534741693
Short name	T1712
Test name
Test status
Simulation time	149498700 ps
CPU time	0.83 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	206880 kb
Host	smart-d27ed6cc-e5a3-4b34-a8b2-eda0d11e0ba0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35347 41693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3534741693
Directory	/workspace/2.usbdev_out_stall/latest

Test location	/workspace/coverage/default/2.usbdev_out_trans_nak.3762839593
Short name	T784
Test name
Test status
Simulation time	146346926 ps
CPU time	0.87 seconds
Started	Aug 01 06:11:26 PM PDT 24
Finished	Aug 01 06:11:27 PM PDT 24
Peak memory	206968 kb
Host	smart-0b51794a-8286-4f2c-96ee-b026739e1c90
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37628 39593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3762839593
Directory	/workspace/2.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/2.usbdev_pending_in_trans.300953135
Short name	T115
Test name
Test status
Simulation time	160527163 ps
CPU time	0.89 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:11:24 PM PDT 24
Peak memory	206908 kb
Host	smart-b39b7872-6a18-4c94-aefb-d9d27c2981b2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30095 3135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.300953135
Directory	/workspace/2.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/2.usbdev_phy_config_pinflip.1875125762
Short name	T2375
Test name
Test status
Simulation time	205861668 ps
CPU time	1.04 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:11:27 PM PDT 24
Peak memory	206908 kb
Host	smart-fb9b7625-e25f-4e03-bfdf-99a1c8c40c8c
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1875125762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1875125762
Directory	/workspace/2.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.3326675327
Short name	T132
Test name
Test status
Simulation time	205523289 ps
CPU time	1.11 seconds
Started	Aug 01 06:11:26 PM PDT 24
Finished	Aug 01 06:11:27 PM PDT 24
Peak memory	206972 kb
Host	smart-66977c33-6bd3-49af-b2ef-80db9ecab224
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33266 75327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.3326675327
Directory	/workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location	/workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1551614020
Short name	T2811
Test name
Test status
Simulation time	137497005 ps
CPU time	0.82 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	206940 kb
Host	smart-25298167-b8ec-433f-864a-29e814b32545
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15516 14020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1551614020
Directory	/workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/2.usbdev_phy_pins_sense.242907821
Short name	T21
Test name
Test status
Simulation time	66173093 ps
CPU time	0.72 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:11:22 PM PDT 24
Peak memory	206908 kb
Host	smart-7a2c7ddb-0c57-4a77-b0ff-0f7f26b53f75
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24290 7821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.242907821
Directory	/workspace/2.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/2.usbdev_pkt_buffer.790096956
Short name	T1378
Test name
Test status
Simulation time	18921175537 ps
CPU time	46.97 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:12:10 PM PDT 24
Peak memory	215368 kb
Host	smart-5715a216-8d72-4083-bfe6-046a90b13305
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79009 6956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.790096956
Directory	/workspace/2.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/2.usbdev_pkt_received.43401647
Short name	T603
Test name
Test status
Simulation time	159321726 ps
CPU time	0.85 seconds
Started	Aug 01 06:11:28 PM PDT 24
Finished	Aug 01 06:11:29 PM PDT 24
Peak memory	206960 kb
Host	smart-056b92da-896c-4b9e-9e63-a677297b9499
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43401 647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.43401647
Directory	/workspace/2.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/2.usbdev_pkt_sent.1746564911
Short name	T2784
Test name
Test status
Simulation time	183124596 ps
CPU time	0.93 seconds
Started	Aug 01 06:11:27 PM PDT 24
Finished	Aug 01 06:11:28 PM PDT 24
Peak memory	206964 kb
Host	smart-5b2f7cf6-bb27-4070-8fc0-8a1081b0d45f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17465 64911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1746564911
Directory	/workspace/2.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/2.usbdev_rand_bus_disconnects.548725850
Short name	T846
Test name
Test status
Simulation time	3609004928 ps
CPU time	26.2 seconds
Started	Aug 01 06:11:28 PM PDT 24
Finished	Aug 01 06:11:55 PM PDT 24
Peak memory	223520 kb
Host	smart-17224739-180b-4a2a-84a0-95cb27694650
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=548725850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.548725850
Directory	/workspace/2.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/2.usbdev_rand_bus_resets.2877587089
Short name	T2317
Test name
Test status
Simulation time	3821086177 ps
CPU time	37.43 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:12:02 PM PDT 24
Peak memory	223552 kb
Host	smart-8aa2c768-5a20-4d19-aba6-d54eca5a81b3
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877587089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2877587089
Directory	/workspace/2.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/2.usbdev_rand_suspends.3147154784
Short name	T2173
Test name
Test status
Simulation time	6943621564 ps
CPU time	34.22 seconds
Started	Aug 01 06:11:27 PM PDT 24
Finished	Aug 01 06:12:02 PM PDT 24
Peak memory	223512 kb
Host	smart-a6a80293-7c28-4a07-9995-38bddb1ccaf9
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147154784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3147154784
Directory	/workspace/2.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/2.usbdev_random_length_in_transaction.1889542830
Short name	T2712
Test name
Test status
Simulation time	265522470 ps
CPU time	1.01 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:25 PM PDT 24
Peak memory	206964 kb
Host	smart-aa07d45f-3da4-44f5-9724-a56d2b9cf324
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18895 42830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.1889542830
Directory	/workspace/2.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/2.usbdev_random_length_out_transaction.1290132879
Short name	T1963
Test name
Test status
Simulation time	146204712 ps
CPU time	0.91 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	206936 kb
Host	smart-ff621e4c-fa25-4c3f-bb35-74a76df6ec92
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12901 32879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1290132879
Directory	/workspace/2.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/2.usbdev_rx_crc_err.549558263
Short name	T1562
Test name
Test status
Simulation time	135503661 ps
CPU time	0.8 seconds
Started	Aug 01 06:11:27 PM PDT 24
Finished	Aug 01 06:11:28 PM PDT 24
Peak memory	206928 kb
Host	smart-4e3afef3-bf3c-493d-9bdf-fa2f87812ba2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54955 8263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.549558263
Directory	/workspace/2.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/2.usbdev_rx_full.649829014
Short name	T1167
Test name
Test status
Simulation time	255650703 ps
CPU time	1.12 seconds
Started	Aug 01 06:11:18 PM PDT 24
Finished	Aug 01 06:11:19 PM PDT 24
Peak memory	206936 kb
Host	smart-e8958563-5512-46d1-b5f6-88f5b585d7ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64982 9014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.649829014
Directory	/workspace/2.usbdev_rx_full/latest

Test location	/workspace/coverage/default/2.usbdev_rx_pid_err.2987453131
Short name	T63
Test name
Test status
Simulation time	197258792 ps
CPU time	0.9 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:11:27 PM PDT 24
Peak memory	206944 kb
Host	smart-5ccd75ef-33a9-45db-bb02-a0b56643ac57
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29874 53131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2987453131
Directory	/workspace/2.usbdev_rx_pid_err/latest

Test location	/workspace/coverage/default/2.usbdev_sec_cm.3332129080
Short name	T124
Test name
Test status
Simulation time	917437771 ps
CPU time	1.76 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	222712 kb
Host	smart-b75613b2-06f5-4c65-ade8-0d3937c982b5
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3332129080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3332129080
Directory	/workspace/2.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.972996583
Short name	T715
Test name
Test status
Simulation time	223133567 ps
CPU time	1 seconds
Started	Aug 01 06:11:27 PM PDT 24
Finished	Aug 01 06:11:28 PM PDT 24
Peak memory	206856 kb
Host	smart-a9e0c429-2b4b-408a-8aba-ae437803fdf1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97299 6583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.972996583
Directory	/workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location	/workspace/coverage/default/2.usbdev_setup_stage.2903510547
Short name	T778
Test name
Test status
Simulation time	156992492 ps
CPU time	0.85 seconds
Started	Aug 01 06:11:23 PM PDT 24
Finished	Aug 01 06:11:24 PM PDT 24
Peak memory	206868 kb
Host	smart-09b454ff-fae0-44b2-ab70-4e5a26b3a986
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29035 10547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2903510547
Directory	/workspace/2.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/2.usbdev_setup_trans_ignored.2115696156
Short name	T2817
Test name
Test status
Simulation time	164969582 ps
CPU time	0.89 seconds
Started	Aug 01 06:11:28 PM PDT 24
Finished	Aug 01 06:11:29 PM PDT 24
Peak memory	206856 kb
Host	smart-9fad7cae-33ab-483f-852c-1b8c93a63d3b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21156 96156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.2115696156
Directory	/workspace/2.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/2.usbdev_smoke.3347580192
Short name	T953
Test name
Test status
Simulation time	250725214 ps
CPU time	1.06 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	206944 kb
Host	smart-14714b63-fbfa-4509-80ae-b486667f243c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33475 80192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.3347580192
Directory	/workspace/2.usbdev_smoke/latest

Test location	/workspace/coverage/default/2.usbdev_spurious_pids_ignored.4089390111
Short name	T2650
Test name
Test status
Simulation time	1794361304 ps
CPU time	13.11 seconds
Started	Aug 01 06:11:27 PM PDT 24
Finished	Aug 01 06:11:40 PM PDT 24
Peak memory	207040 kb
Host	smart-40d0388c-77c4-4fdf-85c2-f4f4da262bb0
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4089390111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.4089390111
Directory	/workspace/2.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/2.usbdev_stall_priority_over_nak.2831504349
Short name	T1262
Test name
Test status
Simulation time	176890952 ps
CPU time	0.94 seconds
Started	Aug 01 06:11:34 PM PDT 24
Finished	Aug 01 06:11:35 PM PDT 24
Peak memory	206868 kb
Host	smart-4e1868be-2163-4dc1-b901-e328523a68c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28315 04349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.2831504349
Directory	/workspace/2.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/2.usbdev_stall_trans.2263808655
Short name	T2344
Test name
Test status
Simulation time	152447007 ps
CPU time	0.82 seconds
Started	Aug 01 06:11:32 PM PDT 24
Finished	Aug 01 06:11:33 PM PDT 24
Peak memory	207000 kb
Host	smart-36a6a5ad-21d9-429f-8c3a-7dd1e578e172
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22638 08655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2263808655
Directory	/workspace/2.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/2.usbdev_stream_len_max.2009771738
Short name	T491
Test name
Test status
Simulation time	1047365712 ps
CPU time	2.5 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:38 PM PDT 24
Peak memory	207024 kb
Host	smart-da3d76ef-7ab9-43ae-8333-f787e7bd5256
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20097 71738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2009771738
Directory	/workspace/2.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/2.usbdev_streaming_out.3747140298
Short name	T958
Test name
Test status
Simulation time	1494958961 ps
CPU time	14.69 seconds
Started	Aug 01 06:11:24 PM PDT 24
Finished	Aug 01 06:11:39 PM PDT 24
Peak memory	223472 kb
Host	smart-fbf6b6dc-2144-41b9-8344-fbdfeecff7dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37471 40298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.3747140298
Directory	/workspace/2.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.3111375723
Short name	T141
Test name
Test status
Simulation time	4976786080 ps
CPU time	35.84 seconds
Started	Aug 01 06:11:21 PM PDT 24
Finished	Aug 01 06:11:57 PM PDT 24
Peak memory	207120 kb
Host	smart-b91b4d4d-9cf8-48d7-a69d-70ab7d41bac8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111375723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host _handshake.3111375723
Directory	/workspace/2.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/20.usbdev_alert_test.939461668
Short name	T743
Test name
Test status
Simulation time	91865289 ps
CPU time	0.72 seconds
Started	Aug 01 06:15:26 PM PDT 24
Finished	Aug 01 06:15:27 PM PDT 24
Peak memory	206960 kb
Host	smart-c354a7e5-abe1-455a-8884-e59ba014df2b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=939461668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.939461668
Directory	/workspace/20.usbdev_alert_test/latest

Test location	/workspace/coverage/default/20.usbdev_av_buffer.3047603157
Short name	T1385
Test name
Test status
Simulation time	147331471 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:16 PM PDT 24
Peak memory	206944 kb
Host	smart-5d9223be-e82a-4014-ab62-ed5650326142
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30476 03157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.3047603157
Directory	/workspace/20.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/20.usbdev_bitstuff_err.3048319753
Short name	T2749
Test name
Test status
Simulation time	144407676 ps
CPU time	0.85 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206860 kb
Host	smart-6ef612e7-5021-4484-83cf-c8713cab954a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30483 19753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3048319753
Directory	/workspace/20.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/20.usbdev_data_toggle_clear.3844984897
Short name	T1485
Test name
Test status
Simulation time	358323405 ps
CPU time	1.33 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:17 PM PDT 24
Peak memory	206988 kb
Host	smart-a6310c0b-f3e3-4b33-ad89-8141ad73d243
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38449 84897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3844984897
Directory	/workspace/20.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/20.usbdev_data_toggle_restore.1865094265
Short name	T1699
Test name
Test status
Simulation time	338612391 ps
CPU time	1.16 seconds
Started	Aug 01 06:15:16 PM PDT 24
Finished	Aug 01 06:15:18 PM PDT 24
Peak memory	206904 kb
Host	smart-9e153db3-648b-42f5-be20-31e4232c1b95
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1865094265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1865094265
Directory	/workspace/20.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/20.usbdev_device_address.748658297
Short name	T1446
Test name
Test status
Simulation time	19368468786 ps
CPU time	31.29 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:47 PM PDT 24
Peak memory	207168 kb
Host	smart-8cfc343e-324b-454d-bc92-0749b1ff7d64
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74865 8297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.748658297
Directory	/workspace/20.usbdev_device_address/latest

Test location	/workspace/coverage/default/20.usbdev_device_timeout.887853185
Short name	T1313
Test name
Test status
Simulation time	837637644 ps
CPU time	5.45 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:20 PM PDT 24
Peak memory	207120 kb
Host	smart-94a346ba-9ce8-47a2-aa8d-f4fe7fd9daeb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887853185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.887853185
Directory	/workspace/20.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/20.usbdev_disable_endpoint.2250158146
Short name	T1874
Test name
Test status
Simulation time	627259897 ps
CPU time	1.57 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206896 kb
Host	smart-4a8c2f51-f391-4f35-a160-6023d171bc54
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22501 58146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2250158146
Directory	/workspace/20.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/20.usbdev_disconnected.155585753
Short name	T1493
Test name
Test status
Simulation time	136516145 ps
CPU time	0.85 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:16 PM PDT 24
Peak memory	206944 kb
Host	smart-2b1acd84-a73d-4c57-a607-8b24cb89c472
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15558 5753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.155585753
Directory	/workspace/20.usbdev_disconnected/latest

Test location	/workspace/coverage/default/20.usbdev_enable.2452295556
Short name	T2310
Test name
Test status
Simulation time	39062646 ps
CPU time	0.69 seconds
Started	Aug 01 06:15:12 PM PDT 24
Finished	Aug 01 06:15:13 PM PDT 24
Peak memory	206904 kb
Host	smart-76e446a7-e985-418c-acfa-400f2881de7b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24522 95556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.2452295556
Directory	/workspace/20.usbdev_enable/latest

Test location	/workspace/coverage/default/20.usbdev_endpoint_access.2862466852
Short name	T1819
Test name
Test status
Simulation time	713361744 ps
CPU time	2.05 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:16 PM PDT 24
Peak memory	207108 kb
Host	smart-c0dcb901-1a13-479c-867f-68a8a7562cce
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28624 66852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.2862466852
Directory	/workspace/20.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/20.usbdev_endpoint_types.381351916
Short name	T1593
Test name
Test status
Simulation time	164811435 ps
CPU time	0.91 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:16 PM PDT 24
Peak memory	206936 kb
Host	smart-60f3d3d7-ba29-4387-9b77-c50d377a9f6a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=381351916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.381351916
Directory	/workspace/20.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/20.usbdev_fifo_rst.3885404914
Short name	T1089
Test name
Test status
Simulation time	172205765 ps
CPU time	1.56 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:17 PM PDT 24
Peak memory	207080 kb
Host	smart-114e2159-8439-4070-983a-b3c64b60bfe7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38854 04914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3885404914
Directory	/workspace/20.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/20.usbdev_in_iso.60047094
Short name	T1623
Test name
Test status
Simulation time	152513979 ps
CPU time	0.9 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:16 PM PDT 24
Peak memory	206876 kb
Host	smart-42e569cf-5031-41db-88e1-8222cceaff42
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=60047094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.60047094
Directory	/workspace/20.usbdev_in_iso/latest

Test location	/workspace/coverage/default/20.usbdev_in_stall.3020642499
Short name	T750
Test name
Test status
Simulation time	163694178 ps
CPU time	0.89 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:16 PM PDT 24
Peak memory	206912 kb
Host	smart-d0fad6ce-7078-4344-b05f-eaaf41b7c6ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30206 42499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.3020642499
Directory	/workspace/20.usbdev_in_stall/latest

Test location	/workspace/coverage/default/20.usbdev_in_trans.3773122600
Short name	T2479
Test name
Test status
Simulation time	161361733 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206820 kb
Host	smart-afd090a2-5c94-47f7-8220-68ca51499a97
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37731 22600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.3773122600
Directory	/workspace/20.usbdev_in_trans/latest

Test location	/workspace/coverage/default/20.usbdev_invalid_sync.4008991690
Short name	T1126
Test name
Test status
Simulation time	5183267622 ps
CPU time	151.02 seconds
Started	Aug 01 06:15:16 PM PDT 24
Finished	Aug 01 06:17:48 PM PDT 24
Peak memory	217700 kb
Host	smart-2a597ded-479e-499c-b4af-ffc38fe52f6d
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4008991690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.4008991690
Directory	/workspace/20.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/20.usbdev_iso_retraction.1103560448
Short name	T1985
Test name
Test status
Simulation time	9074071228 ps
CPU time	109.54 seconds
Started	Aug 01 06:15:17 PM PDT 24
Finished	Aug 01 06:17:07 PM PDT 24
Peak memory	207164 kb
Host	smart-95e3ff84-5c6e-4663-a387-2ce60ca1d825
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1103560448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.1103560448
Directory	/workspace/20.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/20.usbdev_link_in_err.3040896720
Short name	T1486
Test name
Test status
Simulation time	199428735 ps
CPU time	0.86 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206948 kb
Host	smart-879cab17-8246-4fee-9c0e-4ba8f89262c7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30408 96720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3040896720
Directory	/workspace/20.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/20.usbdev_link_suspend.2281546802
Short name	T88
Test name
Test status
Simulation time	5924049494 ps
CPU time	8 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:23 PM PDT 24
Peak memory	207344 kb
Host	smart-19b6dda1-dfa6-4f80-875f-168058a46a81
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22815 46802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2281546802
Directory	/workspace/20.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/20.usbdev_low_speed_traffic.1367381854
Short name	T2358
Test name
Test status
Simulation time	4447054407 ps
CPU time	42.89 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:58 PM PDT 24
Peak memory	217264 kb
Host	smart-bcabc7f4-9c50-4ef6-b71c-a2f21a36f24d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13673 81854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.1367381854
Directory	/workspace/20.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2396690618
Short name	T1942
Test name
Test status
Simulation time	2387451063 ps
CPU time	68.29 seconds
Started	Aug 01 06:15:11 PM PDT 24
Finished	Aug 01 06:16:19 PM PDT 24
Peak memory	216688 kb
Host	smart-9973e8d3-2b6c-437e-bf74-2f2eefacdacc
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2396690618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2396690618
Directory	/workspace/20.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/20.usbdev_max_length_in_transaction.3819604914
Short name	T2082
Test name
Test status
Simulation time	251182852 ps
CPU time	1.01 seconds
Started	Aug 01 06:15:18 PM PDT 24
Finished	Aug 01 06:15:19 PM PDT 24
Peak memory	206956 kb
Host	smart-e7a79e2e-8413-4b30-9a87-b7c38e1273e4
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3819604914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.3819604914
Directory	/workspace/20.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/20.usbdev_max_length_out_transaction.624404927
Short name	T86
Test name
Test status
Simulation time	232410586 ps
CPU time	0.99 seconds
Started	Aug 01 06:15:13 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	206980 kb
Host	smart-90205d23-c952-4beb-ab03-717aa068c52d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62440 4927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.624404927
Directory	/workspace/20.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.10414540
Short name	T2718
Test name
Test status
Simulation time	1577029127 ps
CPU time	42.66 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:58 PM PDT 24
Peak memory	215328 kb
Host	smart-56d852ce-0f74-44df-8b1f-69f1847f3209
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10414 540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.10414540
Directory	/workspace/20.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/20.usbdev_min_inter_pkt_delay.831107958
Short name	T2266
Test name
Test status
Simulation time	3138797568 ps
CPU time	24.98 seconds
Started	Aug 01 06:15:15 PM PDT 24
Finished	Aug 01 06:15:40 PM PDT 24
Peak memory	215348 kb
Host	smart-4e8be347-8590-4b03-976a-776968072f9c
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=831107958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.831107958
Directory	/workspace/20.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/20.usbdev_min_length_in_transaction.900945350
Short name	T2166
Test name
Test status
Simulation time	163035486 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	206944 kb
Host	smart-57214d21-ada8-46da-a65b-66941420ca8d
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=900945350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.900945350
Directory	/workspace/20.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/20.usbdev_min_length_out_transaction.3403216645
Short name	T593
Test name
Test status
Simulation time	138040963 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	206976 kb
Host	smart-c317f99e-33f8-40a8-b926-2aab9381ff83
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34032 16645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3403216645
Directory	/workspace/20.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/20.usbdev_out_iso.3458751796
Short name	T980
Test name
Test status
Simulation time	150870617 ps
CPU time	0.92 seconds
Started	Aug 01 06:15:26 PM PDT 24
Finished	Aug 01 06:15:27 PM PDT 24
Peak memory	206880 kb
Host	smart-7018f2cc-7ea3-4e58-b304-17928bc0c0c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34587 51796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3458751796
Directory	/workspace/20.usbdev_out_iso/latest

Test location	/workspace/coverage/default/20.usbdev_out_stall.2921729501
Short name	T1240
Test name
Test status
Simulation time	174462381 ps
CPU time	0.86 seconds
Started	Aug 01 06:15:25 PM PDT 24
Finished	Aug 01 06:15:26 PM PDT 24
Peak memory	206948 kb
Host	smart-0b8181a3-87ac-4798-9599-5bf403601939
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29217 29501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2921729501
Directory	/workspace/20.usbdev_out_stall/latest

Test location	/workspace/coverage/default/20.usbdev_out_trans_nak.3905874104
Short name	T2487
Test name
Test status
Simulation time	227631737 ps
CPU time	0.9 seconds
Started	Aug 01 06:15:31 PM PDT 24
Finished	Aug 01 06:15:32 PM PDT 24
Peak memory	206952 kb
Host	smart-5d5b1510-cbd1-4d19-a6ef-6cdc8b7281c4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39058 74104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3905874104
Directory	/workspace/20.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/20.usbdev_pending_in_trans.1953361661
Short name	T1756
Test name
Test status
Simulation time	147694341 ps
CPU time	0.86 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	206964 kb
Host	smart-b5aba95b-79a3-4a07-bea4-ac15692a18e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19533 61661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.1953361661
Directory	/workspace/20.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/20.usbdev_phy_config_pinflip.2144835577
Short name	T1100
Test name
Test status
Simulation time	192304612 ps
CPU time	0.99 seconds
Started	Aug 01 06:15:24 PM PDT 24
Finished	Aug 01 06:15:25 PM PDT 24
Peak memory	206952 kb
Host	smart-d6aa91db-e7a4-432a-a841-2e37c7673baa
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2144835577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2144835577
Directory	/workspace/20.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3061466374
Short name	T2648
Test name
Test status
Simulation time	181146644 ps
CPU time	0.83 seconds
Started	Aug 01 06:15:26 PM PDT 24
Finished	Aug 01 06:15:27 PM PDT 24
Peak memory	206892 kb
Host	smart-fe719f8a-201a-462d-8c76-db86586a395e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30614 66374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3061466374
Directory	/workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/20.usbdev_phy_pins_sense.1358791194
Short name	T2064
Test name
Test status
Simulation time	51270407 ps
CPU time	0.72 seconds
Started	Aug 01 06:15:26 PM PDT 24
Finished	Aug 01 06:15:27 PM PDT 24
Peak memory	206884 kb
Host	smart-48a30a2b-48b9-4ded-b776-f7d8a1ba345b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13587 91194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1358791194
Directory	/workspace/20.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/20.usbdev_pkt_buffer.3698920896
Short name	T2103
Test name
Test status
Simulation time	16254369772 ps
CPU time	39.11 seconds
Started	Aug 01 06:15:26 PM PDT 24
Finished	Aug 01 06:16:05 PM PDT 24
Peak memory	215360 kb
Host	smart-97d8b319-ef2c-4775-b8fd-2e128da81218
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989 20896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3698920896
Directory	/workspace/20.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/20.usbdev_pkt_received.963933588
Short name	T2232
Test name
Test status
Simulation time	155034387 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	206936 kb
Host	smart-d973f5ee-5084-4c96-8141-fcdb7d346929
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96393 3588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.963933588
Directory	/workspace/20.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/20.usbdev_pkt_sent.104172255
Short name	T597
Test name
Test status
Simulation time	186910403 ps
CPU time	0.95 seconds
Started	Aug 01 06:15:24 PM PDT 24
Finished	Aug 01 06:15:25 PM PDT 24
Peak memory	206880 kb
Host	smart-ddf9ce7a-2b38-4db3-9314-b5d11ee5dc97
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10417 2255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.104172255
Directory	/workspace/20.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/20.usbdev_random_length_in_transaction.3255391414
Short name	T1433
Test name
Test status
Simulation time	211150985 ps
CPU time	0.94 seconds
Started	Aug 01 06:15:27 PM PDT 24
Finished	Aug 01 06:15:28 PM PDT 24
Peak memory	206952 kb
Host	smart-b98e6631-d79c-4321-bfdb-75c686b138f5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32553 91414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3255391414
Directory	/workspace/20.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/20.usbdev_random_length_out_transaction.3939558726
Short name	T1520
Test name
Test status
Simulation time	167701875 ps
CPU time	0.89 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	206956 kb
Host	smart-1b085e86-e28f-4bac-9813-aee3e4e53a37
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39395 58726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.3939558726
Directory	/workspace/20.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/20.usbdev_rx_crc_err.354862633
Short name	T940
Test name
Test status
Simulation time	166689483 ps
CPU time	0.86 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:15:29 PM PDT 24
Peak memory	206928 kb
Host	smart-45d04aee-875c-4333-bb6e-d2117a4cacf4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35486 2633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.354862633
Directory	/workspace/20.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/20.usbdev_rx_full.1232121510
Short name	T283
Test name
Test status
Simulation time	380720961 ps
CPU time	1.41 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	206932 kb
Host	smart-21f6698c-e116-47c9-9665-0bd932d79137
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321 21510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.1232121510
Directory	/workspace/20.usbdev_rx_full/latest

Test location	/workspace/coverage/default/20.usbdev_setup_stage.1498083693
Short name	T1310
Test name
Test status
Simulation time	147723075 ps
CPU time	0.83 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:15:29 PM PDT 24
Peak memory	206900 kb
Host	smart-3f2446b3-ec00-4d72-b7a1-29594a8b0209
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14980 83693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1498083693
Directory	/workspace/20.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/20.usbdev_setup_trans_ignored.3850952201
Short name	T2234
Test name
Test status
Simulation time	172831037 ps
CPU time	0.92 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	206956 kb
Host	smart-57494929-5f78-4645-b754-49d0ac1de54e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38509 52201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3850952201
Directory	/workspace/20.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/20.usbdev_smoke.3860125674
Short name	T1677
Test name
Test status
Simulation time	248404138 ps
CPU time	1.07 seconds
Started	Aug 01 06:15:33 PM PDT 24
Finished	Aug 01 06:15:34 PM PDT 24
Peak memory	206956 kb
Host	smart-e1eb1053-48e8-4672-afa5-92b8465ac589
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38601 25674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.3860125674
Directory	/workspace/20.usbdev_smoke/latest

Test location	/workspace/coverage/default/20.usbdev_spurious_pids_ignored.3352112111
Short name	T1280
Test name
Test status
Simulation time	2240926509 ps
CPU time	64.14 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:16:35 PM PDT 24
Peak memory	216904 kb
Host	smart-78533c20-b9aa-4fee-bd91-5bc6ab81b08e
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3352112111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.3352112111
Directory	/workspace/20.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/20.usbdev_stall_priority_over_nak.1656937267
Short name	T848
Test name
Test status
Simulation time	159888881 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:25 PM PDT 24
Finished	Aug 01 06:15:26 PM PDT 24
Peak memory	206960 kb
Host	smart-d079d452-7ce6-48f1-a898-06d46f28aeb5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16569 37267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.1656937267
Directory	/workspace/20.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/20.usbdev_stall_trans.1136173754
Short name	T594
Test name
Test status
Simulation time	216730986 ps
CPU time	0.96 seconds
Started	Aug 01 06:15:31 PM PDT 24
Finished	Aug 01 06:15:32 PM PDT 24
Peak memory	206940 kb
Host	smart-2e2d30ae-fba4-4d4e-903d-22c32547b923
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11361 73754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1136173754
Directory	/workspace/20.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/20.usbdev_stream_len_max.163399290
Short name	T1909
Test name
Test status
Simulation time	411255380 ps
CPU time	1.25 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:15:29 PM PDT 24
Peak memory	206924 kb
Host	smart-2e63dd3d-1e4a-463e-b51d-ef5467d43715
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16339 9290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.163399290
Directory	/workspace/20.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/20.usbdev_streaming_out.2244188329
Short name	T2848
Test name
Test status
Simulation time	3459321680 ps
CPU time	34.35 seconds
Started	Aug 01 06:15:26 PM PDT 24
Finished	Aug 01 06:16:01 PM PDT 24
Peak memory	215348 kb
Host	smart-074ab03e-3616-4f6e-95e9-81644e9513dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22441 88329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2244188329
Directory	/workspace/20.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.3157369600
Short name	T1954
Test name
Test status
Simulation time	287892213 ps
CPU time	4.46 seconds
Started	Aug 01 06:15:14 PM PDT 24
Finished	Aug 01 06:15:20 PM PDT 24
Peak memory	207148 kb
Host	smart-819529d2-fbc1-4997-a852-3a431aadeebb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157369600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_hos t_handshake.3157369600
Directory	/workspace/20.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/21.usbdev_alert_test.2451231440
Short name	T1993
Test name
Test status
Simulation time	42993448 ps
CPU time	0.68 seconds
Started	Aug 01 06:15:34 PM PDT 24
Finished	Aug 01 06:15:35 PM PDT 24
Peak memory	206992 kb
Host	smart-2c9195b5-f3e6-4b25-a490-846cc1064e19
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2451231440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.2451231440
Directory	/workspace/21.usbdev_alert_test/latest

Test location	/workspace/coverage/default/21.usbdev_av_buffer.90796204
Short name	T2486
Test name
Test status
Simulation time	201052323 ps
CPU time	0.9 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:15:29 PM PDT 24
Peak memory	206984 kb
Host	smart-dce10592-62fb-4fc4-b994-6b00e3c208a2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90796 204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.90796204
Directory	/workspace/21.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/21.usbdev_bitstuff_err.1024883564
Short name	T1983
Test name
Test status
Simulation time	226463986 ps
CPU time	1 seconds
Started	Aug 01 06:15:32 PM PDT 24
Finished	Aug 01 06:15:33 PM PDT 24
Peak memory	206912 kb
Host	smart-4fed9ba5-b127-4df5-a3a0-23ce467e1c95
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10248 83564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.1024883564
Directory	/workspace/21.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/21.usbdev_data_toggle_clear.2119355027
Short name	T2126
Test name
Test status
Simulation time	308243202 ps
CPU time	1.25 seconds
Started	Aug 01 06:15:27 PM PDT 24
Finished	Aug 01 06:15:28 PM PDT 24
Peak memory	206928 kb
Host	smart-103a4be8-b749-40de-9db5-f2b9ac550d74
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21193 55027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2119355027
Directory	/workspace/21.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/21.usbdev_data_toggle_restore.2311455388
Short name	T765
Test name
Test status
Simulation time	622132700 ps
CPU time	1.93 seconds
Started	Aug 01 06:15:31 PM PDT 24
Finished	Aug 01 06:15:33 PM PDT 24
Peak memory	206956 kb
Host	smart-425d5dd1-f146-487c-a9f7-205ab82251d3
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2311455388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2311455388
Directory	/workspace/21.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/21.usbdev_device_address.1038566629
Short name	T458
Test name
Test status
Simulation time	17488561675 ps
CPU time	27.95 seconds
Started	Aug 01 06:15:27 PM PDT 24
Finished	Aug 01 06:15:55 PM PDT 24
Peak memory	207156 kb
Host	smart-221807e7-e7c4-40c9-934d-ce74178b97fb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10385 66629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.1038566629
Directory	/workspace/21.usbdev_device_address/latest

Test location	/workspace/coverage/default/21.usbdev_device_timeout.2787287206
Short name	T1666
Test name
Test status
Simulation time	1949623636 ps
CPU time	46.97 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:16:18 PM PDT 24
Peak memory	207116 kb
Host	smart-9d4e49e8-9859-4c0b-b84a-b47bfd2bdc04
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787287206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.2787287206
Directory	/workspace/21.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/21.usbdev_disable_endpoint.2823924896
Short name	T1925
Test name
Test status
Simulation time	634087145 ps
CPU time	1.54 seconds
Started	Aug 01 06:15:31 PM PDT 24
Finished	Aug 01 06:15:33 PM PDT 24
Peak memory	207156 kb
Host	smart-a47517e7-7fa3-4049-8a50-1a8375e8630c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28239 24896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2823924896
Directory	/workspace/21.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/21.usbdev_disconnected.1998100933
Short name	T2009
Test name
Test status
Simulation time	188723569 ps
CPU time	0.9 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	207128 kb
Host	smart-37e1e37f-123c-4daf-9a55-3aef1e97f35f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19981 00933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1998100933
Directory	/workspace/21.usbdev_disconnected/latest

Test location	/workspace/coverage/default/21.usbdev_enable.3964668841
Short name	T1632
Test name
Test status
Simulation time	38948281 ps
CPU time	0.7 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	206952 kb
Host	smart-360ba887-d59a-43bb-ac6c-971dd1b1ba8d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39646 68841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3964668841
Directory	/workspace/21.usbdev_enable/latest

Test location	/workspace/coverage/default/21.usbdev_endpoint_access.1009248334
Short name	T1070
Test name
Test status
Simulation time	874870339 ps
CPU time	2.15 seconds
Started	Aug 01 06:15:31 PM PDT 24
Finished	Aug 01 06:15:34 PM PDT 24
Peak memory	207196 kb
Host	smart-3ba3471b-8b53-4422-963b-59c2fc0dd9b6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10092 48334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1009248334
Directory	/workspace/21.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/21.usbdev_endpoint_types.4205656330
Short name	T412
Test name
Test status
Simulation time	470610442 ps
CPU time	1.41 seconds
Started	Aug 01 06:15:24 PM PDT 24
Finished	Aug 01 06:15:26 PM PDT 24
Peak memory	206916 kb
Host	smart-66d31729-1a1f-4752-8f69-ad6dd3cd56bf
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4205656330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.4205656330
Directory	/workspace/21.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/21.usbdev_fifo_rst.777358320
Short name	T1432
Test name
Test status
Simulation time	241982047 ps
CPU time	1.67 seconds
Started	Aug 01 06:15:31 PM PDT 24
Finished	Aug 01 06:15:33 PM PDT 24
Peak memory	207076 kb
Host	smart-bd37b184-0d6b-4a14-8c57-8a5259d90857
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77735 8320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.777358320
Directory	/workspace/21.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/21.usbdev_in_iso.3909713391
Short name	T807
Test name
Test status
Simulation time	238842071 ps
CPU time	1.14 seconds
Started	Aug 01 06:15:32 PM PDT 24
Finished	Aug 01 06:15:33 PM PDT 24
Peak memory	215328 kb
Host	smart-9e7a5a43-e125-492b-802d-5af2bbaa5415
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3909713391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3909713391
Directory	/workspace/21.usbdev_in_iso/latest

Test location	/workspace/coverage/default/21.usbdev_in_stall.2227397043
Short name	T801
Test name
Test status
Simulation time	162716138 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	206972 kb
Host	smart-4a772b76-96fc-485c-9198-7352b09a38e4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22273 97043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2227397043
Directory	/workspace/21.usbdev_in_stall/latest

Test location	/workspace/coverage/default/21.usbdev_in_trans.2941187659
Short name	T2165
Test name
Test status
Simulation time	193948990 ps
CPU time	0.92 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	206960 kb
Host	smart-7263840b-a491-4427-b3e4-cc89ab5d1c93
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29411 87659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2941187659
Directory	/workspace/21.usbdev_in_trans/latest

Test location	/workspace/coverage/default/21.usbdev_invalid_sync.1438032664
Short name	T2673
Test name
Test status
Simulation time	2695521266 ps
CPU time	73.51 seconds
Started	Aug 01 06:15:31 PM PDT 24
Finished	Aug 01 06:16:45 PM PDT 24
Peak memory	215416 kb
Host	smart-70c88de7-d787-4cfd-bbe0-82f2b0da4e46
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1438032664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1438032664
Directory	/workspace/21.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/21.usbdev_iso_retraction.3173609157
Short name	T2412
Test name
Test status
Simulation time	4546180168 ps
CPU time	49.39 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:16:19 PM PDT 24
Peak memory	207148 kb
Host	smart-505cdad2-0f3a-4f5a-8afd-f3b8a2a875c4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3173609157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.3173609157
Directory	/workspace/21.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/21.usbdev_link_in_err.432767927
Short name	T1010
Test name
Test status
Simulation time	208116035 ps
CPU time	0.93 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	206912 kb
Host	smart-c235551e-f8e6-4fee-82f5-6b60542b3268
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43276 7927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.432767927
Directory	/workspace/21.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/21.usbdev_link_suspend.3175243716
Short name	T2142
Test name
Test status
Simulation time	10264884500 ps
CPU time	13.78 seconds
Started	Aug 01 06:15:33 PM PDT 24
Finished	Aug 01 06:15:47 PM PDT 24
Peak memory	206396 kb
Host	smart-53188cce-fd1a-4819-9e7e-d76ec790ba3e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31752 43716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3175243716
Directory	/workspace/21.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/21.usbdev_low_speed_traffic.3180687701
Short name	T1082
Test name
Test status
Simulation time	5475186506 ps
CPU time	43.27 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:16:12 PM PDT 24
Peak memory	223548 kb
Host	smart-cc1a95bf-6ead-489b-a54f-231eecaf004d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31806 87701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.3180687701
Directory	/workspace/21.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2441495772
Short name	T673
Test name
Test status
Simulation time	2212895077 ps
CPU time	16.7 seconds
Started	Aug 01 06:15:27 PM PDT 24
Finished	Aug 01 06:15:44 PM PDT 24
Peak memory	223472 kb
Host	smart-a82b7cfe-8cce-4c05-94a2-bd21a68a1fa6
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2441495772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2441495772
Directory	/workspace/21.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/21.usbdev_max_length_in_transaction.3341910764
Short name	T1743
Test name
Test status
Simulation time	248018716 ps
CPU time	1.02 seconds
Started	Aug 01 06:15:27 PM PDT 24
Finished	Aug 01 06:15:28 PM PDT 24
Peak memory	206924 kb
Host	smart-76824980-b810-4682-873a-fa7897e5e93d
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3341910764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3341910764
Directory	/workspace/21.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/21.usbdev_max_length_out_transaction.1760751797
Short name	T2743
Test name
Test status
Simulation time	223983764 ps
CPU time	0.97 seconds
Started	Aug 01 06:15:25 PM PDT 24
Finished	Aug 01 06:15:27 PM PDT 24
Peak memory	206948 kb
Host	smart-0066cc65-a5ff-4466-85f5-6e55a7337d79
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17607 51797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1760751797
Directory	/workspace/21.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.3774535842
Short name	T1631
Test name
Test status
Simulation time	3423384134 ps
CPU time	98.02 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:17:09 PM PDT 24
Peak memory	223580 kb
Host	smart-8239ec7f-c663-4b44-9c4c-ea9fd27d2897
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37745 35842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.3774535842
Directory	/workspace/21.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/21.usbdev_min_inter_pkt_delay.844180615
Short name	T2043
Test name
Test status
Simulation time	1636889139 ps
CPU time	12.87 seconds
Started	Aug 01 06:15:26 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	215240 kb
Host	smart-635a96de-d68f-491f-b6b9-230f8198115b
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=844180615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.844180615
Directory	/workspace/21.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/21.usbdev_min_length_in_transaction.1668996684
Short name	T1406
Test name
Test status
Simulation time	163668375 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	207008 kb
Host	smart-366c588b-7b70-4588-b51a-94c400297e63
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1668996684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1668996684
Directory	/workspace/21.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/21.usbdev_min_length_out_transaction.4284213212
Short name	T2490
Test name
Test status
Simulation time	155787066 ps
CPU time	0.89 seconds
Started	Aug 01 06:15:25 PM PDT 24
Finished	Aug 01 06:15:26 PM PDT 24
Peak memory	206972 kb
Host	smart-4a1a32ac-10d5-4380-8bf5-76162b3f0b14
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42842 13212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.4284213212
Directory	/workspace/21.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/21.usbdev_out_iso.1036483641
Short name	T1733
Test name
Test status
Simulation time	182311983 ps
CPU time	0.97 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	206912 kb
Host	smart-3885809b-923c-464b-95c4-5664ddf9ba4c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10364 83641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1036483641
Directory	/workspace/21.usbdev_out_iso/latest

Test location	/workspace/coverage/default/21.usbdev_out_stall.1283363626
Short name	T614
Test name
Test status
Simulation time	160999447 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:32 PM PDT 24
Peak memory	207008 kb
Host	smart-17b0f5bd-a2b3-495c-ba99-d8e43a3ad8dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12833 63626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1283363626
Directory	/workspace/21.usbdev_out_stall/latest

Test location	/workspace/coverage/default/21.usbdev_out_trans_nak.2667835116
Short name	T1130
Test name
Test status
Simulation time	170338876 ps
CPU time	0.91 seconds
Started	Aug 01 06:15:32 PM PDT 24
Finished	Aug 01 06:15:33 PM PDT 24
Peak memory	206944 kb
Host	smart-44e7bfed-d2ba-4cc1-b67c-e82f491bb728
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26678 35116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.2667835116
Directory	/workspace/21.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/21.usbdev_pending_in_trans.1114961542
Short name	T2035
Test name
Test status
Simulation time	181753231 ps
CPU time	0.94 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:30 PM PDT 24
Peak memory	206960 kb
Host	smart-ecd6c407-9e85-4915-97f6-c20217b08af8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11149 61542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1114961542
Directory	/workspace/21.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/21.usbdev_phy_config_pinflip.2918364949
Short name	T1305
Test name
Test status
Simulation time	183019669 ps
CPU time	0.95 seconds
Started	Aug 01 06:15:31 PM PDT 24
Finished	Aug 01 06:15:32 PM PDT 24
Peak memory	206952 kb
Host	smart-dead3ef0-22a3-4ba1-829d-166180fb4f5a
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2918364949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2918364949
Directory	/workspace/21.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1382798017
Short name	T1554
Test name
Test status
Simulation time	180350448 ps
CPU time	0.92 seconds
Started	Aug 01 06:15:33 PM PDT 24
Finished	Aug 01 06:15:35 PM PDT 24
Peak memory	206856 kb
Host	smart-8bc93c3c-73aa-49dc-bb2c-657ffd21f55f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13827 98017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1382798017
Directory	/workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/21.usbdev_phy_pins_sense.1620223366
Short name	T989
Test name
Test status
Simulation time	30396453 ps
CPU time	0.66 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:15:28 PM PDT 24
Peak memory	206916 kb
Host	smart-2860dc8c-3ffa-47f4-bcea-aef66b5a3c18
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16202 23366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1620223366
Directory	/workspace/21.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/21.usbdev_pkt_buffer.3876770616
Short name	T669
Test name
Test status
Simulation time	7867942012 ps
CPU time	22.5 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:53 PM PDT 24
Peak memory	215328 kb
Host	smart-79012887-0bb2-4cc0-8df9-7163ad63ef51
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38767 70616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3876770616
Directory	/workspace/21.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/21.usbdev_pkt_received.3929013641
Short name	T741
Test name
Test status
Simulation time	161015471 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:15:29 PM PDT 24
Peak memory	206952 kb
Host	smart-855c2b38-96ab-4b8f-9408-f746466ec44d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39290 13641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3929013641
Directory	/workspace/21.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/21.usbdev_pkt_sent.2067622665
Short name	T739
Test name
Test status
Simulation time	269611972 ps
CPU time	1.06 seconds
Started	Aug 01 06:15:24 PM PDT 24
Finished	Aug 01 06:15:25 PM PDT 24
Peak memory	206960 kb
Host	smart-6f1d3e31-1954-46d6-a699-0ec8a0d0035d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20676 22665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2067622665
Directory	/workspace/21.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/21.usbdev_random_length_in_transaction.4267903198
Short name	T2194
Test name
Test status
Simulation time	181218007 ps
CPU time	0.94 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	207192 kb
Host	smart-0f30a564-5038-4d59-94ff-28926457a09f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42679 03198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.4267903198
Directory	/workspace/21.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/21.usbdev_random_length_out_transaction.2362618644
Short name	T1688
Test name
Test status
Simulation time	160467678 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:33 PM PDT 24
Finished	Aug 01 06:15:34 PM PDT 24
Peak memory	206944 kb
Host	smart-f98514bf-c28c-4cb6-ad09-cacb6d3dba2d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23626 18644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.2362618644
Directory	/workspace/21.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/21.usbdev_rx_crc_err.1048410512
Short name	T644
Test name
Test status
Simulation time	163829376 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:34 PM PDT 24
Finished	Aug 01 06:15:35 PM PDT 24
Peak memory	206960 kb
Host	smart-73e6b66f-51ae-4a84-be77-2ff753e40fa6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484 10512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1048410512
Directory	/workspace/21.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/21.usbdev_rx_full.3145950077
Short name	T2778
Test name
Test status
Simulation time	339129609 ps
CPU time	1.3 seconds
Started	Aug 01 06:15:33 PM PDT 24
Finished	Aug 01 06:15:34 PM PDT 24
Peak memory	206860 kb
Host	smart-740bfd7d-d045-4b2f-83dd-cc98efbf1291
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31459 50077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.3145950077
Directory	/workspace/21.usbdev_rx_full/latest

Test location	/workspace/coverage/default/21.usbdev_setup_stage.1248954982
Short name	T1594
Test name
Test status
Simulation time	192868903 ps
CPU time	0.9 seconds
Started	Aug 01 06:15:33 PM PDT 24
Finished	Aug 01 06:15:34 PM PDT 24
Peak memory	206220 kb
Host	smart-2bbd9ba2-95ec-44e8-894a-fff89fd72594
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12489 54982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1248954982
Directory	/workspace/21.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/21.usbdev_setup_trans_ignored.2475420431
Short name	T1992
Test name
Test status
Simulation time	174407599 ps
CPU time	0.89 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:15:29 PM PDT 24
Peak memory	206956 kb
Host	smart-d749f22c-2883-4e72-b2fb-b04714f78fec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754 20431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2475420431
Directory	/workspace/21.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/21.usbdev_smoke.1495147953
Short name	T2741
Test name
Test status
Simulation time	283356687 ps
CPU time	1.15 seconds
Started	Aug 01 06:15:31 PM PDT 24
Finished	Aug 01 06:15:32 PM PDT 24
Peak memory	206908 kb
Host	smart-61ca971b-23a3-4473-af14-bc466dce9241
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14951 47953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1495147953
Directory	/workspace/21.usbdev_smoke/latest

Test location	/workspace/coverage/default/21.usbdev_spurious_pids_ignored.3000585652
Short name	T1571
Test name
Test status
Simulation time	2421434123 ps
CPU time	16.56 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:47 PM PDT 24
Peak memory	207156 kb
Host	smart-4ae7ca46-c63f-467b-b256-76854016919c
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3000585652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3000585652
Directory	/workspace/21.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/21.usbdev_stall_priority_over_nak.292279948
Short name	T1933
Test name
Test status
Simulation time	178735548 ps
CPU time	0.92 seconds
Started	Aug 01 06:15:28 PM PDT 24
Finished	Aug 01 06:15:29 PM PDT 24
Peak memory	206960 kb
Host	smart-1b6bd92c-6848-4b58-bcb2-4ad88280ca0d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29227 9948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.292279948
Directory	/workspace/21.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/21.usbdev_stall_trans.247606992
Short name	T2404
Test name
Test status
Simulation time	218421901 ps
CPU time	0.99 seconds
Started	Aug 01 06:15:29 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	206896 kb
Host	smart-1ba4d3cb-d97b-491b-97ca-8d98f7da8320
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24760 6992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.247606992
Directory	/workspace/21.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/21.usbdev_stream_len_max.179733442
Short name	T1085
Test name
Test status
Simulation time	625855376 ps
CPU time	1.88 seconds
Started	Aug 01 06:15:33 PM PDT 24
Finished	Aug 01 06:15:35 PM PDT 24
Peak memory	206900 kb
Host	smart-8b29a834-4d98-41f8-84d5-b054cfaf0a8d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17973 3442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.179733442
Directory	/workspace/21.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/21.usbdev_streaming_out.1625558518
Short name	T2736
Test name
Test status
Simulation time	3493971319 ps
CPU time	102.47 seconds
Started	Aug 01 06:15:34 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	216836 kb
Host	smart-e6207198-98f1-4990-bf73-190ef7e3ffa4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16255 58518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.1625558518
Directory	/workspace/21.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.879900109
Short name	T832
Test name
Test status
Simulation time	838208511 ps
CPU time	5.59 seconds
Started	Aug 01 06:15:32 PM PDT 24
Finished	Aug 01 06:15:38 PM PDT 24
Peak memory	207064 kb
Host	smart-26842f2b-0664-4eac-900d-e3775ee0de81
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879900109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_host _handshake.879900109
Directory	/workspace/21.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/22.usbdev_alert_test.1995513062
Short name	T780
Test name
Test status
Simulation time	59230012 ps
CPU time	0.7 seconds
Started	Aug 01 06:15:42 PM PDT 24
Finished	Aug 01 06:15:43 PM PDT 24
Peak memory	206972 kb
Host	smart-3854de52-9c70-47e7-9e39-1a0e15ed1325
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1995513062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1995513062
Directory	/workspace/22.usbdev_alert_test/latest

Test location	/workspace/coverage/default/22.usbdev_av_buffer.2505812809
Short name	T2220
Test name
Test status
Simulation time	155835447 ps
CPU time	0.92 seconds
Started	Aug 01 06:15:30 PM PDT 24
Finished	Aug 01 06:15:31 PM PDT 24
Peak memory	206920 kb
Host	smart-1a9e50d1-2275-4288-a6b4-1b0dcd0df456
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058 12809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2505812809
Directory	/workspace/22.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/22.usbdev_bitstuff_err.2519567910
Short name	T2668
Test name
Test status
Simulation time	214116416 ps
CPU time	0.94 seconds
Started	Aug 01 06:15:34 PM PDT 24
Finished	Aug 01 06:15:35 PM PDT 24
Peak memory	206912 kb
Host	smart-2e76ffde-f050-44da-ad9a-e94a0c3ec56a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25195 67910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2519567910
Directory	/workspace/22.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/22.usbdev_data_toggle_clear.775112893
Short name	T1723
Test name
Test status
Simulation time	488534180 ps
CPU time	1.7 seconds
Started	Aug 01 06:15:33 PM PDT 24
Finished	Aug 01 06:15:35 PM PDT 24
Peak memory	206968 kb
Host	smart-68f046bd-ed9e-41bf-a8f1-66e165b94535
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77511 2893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.775112893
Directory	/workspace/22.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/22.usbdev_data_toggle_restore.1198992714
Short name	T945
Test name
Test status
Simulation time	444265520 ps
CPU time	1.39 seconds
Started	Aug 01 06:15:35 PM PDT 24
Finished	Aug 01 06:15:37 PM PDT 24
Peak memory	206960 kb
Host	smart-8dd2c218-7a6a-4b33-b68d-1d12f3198eec
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1198992714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1198992714
Directory	/workspace/22.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/22.usbdev_device_address.828452222
Short name	T2425
Test name
Test status
Simulation time	18330953425 ps
CPU time	30.47 seconds
Started	Aug 01 06:15:33 PM PDT 24
Finished	Aug 01 06:16:04 PM PDT 24
Peak memory	207156 kb
Host	smart-24fe2791-019a-4122-aa0a-2749f5ea1e3d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82845 2222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.828452222
Directory	/workspace/22.usbdev_device_address/latest

Test location	/workspace/coverage/default/22.usbdev_device_timeout.4245192136
Short name	T957
Test name
Test status
Simulation time	2918936562 ps
CPU time	26.22 seconds
Started	Aug 01 06:15:35 PM PDT 24
Finished	Aug 01 06:16:02 PM PDT 24
Peak memory	207172 kb
Host	smart-8c8202e7-7977-4057-a3fa-fbe03af8fd98
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245192136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.4245192136
Directory	/workspace/22.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/22.usbdev_disable_endpoint.3409745356
Short name	T1437
Test name
Test status
Simulation time	928888838 ps
CPU time	1.94 seconds
Started	Aug 01 06:15:37 PM PDT 24
Finished	Aug 01 06:15:40 PM PDT 24
Peak memory	206940 kb
Host	smart-a22cc25f-bf80-4f55-9651-74c02b8ad6cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097 45356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3409745356
Directory	/workspace/22.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/22.usbdev_enable.1982320564
Short name	T2045
Test name
Test status
Simulation time	48643181 ps
CPU time	0.7 seconds
Started	Aug 01 06:15:44 PM PDT 24
Finished	Aug 01 06:15:45 PM PDT 24
Peak memory	206920 kb
Host	smart-a5e9311f-d6df-4486-8831-cc7b46bb5f81
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19823 20564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1982320564
Directory	/workspace/22.usbdev_enable/latest

Test location	/workspace/coverage/default/22.usbdev_endpoint_access.138941605
Short name	T759
Test name
Test status
Simulation time	679422095 ps
CPU time	2 seconds
Started	Aug 01 06:15:44 PM PDT 24
Finished	Aug 01 06:15:46 PM PDT 24
Peak memory	207168 kb
Host	smart-5d84f4a4-7d7b-44f2-ae09-e308c99d190f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13894 1605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.138941605
Directory	/workspace/22.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/22.usbdev_endpoint_types.1570676603
Short name	T2575
Test name
Test status
Simulation time	465489052 ps
CPU time	1.35 seconds
Started	Aug 01 06:15:39 PM PDT 24
Finished	Aug 01 06:15:41 PM PDT 24
Peak memory	206872 kb
Host	smart-4297bb88-7862-48ca-a9ff-c6451c8e9e6b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1570676603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.1570676603
Directory	/workspace/22.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/22.usbdev_fifo_rst.1423457424
Short name	T1054
Test name
Test status
Simulation time	257146196 ps
CPU time	1.93 seconds
Started	Aug 01 06:15:40 PM PDT 24
Finished	Aug 01 06:15:42 PM PDT 24
Peak memory	207132 kb
Host	smart-b9c40107-9483-4b57-9cd8-c66daae101cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14234 57424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1423457424
Directory	/workspace/22.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/22.usbdev_in_iso.1197566236
Short name	T710
Test name
Test status
Simulation time	196749482 ps
CPU time	1.01 seconds
Started	Aug 01 06:15:37 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	207120 kb
Host	smart-ef457703-cf4d-430b-98ca-4fb24d114c66
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1197566236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1197566236
Directory	/workspace/22.usbdev_in_iso/latest

Test location	/workspace/coverage/default/22.usbdev_in_stall.3334298296
Short name	T2692
Test name
Test status
Simulation time	143816899 ps
CPU time	0.83 seconds
Started	Aug 01 06:15:37 PM PDT 24
Finished	Aug 01 06:15:38 PM PDT 24
Peak memory	206972 kb
Host	smart-6123b0ff-0b94-438a-9592-26aebdf196ab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33342 98296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3334298296
Directory	/workspace/22.usbdev_in_stall/latest

Test location	/workspace/coverage/default/22.usbdev_in_trans.4104100401
Short name	T2227
Test name
Test status
Simulation time	301737970 ps
CPU time	1.09 seconds
Started	Aug 01 06:16:01 PM PDT 24
Finished	Aug 01 06:16:02 PM PDT 24
Peak memory	206952 kb
Host	smart-2c833b18-44ef-468e-80d7-38ac0f1652c1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41041 00401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.4104100401
Directory	/workspace/22.usbdev_in_trans/latest

Test location	/workspace/coverage/default/22.usbdev_invalid_sync.1493989127
Short name	T1438
Test name
Test status
Simulation time	4467257934 ps
CPU time	46.51 seconds
Started	Aug 01 06:15:36 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	217200 kb
Host	smart-39ee7d44-1f13-476a-b012-00337acf2c8e
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1493989127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1493989127
Directory	/workspace/22.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/22.usbdev_iso_retraction.2412468456
Short name	T1914
Test name
Test status
Simulation time	9945850785 ps
CPU time	74.71 seconds
Started	Aug 01 06:15:36 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	207112 kb
Host	smart-0e2baf1f-f3ea-4040-ac61-6ac340a2762c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2412468456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.2412468456
Directory	/workspace/22.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/22.usbdev_link_in_err.3056540014
Short name	T1165
Test name
Test status
Simulation time	296817725 ps
CPU time	1.05 seconds
Started	Aug 01 06:15:45 PM PDT 24
Finished	Aug 01 06:15:46 PM PDT 24
Peak memory	206948 kb
Host	smart-c66b64e7-cbe6-464d-8f43-87886420c63b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30565 40014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3056540014
Directory	/workspace/22.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/22.usbdev_link_suspend.1926295725
Short name	T2356
Test name
Test status
Simulation time	6013786252 ps
CPU time	7.82 seconds
Started	Aug 01 06:15:41 PM PDT 24
Finished	Aug 01 06:15:49 PM PDT 24
Peak memory	215432 kb
Host	smart-4be0b404-0b10-48fa-a28d-e50fc7108033
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19262 95725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1926295725
Directory	/workspace/22.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/22.usbdev_low_speed_traffic.3845715198
Short name	T287
Test name
Test status
Simulation time	3262298683 ps
CPU time	25.46 seconds
Started	Aug 01 06:15:39 PM PDT 24
Finished	Aug 01 06:16:04 PM PDT 24
Peak memory	217456 kb
Host	smart-99829325-552d-458b-9f3f-b7632ece7f50
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38457 15198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.3845715198
Directory	/workspace/22.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1771082643
Short name	T1373
Test name
Test status
Simulation time	2588261376 ps
CPU time	27.8 seconds
Started	Aug 01 06:15:38 PM PDT 24
Finished	Aug 01 06:16:06 PM PDT 24
Peak memory	215396 kb
Host	smart-4edd7ea6-8c65-4ca8-9ecd-8f70ceb0f53c
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1771082643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1771082643
Directory	/workspace/22.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/22.usbdev_max_length_in_transaction.4248100004
Short name	T570
Test name
Test status
Simulation time	258567778 ps
CPU time	1.12 seconds
Started	Aug 01 06:15:38 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	206884 kb
Host	smart-771ab2a5-adbb-4674-9b40-4e44e3d541b0
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=4248100004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.4248100004
Directory	/workspace/22.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/22.usbdev_max_length_out_transaction.714658934
Short name	T1455
Test name
Test status
Simulation time	191851250 ps
CPU time	0.94 seconds
Started	Aug 01 06:15:37 PM PDT 24
Finished	Aug 01 06:15:38 PM PDT 24
Peak memory	206952 kb
Host	smart-df79fef2-d482-4956-9281-8d3138828c9c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71465 8934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.714658934
Directory	/workspace/22.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.742618315
Short name	T2074
Test name
Test status
Simulation time	1871006461 ps
CPU time	14.07 seconds
Started	Aug 01 06:15:41 PM PDT 24
Finished	Aug 01 06:15:55 PM PDT 24
Peak memory	223412 kb
Host	smart-64977f0e-f26f-4c88-ab3b-7d0890fc9d7a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74261 8315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.742618315
Directory	/workspace/22.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/22.usbdev_min_inter_pkt_delay.904984087
Short name	T2513
Test name
Test status
Simulation time	2025001759 ps
CPU time	14.7 seconds
Started	Aug 01 06:15:37 PM PDT 24
Finished	Aug 01 06:15:52 PM PDT 24
Peak memory	215264 kb
Host	smart-e69f0ca0-52c2-45f0-b280-fc7d91587185
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=904984087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.904984087
Directory	/workspace/22.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/22.usbdev_min_length_in_transaction.3710039603
Short name	T1870
Test name
Test status
Simulation time	157607645 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:39 PM PDT 24
Finished	Aug 01 06:15:40 PM PDT 24
Peak memory	206956 kb
Host	smart-3d79f120-7253-4377-b7bf-62344eb03968
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3710039603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.3710039603
Directory	/workspace/22.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/22.usbdev_min_length_out_transaction.247892175
Short name	T2676
Test name
Test status
Simulation time	162800275 ps
CPU time	0.9 seconds
Started	Aug 01 06:15:35 PM PDT 24
Finished	Aug 01 06:15:36 PM PDT 24
Peak memory	206976 kb
Host	smart-8d66b066-eb7c-42e4-9afd-af1bb6078585
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24789 2175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.247892175
Directory	/workspace/22.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/22.usbdev_nak_trans.677385343
Short name	T188
Test name
Test status
Simulation time	216928775 ps
CPU time	0.99 seconds
Started	Aug 01 06:15:38 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	206948 kb
Host	smart-b51744ff-0d17-4811-8dbd-06e0c01bf60e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67738 5343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.677385343
Directory	/workspace/22.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/22.usbdev_out_iso.2287466883
Short name	T1141
Test name
Test status
Simulation time	174047447 ps
CPU time	0.91 seconds
Started	Aug 01 06:15:39 PM PDT 24
Finished	Aug 01 06:15:40 PM PDT 24
Peak memory	206896 kb
Host	smart-76499671-4a3d-4a46-bba8-0569ca34b9a0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22874 66883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2287466883
Directory	/workspace/22.usbdev_out_iso/latest

Test location	/workspace/coverage/default/22.usbdev_out_stall.1042454888
Short name	T1796
Test name
Test status
Simulation time	188937379 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:43 PM PDT 24
Finished	Aug 01 06:15:44 PM PDT 24
Peak memory	206972 kb
Host	smart-eef008f4-8851-4153-adb5-ad2039e8bc6c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10424 54888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1042454888
Directory	/workspace/22.usbdev_out_stall/latest

Test location	/workspace/coverage/default/22.usbdev_out_trans_nak.2253217650
Short name	T1347
Test name
Test status
Simulation time	176864097 ps
CPU time	0.86 seconds
Started	Aug 01 06:15:41 PM PDT 24
Finished	Aug 01 06:15:42 PM PDT 24
Peak memory	206924 kb
Host	smart-2d149895-4ec4-4528-8b17-dd68fcf8274c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22532 17650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2253217650
Directory	/workspace/22.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/22.usbdev_pending_in_trans.2495478786
Short name	T2727
Test name
Test status
Simulation time	254760834 ps
CPU time	0.98 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:49 PM PDT 24
Peak memory	206920 kb
Host	smart-08f1bdf7-8729-4450-98a1-b2bb17c1ce2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24954 78786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2495478786
Directory	/workspace/22.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/22.usbdev_phy_config_pinflip.1813392763
Short name	T1682
Test name
Test status
Simulation time	249010375 ps
CPU time	1.07 seconds
Started	Aug 01 06:15:41 PM PDT 24
Finished	Aug 01 06:15:42 PM PDT 24
Peak memory	206960 kb
Host	smart-d1267861-5dae-4c8a-87de-0130f98cab23
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1813392763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1813392763
Directory	/workspace/22.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3044425373
Short name	T609
Test name
Test status
Simulation time	190579904 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:38 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	206916 kb
Host	smart-e7544385-1238-4a12-8813-a3a1b3a963a4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30444 25373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3044425373
Directory	/workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/22.usbdev_phy_pins_sense.541467777
Short name	T1237
Test name
Test status
Simulation time	42604941 ps
CPU time	0.72 seconds
Started	Aug 01 06:15:40 PM PDT 24
Finished	Aug 01 06:15:41 PM PDT 24
Peak memory	206912 kb
Host	smart-a1caa2c0-e0ca-4a92-bbd5-1fa29cdd8a22
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54146 7777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.541467777
Directory	/workspace/22.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/22.usbdev_pkt_buffer.3805114397
Short name	T1862
Test name
Test status
Simulation time	10951166772 ps
CPU time	27.88 seconds
Started	Aug 01 06:15:38 PM PDT 24
Finished	Aug 01 06:16:06 PM PDT 24
Peak memory	223628 kb
Host	smart-95782a61-7df9-4d16-838b-0c11500e99d7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38051 14397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3805114397
Directory	/workspace/22.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/22.usbdev_pkt_received.1730558557
Short name	T2550
Test name
Test status
Simulation time	197808203 ps
CPU time	0.92 seconds
Started	Aug 01 06:15:37 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	206952 kb
Host	smart-22a55178-b7a2-4c61-bc66-cf73b6f1f8e1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17305 58557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1730558557
Directory	/workspace/22.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/22.usbdev_pkt_sent.2040231684
Short name	T1915
Test name
Test status
Simulation time	222227402 ps
CPU time	0.93 seconds
Started	Aug 01 06:15:38 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	206944 kb
Host	smart-8f77db1b-5c15-43a6-ab30-df299ae4c8c7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20402 31684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2040231684
Directory	/workspace/22.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/22.usbdev_random_length_in_transaction.1476716919
Short name	T1203
Test name
Test status
Simulation time	228621194 ps
CPU time	1 seconds
Started	Aug 01 06:15:36 PM PDT 24
Finished	Aug 01 06:15:37 PM PDT 24
Peak memory	206908 kb
Host	smart-fef9e977-fe0d-407e-9f8d-67895a2a0377
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14767 16919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.1476716919
Directory	/workspace/22.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/22.usbdev_random_length_out_transaction.997328666
Short name	T85
Test name
Test status
Simulation time	149421119 ps
CPU time	0.83 seconds
Started	Aug 01 06:15:43 PM PDT 24
Finished	Aug 01 06:15:43 PM PDT 24
Peak memory	206952 kb
Host	smart-6f4fcd91-f6e4-4df0-b4b9-acc95ea00b51
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99732 8666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.997328666
Directory	/workspace/22.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/22.usbdev_rx_crc_err.1161902784
Short name	T895
Test name
Test status
Simulation time	220272600 ps
CPU time	0.94 seconds
Started	Aug 01 06:15:38 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	206900 kb
Host	smart-5de0c149-65f7-49b1-835b-0f772adeecc0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11619 02784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1161902784
Directory	/workspace/22.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/22.usbdev_rx_full.2499857376
Short name	T955
Test name
Test status
Simulation time	277382341 ps
CPU time	1.13 seconds
Started	Aug 01 06:15:42 PM PDT 24
Finished	Aug 01 06:15:43 PM PDT 24
Peak memory	206944 kb
Host	smart-afa78e14-1caf-4188-b96d-ce5e43d1bac6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24998 57376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.2499857376
Directory	/workspace/22.usbdev_rx_full/latest

Test location	/workspace/coverage/default/22.usbdev_setup_stage.2209481146
Short name	T13
Test name
Test status
Simulation time	152059499 ps
CPU time	0.83 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:49 PM PDT 24
Peak memory	206864 kb
Host	smart-50aca9d2-0d71-4693-b55b-59c4931b6f00
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22094 81146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2209481146
Directory	/workspace/22.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/22.usbdev_setup_trans_ignored.1712744521
Short name	T154
Test name
Test status
Simulation time	144996723 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:43 PM PDT 24
Finished	Aug 01 06:15:44 PM PDT 24
Peak memory	206948 kb
Host	smart-a42a5392-9196-4ad8-8feb-89ac572c7d15
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17127 44521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1712744521
Directory	/workspace/22.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/22.usbdev_smoke.1047926578
Short name	T1323
Test name
Test status
Simulation time	247269606 ps
CPU time	1.1 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:49 PM PDT 24
Peak memory	206904 kb
Host	smart-1d146006-d51e-41a0-888a-97b741ec51b8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10479 26578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.1047926578
Directory	/workspace/22.usbdev_smoke/latest

Test location	/workspace/coverage/default/22.usbdev_spurious_pids_ignored.530095703
Short name	T1672
Test name
Test status
Simulation time	2336404764 ps
CPU time	17.31 seconds
Started	Aug 01 06:15:36 PM PDT 24
Finished	Aug 01 06:15:54 PM PDT 24
Peak memory	207152 kb
Host	smart-e510fe0e-adde-4027-8f27-66ac6110adf0
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=530095703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.530095703
Directory	/workspace/22.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/22.usbdev_stall_priority_over_nak.4265995237
Short name	T727
Test name
Test status
Simulation time	165103775 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:41 PM PDT 24
Finished	Aug 01 06:15:42 PM PDT 24
Peak memory	206956 kb
Host	smart-9c842bc0-314b-46dc-ad2c-ed51510dbf9b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42659 95237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.4265995237
Directory	/workspace/22.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/22.usbdev_stall_trans.328741912
Short name	T1039
Test name
Test status
Simulation time	185434162 ps
CPU time	0.89 seconds
Started	Aug 01 06:15:40 PM PDT 24
Finished	Aug 01 06:15:41 PM PDT 24
Peak memory	206952 kb
Host	smart-36c3f9df-f21c-43cd-a631-b3b65acb398b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32874 1912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.328741912
Directory	/workspace/22.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/22.usbdev_stream_len_max.2942227590
Short name	T2094
Test name
Test status
Simulation time	1080478494 ps
CPU time	2.76 seconds
Started	Aug 01 06:15:39 PM PDT 24
Finished	Aug 01 06:15:42 PM PDT 24
Peak memory	207028 kb
Host	smart-40f10cda-8c06-41ad-90a3-f17d8c5679f7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29422 27590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.2942227590
Directory	/workspace/22.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/22.usbdev_streaming_out.3640069249
Short name	T1292
Test name
Test status
Simulation time	2390346015 ps
CPU time	22.46 seconds
Started	Aug 01 06:15:44 PM PDT 24
Finished	Aug 01 06:16:06 PM PDT 24
Peak memory	217064 kb
Host	smart-bb1b9852-4be5-42fa-bf9a-81bda3970099
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36400 69249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3640069249
Directory	/workspace/22.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.4174290161
Short name	T2168
Test name
Test status
Simulation time	1548599601 ps
CPU time	9.38 seconds
Started	Aug 01 06:15:32 PM PDT 24
Finished	Aug 01 06:15:42 PM PDT 24
Peak memory	207140 kb
Host	smart-0ccfdd40-7b02-4c34-89cb-0a4df8848a04
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174290161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_hos t_handshake.4174290161
Directory	/workspace/22.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/23.usbdev_alert_test.1400723478
Short name	T2423
Test name
Test status
Simulation time	49507916 ps
CPU time	0.7 seconds
Started	Aug 01 06:15:52 PM PDT 24
Finished	Aug 01 06:15:53 PM PDT 24
Peak memory	206996 kb
Host	smart-0d648bf2-fea3-48ba-8068-dae4a8686f59
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1400723478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1400723478
Directory	/workspace/23.usbdev_alert_test/latest

Test location	/workspace/coverage/default/23.usbdev_av_buffer.495198851
Short name	T1701
Test name
Test status
Simulation time	158641932 ps
CPU time	0.82 seconds
Started	Aug 01 06:15:49 PM PDT 24
Finished	Aug 01 06:15:50 PM PDT 24
Peak memory	206972 kb
Host	smart-03fd9619-cb3a-4d5b-a727-9ccabe40df53
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49519 8851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.495198851
Directory	/workspace/23.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/23.usbdev_bitstuff_err.3257486374
Short name	T2046
Test name
Test status
Simulation time	145842432 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:38 PM PDT 24
Finished	Aug 01 06:15:39 PM PDT 24
Peak memory	206920 kb
Host	smart-eb6c2395-0097-41c1-9c01-c4708100ab96
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32574 86374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3257486374
Directory	/workspace/23.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/23.usbdev_data_toggle_clear.4238074530
Short name	T1669
Test name
Test status
Simulation time	467959284 ps
CPU time	1.57 seconds
Started	Aug 01 06:15:44 PM PDT 24
Finished	Aug 01 06:15:46 PM PDT 24
Peak memory	206948 kb
Host	smart-21739dad-7ebf-4890-821d-b70ba06ae14e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380 74530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.4238074530
Directory	/workspace/23.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/23.usbdev_data_toggle_restore.3919611597
Short name	T2669
Test name
Test status
Simulation time	1107672925 ps
CPU time	2.88 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:51 PM PDT 24
Peak memory	207076 kb
Host	smart-c6917399-a5a6-4153-a152-f9e19160a0f2
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3919611597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.3919611597
Directory	/workspace/23.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/23.usbdev_device_address.2343668870
Short name	T454
Test name
Test status
Simulation time	34426982257 ps
CPU time	51.59 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:16:40 PM PDT 24
Peak memory	207128 kb
Host	smart-c25be9d9-f89d-4726-8c83-cab525b0582e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23436 68870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2343668870
Directory	/workspace/23.usbdev_device_address/latest

Test location	/workspace/coverage/default/23.usbdev_device_timeout.2822999062
Short name	T1659
Test name
Test status
Simulation time	5008832596 ps
CPU time	30.59 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:16:18 PM PDT 24
Peak memory	207100 kb
Host	smart-378cdd1f-f3c9-4fc8-aec8-6f5448207f62
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822999062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.2822999062
Directory	/workspace/23.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/23.usbdev_disable_endpoint.1535788708
Short name	T2294
Test name
Test status
Simulation time	889539962 ps
CPU time	2.15 seconds
Started	Aug 01 06:15:43 PM PDT 24
Finished	Aug 01 06:15:45 PM PDT 24
Peak memory	206932 kb
Host	smart-78127a43-255d-4e73-871c-5145b3a1a7a2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15357 88708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.1535788708
Directory	/workspace/23.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/23.usbdev_disconnected.26393661
Short name	T1580
Test name
Test status
Simulation time	135509636 ps
CPU time	0.8 seconds
Started	Aug 01 06:15:41 PM PDT 24
Finished	Aug 01 06:15:42 PM PDT 24
Peak memory	206888 kb
Host	smart-1fd64044-9606-44e8-ba4d-d89ec3552636
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26393 661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.26393661
Directory	/workspace/23.usbdev_disconnected/latest

Test location	/workspace/coverage/default/23.usbdev_enable.2830125279
Short name	T598
Test name
Test status
Simulation time	56887802 ps
CPU time	0.71 seconds
Started	Aug 01 06:15:43 PM PDT 24
Finished	Aug 01 06:15:44 PM PDT 24
Peak memory	206908 kb
Host	smart-458f7a65-352a-4738-997c-50db72d67167
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28301 25279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2830125279
Directory	/workspace/23.usbdev_enable/latest

Test location	/workspace/coverage/default/23.usbdev_endpoint_access.2514272185
Short name	T2831
Test name
Test status
Simulation time	917571263 ps
CPU time	2.54 seconds
Started	Aug 01 06:15:43 PM PDT 24
Finished	Aug 01 06:15:46 PM PDT 24
Peak memory	207124 kb
Host	smart-52fa1605-fcba-4026-a6c9-eff658e53da1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25142 72185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.2514272185
Directory	/workspace/23.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/23.usbdev_endpoint_types.2756696415
Short name	T2454
Test name
Test status
Simulation time	424853410 ps
CPU time	1.25 seconds
Started	Aug 01 06:15:43 PM PDT 24
Finished	Aug 01 06:15:44 PM PDT 24
Peak memory	206924 kb
Host	smart-51d6b251-47c1-4090-9b04-90b871abe7ee
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2756696415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.2756696415
Directory	/workspace/23.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/23.usbdev_fifo_rst.1514441217
Short name	T569
Test name
Test status
Simulation time	271837158 ps
CPU time	2.24 seconds
Started	Aug 01 06:15:40 PM PDT 24
Finished	Aug 01 06:15:43 PM PDT 24
Peak memory	207152 kb
Host	smart-72c9b34d-c6b3-42f4-8703-6af26b703a05
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15144 41217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.1514441217
Directory	/workspace/23.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/23.usbdev_in_iso.622244768
Short name	T2643
Test name
Test status
Simulation time	170653159 ps
CPU time	0.96 seconds
Started	Aug 01 06:15:37 PM PDT 24
Finished	Aug 01 06:15:38 PM PDT 24
Peak memory	206964 kb
Host	smart-c3611399-2a2e-4d1f-8b76-ad1205e8c12a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=622244768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.622244768
Directory	/workspace/23.usbdev_in_iso/latest

Test location	/workspace/coverage/default/23.usbdev_in_stall.598132120
Short name	T822
Test name
Test status
Simulation time	140528580 ps
CPU time	0.82 seconds
Started	Aug 01 06:15:40 PM PDT 24
Finished	Aug 01 06:15:41 PM PDT 24
Peak memory	206928 kb
Host	smart-fa6c9d15-3eb2-4672-a636-c97c524acb12
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59813 2120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.598132120
Directory	/workspace/23.usbdev_in_stall/latest

Test location	/workspace/coverage/default/23.usbdev_in_trans.351349807
Short name	T915
Test name
Test status
Simulation time	178595649 ps
CPU time	0.95 seconds
Started	Aug 01 06:15:37 PM PDT 24
Finished	Aug 01 06:15:38 PM PDT 24
Peak memory	206944 kb
Host	smart-48852452-1748-4206-b3b7-e51ee2fc2e75
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35134 9807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.351349807
Directory	/workspace/23.usbdev_in_trans/latest

Test location	/workspace/coverage/default/23.usbdev_invalid_sync.2710454488
Short name	T2612
Test name
Test status
Simulation time	2309377246 ps
CPU time	22.81 seconds
Started	Aug 01 06:15:44 PM PDT 24
Finished	Aug 01 06:16:07 PM PDT 24
Peak memory	217180 kb
Host	smart-f881ca86-662b-4889-95ac-e58afd126330
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2710454488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.2710454488
Directory	/workspace/23.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/23.usbdev_iso_retraction.1719761686
Short name	T2524
Test name
Test status
Simulation time	6402726199 ps
CPU time	70.5 seconds
Started	Aug 01 06:15:40 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	207156 kb
Host	smart-324a4c7a-16a0-402d-b9c1-8adee934d33c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1719761686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.1719761686
Directory	/workspace/23.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/23.usbdev_link_in_err.1622555331
Short name	T2849
Test name
Test status
Simulation time	156526003 ps
CPU time	0.85 seconds
Started	Aug 01 06:15:40 PM PDT 24
Finished	Aug 01 06:15:41 PM PDT 24
Peak memory	206920 kb
Host	smart-6f3f4640-b693-4a54-a2a4-fa96980fc50c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16225 55331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.1622555331
Directory	/workspace/23.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/23.usbdev_link_suspend.1987463116
Short name	T2306
Test name
Test status
Simulation time	10853976840 ps
CPU time	13.37 seconds
Started	Aug 01 06:15:40 PM PDT 24
Finished	Aug 01 06:15:54 PM PDT 24
Peak memory	207164 kb
Host	smart-564cbecf-96ad-4e0b-892b-68ac56e60cb6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19874 63116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.1987463116
Directory	/workspace/23.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/23.usbdev_low_speed_traffic.3901359644
Short name	T1248
Test name
Test status
Simulation time	5430226485 ps
CPU time	40.11 seconds
Started	Aug 01 06:15:40 PM PDT 24
Finished	Aug 01 06:16:21 PM PDT 24
Peak memory	223580 kb
Host	smart-ae9e4605-4433-4df8-b012-9023179bbdb5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39013 59644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3901359644
Directory	/workspace/23.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/23.usbdev_max_inter_pkt_delay.858311652
Short name	T2456
Test name
Test status
Simulation time	3142514566 ps
CPU time	23.46 seconds
Started	Aug 01 06:16:02 PM PDT 24
Finished	Aug 01 06:16:26 PM PDT 24
Peak memory	207128 kb
Host	smart-41b2d693-b0ee-4276-9b5d-7592503865b2
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=858311652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.858311652
Directory	/workspace/23.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/23.usbdev_max_length_in_transaction.647224099
Short name	T1268
Test name
Test status
Simulation time	252733538 ps
CPU time	0.98 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:50 PM PDT 24
Peak memory	206908 kb
Host	smart-b47e8da1-00af-46be-aa07-a21b5801a243
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=647224099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.647224099
Directory	/workspace/23.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/23.usbdev_max_length_out_transaction.830907366
Short name	T1322
Test name
Test status
Simulation time	212831698 ps
CPU time	0.95 seconds
Started	Aug 01 06:15:51 PM PDT 24
Finished	Aug 01 06:15:52 PM PDT 24
Peak memory	206980 kb
Host	smart-797732c4-039e-45ae-9b38-0f49170748d5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83090 7366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.830907366
Directory	/workspace/23.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.3422172668
Short name	T547
Test name
Test status
Simulation time	3100025043 ps
CPU time	23.75 seconds
Started	Aug 01 06:15:56 PM PDT 24
Finished	Aug 01 06:16:20 PM PDT 24
Peak memory	223536 kb
Host	smart-af23b632-ee65-46fa-bb9b-de4921a0ee9e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34221 72668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.3422172668
Directory	/workspace/23.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/23.usbdev_min_inter_pkt_delay.3325884648
Short name	T1664
Test name
Test status
Simulation time	3012024492 ps
CPU time	84.67 seconds
Started	Aug 01 06:15:51 PM PDT 24
Finished	Aug 01 06:17:16 PM PDT 24
Peak memory	216824 kb
Host	smart-9bf2e98a-6612-40f8-8d27-baf2d3591ece
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3325884648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.3325884648
Directory	/workspace/23.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/23.usbdev_min_length_in_transaction.2931319151
Short name	T1551
Test name
Test status
Simulation time	158488878 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:45 PM PDT 24
Finished	Aug 01 06:15:46 PM PDT 24
Peak memory	206904 kb
Host	smart-9d9c18c6-01b2-40a1-ad82-e87a93ca027f
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2931319151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2931319151
Directory	/workspace/23.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/23.usbdev_min_length_out_transaction.853991630
Short name	T2642
Test name
Test status
Simulation time	160292431 ps
CPU time	0.92 seconds
Started	Aug 01 06:15:52 PM PDT 24
Finished	Aug 01 06:15:53 PM PDT 24
Peak memory	206988 kb
Host	smart-784fbe32-ff12-452f-8158-00841e7cdf38
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85399 1630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.853991630
Directory	/workspace/23.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/23.usbdev_nak_trans.2737814297
Short name	T185
Test name
Test status
Simulation time	214267834 ps
CPU time	0.97 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:50 PM PDT 24
Peak memory	206928 kb
Host	smart-7a3bb9b7-618c-497d-be48-69cc5b7d7e4a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27378 14297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2737814297
Directory	/workspace/23.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/23.usbdev_out_iso.2473035533
Short name	T2806
Test name
Test status
Simulation time	188589377 ps
CPU time	0.91 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:15:59 PM PDT 24
Peak memory	206968 kb
Host	smart-9c599fe8-ad1e-4b95-bfd7-ef279ce4648a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24730 35533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2473035533
Directory	/workspace/23.usbdev_out_iso/latest

Test location	/workspace/coverage/default/23.usbdev_out_stall.2528454432
Short name	T2757
Test name
Test status
Simulation time	206968767 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:49 PM PDT 24
Peak memory	206968 kb
Host	smart-e7940bb0-94f7-419f-8181-da80d2bef7f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25284 54432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2528454432
Directory	/workspace/23.usbdev_out_stall/latest

Test location	/workspace/coverage/default/23.usbdev_out_trans_nak.3594040426
Short name	T2419
Test name
Test status
Simulation time	205995615 ps
CPU time	1.05 seconds
Started	Aug 01 06:15:51 PM PDT 24
Finished	Aug 01 06:15:52 PM PDT 24
Peak memory	206960 kb
Host	smart-d910774c-3223-4b66-aacc-212404076ba9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35940 40426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3594040426
Directory	/workspace/23.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/23.usbdev_pending_in_trans.1728619831
Short name	T1094
Test name
Test status
Simulation time	162465968 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:49 PM PDT 24
Finished	Aug 01 06:15:50 PM PDT 24
Peak memory	206940 kb
Host	smart-f6a5e933-5e29-4f17-8810-5abcaa36a525
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17286 19831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.1728619831
Directory	/workspace/23.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/23.usbdev_phy_config_pinflip.3326790369
Short name	T2058
Test name
Test status
Simulation time	276530602 ps
CPU time	1.1 seconds
Started	Aug 01 06:15:56 PM PDT 24
Finished	Aug 01 06:15:57 PM PDT 24
Peak memory	206952 kb
Host	smart-5493882f-e9d5-4613-8dd5-c5cdb006f4df
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3326790369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3326790369
Directory	/workspace/23.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1319904975
Short name	T873
Test name
Test status
Simulation time	161982156 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:49 PM PDT 24
Peak memory	206892 kb
Host	smart-d8c6795d-898a-4e20-8844-d7041ac5d425
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13199 04975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1319904975
Directory	/workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/23.usbdev_phy_pins_sense.273735532
Short name	T1713
Test name
Test status
Simulation time	39068900 ps
CPU time	0.66 seconds
Started	Aug 01 06:15:46 PM PDT 24
Finished	Aug 01 06:15:47 PM PDT 24
Peak memory	206908 kb
Host	smart-90a0160d-e4b6-4b07-bb69-650076a9b73c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27373 5532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.273735532
Directory	/workspace/23.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/23.usbdev_pkt_buffer.3010638892
Short name	T2565
Test name
Test status
Simulation time	6288957206 ps
CPU time	17.45 seconds
Started	Aug 01 06:15:55 PM PDT 24
Finished	Aug 01 06:16:13 PM PDT 24
Peak memory	215332 kb
Host	smart-159c17c7-3408-4640-8709-c9536b02ad4d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30106 38892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.3010638892
Directory	/workspace/23.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/23.usbdev_pkt_received.1902391579
Short name	T2318
Test name
Test status
Simulation time	166791097 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:49 PM PDT 24
Peak memory	206948 kb
Host	smart-84901d18-0c39-4037-8fc1-74dda4c27b2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19023 91579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.1902391579
Directory	/workspace/23.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/23.usbdev_pkt_sent.2923151368
Short name	T1910
Test name
Test status
Simulation time	219437287 ps
CPU time	0.99 seconds
Started	Aug 01 06:15:53 PM PDT 24
Finished	Aug 01 06:15:55 PM PDT 24
Peak memory	206960 kb
Host	smart-67853c9a-d92a-4e70-a1f2-b25abb6b3bba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29231 51368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2923151368
Directory	/workspace/23.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/23.usbdev_random_length_in_transaction.4137550505
Short name	T1967
Test name
Test status
Simulation time	148841571 ps
CPU time	0.84 seconds
Started	Aug 01 06:15:52 PM PDT 24
Finished	Aug 01 06:15:53 PM PDT 24
Peak memory	206968 kb
Host	smart-217e5a40-c901-4288-a6f4-3b520e6021e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41375 50505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.4137550505
Directory	/workspace/23.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/23.usbdev_random_length_out_transaction.3977464195
Short name	T2764
Test name
Test status
Simulation time	161044559 ps
CPU time	0.91 seconds
Started	Aug 01 06:15:56 PM PDT 24
Finished	Aug 01 06:15:57 PM PDT 24
Peak memory	206944 kb
Host	smart-e65d044c-f560-41dc-be15-9a2059ab34d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39774 64195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3977464195
Directory	/workspace/23.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/23.usbdev_rx_crc_err.1918862446
Short name	T1801
Test name
Test status
Simulation time	202880508 ps
CPU time	0.86 seconds
Started	Aug 01 06:15:47 PM PDT 24
Finished	Aug 01 06:15:48 PM PDT 24
Peak memory	206900 kb
Host	smart-cef499c4-2637-42a1-8a38-62b202801fde
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19188 62446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1918862446
Directory	/workspace/23.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/23.usbdev_rx_full.136990918
Short name	T1045
Test name
Test status
Simulation time	365598840 ps
CPU time	1.25 seconds
Started	Aug 01 06:15:46 PM PDT 24
Finished	Aug 01 06:15:47 PM PDT 24
Peak memory	206932 kb
Host	smart-22d8eade-226d-48d2-bc34-76ef26cd8fd4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13699 0918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.136990918
Directory	/workspace/23.usbdev_rx_full/latest

Test location	/workspace/coverage/default/23.usbdev_setup_stage.4234759521
Short name	T551
Test name
Test status
Simulation time	158775562 ps
CPU time	0.86 seconds
Started	Aug 01 06:15:53 PM PDT 24
Finished	Aug 01 06:15:54 PM PDT 24
Peak memory	206872 kb
Host	smart-651858b3-78a4-469b-bb95-39b06b3ba60d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42347 59521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.4234759521
Directory	/workspace/23.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/23.usbdev_setup_trans_ignored.2545498880
Short name	T2508
Test name
Test status
Simulation time	148794456 ps
CPU time	0.82 seconds
Started	Aug 01 06:15:47 PM PDT 24
Finished	Aug 01 06:15:48 PM PDT 24
Peak memory	206968 kb
Host	smart-b19b3b01-2563-4878-985f-6f7eb9b5e6d0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25454 98880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2545498880
Directory	/workspace/23.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/23.usbdev_smoke.4083808108
Short name	T1555
Test name
Test status
Simulation time	211688144 ps
CPU time	1.03 seconds
Started	Aug 01 06:15:50 PM PDT 24
Finished	Aug 01 06:15:51 PM PDT 24
Peak memory	206932 kb
Host	smart-89d21c2e-1549-4cd2-84cc-88411adf49da
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40838 08108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.4083808108
Directory	/workspace/23.usbdev_smoke/latest

Test location	/workspace/coverage/default/23.usbdev_spurious_pids_ignored.3704342686
Short name	T1390
Test name
Test status
Simulation time	2613514245 ps
CPU time	75.38 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:17:13 PM PDT 24
Peak memory	217236 kb
Host	smart-5e51835c-0212-44a9-9307-c75cd7012c9a
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3704342686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3704342686
Directory	/workspace/23.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/23.usbdev_stall_priority_over_nak.345104617
Short name	T2834
Test name
Test status
Simulation time	213108243 ps
CPU time	0.93 seconds
Started	Aug 01 06:15:54 PM PDT 24
Finished	Aug 01 06:15:55 PM PDT 24
Peak memory	206968 kb
Host	smart-7bef4619-3409-4a47-a50b-a085a716327f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34510 4617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.345104617
Directory	/workspace/23.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/23.usbdev_stall_trans.2570225480
Short name	T1038
Test name
Test status
Simulation time	172028934 ps
CPU time	0.85 seconds
Started	Aug 01 06:15:59 PM PDT 24
Finished	Aug 01 06:16:00 PM PDT 24
Peak memory	206904 kb
Host	smart-4ed12a7f-e05e-4a0a-b9b6-d676e7cc9fdc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25702 25480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.2570225480
Directory	/workspace/23.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/23.usbdev_stream_len_max.2928689387
Short name	T744
Test name
Test status
Simulation time	1218099432 ps
CPU time	2.66 seconds
Started	Aug 01 06:16:02 PM PDT 24
Finished	Aug 01 06:16:05 PM PDT 24
Peak memory	207160 kb
Host	smart-dce87fbf-9be8-4a31-8dc0-5f758dbc80a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29286 89387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2928689387
Directory	/workspace/23.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/23.usbdev_streaming_out.2438758762
Short name	T2890
Test name
Test status
Simulation time	2062067719 ps
CPU time	56.46 seconds
Started	Aug 01 06:15:47 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	215368 kb
Host	smart-20bf25ef-fa32-4b67-a105-d9c98b161562
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24387 58762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2438758762
Directory	/workspace/23.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.2511301573
Short name	T2199
Test name
Test status
Simulation time	1286771412 ps
CPU time	30.04 seconds
Started	Aug 01 06:15:37 PM PDT 24
Finished	Aug 01 06:16:08 PM PDT 24
Peak memory	207132 kb
Host	smart-bff364a8-bb97-49b1-89fd-703305f392bd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511301573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_hos t_handshake.2511301573
Directory	/workspace/23.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/24.usbdev_alert_test.2071953211
Short name	T1508
Test name
Test status
Simulation time	57659221 ps
CPU time	0.69 seconds
Started	Aug 01 06:16:07 PM PDT 24
Finished	Aug 01 06:16:07 PM PDT 24
Peak memory	206960 kb
Host	smart-ee7c2175-1118-4727-90c1-e41c859b0b97
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2071953211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2071953211
Directory	/workspace/24.usbdev_alert_test/latest

Test location	/workspace/coverage/default/24.usbdev_av_buffer.1733843304
Short name	T2183
Test name
Test status
Simulation time	217813204 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:05 PM PDT 24
Finished	Aug 01 06:16:06 PM PDT 24
Peak memory	206964 kb
Host	smart-a23b5c17-020a-4aa6-9a45-f9606fed7de7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17338 43304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1733843304
Directory	/workspace/24.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/24.usbdev_bitstuff_err.3817671809
Short name	T57
Test name
Test status
Simulation time	157130872 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:57 PM PDT 24
Finished	Aug 01 06:15:58 PM PDT 24
Peak memory	206876 kb
Host	smart-b5405b0c-9e11-4c21-84a3-153a4a40342d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176 71809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3817671809
Directory	/workspace/24.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/24.usbdev_data_toggle_clear.577608465
Short name	T2750
Test name
Test status
Simulation time	270379171 ps
CPU time	1.13 seconds
Started	Aug 01 06:15:52 PM PDT 24
Finished	Aug 01 06:15:53 PM PDT 24
Peak memory	206932 kb
Host	smart-4209a3bb-34a9-4cb9-86c8-20438a95bc15
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57760 8465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.577608465
Directory	/workspace/24.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/24.usbdev_data_toggle_restore.1225205865
Short name	T1191
Test name
Test status
Simulation time	342041100 ps
CPU time	1.19 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:16:00 PM PDT 24
Peak memory	206952 kb
Host	smart-0dfb2ea8-8911-42aa-872b-1613b62cff37
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1225205865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.1225205865
Directory	/workspace/24.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/24.usbdev_device_address.210445427
Short name	T2316
Test name
Test status
Simulation time	18674368199 ps
CPU time	28.11 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:16:26 PM PDT 24
Peak memory	207200 kb
Host	smart-b941dcde-bff1-4c45-abf8-d228f228a8c7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21044 5427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.210445427
Directory	/workspace/24.usbdev_device_address/latest

Test location	/workspace/coverage/default/24.usbdev_device_timeout.1228608773
Short name	T2698
Test name
Test status
Simulation time	4355495895 ps
CPU time	28.08 seconds
Started	Aug 01 06:15:50 PM PDT 24
Finished	Aug 01 06:16:19 PM PDT 24
Peak memory	207204 kb
Host	smart-10c4fc70-e78c-4368-86ae-81c4a4ab8b90
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228608773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.1228608773
Directory	/workspace/24.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/24.usbdev_disable_endpoint.56469649
Short name	T1246
Test name
Test status
Simulation time	943428383 ps
CPU time	2.36 seconds
Started	Aug 01 06:16:05 PM PDT 24
Finished	Aug 01 06:16:08 PM PDT 24
Peak memory	206920 kb
Host	smart-bdd59b76-9bae-4373-9140-d2605670d852
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56469 649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.56469649
Directory	/workspace/24.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/24.usbdev_disconnected.1595237238
Short name	T665
Test name
Test status
Simulation time	146916491 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:55 PM PDT 24
Finished	Aug 01 06:15:56 PM PDT 24
Peak memory	206908 kb
Host	smart-b3b6ace4-5b33-4603-a0dc-3cb763f69132
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15952 37238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1595237238
Directory	/workspace/24.usbdev_disconnected/latest

Test location	/workspace/coverage/default/24.usbdev_enable.1310246442
Short name	T538
Test name
Test status
Simulation time	32696738 ps
CPU time	0.69 seconds
Started	Aug 01 06:15:54 PM PDT 24
Finished	Aug 01 06:15:55 PM PDT 24
Peak memory	206928 kb
Host	smart-d53c57d7-4e1f-49fa-8c67-0177664ed8e6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13102 46442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1310246442
Directory	/workspace/24.usbdev_enable/latest

Test location	/workspace/coverage/default/24.usbdev_endpoint_access.2959025739
Short name	T1290
Test name
Test status
Simulation time	795102862 ps
CPU time	2.35 seconds
Started	Aug 01 06:15:51 PM PDT 24
Finished	Aug 01 06:15:53 PM PDT 24
Peak memory	207080 kb
Host	smart-7c17d1d6-3340-471a-a600-9262d02fbe61
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29590 25739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2959025739
Directory	/workspace/24.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/24.usbdev_endpoint_types.3433558908
Short name	T322
Test name
Test status
Simulation time	607558019 ps
CPU time	1.75 seconds
Started	Aug 01 06:15:53 PM PDT 24
Finished	Aug 01 06:15:55 PM PDT 24
Peak memory	206940 kb
Host	smart-a5bf46d5-e42a-4ca0-a1e1-41f92bb23141
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3433558908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.3433558908
Directory	/workspace/24.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/24.usbdev_fifo_rst.502559760
Short name	T770
Test name
Test status
Simulation time	459244189 ps
CPU time	3.01 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:16:01 PM PDT 24
Peak memory	207048 kb
Host	smart-8e80ae74-d333-455b-8243-065793438529
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50255 9760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.502559760
Directory	/workspace/24.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/24.usbdev_in_iso.125365082
Short name	T1886
Test name
Test status
Simulation time	201180799 ps
CPU time	1 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:49 PM PDT 24
Peak memory	207148 kb
Host	smart-eb182225-d9f6-4584-9bf8-4547f510d3cc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=125365082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.125365082
Directory	/workspace/24.usbdev_in_iso/latest

Test location	/workspace/coverage/default/24.usbdev_in_stall.3261140758
Short name	T2378
Test name
Test status
Simulation time	170336000 ps
CPU time	0.9 seconds
Started	Aug 01 06:15:53 PM PDT 24
Finished	Aug 01 06:15:54 PM PDT 24
Peak memory	206896 kb
Host	smart-f039bd75-32da-4761-9c7a-e360babb2c24
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32611 40758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.3261140758
Directory	/workspace/24.usbdev_in_stall/latest

Test location	/workspace/coverage/default/24.usbdev_in_trans.4229456475
Short name	T1960
Test name
Test status
Simulation time	234493052 ps
CPU time	1.02 seconds
Started	Aug 01 06:15:52 PM PDT 24
Finished	Aug 01 06:15:53 PM PDT 24
Peak memory	206964 kb
Host	smart-485e386a-bf60-49a3-9f83-a5080189d70f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42294 56475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.4229456475
Directory	/workspace/24.usbdev_in_trans/latest

Test location	/workspace/coverage/default/24.usbdev_iso_retraction.845468427
Short name	T1891
Test name
Test status
Simulation time	8243054730 ps
CPU time	55.88 seconds
Started	Aug 01 06:15:54 PM PDT 24
Finished	Aug 01 06:16:50 PM PDT 24
Peak memory	207144 kb
Host	smart-7771a742-c876-4198-b85c-8fa4b2555742
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=845468427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.845468427
Directory	/workspace/24.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/24.usbdev_link_in_err.950848225
Short name	T2606
Test name
Test status
Simulation time	289728573 ps
CPU time	1.08 seconds
Started	Aug 01 06:15:50 PM PDT 24
Finished	Aug 01 06:15:51 PM PDT 24
Peak memory	206940 kb
Host	smart-37aaae25-36fa-46e4-b84b-8ecdf82e9846
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95084 8225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.950848225
Directory	/workspace/24.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/24.usbdev_link_suspend.2234793592
Short name	T2023
Test name
Test status
Simulation time	5482567667 ps
CPU time	7.09 seconds
Started	Aug 01 06:15:53 PM PDT 24
Finished	Aug 01 06:16:00 PM PDT 24
Peak memory	215348 kb
Host	smart-b56efa14-c3bc-4616-868b-08805fbf5028
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22347 93592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2234793592
Directory	/workspace/24.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/24.usbdev_low_speed_traffic.3760802696
Short name	T1336
Test name
Test status
Simulation time	4934375177 ps
CPU time	51.05 seconds
Started	Aug 01 06:15:50 PM PDT 24
Finished	Aug 01 06:16:41 PM PDT 24
Peak memory	223608 kb
Host	smart-c0e5fabc-4784-474d-ad1a-6eaf673eb6cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37608 02696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.3760802696
Directory	/workspace/24.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/24.usbdev_max_inter_pkt_delay.577677835
Short name	T1660
Test name
Test status
Simulation time	2648822782 ps
CPU time	21.14 seconds
Started	Aug 01 06:15:57 PM PDT 24
Finished	Aug 01 06:16:19 PM PDT 24
Peak memory	217156 kb
Host	smart-bc445614-74bb-4fdb-8ee7-48b4295d02db
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=577677835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.577677835
Directory	/workspace/24.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/24.usbdev_max_length_in_transaction.3273933643
Short name	T2251
Test name
Test status
Simulation time	282212334 ps
CPU time	1.02 seconds
Started	Aug 01 06:15:59 PM PDT 24
Finished	Aug 01 06:16:00 PM PDT 24
Peak memory	206948 kb
Host	smart-0f735aee-5695-4ac0-9431-71af4c44cd9d
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3273933643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3273933643
Directory	/workspace/24.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/24.usbdev_max_length_out_transaction.1818155170
Short name	T1639
Test name
Test status
Simulation time	197929823 ps
CPU time	0.95 seconds
Started	Aug 01 06:15:54 PM PDT 24
Finished	Aug 01 06:15:55 PM PDT 24
Peak memory	206936 kb
Host	smart-93161207-0e12-4e62-a7f7-de9d6c08d1fd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18181 55170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1818155170
Directory	/workspace/24.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.200383987
Short name	T1667
Test name
Test status
Simulation time	2409180819 ps
CPU time	18.04 seconds
Started	Aug 01 06:15:51 PM PDT 24
Finished	Aug 01 06:16:09 PM PDT 24
Peak memory	207152 kb
Host	smart-247939a6-657f-4b44-b168-004f9f67f4c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20038 3987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.200383987
Directory	/workspace/24.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3305116485
Short name	T1401
Test name
Test status
Simulation time	2223004069 ps
CPU time	21.87 seconds
Started	Aug 01 06:15:54 PM PDT 24
Finished	Aug 01 06:16:16 PM PDT 24
Peak memory	223560 kb
Host	smart-3b57831a-77cc-472e-9f16-8e63a67e7879
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3305116485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3305116485
Directory	/workspace/24.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/24.usbdev_min_length_in_transaction.2137307431
Short name	T1279
Test name
Test status
Simulation time	184114565 ps
CPU time	1.02 seconds
Started	Aug 01 06:15:48 PM PDT 24
Finished	Aug 01 06:15:50 PM PDT 24
Peak memory	206864 kb
Host	smart-127b3a56-133c-4427-ab96-dcb132aafc0b
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2137307431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.2137307431
Directory	/workspace/24.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/24.usbdev_min_length_out_transaction.2103255794
Short name	T1327
Test name
Test status
Simulation time	145729219 ps
CPU time	0.8 seconds
Started	Aug 01 06:15:44 PM PDT 24
Finished	Aug 01 06:15:45 PM PDT 24
Peak memory	206908 kb
Host	smart-bde0d39a-9d4e-4ba1-bd63-4682cb432a4f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21032 55794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2103255794
Directory	/workspace/24.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/24.usbdev_out_iso.1499604997
Short name	T1578
Test name
Test status
Simulation time	201598750 ps
CPU time	0.94 seconds
Started	Aug 01 06:15:57 PM PDT 24
Finished	Aug 01 06:15:58 PM PDT 24
Peak memory	207004 kb
Host	smart-d6bba70f-fe61-47b0-a9c0-3adf8feeb6f4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14996 04997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1499604997
Directory	/workspace/24.usbdev_out_iso/latest

Test location	/workspace/coverage/default/24.usbdev_out_stall.4015654703
Short name	T1971
Test name
Test status
Simulation time	204339732 ps
CPU time	0.89 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:15:59 PM PDT 24
Peak memory	206964 kb
Host	smart-286165b1-81f1-4f94-a00c-97db41712dc1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40156 54703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.4015654703
Directory	/workspace/24.usbdev_out_stall/latest

Test location	/workspace/coverage/default/24.usbdev_out_trans_nak.3296818460
Short name	T2652
Test name
Test status
Simulation time	173109079 ps
CPU time	0.91 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:15:59 PM PDT 24
Peak memory	206952 kb
Host	smart-5ee8e9f7-9acd-47bb-9eec-bfc3d4f7447b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32968 18460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.3296818460
Directory	/workspace/24.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/24.usbdev_pending_in_trans.312826757
Short name	T142
Test name
Test status
Simulation time	182404567 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:02 PM PDT 24
Finished	Aug 01 06:16:04 PM PDT 24
Peak memory	206972 kb
Host	smart-c14d125b-18ec-4678-b7e0-9a507f4f75b2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31282 6757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.312826757
Directory	/workspace/24.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/24.usbdev_phy_config_pinflip.569414815
Short name	T1783
Test name
Test status
Simulation time	243791051 ps
CPU time	1 seconds
Started	Aug 01 06:16:03 PM PDT 24
Finished	Aug 01 06:16:04 PM PDT 24
Peak memory	206904 kb
Host	smart-e9ba9240-de58-4814-801e-a113bc49c872
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=569414815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.569414815
Directory	/workspace/24.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.202175795
Short name	T120
Test name
Test status
Simulation time	153920839 ps
CPU time	0.83 seconds
Started	Aug 01 06:15:57 PM PDT 24
Finished	Aug 01 06:15:58 PM PDT 24
Peak memory	206936 kb
Host	smart-8ef02a50-d64c-4b5a-9810-1da5323c6e52
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20217 5795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.202175795
Directory	/workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/24.usbdev_phy_pins_sense.3973558765
Short name	T24
Test name
Test status
Simulation time	98571959 ps
CPU time	0.75 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:15:59 PM PDT 24
Peak memory	206896 kb
Host	smart-ce4cdd47-4824-4f62-9aa1-8452cb920e47
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39735 58765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.3973558765
Directory	/workspace/24.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/24.usbdev_pkt_buffer.2899703762
Short name	T1217
Test name
Test status
Simulation time	11946253633 ps
CPU time	32.1 seconds
Started	Aug 01 06:16:02 PM PDT 24
Finished	Aug 01 06:16:34 PM PDT 24
Peak memory	223572 kb
Host	smart-3d7f66d8-3406-46ba-bdd9-a2167265cd7c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28997 03762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2899703762
Directory	/workspace/24.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/24.usbdev_pkt_received.432121430
Short name	T1040
Test name
Test status
Simulation time	171953659 ps
CPU time	0.9 seconds
Started	Aug 01 06:16:00 PM PDT 24
Finished	Aug 01 06:16:01 PM PDT 24
Peak memory	206960 kb
Host	smart-e2df2024-1aa8-4370-b1c2-fb355683c02b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43212 1430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.432121430
Directory	/workspace/24.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/24.usbdev_pkt_sent.3486016342
Short name	T2408
Test name
Test status
Simulation time	283273430 ps
CPU time	1.05 seconds
Started	Aug 01 06:15:55 PM PDT 24
Finished	Aug 01 06:15:56 PM PDT 24
Peak memory	206940 kb
Host	smart-2001290b-18b6-44f4-867b-0b0eb1ecd90f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34860 16342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.3486016342
Directory	/workspace/24.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/24.usbdev_random_length_in_transaction.2039118037
Short name	T1622
Test name
Test status
Simulation time	187907535 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:09 PM PDT 24
Peak memory	206936 kb
Host	smart-b9865101-aa7b-48bd-bc90-0455f54687f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20391 18037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.2039118037
Directory	/workspace/24.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/24.usbdev_random_length_out_transaction.1788375689
Short name	T1965
Test name
Test status
Simulation time	164845308 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:07 PM PDT 24
Finished	Aug 01 06:16:08 PM PDT 24
Peak memory	206960 kb
Host	smart-148dfb2a-c981-48a8-81c1-fb1235afa168
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17883 75689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.1788375689
Directory	/workspace/24.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/24.usbdev_rx_crc_err.507591505
Short name	T2020
Test name
Test status
Simulation time	187552584 ps
CPU time	0.88 seconds
Started	Aug 01 06:15:57 PM PDT 24
Finished	Aug 01 06:16:03 PM PDT 24
Peak memory	206940 kb
Host	smart-9abc3657-ff55-47b4-a7bd-fa8a4877c248
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50759 1505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.507591505
Directory	/workspace/24.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/24.usbdev_rx_full.3198991852
Short name	T1383
Test name
Test status
Simulation time	340380169 ps
CPU time	1.29 seconds
Started	Aug 01 06:15:57 PM PDT 24
Finished	Aug 01 06:15:58 PM PDT 24
Peak memory	206944 kb
Host	smart-25eb7870-b6be-40fe-9e22-4f5cc53ca989
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31989 91852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.3198991852
Directory	/workspace/24.usbdev_rx_full/latest

Test location	/workspace/coverage/default/24.usbdev_setup_stage.1454806941
Short name	T1360
Test name
Test status
Simulation time	197522816 ps
CPU time	0.9 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:15:59 PM PDT 24
Peak memory	206888 kb
Host	smart-9288ce13-59a5-4d2d-a17a-3a8e1b2644da
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14548 06941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1454806941
Directory	/workspace/24.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/24.usbdev_setup_trans_ignored.2801309262
Short name	T1987
Test name
Test status
Simulation time	149269776 ps
CPU time	0.85 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:15:59 PM PDT 24
Peak memory	206928 kb
Host	smart-45c601ca-622c-4cec-97f0-4a7539d54722
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28013 09262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2801309262
Directory	/workspace/24.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/24.usbdev_smoke.1364699464
Short name	T2879
Test name
Test status
Simulation time	219524256 ps
CPU time	1.03 seconds
Started	Aug 01 06:16:00 PM PDT 24
Finished	Aug 01 06:16:01 PM PDT 24
Peak memory	206956 kb
Host	smart-2f4a19e2-41b9-4d02-98d7-9c869fee234a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13646 99464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1364699464
Directory	/workspace/24.usbdev_smoke/latest

Test location	/workspace/coverage/default/24.usbdev_stall_priority_over_nak.2433488159
Short name	T2492
Test name
Test status
Simulation time	149214502 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:00 PM PDT 24
Finished	Aug 01 06:16:01 PM PDT 24
Peak memory	206936 kb
Host	smart-ebbbb5e9-0ed9-4279-ae23-59ce01726c41
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24334 88159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2433488159
Directory	/workspace/24.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/24.usbdev_stall_trans.1301663091
Short name	T530
Test name
Test status
Simulation time	203470514 ps
CPU time	0.91 seconds
Started	Aug 01 06:16:06 PM PDT 24
Finished	Aug 01 06:16:07 PM PDT 24
Peak memory	206916 kb
Host	smart-16c3d6df-c28a-4756-b834-8389ed6a2169
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13016 63091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1301663091
Directory	/workspace/24.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/24.usbdev_stream_len_max.1466066122
Short name	T1811
Test name
Test status
Simulation time	1377355088 ps
CPU time	3.43 seconds
Started	Aug 01 06:16:02 PM PDT 24
Finished	Aug 01 06:16:06 PM PDT 24
Peak memory	207080 kb
Host	smart-d4286100-c478-420b-a651-053411c46c89
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14660 66122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1466066122
Directory	/workspace/24.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/24.usbdev_streaming_out.1058134986
Short name	T785
Test name
Test status
Simulation time	2386593184 ps
CPU time	22.58 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:16:21 PM PDT 24
Peak memory	215356 kb
Host	smart-e87d2dd6-f4b0-486b-81b4-daea09bfd299
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10581 34986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1058134986
Directory	/workspace/24.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.1206816749
Short name	T1903
Test name
Test status
Simulation time	3854083476 ps
CPU time	33.25 seconds
Started	Aug 01 06:15:51 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	207072 kb
Host	smart-296d4307-dd8d-4c58-8150-bcb0e0e0597d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206816749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_hos t_handshake.1206816749
Directory	/workspace/24.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/25.usbdev_alert_test.268702272
Short name	T2145
Test name
Test status
Simulation time	48851238 ps
CPU time	0.71 seconds
Started	Aug 01 06:16:17 PM PDT 24
Finished	Aug 01 06:16:18 PM PDT 24
Peak memory	206924 kb
Host	smart-65dc6088-8ea1-4e84-bccd-deda4b20dc03
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=268702272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.268702272
Directory	/workspace/25.usbdev_alert_test/latest

Test location	/workspace/coverage/default/25.usbdev_av_buffer.4263373530
Short name	T2446
Test name
Test status
Simulation time	157119385 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	206968 kb
Host	smart-1e299e0e-80d4-4a75-819c-e821150646b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42633 73530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.4263373530
Directory	/workspace/25.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/25.usbdev_bitstuff_err.2618396211
Short name	T708
Test name
Test status
Simulation time	146066136 ps
CPU time	0.8 seconds
Started	Aug 01 06:15:56 PM PDT 24
Finished	Aug 01 06:15:57 PM PDT 24
Peak memory	206824 kb
Host	smart-0fd97eba-1db3-4b59-8c8d-2d70c3b15a44
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26183 96211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2618396211
Directory	/workspace/25.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/25.usbdev_data_toggle_clear.2720682956
Short name	T2288
Test name
Test status
Simulation time	264432086 ps
CPU time	1.08 seconds
Started	Aug 01 06:16:06 PM PDT 24
Finished	Aug 01 06:16:07 PM PDT 24
Peak memory	206936 kb
Host	smart-7f670cb4-dc3e-4386-b4e9-69f38360a8e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27206 82956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2720682956
Directory	/workspace/25.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/25.usbdev_data_toggle_restore.950720500
Short name	T2357
Test name
Test status
Simulation time	1194352994 ps
CPU time	3.29 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	207152 kb
Host	smart-4fc6a9cf-b87d-43dc-89c5-233d4027be44
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=950720500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.950720500
Directory	/workspace/25.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/25.usbdev_device_address.760985065
Short name	T216
Test name
Test status
Simulation time	16560204028 ps
CPU time	28.66 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	207080 kb
Host	smart-7910208d-edb3-4f33-8686-f76c966b77ec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76098 5065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.760985065
Directory	/workspace/25.usbdev_device_address/latest

Test location	/workspace/coverage/default/25.usbdev_device_timeout.4014633153
Short name	T2086
Test name
Test status
Simulation time	1555684881 ps
CPU time	13.03 seconds
Started	Aug 01 06:15:55 PM PDT 24
Finished	Aug 01 06:16:09 PM PDT 24
Peak memory	207128 kb
Host	smart-e7190379-64b1-4386-a65c-dfe88a6e7a88
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014633153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.4014633153
Directory	/workspace/25.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/25.usbdev_disable_endpoint.3858222761
Short name	T2735
Test name
Test status
Simulation time	640544423 ps
CPU time	1.81 seconds
Started	Aug 01 06:15:57 PM PDT 24
Finished	Aug 01 06:15:59 PM PDT 24
Peak memory	206924 kb
Host	smart-6259e0dd-0a36-449b-96d6-ea6660e0b66c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38582 22761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3858222761
Directory	/workspace/25.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/25.usbdev_disconnected.251716589
Short name	T688
Test name
Test status
Simulation time	141892456 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:01 PM PDT 24
Finished	Aug 01 06:16:02 PM PDT 24
Peak memory	206872 kb
Host	smart-b49d2ae4-2a94-4303-8b46-8913b461ba32
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25171 6589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.251716589
Directory	/workspace/25.usbdev_disconnected/latest

Test location	/workspace/coverage/default/25.usbdev_enable.3493349409
Short name	T2336
Test name
Test status
Simulation time	36610145 ps
CPU time	0.72 seconds
Started	Aug 01 06:16:03 PM PDT 24
Finished	Aug 01 06:16:03 PM PDT 24
Peak memory	206892 kb
Host	smart-4becef4b-cd65-4e32-a4b3-00989b9f19db
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34933 49409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3493349409
Directory	/workspace/25.usbdev_enable/latest

Test location	/workspace/coverage/default/25.usbdev_endpoint_access.2492503343
Short name	T2657
Test name
Test status
Simulation time	959539980 ps
CPU time	2.6 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	207156 kb
Host	smart-f53bf440-d9e8-4242-9418-9d89409083cd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24925 03343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.2492503343
Directory	/workspace/25.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/25.usbdev_endpoint_types.1793870689
Short name	T341
Test name
Test status
Simulation time	562505759 ps
CPU time	1.47 seconds
Started	Aug 01 06:16:09 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	206900 kb
Host	smart-2975d38d-86c2-4acf-b73b-58a4bf3faf23
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1793870689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.1793870689
Directory	/workspace/25.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/25.usbdev_fifo_rst.3330350433
Short name	T83
Test name
Test status
Simulation time	180099454 ps
CPU time	2.19 seconds
Started	Aug 01 06:16:02 PM PDT 24
Finished	Aug 01 06:16:04 PM PDT 24
Peak memory	207076 kb
Host	smart-946958d1-aef5-4449-b205-e030b45bb8a6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33303 50433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3330350433
Directory	/workspace/25.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/25.usbdev_in_iso.384243377
Short name	T2393
Test name
Test status
Simulation time	197725020 ps
CPU time	1.12 seconds
Started	Aug 01 06:16:01 PM PDT 24
Finished	Aug 01 06:16:02 PM PDT 24
Peak memory	207096 kb
Host	smart-4956806c-cdd4-4bb2-b83a-4867ee4cd963
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=384243377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.384243377
Directory	/workspace/25.usbdev_in_iso/latest

Test location	/workspace/coverage/default/25.usbdev_in_stall.2361888975
Short name	T2407
Test name
Test status
Simulation time	147182202 ps
CPU time	0.82 seconds
Started	Aug 01 06:16:00 PM PDT 24
Finished	Aug 01 06:16:01 PM PDT 24
Peak memory	206940 kb
Host	smart-32ad4c6a-d2ca-47c7-9271-1d068f45fd57
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23618 88975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2361888975
Directory	/workspace/25.usbdev_in_stall/latest

Test location	/workspace/coverage/default/25.usbdev_in_trans.3127384927
Short name	T1215
Test name
Test status
Simulation time	223971114 ps
CPU time	1.03 seconds
Started	Aug 01 06:16:01 PM PDT 24
Finished	Aug 01 06:16:02 PM PDT 24
Peak memory	206972 kb
Host	smart-afac5dfc-242c-42e6-98d8-8e14f06b5498
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31273 84927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.3127384927
Directory	/workspace/25.usbdev_in_trans/latest

Test location	/workspace/coverage/default/25.usbdev_invalid_sync.2566504267
Short name	T1605
Test name
Test status
Simulation time	4081246311 ps
CPU time	32.98 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:16:31 PM PDT 24
Peak memory	223428 kb
Host	smart-673caa89-7de7-4840-9116-a3377bd22c54
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2566504267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.2566504267
Directory	/workspace/25.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/25.usbdev_iso_retraction.1137982801
Short name	T2197
Test name
Test status
Simulation time	10911239244 ps
CPU time	81.73 seconds
Started	Aug 01 06:16:06 PM PDT 24
Finished	Aug 01 06:17:28 PM PDT 24
Peak memory	207120 kb
Host	smart-6dbd8400-a2c0-4938-8109-e5b20c7d75a5
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1137982801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.1137982801
Directory	/workspace/25.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/25.usbdev_link_in_err.1724001515
Short name	T954
Test name
Test status
Simulation time	227533745 ps
CPU time	1 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:09 PM PDT 24
Peak memory	206940 kb
Host	smart-2d02e3cf-0347-40e9-9cac-8d4132f87f1b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17240 01515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1724001515
Directory	/workspace/25.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/25.usbdev_link_suspend.1102873751
Short name	T89
Test name
Test status
Simulation time	3316083716 ps
CPU time	5.23 seconds
Started	Aug 01 06:16:06 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	215316 kb
Host	smart-d1ee20d2-d852-40e1-aeee-b666ba177d92
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11028 73751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1102873751
Directory	/workspace/25.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3567976555
Short name	T1908
Test name
Test status
Simulation time	3051681419 ps
CPU time	27.16 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:35 PM PDT 24
Peak memory	215280 kb
Host	smart-96818399-12f8-454e-96b2-1aeccaf692b9
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3567976555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3567976555
Directory	/workspace/25.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/25.usbdev_max_length_in_transaction.733278498
Short name	T2884
Test name
Test status
Simulation time	240428957 ps
CPU time	0.99 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:09 PM PDT 24
Peak memory	206908 kb
Host	smart-45132e48-1ba8-46b7-8f17-df4f6bead524
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=733278498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.733278498
Directory	/workspace/25.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/25.usbdev_max_length_out_transaction.3156582017
Short name	T1788
Test name
Test status
Simulation time	198722782 ps
CPU time	0.94 seconds
Started	Aug 01 06:16:05 PM PDT 24
Finished	Aug 01 06:16:06 PM PDT 24
Peak memory	206968 kb
Host	smart-c0a367ac-ce96-468f-9280-1efe9041ad5a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31565 82017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.3156582017
Directory	/workspace/25.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/25.usbdev_min_inter_pkt_delay.2728365230
Short name	T2661
Test name
Test status
Simulation time	2838405338 ps
CPU time	80.01 seconds
Started	Aug 01 06:15:56 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	215320 kb
Host	smart-baaa92de-da4b-4d37-ad8b-b7bbc4a70571
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2728365230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.2728365230
Directory	/workspace/25.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/25.usbdev_min_length_in_transaction.1679995234
Short name	T1491
Test name
Test status
Simulation time	188194514 ps
CPU time	0.87 seconds
Started	Aug 01 06:15:55 PM PDT 24
Finished	Aug 01 06:15:56 PM PDT 24
Peak memory	206948 kb
Host	smart-b47d07fc-dc35-4266-842a-caaef9fce0de
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1679995234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.1679995234
Directory	/workspace/25.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/25.usbdev_min_length_out_transaction.2413464285
Short name	T769
Test name
Test status
Simulation time	139549302 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:09 PM PDT 24
Finished	Aug 01 06:16:10 PM PDT 24
Peak memory	207176 kb
Host	smart-e98e692c-5ebe-496d-b8de-e220e7437f5c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24134 64285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2413464285
Directory	/workspace/25.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/25.usbdev_out_iso.1448314165
Short name	T1818
Test name
Test status
Simulation time	154748786 ps
CPU time	0.84 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	206948 kb
Host	smart-18bde2ac-9871-4d26-80b3-bfed0046599d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14483 14165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1448314165
Directory	/workspace/25.usbdev_out_iso/latest

Test location	/workspace/coverage/default/25.usbdev_out_stall.2078383157
Short name	T1504
Test name
Test status
Simulation time	183582283 ps
CPU time	0.92 seconds
Started	Aug 01 06:16:17 PM PDT 24
Finished	Aug 01 06:16:18 PM PDT 24
Peak memory	206920 kb
Host	smart-eb7d3312-cff5-4729-917b-adda66f79d18
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20783 83157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2078383157
Directory	/workspace/25.usbdev_out_stall/latest

Test location	/workspace/coverage/default/25.usbdev_out_trans_nak.459931024
Short name	T2520
Test name
Test status
Simulation time	194328161 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:17 PM PDT 24
Finished	Aug 01 06:16:18 PM PDT 24
Peak memory	206944 kb
Host	smart-e788002e-2288-4013-b4ef-6f0d1dad5406
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45993 1024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.459931024
Directory	/workspace/25.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/25.usbdev_pending_in_trans.333609367
Short name	T12
Test name
Test status
Simulation time	192359325 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	206944 kb
Host	smart-d1633139-1615-4637-adc4-a11ca2055700
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33360 9367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.333609367
Directory	/workspace/25.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/25.usbdev_phy_config_pinflip.370490128
Short name	T2038
Test name
Test status
Simulation time	257117797 ps
CPU time	1.06 seconds
Started	Aug 01 06:16:11 PM PDT 24
Finished	Aug 01 06:16:12 PM PDT 24
Peak memory	206928 kb
Host	smart-06dcf07a-d06d-4931-b7f2-b701353f2899
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=370490128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.370490128
Directory	/workspace/25.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.300438522
Short name	T680
Test name
Test status
Simulation time	173384078 ps
CPU time	0.86 seconds
Started	Aug 01 06:16:11 PM PDT 24
Finished	Aug 01 06:16:12 PM PDT 24
Peak memory	206884 kb
Host	smart-cafc7246-f97e-4394-9b39-c5ebdb93d763
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30043 8522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.300438522
Directory	/workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/25.usbdev_phy_pins_sense.1305916031
Short name	T1031
Test name
Test status
Simulation time	44076731 ps
CPU time	0.69 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	206860 kb
Host	smart-d8a6bb95-3103-4186-9b9d-2e89e6cb784a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13059 16031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1305916031
Directory	/workspace/25.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/25.usbdev_pkt_buffer.962862654
Short name	T2185
Test name
Test status
Simulation time	14625034529 ps
CPU time	40.37 seconds
Started	Aug 01 06:16:17 PM PDT 24
Finished	Aug 01 06:16:57 PM PDT 24
Peak memory	215340 kb
Host	smart-1f716d0c-8dd7-4863-b525-48eb2fffd86e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96286 2654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.962862654
Directory	/workspace/25.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/25.usbdev_pkt_received.2538716377
Short name	T2275
Test name
Test status
Simulation time	166232785 ps
CPU time	1.01 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:12 PM PDT 24
Peak memory	206952 kb
Host	smart-4edddd30-5e4a-438b-828e-148c295a280c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25387 16377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2538716377
Directory	/workspace/25.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/25.usbdev_pkt_sent.184349937
Short name	T576
Test name
Test status
Simulation time	211962251 ps
CPU time	0.9 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206888 kb
Host	smart-09ed84b6-9723-4319-b937-c94b15dbf55e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18434 9937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.184349937
Directory	/workspace/25.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/25.usbdev_random_length_in_transaction.3837791144
Short name	T1396
Test name
Test status
Simulation time	169844077 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:15 PM PDT 24
Finished	Aug 01 06:16:16 PM PDT 24
Peak memory	206996 kb
Host	smart-d5fef981-4fbf-4bea-a208-af66d18b3859
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38377 91144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3837791144
Directory	/workspace/25.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/25.usbdev_random_length_out_transaction.1576510013
Short name	T2471
Test name
Test status
Simulation time	182540711 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	206912 kb
Host	smart-9975856f-6ff9-44fe-beda-b1bf7ae4882e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15765 10013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.1576510013
Directory	/workspace/25.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/25.usbdev_rx_crc_err.137810297
Short name	T1502
Test name
Test status
Simulation time	163138280 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:19 PM PDT 24
Finished	Aug 01 06:16:20 PM PDT 24
Peak memory	206964 kb
Host	smart-a7891f79-64fe-4d7a-99cc-44a531d87a10
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13781 0297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.137810297
Directory	/workspace/25.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/25.usbdev_rx_full.4146315797
Short name	T279
Test name
Test status
Simulation time	266800835 ps
CPU time	1.12 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	206948 kb
Host	smart-8e31d10c-e270-4209-9e71-340e1f5ce95d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41463 15797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.4146315797
Directory	/workspace/25.usbdev_rx_full/latest

Test location	/workspace/coverage/default/25.usbdev_setup_stage.4266568096
Short name	T1430
Test name
Test status
Simulation time	143253449 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:09 PM PDT 24
Peak memory	206920 kb
Host	smart-a940ad13-a390-4f54-808a-18f7ff7442cc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42665 68096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.4266568096
Directory	/workspace/25.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/25.usbdev_setup_trans_ignored.3593278477
Short name	T1620
Test name
Test status
Simulation time	187485273 ps
CPU time	0.86 seconds
Started	Aug 01 06:16:12 PM PDT 24
Finished	Aug 01 06:16:13 PM PDT 24
Peak memory	206932 kb
Host	smart-3de1088c-0f97-4216-874b-919d33f218ee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35932 78477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3593278477
Directory	/workspace/25.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/25.usbdev_smoke.2958063192
Short name	T2452
Test name
Test status
Simulation time	204657059 ps
CPU time	1.02 seconds
Started	Aug 01 06:16:11 PM PDT 24
Finished	Aug 01 06:16:12 PM PDT 24
Peak memory	206956 kb
Host	smart-03809b88-6861-4ef3-858a-91d560b41d98
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29580 63192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.2958063192
Directory	/workspace/25.usbdev_smoke/latest

Test location	/workspace/coverage/default/25.usbdev_spurious_pids_ignored.2572108546
Short name	T2585
Test name
Test status
Simulation time	2559282672 ps
CPU time	25.09 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	215400 kb
Host	smart-4ed5a861-7606-4138-aa0d-b0cb8f11be94
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2572108546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2572108546
Directory	/workspace/25.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/25.usbdev_stall_priority_over_nak.1420812763
Short name	T2095
Test name
Test status
Simulation time	217626212 ps
CPU time	0.97 seconds
Started	Aug 01 06:16:17 PM PDT 24
Finished	Aug 01 06:16:18 PM PDT 24
Peak memory	206916 kb
Host	smart-f092ba76-ca20-491b-ad68-23456b8f1701
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14208 12763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1420812763
Directory	/workspace/25.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/25.usbdev_stall_trans.265408249
Short name	T2158
Test name
Test status
Simulation time	174808765 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	206940 kb
Host	smart-74481e38-a5a7-40ef-9f77-ca9d8a864975
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26540 8249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.265408249
Directory	/workspace/25.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/25.usbdev_stream_len_max.422009069
Short name	T900
Test name
Test status
Simulation time	542331781 ps
CPU time	1.6 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:10 PM PDT 24
Peak memory	206848 kb
Host	smart-9719f7d7-cce9-4d86-909e-1e0eefd43bd5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42200 9069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.422009069
Directory	/workspace/25.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/25.usbdev_streaming_out.924880494
Short name	T763
Test name
Test status
Simulation time	3722924349 ps
CPU time	39.81 seconds
Started	Aug 01 06:16:11 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	216868 kb
Host	smart-eb97cf54-849d-4d92-a370-e97d6f269513
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92488 0494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.924880494
Directory	/workspace/25.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.3930052314
Short name	T1824
Test name
Test status
Simulation time	5016228435 ps
CPU time	32.76 seconds
Started	Aug 01 06:15:58 PM PDT 24
Finished	Aug 01 06:16:30 PM PDT 24
Peak memory	207176 kb
Host	smart-bcf816b2-f9ad-4a8a-9d41-8130c6b820cc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930052314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos t_handshake.3930052314
Directory	/workspace/25.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/26.usbdev_alert_test.1615034207
Short name	T2853
Test name
Test status
Simulation time	38010945 ps
CPU time	0.68 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206976 kb
Host	smart-6d826e13-aa75-4995-a29c-dfefdd18a21b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1615034207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.1615034207
Directory	/workspace/26.usbdev_alert_test/latest

Test location	/workspace/coverage/default/26.usbdev_av_buffer.3730223700
Short name	T875
Test name
Test status
Simulation time	160322970 ps
CPU time	0.91 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:12 PM PDT 24
Peak memory	206956 kb
Host	smart-6f1b5138-b3a5-438c-9bdd-7bc4f0fbd152
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37302 23700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3730223700
Directory	/workspace/26.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/26.usbdev_bitstuff_err.3970439152
Short name	T61
Test name
Test status
Simulation time	161291562 ps
CPU time	0.9 seconds
Started	Aug 01 06:16:16 PM PDT 24
Finished	Aug 01 06:16:17 PM PDT 24
Peak memory	206888 kb
Host	smart-faa66ebb-21dd-49eb-83bf-1af0786325bd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39704 39152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3970439152
Directory	/workspace/26.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/26.usbdev_data_toggle_clear.3800703957
Short name	T2410
Test name
Test status
Simulation time	362712592 ps
CPU time	1.34 seconds
Started	Aug 01 06:16:09 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	206964 kb
Host	smart-7617a206-3ea7-444a-9502-67b9e18c923c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38007 03957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3800703957
Directory	/workspace/26.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/26.usbdev_data_toggle_restore.706766028
Short name	T2090
Test name
Test status
Simulation time	960558442 ps
CPU time	2.59 seconds
Started	Aug 01 06:16:15 PM PDT 24
Finished	Aug 01 06:16:18 PM PDT 24
Peak memory	207140 kb
Host	smart-15cf7986-938a-4a84-a6f8-ba1ca295c10b
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=706766028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.706766028
Directory	/workspace/26.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/26.usbdev_device_timeout.4220081995
Short name	T645
Test name
Test status
Simulation time	1411885756 ps
CPU time	32.9 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	207184 kb
Host	smart-619d3b56-ceac-4aaa-8c5c-2c9dd35f8556
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220081995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.4220081995
Directory	/workspace/26.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/26.usbdev_disable_endpoint.1585170749
Short name	T1199
Test name
Test status
Simulation time	785433278 ps
CPU time	1.95 seconds
Started	Aug 01 06:16:09 PM PDT 24
Finished	Aug 01 06:16:11 PM PDT 24
Peak memory	206908 kb
Host	smart-964b2bd6-f6fe-4e74-9136-c2112034b037
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15851 70749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1585170749
Directory	/workspace/26.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/26.usbdev_disconnected.2418527464
Short name	T2836
Test name
Test status
Simulation time	141203993 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	206916 kb
Host	smart-626ceaff-312a-41ed-8eda-e6f82ef3bf67
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24185 27464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2418527464
Directory	/workspace/26.usbdev_disconnected/latest

Test location	/workspace/coverage/default/26.usbdev_enable.2753663394
Short name	T2424
Test name
Test status
Simulation time	36106536 ps
CPU time	0.72 seconds
Started	Aug 01 06:16:08 PM PDT 24
Finished	Aug 01 06:16:09 PM PDT 24
Peak memory	206828 kb
Host	smart-91c0e0c8-99eb-4098-8900-1db25da61b8c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27536 63394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2753663394
Directory	/workspace/26.usbdev_enable/latest

Test location	/workspace/coverage/default/26.usbdev_endpoint_access.2529107029
Short name	T1565
Test name
Test status
Simulation time	809805938 ps
CPU time	2.48 seconds
Started	Aug 01 06:16:07 PM PDT 24
Finished	Aug 01 06:16:10 PM PDT 24
Peak memory	207136 kb
Host	smart-84d6660c-3794-483a-aed4-adc47434423e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25291 07029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.2529107029
Directory	/workspace/26.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/26.usbdev_endpoint_types.2683006430
Short name	T2453
Test name
Test status
Simulation time	284769956 ps
CPU time	1.08 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206936 kb
Host	smart-489656aa-abf6-4944-9759-3c0e43d5f382
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2683006430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.2683006430
Directory	/workspace/26.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/26.usbdev_fifo_rst.2384158859
Short name	T619
Test name
Test status
Simulation time	282859311 ps
CPU time	2.4 seconds
Started	Aug 01 06:16:20 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	207080 kb
Host	smart-f3843fe5-c13a-468c-b9a1-2cbac61f7eba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23841 58859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2384158859
Directory	/workspace/26.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/26.usbdev_in_iso.4181876686
Short name	T1392
Test name
Test status
Simulation time	207377177 ps
CPU time	1.11 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:25 PM PDT 24
Peak memory	207124 kb
Host	smart-93f1d33f-0b69-472c-bb2e-1b0b6c6cbaf4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4181876686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.4181876686
Directory	/workspace/26.usbdev_in_iso/latest

Test location	/workspace/coverage/default/26.usbdev_in_stall.657882365
Short name	T2795
Test name
Test status
Simulation time	206098207 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:17 PM PDT 24
Finished	Aug 01 06:16:18 PM PDT 24
Peak memory	206904 kb
Host	smart-527aaa11-787a-4442-afca-5804f28b2938
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65788 2365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.657882365
Directory	/workspace/26.usbdev_in_stall/latest

Test location	/workspace/coverage/default/26.usbdev_in_trans.3402629957
Short name	T1097
Test name
Test status
Simulation time	152273054 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:27 PM PDT 24
Finished	Aug 01 06:16:28 PM PDT 24
Peak memory	206900 kb
Host	smart-a2ad7b89-a4e7-4f56-bd8c-f2bf2af8d976
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34026 29957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3402629957
Directory	/workspace/26.usbdev_in_trans/latest

Test location	/workspace/coverage/default/26.usbdev_invalid_sync.374162866
Short name	T1515
Test name
Test status
Simulation time	2795381019 ps
CPU time	20.54 seconds
Started	Aug 01 06:16:27 PM PDT 24
Finished	Aug 01 06:16:48 PM PDT 24
Peak memory	223540 kb
Host	smart-9dedb0d3-b22f-4460-b36c-d03e2fa118b5
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=374162866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.374162866
Directory	/workspace/26.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/26.usbdev_iso_retraction.2900150986
Short name	T2702
Test name
Test status
Simulation time	4765006536 ps
CPU time	56.61 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	207124 kb
Host	smart-86b4ed4e-6254-4114-a4a5-a2db5f2a99e3
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2900150986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.2900150986
Directory	/workspace/26.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/26.usbdev_link_in_err.327134884
Short name	T1355
Test name
Test status
Simulation time	186261822 ps
CPU time	0.93 seconds
Started	Aug 01 06:16:18 PM PDT 24
Finished	Aug 01 06:16:19 PM PDT 24
Peak memory	206932 kb
Host	smart-dff5bb0e-3032-4f5e-908e-90f20b6ea7f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32713 4884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.327134884
Directory	/workspace/26.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/26.usbdev_link_suspend.776356927
Short name	T2555
Test name
Test status
Simulation time	4281878652 ps
CPU time	5.69 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:29 PM PDT 24
Peak memory	215332 kb
Host	smart-f8e67740-1289-4347-be09-f92c04d46428
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77635 6927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.776356927
Directory	/workspace/26.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/26.usbdev_low_speed_traffic.396414633
Short name	T2902
Test name
Test status
Simulation time	4565293702 ps
CPU time	34.51 seconds
Started	Aug 01 06:16:21 PM PDT 24
Finished	Aug 01 06:16:56 PM PDT 24
Peak memory	215348 kb
Host	smart-6912f48d-e81f-4cb7-9dcb-abd3b6a73ea5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39641 4633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.396414633
Directory	/workspace/26.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/26.usbdev_max_inter_pkt_delay.911343538
Short name	T2499
Test name
Test status
Simulation time	2549790986 ps
CPU time	72.37 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	215384 kb
Host	smart-5f586559-ee6d-4b85-9d52-b607a070ba23
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=911343538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.911343538
Directory	/workspace/26.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/26.usbdev_max_length_in_transaction.3871952536
Short name	T611
Test name
Test status
Simulation time	239902435 ps
CPU time	0.99 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:25 PM PDT 24
Peak memory	206956 kb
Host	smart-29d265ca-5bd2-41d1-88cb-e09840e889e5
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3871952536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3871952536
Directory	/workspace/26.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/26.usbdev_max_length_out_transaction.3892806342
Short name	T482
Test name
Test status
Simulation time	214786438 ps
CPU time	1 seconds
Started	Aug 01 06:16:20 PM PDT 24
Finished	Aug 01 06:16:21 PM PDT 24
Peak memory	206956 kb
Host	smart-48a68d81-86e1-4e14-8701-f240db8f7b04
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38928 06342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3892806342
Directory	/workspace/26.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2037474391
Short name	T1350
Test name
Test status
Simulation time	2240966410 ps
CPU time	63.13 seconds
Started	Aug 01 06:16:27 PM PDT 24
Finished	Aug 01 06:17:30 PM PDT 24
Peak memory	215464 kb
Host	smart-4fdda4fa-9460-413c-941c-cc666260d675
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2037474391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2037474391
Directory	/workspace/26.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/26.usbdev_min_length_in_transaction.2366292933
Short name	T964
Test name
Test status
Simulation time	170583279 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	206924 kb
Host	smart-4dd5fa14-956a-44ed-9d87-77a3d4b74faf
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2366292933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.2366292933
Directory	/workspace/26.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/26.usbdev_min_length_out_transaction.3928222473
Short name	T1894
Test name
Test status
Simulation time	146299584 ps
CPU time	0.84 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206920 kb
Host	smart-3483c312-68bd-4f16-8bf9-de3af6176dbf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39282 22473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3928222473
Directory	/workspace/26.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/26.usbdev_nak_trans.1205958040
Short name	T175
Test name
Test status
Simulation time	206627587 ps
CPU time	0.95 seconds
Started	Aug 01 06:16:20 PM PDT 24
Finished	Aug 01 06:16:22 PM PDT 24
Peak memory	206956 kb
Host	smart-3d729bb0-a530-41b0-a60d-b20d510df7dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12059 58040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1205958040
Directory	/workspace/26.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/26.usbdev_out_iso.2379030437
Short name	T1975
Test name
Test status
Simulation time	169435723 ps
CPU time	0.86 seconds
Started	Aug 01 06:16:21 PM PDT 24
Finished	Aug 01 06:16:22 PM PDT 24
Peak memory	206912 kb
Host	smart-2d1d1fd5-8a3b-4475-a242-2d13ff794245
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790 30437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.2379030437
Directory	/workspace/26.usbdev_out_iso/latest

Test location	/workspace/coverage/default/26.usbdev_out_stall.4235782556
Short name	T589
Test name
Test status
Simulation time	163910839 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:27 PM PDT 24
Finished	Aug 01 06:16:27 PM PDT 24
Peak memory	206964 kb
Host	smart-824d590c-bedf-4557-a473-1c7be5e29f4c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42357 82556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.4235782556
Directory	/workspace/26.usbdev_out_stall/latest

Test location	/workspace/coverage/default/26.usbdev_out_trans_nak.4272951308
Short name	T2312
Test name
Test status
Simulation time	159851395 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:25 PM PDT 24
Peak memory	206924 kb
Host	smart-08df07c0-bbbf-4f90-a6e3-1d6b941f517f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42729 51308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.4272951308
Directory	/workspace/26.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/26.usbdev_pending_in_trans.1031257575
Short name	T1779
Test name
Test status
Simulation time	156606435 ps
CPU time	0.84 seconds
Started	Aug 01 06:16:25 PM PDT 24
Finished	Aug 01 06:16:26 PM PDT 24
Peak memory	206980 kb
Host	smart-2cca7916-c16f-4cbf-9799-220b600dbf17
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10312 57575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1031257575
Directory	/workspace/26.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/26.usbdev_phy_config_pinflip.917605292
Short name	T1585
Test name
Test status
Simulation time	226341972 ps
CPU time	1.05 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	206980 kb
Host	smart-3309ba34-bc7c-4aad-b711-b1adbcf49922
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=917605292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.917605292
Directory	/workspace/26.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2294357622
Short name	T1188
Test name
Test status
Simulation time	145003322 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206868 kb
Host	smart-ef120a97-7b6a-42fe-b5e7-19f85beeadbb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22943 57622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2294357622
Directory	/workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/26.usbdev_phy_pins_sense.1570388215
Short name	T1747
Test name
Test status
Simulation time	44561074 ps
CPU time	0.71 seconds
Started	Aug 01 06:16:25 PM PDT 24
Finished	Aug 01 06:16:26 PM PDT 24
Peak memory	207128 kb
Host	smart-49f458a8-c1fe-4f0e-9e2f-6e01f6c8e8c5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15703 88215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1570388215
Directory	/workspace/26.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/26.usbdev_pkt_buffer.1458094560
Short name	T1326
Test name
Test status
Simulation time	11177027851 ps
CPU time	27.79 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	215376 kb
Host	smart-2601e5fb-f438-4962-8662-fadc0e6d85a9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14580 94560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1458094560
Directory	/workspace/26.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/26.usbdev_pkt_received.4007704913
Short name	T306
Test name
Test status
Simulation time	161081925 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:20 PM PDT 24
Finished	Aug 01 06:16:21 PM PDT 24
Peak memory	206948 kb
Host	smart-540fa537-34bc-441c-bc76-23747a897a6d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077 04913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.4007704913
Directory	/workspace/26.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/26.usbdev_pkt_sent.3320549243
Short name	T852
Test name
Test status
Simulation time	271884271 ps
CPU time	1.13 seconds
Started	Aug 01 06:16:26 PM PDT 24
Finished	Aug 01 06:16:27 PM PDT 24
Peak memory	206876 kb
Host	smart-a8a55c25-7fe9-47c4-bd78-1150e193c197
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33205 49243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3320549243
Directory	/workspace/26.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/26.usbdev_random_length_in_transaction.3319748707
Short name	T1725
Test name
Test status
Simulation time	176464302 ps
CPU time	0.95 seconds
Started	Aug 01 06:16:29 PM PDT 24
Finished	Aug 01 06:16:30 PM PDT 24
Peak memory	206960 kb
Host	smart-ac24b12b-5466-4177-97de-5c712441c1f4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33197 48707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.3319748707
Directory	/workspace/26.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/26.usbdev_random_length_out_transaction.1842236539
Short name	T493
Test name
Test status
Simulation time	159650981 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:19 PM PDT 24
Finished	Aug 01 06:16:20 PM PDT 24
Peak memory	206932 kb
Host	smart-37169bdb-a0f6-4fb5-b2bd-7efd07ff02bf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422 36539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.1842236539
Directory	/workspace/26.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/26.usbdev_rx_crc_err.1572980544
Short name	T1035
Test name
Test status
Simulation time	144709527 ps
CPU time	0.82 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	206916 kb
Host	smart-758b27d6-7f11-4756-bc03-40436de2b329
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15729 80544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1572980544
Directory	/workspace/26.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/26.usbdev_rx_full.2486095010
Short name	T835
Test name
Test status
Simulation time	255365738 ps
CPU time	1.08 seconds
Started	Aug 01 06:16:25 PM PDT 24
Finished	Aug 01 06:16:26 PM PDT 24
Peak memory	206880 kb
Host	smart-aecbb063-9e83-44fa-add6-56141e735a2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24860 95010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.2486095010
Directory	/workspace/26.usbdev_rx_full/latest

Test location	/workspace/coverage/default/26.usbdev_setup_stage.3990059923
Short name	T1826
Test name
Test status
Simulation time	157614598 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	206860 kb
Host	smart-083cdbb5-529c-4133-9c03-f228927e5aec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900 59923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3990059923
Directory	/workspace/26.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/26.usbdev_setup_trans_ignored.4253974161
Short name	T284
Test name
Test status
Simulation time	168577689 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:25 PM PDT 24
Peak memory	206952 kb
Host	smart-fba426cb-caf9-4dc0-a9b5-0ee395afa8ac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42539 74161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.4253974161
Directory	/workspace/26.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/26.usbdev_smoke.1340071631
Short name	T604
Test name
Test status
Simulation time	248233573 ps
CPU time	1.03 seconds
Started	Aug 01 06:16:21 PM PDT 24
Finished	Aug 01 06:16:22 PM PDT 24
Peak memory	206956 kb
Host	smart-9780dcb8-9408-455a-8c2d-5475260f0bf6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13400 71631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.1340071631
Directory	/workspace/26.usbdev_smoke/latest

Test location	/workspace/coverage/default/26.usbdev_spurious_pids_ignored.2751584869
Short name	T203
Test name
Test status
Simulation time	2608387104 ps
CPU time	25.33 seconds
Started	Aug 01 06:16:17 PM PDT 24
Finished	Aug 01 06:16:42 PM PDT 24
Peak memory	223532 kb
Host	smart-bd691126-1cd1-4f68-a64b-0d909a652f9a
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2751584869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2751584869
Directory	/workspace/26.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/26.usbdev_stall_priority_over_nak.3209911933
Short name	T2829
Test name
Test status
Simulation time	192625061 ps
CPU time	0.91 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	207176 kb
Host	smart-58c739a6-7d0f-407b-a26d-d392708ee30e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32099 11933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3209911933
Directory	/workspace/26.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/26.usbdev_stall_trans.1239722757
Short name	T1812
Test name
Test status
Simulation time	177003025 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:26 PM PDT 24
Finished	Aug 01 06:16:27 PM PDT 24
Peak memory	206912 kb
Host	smart-73c05ec3-8d8c-4543-ae50-b386c52c4862
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397 22757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1239722757
Directory	/workspace/26.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/26.usbdev_stream_len_max.163176027
Short name	T2015
Test name
Test status
Simulation time	275506495 ps
CPU time	1.04 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206916 kb
Host	smart-be229bb0-8868-4685-8c60-d93eaaa4f5a1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16317 6027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.163176027
Directory	/workspace/26.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/26.usbdev_streaming_out.2329568532
Short name	T2888
Test name
Test status
Simulation time	2189633195 ps
CPU time	16.28 seconds
Started	Aug 01 06:16:27 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	216312 kb
Host	smart-40ec360c-8bf4-45b3-b858-9c7bd794e6e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23295 68532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2329568532
Directory	/workspace/26.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.2334418846
Short name	T2429
Test name
Test status
Simulation time	146209313 ps
CPU time	0.84 seconds
Started	Aug 01 06:16:10 PM PDT 24
Finished	Aug 01 06:16:12 PM PDT 24
Peak memory	206928 kb
Host	smart-d9d61219-8f7b-4322-ae38-145c67f0696a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334418846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos t_handshake.2334418846
Directory	/workspace/26.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/27.usbdev_alert_test.1686943281
Short name	T1566
Test name
Test status
Simulation time	71267843 ps
CPU time	0.69 seconds
Started	Aug 01 06:16:35 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206968 kb
Host	smart-fe1c183c-25f8-4cfb-a876-8b1a1e0a5759
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1686943281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.1686943281
Directory	/workspace/27.usbdev_alert_test/latest

Test location	/workspace/coverage/default/27.usbdev_av_buffer.2479896435
Short name	T1722
Test name
Test status
Simulation time	148948260 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	206944 kb
Host	smart-78ca1c13-18ee-410c-89be-184c0ec09792
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24798 96435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2479896435
Directory	/workspace/27.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/27.usbdev_bitstuff_err.1793791341
Short name	T1157
Test name
Test status
Simulation time	150630166 ps
CPU time	0.86 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:25 PM PDT 24
Peak memory	206916 kb
Host	smart-c8ceae2f-3f3e-4c12-8395-334b8d4e34e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17937 91341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1793791341
Directory	/workspace/27.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/27.usbdev_data_toggle_clear.847117507
Short name	T2693
Test name
Test status
Simulation time	505249888 ps
CPU time	1.65 seconds
Started	Aug 01 06:16:17 PM PDT 24
Finished	Aug 01 06:16:19 PM PDT 24
Peak memory	206948 kb
Host	smart-05eb6ff9-046f-427b-9bbb-9140fc25e67c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84711 7507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.847117507
Directory	/workspace/27.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/27.usbdev_data_toggle_restore.1603470518
Short name	T687
Test name
Test status
Simulation time	346804075 ps
CPU time	1.28 seconds
Started	Aug 01 06:16:26 PM PDT 24
Finished	Aug 01 06:16:27 PM PDT 24
Peak memory	206952 kb
Host	smart-fe659008-a642-4dd3-87bc-5c5557618084
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1603470518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.1603470518
Directory	/workspace/27.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/27.usbdev_device_address.2760044201
Short name	T221
Test name
Test status
Simulation time	22285775988 ps
CPU time	40.18 seconds
Started	Aug 01 06:16:19 PM PDT 24
Finished	Aug 01 06:16:59 PM PDT 24
Peak memory	207200 kb
Host	smart-3940cb50-7ec9-4d09-8bdc-3fea1a5979a6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27600 44201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.2760044201
Directory	/workspace/27.usbdev_device_address/latest

Test location	/workspace/coverage/default/27.usbdev_device_timeout.1027254749
Short name	T2076
Test name
Test status
Simulation time	4980302690 ps
CPU time	32.45 seconds
Started	Aug 01 06:16:18 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	207140 kb
Host	smart-51ab7ba6-5b48-4483-a88e-5bdf251d9d8b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027254749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.1027254749
Directory	/workspace/27.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/27.usbdev_disable_endpoint.3856763391
Short name	T2473
Test name
Test status
Simulation time	423970864 ps
CPU time	1.47 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206952 kb
Host	smart-58953c7d-566c-469c-9039-f43b3fd399f6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567 63391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.3856763391
Directory	/workspace/27.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/27.usbdev_disconnected.4160946168
Short name	T1932
Test name
Test status
Simulation time	164270286 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:25 PM PDT 24
Finished	Aug 01 06:16:26 PM PDT 24
Peak memory	206864 kb
Host	smart-a7f15c93-817b-4119-b28c-fc7b01f6f511
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41609 46168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.4160946168
Directory	/workspace/27.usbdev_disconnected/latest

Test location	/workspace/coverage/default/27.usbdev_enable.2957764261
Short name	T2441
Test name
Test status
Simulation time	37755153 ps
CPU time	0.7 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:25 PM PDT 24
Peak memory	206920 kb
Host	smart-9562f2ba-838a-48e4-9ff5-02d4f530c851
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29577 64261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.2957764261
Directory	/workspace/27.usbdev_enable/latest

Test location	/workspace/coverage/default/27.usbdev_endpoint_access.4177263385
Short name	T2214
Test name
Test status
Simulation time	1057982460 ps
CPU time	2.73 seconds
Started	Aug 01 06:16:25 PM PDT 24
Finished	Aug 01 06:16:28 PM PDT 24
Peak memory	207140 kb
Host	smart-78d1395e-421b-46cb-b6d0-57b03a4559dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41772 63385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.4177263385
Directory	/workspace/27.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/27.usbdev_fifo_rst.2324431383
Short name	T2442
Test name
Test status
Simulation time	285187474 ps
CPU time	1.98 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:26 PM PDT 24
Peak memory	207116 kb
Host	smart-c2e81f99-1f73-4f7b-9d38-eeec8a86fa91
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23244 31383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2324431383
Directory	/workspace/27.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/27.usbdev_in_iso.3205526318
Short name	T2238
Test name
Test status
Simulation time	182768624 ps
CPU time	1.03 seconds
Started	Aug 01 06:16:25 PM PDT 24
Finished	Aug 01 06:16:26 PM PDT 24
Peak memory	207132 kb
Host	smart-01ab994c-9985-4ac8-96de-a3f0a29a9d35
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3205526318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3205526318
Directory	/workspace/27.usbdev_in_iso/latest

Test location	/workspace/coverage/default/27.usbdev_in_stall.3319864987
Short name	T2533
Test name
Test status
Simulation time	147079223 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:26 PM PDT 24
Finished	Aug 01 06:16:27 PM PDT 24
Peak memory	206928 kb
Host	smart-47bf4f14-5e62-4b7b-8091-f72019aee062
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33198 64987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3319864987
Directory	/workspace/27.usbdev_in_stall/latest

Test location	/workspace/coverage/default/27.usbdev_in_trans.3014182756
Short name	T1016
Test name
Test status
Simulation time	198491201 ps
CPU time	0.94 seconds
Started	Aug 01 06:16:27 PM PDT 24
Finished	Aug 01 06:16:28 PM PDT 24
Peak memory	206928 kb
Host	smart-efd65c91-b649-4a17-a06a-c9cf23efeb23
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30141 82756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3014182756
Directory	/workspace/27.usbdev_in_trans/latest

Test location	/workspace/coverage/default/27.usbdev_invalid_sync.842107668
Short name	T1386
Test name
Test status
Simulation time	3173800507 ps
CPU time	34.15 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:58 PM PDT 24
Peak memory	223500 kb
Host	smart-69e4e9b7-758c-4f1c-a8ca-520c1d6fdd81
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=842107668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.842107668
Directory	/workspace/27.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/27.usbdev_iso_retraction.481461957
Short name	T2438
Test name
Test status
Simulation time	12800155369 ps
CPU time	154.47 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:18:58 PM PDT 24
Peak memory	207168 kb
Host	smart-00478a0d-3c9e-41d3-94bc-29507e1b62db
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=481461957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.481461957
Directory	/workspace/27.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/27.usbdev_link_in_err.1533032895
Short name	T1575
Test name
Test status
Simulation time	203868211 ps
CPU time	0.92 seconds
Started	Aug 01 06:16:26 PM PDT 24
Finished	Aug 01 06:16:27 PM PDT 24
Peak memory	206948 kb
Host	smart-bdd92f55-56c9-468d-8208-563e8aef73d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15330 32895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.1533032895
Directory	/workspace/27.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/27.usbdev_link_suspend.413955945
Short name	T2683
Test name
Test status
Simulation time	3950992975 ps
CPU time	5.64 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:28 PM PDT 24
Peak memory	215304 kb
Host	smart-09bb18da-0a9c-48ca-8958-53441c477e21
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41395 5945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.413955945
Directory	/workspace/27.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/27.usbdev_low_speed_traffic.3695225474
Short name	T1032
Test name
Test status
Simulation time	3184475505 ps
CPU time	29.8 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:53 PM PDT 24
Peak memory	223492 kb
Host	smart-1179c77d-e773-4fd3-93b5-e5b28e534479
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36952 25474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3695225474
Directory	/workspace/27.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2394910963
Short name	T617
Test name
Test status
Simulation time	2368759971 ps
CPU time	22.63 seconds
Started	Aug 01 06:16:27 PM PDT 24
Finished	Aug 01 06:16:49 PM PDT 24
Peak memory	215460 kb
Host	smart-4ce84d21-5e3a-401e-a06c-ae8a13df98ea
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2394910963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2394910963
Directory	/workspace/27.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/27.usbdev_max_length_in_transaction.2906446582
Short name	T1051
Test name
Test status
Simulation time	275517005 ps
CPU time	0.97 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	206944 kb
Host	smart-d0888ee1-3ccb-44bf-804f-240516d9c99d
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2906446582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.2906446582
Directory	/workspace/27.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/27.usbdev_max_length_out_transaction.138651812
Short name	T2392
Test name
Test status
Simulation time	193441101 ps
CPU time	1 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206900 kb
Host	smart-6387e6f8-94c5-4657-8238-d216d41d1955
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13865 1812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.138651812
Directory	/workspace/27.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/27.usbdev_min_inter_pkt_delay.3223136164
Short name	T1651
Test name
Test status
Simulation time	2891716354 ps
CPU time	22.63 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:46 PM PDT 24
Peak memory	223536 kb
Host	smart-12311f43-c14a-4f7a-9bb1-cceb298bfc80
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3223136164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.3223136164
Directory	/workspace/27.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/27.usbdev_min_length_in_transaction.2542998211
Short name	T2506
Test name
Test status
Simulation time	177374912 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:22 PM PDT 24
Finished	Aug 01 06:16:23 PM PDT 24
Peak memory	206924 kb
Host	smart-c7ea34b5-1a67-4966-8416-1f7d4a5347c3
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2542998211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2542998211
Directory	/workspace/27.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/27.usbdev_min_length_out_transaction.1960934561
Short name	T934
Test name
Test status
Simulation time	144067979 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:19 PM PDT 24
Finished	Aug 01 06:16:20 PM PDT 24
Peak memory	206928 kb
Host	smart-32ff2161-01f9-4d3a-b6f3-41af2055a6c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19609 34561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1960934561
Directory	/workspace/27.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/27.usbdev_nak_trans.2721513823
Short name	T1318
Test name
Test status
Simulation time	219115550 ps
CPU time	0.99 seconds
Started	Aug 01 06:16:25 PM PDT 24
Finished	Aug 01 06:16:27 PM PDT 24
Peak memory	206980 kb
Host	smart-50b16465-e704-44df-9e13-4a5f8c4fbf63
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27215 13823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2721513823
Directory	/workspace/27.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/27.usbdev_out_iso.3902197741
Short name	T1087
Test name
Test status
Simulation time	198545530 ps
CPU time	0.98 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206920 kb
Host	smart-71c269a6-5da8-4af8-a79d-bc9e33706e3a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39021 97741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3902197741
Directory	/workspace/27.usbdev_out_iso/latest

Test location	/workspace/coverage/default/27.usbdev_out_stall.1242606505
Short name	T2813
Test name
Test status
Simulation time	164268980 ps
CPU time	0.92 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206896 kb
Host	smart-b991c23b-7a9d-4577-9557-7cf0a1d8002b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12426 06505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1242606505
Directory	/workspace/27.usbdev_out_stall/latest

Test location	/workspace/coverage/default/27.usbdev_out_trans_nak.3905006693
Short name	T1582
Test name
Test status
Simulation time	148887390 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:25 PM PDT 24
Peak memory	206924 kb
Host	smart-5ef3960b-cbf6-4e35-81b2-8ec43ed7af4f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39050 06693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.3905006693
Directory	/workspace/27.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/27.usbdev_pending_in_trans.4006392649
Short name	T1471
Test name
Test status
Simulation time	155034044 ps
CPU time	0.84 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:25 PM PDT 24
Peak memory	206960 kb
Host	smart-3bf579a2-986e-48c5-bc1b-b602acca3902
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40063 92649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.4006392649
Directory	/workspace/27.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/27.usbdev_phy_config_pinflip.3399802299
Short name	T529
Test name
Test status
Simulation time	220546680 ps
CPU time	1.02 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:24 PM PDT 24
Peak memory	206952 kb
Host	smart-081ce247-b6d8-4332-b8e7-afdd015d94b2
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3399802299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3399802299
Directory	/workspace/27.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.4106401722
Short name	T122
Test name
Test status
Simulation time	178085235 ps
CPU time	0.92 seconds
Started	Aug 01 06:16:33 PM PDT 24
Finished	Aug 01 06:16:34 PM PDT 24
Peak memory	206948 kb
Host	smart-f549c14a-f624-439d-8480-533a6266f84e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41064 01722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.4106401722
Directory	/workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/27.usbdev_phy_pins_sense.252585895
Short name	T1253
Test name
Test status
Simulation time	42461429 ps
CPU time	0.72 seconds
Started	Aug 01 06:16:25 PM PDT 24
Finished	Aug 01 06:16:26 PM PDT 24
Peak memory	206888 kb
Host	smart-4900a123-e2d6-4af6-9c7f-fcca2226c045
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25258 5895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.252585895
Directory	/workspace/27.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/27.usbdev_pkt_buffer.706456748
Short name	T2349
Test name
Test status
Simulation time	12067081891 ps
CPU time	29.87 seconds
Started	Aug 01 06:16:24 PM PDT 24
Finished	Aug 01 06:16:54 PM PDT 24
Peak memory	215372 kb
Host	smart-87214294-ed39-42ce-b41b-b2ace3bd5fe4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70645 6748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.706456748
Directory	/workspace/27.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/27.usbdev_pkt_received.1936882710
Short name	T939
Test name
Test status
Simulation time	181849743 ps
CPU time	0.94 seconds
Started	Aug 01 06:16:35 PM PDT 24
Finished	Aug 01 06:16:37 PM PDT 24
Peak memory	206896 kb
Host	smart-6dea5eab-4505-46dc-b966-e550d8022909
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19368 82710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1936882710
Directory	/workspace/27.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/27.usbdev_pkt_sent.1201240231
Short name	T1595
Test name
Test status
Simulation time	214838041 ps
CPU time	0.95 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206908 kb
Host	smart-6780209b-f7d5-4e59-b16d-79939d90cd0d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12012 40231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.1201240231
Directory	/workspace/27.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/27.usbdev_random_length_in_transaction.713807611
Short name	T2016
Test name
Test status
Simulation time	230895368 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:27 PM PDT 24
Finished	Aug 01 06:16:28 PM PDT 24
Peak memory	206988 kb
Host	smart-dffb292f-8049-46ed-826a-22a6c0464506
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71380 7611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.713807611
Directory	/workspace/27.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/27.usbdev_random_length_out_transaction.3208684478
Short name	T646
Test name
Test status
Simulation time	150624592 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206904 kb
Host	smart-597c4829-52b0-4108-88c2-35069010fa1d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086 84478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3208684478
Directory	/workspace/27.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/27.usbdev_rx_crc_err.3228608146
Short name	T1916
Test name
Test status
Simulation time	140416977 ps
CPU time	0.82 seconds
Started	Aug 01 06:16:30 PM PDT 24
Finished	Aug 01 06:16:31 PM PDT 24
Peak memory	206916 kb
Host	smart-a76f7be0-ee3c-42c0-9843-7385a73a9ae0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32286 08146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3228608146
Directory	/workspace/27.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/27.usbdev_rx_full.1432583072
Short name	T2198
Test name
Test status
Simulation time	357367195 ps
CPU time	1.21 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206952 kb
Host	smart-b5d17782-9f3e-43f6-934f-c9cc76692ff1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14325 83072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.1432583072
Directory	/workspace/27.usbdev_rx_full/latest

Test location	/workspace/coverage/default/27.usbdev_setup_stage.4294248826
Short name	T2664
Test name
Test status
Simulation time	151668319 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:30 PM PDT 24
Finished	Aug 01 06:16:31 PM PDT 24
Peak memory	206912 kb
Host	smart-28c69694-a0b4-4c97-a666-e644d104aeee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42942 48826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.4294248826
Directory	/workspace/27.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/27.usbdev_setup_trans_ignored.4263129849
Short name	T2807
Test name
Test status
Simulation time	161003837 ps
CPU time	0.84 seconds
Started	Aug 01 06:16:31 PM PDT 24
Finished	Aug 01 06:16:32 PM PDT 24
Peak memory	206952 kb
Host	smart-47cd8512-e7d6-4aeb-8b02-e9cf838eff1f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42631 29849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.4263129849
Directory	/workspace/27.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/27.usbdev_smoke.1717251995
Short name	T755
Test name
Test status
Simulation time	218199281 ps
CPU time	1.02 seconds
Started	Aug 01 06:16:30 PM PDT 24
Finished	Aug 01 06:16:32 PM PDT 24
Peak memory	206920 kb
Host	smart-05d5b24f-1c07-4fa4-b017-2a282d561a3a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17172 51995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1717251995
Directory	/workspace/27.usbdev_smoke/latest

Test location	/workspace/coverage/default/27.usbdev_spurious_pids_ignored.4147716356
Short name	T1062
Test name
Test status
Simulation time	3316732125 ps
CPU time	33.59 seconds
Started	Aug 01 06:16:30 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	223484 kb
Host	smart-044149cd-c816-431c-88e7-7a91ddf78e1a
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4147716356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.4147716356
Directory	/workspace/27.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/27.usbdev_stall_priority_over_nak.4145419785
Short name	T1184
Test name
Test status
Simulation time	212593492 ps
CPU time	0.95 seconds
Started	Aug 01 06:16:30 PM PDT 24
Finished	Aug 01 06:16:31 PM PDT 24
Peak memory	206912 kb
Host	smart-4c31e4be-7c3d-4b71-891c-ed9211301665
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41454 19785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.4145419785
Directory	/workspace/27.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/27.usbdev_stall_trans.1938121304
Short name	T2123
Test name
Test status
Simulation time	166061182 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:28 PM PDT 24
Finished	Aug 01 06:16:29 PM PDT 24
Peak memory	206928 kb
Host	smart-b6e997e6-ccb4-4ee2-8a8b-a826db0f9c43
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19381 21304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.1938121304
Directory	/workspace/27.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/27.usbdev_stream_len_max.1006975039
Short name	T936
Test name
Test status
Simulation time	631879017 ps
CPU time	1.9 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:37 PM PDT 24
Peak memory	206912 kb
Host	smart-e4c812b1-6071-4fd6-afae-43cb89ceb6eb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10069 75039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.1006975039
Directory	/workspace/27.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/27.usbdev_streaming_out.1157390279
Short name	T910
Test name
Test status
Simulation time	1861497897 ps
CPU time	53.65 seconds
Started	Aug 01 06:16:35 PM PDT 24
Finished	Aug 01 06:17:29 PM PDT 24
Peak memory	215336 kb
Host	smart-52fb7152-8403-411b-966d-c1b2388b906c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11573 90279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1157390279
Directory	/workspace/27.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.2962424160
Short name	T2758
Test name
Test status
Simulation time	2183477294 ps
CPU time	14.19 seconds
Started	Aug 01 06:16:23 PM PDT 24
Finished	Aug 01 06:16:38 PM PDT 24
Peak memory	207424 kb
Host	smart-6d5d033a-a9c8-4669-abf9-6e79ce92ef94
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962424160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos t_handshake.2962424160
Directory	/workspace/27.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/28.usbdev_alert_test.519059365
Short name	T1302
Test name
Test status
Simulation time	56432126 ps
CPU time	0.69 seconds
Started	Aug 01 06:16:40 PM PDT 24
Finished	Aug 01 06:16:41 PM PDT 24
Peak memory	206988 kb
Host	smart-8d91e04f-dedc-40b1-bf61-75664ac3ab7d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=519059365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.519059365
Directory	/workspace/28.usbdev_alert_test/latest

Test location	/workspace/coverage/default/28.usbdev_av_buffer.1870930449
Short name	T2685
Test name
Test status
Simulation time	171586437 ps
CPU time	0.9 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206964 kb
Host	smart-3e9f9aa9-3bfe-4be0-bb1b-acb8f6e7b42f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18709 30449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1870930449
Directory	/workspace/28.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/28.usbdev_bitstuff_err.3546588742
Short name	T1741
Test name
Test status
Simulation time	168616106 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:37 PM PDT 24
Finished	Aug 01 06:16:38 PM PDT 24
Peak memory	206912 kb
Host	smart-41bd5a47-e048-4492-b7fd-d47d4c050d6d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35465 88742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3546588742
Directory	/workspace/28.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/28.usbdev_data_toggle_clear.2985408251
Short name	T82
Test name
Test status
Simulation time	534922412 ps
CPU time	1.69 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:37 PM PDT 24
Peak memory	206924 kb
Host	smart-62e8eb58-daab-455c-a493-d319ee7488dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29854 08251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2985408251
Directory	/workspace/28.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/28.usbdev_data_toggle_restore.3862801972
Short name	T992
Test name
Test status
Simulation time	1409765261 ps
CPU time	3.57 seconds
Started	Aug 01 06:16:31 PM PDT 24
Finished	Aug 01 06:16:35 PM PDT 24
Peak memory	207172 kb
Host	smart-5ab1b10e-61a7-4790-9d78-2d6c96f5b9e1
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3862801972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3862801972
Directory	/workspace/28.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/28.usbdev_device_address.1539960407
Short name	T459
Test name
Test status
Simulation time	46164505538 ps
CPU time	69.18 seconds
Started	Aug 01 06:16:33 PM PDT 24
Finished	Aug 01 06:17:42 PM PDT 24
Peak memory	207136 kb
Host	smart-d82acfe0-af20-40e0-93bb-5af301b29b1a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15399 60407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1539960407
Directory	/workspace/28.usbdev_device_address/latest

Test location	/workspace/coverage/default/28.usbdev_device_timeout.1071125199
Short name	T1221
Test name
Test status
Simulation time	5286032903 ps
CPU time	45.7 seconds
Started	Aug 01 06:16:39 PM PDT 24
Finished	Aug 01 06:17:25 PM PDT 24
Peak memory	207208 kb
Host	smart-4b0ee232-5986-4ce0-8171-42aa9c8f2e3e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071125199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.1071125199
Directory	/workspace/28.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/28.usbdev_disable_endpoint.2912757671
Short name	T829
Test name
Test status
Simulation time	1171521063 ps
CPU time	2.42 seconds
Started	Aug 01 06:16:39 PM PDT 24
Finished	Aug 01 06:16:42 PM PDT 24
Peak memory	206940 kb
Host	smart-0a494518-0c2b-468f-b45f-4ed6b4f7246a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29127 57671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.2912757671
Directory	/workspace/28.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/28.usbdev_disconnected.2736988408
Short name	T2730
Test name
Test status
Simulation time	149237129 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:37 PM PDT 24
Finished	Aug 01 06:16:38 PM PDT 24
Peak memory	206908 kb
Host	smart-7bd0fd8f-30e7-4310-ab6c-dde4fee4d844
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27369 88408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2736988408
Directory	/workspace/28.usbdev_disconnected/latest

Test location	/workspace/coverage/default/28.usbdev_enable.3166970347
Short name	T1600
Test name
Test status
Simulation time	64269024 ps
CPU time	0.73 seconds
Started	Aug 01 06:16:28 PM PDT 24
Finished	Aug 01 06:16:29 PM PDT 24
Peak memory	206920 kb
Host	smart-f08c260a-ce48-48f4-8dfa-81f1df0faea3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669 70347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3166970347
Directory	/workspace/28.usbdev_enable/latest

Test location	/workspace/coverage/default/28.usbdev_endpoint_access.3135354201
Short name	T2502
Test name
Test status
Simulation time	904078960 ps
CPU time	2.56 seconds
Started	Aug 01 06:16:31 PM PDT 24
Finished	Aug 01 06:16:33 PM PDT 24
Peak memory	207184 kb
Host	smart-b3e055c6-4828-4e7f-889f-a1c70c870843
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31353 54201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3135354201
Directory	/workspace/28.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/28.usbdev_endpoint_types.3783929541
Short name	T1427
Test name
Test status
Simulation time	258245458 ps
CPU time	1.05 seconds
Started	Aug 01 06:16:36 PM PDT 24
Finished	Aug 01 06:16:37 PM PDT 24
Peak memory	206928 kb
Host	smart-4e104044-8087-499b-8640-3a26ccb8a1e4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3783929541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.3783929541
Directory	/workspace/28.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/28.usbdev_fifo_rst.740776421
Short name	T114
Test name
Test status
Simulation time	225179370 ps
CPU time	1.52 seconds
Started	Aug 01 06:16:28 PM PDT 24
Finished	Aug 01 06:16:30 PM PDT 24
Peak memory	207092 kb
Host	smart-aa95de9c-fb11-4e72-88d3-5ccd0ee41c1a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74077 6421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.740776421
Directory	/workspace/28.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/28.usbdev_in_iso.4144498193
Short name	T561
Test name
Test status
Simulation time	221951846 ps
CPU time	1.03 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	215316 kb
Host	smart-12104618-b893-47db-8d87-b426d5df96cb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4144498193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.4144498193
Directory	/workspace/28.usbdev_in_iso/latest

Test location	/workspace/coverage/default/28.usbdev_in_stall.3630043096
Short name	T2262
Test name
Test status
Simulation time	140085878 ps
CPU time	0.82 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206916 kb
Host	smart-a650061e-ab63-4704-b815-9d068c4732e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36300 43096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.3630043096
Directory	/workspace/28.usbdev_in_stall/latest

Test location	/workspace/coverage/default/28.usbdev_in_trans.4081478157
Short name	T1105
Test name
Test status
Simulation time	178761968 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:35 PM PDT 24
Peak memory	206972 kb
Host	smart-0cddb47e-570a-4382-816b-2d2cb6953628
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40814 78157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.4081478157
Directory	/workspace/28.usbdev_in_trans/latest

Test location	/workspace/coverage/default/28.usbdev_invalid_sync.3232233576
Short name	T826
Test name
Test status
Simulation time	4059257339 ps
CPU time	32.52 seconds
Started	Aug 01 06:16:32 PM PDT 24
Finished	Aug 01 06:17:05 PM PDT 24
Peak memory	223576 kb
Host	smart-2d783251-6b6a-498e-92ac-865c5f5cb7cd
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3232233576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3232233576
Directory	/workspace/28.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/28.usbdev_iso_retraction.93428391
Short name	T789
Test name
Test status
Simulation time	14716914957 ps
CPU time	97.53 seconds
Started	Aug 01 06:16:29 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	207176 kb
Host	smart-52a56ced-fc73-42c6-95bd-224caf56c8de
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=93428391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.93428391
Directory	/workspace/28.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/28.usbdev_link_in_err.4055211278
Short name	T590
Test name
Test status
Simulation time	223819348 ps
CPU time	1.01 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206940 kb
Host	smart-9faa972a-39bd-49ba-9acd-bfb4bab0202e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40552 11278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.4055211278
Directory	/workspace/28.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/28.usbdev_link_suspend.3527334443
Short name	T99
Test name
Test status
Simulation time	5051209948 ps
CPU time	7.1 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:42 PM PDT 24
Peak memory	215428 kb
Host	smart-af008cfd-a69f-4f9b-ac76-2e93cb77a933
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35273 34443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3527334443
Directory	/workspace/28.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/28.usbdev_low_speed_traffic.1446459696
Short name	T2826
Test name
Test status
Simulation time	2819376886 ps
CPU time	27.37 seconds
Started	Aug 01 06:16:28 PM PDT 24
Finished	Aug 01 06:16:55 PM PDT 24
Peak memory	215272 kb
Host	smart-511bf6ec-ea9c-4243-9fb2-494b6addf21e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14464 59696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.1446459696
Directory	/workspace/28.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/28.usbdev_max_inter_pkt_delay.697965056
Short name	T2804
Test name
Test status
Simulation time	2197526369 ps
CPU time	62.67 seconds
Started	Aug 01 06:16:31 PM PDT 24
Finished	Aug 01 06:17:34 PM PDT 24
Peak memory	216708 kb
Host	smart-b5bfdaa7-5130-4a88-8dbd-b69fd522adc6
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=697965056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.697965056
Directory	/workspace/28.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/28.usbdev_max_length_in_transaction.662792825
Short name	T1176
Test name
Test status
Simulation time	260844542 ps
CPU time	1.01 seconds
Started	Aug 01 06:16:33 PM PDT 24
Finished	Aug 01 06:16:34 PM PDT 24
Peak memory	206916 kb
Host	smart-08e7e574-eb86-4466-a9e2-85396a22ee9d
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=662792825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.662792825
Directory	/workspace/28.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/28.usbdev_max_length_out_transaction.307358855
Short name	T2687
Test name
Test status
Simulation time	203037098 ps
CPU time	0.91 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206980 kb
Host	smart-342d7d5a-f3ec-4687-8010-6e1a21ad6540
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30735 8855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.307358855
Directory	/workspace/28.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2098278339
Short name	T1238
Test name
Test status
Simulation time	2486828008 ps
CPU time	72.45 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:17:48 PM PDT 24
Peak memory	216716 kb
Host	smart-8d9502da-bb70-46f6-b40c-5bf592ec8e13
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2098278339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2098278339
Directory	/workspace/28.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/28.usbdev_min_length_in_transaction.2289801688
Short name	T1609
Test name
Test status
Simulation time	157287418 ps
CPU time	0.9 seconds
Started	Aug 01 06:16:41 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	206864 kb
Host	smart-0e42b556-0c13-42b7-8dbf-027fe52364c6
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2289801688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2289801688
Directory	/workspace/28.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/28.usbdev_min_length_out_transaction.2185983177
Short name	T1579
Test name
Test status
Simulation time	223862444 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:38 PM PDT 24
Finished	Aug 01 06:16:39 PM PDT 24
Peak memory	206980 kb
Host	smart-024bce18-ae10-4477-8a7b-10e5c256e937
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21859 83177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2185983177
Directory	/workspace/28.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/28.usbdev_nak_trans.1354910978
Short name	T2655
Test name
Test status
Simulation time	209724031 ps
CPU time	1 seconds
Started	Aug 01 06:16:36 PM PDT 24
Finished	Aug 01 06:16:38 PM PDT 24
Peak memory	206948 kb
Host	smart-9bd25962-3deb-4b46-9075-7095a7acd6fb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13549 10978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1354910978
Directory	/workspace/28.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/28.usbdev_out_iso.474896036
Short name	T2050
Test name
Test status
Simulation time	169469411 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:35 PM PDT 24
Finished	Aug 01 06:16:37 PM PDT 24
Peak memory	206948 kb
Host	smart-6ad8d7a2-a9ed-4330-b5b9-b040cd95dd6c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47489 6036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.474896036
Directory	/workspace/28.usbdev_out_iso/latest

Test location	/workspace/coverage/default/28.usbdev_out_stall.3644800595
Short name	T1952
Test name
Test status
Simulation time	192494201 ps
CPU time	0.91 seconds
Started	Aug 01 06:16:39 PM PDT 24
Finished	Aug 01 06:16:41 PM PDT 24
Peak memory	206968 kb
Host	smart-134f4c74-a646-4165-bd2d-0a0ed90618e0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36448 00595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3644800595
Directory	/workspace/28.usbdev_out_stall/latest

Test location	/workspace/coverage/default/28.usbdev_out_trans_nak.420843870
Short name	T1792
Test name
Test status
Simulation time	175471226 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:29 PM PDT 24
Finished	Aug 01 06:16:30 PM PDT 24
Peak memory	206916 kb
Host	smart-8fe813b4-6525-414c-95e7-2fde54da9810
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42084 3870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.420843870
Directory	/workspace/28.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/28.usbdev_pending_in_trans.448079073
Short name	T212
Test name
Test status
Simulation time	196611195 ps
CPU time	0.92 seconds
Started	Aug 01 06:16:36 PM PDT 24
Finished	Aug 01 06:16:37 PM PDT 24
Peak memory	206956 kb
Host	smart-695fdb91-5a66-4c73-a46f-f254be4df2cb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44807 9073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.448079073
Directory	/workspace/28.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2776566800
Short name	T1314
Test name
Test status
Simulation time	155371079 ps
CPU time	0.86 seconds
Started	Aug 01 06:16:37 PM PDT 24
Finished	Aug 01 06:16:38 PM PDT 24
Peak memory	206920 kb
Host	smart-03570814-a5be-4b03-a77b-ccda9c53d37c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27765 66800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2776566800
Directory	/workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/28.usbdev_phy_pins_sense.3808816396
Short name	T1951
Test name
Test status
Simulation time	73661590 ps
CPU time	0.74 seconds
Started	Aug 01 06:16:38 PM PDT 24
Finished	Aug 01 06:16:39 PM PDT 24
Peak memory	206912 kb
Host	smart-5af41bab-a30c-4de5-8c21-547ef00e16c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38088 16396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3808816396
Directory	/workspace/28.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/28.usbdev_pkt_buffer.1331974276
Short name	T251
Test name
Test status
Simulation time	7014846803 ps
CPU time	16.97 seconds
Started	Aug 01 06:16:32 PM PDT 24
Finished	Aug 01 06:16:49 PM PDT 24
Peak memory	215380 kb
Host	smart-481bc0e4-8b08-455e-9737-9aba9b2de7f6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13319 74276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1331974276
Directory	/workspace/28.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/28.usbdev_pkt_received.2614351192
Short name	T1216
Test name
Test status
Simulation time	186590684 ps
CPU time	0.92 seconds
Started	Aug 01 06:16:36 PM PDT 24
Finished	Aug 01 06:16:37 PM PDT 24
Peak memory	206948 kb
Host	smart-517d3195-c0c6-4c77-8d25-d0f3878231c8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26143 51192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2614351192
Directory	/workspace/28.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/28.usbdev_pkt_sent.3485464687
Short name	T2067
Test name
Test status
Simulation time	204692399 ps
CPU time	0.98 seconds
Started	Aug 01 06:16:32 PM PDT 24
Finished	Aug 01 06:16:33 PM PDT 24
Peak memory	206928 kb
Host	smart-d8d11c3d-c864-40d2-a990-40bec6d7aedf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34854 64687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.3485464687
Directory	/workspace/28.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/28.usbdev_random_length_in_transaction.1954653408
Short name	T2134
Test name
Test status
Simulation time	225060350 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:41 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	206868 kb
Host	smart-5ba9fb83-2239-41cd-825e-bf7befe2a3a7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19546 53408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.1954653408
Directory	/workspace/28.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/28.usbdev_random_length_out_transaction.4002179537
Short name	T1418
Test name
Test status
Simulation time	167321958 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:31 PM PDT 24
Finished	Aug 01 06:16:32 PM PDT 24
Peak memory	206944 kb
Host	smart-11cbbf1a-3f3d-4eb3-b527-1cadf4cb1ee4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40021 79537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.4002179537
Directory	/workspace/28.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/28.usbdev_rx_crc_err.3281623110
Short name	T59
Test name
Test status
Simulation time	176965156 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:34 PM PDT 24
Finished	Aug 01 06:16:36 PM PDT 24
Peak memory	206972 kb
Host	smart-ad33b97d-a345-472b-8f67-ef87fc6c1442
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32816 23110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3281623110
Directory	/workspace/28.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/28.usbdev_setup_stage.2713290653
Short name	T2386
Test name
Test status
Simulation time	152321780 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:30 PM PDT 24
Finished	Aug 01 06:16:31 PM PDT 24
Peak memory	206908 kb
Host	smart-dcd1edf9-3dc2-44fc-9aee-d656a9217c10
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27132 90653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.2713290653
Directory	/workspace/28.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/28.usbdev_setup_trans_ignored.2875079088
Short name	T1154
Test name
Test status
Simulation time	149843415 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:41 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	206864 kb
Host	smart-10ea555e-6c41-4837-90ed-7f29900b471c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28750 79088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2875079088
Directory	/workspace/28.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/28.usbdev_smoke.3529667406
Short name	T18
Test name
Test status
Simulation time	283029492 ps
CPU time	1.26 seconds
Started	Aug 01 06:16:38 PM PDT 24
Finished	Aug 01 06:16:39 PM PDT 24
Peak memory	206952 kb
Host	smart-9af68f00-ec81-4523-8f24-c6ace84a2413
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35296 67406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.3529667406
Directory	/workspace/28.usbdev_smoke/latest

Test location	/workspace/coverage/default/28.usbdev_spurious_pids_ignored.994145149
Short name	T1648
Test name
Test status
Simulation time	1585011336 ps
CPU time	41.51 seconds
Started	Aug 01 06:16:31 PM PDT 24
Finished	Aug 01 06:17:12 PM PDT 24
Peak memory	216880 kb
Host	smart-15b13628-b40c-4c59-808d-7ab8e24e1f9a
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=994145149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.994145149
Directory	/workspace/28.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/28.usbdev_stall_priority_over_nak.3923005953
Short name	T914
Test name
Test status
Simulation time	185288642 ps
CPU time	0.92 seconds
Started	Aug 01 06:16:41 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	206812 kb
Host	smart-63ff412b-c337-4d23-9ac7-2aa92c858395
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39230 05953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3923005953
Directory	/workspace/28.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/28.usbdev_stall_trans.584560795
Short name	T2243
Test name
Test status
Simulation time	180318966 ps
CPU time	0.9 seconds
Started	Aug 01 06:16:32 PM PDT 24
Finished	Aug 01 06:16:33 PM PDT 24
Peak memory	206928 kb
Host	smart-903cf5a4-c876-4f37-abb1-35cc6d31623c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58456 0795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.584560795
Directory	/workspace/28.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/28.usbdev_stream_len_max.147654746
Short name	T1258
Test name
Test status
Simulation time	224442612 ps
CPU time	1.02 seconds
Started	Aug 01 06:16:46 PM PDT 24
Finished	Aug 01 06:16:47 PM PDT 24
Peak memory	206920 kb
Host	smart-a4c9f34a-c86a-4c2c-bc8f-c3ef25e42ca2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14765 4746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.147654746
Directory	/workspace/28.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/28.usbdev_streaming_out.1919838404
Short name	T2594
Test name
Test status
Simulation time	2753347194 ps
CPU time	71.76 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	215308 kb
Host	smart-950c1555-0ebc-4ce0-86e8-4b5dc0d3620d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19198 38404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1919838404
Directory	/workspace/28.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.1462269229
Short name	T965
Test name
Test status
Simulation time	3021665681 ps
CPU time	27.17 seconds
Started	Aug 01 06:16:30 PM PDT 24
Finished	Aug 01 06:16:58 PM PDT 24
Peak memory	207200 kb
Host	smart-c2435f4b-9577-4ced-8c20-b987804953f3
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462269229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos t_handshake.1462269229
Directory	/workspace/28.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/29.usbdev_alert_test.600557677
Short name	T1340
Test name
Test status
Simulation time	30928353 ps
CPU time	0.65 seconds
Started	Aug 01 06:16:52 PM PDT 24
Finished	Aug 01 06:16:53 PM PDT 24
Peak memory	206984 kb
Host	smart-a9af02eb-d556-4f22-95de-d16debac43b3
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=600557677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.600557677
Directory	/workspace/29.usbdev_alert_test/latest

Test location	/workspace/coverage/default/29.usbdev_av_buffer.1695779479
Short name	T1584
Test name
Test status
Simulation time	169738851 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:16:52 PM PDT 24
Peak memory	206848 kb
Host	smart-588b3986-0595-43d6-99b6-399cae9c23ef
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957 79479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.1695779479
Directory	/workspace/29.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/29.usbdev_bitstuff_err.451781425
Short name	T1920
Test name
Test status
Simulation time	138209223 ps
CPU time	0.81 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	206920 kb
Host	smart-425e3fa7-7add-471d-a080-aa7b75d5dd22
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45178 1425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.451781425
Directory	/workspace/29.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/29.usbdev_data_toggle_clear.2227538889
Short name	T2193
Test name
Test status
Simulation time	633792926 ps
CPU time	2.24 seconds
Started	Aug 01 06:16:41 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	207100 kb
Host	smart-d41ea1c6-7b6d-4ec3-a80e-1ebcb14209f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22275 38889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.2227538889
Directory	/workspace/29.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/29.usbdev_data_toggle_restore.3340933576
Short name	T1636
Test name
Test status
Simulation time	1274286175 ps
CPU time	3.24 seconds
Started	Aug 01 06:16:36 PM PDT 24
Finished	Aug 01 06:16:40 PM PDT 24
Peak memory	207108 kb
Host	smart-6614ef0b-45d8-46c2-a790-03c200e436cf
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3340933576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.3340933576
Directory	/workspace/29.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/29.usbdev_device_address.3055164902
Short name	T2583
Test name
Test status
Simulation time	15725786526 ps
CPU time	25.37 seconds
Started	Aug 01 06:16:46 PM PDT 24
Finished	Aug 01 06:17:11 PM PDT 24
Peak memory	207188 kb
Host	smart-df4c3c26-83e2-44ab-a80f-b57fe784518e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551 64902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3055164902
Directory	/workspace/29.usbdev_device_address/latest

Test location	/workspace/coverage/default/29.usbdev_device_timeout.1839514965
Short name	T2282
Test name
Test status
Simulation time	1696272637 ps
CPU time	38.71 seconds
Started	Aug 01 06:16:43 PM PDT 24
Finished	Aug 01 06:17:22 PM PDT 24
Peak memory	207084 kb
Host	smart-74d8ce06-d722-4ab5-9301-3b022a7d4e7e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839514965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.1839514965
Directory	/workspace/29.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/29.usbdev_disable_endpoint.1834512814
Short name	T1645
Test name
Test status
Simulation time	1084873236 ps
CPU time	2.14 seconds
Started	Aug 01 06:16:41 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	206872 kb
Host	smart-0a90ef79-73e9-46c0-9050-0f101f31fe8d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18345 12814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1834512814
Directory	/workspace/29.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/29.usbdev_disconnected.2395941352
Short name	T1334
Test name
Test status
Simulation time	139253127 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:40 PM PDT 24
Finished	Aug 01 06:16:42 PM PDT 24
Peak memory	206888 kb
Host	smart-9acb13e0-4835-428d-b3c9-b6b3b9c7a96e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959 41352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2395941352
Directory	/workspace/29.usbdev_disconnected/latest

Test location	/workspace/coverage/default/29.usbdev_enable.2635662033
Short name	T618
Test name
Test status
Simulation time	42214850 ps
CPU time	0.71 seconds
Started	Aug 01 06:16:39 PM PDT 24
Finished	Aug 01 06:16:40 PM PDT 24
Peak memory	206900 kb
Host	smart-c5b1bf22-4f8a-4c4d-a5a8-e5487c73ad0d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26356 62033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2635662033
Directory	/workspace/29.usbdev_enable/latest

Test location	/workspace/coverage/default/29.usbdev_endpoint_access.2007081827
Short name	T1030
Test name
Test status
Simulation time	722082716 ps
CPU time	2.05 seconds
Started	Aug 01 06:16:40 PM PDT 24
Finished	Aug 01 06:16:42 PM PDT 24
Peak memory	207112 kb
Host	smart-8ad92a5f-75f7-4e62-8292-f3eac99077f2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20070 81827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.2007081827
Directory	/workspace/29.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/29.usbdev_endpoint_types.1361051903
Short name	T375
Test name
Test status
Simulation time	477482555 ps
CPU time	1.3 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	206888 kb
Host	smart-619b42be-77dc-4fd8-ab2e-e1a845b43f63
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1361051903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.1361051903
Directory	/workspace/29.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/29.usbdev_fifo_rst.3509984961
Short name	T1974
Test name
Test status
Simulation time	223035761 ps
CPU time	1.37 seconds
Started	Aug 01 06:16:41 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	207176 kb
Host	smart-39ac12d4-0452-4817-89ea-e70bd74c319d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35099 84961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3509984961
Directory	/workspace/29.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/29.usbdev_in_iso.2967328631
Short name	T2728
Test name
Test status
Simulation time	181640403 ps
CPU time	0.97 seconds
Started	Aug 01 06:16:41 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	206868 kb
Host	smart-873b3ee1-4625-47a7-bef6-76c2e355fa9e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2967328631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2967328631
Directory	/workspace/29.usbdev_in_iso/latest

Test location	/workspace/coverage/default/29.usbdev_in_stall.2378455929
Short name	T2439
Test name
Test status
Simulation time	172619218 ps
CPU time	0.81 seconds
Started	Aug 01 06:16:40 PM PDT 24
Finished	Aug 01 06:16:42 PM PDT 24
Peak memory	206896 kb
Host	smart-9eb65961-6202-4bfa-abdb-cb94c2d1969d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23784 55929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2378455929
Directory	/workspace/29.usbdev_in_stall/latest

Test location	/workspace/coverage/default/29.usbdev_in_trans.3200508616
Short name	T817
Test name
Test status
Simulation time	229549631 ps
CPU time	0.98 seconds
Started	Aug 01 06:16:43 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	206948 kb
Host	smart-8e0fcd9b-c25d-446a-b7c6-bff761296a0f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32005 08616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3200508616
Directory	/workspace/29.usbdev_in_trans/latest

Test location	/workspace/coverage/default/29.usbdev_invalid_sync.881975356
Short name	T1793
Test name
Test status
Simulation time	3681051877 ps
CPU time	34.5 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:17:26 PM PDT 24
Peak memory	223540 kb
Host	smart-bbb4b7a3-ba54-42e9-b7ae-47a8531bae59
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=881975356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.881975356
Directory	/workspace/29.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/29.usbdev_iso_retraction.1088793078
Short name	T1338
Test name
Test status
Simulation time	4695838447 ps
CPU time	53.91 seconds
Started	Aug 01 06:16:43 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	207140 kb
Host	smart-2cbd672d-664c-4648-843f-b2e92b1460e8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1088793078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1088793078
Directory	/workspace/29.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/29.usbdev_link_in_err.2377977159
Short name	T2164
Test name
Test status
Simulation time	243363816 ps
CPU time	1.05 seconds
Started	Aug 01 06:16:39 PM PDT 24
Finished	Aug 01 06:16:40 PM PDT 24
Peak memory	206924 kb
Host	smart-18c4f7c7-bb08-41b7-a11c-88d57b7f9393
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23779 77159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2377977159
Directory	/workspace/29.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/29.usbdev_link_suspend.1418744618
Short name	T2271
Test name
Test status
Simulation time	8454347949 ps
CPU time	11.6 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:16:54 PM PDT 24
Peak memory	207164 kb
Host	smart-dacd201f-fe94-49c3-a5c1-dea6fc10f954
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14187 44618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1418744618
Directory	/workspace/29.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/29.usbdev_low_speed_traffic.2340447881
Short name	T1077
Test name
Test status
Simulation time	3443190563 ps
CPU time	29.61 seconds
Started	Aug 01 06:16:43 PM PDT 24
Finished	Aug 01 06:17:13 PM PDT 24
Peak memory	223496 kb
Host	smart-64d0f517-176a-4c1c-82fe-f6db6ff81bac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23404 47881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.2340447881
Directory	/workspace/29.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/29.usbdev_max_inter_pkt_delay.3692650465
Short name	T998
Test name
Test status
Simulation time	3625077579 ps
CPU time	100.95 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:18:23 PM PDT 24
Peak memory	216696 kb
Host	smart-f5eac1cd-3d54-4d5e-81c2-d10b25f3d134
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3692650465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.3692650465
Directory	/workspace/29.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/29.usbdev_max_length_in_transaction.142513241
Short name	T245
Test name
Test status
Simulation time	265096665 ps
CPU time	0.98 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	206864 kb
Host	smart-bc892655-daf0-4f9a-a7af-a454f3422028
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=142513241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.142513241
Directory	/workspace/29.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/29.usbdev_max_length_out_transaction.2018247237
Short name	T2865
Test name
Test status
Simulation time	202806159 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	206952 kb
Host	smart-6f905f88-c823-450d-b1ad-d4aefd07dca6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20182 47237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2018247237
Directory	/workspace/29.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/29.usbdev_min_inter_pkt_delay.631770952
Short name	T747
Test name
Test status
Simulation time	2806852387 ps
CPU time	77.14 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:18:00 PM PDT 24
Peak memory	215332 kb
Host	smart-d1e8b61b-1942-479c-bdf4-f2b500d7ca08
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=631770952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.631770952
Directory	/workspace/29.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/29.usbdev_min_length_in_transaction.2457551279
Short name	T1751
Test name
Test status
Simulation time	156550480 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:45 PM PDT 24
Finished	Aug 01 06:16:46 PM PDT 24
Peak memory	206916 kb
Host	smart-62313ce0-6e52-4e23-a2fa-c6ae31e48b54
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2457551279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2457551279
Directory	/workspace/29.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/29.usbdev_min_length_out_transaction.3237992214
Short name	T787
Test name
Test status
Simulation time	145124524 ps
CPU time	0.81 seconds
Started	Aug 01 06:16:45 PM PDT 24
Finished	Aug 01 06:16:46 PM PDT 24
Peak memory	206988 kb
Host	smart-9e384682-8fa0-4f33-a562-98171fa5cb54
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32379 92214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3237992214
Directory	/workspace/29.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/29.usbdev_nak_trans.314002131
Short name	T184
Test name
Test status
Simulation time	238530224 ps
CPU time	0.93 seconds
Started	Aug 01 06:16:40 PM PDT 24
Finished	Aug 01 06:16:42 PM PDT 24
Peak memory	206928 kb
Host	smart-79ce9347-a266-4836-8390-b4ca874990fe
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31400 2131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.314002131
Directory	/workspace/29.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/29.usbdev_out_iso.2117823989
Short name	T2431
Test name
Test status
Simulation time	148740520 ps
CPU time	0.82 seconds
Started	Aug 01 06:16:43 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	206944 kb
Host	smart-56fc9daa-21f3-4bef-a424-06db5baccafc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21178 23989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2117823989
Directory	/workspace/29.usbdev_out_iso/latest

Test location	/workspace/coverage/default/29.usbdev_out_stall.1355093758
Short name	T616
Test name
Test status
Simulation time	166273983 ps
CPU time	0.86 seconds
Started	Aug 01 06:16:43 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	206908 kb
Host	smart-6f789932-df74-4873-9e5f-586923fa2d25
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13550 93758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.1355093758
Directory	/workspace/29.usbdev_out_stall/latest

Test location	/workspace/coverage/default/29.usbdev_out_trans_nak.278395161
Short name	T647
Test name
Test status
Simulation time	226913605 ps
CPU time	0.94 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	206940 kb
Host	smart-8ca5f344-c6f0-4b65-9d36-e2acd33af9fc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27839 5161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.278395161
Directory	/workspace/29.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/29.usbdev_pending_in_trans.922249006
Short name	T2568
Test name
Test status
Simulation time	158855646 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:44 PM PDT 24
Finished	Aug 01 06:16:45 PM PDT 24
Peak memory	206912 kb
Host	smart-eb79f09c-9478-48e8-8d1f-c9fb5c96ec3c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92224 9006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.922249006
Directory	/workspace/29.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/29.usbdev_phy_config_pinflip.2332130247
Short name	T582
Test name
Test status
Simulation time	245372481 ps
CPU time	1.02 seconds
Started	Aug 01 06:16:45 PM PDT 24
Finished	Aug 01 06:16:46 PM PDT 24
Peak memory	206964 kb
Host	smart-194f4beb-bc70-453f-93f6-ac4ade40da0e
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2332130247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.2332130247
Directory	/workspace/29.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3045138621
Short name	T2770
Test name
Test status
Simulation time	164773257 ps
CPU time	0.86 seconds
Started	Aug 01 06:16:45 PM PDT 24
Finished	Aug 01 06:16:46 PM PDT 24
Peak memory	206956 kb
Host	smart-d1e9889e-6265-4e54-b48d-c6ca883bd6e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30451 38621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3045138621
Directory	/workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/29.usbdev_phy_pins_sense.3877529746
Short name	T2286
Test name
Test status
Simulation time	90216379 ps
CPU time	0.74 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:16:52 PM PDT 24
Peak memory	206804 kb
Host	smart-62abb9f9-2c04-4bc5-902e-0092ac9ee9c8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38775 29746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3877529746
Directory	/workspace/29.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/29.usbdev_pkt_received.3222652304
Short name	T2120
Test name
Test status
Simulation time	176232227 ps
CPU time	0.91 seconds
Started	Aug 01 06:16:46 PM PDT 24
Finished	Aug 01 06:16:47 PM PDT 24
Peak memory	206948 kb
Host	smart-9f511365-848e-439c-be02-a4f02f834225
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32226 52304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.3222652304
Directory	/workspace/29.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/29.usbdev_pkt_sent.392164902
Short name	T2601
Test name
Test status
Simulation time	175465487 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:45 PM PDT 24
Finished	Aug 01 06:16:46 PM PDT 24
Peak memory	206632 kb
Host	smart-803ce01a-0dba-41d0-8ac6-ce94fa50c98d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39216 4902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.392164902
Directory	/workspace/29.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/29.usbdev_random_length_in_transaction.3569544412
Short name	T2628
Test name
Test status
Simulation time	203892116 ps
CPU time	0.97 seconds
Started	Aug 01 06:16:42 PM PDT 24
Finished	Aug 01 06:16:43 PM PDT 24
Peak memory	206964 kb
Host	smart-f52d53df-4c05-423a-b095-01aa66781d1f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35695 44412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.3569544412
Directory	/workspace/29.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/29.usbdev_random_length_out_transaction.3170852505
Short name	T10
Test name
Test status
Simulation time	153230950 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:40 PM PDT 24
Finished	Aug 01 06:16:42 PM PDT 24
Peak memory	206964 kb
Host	smart-3711c016-5662-4953-a53b-d128a579dfdb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31708 52505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3170852505
Directory	/workspace/29.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/29.usbdev_rx_crc_err.1438816770
Short name	T1959
Test name
Test status
Simulation time	159013252 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:44 PM PDT 24
Finished	Aug 01 06:16:45 PM PDT 24
Peak memory	206916 kb
Host	smart-b7c2306f-63d4-4ee6-884a-71e4fdd26ed4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14388 16770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1438816770
Directory	/workspace/29.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/29.usbdev_rx_full.2015990281
Short name	T280
Test name
Test status
Simulation time	262920723 ps
CPU time	1.08 seconds
Started	Aug 01 06:16:45 PM PDT 24
Finished	Aug 01 06:16:46 PM PDT 24
Peak memory	206944 kb
Host	smart-c9b6a5c3-90c5-4945-ac59-4e1cb6331776
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20159 90281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.2015990281
Directory	/workspace/29.usbdev_rx_full/latest

Test location	/workspace/coverage/default/29.usbdev_setup_stage.3476539287
Short name	T2256
Test name
Test status
Simulation time	154773765 ps
CPU time	0.86 seconds
Started	Aug 01 06:16:43 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	206868 kb
Host	smart-c023b1ce-7a92-4bc7-a6ae-0a1551c8c181
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34765 39287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.3476539287
Directory	/workspace/29.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/29.usbdev_setup_trans_ignored.3729635046
Short name	T850
Test name
Test status
Simulation time	150805220 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:16:52 PM PDT 24
Peak memory	206912 kb
Host	smart-426fa428-711f-4176-be7d-6be1addd429e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37296 35046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3729635046
Directory	/workspace/29.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/29.usbdev_smoke.2025300277
Short name	T1810
Test name
Test status
Simulation time	241985268 ps
CPU time	1.05 seconds
Started	Aug 01 06:16:46 PM PDT 24
Finished	Aug 01 06:16:48 PM PDT 24
Peak memory	206956 kb
Host	smart-45effc6f-7012-433a-87e8-a4fd9c9e0723
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20253 00277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2025300277
Directory	/workspace/29.usbdev_smoke/latest

Test location	/workspace/coverage/default/29.usbdev_spurious_pids_ignored.3531556048
Short name	T1591
Test name
Test status
Simulation time	2802835277 ps
CPU time	20.83 seconds
Started	Aug 01 06:16:45 PM PDT 24
Finished	Aug 01 06:17:07 PM PDT 24
Peak memory	215428 kb
Host	smart-c2ebede8-a509-43b8-937f-c9b0e6516b03
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3531556048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3531556048
Directory	/workspace/29.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/29.usbdev_stall_priority_over_nak.3591488525
Short name	T2821
Test name
Test status
Simulation time	191005413 ps
CPU time	0.93 seconds
Started	Aug 01 06:16:45 PM PDT 24
Finished	Aug 01 06:16:46 PM PDT 24
Peak memory	206632 kb
Host	smart-1e740a63-dcf6-4f78-974a-d42405b59ac8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35914 88525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3591488525
Directory	/workspace/29.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/29.usbdev_stall_trans.4079690109
Short name	T2588
Test name
Test status
Simulation time	206767156 ps
CPU time	0.95 seconds
Started	Aug 01 06:16:44 PM PDT 24
Finished	Aug 01 06:16:45 PM PDT 24
Peak memory	206924 kb
Host	smart-dd23f1e8-3b64-4850-9479-b892f5fb6e63
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40796 90109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.4079690109
Directory	/workspace/29.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/29.usbdev_stream_len_max.1984656833
Short name	T2839
Test name
Test status
Simulation time	507812838 ps
CPU time	1.51 seconds
Started	Aug 01 06:16:45 PM PDT 24
Finished	Aug 01 06:16:46 PM PDT 24
Peak memory	206932 kb
Host	smart-738f536f-5ebc-40a0-9a19-db3731feddcc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19846 56833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1984656833
Directory	/workspace/29.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/29.usbdev_streaming_out.644390232
Short name	T208
Test name
Test status
Simulation time	1639973173 ps
CPU time	15.86 seconds
Started	Aug 01 06:16:46 PM PDT 24
Finished	Aug 01 06:17:02 PM PDT 24
Peak memory	216676 kb
Host	smart-1e0d74ce-cc8c-4015-bf47-4ad274c0bac7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64439 0232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.644390232
Directory	/workspace/29.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.3997599307
Short name	T1055
Test name
Test status
Simulation time	193752896 ps
CPU time	0.92 seconds
Started	Aug 01 06:16:43 PM PDT 24
Finished	Aug 01 06:16:44 PM PDT 24
Peak memory	206944 kb
Host	smart-a71d8764-fd44-4656-8f74-c29dccc153fc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997599307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos t_handshake.3997599307
Directory	/workspace/29.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/3.usbdev_alert_test.3460937592
Short name	T722
Test name
Test status
Simulation time	40381008 ps
CPU time	0.68 seconds
Started	Aug 01 06:11:39 PM PDT 24
Finished	Aug 01 06:11:40 PM PDT 24
Peak memory	206992 kb
Host	smart-05de0e96-774a-4a49-82f2-8f5c41fdb53c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3460937592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3460937592
Directory	/workspace/3.usbdev_alert_test/latest

Test location	/workspace/coverage/default/3.usbdev_av_buffer.2889141375
Short name	T2675
Test name
Test status
Simulation time	167099025 ps
CPU time	0.86 seconds
Started	Aug 01 06:11:27 PM PDT 24
Finished	Aug 01 06:11:28 PM PDT 24
Peak memory	206884 kb
Host	smart-dec4a79f-619e-467c-ad2c-f6c7d2e98a84
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28891 41375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2889141375
Directory	/workspace/3.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/3.usbdev_av_empty.2292025189
Short name	T33
Test name
Test status
Simulation time	175395945 ps
CPU time	0.93 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:11:26 PM PDT 24
Peak memory	205996 kb
Host	smart-28e0f351-68fc-4d34-8458-226bd6a02751
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22920 25189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2292025189
Directory	/workspace/3.usbdev_av_empty/latest

Test location	/workspace/coverage/default/3.usbdev_av_overflow.2142442207
Short name	T48
Test name
Test status
Simulation time	158540274 ps
CPU time	0.81 seconds
Started	Aug 01 06:11:30 PM PDT 24
Finished	Aug 01 06:11:31 PM PDT 24
Peak memory	206892 kb
Host	smart-ebc2c9fc-44ba-4529-8fde-bfc639e21e5e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21424 42207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2142442207
Directory	/workspace/3.usbdev_av_overflow/latest

Test location	/workspace/coverage/default/3.usbdev_bitstuff_err.4113923094
Short name	T1254
Test name
Test status
Simulation time	168470206 ps
CPU time	0.82 seconds
Started	Aug 01 06:11:22 PM PDT 24
Finished	Aug 01 06:11:23 PM PDT 24
Peak memory	206904 kb
Host	smart-15ff04f7-a54d-4b51-8615-767c675600c4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41139 23094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.4113923094
Directory	/workspace/3.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/3.usbdev_data_toggle_clear.2309959364
Short name	T1296
Test name
Test status
Simulation time	400331561 ps
CPU time	1.54 seconds
Started	Aug 01 06:11:26 PM PDT 24
Finished	Aug 01 06:11:28 PM PDT 24
Peak memory	206908 kb
Host	smart-7a39500f-ba87-408b-849d-13348482f12a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099 59364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.2309959364
Directory	/workspace/3.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/3.usbdev_data_toggle_restore.3413145530
Short name	T500
Test name
Test status
Simulation time	1214998828 ps
CPU time	3.14 seconds
Started	Aug 01 06:11:27 PM PDT 24
Finished	Aug 01 06:11:30 PM PDT 24
Peak memory	207056 kb
Host	smart-5843d477-f6b2-4d7f-9bb3-cb4b7391aab1
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3413145530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3413145530
Directory	/workspace/3.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/3.usbdev_device_address.1109513634
Short name	T1837
Test name
Test status
Simulation time	30488001316 ps
CPU time	52.8 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:12:18 PM PDT 24
Peak memory	206228 kb
Host	smart-45b7f833-2e95-42da-beac-519f8657bd94
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11095 13634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1109513634
Directory	/workspace/3.usbdev_device_address/latest

Test location	/workspace/coverage/default/3.usbdev_device_timeout.2499667334
Short name	T1222
Test name
Test status
Simulation time	1577278292 ps
CPU time	37.88 seconds
Started	Aug 01 06:11:25 PM PDT 24
Finished	Aug 01 06:12:03 PM PDT 24
Peak memory	207148 kb
Host	smart-76cbc27e-f9d6-4542-8927-9d6a6c2f4d72
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499667334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.2499667334
Directory	/workspace/3.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/3.usbdev_disable_endpoint.3580400100
Short name	T1146
Test name
Test status
Simulation time	604401710 ps
CPU time	1.68 seconds
Started	Aug 01 06:11:27 PM PDT 24
Finished	Aug 01 06:11:29 PM PDT 24
Peak memory	206820 kb
Host	smart-106e92c1-521b-4ebf-829c-0841a7f7ee4b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35804 00100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3580400100
Directory	/workspace/3.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/3.usbdev_disconnected.3534630042
Short name	T1116
Test name
Test status
Simulation time	173545491 ps
CPU time	0.85 seconds
Started	Aug 01 06:11:34 PM PDT 24
Finished	Aug 01 06:11:35 PM PDT 24
Peak memory	206828 kb
Host	smart-42cbd690-c4c6-42aa-8e8c-a1c2b2ead61d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35346 30042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.3534630042
Directory	/workspace/3.usbdev_disconnected/latest

Test location	/workspace/coverage/default/3.usbdev_enable.1913145507
Short name	T2337
Test name
Test status
Simulation time	35064916 ps
CPU time	0.68 seconds
Started	Aug 01 06:11:31 PM PDT 24
Finished	Aug 01 06:11:32 PM PDT 24
Peak memory	206920 kb
Host	smart-a2793bc8-5ae4-41ca-9436-cae7fed757b5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19131 45507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1913145507
Directory	/workspace/3.usbdev_enable/latest

Test location	/workspace/coverage/default/3.usbdev_endpoint_access.2280290837
Short name	T1218
Test name
Test status
Simulation time	830563126 ps
CPU time	2.26 seconds
Started	Aug 01 06:11:34 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	207040 kb
Host	smart-1550fbf0-9f74-4244-a2c4-3b4e9eedd508
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22802 90837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2280290837
Directory	/workspace/3.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/3.usbdev_endpoint_types.4243541339
Short name	T2011
Test name
Test status
Simulation time	164955642 ps
CPU time	0.84 seconds
Started	Aug 01 06:11:31 PM PDT 24
Finished	Aug 01 06:11:32 PM PDT 24
Peak memory	206944 kb
Host	smart-ed28720b-0e92-4c96-ac8e-fdeffc268244
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4243541339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.4243541339
Directory	/workspace/3.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/3.usbdev_fifo_rst.967717934
Short name	T714
Test name
Test status
Simulation time	413627665 ps
CPU time	2.85 seconds
Started	Aug 01 06:11:32 PM PDT 24
Finished	Aug 01 06:11:35 PM PDT 24
Peak memory	207204 kb
Host	smart-435e1189-c9b9-4847-afe7-71358395d04a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96771 7934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.967717934
Directory	/workspace/3.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/3.usbdev_freq_hiclk.2040896956
Short name	T471
Test name
Test status
Simulation time	102188004931 ps
CPU time	155.13 seconds
Started	Aug 01 06:11:31 PM PDT 24
Finished	Aug 01 06:14:06 PM PDT 24
Peak memory	207128 kb
Host	smart-a2867438-a7ef-40b0-9a1e-15e61722b32a
User	root
Command	/workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2040896956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.2040896956
Directory	/workspace/3.usbdev_freq_hiclk/latest

Test location	/workspace/coverage/default/3.usbdev_freq_hiclk_max.2466687075
Short name	T2229
Test name
Test status
Simulation time	92178456427 ps
CPU time	158.71 seconds
Started	Aug 01 06:11:32 PM PDT 24
Finished	Aug 01 06:14:11 PM PDT 24
Peak memory	207200 kb
Host	smart-289da429-d078-4028-9b54-a569f5c7a97f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466687075 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.2466687075
Directory	/workspace/3.usbdev_freq_hiclk_max/latest

Test location	/workspace/coverage/default/3.usbdev_freq_loclk.2216204932
Short name	T2399
Test name
Test status
Simulation time	84136458350 ps
CPU time	139.4 seconds
Started	Aug 01 06:11:32 PM PDT 24
Finished	Aug 01 06:13:51 PM PDT 24
Peak memory	207220 kb
Host	smart-5fc611a8-5f2c-4302-b709-154d0b8ce5da
User	root
Command	/workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2216204932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.2216204932
Directory	/workspace/3.usbdev_freq_loclk/latest

Test location	/workspace/coverage/default/3.usbdev_freq_loclk_max.1627297510
Short name	T469
Test name
Test status
Simulation time	82112426210 ps
CPU time	116.95 seconds
Started	Aug 01 06:11:34 PM PDT 24
Finished	Aug 01 06:13:31 PM PDT 24
Peak memory	207064 kb
Host	smart-b172d67c-e091-4d4e-970e-788d850ed26d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627297510 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1627297510
Directory	/workspace/3.usbdev_freq_loclk_max/latest

Test location	/workspace/coverage/default/3.usbdev_in_iso.165600609
Short name	T891
Test name
Test status
Simulation time	230875993 ps
CPU time	1.17 seconds
Started	Aug 01 06:11:32 PM PDT 24
Finished	Aug 01 06:11:33 PM PDT 24
Peak memory	215320 kb
Host	smart-b54c783f-d2e6-4613-ac28-334d8c80cd3e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=165600609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.165600609
Directory	/workspace/3.usbdev_in_iso/latest

Test location	/workspace/coverage/default/3.usbdev_in_stall.1292665351
Short name	T1822
Test name
Test status
Simulation time	210109387 ps
CPU time	0.91 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	206920 kb
Host	smart-606e9b40-0624-4b7a-bd16-422f00b38708
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12926 65351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.1292665351
Directory	/workspace/3.usbdev_in_stall/latest

Test location	/workspace/coverage/default/3.usbdev_in_trans.2826628491
Short name	T796
Test name
Test status
Simulation time	287449883 ps
CPU time	1.14 seconds
Started	Aug 01 06:11:27 PM PDT 24
Finished	Aug 01 06:11:29 PM PDT 24
Peak memory	206856 kb
Host	smart-970b4ff4-5ea7-49a8-965f-870f9728012c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28266 28491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2826628491
Directory	/workspace/3.usbdev_in_trans/latest

Test location	/workspace/coverage/default/3.usbdev_invalid_sync.2972742359
Short name	T1381
Test name
Test status
Simulation time	2558261129 ps
CPU time	19.89 seconds
Started	Aug 01 06:11:31 PM PDT 24
Finished	Aug 01 06:11:51 PM PDT 24
Peak memory	215364 kb
Host	smart-e58e2c92-312d-41c8-b4e2-ee34d41fa6aa
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2972742359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.2972742359
Directory	/workspace/3.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/3.usbdev_iso_retraction.1659784175
Short name	T2560
Test name
Test status
Simulation time	3800431219 ps
CPU time	42 seconds
Started	Aug 01 06:11:34 PM PDT 24
Finished	Aug 01 06:12:17 PM PDT 24
Peak memory	207136 kb
Host	smart-62e8bccc-6830-4f4e-b283-e04f2ee96e1d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1659784175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.1659784175
Directory	/workspace/3.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/3.usbdev_link_in_err.400653798
Short name	T913
Test name
Test status
Simulation time	233323203 ps
CPU time	1.02 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	206896 kb
Host	smart-2f60ed50-68db-4737-b5e3-15e85d2ca456
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40065 3798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.400653798
Directory	/workspace/3.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/3.usbdev_link_suspend.2693137479
Short name	T2509
Test name
Test status
Simulation time	3764057982 ps
CPU time	6.26 seconds
Started	Aug 01 06:11:38 PM PDT 24
Finished	Aug 01 06:11:44 PM PDT 24
Peak memory	207128 kb
Host	smart-533a7778-0517-4a78-a6db-334be822603e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26931 37479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2693137479
Directory	/workspace/3.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/3.usbdev_low_speed_traffic.2497593739
Short name	T2897
Test name
Test status
Simulation time	2970334567 ps
CPU time	22.83 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:59 PM PDT 24
Peak memory	223564 kb
Host	smart-47970362-d37d-4899-866f-d2292f2934a0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24975 93739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2497593739
Directory	/workspace/3.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/3.usbdev_max_inter_pkt_delay.920545684
Short name	T1064
Test name
Test status
Simulation time	2663866679 ps
CPU time	79.64 seconds
Started	Aug 01 06:11:37 PM PDT 24
Finished	Aug 01 06:12:57 PM PDT 24
Peak memory	216944 kb
Host	smart-e2274b95-9bae-4a46-bc79-6e2055486aae
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=920545684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.920545684
Directory	/workspace/3.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/3.usbdev_max_length_in_transaction.4000729739
Short name	T20
Test name
Test status
Simulation time	282272215 ps
CPU time	1.01 seconds
Started	Aug 01 06:11:38 PM PDT 24
Finished	Aug 01 06:11:39 PM PDT 24
Peak memory	206948 kb
Host	smart-ab21781b-f073-402f-ab40-30a058b4fbf3
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=4000729739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.4000729739
Directory	/workspace/3.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/3.usbdev_max_length_out_transaction.4007091506
Short name	T718
Test name
Test status
Simulation time	205256573 ps
CPU time	1.08 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	206952 kb
Host	smart-fef94782-2b2f-4e55-91da-84bf18a94974
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40070 91506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.4007091506
Directory	/workspace/3.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.3871334653
Short name	T675
Test name
Test status
Simulation time	2189350716 ps
CPU time	20.66 seconds
Started	Aug 01 06:11:37 PM PDT 24
Finished	Aug 01 06:11:58 PM PDT 24
Peak memory	216964 kb
Host	smart-7bc5ae62-c2b4-4ab3-aec6-4afa62430e33
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38713 34653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.3871334653
Directory	/workspace/3.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/3.usbdev_max_usb_traffic.279752669
Short name	T1057
Test name
Test status
Simulation time	3421322930 ps
CPU time	35.11 seconds
Started	Aug 01 06:11:41 PM PDT 24
Finished	Aug 01 06:12:16 PM PDT 24
Peak memory	217512 kb
Host	smart-be5ff37a-6a33-4cc3-87eb-8406bef03224
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=279752669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.279752669
Directory	/workspace/3.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/3.usbdev_min_inter_pkt_delay.4044878823
Short name	T514
Test name
Test status
Simulation time	2313019468 ps
CPU time	66.32 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:12:41 PM PDT 24
Peak memory	215332 kb
Host	smart-3f2b49e2-b68b-4d8a-b168-869e634b31de
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=4044878823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.4044878823
Directory	/workspace/3.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/3.usbdev_min_length_in_transaction.130289652
Short name	T2059
Test name
Test status
Simulation time	208597560 ps
CPU time	0.89 seconds
Started	Aug 01 06:11:34 PM PDT 24
Finished	Aug 01 06:11:35 PM PDT 24
Peak memory	206924 kb
Host	smart-a023aa14-36c8-486d-bc57-a13d63aed4d0
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=130289652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.130289652
Directory	/workspace/3.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/3.usbdev_min_length_out_transaction.3212999395
Short name	T925
Test name
Test status
Simulation time	175176540 ps
CPU time	0.86 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	206956 kb
Host	smart-a1f005d5-42db-44a5-b3f5-cce240faa816
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32129 99395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3212999395
Directory	/workspace/3.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/3.usbdev_nak_trans.2570561988
Short name	T1625
Test name
Test status
Simulation time	213092017 ps
CPU time	0.98 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	206964 kb
Host	smart-d14956de-43ab-4a85-b0d7-e81f4e4f4d2b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25705 61988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.2570561988
Directory	/workspace/3.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/3.usbdev_out_iso.1480807894
Short name	T1587
Test name
Test status
Simulation time	159850437 ps
CPU time	0.84 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	206952 kb
Host	smart-08aaa19d-844b-4629-b253-5c7e5c844899
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14808 07894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1480807894
Directory	/workspace/3.usbdev_out_iso/latest

Test location	/workspace/coverage/default/3.usbdev_out_stall.4237908101
Short name	T2500
Test name
Test status
Simulation time	257341680 ps
CPU time	0.94 seconds
Started	Aug 01 06:11:40 PM PDT 24
Finished	Aug 01 06:11:41 PM PDT 24
Peak memory	206968 kb
Host	smart-28352383-cd11-4236-9c14-527e2ab59998
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42379 08101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.4237908101
Directory	/workspace/3.usbdev_out_stall/latest

Test location	/workspace/coverage/default/3.usbdev_out_trans_nak.3024438913
Short name	T990
Test name
Test status
Simulation time	183399772 ps
CPU time	0.96 seconds
Started	Aug 01 06:11:37 PM PDT 24
Finished	Aug 01 06:11:38 PM PDT 24
Peak memory	206800 kb
Host	smart-3e8a08c9-ad8e-452a-aa02-8116361f5cfc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30244 38913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3024438913
Directory	/workspace/3.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/3.usbdev_pending_in_trans.932788976
Short name	T1663
Test name
Test status
Simulation time	160649248 ps
CPU time	0.83 seconds
Started	Aug 01 06:11:37 PM PDT 24
Finished	Aug 01 06:11:38 PM PDT 24
Peak memory	206896 kb
Host	smart-3cbab361-d1e1-4944-a119-2bb8211495cd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93278 8976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.932788976
Directory	/workspace/3.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/3.usbdev_phy_config_pinflip.739881811
Short name	T1638
Test name
Test status
Simulation time	227601401 ps
CPU time	1.01 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	206976 kb
Host	smart-1403b24b-de58-4382-af0a-8a3f0f429369
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=739881811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.739881811
Directory	/workspace/3.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.347205755
Short name	T2458
Test name
Test status
Simulation time	260578283 ps
CPU time	1.2 seconds
Started	Aug 01 06:11:33 PM PDT 24
Finished	Aug 01 06:11:35 PM PDT 24
Peak memory	206960 kb
Host	smart-542ccc7a-91a8-4543-809e-b5df9386a1c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34720 5755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.347205755
Directory	/workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location	/workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3864992602
Short name	T1892
Test name
Test status
Simulation time	169914512 ps
CPU time	0.86 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	206932 kb
Host	smart-b053321c-ebe0-4c30-847d-21e66ae0d90a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649 92602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3864992602
Directory	/workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/3.usbdev_phy_pins_sense.1544884570
Short name	T1777
Test name
Test status
Simulation time	79746445 ps
CPU time	0.75 seconds
Started	Aug 01 06:11:38 PM PDT 24
Finished	Aug 01 06:11:39 PM PDT 24
Peak memory	206840 kb
Host	smart-d8b39836-0f4a-4f44-a7c7-c9723daa40a7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15448 84570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1544884570
Directory	/workspace/3.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/3.usbdev_pkt_buffer.3952632290
Short name	T1228
Test name
Test status
Simulation time	15982197919 ps
CPU time	42.98 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:12:19 PM PDT 24
Peak memory	215384 kb
Host	smart-95d9fa60-8327-4bac-8e80-65a85f47daa4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39526 32290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3952632290
Directory	/workspace/3.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/3.usbdev_pkt_received.51430965
Short name	T140
Test name
Test status
Simulation time	177556125 ps
CPU time	0.92 seconds
Started	Aug 01 06:11:46 PM PDT 24
Finished	Aug 01 06:11:47 PM PDT 24
Peak memory	206952 kb
Host	smart-3b5e1303-2b47-4990-b64a-80d135342891
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51430 965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.51430965
Directory	/workspace/3.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/3.usbdev_pkt_sent.4191014768
Short name	T984
Test name
Test status
Simulation time	169006584 ps
CPU time	0.91 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	207004 kb
Host	smart-fa0aee75-8087-4269-bdf9-2f65870c15ec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41910 14768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.4191014768
Directory	/workspace/3.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/3.usbdev_rand_bus_disconnects.704271162
Short name	T1619
Test name
Test status
Simulation time	3196909598 ps
CPU time	21.1 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:58 PM PDT 24
Peak memory	223484 kb
Host	smart-0c56bd2f-0c0f-4d19-8420-6e7f9723c59b
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=704271162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.704271162
Directory	/workspace/3.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/3.usbdev_rand_bus_resets.1400333464
Short name	T907
Test name
Test status
Simulation time	6368168668 ps
CPU time	67.4 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:12:43 PM PDT 24
Peak memory	223492 kb
Host	smart-daa03cc0-7d9c-4bee-a4f7-965a9fab432c
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400333464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.1400333464
Directory	/workspace/3.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/3.usbdev_rand_suspends.2110106781
Short name	T1144
Test name
Test status
Simulation time	5840628458 ps
CPU time	76.2 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:12:52 PM PDT 24
Peak memory	215372 kb
Host	smart-7d20047a-e544-4ecb-b6b6-57a48c1f4355
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110106781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2110106781
Directory	/workspace/3.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/3.usbdev_random_length_in_transaction.4207889461
Short name	T1717
Test name
Test status
Simulation time	170496522 ps
CPU time	0.93 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	206932 kb
Host	smart-98d3ff46-0ddc-45dd-89c1-b14bdef85599
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42078 89461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.4207889461
Directory	/workspace/3.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/3.usbdev_random_length_out_transaction.784011288
Short name	T2745
Test name
Test status
Simulation time	179362614 ps
CPU time	0.91 seconds
Started	Aug 01 06:11:34 PM PDT 24
Finished	Aug 01 06:11:35 PM PDT 24
Peak memory	206924 kb
Host	smart-0947b838-64c1-4414-88ae-dbd53baadc7e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78401 1288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.784011288
Directory	/workspace/3.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/3.usbdev_rx_crc_err.828273327
Short name	T2219
Test name
Test status
Simulation time	160955719 ps
CPU time	0.88 seconds
Started	Aug 01 06:11:38 PM PDT 24
Finished	Aug 01 06:11:39 PM PDT 24
Peak memory	206844 kb
Host	smart-6049bc03-61f6-494e-9748-6c01e4738d21
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82827 3327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.828273327
Directory	/workspace/3.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/3.usbdev_rx_full.2320920297
Short name	T2679
Test name
Test status
Simulation time	254274035 ps
CPU time	1.1 seconds
Started	Aug 01 06:11:39 PM PDT 24
Finished	Aug 01 06:11:40 PM PDT 24
Peak memory	206952 kb
Host	smart-0cd2507a-b27f-4b5c-8dd7-97d461dee49b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23209 20297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.2320920297
Directory	/workspace/3.usbdev_rx_full/latest

Test location	/workspace/coverage/default/3.usbdev_rx_pid_err.2398099802
Short name	T65
Test name
Test status
Simulation time	188592298 ps
CPU time	0.86 seconds
Started	Aug 01 06:11:39 PM PDT 24
Finished	Aug 01 06:11:40 PM PDT 24
Peak memory	206972 kb
Host	smart-6f6f490c-2b97-4626-a711-1e8830de6530
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23980 99802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2398099802
Directory	/workspace/3.usbdev_rx_pid_err/latest

Test location	/workspace/coverage/default/3.usbdev_sec_cm.3651731268
Short name	T139
Test name
Test status
Simulation time	888326653 ps
CPU time	1.6 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:38 PM PDT 24
Peak memory	223800 kb
Host	smart-29888ac3-bd3f-4371-8afc-ea810de18df9
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3651731268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3651731268
Directory	/workspace/3.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/3.usbdev_setup_priority.3046407869
Short name	T41
Test name
Test status
Simulation time	442698457 ps
CPU time	1.47 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:38 PM PDT 24
Peak memory	206868 kb
Host	smart-6d2ba805-263f-4991-8da5-5e72786c9b86
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30464 07869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3046407869
Directory	/workspace/3.usbdev_setup_priority/latest

Test location	/workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.3523264799
Short name	T704
Test name
Test status
Simulation time	300474482 ps
CPU time	1.11 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	206956 kb
Host	smart-597a69c9-6df9-4409-a754-aa4ab3860031
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35232 64799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.3523264799
Directory	/workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location	/workspace/coverage/default/3.usbdev_setup_stage.3596149160
Short name	T1442
Test name
Test status
Simulation time	148340250 ps
CPU time	0.82 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	206924 kb
Host	smart-ba67df1b-a73f-48cb-a59c-40bb95fa7550
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961 49160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3596149160
Directory	/workspace/3.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/3.usbdev_setup_trans_ignored.2590552492
Short name	T1897
Test name
Test status
Simulation time	218154590 ps
CPU time	0.88 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	206936 kb
Host	smart-552d43cb-6196-422e-90e8-09f01e472479
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25905 52492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2590552492
Directory	/workspace/3.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/3.usbdev_smoke.1995431437
Short name	T2496
Test name
Test status
Simulation time	241283076 ps
CPU time	1.08 seconds
Started	Aug 01 06:11:37 PM PDT 24
Finished	Aug 01 06:11:38 PM PDT 24
Peak memory	206952 kb
Host	smart-861b1e6e-282e-4bec-ab58-60634858527d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19954 31437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1995431437
Directory	/workspace/3.usbdev_smoke/latest

Test location	/workspace/coverage/default/3.usbdev_spurious_pids_ignored.3264266159
Short name	T2579
Test name
Test status
Simulation time	2313812303 ps
CPU time	17.83 seconds
Started	Aug 01 06:11:37 PM PDT 24
Finished	Aug 01 06:11:55 PM PDT 24
Peak memory	223456 kb
Host	smart-699e7b91-beb5-4708-828b-972be9469db0
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3264266159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3264266159
Directory	/workspace/3.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/3.usbdev_stall_priority_over_nak.1168238050
Short name	T2610
Test name
Test status
Simulation time	155675414 ps
CPU time	0.83 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:37 PM PDT 24
Peak memory	206952 kb
Host	smart-e286d8db-d218-4c19-8b6f-738704177511
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11682 38050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.1168238050
Directory	/workspace/3.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/3.usbdev_stall_trans.1980159851
Short name	T821
Test name
Test status
Simulation time	203161404 ps
CPU time	0.88 seconds
Started	Aug 01 06:11:38 PM PDT 24
Finished	Aug 01 06:11:39 PM PDT 24
Peak memory	207168 kb
Host	smart-a421db8f-c066-41b7-a15a-646cc80f8292
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19801 59851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.1980159851
Directory	/workspace/3.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/3.usbdev_stream_len_max.2683893726
Short name	T474
Test name
Test status
Simulation time	1299879888 ps
CPU time	2.9 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:11:39 PM PDT 24
Peak memory	207060 kb
Host	smart-cccd6dfd-9c81-4bb6-a6bc-ff9840218c43
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26838 93726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2683893726
Directory	/workspace/3.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/3.usbdev_streaming_out.536010305
Short name	T2801
Test name
Test status
Simulation time	3264050965 ps
CPU time	94.37 seconds
Started	Aug 01 06:11:39 PM PDT 24
Finished	Aug 01 06:13:14 PM PDT 24
Peak memory	216712 kb
Host	smart-d51ea1da-e686-4add-b5e9-1ae424cb6ed5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53601 0305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.536010305
Directory	/workspace/3.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/3.usbdev_stress_usb_traffic.3206871316
Short name	T64
Test name
Test status
Simulation time	8016046772 ps
CPU time	121.34 seconds
Started	Aug 01 06:11:36 PM PDT 24
Finished	Aug 01 06:13:38 PM PDT 24
Peak memory	223572 kb
Host	smart-ebd124ff-f2c6-4729-a6e3-bd77baa78308
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad _crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206871316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3206871316
Directory	/workspace/3.usbdev_stress_usb_traffic/latest

Test location	/workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.1862600094
Short name	T2060
Test name
Test status
Simulation time	3879668521 ps
CPU time	33.13 seconds
Started	Aug 01 06:11:32 PM PDT 24
Finished	Aug 01 06:12:05 PM PDT 24
Peak memory	207228 kb
Host	smart-3b487e3a-4851-4483-8928-535f10ecef9f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862600094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host _handshake.1862600094
Directory	/workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/30.usbdev_alert_test.3187835351
Short name	T1726
Test name
Test status
Simulation time	65880462 ps
CPU time	0.7 seconds
Started	Aug 01 06:16:53 PM PDT 24
Finished	Aug 01 06:16:54 PM PDT 24
Peak memory	206988 kb
Host	smart-290558ae-5814-4118-9d5f-96a94cca6c10
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3187835351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3187835351
Directory	/workspace/30.usbdev_alert_test/latest

Test location	/workspace/coverage/default/30.usbdev_av_buffer.1393277027
Short name	T2797
Test name
Test status
Simulation time	189407309 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206948 kb
Host	smart-6287f1bf-157d-48b3-b00e-e24e90db10ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13932 77027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1393277027
Directory	/workspace/30.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/30.usbdev_bitstuff_err.989249340
Short name	T1820
Test name
Test status
Simulation time	147868747 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:53 PM PDT 24
Finished	Aug 01 06:16:55 PM PDT 24
Peak memory	206928 kb
Host	smart-22147f0e-8500-4fac-978a-f777784b11c0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98924 9340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.989249340
Directory	/workspace/30.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/30.usbdev_data_toggle_clear.1647107740
Short name	T1284
Test name
Test status
Simulation time	292193356 ps
CPU time	1.08 seconds
Started	Aug 01 06:16:53 PM PDT 24
Finished	Aug 01 06:16:54 PM PDT 24
Peak memory	206924 kb
Host	smart-3a659e95-81f9-4187-a222-0b928a6229f9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16471 07740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1647107740
Directory	/workspace/30.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/30.usbdev_data_toggle_restore.2595731699
Short name	T2597
Test name
Test status
Simulation time	1190841873 ps
CPU time	2.92 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:53 PM PDT 24
Peak memory	207072 kb
Host	smart-fdc20862-99fc-4e5e-b2cd-ecdb7acd6eaa
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2595731699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2595731699
Directory	/workspace/30.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/30.usbdev_device_address.2788372083
Short name	T2387
Test name
Test status
Simulation time	59236119806 ps
CPU time	91.52 seconds
Started	Aug 01 06:16:53 PM PDT 24
Finished	Aug 01 06:18:24 PM PDT 24
Peak memory	207156 kb
Host	smart-10ddb604-0334-4c52-97b4-0dbb603e555d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27883 72083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2788372083
Directory	/workspace/30.usbdev_device_address/latest

Test location	/workspace/coverage/default/30.usbdev_device_timeout.2792436565
Short name	T1634
Test name
Test status
Simulation time	610508970 ps
CPU time	4.84 seconds
Started	Aug 01 06:16:53 PM PDT 24
Finished	Aug 01 06:16:58 PM PDT 24
Peak memory	207092 kb
Host	smart-c249635c-26c7-4661-bb30-192f970832d0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792436565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.2792436565
Directory	/workspace/30.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/30.usbdev_disable_endpoint.628304886
Short name	T307
Test name
Test status
Simulation time	493307800 ps
CPU time	1.41 seconds
Started	Aug 01 06:16:47 PM PDT 24
Finished	Aug 01 06:16:48 PM PDT 24
Peak memory	206916 kb
Host	smart-d08154c3-09a1-4e16-b55d-a294cf20adb8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62830 4886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.628304886
Directory	/workspace/30.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/30.usbdev_disconnected.4191675874
Short name	T667
Test name
Test status
Simulation time	142305887 ps
CPU time	0.81 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206764 kb
Host	smart-8264b923-b85f-4ccc-9fea-545329a83c10
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41916 75874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.4191675874
Directory	/workspace/30.usbdev_disconnected/latest

Test location	/workspace/coverage/default/30.usbdev_enable.1681033984
Short name	T2893
Test name
Test status
Simulation time	35665430 ps
CPU time	0.65 seconds
Started	Aug 01 06:16:49 PM PDT 24
Finished	Aug 01 06:16:50 PM PDT 24
Peak memory	206868 kb
Host	smart-73cf10d9-89bb-414e-8156-4212cb2e535e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16810 33984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1681033984
Directory	/workspace/30.usbdev_enable/latest

Test location	/workspace/coverage/default/30.usbdev_endpoint_access.855235675
Short name	T1159
Test name
Test status
Simulation time	935003877 ps
CPU time	2.49 seconds
Started	Aug 01 06:16:48 PM PDT 24
Finished	Aug 01 06:16:50 PM PDT 24
Peak memory	207136 kb
Host	smart-8cc7e534-8015-4c93-94aa-353ecec0fca1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85523 5675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.855235675
Directory	/workspace/30.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/30.usbdev_fifo_rst.2872325751
Short name	T1758
Test name
Test status
Simulation time	166111557 ps
CPU time	1.43 seconds
Started	Aug 01 06:16:49 PM PDT 24
Finished	Aug 01 06:16:50 PM PDT 24
Peak memory	207108 kb
Host	smart-ffa864f2-3ef9-42e1-b0c9-0c68e555c158
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28723 25751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2872325751
Directory	/workspace/30.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/30.usbdev_in_iso.4147312354
Short name	T1112
Test name
Test status
Simulation time	243252442 ps
CPU time	1.12 seconds
Started	Aug 01 06:16:52 PM PDT 24
Finished	Aug 01 06:16:54 PM PDT 24
Peak memory	215324 kb
Host	smart-477d2aff-60eb-4db8-8982-f865240088cc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4147312354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.4147312354
Directory	/workspace/30.usbdev_in_iso/latest

Test location	/workspace/coverage/default/30.usbdev_in_stall.3907164119
Short name	T2108
Test name
Test status
Simulation time	144921487 ps
CPU time	0.81 seconds
Started	Aug 01 06:16:53 PM PDT 24
Finished	Aug 01 06:16:54 PM PDT 24
Peak memory	206936 kb
Host	smart-a616d7a4-4834-44e5-b0e3-65f492996b8d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39071 64119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.3907164119
Directory	/workspace/30.usbdev_in_stall/latest

Test location	/workspace/coverage/default/30.usbdev_in_trans.4255734867
Short name	T1425
Test name
Test status
Simulation time	220885287 ps
CPU time	1 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:16:52 PM PDT 24
Peak memory	206924 kb
Host	smart-448f445f-65eb-462b-b059-76ef50ec897b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42557 34867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.4255734867
Directory	/workspace/30.usbdev_in_trans/latest

Test location	/workspace/coverage/default/30.usbdev_invalid_sync.2950958682
Short name	T1750
Test name
Test status
Simulation time	3861071336 ps
CPU time	38.44 seconds
Started	Aug 01 06:16:58 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	217276 kb
Host	smart-653991bb-6f33-40fc-8e8a-60a2a0148482
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2950958682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2950958682
Directory	/workspace/30.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/30.usbdev_iso_retraction.1965424923
Short name	T2824
Test name
Test status
Simulation time	6523771442 ps
CPU time	71.91 seconds
Started	Aug 01 06:16:52 PM PDT 24
Finished	Aug 01 06:18:04 PM PDT 24
Peak memory	207156 kb
Host	smart-456eb616-13bc-4279-a1a5-c48ec5e161e8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1965424923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1965424923
Directory	/workspace/30.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/30.usbdev_link_in_err.2353060400
Short name	T1281
Test name
Test status
Simulation time	160058827 ps
CPU time	0.95 seconds
Started	Aug 01 06:16:49 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206916 kb
Host	smart-62e8c945-be3f-4d08-b4ee-bad3be975343
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23530 60400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2353060400
Directory	/workspace/30.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/30.usbdev_link_suspend.107691206
Short name	T97
Test name
Test status
Simulation time	5552205752 ps
CPU time	7.83 seconds
Started	Aug 01 06:16:56 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	215332 kb
Host	smart-25aa47ba-e100-48cd-93dd-d55ffdf0295c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10769 1206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.107691206
Directory	/workspace/30.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/30.usbdev_low_speed_traffic.632132600
Short name	T2818
Test name
Test status
Simulation time	5052106226 ps
CPU time	37.06 seconds
Started	Aug 01 06:16:54 PM PDT 24
Finished	Aug 01 06:17:31 PM PDT 24
Peak memory	223596 kb
Host	smart-ebc2db19-c977-41ab-8a0a-a8d4736a6ccc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63213 2600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.632132600
Directory	/workspace/30.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1930050414
Short name	T1827
Test name
Test status
Simulation time	3462739840 ps
CPU time	35.71 seconds
Started	Aug 01 06:16:46 PM PDT 24
Finished	Aug 01 06:17:22 PM PDT 24
Peak memory	216932 kb
Host	smart-7485e9b5-852f-4fa4-b39e-efa92f1d51ff
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1930050414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1930050414
Directory	/workspace/30.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/30.usbdev_max_length_in_transaction.20952864
Short name	T2433
Test name
Test status
Simulation time	241881732 ps
CPU time	1.02 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:16:52 PM PDT 24
Peak memory	207168 kb
Host	smart-81dda907-af92-4a03-8c9c-7a98a5994ebd
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=20952864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.20952864
Directory	/workspace/30.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/30.usbdev_max_length_out_transaction.1562136932
Short name	T1661
Test name
Test status
Simulation time	204741204 ps
CPU time	0.98 seconds
Started	Aug 01 06:16:55 PM PDT 24
Finished	Aug 01 06:16:56 PM PDT 24
Peak memory	206960 kb
Host	smart-e2f3572d-59c8-4abb-a74a-7ce3704c168b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15621 36932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1562136932
Directory	/workspace/30.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/30.usbdev_min_inter_pkt_delay.1154618907
Short name	T2137
Test name
Test status
Simulation time	3507769948 ps
CPU time	99.92 seconds
Started	Aug 01 06:16:57 PM PDT 24
Finished	Aug 01 06:18:37 PM PDT 24
Peak memory	215408 kb
Host	smart-c28aeb9a-55a6-4872-9b86-76315dfcba0e
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1154618907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.1154618907
Directory	/workspace/30.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/30.usbdev_min_length_in_transaction.1468908542
Short name	T1872
Test name
Test status
Simulation time	167581361 ps
CPU time	0.89 seconds
Started	Aug 01 06:17:06 PM PDT 24
Finished	Aug 01 06:17:07 PM PDT 24
Peak memory	206928 kb
Host	smart-7bbb32ec-4f39-49aa-9d48-ac9d79a0fa23
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1468908542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1468908542
Directory	/workspace/30.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/30.usbdev_min_length_out_transaction.673523501
Short name	T1893
Test name
Test status
Simulation time	141079866 ps
CPU time	0.81 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206936 kb
Host	smart-204b057b-f58f-499f-b9dc-d798a531e06c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67352 3501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.673523501
Directory	/workspace/30.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/30.usbdev_nak_trans.1124113391
Short name	T181
Test name
Test status
Simulation time	297348208 ps
CPU time	1.08 seconds
Started	Aug 01 06:16:52 PM PDT 24
Finished	Aug 01 06:16:54 PM PDT 24
Peak memory	206912 kb
Host	smart-c076eca9-4c84-4596-af39-f25151d43621
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11241 13391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.1124113391
Directory	/workspace/30.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/30.usbdev_out_iso.2400301290
Short name	T2889
Test name
Test status
Simulation time	193715913 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206900 kb
Host	smart-3d4b70a7-aa0f-4e8b-aab3-38fa47d62837
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24003 01290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.2400301290
Directory	/workspace/30.usbdev_out_iso/latest

Test location	/workspace/coverage/default/30.usbdev_out_stall.2557117883
Short name	T1420
Test name
Test status
Simulation time	188615176 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:06 PM PDT 24
Finished	Aug 01 06:17:07 PM PDT 24
Peak memory	206880 kb
Host	smart-a0851f21-8416-4336-9c43-e7ca7335039b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25571 17883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.2557117883
Directory	/workspace/30.usbdev_out_stall/latest

Test location	/workspace/coverage/default/30.usbdev_out_trans_nak.3439884105
Short name	T858
Test name
Test status
Simulation time	193175491 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206964 kb
Host	smart-65c8d3b5-aa06-4a7c-ad1a-d5ea6728bf84
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34398 84105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.3439884105
Directory	/workspace/30.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/30.usbdev_pending_in_trans.4095932245
Short name	T2603
Test name
Test status
Simulation time	153491166 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:16:52 PM PDT 24
Peak memory	206968 kb
Host	smart-14702e61-551b-4098-95ef-ba16b7fe8186
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40959 32245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.4095932245
Directory	/workspace/30.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/30.usbdev_phy_config_pinflip.4105057347
Short name	T29
Test name
Test status
Simulation time	202317189 ps
CPU time	0.93 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206948 kb
Host	smart-8e870dca-36cb-44e8-918e-a050e63cdb7f
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=4105057347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.4105057347
Directory	/workspace/30.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3616866880
Short name	T1926
Test name
Test status
Simulation time	146094176 ps
CPU time	0.83 seconds
Started	Aug 01 06:16:52 PM PDT 24
Finished	Aug 01 06:16:53 PM PDT 24
Peak memory	206904 kb
Host	smart-b432d6b5-347e-41ce-91ab-b87f025969d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36168 66880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3616866880
Directory	/workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/30.usbdev_phy_pins_sense.495672859
Short name	T23
Test name
Test status
Simulation time	62668615 ps
CPU time	0.69 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206884 kb
Host	smart-cd2405dd-e95b-4724-a0a3-00dd7ee78a8c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49567 2859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.495672859
Directory	/workspace/30.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/30.usbdev_pkt_buffer.1892839141
Short name	T2462
Test name
Test status
Simulation time	11056417442 ps
CPU time	27.54 seconds
Started	Aug 01 06:17:01 PM PDT 24
Finished	Aug 01 06:17:29 PM PDT 24
Peak memory	215412 kb
Host	smart-cec1c077-517f-490b-8ff8-127e12955d61
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18928 39141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1892839141
Directory	/workspace/30.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/30.usbdev_pkt_received.1952031316
Short name	T1343
Test name
Test status
Simulation time	169801149 ps
CPU time	0.88 seconds
Started	Aug 01 06:16:58 PM PDT 24
Finished	Aug 01 06:16:59 PM PDT 24
Peak memory	206876 kb
Host	smart-dcfe30d5-2271-42bd-b339-61472c666476
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19520 31316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1952031316
Directory	/workspace/30.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/30.usbdev_pkt_sent.1671042804
Short name	T2353
Test name
Test status
Simulation time	214747866 ps
CPU time	0.94 seconds
Started	Aug 01 06:17:03 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	206924 kb
Host	smart-4fbf5cef-e0aa-4591-a5bc-a1b92cb34f8e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16710 42804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1671042804
Directory	/workspace/30.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/30.usbdev_random_length_in_transaction.3483350598
Short name	T1630
Test name
Test status
Simulation time	235806287 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206956 kb
Host	smart-7c61eb1c-ee2e-49b7-9d1f-117b3ce4e68e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34833 50598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3483350598
Directory	/workspace/30.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/30.usbdev_random_length_out_transaction.1477170069
Short name	T2459
Test name
Test status
Simulation time	165001428 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206928 kb
Host	smart-8a4f5f54-9746-43cc-9174-9c834432415e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14771 70069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1477170069
Directory	/workspace/30.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/30.usbdev_rx_crc_err.3641567701
Short name	T1315
Test name
Test status
Simulation time	234783728 ps
CPU time	0.93 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:16:52 PM PDT 24
Peak memory	206864 kb
Host	smart-05d331f4-1587-46d2-9e05-dc3dd7a0c7ad
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36415 67701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.3641567701
Directory	/workspace/30.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/30.usbdev_rx_full.3039957476
Short name	T42
Test name
Test status
Simulation time	249343807 ps
CPU time	1.08 seconds
Started	Aug 01 06:16:50 PM PDT 24
Finished	Aug 01 06:16:51 PM PDT 24
Peak memory	206952 kb
Host	smart-763ce1e5-dd5f-41be-ab15-837c462c16aa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30399 57476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.3039957476
Directory	/workspace/30.usbdev_rx_full/latest

Test location	/workspace/coverage/default/30.usbdev_setup_stage.2606343494
Short name	T782
Test name
Test status
Simulation time	171415068 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:53 PM PDT 24
Finished	Aug 01 06:16:54 PM PDT 24
Peak memory	206916 kb
Host	smart-75596fac-545c-499c-aaf8-a0f6a719b7ef
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26063 43494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.2606343494
Directory	/workspace/30.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/30.usbdev_setup_trans_ignored.630953376
Short name	T2785
Test name
Test status
Simulation time	141889525 ps
CPU time	0.82 seconds
Started	Aug 01 06:16:52 PM PDT 24
Finished	Aug 01 06:16:53 PM PDT 24
Peak memory	206888 kb
Host	smart-60ec7bff-d918-40e9-8748-7ca25b3fcfaa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63095 3376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.630953376
Directory	/workspace/30.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/30.usbdev_smoke.3450560706
Short name	T818
Test name
Test status
Simulation time	236717821 ps
CPU time	1.11 seconds
Started	Aug 01 06:16:54 PM PDT 24
Finished	Aug 01 06:16:55 PM PDT 24
Peak memory	206960 kb
Host	smart-fc9f3806-6f8d-4260-abce-384ce0bc9bf1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34505 60706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3450560706
Directory	/workspace/30.usbdev_smoke/latest

Test location	/workspace/coverage/default/30.usbdev_spurious_pids_ignored.1160158315
Short name	T878
Test name
Test status
Simulation time	2365562787 ps
CPU time	24.35 seconds
Started	Aug 01 06:16:52 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	223620 kb
Host	smart-7b07cbbd-700d-4927-a183-7401c9570c8e
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1160158315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.1160158315
Directory	/workspace/30.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/30.usbdev_stall_priority_over_nak.2926704367
Short name	T1208
Test name
Test status
Simulation time	201261364 ps
CPU time	0.92 seconds
Started	Aug 01 06:16:55 PM PDT 24
Finished	Aug 01 06:16:56 PM PDT 24
Peak memory	206960 kb
Host	smart-5fa8e881-a5b4-47c7-b116-76d63e946078
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29267 04367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2926704367
Directory	/workspace/30.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/30.usbdev_stall_trans.2888117198
Short name	T2512
Test name
Test status
Simulation time	174704252 ps
CPU time	0.96 seconds
Started	Aug 01 06:16:49 PM PDT 24
Finished	Aug 01 06:16:50 PM PDT 24
Peak memory	206892 kb
Host	smart-9d0272c7-d242-4d66-8886-af04a8ffda15
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28881 17198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2888117198
Directory	/workspace/30.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/30.usbdev_stream_len_max.4058896460
Short name	T2705
Test name
Test status
Simulation time	689828440 ps
CPU time	1.79 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:16:53 PM PDT 24
Peak memory	206916 kb
Host	smart-8a526344-78aa-497e-80d2-db1c65bd5df6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40588 96460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.4058896460
Directory	/workspace/30.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/30.usbdev_streaming_out.28194076
Short name	T2026
Test name
Test status
Simulation time	2472114073 ps
CPU time	69.08 seconds
Started	Aug 01 06:16:52 PM PDT 24
Finished	Aug 01 06:18:01 PM PDT 24
Peak memory	216948 kb
Host	smart-8543f343-a78d-45a0-9139-fad231fc8c3d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28194 076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.28194076
Directory	/workspace/30.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.1854976958
Short name	T2457
Test name
Test status
Simulation time	5226735208 ps
CPU time	45.51 seconds
Started	Aug 01 06:17:03 PM PDT 24
Finished	Aug 01 06:17:49 PM PDT 24
Peak memory	207188 kb
Host	smart-35259199-3402-4fb9-91c9-4f131334ed5c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854976958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_hos t_handshake.1854976958
Directory	/workspace/30.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/31.usbdev_alert_test.4160909218
Short name	T1494
Test name
Test status
Simulation time	34135440 ps
CPU time	0.66 seconds
Started	Aug 01 06:17:14 PM PDT 24
Finished	Aug 01 06:17:14 PM PDT 24
Peak memory	206944 kb
Host	smart-d4a68739-db7a-45e5-a6e3-8b1052effe6c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=4160909218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.4160909218
Directory	/workspace/31.usbdev_alert_test/latest

Test location	/workspace/coverage/default/31.usbdev_av_buffer.2188337050
Short name	T560
Test name
Test status
Simulation time	167939675 ps
CPU time	0.89 seconds
Started	Aug 01 06:16:52 PM PDT 24
Finished	Aug 01 06:16:53 PM PDT 24
Peak memory	206964 kb
Host	smart-9e376038-ee23-4e9e-bafa-fd6806a5e599
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21883 37050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.2188337050
Directory	/workspace/31.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/31.usbdev_bitstuff_err.3484507894
Short name	T1459
Test name
Test status
Simulation time	209933994 ps
CPU time	0.9 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:16:52 PM PDT 24
Peak memory	206884 kb
Host	smart-379bdc87-9f41-4224-b951-15d30fadcaa0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34845 07894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3484507894
Directory	/workspace/31.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/31.usbdev_data_toggle_clear.2640418083
Short name	T1813
Test name
Test status
Simulation time	511083898 ps
CPU time	1.69 seconds
Started	Aug 01 06:16:55 PM PDT 24
Finished	Aug 01 06:16:56 PM PDT 24
Peak memory	206948 kb
Host	smart-4ee25461-da02-4e72-b0f4-6771d603f51e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26404 18083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.2640418083
Directory	/workspace/31.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/31.usbdev_data_toggle_restore.2827776623
Short name	T648
Test name
Test status
Simulation time	1324204126 ps
CPU time	3.39 seconds
Started	Aug 01 06:16:58 PM PDT 24
Finished	Aug 01 06:17:01 PM PDT 24
Peak memory	207164 kb
Host	smart-3a3692ca-f2a6-4007-be49-bd88766096e8
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2827776623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2827776623
Directory	/workspace/31.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/31.usbdev_device_address.581792254
Short name	T1577
Test name
Test status
Simulation time	63793978036 ps
CPU time	103.94 seconds
Started	Aug 01 06:16:51 PM PDT 24
Finished	Aug 01 06:18:35 PM PDT 24
Peak memory	207164 kb
Host	smart-c53f492a-b6a8-4b16-a9eb-f9618df12290
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58179 2254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.581792254
Directory	/workspace/31.usbdev_device_address/latest

Test location	/workspace/coverage/default/31.usbdev_device_timeout.3449620256
Short name	T621
Test name
Test status
Simulation time	618359995 ps
CPU time	4.86 seconds
Started	Aug 01 06:16:55 PM PDT 24
Finished	Aug 01 06:17:00 PM PDT 24
Peak memory	207120 kb
Host	smart-0376743e-f835-44be-9517-ac841174d9dd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449620256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.3449620256
Directory	/workspace/31.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/31.usbdev_disable_endpoint.3122815054
Short name	T2867
Test name
Test status
Simulation time	848115347 ps
CPU time	1.96 seconds
Started	Aug 01 06:17:08 PM PDT 24
Finished	Aug 01 06:17:11 PM PDT 24
Peak memory	206912 kb
Host	smart-8cba04ff-5459-4da2-bdac-aedd38135b7b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31228 15054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3122815054
Directory	/workspace/31.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/31.usbdev_disconnected.3226077128
Short name	T1370
Test name
Test status
Simulation time	172777961 ps
CPU time	0.85 seconds
Started	Aug 01 06:16:53 PM PDT 24
Finished	Aug 01 06:16:54 PM PDT 24
Peak memory	206896 kb
Host	smart-1c98d1bd-6afe-489d-ac7c-692c12695646
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32260 77128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3226077128
Directory	/workspace/31.usbdev_disconnected/latest

Test location	/workspace/coverage/default/31.usbdev_enable.679364153
Short name	T555
Test name
Test status
Simulation time	51217645 ps
CPU time	0.72 seconds
Started	Aug 01 06:17:02 PM PDT 24
Finished	Aug 01 06:17:03 PM PDT 24
Peak memory	206884 kb
Host	smart-b4de53f6-9dd6-4e50-a945-da2c96a9535a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67936 4153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.679364153
Directory	/workspace/31.usbdev_enable/latest

Test location	/workspace/coverage/default/31.usbdev_endpoint_access.4211688430
Short name	T1512
Test name
Test status
Simulation time	871292385 ps
CPU time	2.24 seconds
Started	Aug 01 06:17:03 PM PDT 24
Finished	Aug 01 06:17:05 PM PDT 24
Peak memory	207168 kb
Host	smart-dd19b612-fff4-45b5-8e2d-ff1125073dde
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42116 88430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.4211688430
Directory	/workspace/31.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/31.usbdev_fifo_rst.365308521
Short name	T2803
Test name
Test status
Simulation time	148707480 ps
CPU time	1.44 seconds
Started	Aug 01 06:17:02 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	207112 kb
Host	smart-996a7da7-b1e6-4477-9fa6-c4159145e6b5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36530 8521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.365308521
Directory	/workspace/31.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/31.usbdev_in_iso.42067428
Short name	T1597
Test name
Test status
Simulation time	162305467 ps
CPU time	0.94 seconds
Started	Aug 01 06:17:03 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	206972 kb
Host	smart-2a3c8713-ef4f-48ef-bf3c-846f4ed99709
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=42067428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.42067428
Directory	/workspace/31.usbdev_in_iso/latest

Test location	/workspace/coverage/default/31.usbdev_in_stall.1991856755
Short name	T1608
Test name
Test status
Simulation time	155465018 ps
CPU time	0.84 seconds
Started	Aug 01 06:17:07 PM PDT 24
Finished	Aug 01 06:17:08 PM PDT 24
Peak memory	206936 kb
Host	smart-b32276f4-61d7-40cf-bc72-8240b025672d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19918 56755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1991856755
Directory	/workspace/31.usbdev_in_stall/latest

Test location	/workspace/coverage/default/31.usbdev_in_trans.4018552142
Short name	T881
Test name
Test status
Simulation time	181781208 ps
CPU time	0.85 seconds
Started	Aug 01 06:17:00 PM PDT 24
Finished	Aug 01 06:17:01 PM PDT 24
Peak memory	206936 kb
Host	smart-660ec395-cff6-421c-8845-637919e19206
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40185 52142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.4018552142
Directory	/workspace/31.usbdev_in_trans/latest

Test location	/workspace/coverage/default/31.usbdev_invalid_sync.2146565530
Short name	T2825
Test name
Test status
Simulation time	2767643828 ps
CPU time	27.61 seconds
Started	Aug 01 06:17:12 PM PDT 24
Finished	Aug 01 06:17:39 PM PDT 24
Peak memory	217296 kb
Host	smart-ea304860-558e-46d6-9ad4-56093721a7e3
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2146565530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.2146565530
Directory	/workspace/31.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/31.usbdev_iso_retraction.2210889697
Short name	T2895
Test name
Test status
Simulation time	8016171830 ps
CPU time	58.56 seconds
Started	Aug 01 06:17:00 PM PDT 24
Finished	Aug 01 06:17:59 PM PDT 24
Peak memory	207196 kb
Host	smart-f57d8daa-0932-4921-9721-92e4095c6e8e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2210889697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.2210889697
Directory	/workspace/31.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/31.usbdev_link_in_err.3670112447
Short name	T571
Test name
Test status
Simulation time	176208596 ps
CPU time	0.87 seconds
Started	Aug 01 06:16:59 PM PDT 24
Finished	Aug 01 06:17:00 PM PDT 24
Peak memory	206936 kb
Host	smart-ff664afd-37ac-4755-a91b-9392ba4951cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36701 12447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3670112447
Directory	/workspace/31.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/31.usbdev_link_suspend.2267289848
Short name	T1413
Test name
Test status
Simulation time	10973813893 ps
CPU time	13.2 seconds
Started	Aug 01 06:17:01 PM PDT 24
Finished	Aug 01 06:17:14 PM PDT 24
Peak memory	207128 kb
Host	smart-341d2013-38d0-4917-8ada-e96f08fb1f65
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22672 89848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2267289848
Directory	/workspace/31.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/31.usbdev_low_speed_traffic.413396938
Short name	T2062
Test name
Test status
Simulation time	4330022258 ps
CPU time	41.09 seconds
Started	Aug 01 06:17:03 PM PDT 24
Finished	Aug 01 06:17:44 PM PDT 24
Peak memory	217984 kb
Host	smart-4dc6585f-3d51-45d9-ab1d-b4bac7132e40
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41339 6938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.413396938
Directory	/workspace/31.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/31.usbdev_max_inter_pkt_delay.4162498592
Short name	T1835
Test name
Test status
Simulation time	2233935735 ps
CPU time	22.36 seconds
Started	Aug 01 06:17:02 PM PDT 24
Finished	Aug 01 06:17:25 PM PDT 24
Peak memory	223556 kb
Host	smart-21d0645e-be1d-4415-93f8-de7bd60dcdfd
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4162498592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.4162498592
Directory	/workspace/31.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/31.usbdev_max_length_in_transaction.155788036
Short name	T872
Test name
Test status
Simulation time	241172757 ps
CPU time	0.99 seconds
Started	Aug 01 06:17:04 PM PDT 24
Finished	Aug 01 06:17:05 PM PDT 24
Peak memory	206904 kb
Host	smart-857e7967-1eed-4cb9-bdf5-a9680bb9b910
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=155788036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.155788036
Directory	/workspace/31.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/31.usbdev_max_length_out_transaction.649521468
Short name	T2900
Test name
Test status
Simulation time	246925918 ps
CPU time	1.06 seconds
Started	Aug 01 06:17:02 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	206980 kb
Host	smart-be87682d-71dd-4aeb-acc9-b91202ff4c29
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64952 1468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.649521468
Directory	/workspace/31.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/31.usbdev_min_inter_pkt_delay.3421030596
Short name	T799
Test name
Test status
Simulation time	3437441507 ps
CPU time	94.03 seconds
Started	Aug 01 06:17:13 PM PDT 24
Finished	Aug 01 06:18:47 PM PDT 24
Peak memory	216884 kb
Host	smart-f982c4de-47e2-47db-ab03-b6ebb609b25d
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3421030596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.3421030596
Directory	/workspace/31.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/31.usbdev_min_length_in_transaction.3566652240
Short name	T836
Test name
Test status
Simulation time	155878830 ps
CPU time	0.84 seconds
Started	Aug 01 06:17:14 PM PDT 24
Finished	Aug 01 06:17:15 PM PDT 24
Peak memory	206956 kb
Host	smart-7604f64a-c777-4df2-9317-853273eed092
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3566652240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3566652240
Directory	/workspace/31.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/31.usbdev_min_length_out_transaction.3637296399
Short name	T1047
Test name
Test status
Simulation time	140477598 ps
CPU time	0.89 seconds
Started	Aug 01 06:17:06 PM PDT 24
Finished	Aug 01 06:17:07 PM PDT 24
Peak memory	207176 kb
Host	smart-760c177a-159d-4cab-8f1f-f2e472aa644f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36372 96399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.3637296399
Directory	/workspace/31.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/31.usbdev_nak_trans.2130455801
Short name	T174
Test name
Test status
Simulation time	165934885 ps
CPU time	0.88 seconds
Started	Aug 01 06:17:01 PM PDT 24
Finished	Aug 01 06:17:02 PM PDT 24
Peak memory	206968 kb
Host	smart-9b1db6ce-ed8a-4abe-89d1-205494849266
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21304 55801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2130455801
Directory	/workspace/31.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/31.usbdev_out_iso.2984305624
Short name	T1197
Test name
Test status
Simulation time	218563137 ps
CPU time	1 seconds
Started	Aug 01 06:17:02 PM PDT 24
Finished	Aug 01 06:17:03 PM PDT 24
Peak memory	206944 kb
Host	smart-6e6962cb-177d-445c-aeb1-057584c895d1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29843 05624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2984305624
Directory	/workspace/31.usbdev_out_iso/latest

Test location	/workspace/coverage/default/31.usbdev_out_stall.2961311674
Short name	T1946
Test name
Test status
Simulation time	201209150 ps
CPU time	0.96 seconds
Started	Aug 01 06:17:01 PM PDT 24
Finished	Aug 01 06:17:02 PM PDT 24
Peak memory	206948 kb
Host	smart-7c4bdb5f-86e7-4b37-b7ba-bd5c74d6e668
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29613 11674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2961311674
Directory	/workspace/31.usbdev_out_stall/latest

Test location	/workspace/coverage/default/31.usbdev_out_trans_nak.508278997
Short name	T431
Test name
Test status
Simulation time	186301222 ps
CPU time	0.89 seconds
Started	Aug 01 06:17:02 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	206944 kb
Host	smart-9b686259-5781-47ab-9a10-3a7eb19f5207
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50827 8997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.508278997
Directory	/workspace/31.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/31.usbdev_pending_in_trans.1508093282
Short name	T1150
Test name
Test status
Simulation time	159042899 ps
CPU time	0.85 seconds
Started	Aug 01 06:17:02 PM PDT 24
Finished	Aug 01 06:17:03 PM PDT 24
Peak memory	206960 kb
Host	smart-24b492b0-c41a-421d-b790-780f44703a76
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15080 93282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1508093282
Directory	/workspace/31.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/31.usbdev_phy_config_pinflip.1235971197
Short name	T2713
Test name
Test status
Simulation time	232510094 ps
CPU time	0.98 seconds
Started	Aug 01 06:17:08 PM PDT 24
Finished	Aug 01 06:17:10 PM PDT 24
Peak memory	206956 kb
Host	smart-9c80aeb9-9f03-4bd9-a3af-a519b30c8ae1
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1235971197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.1235971197
Directory	/workspace/31.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3003429744
Short name	T2190
Test name
Test status
Simulation time	167091051 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:06 PM PDT 24
Finished	Aug 01 06:17:07 PM PDT 24
Peak memory	206920 kb
Host	smart-3f8d0f85-2d3a-44f1-9003-aefa5deb72f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30034 29744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3003429744
Directory	/workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/31.usbdev_phy_pins_sense.2677808149
Short name	T1133
Test name
Test status
Simulation time	41138161 ps
CPU time	0.72 seconds
Started	Aug 01 06:17:03 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	206912 kb
Host	smart-7ae03cc3-1f22-4fe0-b074-3f0f4928fd7f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26778 08149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.2677808149
Directory	/workspace/31.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/31.usbdev_pkt_buffer.3191868484
Short name	T2415
Test name
Test status
Simulation time	7332107067 ps
CPU time	19.98 seconds
Started	Aug 01 06:17:07 PM PDT 24
Finished	Aug 01 06:17:27 PM PDT 24
Peak memory	215348 kb
Host	smart-ef26ac74-fb4b-4cf9-b268-74ab71b92d66
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31918 68484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3191868484
Directory	/workspace/31.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/31.usbdev_pkt_received.1279679095
Short name	T2331
Test name
Test status
Simulation time	151543392 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:08 PM PDT 24
Finished	Aug 01 06:17:09 PM PDT 24
Peak memory	206904 kb
Host	smart-f6f6351f-ab63-4e65-8986-601df151b746
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12796 79095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1279679095
Directory	/workspace/31.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/31.usbdev_pkt_sent.4235373113
Short name	T2617
Test name
Test status
Simulation time	171759683 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:08 PM PDT 24
Finished	Aug 01 06:17:09 PM PDT 24
Peak memory	206984 kb
Host	smart-a5494d16-e0d2-4f06-8fe0-c46b7ac7c558
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42353 73113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.4235373113
Directory	/workspace/31.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/31.usbdev_random_length_in_transaction.3367796004
Short name	T2786
Test name
Test status
Simulation time	228176779 ps
CPU time	1.01 seconds
Started	Aug 01 06:17:07 PM PDT 24
Finished	Aug 01 06:17:08 PM PDT 24
Peak memory	206936 kb
Host	smart-f28d4260-dfb1-472d-8560-3db76ade317d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33677 96004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3367796004
Directory	/workspace/31.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/31.usbdev_random_length_out_transaction.1656694312
Short name	T658
Test name
Test status
Simulation time	220756195 ps
CPU time	0.97 seconds
Started	Aug 01 06:16:59 PM PDT 24
Finished	Aug 01 06:17:00 PM PDT 24
Peak memory	206956 kb
Host	smart-d1a0a591-eb82-45c3-b678-4f046c345b47
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16566 94312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1656694312
Directory	/workspace/31.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/31.usbdev_rx_crc_err.3768142833
Short name	T1738
Test name
Test status
Simulation time	158675484 ps
CPU time	0.84 seconds
Started	Aug 01 06:17:02 PM PDT 24
Finished	Aug 01 06:17:03 PM PDT 24
Peak memory	206940 kb
Host	smart-a2277ddc-b388-4670-87d0-04817b4afbe1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37681 42833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3768142833
Directory	/workspace/31.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/31.usbdev_rx_full.2341439059
Short name	T1843
Test name
Test status
Simulation time	265752871 ps
CPU time	1.09 seconds
Started	Aug 01 06:17:09 PM PDT 24
Finished	Aug 01 06:17:11 PM PDT 24
Peak memory	206932 kb
Host	smart-037023db-5036-4afe-8028-09e8cc0f3cf4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23414 39059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.2341439059
Directory	/workspace/31.usbdev_rx_full/latest

Test location	/workspace/coverage/default/31.usbdev_setup_stage.2717498850
Short name	T2235
Test name
Test status
Simulation time	174348607 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:05 PM PDT 24
Finished	Aug 01 06:17:06 PM PDT 24
Peak memory	206920 kb
Host	smart-888ff474-df11-49b4-800b-133b5d887a87
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27174 98850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.2717498850
Directory	/workspace/31.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/31.usbdev_setup_trans_ignored.626429627
Short name	T490
Test name
Test status
Simulation time	145112229 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:03 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	206960 kb
Host	smart-f792de08-152b-40c0-9049-659aaf9b8070
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62642 9627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.626429627
Directory	/workspace/31.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/31.usbdev_smoke.587823169
Short name	T1521
Test name
Test status
Simulation time	210911554 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:07 PM PDT 24
Finished	Aug 01 06:17:08 PM PDT 24
Peak memory	206944 kb
Host	smart-d0628683-3050-467e-bfa2-caeffdca6779
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58782 3169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.587823169
Directory	/workspace/31.usbdev_smoke/latest

Test location	/workspace/coverage/default/31.usbdev_spurious_pids_ignored.3071672555
Short name	T2150
Test name
Test status
Simulation time	3215741019 ps
CPU time	24.8 seconds
Started	Aug 01 06:17:08 PM PDT 24
Finished	Aug 01 06:17:33 PM PDT 24
Peak memory	223536 kb
Host	smart-82a9bce2-9e23-49c1-b209-7b949ab08f43
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3071672555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3071672555
Directory	/workspace/31.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/31.usbdev_stall_priority_over_nak.4247696773
Short name	T761
Test name
Test status
Simulation time	162434863 ps
CPU time	0.84 seconds
Started	Aug 01 06:17:03 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	206960 kb
Host	smart-f26d2589-fd50-4846-9556-554ba78f8a48
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42476 96773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.4247696773
Directory	/workspace/31.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/31.usbdev_stall_trans.3342646974
Short name	T1227
Test name
Test status
Simulation time	169076826 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:00 PM PDT 24
Finished	Aug 01 06:17:02 PM PDT 24
Peak memory	206928 kb
Host	smart-ea49b62a-5bf9-4366-9c89-859fe91ef4da
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33426 46974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3342646974
Directory	/workspace/31.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/31.usbdev_stream_len_max.1452726447
Short name	T1409
Test name
Test status
Simulation time	453370608 ps
CPU time	1.32 seconds
Started	Aug 01 06:17:03 PM PDT 24
Finished	Aug 01 06:17:04 PM PDT 24
Peak memory	206880 kb
Host	smart-32dcc31d-91d8-4416-8186-e84eaa97fadc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14527 26447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.1452726447
Directory	/workspace/31.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/31.usbdev_streaming_out.1379440405
Short name	T1451
Test name
Test status
Simulation time	3013150698 ps
CPU time	21.97 seconds
Started	Aug 01 06:17:02 PM PDT 24
Finished	Aug 01 06:17:24 PM PDT 24
Peak memory	217068 kb
Host	smart-c04ce5b2-adc6-4124-8fd3-a9c656eaf883
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13794 40405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1379440405
Directory	/workspace/31.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.2953598748
Short name	T887
Test name
Test status
Simulation time	3718617175 ps
CPU time	25.71 seconds
Started	Aug 01 06:16:54 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	207208 kb
Host	smart-f50c54e5-9667-47db-8211-1349878ed3d2
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953598748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos t_handshake.2953598748
Directory	/workspace/31.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/32.usbdev_alert_test.3596912172
Short name	T545
Test name
Test status
Simulation time	35557325 ps
CPU time	0.64 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:18 PM PDT 24
Peak memory	206984 kb
Host	smart-281ee736-d2bf-473f-8f1c-e1de1e11b7bb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3596912172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3596912172
Directory	/workspace/32.usbdev_alert_test/latest

Test location	/workspace/coverage/default/32.usbdev_av_buffer.3658925556
Short name	T1641
Test name
Test status
Simulation time	160898427 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:00 PM PDT 24
Finished	Aug 01 06:17:02 PM PDT 24
Peak memory	206908 kb
Host	smart-bdb7d339-0fe7-4ddc-b5bd-ffa696d7c2cc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36589 25556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3658925556
Directory	/workspace/32.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/32.usbdev_bitstuff_err.129104679
Short name	T2822
Test name
Test status
Simulation time	151329557 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:13 PM PDT 24
Finished	Aug 01 06:17:14 PM PDT 24
Peak memory	206868 kb
Host	smart-2d1fb36d-fce4-49ee-a52a-38a09aad6a60
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12910 4679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.129104679
Directory	/workspace/32.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/32.usbdev_data_toggle_clear.563461960
Short name	T2469
Test name
Test status
Simulation time	238503184 ps
CPU time	1.04 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:18 PM PDT 24
Peak memory	206928 kb
Host	smart-913aa098-e7af-4ba6-8a26-f57465933a0d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56346 1960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.563461960
Directory	/workspace/32.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/32.usbdev_data_toggle_restore.3067029215
Short name	T1027
Test name
Test status
Simulation time	762455398 ps
CPU time	2.12 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	207172 kb
Host	smart-3c6ea16d-9c2b-4e90-8aae-5e56bae1d891
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3067029215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3067029215
Directory	/workspace/32.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/32.usbdev_device_address.3283929756
Short name	T227
Test name
Test status
Simulation time	16147569418 ps
CPU time	24.04 seconds
Started	Aug 01 06:17:20 PM PDT 24
Finished	Aug 01 06:17:44 PM PDT 24
Peak memory	207164 kb
Host	smart-8fb0f982-6517-4a84-81b1-5312e644f5f6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32839 29756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.3283929756
Directory	/workspace/32.usbdev_device_address/latest

Test location	/workspace/coverage/default/32.usbdev_device_timeout.3790165587
Short name	T2174
Test name
Test status
Simulation time	6127870838 ps
CPU time	57.06 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:18:13 PM PDT 24
Peak memory	207144 kb
Host	smart-576820a0-3a2b-4e97-9536-ac3ede9273be
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790165587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.3790165587
Directory	/workspace/32.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/32.usbdev_disable_endpoint.2301423992
Short name	T1172
Test name
Test status
Simulation time	1383102920 ps
CPU time	2.48 seconds
Started	Aug 01 06:17:10 PM PDT 24
Finished	Aug 01 06:17:13 PM PDT 24
Peak memory	206892 kb
Host	smart-aec4087e-8673-4686-ab02-e807a1583cb2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23014 23992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2301423992
Directory	/workspace/32.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/32.usbdev_disconnected.2238607115
Short name	T28
Test name
Test status
Simulation time	137496277 ps
CPU time	0.8 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:16 PM PDT 24
Peak memory	206916 kb
Host	smart-7dbefbeb-c437-4354-a02b-d89b3d1275d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22386 07115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2238607115
Directory	/workspace/32.usbdev_disconnected/latest

Test location	/workspace/coverage/default/32.usbdev_enable.1913616513
Short name	T2489
Test name
Test status
Simulation time	81458080 ps
CPU time	0.78 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	206896 kb
Host	smart-38fdb140-4d6c-4c10-b9a1-7e47c2668178
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19136 16513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.1913616513
Directory	/workspace/32.usbdev_enable/latest

Test location	/workspace/coverage/default/32.usbdev_endpoint_access.1318559418
Short name	T1871
Test name
Test status
Simulation time	796962903 ps
CPU time	2.22 seconds
Started	Aug 01 06:17:20 PM PDT 24
Finished	Aug 01 06:17:22 PM PDT 24
Peak memory	207152 kb
Host	smart-86205ba5-7b79-4c6a-a5cc-1c57aa02a530
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13185 59418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.1318559418
Directory	/workspace/32.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/32.usbdev_endpoint_types.1194627496
Short name	T417
Test name
Test status
Simulation time	234846203 ps
CPU time	1 seconds
Started	Aug 01 06:17:13 PM PDT 24
Finished	Aug 01 06:17:14 PM PDT 24
Peak memory	206928 kb
Host	smart-18754d25-f1b2-44f2-8a3d-f9eb9cdc9ddb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1194627496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.1194627496
Directory	/workspace/32.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/32.usbdev_fifo_rst.1447821801
Short name	T723
Test name
Test status
Simulation time	334240813 ps
CPU time	2.68 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	207136 kb
Host	smart-2b6b3d30-7c93-4282-82df-12900544eefb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14478 21801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1447821801
Directory	/workspace/32.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/32.usbdev_in_iso.3370331600
Short name	T1901
Test name
Test status
Simulation time	158334030 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:21 PM PDT 24
Finished	Aug 01 06:17:22 PM PDT 24
Peak memory	206968 kb
Host	smart-47daab56-72d2-4487-93da-237b4287997c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3370331600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.3370331600
Directory	/workspace/32.usbdev_in_iso/latest

Test location	/workspace/coverage/default/32.usbdev_in_stall.3372174336
Short name	T2709
Test name
Test status
Simulation time	150963862 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	206904 kb
Host	smart-c60469d7-f232-4b09-bf36-a61b308b29eb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33721 74336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3372174336
Directory	/workspace/32.usbdev_in_stall/latest

Test location	/workspace/coverage/default/32.usbdev_in_trans.605484800
Short name	T918
Test name
Test status
Simulation time	263911905 ps
CPU time	1.05 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:17:19 PM PDT 24
Peak memory	206960 kb
Host	smart-2ad976d7-92da-4194-8ad3-cdb811f5a9e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60548 4800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.605484800
Directory	/workspace/32.usbdev_in_trans/latest

Test location	/workspace/coverage/default/32.usbdev_invalid_sync.895350157
Short name	T1365
Test name
Test status
Simulation time	4350991480 ps
CPU time	129.02 seconds
Started	Aug 01 06:17:12 PM PDT 24
Finished	Aug 01 06:19:21 PM PDT 24
Peak memory	217612 kb
Host	smart-2b8ae970-7cc9-4adc-9c21-72c6d5f424e6
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=895350157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.895350157
Directory	/workspace/32.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/32.usbdev_iso_retraction.1386837105
Short name	T1283
Test name
Test status
Simulation time	9542167150 ps
CPU time	67.58 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:18:25 PM PDT 24
Peak memory	207140 kb
Host	smart-3935f02d-e355-4a57-a5c6-97012cd4bed4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1386837105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.1386837105
Directory	/workspace/32.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/32.usbdev_link_in_err.1152237258
Short name	T1789
Test name
Test status
Simulation time	212984357 ps
CPU time	1.02 seconds
Started	Aug 01 06:17:13 PM PDT 24
Finished	Aug 01 06:17:15 PM PDT 24
Peak memory	206952 kb
Host	smart-c050ad0c-7e38-4263-8911-3c939b9ff513
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11522 37258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1152237258
Directory	/workspace/32.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/32.usbdev_link_suspend.777158230
Short name	T2715
Test name
Test status
Simulation time	3635752924 ps
CPU time	4.84 seconds
Started	Aug 01 06:17:11 PM PDT 24
Finished	Aug 01 06:17:16 PM PDT 24
Peak memory	215380 kb
Host	smart-9f2c560a-2905-4c22-8004-37549c04da2c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77715 8230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.777158230
Directory	/workspace/32.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/32.usbdev_low_speed_traffic.950619533
Short name	T286
Test name
Test status
Simulation time	4818958411 ps
CPU time	36.66 seconds
Started	Aug 01 06:17:16 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	215376 kb
Host	smart-b3ee896c-6c44-4100-8a46-a5efb8e5a129
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95061 9533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.950619533
Directory	/workspace/32.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/32.usbdev_max_inter_pkt_delay.188927298
Short name	T1171
Test name
Test status
Simulation time	2197056793 ps
CPU time	16.14 seconds
Started	Aug 01 06:17:19 PM PDT 24
Finished	Aug 01 06:17:35 PM PDT 24
Peak memory	215364 kb
Host	smart-04ef4ec8-929b-4192-9b5c-62b9ffd94fef
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=188927298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.188927298
Directory	/workspace/32.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/32.usbdev_max_length_in_transaction.1598228600
Short name	T1890
Test name
Test status
Simulation time	245249005 ps
CPU time	1 seconds
Started	Aug 01 06:17:13 PM PDT 24
Finished	Aug 01 06:17:14 PM PDT 24
Peak memory	206864 kb
Host	smart-652a294e-e896-4cd3-a18e-dcff13095b01
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1598228600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1598228600
Directory	/workspace/32.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/32.usbdev_max_length_out_transaction.4001411310
Short name	T473
Test name
Test status
Simulation time	184981245 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:18 PM PDT 24
Peak memory	206960 kb
Host	smart-1955fef6-8df0-4863-bb2a-30af4cf28655
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40014 11310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.4001411310
Directory	/workspace/32.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/32.usbdev_min_inter_pkt_delay.18281967
Short name	T1349
Test name
Test status
Simulation time	2956009879 ps
CPU time	22.52 seconds
Started	Aug 01 06:17:13 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	207172 kb
Host	smart-3d9c6700-4d4b-4aa0-8777-3c53e9f56e7d
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=18281967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.18281967
Directory	/workspace/32.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/32.usbdev_min_length_in_transaction.3325331455
Short name	T2099
Test name
Test status
Simulation time	168092981 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:20 PM PDT 24
Finished	Aug 01 06:17:21 PM PDT 24
Peak memory	206908 kb
Host	smart-6afbeb8c-e601-4f48-a3a5-52eac067cc92
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3325331455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3325331455
Directory	/workspace/32.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/32.usbdev_min_length_out_transaction.3554216966
Short name	T2212
Test name
Test status
Simulation time	153672703 ps
CPU time	0.83 seconds
Started	Aug 01 06:17:12 PM PDT 24
Finished	Aug 01 06:17:12 PM PDT 24
Peak memory	206972 kb
Host	smart-a881ab16-3026-4af6-9ca8-cddc8f6b3300
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542 16966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3554216966
Directory	/workspace/32.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/32.usbdev_nak_trans.3045339245
Short name	T183
Test name
Test status
Simulation time	193990499 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:16 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	206952 kb
Host	smart-4506a597-8daa-4901-99d8-a26f886d5706
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30453 39245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.3045339245
Directory	/workspace/32.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/32.usbdev_out_iso.2585086281
Short name	T2083
Test name
Test status
Simulation time	193179407 ps
CPU time	0.88 seconds
Started	Aug 01 06:17:08 PM PDT 24
Finished	Aug 01 06:17:09 PM PDT 24
Peak memory	206904 kb
Host	smart-22a00217-f25c-4ea0-a7eb-114d691c626f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25850 86281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2585086281
Directory	/workspace/32.usbdev_out_iso/latest

Test location	/workspace/coverage/default/32.usbdev_out_stall.2420815988
Short name	T568
Test name
Test status
Simulation time	201183191 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:18 PM PDT 24
Peak memory	206948 kb
Host	smart-44ed46c3-87be-4a1d-b101-eed6ab450a3a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24208 15988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2420815988
Directory	/workspace/32.usbdev_out_stall/latest

Test location	/workspace/coverage/default/32.usbdev_out_trans_nak.804128794
Short name	T2226
Test name
Test status
Simulation time	186435096 ps
CPU time	0.89 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:16 PM PDT 24
Peak memory	206928 kb
Host	smart-3d04d8ab-1006-4469-942c-65c2a97d8169
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80412 8794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.804128794
Directory	/workspace/32.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/32.usbdev_pending_in_trans.2801152092
Short name	T2338
Test name
Test status
Simulation time	149745862 ps
CPU time	0.88 seconds
Started	Aug 01 06:17:19 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	206900 kb
Host	smart-aed1622b-4d26-4e60-a24d-092f35500e9b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28011 52092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2801152092
Directory	/workspace/32.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/32.usbdev_phy_config_pinflip.2633491747
Short name	T987
Test name
Test status
Simulation time	245539305 ps
CPU time	1.04 seconds
Started	Aug 01 06:17:13 PM PDT 24
Finished	Aug 01 06:17:14 PM PDT 24
Peak memory	206952 kb
Host	smart-5faaead1-970c-4300-b9eb-d9120d837a98
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2633491747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2633491747
Directory	/workspace/32.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.293367976
Short name	T1678
Test name
Test status
Simulation time	150491792 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:13 PM PDT 24
Finished	Aug 01 06:17:14 PM PDT 24
Peak memory	206956 kb
Host	smart-87682e60-3ade-4b2a-b270-bcfad3355382
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29336 7976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.293367976
Directory	/workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/32.usbdev_phy_pins_sense.2980761499
Short name	T1852
Test name
Test status
Simulation time	36540375 ps
CPU time	0.69 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:16 PM PDT 24
Peak memory	206912 kb
Host	smart-2d5ee379-e07a-49e4-91f1-326d622ef10f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29807 61499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.2980761499
Directory	/workspace/32.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/32.usbdev_pkt_buffer.832665042
Short name	T1466
Test name
Test status
Simulation time	11053321985 ps
CPU time	29.65 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:46 PM PDT 24
Peak memory	215416 kb
Host	smart-ed1923ea-42b9-4c75-a738-bbdda0d9a2ef
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83266 5042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.832665042
Directory	/workspace/32.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/32.usbdev_pkt_received.2760211355
Short name	T1461
Test name
Test status
Simulation time	143653492 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:16 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	207160 kb
Host	smart-b6169219-92a6-4170-9c95-50eb01e27bc1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27602 11355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.2760211355
Directory	/workspace/32.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/32.usbdev_pkt_sent.1121534954
Short name	T1683
Test name
Test status
Simulation time	235076851 ps
CPU time	1.03 seconds
Started	Aug 01 06:17:14 PM PDT 24
Finished	Aug 01 06:17:15 PM PDT 24
Peak memory	206960 kb
Host	smart-dcf63617-458e-42de-96c6-6a2e4186083e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215 34954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.1121534954
Directory	/workspace/32.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/32.usbdev_random_length_in_transaction.321459348
Short name	T2396
Test name
Test status
Simulation time	161312250 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:18 PM PDT 24
Peak memory	206972 kb
Host	smart-d7aea55c-b1fd-4800-bf69-06bced5bfd42
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32145 9348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.321459348
Directory	/workspace/32.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/32.usbdev_random_length_out_transaction.688921928
Short name	T1229
Test name
Test status
Simulation time	234298840 ps
CPU time	0.95 seconds
Started	Aug 01 06:17:16 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	206964 kb
Host	smart-378020b1-2d8d-4b09-b357-ca42434c0fd0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68892 1928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.688921928
Directory	/workspace/32.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/32.usbdev_rx_crc_err.1033801568
Short name	T1369
Test name
Test status
Simulation time	144553331 ps
CPU time	0.81 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:18 PM PDT 24
Peak memory	206844 kb
Host	smart-ab8245f0-02f1-4c66-adbf-2b8a57b4cda1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10338 01568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1033801568
Directory	/workspace/32.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/32.usbdev_rx_full.2251404126
Short name	T2374
Test name
Test status
Simulation time	275806112 ps
CPU time	1.07 seconds
Started	Aug 01 06:17:14 PM PDT 24
Finished	Aug 01 06:17:15 PM PDT 24
Peak memory	206920 kb
Host	smart-747a7255-5a65-4278-a11e-05bc04d9cbbb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22514 04126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.2251404126
Directory	/workspace/32.usbdev_rx_full/latest

Test location	/workspace/coverage/default/32.usbdev_setup_stage.2891884117
Short name	T2595
Test name
Test status
Simulation time	212491603 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:18 PM PDT 24
Peak memory	206920 kb
Host	smart-896b13a1-ded6-4ddf-9f4a-3b7443599865
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28918 84117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2891884117
Directory	/workspace/32.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/32.usbdev_setup_trans_ignored.1775657062
Short name	T2075
Test name
Test status
Simulation time	192905405 ps
CPU time	0.91 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:16 PM PDT 24
Peak memory	206968 kb
Host	smart-31645085-ea8f-4649-9705-74075191588d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17756 57062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1775657062
Directory	/workspace/32.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/32.usbdev_smoke.2632584615
Short name	T2443
Test name
Test status
Simulation time	212808302 ps
CPU time	1.01 seconds
Started	Aug 01 06:17:14 PM PDT 24
Finished	Aug 01 06:17:15 PM PDT 24
Peak memory	206948 kb
Host	smart-3e918e8a-6f8c-463b-bf17-41370ab1a937
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26325 84615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2632584615
Directory	/workspace/32.usbdev_smoke/latest

Test location	/workspace/coverage/default/32.usbdev_spurious_pids_ignored.1253805493
Short name	T1705
Test name
Test status
Simulation time	2681569098 ps
CPU time	71.98 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:18:30 PM PDT 24
Peak memory	223448 kb
Host	smart-d3384310-c32a-4d53-a2f3-fe411f0a0346
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1253805493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1253805493
Directory	/workspace/32.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/32.usbdev_stall_priority_over_nak.1900489897
Short name	T2051
Test name
Test status
Simulation time	177050445 ps
CPU time	0.95 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:18 PM PDT 24
Peak memory	206844 kb
Host	smart-4ce5854d-8a12-4c27-ac7e-0cb1f08dd75c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19004 89897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.1900489897
Directory	/workspace/32.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/32.usbdev_stall_trans.2497117266
Short name	T1260
Test name
Test status
Simulation time	201141473 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:11 PM PDT 24
Finished	Aug 01 06:17:12 PM PDT 24
Peak memory	206996 kb
Host	smart-e92742bd-fae3-422d-b416-5bff4fc878c4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24971 17266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.2497117266
Directory	/workspace/32.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/32.usbdev_stream_len_max.1064787765
Short name	T1195
Test name
Test status
Simulation time	320141142 ps
CPU time	1.08 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:17:19 PM PDT 24
Peak memory	206916 kb
Host	smart-3bd184fe-30af-48cb-a265-cddabf7a8164
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10647 87765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1064787765
Directory	/workspace/32.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/32.usbdev_streaming_out.2129198763
Short name	T464
Test name
Test status
Simulation time	2128765942 ps
CPU time	21.73 seconds
Started	Aug 01 06:17:13 PM PDT 24
Finished	Aug 01 06:17:34 PM PDT 24
Peak memory	215280 kb
Host	smart-62aaed0e-4d9b-4b7a-b27c-99a3f91e304f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21291 98763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.2129198763
Directory	/workspace/32.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.3686560758
Short name	T1232
Test name
Test status
Simulation time	890851252 ps
CPU time	5.62 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:17:24 PM PDT 24
Peak memory	207060 kb
Host	smart-f3453433-dc67-4938-8902-eec73f88daa0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686560758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos t_handshake.3686560758
Directory	/workspace/32.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/33.usbdev_alert_test.1352420367
Short name	T952
Test name
Test status
Simulation time	56243779 ps
CPU time	0.72 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206924 kb
Host	smart-742e5d27-2d46-4c16-9b41-4c12f06d6a97
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1352420367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.1352420367
Directory	/workspace/33.usbdev_alert_test/latest

Test location	/workspace/coverage/default/33.usbdev_av_buffer.1124897763
Short name	T2874
Test name
Test status
Simulation time	165666412 ps
CPU time	0.85 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:16 PM PDT 24
Peak memory	206972 kb
Host	smart-ef766d03-24bb-4490-8e23-a38a7c5605db
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11248 97763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1124897763
Directory	/workspace/33.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/33.usbdev_bitstuff_err.3679299045
Short name	T1358
Test name
Test status
Simulation time	173877500 ps
CPU time	0.83 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:16 PM PDT 24
Peak memory	206916 kb
Host	smart-7d574848-a084-4e58-8d86-321a63bb6282
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36792 99045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3679299045
Directory	/workspace/33.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/33.usbdev_data_toggle_clear.4159559866
Short name	T2055
Test name
Test status
Simulation time	537762217 ps
CPU time	1.97 seconds
Started	Aug 01 06:17:19 PM PDT 24
Finished	Aug 01 06:17:21 PM PDT 24
Peak memory	206904 kb
Host	smart-e3a18f44-9af8-4347-ae02-5e9ce180541a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41595 59866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.4159559866
Directory	/workspace/33.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/33.usbdev_data_toggle_restore.1808789693
Short name	T1080
Test name
Test status
Simulation time	725576660 ps
CPU time	2.12 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	206936 kb
Host	smart-5b02818d-3889-4a1c-9151-66eeaa35a1e4
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1808789693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.1808789693
Directory	/workspace/33.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/33.usbdev_device_address.1750857788
Short name	T1734
Test name
Test status
Simulation time	52617243999 ps
CPU time	78.32 seconds
Started	Aug 01 06:17:16 PM PDT 24
Finished	Aug 01 06:18:35 PM PDT 24
Peak memory	207140 kb
Host	smart-42ccefbb-d671-42db-95a6-6859c25270b6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17508 57788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1750857788
Directory	/workspace/33.usbdev_device_address/latest

Test location	/workspace/coverage/default/33.usbdev_device_timeout.1076566033
Short name	T2133
Test name
Test status
Simulation time	739494400 ps
CPU time	15.35 seconds
Started	Aug 01 06:17:20 PM PDT 24
Finished	Aug 01 06:17:35 PM PDT 24
Peak memory	207084 kb
Host	smart-83f10320-987e-4d68-b808-e95f0918231a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076566033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.1076566033
Directory	/workspace/33.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/33.usbdev_disable_endpoint.2833574532
Short name	T797
Test name
Test status
Simulation time	1168957322 ps
CPU time	2.45 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:19 PM PDT 24
Peak memory	206896 kb
Host	smart-733336e4-3f83-4452-a50f-eb3ad01b3e0a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28335 74532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.2833574532
Directory	/workspace/33.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/33.usbdev_disconnected.1180997812
Short name	T1902
Test name
Test status
Simulation time	157770686 ps
CPU time	0.81 seconds
Started	Aug 01 06:17:16 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	206896 kb
Host	smart-557e3c08-6199-4537-b1dc-ee7a84abcba8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11809 97812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.1180997812
Directory	/workspace/33.usbdev_disconnected/latest

Test location	/workspace/coverage/default/33.usbdev_enable.263316746
Short name	T1177
Test name
Test status
Simulation time	52816866 ps
CPU time	0.72 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:16 PM PDT 24
Peak memory	206920 kb
Host	smart-172eea54-59c7-46b4-8449-2e564fd85b6b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26331 6746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.263316746
Directory	/workspace/33.usbdev_enable/latest

Test location	/workspace/coverage/default/33.usbdev_endpoint_access.616308724
Short name	T517
Test name
Test status
Simulation time	850534924 ps
CPU time	2.23 seconds
Started	Aug 01 06:17:16 PM PDT 24
Finished	Aug 01 06:17:19 PM PDT 24
Peak memory	207120 kb
Host	smart-1a8c29bf-ae78-4b41-ada1-2aaf88ec2fbb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61630 8724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.616308724
Directory	/workspace/33.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/33.usbdev_endpoint_types.3610955597
Short name	T315
Test name
Test status
Simulation time	504069499 ps
CPU time	1.37 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:19 PM PDT 24
Peak memory	206776 kb
Host	smart-4e9f35ef-a48b-4218-b27a-9042450265af
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3610955597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.3610955597
Directory	/workspace/33.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/33.usbdev_fifo_rst.2875510562
Short name	T1109
Test name
Test status
Simulation time	189989525 ps
CPU time	1.28 seconds
Started	Aug 01 06:17:19 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	207136 kb
Host	smart-8a48ebf7-6f37-49c2-83b3-2ec5bad04d45
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755 10562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2875510562
Directory	/workspace/33.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/33.usbdev_in_iso.3904075652
Short name	T1610
Test name
Test status
Simulation time	201598429 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:17 PM PDT 24
Finished	Aug 01 06:17:18 PM PDT 24
Peak memory	206936 kb
Host	smart-0ae19732-9c0b-4761-8cf9-40c3753456de
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3904075652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3904075652
Directory	/workspace/33.usbdev_in_iso/latest

Test location	/workspace/coverage/default/33.usbdev_in_stall.2638396057
Short name	T1857
Test name
Test status
Simulation time	156699630 ps
CPU time	0.92 seconds
Started	Aug 01 06:17:19 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	206888 kb
Host	smart-3f931e1b-b2b2-40d2-b5f1-63f15d085717
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26383 96057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2638396057
Directory	/workspace/33.usbdev_in_stall/latest

Test location	/workspace/coverage/default/33.usbdev_in_trans.4091314928
Short name	T774
Test name
Test status
Simulation time	208685976 ps
CPU time	1 seconds
Started	Aug 01 06:17:19 PM PDT 24
Finished	Aug 01 06:17:21 PM PDT 24
Peak memory	206900 kb
Host	smart-c1681bd7-4b82-44c4-90e7-46f76241a3cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40913 14928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.4091314928
Directory	/workspace/33.usbdev_in_trans/latest

Test location	/workspace/coverage/default/33.usbdev_invalid_sync.1217146359
Short name	T1299
Test name
Test status
Simulation time	3488008301 ps
CPU time	26.63 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:17:45 PM PDT 24
Peak memory	223564 kb
Host	smart-add901a8-5793-42ce-818b-df62d98c34a5
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1217146359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1217146359
Directory	/workspace/33.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/33.usbdev_iso_retraction.282049471
Short name	T1187
Test name
Test status
Simulation time	12281375671 ps
CPU time	131.41 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:19:30 PM PDT 24
Peak memory	207140 kb
Host	smart-2bd7f3ee-1833-4a5b-b15a-d7b77f984e95
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=282049471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.282049471
Directory	/workspace/33.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/33.usbdev_link_in_err.2426794173
Short name	T1795
Test name
Test status
Simulation time	181373317 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:15 PM PDT 24
Finished	Aug 01 06:17:17 PM PDT 24
Peak memory	206956 kb
Host	smart-7c2b5b26-94c2-4939-bbd2-988e1002e3b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24267 94173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2426794173
Directory	/workspace/33.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/33.usbdev_link_suspend.3896123364
Short name	T2805
Test name
Test status
Simulation time	4952242208 ps
CPU time	6.33 seconds
Started	Aug 01 06:17:25 PM PDT 24
Finished	Aug 01 06:17:31 PM PDT 24
Peak memory	207084 kb
Host	smart-fe43aa2c-9101-48eb-bafd-55cd2e7c0e02
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38961 23364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.3896123364
Directory	/workspace/33.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/33.usbdev_low_speed_traffic.611400346
Short name	T986
Test name
Test status
Simulation time	2565355893 ps
CPU time	20.27 seconds
Started	Aug 01 06:17:23 PM PDT 24
Finished	Aug 01 06:17:43 PM PDT 24
Peak memory	215380 kb
Host	smart-052f3eb1-616b-4a24-8341-cc23359b78df
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61140 0346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.611400346
Directory	/workspace/33.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/33.usbdev_max_inter_pkt_delay.3824042225
Short name	T1397
Test name
Test status
Simulation time	2110333722 ps
CPU time	55.98 seconds
Started	Aug 01 06:17:19 PM PDT 24
Finished	Aug 01 06:18:16 PM PDT 24
Peak memory	223392 kb
Host	smart-04782c60-6466-435d-8649-bffe4d4039dd
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3824042225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.3824042225
Directory	/workspace/33.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/33.usbdev_max_length_in_transaction.642869688
Short name	T1152
Test name
Test status
Simulation time	285439827 ps
CPU time	1.12 seconds
Started	Aug 01 06:17:19 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	206912 kb
Host	smart-3bf5950c-d481-4ed4-8e61-19650f3b95b9
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=642869688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.642869688
Directory	/workspace/33.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/33.usbdev_max_length_out_transaction.4025851021
Short name	T565
Test name
Test status
Simulation time	222866881 ps
CPU time	0.98 seconds
Started	Aug 01 06:17:19 PM PDT 24
Finished	Aug 01 06:17:20 PM PDT 24
Peak memory	206952 kb
Host	smart-b6aa3f7e-7482-439d-80ac-c834d5be1512
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40258 51021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.4025851021
Directory	/workspace/33.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2946906278
Short name	T2236
Test name
Test status
Simulation time	2767013493 ps
CPU time	25.89 seconds
Started	Aug 01 06:17:20 PM PDT 24
Finished	Aug 01 06:17:46 PM PDT 24
Peak memory	223544 kb
Host	smart-194a196f-420c-4e3e-a588-e4f3498baca8
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2946906278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2946906278
Directory	/workspace/33.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/33.usbdev_min_length_in_transaction.2834305815
Short name	T495
Test name
Test status
Simulation time	160433019 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:17:19 PM PDT 24
Peak memory	206936 kb
Host	smart-c7ebc870-dd18-4305-b9c5-7104681ed4c7
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2834305815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2834305815
Directory	/workspace/33.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/33.usbdev_min_length_out_transaction.1151551719
Short name	T2205
Test name
Test status
Simulation time	149433784 ps
CPU time	0.83 seconds
Started	Aug 01 06:17:18 PM PDT 24
Finished	Aug 01 06:17:19 PM PDT 24
Peak memory	206928 kb
Host	smart-eb2e2cc4-5530-40c6-bb4e-9f2d878d2d11
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11515 51719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.1151551719
Directory	/workspace/33.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/33.usbdev_nak_trans.1203454922
Short name	T191
Test name
Test status
Simulation time	211459273 ps
CPU time	0.91 seconds
Started	Aug 01 06:17:14 PM PDT 24
Finished	Aug 01 06:17:15 PM PDT 24
Peak memory	206968 kb
Host	smart-e474c703-cb91-4f9f-9926-b7e941660152
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12034 54922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1203454922
Directory	/workspace/33.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/33.usbdev_out_iso.2490471210
Short name	T1887
Test name
Test status
Simulation time	240454580 ps
CPU time	1.05 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	206960 kb
Host	smart-3ed8489e-21c5-461f-bef4-1138971327c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24904 71210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2490471210
Directory	/workspace/33.usbdev_out_iso/latest

Test location	/workspace/coverage/default/33.usbdev_out_stall.3324662036
Short name	T1234
Test name
Test status
Simulation time	191455906 ps
CPU time	0.91 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:35 PM PDT 24
Peak memory	206936 kb
Host	smart-55994b0d-cf7f-4afd-9ae8-7d89fc168245
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33246 62036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3324662036
Directory	/workspace/33.usbdev_out_stall/latest

Test location	/workspace/coverage/default/33.usbdev_out_trans_nak.2549397332
Short name	T1742
Test name
Test status
Simulation time	154230307 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206952 kb
Host	smart-dd854732-7aac-4c9f-830d-2f627c477196
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25493 97332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.2549397332
Directory	/workspace/33.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/33.usbdev_pending_in_trans.2017123657
Short name	T1468
Test name
Test status
Simulation time	151391580 ps
CPU time	0.84 seconds
Started	Aug 01 06:17:37 PM PDT 24
Finished	Aug 01 06:17:38 PM PDT 24
Peak memory	206972 kb
Host	smart-0956b3f5-6c06-418f-b197-f5d0b4ad26df
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20171 23657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2017123657
Directory	/workspace/33.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/33.usbdev_phy_config_pinflip.948956951
Short name	T1366
Test name
Test status
Simulation time	232108554 ps
CPU time	1.04 seconds
Started	Aug 01 06:17:37 PM PDT 24
Finished	Aug 01 06:17:38 PM PDT 24
Peak memory	206956 kb
Host	smart-b874d319-c77d-463b-b2af-2215bfce6c50
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=948956951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.948956951
Directory	/workspace/33.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3664925761
Short name	T929
Test name
Test status
Simulation time	142740228 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206868 kb
Host	smart-1d4a11b2-b174-4fd5-8a9d-af8f40effde1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36649 25761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3664925761
Directory	/workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/33.usbdev_phy_pins_sense.1561266148
Short name	T884
Test name
Test status
Simulation time	92022716 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:37 PM PDT 24
Finished	Aug 01 06:17:38 PM PDT 24
Peak memory	206872 kb
Host	smart-3eb90758-2e3a-4bf7-a209-c3cf386d9f5e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15612 66148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1561266148
Directory	/workspace/33.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/33.usbdev_pkt_buffer.889634855
Short name	T16
Test name
Test status
Simulation time	8599497316 ps
CPU time	24.3 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	215324 kb
Host	smart-a82c4fe0-5e9b-4d7d-8a8d-9c8a383a4577
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88963 4855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.889634855
Directory	/workspace/33.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/33.usbdev_pkt_received.1696455493
Short name	T1698
Test name
Test status
Simulation time	163688763 ps
CPU time	0.88 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:35 PM PDT 24
Peak memory	206916 kb
Host	smart-44fbee3b-7bf1-4a03-b8b8-aed98128bad3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16964 55493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1696455493
Directory	/workspace/33.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/33.usbdev_pkt_sent.1863290348
Short name	T1118
Test name
Test status
Simulation time	158774610 ps
CPU time	0.88 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	206940 kb
Host	smart-19c61d0d-3ee9-47b4-925e-36dc6cbf0787
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18632 90348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.1863290348
Directory	/workspace/33.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/33.usbdev_random_length_in_transaction.1861395596
Short name	T485
Test name
Test status
Simulation time	211040326 ps
CPU time	0.95 seconds
Started	Aug 01 06:17:37 PM PDT 24
Finished	Aug 01 06:17:38 PM PDT 24
Peak memory	206908 kb
Host	smart-bf45754c-ba2f-499d-859d-5ea7f5c036e7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18613 95596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.1861395596
Directory	/workspace/33.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/33.usbdev_random_length_out_transaction.1234381739
Short name	T1158
Test name
Test status
Simulation time	148327840 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	206884 kb
Host	smart-e9a68414-967f-40c7-82de-bd843e1325a6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12343 81739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1234381739
Directory	/workspace/33.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/33.usbdev_rx_crc_err.3509029913
Short name	T1876
Test name
Test status
Simulation time	151379504 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206968 kb
Host	smart-2b29182a-a907-4db0-b833-5c433b344d11
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35090 29913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.3509029913
Directory	/workspace/33.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/33.usbdev_rx_full.642612060
Short name	T798
Test name
Test status
Simulation time	440817044 ps
CPU time	1.4 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206948 kb
Host	smart-7719ca60-2762-4434-b8cc-0d2db8980ca0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64261 2060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.642612060
Directory	/workspace/33.usbdev_rx_full/latest

Test location	/workspace/coverage/default/33.usbdev_setup_stage.296508224
Short name	T1707
Test name
Test status
Simulation time	153032724 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:33 PM PDT 24
Finished	Aug 01 06:17:34 PM PDT 24
Peak memory	206952 kb
Host	smart-75411836-87e7-4cc4-9933-e226a60059f4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29650 8224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.296508224
Directory	/workspace/33.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/33.usbdev_setup_trans_ignored.3880824919
Short name	T1214
Test name
Test status
Simulation time	196051716 ps
CPU time	0.92 seconds
Started	Aug 01 06:17:33 PM PDT 24
Finished	Aug 01 06:17:34 PM PDT 24
Peak memory	206952 kb
Host	smart-e90dd187-619d-44d1-bf85-2b9ba6871b2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38808 24919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3880824919
Directory	/workspace/33.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/33.usbdev_smoke.1262194315
Short name	T2793
Test name
Test status
Simulation time	252639798 ps
CPU time	1.02 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206932 kb
Host	smart-eeeb0765-e326-4fd1-b4d5-f868b56500cc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621 94315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.1262194315
Directory	/workspace/33.usbdev_smoke/latest

Test location	/workspace/coverage/default/33.usbdev_spurious_pids_ignored.1827805192
Short name	T1306
Test name
Test status
Simulation time	1965393755 ps
CPU time	18.86 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	223492 kb
Host	smart-3db6646a-0532-49ac-b7dc-fa07158a1a31
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1827805192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1827805192
Directory	/workspace/33.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/33.usbdev_stall_priority_over_nak.2496354793
Short name	T1911
Test name
Test status
Simulation time	265990742 ps
CPU time	0.94 seconds
Started	Aug 01 06:17:31 PM PDT 24
Finished	Aug 01 06:17:32 PM PDT 24
Peak memory	206940 kb
Host	smart-f77477f6-d8c7-4726-a010-1d8ee62778d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24963 54793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2496354793
Directory	/workspace/33.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/33.usbdev_stall_trans.3026738464
Short name	T2231
Test name
Test status
Simulation time	178147984 ps
CPU time	0.97 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206940 kb
Host	smart-09d90719-fb99-48dc-b394-56034fd93131
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30267 38464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3026738464
Directory	/workspace/33.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/33.usbdev_stream_len_max.3917258751
Short name	T960
Test name
Test status
Simulation time	340073405 ps
CPU time	1.23 seconds
Started	Aug 01 06:17:33 PM PDT 24
Finished	Aug 01 06:17:34 PM PDT 24
Peak memory	206884 kb
Host	smart-6d0f79d9-be8c-46df-bd83-c14bc92859d3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39172 58751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.3917258751
Directory	/workspace/33.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/33.usbdev_streaming_out.1294276421
Short name	T2503
Test name
Test status
Simulation time	3596518596 ps
CPU time	106.96 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:19:22 PM PDT 24
Peak memory	215360 kb
Host	smart-d94cdebe-65b0-474f-a123-d87ffafafe86
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12942 76421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1294276421
Directory	/workspace/33.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.4018199667
Short name	T654
Test name
Test status
Simulation time	1144492800 ps
CPU time	25.82 seconds
Started	Aug 01 06:17:12 PM PDT 24
Finished	Aug 01 06:17:38 PM PDT 24
Peak memory	207084 kb
Host	smart-9cacf9b9-1e98-403a-8090-b979ae3291af
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018199667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos t_handshake.4018199667
Directory	/workspace/33.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/34.usbdev_alert_test.1667256745
Short name	T1483
Test name
Test status
Simulation time	39157545 ps
CPU time	0.68 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	206960 kb
Host	smart-d7dd177d-16db-447b-a47d-fada204c066b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1667256745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.1667256745
Directory	/workspace/34.usbdev_alert_test/latest

Test location	/workspace/coverage/default/34.usbdev_av_buffer.4171405632
Short name	T896
Test name
Test status
Simulation time	171999251 ps
CPU time	0.92 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	206932 kb
Host	smart-8f17e521-51c7-4787-9b0b-168f411ca4dd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41714 05632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.4171405632
Directory	/workspace/34.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/34.usbdev_bitstuff_err.297208129
Short name	T60
Test name
Test status
Simulation time	144464934 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:35 PM PDT 24
Peak memory	207124 kb
Host	smart-5887346a-df77-4a0e-9e88-9ea3c0cb02b5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29720 8129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.297208129
Directory	/workspace/34.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/34.usbdev_data_toggle_clear.4144069338
Short name	T1424
Test name
Test status
Simulation time	390189956 ps
CPU time	1.38 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206904 kb
Host	smart-c22ff0c0-b5ed-40cb-9652-b2d49661fea5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41440 69338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.4144069338
Directory	/workspace/34.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/34.usbdev_data_toggle_restore.3726905319
Short name	T71
Test name
Test status
Simulation time	1111462272 ps
CPU time	2.97 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:40 PM PDT 24
Peak memory	207148 kb
Host	smart-2d695b58-b82e-448f-a7bb-583af00c6077
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3726905319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3726905319
Directory	/workspace/34.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/34.usbdev_device_address.3621650703
Short name	T150
Test name
Test status
Simulation time	60879491244 ps
CPU time	97.54 seconds
Started	Aug 01 06:17:37 PM PDT 24
Finished	Aug 01 06:19:14 PM PDT 24
Peak memory	207168 kb
Host	smart-f1419dc0-cb11-4533-9c89-7fc734cbd4b8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36216 50703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.3621650703
Directory	/workspace/34.usbdev_device_address/latest

Test location	/workspace/coverage/default/34.usbdev_device_timeout.4137033720
Short name	T1697
Test name
Test status
Simulation time	1441874261 ps
CPU time	34.02 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:18:09 PM PDT 24
Peak memory	207088 kb
Host	smart-cad9440b-221f-4f1b-bdaf-f8a86add0c2d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137033720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.4137033720
Directory	/workspace/34.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/34.usbdev_disable_endpoint.3729284584
Short name	T1771
Test name
Test status
Simulation time	613092705 ps
CPU time	1.65 seconds
Started	Aug 01 06:17:32 PM PDT 24
Finished	Aug 01 06:17:34 PM PDT 24
Peak memory	206908 kb
Host	smart-a46401d6-2925-4181-a4fe-404e9c51c7f7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37292 84584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.3729284584
Directory	/workspace/34.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/34.usbdev_disconnected.4185418970
Short name	T2377
Test name
Test status
Simulation time	203327540 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	206892 kb
Host	smart-048eb846-c56b-4fad-a073-320a51cfebea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41854 18970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.4185418970
Directory	/workspace/34.usbdev_disconnected/latest

Test location	/workspace/coverage/default/34.usbdev_enable.399119893
Short name	T1588
Test name
Test status
Simulation time	36868690 ps
CPU time	0.7 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206816 kb
Host	smart-18ab96e8-1bf5-4bd8-92f2-1d96c50063b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39911 9893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.399119893
Directory	/workspace/34.usbdev_enable/latest

Test location	/workspace/coverage/default/34.usbdev_endpoint_access.4227866765
Short name	T2557
Test name
Test status
Simulation time	809806290 ps
CPU time	2.53 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:38 PM PDT 24
Peak memory	207116 kb
Host	smart-22922f52-4c01-4542-ae6c-967bf76e7fb7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42278 66765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.4227866765
Directory	/workspace/34.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/34.usbdev_endpoint_types.3175772987
Short name	T331
Test name
Test status
Simulation time	273590073 ps
CPU time	1.16 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	206904 kb
Host	smart-8a84e2b5-d53a-4a6a-9cfa-93e25de664bd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3175772987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.3175772987
Directory	/workspace/34.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/34.usbdev_fifo_rst.2440768980
Short name	T1832
Test name
Test status
Simulation time	177970077 ps
CPU time	1.75 seconds
Started	Aug 01 06:17:37 PM PDT 24
Finished	Aug 01 06:17:39 PM PDT 24
Peak memory	207104 kb
Host	smart-374b9efb-c428-4cb2-a397-a5f2783ae1bd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24407 68980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.2440768980
Directory	/workspace/34.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/34.usbdev_in_iso.3482757832
Short name	T719
Test name
Test status
Simulation time	220500559 ps
CPU time	1.16 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	215272 kb
Host	smart-078e1dc3-eac1-4c94-9500-904ec62b59b8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3482757832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.3482757832
Directory	/workspace/34.usbdev_in_iso/latest

Test location	/workspace/coverage/default/34.usbdev_in_stall.3178159330
Short name	T885
Test name
Test status
Simulation time	145743314 ps
CPU time	0.85 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:35 PM PDT 24
Peak memory	206940 kb
Host	smart-82b453a5-055b-46d0-8fdc-58fabb4f82d6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31781 59330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3178159330
Directory	/workspace/34.usbdev_in_stall/latest

Test location	/workspace/coverage/default/34.usbdev_in_trans.1625933123
Short name	T498
Test name
Test status
Simulation time	216984944 ps
CPU time	0.98 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206972 kb
Host	smart-f2d093ee-5e50-40d9-8e24-e1f0d92dc53f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16259 33123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1625933123
Directory	/workspace/34.usbdev_in_trans/latest

Test location	/workspace/coverage/default/34.usbdev_invalid_sync.2390437300
Short name	T664
Test name
Test status
Simulation time	3853988758 ps
CPU time	30.66 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:18:07 PM PDT 24
Peak memory	217232 kb
Host	smart-313d7344-5858-4583-9242-93c67243ab60
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2390437300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2390437300
Directory	/workspace/34.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/34.usbdev_link_in_err.3026831790
Short name	T638
Test name
Test status
Simulation time	188924340 ps
CPU time	0.98 seconds
Started	Aug 01 06:17:33 PM PDT 24
Finished	Aug 01 06:17:34 PM PDT 24
Peak memory	206928 kb
Host	smart-76866b1a-b706-4dc6-a4a7-24a93212a004
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30268 31790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3026831790
Directory	/workspace/34.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/34.usbdev_link_suspend.1211507901
Short name	T2511
Test name
Test status
Simulation time	3440695149 ps
CPU time	5.17 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:40 PM PDT 24
Peak memory	207064 kb
Host	smart-0b1889fa-110c-4a02-bc27-0a76dc2d3c2f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12115 07901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1211507901
Directory	/workspace/34.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/34.usbdev_low_speed_traffic.1662563206
Short name	T1679
Test name
Test status
Simulation time	4395589981 ps
CPU time	120.47 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:19:35 PM PDT 24
Peak memory	217864 kb
Host	smart-fa204384-1d2a-4c41-8d2b-be703a02190a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16625 63206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.1662563206
Directory	/workspace/34.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2864445429
Short name	T751
Test name
Test status
Simulation time	1795807848 ps
CPU time	18.47 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	216632 kb
Host	smart-c34c2d96-a155-4458-b27a-e2c747931367
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2864445429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2864445429
Directory	/workspace/34.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/34.usbdev_max_length_in_transaction.2372945586
Short name	T766
Test name
Test status
Simulation time	261707967 ps
CPU time	1.02 seconds
Started	Aug 01 06:17:32 PM PDT 24
Finished	Aug 01 06:17:33 PM PDT 24
Peak memory	207008 kb
Host	smart-3b184fec-95ab-40ff-9f0b-364f1c415f94
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2372945586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.2372945586
Directory	/workspace/34.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/34.usbdev_max_length_out_transaction.3092320522
Short name	T1838
Test name
Test status
Simulation time	211563246 ps
CPU time	0.95 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:38 PM PDT 24
Peak memory	206952 kb
Host	smart-a371ae7f-fffd-4a8a-8daa-207cf802500c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30923 20522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3092320522
Directory	/workspace/34.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/34.usbdev_min_inter_pkt_delay.104413795
Short name	T2270
Test name
Test status
Simulation time	2381069078 ps
CPU time	23.53 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	223560 kb
Host	smart-0d5f1f30-0f12-4684-b9e3-384ea0466363
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=104413795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.104413795
Directory	/workspace/34.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/34.usbdev_min_length_in_transaction.691988575
Short name	T2245
Test name
Test status
Simulation time	164254981 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:33 PM PDT 24
Finished	Aug 01 06:17:34 PM PDT 24
Peak memory	206800 kb
Host	smart-0012e64b-86c7-44ab-98f0-c6a66a52fe28
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=691988575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.691988575
Directory	/workspace/34.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/34.usbdev_min_length_out_transaction.3116313190
Short name	T518
Test name
Test status
Simulation time	144041263 ps
CPU time	0.84 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:35 PM PDT 24
Peak memory	206952 kb
Host	smart-4be96517-c410-45f0-ac53-ef037684248c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31163 13190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3116313190
Directory	/workspace/34.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/34.usbdev_nak_trans.1609974110
Short name	T169
Test name
Test status
Simulation time	198598342 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:33 PM PDT 24
Finished	Aug 01 06:17:34 PM PDT 24
Peak memory	206948 kb
Host	smart-5d411228-7df2-4fd7-b58b-212018cb5969
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16099 74110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1609974110
Directory	/workspace/34.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/34.usbdev_out_iso.3705859759
Short name	T2762
Test name
Test status
Simulation time	215169392 ps
CPU time	0.97 seconds
Started	Aug 01 06:17:36 PM PDT 24
Finished	Aug 01 06:17:37 PM PDT 24
Peak memory	206928 kb
Host	smart-321c5383-3029-4218-ad80-4037574907f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37058 59759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3705859759
Directory	/workspace/34.usbdev_out_iso/latest

Test location	/workspace/coverage/default/34.usbdev_out_stall.3633461426
Short name	T2765
Test name
Test status
Simulation time	263185419 ps
CPU time	1.04 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	206932 kb
Host	smart-56142b09-4c39-4203-a4e0-dd70ffe3b842
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36334 61426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3633461426
Directory	/workspace/34.usbdev_out_stall/latest

Test location	/workspace/coverage/default/34.usbdev_out_trans_nak.1825999763
Short name	T2102
Test name
Test status
Simulation time	160083997 ps
CPU time	0.91 seconds
Started	Aug 01 06:17:37 PM PDT 24
Finished	Aug 01 06:17:38 PM PDT 24
Peak memory	206904 kb
Host	smart-091c74c3-fe03-4370-a396-60b7e028da69
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18259 99763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.1825999763
Directory	/workspace/34.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/34.usbdev_pending_in_trans.3710474644
Short name	T2054
Test name
Test status
Simulation time	191973260 ps
CPU time	0.92 seconds
Started	Aug 01 06:17:35 PM PDT 24
Finished	Aug 01 06:17:36 PM PDT 24
Peak memory	206940 kb
Host	smart-ae2f07a0-fb57-430e-9d0d-38885f56f412
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37104 74644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3710474644
Directory	/workspace/34.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/34.usbdev_phy_config_pinflip.267556145
Short name	T1269
Test name
Test status
Simulation time	249525560 ps
CPU time	1.05 seconds
Started	Aug 01 06:17:34 PM PDT 24
Finished	Aug 01 06:17:35 PM PDT 24
Peak memory	206940 kb
Host	smart-01e4f3d0-24c5-408e-b717-e3465652bbf7
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=267556145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.267556145
Directory	/workspace/34.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.800251945
Short name	T2397
Test name
Test status
Simulation time	189142073 ps
CPU time	0.89 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:17:55 PM PDT 24
Peak memory	206884 kb
Host	smart-04f0a157-02d5-4dfc-b2e4-70d9cfb606e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80025 1945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.800251945
Directory	/workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/34.usbdev_phy_pins_sense.2817197449
Short name	T2005
Test name
Test status
Simulation time	54242446 ps
CPU time	0.72 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:17:55 PM PDT 24
Peak memory	206908 kb
Host	smart-c1b204a7-b35f-4319-adbb-fc6c3cb54918
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28171 97449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.2817197449
Directory	/workspace/34.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/34.usbdev_pkt_buffer.2652352617
Short name	T2587
Test name
Test status
Simulation time	20334755557 ps
CPU time	49.64 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:18:43 PM PDT 24
Peak memory	215376 kb
Host	smart-f10edf30-7e1a-4acf-a66f-fa5681050397
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26523 52617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2652352617
Directory	/workspace/34.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/34.usbdev_pkt_received.3167327708
Short name	T2364
Test name
Test status
Simulation time	146982447 ps
CPU time	0.84 seconds
Started	Aug 01 06:17:50 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206904 kb
Host	smart-af896bf9-8247-4aa8-9240-436f82224493
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31673 27708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3167327708
Directory	/workspace/34.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/34.usbdev_pkt_sent.1777790942
Short name	T2367
Test name
Test status
Simulation time	154637286 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:07 PM PDT 24
Finished	Aug 01 06:18:08 PM PDT 24
Peak memory	206964 kb
Host	smart-7a2ee881-a139-435b-8964-2f4a07b3d31c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17777 90942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1777790942
Directory	/workspace/34.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/34.usbdev_random_length_in_transaction.2890888859
Short name	T1769
Test name
Test status
Simulation time	158841367 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:17:50 PM PDT 24
Peak memory	206908 kb
Host	smart-8be802d6-327e-40f3-8a3b-128d3cf20d52
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28908 88859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.2890888859
Directory	/workspace/34.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/34.usbdev_random_length_out_transaction.2981067420
Short name	T1919
Test name
Test status
Simulation time	161329143 ps
CPU time	0.92 seconds
Started	Aug 01 06:17:51 PM PDT 24
Finished	Aug 01 06:17:52 PM PDT 24
Peak memory	206952 kb
Host	smart-cda73c7e-9b8c-459d-a910-819a6070f958
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29810 67420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2981067420
Directory	/workspace/34.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/34.usbdev_rx_crc_err.1892533828
Short name	T1490
Test name
Test status
Simulation time	182707079 ps
CPU time	0.97 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206948 kb
Host	smart-0a2a49a8-1f4a-4b55-bac6-dcbfa4173b4e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18925 33828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1892533828
Directory	/workspace/34.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/34.usbdev_rx_full.2095354709
Short name	T2144
Test name
Test status
Simulation time	314095639 ps
CPU time	1.14 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	207004 kb
Host	smart-da06e23a-4682-4f56-b1b9-38e0c47d7e17
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20953 54709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.2095354709
Directory	/workspace/34.usbdev_rx_full/latest

Test location	/workspace/coverage/default/34.usbdev_setup_stage.1041391171
Short name	T503
Test name
Test status
Simulation time	154681975 ps
CPU time	0.92 seconds
Started	Aug 01 06:17:50 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206844 kb
Host	smart-d762c166-00fd-4639-89db-5cdf7f0715d3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10413 91171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.1041391171
Directory	/workspace/34.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/34.usbdev_setup_trans_ignored.1376606657
Short name	T1379
Test name
Test status
Simulation time	182239654 ps
CPU time	1.03 seconds
Started	Aug 01 06:17:51 PM PDT 24
Finished	Aug 01 06:17:52 PM PDT 24
Peak memory	206952 kb
Host	smart-da15e507-c621-42c2-9190-ddb24c4cbffb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13766 06657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1376606657
Directory	/workspace/34.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/34.usbdev_smoke.3799320341
Short name	T1647
Test name
Test status
Simulation time	186639578 ps
CPU time	1.01 seconds
Started	Aug 01 06:17:51 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	206956 kb
Host	smart-ef00b3e5-8f36-4104-891f-b6c900653523
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37993 20341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3799320341
Directory	/workspace/34.usbdev_smoke/latest

Test location	/workspace/coverage/default/34.usbdev_spurious_pids_ignored.3098550341
Short name	T2871
Test name
Test status
Simulation time	3719576622 ps
CPU time	101.74 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:19:35 PM PDT 24
Peak memory	215436 kb
Host	smart-6daca935-539d-4e64-b9bb-f75d8b2ecece
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3098550341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3098550341
Directory	/workspace/34.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/34.usbdev_stall_priority_over_nak.826201793
Short name	T1367
Test name
Test status
Simulation time	171027820 ps
CPU time	0.92 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206968 kb
Host	smart-167e04bc-06a7-405c-bd38-98d466057d5b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82620 1793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.826201793
Directory	/workspace/34.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/34.usbdev_stall_trans.1543242315
Short name	T2572
Test name
Test status
Simulation time	171209864 ps
CPU time	0.88 seconds
Started	Aug 01 06:17:50 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206928 kb
Host	smart-f90d9efe-b856-44e2-8e4c-078c92b0a624
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15432 42315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1543242315
Directory	/workspace/34.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/34.usbdev_stream_len_max.314073393
Short name	T1735
Test name
Test status
Simulation time	200040615 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	206880 kb
Host	smart-034940b1-ac1e-4f05-876a-34abea999f05
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31407 3393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.314073393
Directory	/workspace/34.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/34.usbdev_streaming_out.1341436435
Short name	T1556
Test name
Test status
Simulation time	2832172581 ps
CPU time	27.55 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:18:21 PM PDT 24
Peak memory	217096 kb
Host	smart-01291307-fa3f-43e1-90a8-0bb65f8c49db
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13414 36435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1341436435
Directory	/workspace/34.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.1344363152
Short name	T1449
Test name
Test status
Simulation time	2568035926 ps
CPU time	19.13 seconds
Started	Aug 01 06:17:31 PM PDT 24
Finished	Aug 01 06:17:50 PM PDT 24
Peak memory	207140 kb
Host	smart-c7164cd4-f087-4b3d-a894-2db3e49cf538
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344363152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos t_handshake.1344363152
Directory	/workspace/34.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/35.usbdev_alert_test.1503553275
Short name	T2789
Test name
Test status
Simulation time	73960643 ps
CPU time	0.71 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:17:55 PM PDT 24
Peak memory	206968 kb
Host	smart-bb14ed88-5300-44f9-b7a7-dd63e46bd8d4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1503553275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.1503553275
Directory	/workspace/35.usbdev_alert_test/latest

Test location	/workspace/coverage/default/35.usbdev_av_buffer.940740037
Short name	T1737
Test name
Test status
Simulation time	165626570 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:50 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206856 kb
Host	smart-7ffe2b5b-7f93-4a2c-af8e-c5be5351c12e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94074 0037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.940740037
Directory	/workspace/35.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/35.usbdev_bitstuff_err.1021020611
Short name	T2335
Test name
Test status
Simulation time	161210414 ps
CPU time	0.92 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206924 kb
Host	smart-5e15249a-f2fb-4308-89eb-03776cd705af
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10210 20611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1021020611
Directory	/workspace/35.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/35.usbdev_data_toggle_clear.1256235100
Short name	T1768
Test name
Test status
Simulation time	372019842 ps
CPU time	1.42 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:17:55 PM PDT 24
Peak memory	206968 kb
Host	smart-5d88e2b9-bcfc-46a4-82aa-20ba7b58b207
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562 35100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1256235100
Directory	/workspace/35.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/35.usbdev_data_toggle_restore.940929957
Short name	T982
Test name
Test status
Simulation time	477658213 ps
CPU time	1.43 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	206944 kb
Host	smart-91cd06f8-268b-4180-9c29-a2ade2cd1c60
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=940929957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.940929957
Directory	/workspace/35.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/35.usbdev_device_address.4051822144
Short name	T2519
Test name
Test status
Simulation time	18984490975 ps
CPU time	28.2 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:18:20 PM PDT 24
Peak memory	207140 kb
Host	smart-deff5a58-32e3-4cac-98c0-2c928e58a07e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518 22144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.4051822144
Directory	/workspace/35.usbdev_device_address/latest

Test location	/workspace/coverage/default/35.usbdev_device_timeout.863382768
Short name	T1300
Test name
Test status
Simulation time	3224340377 ps
CPU time	22.54 seconds
Started	Aug 01 06:17:47 PM PDT 24
Finished	Aug 01 06:18:10 PM PDT 24
Peak memory	207148 kb
Host	smart-71e0982d-4bb7-438c-b94f-fbba5e32b4a4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863382768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.863382768
Directory	/workspace/35.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/35.usbdev_disable_endpoint.3533705731
Short name	T452
Test name
Test status
Simulation time	893877992 ps
CPU time	2.26 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206936 kb
Host	smart-ce8a4939-c8c7-467d-97d8-c5fc6b50835b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35337 05731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.3533705731
Directory	/workspace/35.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/35.usbdev_disconnected.3666730110
Short name	T1139
Test name
Test status
Simulation time	140765924 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:17:55 PM PDT 24
Peak memory	206912 kb
Host	smart-50ff5f62-6dc0-4b2d-9c38-1cdc0aa9a0b7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36667 30110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3666730110
Directory	/workspace/35.usbdev_disconnected/latest

Test location	/workspace/coverage/default/35.usbdev_enable.1112951608
Short name	T1124
Test name
Test status
Simulation time	34892053 ps
CPU time	0.7 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:17:55 PM PDT 24
Peak memory	206876 kb
Host	smart-0d1ac45b-2dda-47e4-88c4-223043243f5c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11129 51608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1112951608
Directory	/workspace/35.usbdev_enable/latest

Test location	/workspace/coverage/default/35.usbdev_endpoint_access.3510982836
Short name	T525
Test name
Test status
Simulation time	951461970 ps
CPU time	2.39 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	207184 kb
Host	smart-86947faf-1214-4fe2-a150-198e2d1c4d95
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35109 82836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3510982836
Directory	/workspace/35.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/35.usbdev_endpoint_types.3361788435
Short name	T311
Test name
Test status
Simulation time	467100638 ps
CPU time	1.32 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:17:50 PM PDT 24
Peak memory	207144 kb
Host	smart-3c3f0715-0e60-48d1-b8ed-5e0bd91ba4a2
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3361788435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.3361788435
Directory	/workspace/35.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/35.usbdev_fifo_rst.389344323
Short name	T1728
Test name
Test status
Simulation time	176726681 ps
CPU time	2.19 seconds
Started	Aug 01 06:17:51 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	207076 kb
Host	smart-9f870584-2135-4c98-ac8e-475eed14d943
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38934 4323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.389344323
Directory	/workspace/35.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/35.usbdev_in_iso.3445436993
Short name	T2308
Test name
Test status
Simulation time	201753467 ps
CPU time	1.03 seconds
Started	Aug 01 06:18:03 PM PDT 24
Finished	Aug 01 06:18:04 PM PDT 24
Peak memory	206968 kb
Host	smart-3274436c-3fdf-48a4-8a4b-a7f0412962b9
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3445436993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3445436993
Directory	/workspace/35.usbdev_in_iso/latest

Test location	/workspace/coverage/default/35.usbdev_in_stall.978939275
Short name	T1250
Test name
Test status
Simulation time	145445081 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206920 kb
Host	smart-16752b2e-8727-4192-a4d1-a615980da964
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97893 9275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.978939275
Directory	/workspace/35.usbdev_in_stall/latest

Test location	/workspace/coverage/default/35.usbdev_in_trans.2066298864
Short name	T1445
Test name
Test status
Simulation time	308037949 ps
CPU time	1.12 seconds
Started	Aug 01 06:17:51 PM PDT 24
Finished	Aug 01 06:17:52 PM PDT 24
Peak memory	206948 kb
Host	smart-949dc43e-949b-476e-8f99-31c4c81b74a2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20662 98864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2066298864
Directory	/workspace/35.usbdev_in_trans/latest

Test location	/workspace/coverage/default/35.usbdev_invalid_sync.2851564936
Short name	T2816
Test name
Test status
Simulation time	3822953700 ps
CPU time	104.42 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:19:33 PM PDT 24
Peak memory	217104 kb
Host	smart-c97cf794-18a6-4470-9a09-d0685e4bfbb3
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2851564936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.2851564936
Directory	/workspace/35.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/35.usbdev_iso_retraction.1006693735
Short name	T1155
Test name
Test status
Simulation time	5887691265 ps
CPU time	40.66 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:18:35 PM PDT 24
Peak memory	207112 kb
Host	smart-5e1b368f-1e41-4f35-bb29-2817b99180bf
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1006693735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.1006693735
Directory	/workspace/35.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/35.usbdev_link_in_err.1618352052
Short name	T1671
Test name
Test status
Simulation time	203228668 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:17:50 PM PDT 24
Peak memory	206952 kb
Host	smart-c355b19d-058b-4d49-9f2c-525f33dec679
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16183 52052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1618352052
Directory	/workspace/35.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/35.usbdev_link_suspend.2619262059
Short name	T926
Test name
Test status
Simulation time	10604918315 ps
CPU time	14.22 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:18:07 PM PDT 24
Peak memory	207172 kb
Host	smart-b3ed4a63-784d-4b47-aee0-1930dbd1c69d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26192 62059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2619262059
Directory	/workspace/35.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/35.usbdev_low_speed_traffic.867674872
Short name	T2341
Test name
Test status
Simulation time	3843648561 ps
CPU time	36.77 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:18:26 PM PDT 24
Peak memory	223564 kb
Host	smart-4175fde6-43f0-4dec-b099-ab80a3e3dc8c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86767 4872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.867674872
Directory	/workspace/35.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3784873453
Short name	T711
Test name
Test status
Simulation time	2208768740 ps
CPU time	64.28 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	216680 kb
Host	smart-336c0f29-a097-4729-8549-507c4405d96f
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3784873453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3784873453
Directory	/workspace/35.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/35.usbdev_max_length_in_transaction.1089633880
Short name	T859
Test name
Test status
Simulation time	294101790 ps
CPU time	1.12 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	206948 kb
Host	smart-7bc1806e-a414-462f-9df9-a22b4d782ed4
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1089633880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1089633880
Directory	/workspace/35.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/35.usbdev_max_length_out_transaction.4135118747
Short name	T2566
Test name
Test status
Simulation time	191257967 ps
CPU time	1 seconds
Started	Aug 01 06:17:51 PM PDT 24
Finished	Aug 01 06:17:52 PM PDT 24
Peak memory	206960 kb
Host	smart-7a66261e-0413-4c33-a026-ddb9c545604f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41351 18747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.4135118747
Directory	/workspace/35.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/35.usbdev_min_inter_pkt_delay.3581242217
Short name	T1780
Test name
Test status
Simulation time	4006807446 ps
CPU time	30.57 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:18:24 PM PDT 24
Peak memory	207212 kb
Host	smart-a702c585-7dc3-4547-9ac9-ff56082853a9
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3581242217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.3581242217
Directory	/workspace/35.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/35.usbdev_min_length_in_transaction.1487819245
Short name	T684
Test name
Test status
Simulation time	180913008 ps
CPU time	0.88 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	206948 kb
Host	smart-4be05236-20cf-4669-ad91-d4e900b16814
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1487819245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.1487819245
Directory	/workspace/35.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/35.usbdev_min_length_out_transaction.857520602
Short name	T1444
Test name
Test status
Simulation time	146698390 ps
CPU time	0.89 seconds
Started	Aug 01 06:17:51 PM PDT 24
Finished	Aug 01 06:17:52 PM PDT 24
Peak memory	206948 kb
Host	smart-878872c6-760a-4ec9-bad7-bdc0414bc30a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85752 0602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.857520602
Directory	/workspace/35.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/35.usbdev_nak_trans.1360881872
Short name	T1629
Test name
Test status
Simulation time	251161657 ps
CPU time	0.99 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	206896 kb
Host	smart-04eb6e8c-eb0f-4ed7-b2c1-cf626d98f25e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13608 81872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1360881872
Directory	/workspace/35.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/35.usbdev_out_iso.3606673885
Short name	T512
Test name
Test status
Simulation time	192267220 ps
CPU time	0.91 seconds
Started	Aug 01 06:17:50 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206944 kb
Host	smart-2760e1ca-b29a-48d7-b878-3ed37b60e072
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36066 73885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.3606673885
Directory	/workspace/35.usbdev_out_iso/latest

Test location	/workspace/coverage/default/35.usbdev_out_stall.746112737
Short name	T2277
Test name
Test status
Simulation time	177821024 ps
CPU time	0.9 seconds
Started	Aug 01 06:17:51 PM PDT 24
Finished	Aug 01 06:17:52 PM PDT 24
Peak memory	206984 kb
Host	smart-78fe82e2-f440-42e1-887d-883cc4e667d6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74611 2737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.746112737
Directory	/workspace/35.usbdev_out_stall/latest

Test location	/workspace/coverage/default/35.usbdev_out_trans_nak.264421502
Short name	T663
Test name
Test status
Simulation time	160743390 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	206996 kb
Host	smart-74a169b6-c96f-48d8-bd76-ca7405d46990
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26442 1502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.264421502
Directory	/workspace/35.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/35.usbdev_pending_in_trans.1542437708
Short name	T1417
Test name
Test status
Simulation time	148610740 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:17:55 PM PDT 24
Peak memory	206824 kb
Host	smart-3ff0a728-a93f-459d-867d-aeeb83e1d2d5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15424 37708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1542437708
Directory	/workspace/35.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/35.usbdev_phy_config_pinflip.428082283
Short name	T2859
Test name
Test status
Simulation time	244200669 ps
CPU time	1.19 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206932 kb
Host	smart-cdc6b44e-c32f-4bdc-b36c-f36fbb5112a3
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=428082283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.428082283
Directory	/workspace/35.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.4067722353
Short name	T1078
Test name
Test status
Simulation time	147966753 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:53 PM PDT 24
Peak memory	206968 kb
Host	smart-a9e37e5f-a8eb-43cf-94dc-b9ebb1230d72
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40677 22353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.4067722353
Directory	/workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/35.usbdev_phy_pins_sense.3278734032
Short name	T8
Test name
Test status
Simulation time	50040642 ps
CPU time	0.67 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:17:50 PM PDT 24
Peak memory	206884 kb
Host	smart-53f26a2c-330e-4662-914f-5c4163aa790d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32787 34032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.3278734032
Directory	/workspace/35.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/35.usbdev_pkt_buffer.323598594
Short name	T249
Test name
Test status
Simulation time	6595487427 ps
CPU time	16.11 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:18:10 PM PDT 24
Peak memory	215432 kb
Host	smart-1e610ced-6aa0-4172-93af-5c3c6a90402f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32359 8594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.323598594
Directory	/workspace/35.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/35.usbdev_pkt_received.18957626
Short name	T544
Test name
Test status
Simulation time	149236852 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206948 kb
Host	smart-f1697959-c1e7-4d5f-bccc-cb074e3185a9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18957 626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.18957626
Directory	/workspace/35.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/35.usbdev_pkt_sent.3125672982
Short name	T781
Test name
Test status
Simulation time	187566708 ps
CPU time	0.94 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	206872 kb
Host	smart-58baaa9c-a02b-436a-a263-a8a3b70bf607
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31256 72982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3125672982
Directory	/workspace/35.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/35.usbdev_random_length_in_transaction.2725527081
Short name	T1244
Test name
Test status
Simulation time	223603928 ps
CPU time	1.1 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206924 kb
Host	smart-f04142d4-cffc-41bc-9956-07f02f708b01
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27255 27081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2725527081
Directory	/workspace/35.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/35.usbdev_random_length_out_transaction.2480667346
Short name	T487
Test name
Test status
Simulation time	206245283 ps
CPU time	1.04 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206924 kb
Host	smart-cbd5c403-adee-473f-80eb-1354dc75e732
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24806 67346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2480667346
Directory	/workspace/35.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/35.usbdev_rx_crc_err.1309272834
Short name	T853
Test name
Test status
Simulation time	181267242 ps
CPU time	0.89 seconds
Started	Aug 01 06:17:50 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206948 kb
Host	smart-e9ee55cb-f55f-4160-879c-cc1b7d37d0fc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13092 72834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.1309272834
Directory	/workspace/35.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/35.usbdev_rx_full.3327711038
Short name	T2152
Test name
Test status
Simulation time	250416568 ps
CPU time	1.03 seconds
Started	Aug 01 06:17:50 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206952 kb
Host	smart-309216ce-3d0b-414a-a992-4282263026f4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33277 11038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.3327711038
Directory	/workspace/35.usbdev_rx_full/latest

Test location	/workspace/coverage/default/35.usbdev_setup_stage.3745133589
Short name	T783
Test name
Test status
Simulation time	155548211 ps
CPU time	0.85 seconds
Started	Aug 01 06:17:50 PM PDT 24
Finished	Aug 01 06:17:51 PM PDT 24
Peak memory	206888 kb
Host	smart-6ab24192-7120-4bac-85bf-75448bebd4e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37451 33589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.3745133589
Directory	/workspace/35.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/35.usbdev_setup_trans_ignored.1084614045
Short name	T1362
Test name
Test status
Simulation time	154763327 ps
CPU time	0.83 seconds
Started	Aug 01 06:17:49 PM PDT 24
Finished	Aug 01 06:17:50 PM PDT 24
Peak memory	206952 kb
Host	smart-b014bd6c-0cdf-47f4-b7e9-0882337f581d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10846 14045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.1084614045
Directory	/workspace/35.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/35.usbdev_smoke.4158508486
Short name	T820
Test name
Test status
Simulation time	253698682 ps
CPU time	1.08 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206964 kb
Host	smart-6c13c6d5-63dd-4d59-a2ad-91c929711d15
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41585 08486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.4158508486
Directory	/workspace/35.usbdev_smoke/latest

Test location	/workspace/coverage/default/35.usbdev_spurious_pids_ignored.2613283003
Short name	T1079
Test name
Test status
Simulation time	2999254749 ps
CPU time	31.83 seconds
Started	Aug 01 06:17:50 PM PDT 24
Finished	Aug 01 06:18:22 PM PDT 24
Peak memory	223496 kb
Host	smart-e74f8b0e-789f-430f-a7c6-679e2fb5d75c
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2613283003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.2613283003
Directory	/workspace/35.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/35.usbdev_stall_priority_over_nak.2001757233
Short name	T438
Test name
Test status
Simulation time	159195237 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	206924 kb
Host	smart-3973bad4-58ef-47c7-b78e-74f16e0e1b24
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20017 57233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2001757233
Directory	/workspace/35.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/35.usbdev_stall_trans.351029307
Short name	T1514
Test name
Test status
Simulation time	201530366 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:17:59 PM PDT 24
Peak memory	206972 kb
Host	smart-b982f191-e00a-45ab-a750-d0ccc15477b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35102 9307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.351029307
Directory	/workspace/35.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/35.usbdev_stream_len_max.3763679407
Short name	T147
Test name
Test status
Simulation time	1335282999 ps
CPU time	3.09 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	207052 kb
Host	smart-b565726e-2dae-4a5b-b1c0-6b16235d600a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37636 79407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.3763679407
Directory	/workspace/35.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/35.usbdev_streaming_out.1907498490
Short name	T2707
Test name
Test status
Simulation time	2353523468 ps
CPU time	22.52 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	223540 kb
Host	smart-b8ecbede-29e9-4562-adea-b31f3c20078a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19074 98490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1907498490
Directory	/workspace/35.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.3016140376
Short name	T515
Test name
Test status
Simulation time	461374343 ps
CPU time	8.01 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:18:02 PM PDT 24
Peak memory	207092 kb
Host	smart-7e2097d5-7135-492b-8752-b72951293339
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016140376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos t_handshake.3016140376
Directory	/workspace/35.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/36.usbdev_alert_test.3289510231
Short name	T1395
Test name
Test status
Simulation time	59071038 ps
CPU time	0.69 seconds
Started	Aug 01 06:18:05 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206972 kb
Host	smart-7cd8eca0-a31e-414b-90f1-16d1284b5c4f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3289510231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.3289510231
Directory	/workspace/36.usbdev_alert_test/latest

Test location	/workspace/coverage/default/36.usbdev_av_buffer.3382134924
Short name	T1189
Test name
Test status
Simulation time	160101531 ps
CPU time	0.89 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:17:59 PM PDT 24
Peak memory	206972 kb
Host	smart-8f18e153-8a2f-4cef-9ff5-2dd5a21a1876
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33821 34924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3382134924
Directory	/workspace/36.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/36.usbdev_bitstuff_err.426585861
Short name	T1616
Test name
Test status
Simulation time	155045524 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206908 kb
Host	smart-4a7f545d-f675-48a3-9343-87bb6513dd2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42658 5861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.426585861
Directory	/workspace/36.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/36.usbdev_data_toggle_clear.3296399043
Short name	T762
Test name
Test status
Simulation time	474900239 ps
CPU time	1.67 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206944 kb
Host	smart-479d44d1-e4af-45a7-83af-f0ece4e5d4e5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32963 99043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3296399043
Directory	/workspace/36.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/36.usbdev_data_toggle_restore.156726069
Short name	T1757
Test name
Test status
Simulation time	1119830597 ps
CPU time	2.74 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:18:00 PM PDT 24
Peak memory	207140 kb
Host	smart-3f842aa8-d96a-4233-a809-fbcd0bdd988e
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=156726069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.156726069
Directory	/workspace/36.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/36.usbdev_device_address.3688288173
Short name	T2307
Test name
Test status
Simulation time	28856710406 ps
CPU time	48.12 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:18:44 PM PDT 24
Peak memory	207188 kb
Host	smart-9fa4218b-73f0-4de7-bcc2-e9bbdde9d628
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36882 88173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.3688288173
Directory	/workspace/36.usbdev_device_address/latest

Test location	/workspace/coverage/default/36.usbdev_device_timeout.781333966
Short name	T1773
Test name
Test status
Simulation time	736147976 ps
CPU time	15.79 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:18:08 PM PDT 24
Peak memory	207124 kb
Host	smart-3374129e-00c8-4c68-b35a-8e246cc55c4b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781333966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.781333966
Directory	/workspace/36.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/36.usbdev_disable_endpoint.4085151191
Short name	T1670
Test name
Test status
Simulation time	580437124 ps
CPU time	1.61 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:18:00 PM PDT 24
Peak memory	206928 kb
Host	smart-9a211524-55f6-401e-bc6f-743b0e30825b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40851 51191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.4085151191
Directory	/workspace/36.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/36.usbdev_disconnected.1482594225
Short name	T1856
Test name
Test status
Simulation time	149288661 ps
CPU time	0.88 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	206924 kb
Host	smart-6af38307-3bf5-4b11-9548-34a70151da9a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14825 94225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1482594225
Directory	/workspace/36.usbdev_disconnected/latest

Test location	/workspace/coverage/default/36.usbdev_enable.3395776876
Short name	T244
Test name
Test status
Simulation time	76115813 ps
CPU time	0.75 seconds
Started	Aug 01 06:17:52 PM PDT 24
Finished	Aug 01 06:17:52 PM PDT 24
Peak memory	206872 kb
Host	smart-c76f5aae-023e-493d-9377-4c7f27495249
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33957 76876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.3395776876
Directory	/workspace/36.usbdev_enable/latest

Test location	/workspace/coverage/default/36.usbdev_endpoint_access.326883810
Short name	T2899
Test name
Test status
Simulation time	826160989 ps
CPU time	2.43 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:07 PM PDT 24
Peak memory	207096 kb
Host	smart-2e292deb-5577-4b83-940e-b260e1b811c5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32688 3810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.326883810
Directory	/workspace/36.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/36.usbdev_endpoint_types.2767754710
Short name	T1986
Test name
Test status
Simulation time	261109785 ps
CPU time	1.05 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206916 kb
Host	smart-29d5a76c-b2cf-4268-8fb6-1ddc0acb5434
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2767754710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.2767754710
Directory	/workspace/36.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/36.usbdev_fifo_rst.1323225239
Short name	T562
Test name
Test status
Simulation time	255229604 ps
CPU time	2.15 seconds
Started	Aug 01 06:18:02 PM PDT 24
Finished	Aug 01 06:18:04 PM PDT 24
Peak memory	207080 kb
Host	smart-91d2ef8e-014a-4fa8-867e-1ad3104568b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13232 25239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1323225239
Directory	/workspace/36.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/36.usbdev_in_iso.3647583691
Short name	T2444
Test name
Test status
Simulation time	209974378 ps
CPU time	0.93 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206972 kb
Host	smart-cf44b349-2a66-4b89-901a-4ed16d3fc6da
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3647583691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.3647583691
Directory	/workspace/36.usbdev_in_iso/latest

Test location	/workspace/coverage/default/36.usbdev_in_stall.1180461425
Short name	T1407
Test name
Test status
Simulation time	139656453 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206876 kb
Host	smart-e0829181-3059-4ec6-a875-9ed9f848c3c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11804 61425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1180461425
Directory	/workspace/36.usbdev_in_stall/latest

Test location	/workspace/coverage/default/36.usbdev_in_trans.358159111
Short name	T486
Test name
Test status
Simulation time	239076213 ps
CPU time	1.01 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	206908 kb
Host	smart-f4907660-26da-4e96-a603-f7df5ffca12d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35815 9111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.358159111
Directory	/workspace/36.usbdev_in_trans/latest

Test location	/workspace/coverage/default/36.usbdev_invalid_sync.4171960612
Short name	T2495
Test name
Test status
Simulation time	3417296472 ps
CPU time	34.17 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	217168 kb
Host	smart-7cc804b6-838d-4b8c-bb00-dfd1700baa40
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4171960612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.4171960612
Directory	/workspace/36.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/36.usbdev_iso_retraction.30852861
Short name	T2300
Test name
Test status
Simulation time	9209218743 ps
CPU time	64.62 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:19:02 PM PDT 24
Peak memory	207140 kb
Host	smart-dfb64e8b-2203-4cb5-b0ec-91a5b3c381cb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=30852861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.30852861
Directory	/workspace/36.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/36.usbdev_link_in_err.114229583
Short name	T2656
Test name
Test status
Simulation time	239748566 ps
CPU time	1.02 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206928 kb
Host	smart-a1d6b47f-4b83-4b98-88d8-62b1e311d1b0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11422 9583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.114229583
Directory	/workspace/36.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/36.usbdev_link_suspend.979812033
Short name	T1384
Test name
Test status
Simulation time	5269131108 ps
CPU time	6.78 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:18:02 PM PDT 24
Peak memory	215480 kb
Host	smart-19ff1095-d507-4cb0-b8df-2783e08db5fc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97981 2033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.979812033
Directory	/workspace/36.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/36.usbdev_low_speed_traffic.3687241113
Short name	T460
Test name
Test status
Simulation time	3958713669 ps
CPU time	115.15 seconds
Started	Aug 01 06:18:01 PM PDT 24
Finished	Aug 01 06:19:56 PM PDT 24
Peak memory	217060 kb
Host	smart-e85ae92c-9cb2-46ef-9327-7ccd077fae63
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36872 41113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.3687241113
Directory	/workspace/36.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1311878807
Short name	T2755
Test name
Test status
Simulation time	2276408649 ps
CPU time	21.11 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:18:14 PM PDT 24
Peak memory	215408 kb
Host	smart-0e6fa44e-bc55-4b11-9ee8-ae6cc33dc1c4
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1311878807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1311878807
Directory	/workspace/36.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/36.usbdev_max_length_in_transaction.3614629049
Short name	T2274
Test name
Test status
Simulation time	259656399 ps
CPU time	1.11 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	206944 kb
Host	smart-8b6bcb95-2e38-4de7-abcd-5fd60d44b346
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3614629049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.3614629049
Directory	/workspace/36.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/36.usbdev_max_length_out_transaction.3150031775
Short name	T1153
Test name
Test status
Simulation time	187539050 ps
CPU time	1.03 seconds
Started	Aug 01 06:18:01 PM PDT 24
Finished	Aug 01 06:18:02 PM PDT 24
Peak memory	206936 kb
Host	smart-30c2574d-8065-4406-8910-fcf05df9b986
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31500 31775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.3150031775
Directory	/workspace/36.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3601641653
Short name	T1107
Test name
Test status
Simulation time	2867355148 ps
CPU time	83.66 seconds
Started	Aug 01 06:18:00 PM PDT 24
Finished	Aug 01 06:19:24 PM PDT 24
Peak memory	216672 kb
Host	smart-687c791b-a7a5-423b-821f-c127ec470817
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3601641653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3601641653
Directory	/workspace/36.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/36.usbdev_min_length_in_transaction.431285990
Short name	T2561
Test name
Test status
Simulation time	176934204 ps
CPU time	0.89 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:17:59 PM PDT 24
Peak memory	206948 kb
Host	smart-0085911d-75a3-432b-8e8f-10aa74cde783
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=431285990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.431285990
Directory	/workspace/36.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/36.usbdev_min_length_out_transaction.2098347115
Short name	T2132
Test name
Test status
Simulation time	139708080 ps
CPU time	0.84 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	207000 kb
Host	smart-351fe171-27fd-4c4b-b2cd-107624dd400b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20983 47115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2098347115
Directory	/workspace/36.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/36.usbdev_nak_trans.3367020296
Short name	T170
Test name
Test status
Simulation time	233330528 ps
CPU time	1.01 seconds
Started	Aug 01 06:17:54 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206852 kb
Host	smart-9668ae7c-734f-43df-87c4-401dfe6ac555
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33670 20296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.3367020296
Directory	/workspace/36.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/36.usbdev_out_iso.319979945
Short name	T484
Test name
Test status
Simulation time	217372922 ps
CPU time	0.91 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206852 kb
Host	smart-bb629791-446f-4459-905f-8b78d6d4c3f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31997 9945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.319979945
Directory	/workspace/36.usbdev_out_iso/latest

Test location	/workspace/coverage/default/36.usbdev_out_stall.3711579168
Short name	T861
Test name
Test status
Simulation time	147809985 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206956 kb
Host	smart-5f75bd48-c17e-43c4-8ba7-6a154ba9bf89
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115 79168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3711579168
Directory	/workspace/36.usbdev_out_stall/latest

Test location	/workspace/coverage/default/36.usbdev_out_trans_nak.1481685107
Short name	T2326
Test name
Test status
Simulation time	167862731 ps
CPU time	0.85 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	206960 kb
Host	smart-3f5f3c2b-d867-4838-af3d-7fe474f43930
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14816 85107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1481685107
Directory	/workspace/36.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/36.usbdev_pending_in_trans.38499816
Short name	T219
Test name
Test status
Simulation time	153202176 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206952 kb
Host	smart-67c7058d-ecdd-41c3-8107-bd4871a02335
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38499 816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.38499816
Directory	/workspace/36.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/36.usbdev_phy_config_pinflip.191814260
Short name	T1020
Test name
Test status
Simulation time	207647656 ps
CPU time	1 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	206964 kb
Host	smart-08e48814-5b50-49e6-935c-07f9657a5702
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=191814260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.191814260
Directory	/workspace/36.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3616155029
Short name	T1204
Test name
Test status
Simulation time	153748475 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	206944 kb
Host	smart-a9a15f25-f588-4ae6-8cc0-d9e79e13eb8a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36161 55029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3616155029
Directory	/workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/36.usbdev_phy_pins_sense.381573068
Short name	T2237
Test name
Test status
Simulation time	35487738 ps
CPU time	0.71 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	206884 kb
Host	smart-f01ae50f-8b0f-476e-8cd6-ef0729a4aaa2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38157 3068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.381573068
Directory	/workspace/36.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/36.usbdev_pkt_buffer.1945861214
Short name	T1439
Test name
Test status
Simulation time	6376756969 ps
CPU time	15.66 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:18:11 PM PDT 24
Peak memory	215384 kb
Host	smart-3fb3646b-cfb8-46c0-9ec5-b36f3dc1c6f5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19458 61214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1945861214
Directory	/workspace/36.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/36.usbdev_pkt_received.3589333663
Short name	T841
Test name
Test status
Simulation time	147664219 ps
CPU time	0.84 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	206864 kb
Host	smart-8ffda49a-706b-4b46-9f75-4851ce518464
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35893 33663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3589333663
Directory	/workspace/36.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/36.usbdev_pkt_sent.1573010203
Short name	T144
Test name
Test status
Simulation time	223173813 ps
CPU time	0.96 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206964 kb
Host	smart-3e05cae7-7207-431e-b446-358397533165
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15730 10203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.1573010203
Directory	/workspace/36.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/36.usbdev_random_length_in_transaction.927701227
Short name	T2066
Test name
Test status
Simulation time	247103465 ps
CPU time	1.01 seconds
Started	Aug 01 06:17:56 PM PDT 24
Finished	Aug 01 06:17:57 PM PDT 24
Peak memory	206972 kb
Host	smart-6ebcacea-f714-48cc-8703-6357c50bd415
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92770 1227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.927701227
Directory	/workspace/36.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/36.usbdev_random_length_out_transaction.3976194945
Short name	T1470
Test name
Test status
Simulation time	156915824 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	206964 kb
Host	smart-01903530-5204-44a9-b103-d592e04b5d16
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39761 94945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3976194945
Directory	/workspace/36.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/36.usbdev_rx_crc_err.1378184686
Short name	T2290
Test name
Test status
Simulation time	158385647 ps
CPU time	0.85 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	206908 kb
Host	smart-006df24f-b0c1-4e52-b89b-252cc1b09a48
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13781 84686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.1378184686
Directory	/workspace/36.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/36.usbdev_rx_full.2304635486
Short name	T1088
Test name
Test status
Simulation time	244405530 ps
CPU time	1.04 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:17:59 PM PDT 24
Peak memory	206952 kb
Host	smart-61983c8f-80b6-4b55-9135-afae4781e6d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23046 35486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.2304635486
Directory	/workspace/36.usbdev_rx_full/latest

Test location	/workspace/coverage/default/36.usbdev_setup_stage.2974412798
Short name	T1950
Test name
Test status
Simulation time	194908289 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:17:58 PM PDT 24
Peak memory	206916 kb
Host	smart-1a1ea369-4c05-44db-a6c8-674f16db904a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29744 12798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2974412798
Directory	/workspace/36.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/36.usbdev_setup_trans_ignored.2973788820
Short name	T520
Test name
Test status
Simulation time	153560808 ps
CPU time	0.86 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:17:59 PM PDT 24
Peak memory	206956 kb
Host	smart-0ee7d80a-819f-49ba-ba67-632447372697
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29737 88820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2973788820
Directory	/workspace/36.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/36.usbdev_smoke.3623335253
Short name	T1618
Test name
Test status
Simulation time	311040243 ps
CPU time	1.06 seconds
Started	Aug 01 06:17:53 PM PDT 24
Finished	Aug 01 06:17:54 PM PDT 24
Peak memory	206940 kb
Host	smart-95ec6629-1e0e-4b61-b3a9-3f339ddf69f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36233 35253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3623335253
Directory	/workspace/36.usbdev_smoke/latest

Test location	/workspace/coverage/default/36.usbdev_spurious_pids_ignored.2259984195
Short name	T1755
Test name
Test status
Simulation time	2563989723 ps
CPU time	21.22 seconds
Started	Aug 01 06:18:01 PM PDT 24
Finished	Aug 01 06:18:22 PM PDT 24
Peak memory	223456 kb
Host	smart-6935319e-30cc-4015-9f78-1b207c0fc16f
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2259984195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.2259984195
Directory	/workspace/36.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/36.usbdev_stall_priority_over_nak.3917222190
Short name	T2478
Test name
Test status
Simulation time	231741640 ps
CPU time	0.94 seconds
Started	Aug 01 06:18:00 PM PDT 24
Finished	Aug 01 06:18:01 PM PDT 24
Peak memory	206916 kb
Host	smart-db22930b-fa01-44c9-a767-478dc4386d10
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39172 22190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3917222190
Directory	/workspace/36.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/36.usbdev_stall_trans.1354206779
Short name	T1994
Test name
Test status
Simulation time	189679146 ps
CPU time	0.94 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:17:59 PM PDT 24
Peak memory	206956 kb
Host	smart-09724bb6-9c3b-4e29-ac91-9d5e7e1c19eb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13542 06779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1354206779
Directory	/workspace/36.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/36.usbdev_stream_len_max.188923341
Short name	T1995
Test name
Test status
Simulation time	406238636 ps
CPU time	1.28 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206916 kb
Host	smart-0742092e-d9a0-440b-84fd-d623b0a90d56
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18892 3341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.188923341
Directory	/workspace/36.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/36.usbdev_streaming_out.1488136065
Short name	T1213
Test name
Test status
Simulation time	1440203904 ps
CPU time	40.88 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:18:39 PM PDT 24
Peak memory	223440 kb
Host	smart-21b95c2a-6494-41e6-af40-3b13d2239497
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14881 36065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.1488136065
Directory	/workspace/36.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.2397383341
Short name	T1044
Test name
Test status
Simulation time	1018245251 ps
CPU time	20.85 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	207152 kb
Host	smart-895e5e0b-dcde-4bdd-833c-97dbd7a57658
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397383341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos t_handshake.2397383341
Directory	/workspace/36.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/37.usbdev_alert_test.2516441766
Short name	T897
Test name
Test status
Simulation time	28306316 ps
CPU time	0.69 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:05 PM PDT 24
Peak memory	206944 kb
Host	smart-dc4222e2-5c03-41b9-b05b-d212f3a9208b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2516441766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2516441766
Directory	/workspace/37.usbdev_alert_test/latest

Test location	/workspace/coverage/default/37.usbdev_av_buffer.1597780011
Short name	T2163
Test name
Test status
Simulation time	179542046 ps
CPU time	0.95 seconds
Started	Aug 01 06:18:00 PM PDT 24
Finished	Aug 01 06:18:01 PM PDT 24
Peak memory	206928 kb
Host	smart-0311e745-fb7f-4afd-a790-2aa63fd4ea04
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15977 80011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.1597780011
Directory	/workspace/37.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/37.usbdev_bitstuff_err.3258075410
Short name	T1180
Test name
Test status
Simulation time	188212012 ps
CPU time	0.87 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:17:59 PM PDT 24
Peak memory	206916 kb
Host	smart-427e312e-c419-4fcf-8972-7aaa6b13d0d5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32580 75410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.3258075410
Directory	/workspace/37.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/37.usbdev_data_toggle_clear.790555778
Short name	T2697
Test name
Test status
Simulation time	269946039 ps
CPU time	1.16 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206952 kb
Host	smart-0d7afc7e-f05f-405c-abd3-0b51fa5dac80
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79055 5778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.790555778
Directory	/workspace/37.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/37.usbdev_device_address.1621586416
Short name	T2119
Test name
Test status
Simulation time	29231968156 ps
CPU time	47.25 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:18:44 PM PDT 24
Peak memory	207128 kb
Host	smart-0b23deda-b2b9-4823-963d-12b11f638823
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16215 86416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.1621586416
Directory	/workspace/37.usbdev_device_address/latest

Test location	/workspace/coverage/default/37.usbdev_device_timeout.1760850784
Short name	T1160
Test name
Test status
Simulation time	4323300701 ps
CPU time	37.85 seconds
Started	Aug 01 06:17:57 PM PDT 24
Finished	Aug 01 06:18:35 PM PDT 24
Peak memory	207088 kb
Host	smart-dc2ccaec-4212-4478-b1b1-c049c2efcdf5
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760850784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.1760850784
Directory	/workspace/37.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/37.usbdev_disable_endpoint.3685978330
Short name	T404
Test name
Test status
Simulation time	637084331 ps
CPU time	1.57 seconds
Started	Aug 01 06:17:58 PM PDT 24
Finished	Aug 01 06:18:00 PM PDT 24
Peak memory	206940 kb
Host	smart-12b512f9-666a-44ad-822e-f54448c0fa47
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859 78330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.3685978330
Directory	/workspace/37.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/37.usbdev_disconnected.1960104126
Short name	T1099
Test name
Test status
Simulation time	142886642 ps
CPU time	0.82 seconds
Started	Aug 01 06:17:55 PM PDT 24
Finished	Aug 01 06:17:56 PM PDT 24
Peak memory	206876 kb
Host	smart-38fc48cb-118f-4ca5-a838-af88c4cde51f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19601 04126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1960104126
Directory	/workspace/37.usbdev_disconnected/latest

Test location	/workspace/coverage/default/37.usbdev_enable.4268880632
Short name	T601
Test name
Test status
Simulation time	44898059 ps
CPU time	0.7 seconds
Started	Aug 01 06:18:01 PM PDT 24
Finished	Aug 01 06:18:02 PM PDT 24
Peak memory	206892 kb
Host	smart-e892f4a8-d29f-41a1-9077-b0f085cc3ecd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42688 80632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.4268880632
Directory	/workspace/37.usbdev_enable/latest

Test location	/workspace/coverage/default/37.usbdev_endpoint_access.614900481
Short name	T1357
Test name
Test status
Simulation time	947650811 ps
CPU time	2.45 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	207172 kb
Host	smart-7cc26970-3280-4913-988d-a41a6c5f6d37
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61490 0481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.614900481
Directory	/workspace/37.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/37.usbdev_endpoint_types.3663089420
Short name	T351
Test name
Test status
Simulation time	689651798 ps
CPU time	1.63 seconds
Started	Aug 01 06:18:03 PM PDT 24
Finished	Aug 01 06:18:04 PM PDT 24
Peak memory	206912 kb
Host	smart-a212fbf7-d839-4304-b5eb-16a589f9ed4b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3663089420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.3663089420
Directory	/workspace/37.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/37.usbdev_fifo_rst.4101150920
Short name	T1128
Test name
Test status
Simulation time	404489947 ps
CPU time	2.73 seconds
Started	Aug 01 06:18:05 PM PDT 24
Finished	Aug 01 06:18:08 PM PDT 24
Peak memory	207056 kb
Host	smart-802a54b1-babc-4c30-aee0-617677fb7510
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41011 50920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.4101150920
Directory	/workspace/37.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/37.usbdev_in_iso.3027996270
Short name	T1426
Test name
Test status
Simulation time	218626342 ps
CPU time	1.13 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:16 PM PDT 24
Peak memory	215332 kb
Host	smart-c18a9543-1e8c-496f-9689-8a120db9fee5
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3027996270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3027996270
Directory	/workspace/37.usbdev_in_iso/latest

Test location	/workspace/coverage/default/37.usbdev_in_stall.3084449092
Short name	T1090
Test name
Test status
Simulation time	166169996 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206920 kb
Host	smart-35e24c75-4d3a-4604-af80-a67b2136c234
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30844 49092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.3084449092
Directory	/workspace/37.usbdev_in_stall/latest

Test location	/workspace/coverage/default/37.usbdev_in_trans.1470917277
Short name	T2213
Test name
Test status
Simulation time	196479272 ps
CPU time	0.98 seconds
Started	Aug 01 06:18:03 PM PDT 24
Finished	Aug 01 06:18:04 PM PDT 24
Peak memory	206972 kb
Host	smart-25f23883-28f8-4f3a-ac95-c6b881e3a185
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14709 17277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.1470917277
Directory	/workspace/37.usbdev_in_trans/latest

Test location	/workspace/coverage/default/37.usbdev_invalid_sync.4269427415
Short name	T898
Test name
Test status
Simulation time	4575086599 ps
CPU time	47.45 seconds
Started	Aug 01 06:18:02 PM PDT 24
Finished	Aug 01 06:18:49 PM PDT 24
Peak memory	223536 kb
Host	smart-16824ee8-e336-4f1e-acf0-1edd714a837a
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4269427415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.4269427415
Directory	/workspace/37.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/37.usbdev_iso_retraction.470194517
Short name	T1143
Test name
Test status
Simulation time	5787173852 ps
CPU time	68.61 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:19:14 PM PDT 24
Peak memory	207096 kb
Host	smart-1717d307-8c8f-4098-a8f4-cf9f6d8c969f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=470194517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.470194517
Directory	/workspace/37.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/37.usbdev_link_in_err.2257923926
Short name	T1226
Test name
Test status
Simulation time	240694993 ps
CPU time	1.03 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:18:20 PM PDT 24
Peak memory	206980 kb
Host	smart-4ff54036-e1f2-450b-b84c-be39da5f4c2a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22579 23926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.2257923926
Directory	/workspace/37.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/37.usbdev_link_suspend.52332341
Short name	T2303
Test name
Test status
Simulation time	3822147543 ps
CPU time	5.14 seconds
Started	Aug 01 06:18:02 PM PDT 24
Finished	Aug 01 06:18:08 PM PDT 24
Peak memory	215320 kb
Host	smart-1b46bfe9-829e-4e39-9a44-186cd7b008b0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52332 341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.52332341
Directory	/workspace/37.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/37.usbdev_low_speed_traffic.211833331
Short name	T2405
Test name
Test status
Simulation time	3839584319 ps
CPU time	37.86 seconds
Started	Aug 01 06:18:03 PM PDT 24
Finished	Aug 01 06:18:41 PM PDT 24
Peak memory	217360 kb
Host	smart-a68c31e2-64e5-4222-b9d4-96fa41695eea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21183 3331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.211833331
Directory	/workspace/37.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/37.usbdev_max_inter_pkt_delay.825775678
Short name	T1665
Test name
Test status
Simulation time	4464341889 ps
CPU time	44.63 seconds
Started	Aug 01 06:18:13 PM PDT 24
Finished	Aug 01 06:18:58 PM PDT 24
Peak memory	215400 kb
Host	smart-9d6272d3-60e6-4226-ae0e-f98bd14bd59c
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=825775678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.825775678
Directory	/workspace/37.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/37.usbdev_max_length_in_transaction.2403269982
Short name	T2864
Test name
Test status
Simulation time	239508766 ps
CPU time	1.09 seconds
Started	Aug 01 06:18:02 PM PDT 24
Finished	Aug 01 06:18:03 PM PDT 24
Peak memory	206964 kb
Host	smart-06a08131-2e54-4f32-8b18-88596ce07d26
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2403269982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.2403269982
Directory	/workspace/37.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/37.usbdev_max_length_out_transaction.1313075901
Short name	T1532
Test name
Test status
Simulation time	213874851 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:10 PM PDT 24
Finished	Aug 01 06:18:11 PM PDT 24
Peak memory	206960 kb
Host	smart-24a95e0f-2060-476e-b7f6-97600641ef12
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13130 75901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1313075901
Directory	/workspace/37.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/37.usbdev_min_inter_pkt_delay.142747400
Short name	T1288
Test name
Test status
Simulation time	2049229737 ps
CPU time	21.21 seconds
Started	Aug 01 06:18:13 PM PDT 24
Finished	Aug 01 06:18:34 PM PDT 24
Peak memory	223480 kb
Host	smart-110ab770-8d6a-4a8c-83dc-ca804e9a1591
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=142747400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.142747400
Directory	/workspace/37.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/37.usbdev_min_length_in_transaction.1064187998
Short name	T1408
Test name
Test status
Simulation time	164443023 ps
CPU time	0.87 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:13 PM PDT 24
Peak memory	206948 kb
Host	smart-ddcdddf1-bb3c-40c5-a54b-13c5587aa846
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1064187998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1064187998
Directory	/workspace/37.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/37.usbdev_min_length_out_transaction.2877444602
Short name	T2428
Test name
Test status
Simulation time	168086513 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:02 PM PDT 24
Finished	Aug 01 06:18:03 PM PDT 24
Peak memory	206948 kb
Host	smart-dd7a4c1a-3ed5-4d55-aa4e-efd14f00c2f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28774 44602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2877444602
Directory	/workspace/37.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/37.usbdev_nak_trans.95606063
Short name	T171
Test name
Test status
Simulation time	204728949 ps
CPU time	0.94 seconds
Started	Aug 01 06:18:06 PM PDT 24
Finished	Aug 01 06:18:07 PM PDT 24
Peak memory	206908 kb
Host	smart-b3b5b9df-03f3-4ca3-864f-fbcdb7c199ec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95606 063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.95606063
Directory	/workspace/37.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/37.usbdev_out_iso.643654532
Short name	T158
Test name
Test status
Simulation time	146831748 ps
CPU time	0.87 seconds
Started	Aug 01 06:18:05 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206952 kb
Host	smart-cb0847e8-5286-4366-ab4d-8fd9b484beb0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64365 4532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.643654532
Directory	/workspace/37.usbdev_out_iso/latest

Test location	/workspace/coverage/default/37.usbdev_out_stall.2472597371
Short name	T2527
Test name
Test status
Simulation time	196648976 ps
CPU time	1.01 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206920 kb
Host	smart-a7997bde-8ee4-4366-9848-df717f657422
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24725 97371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2472597371
Directory	/workspace/37.usbdev_out_stall/latest

Test location	/workspace/coverage/default/37.usbdev_out_trans_nak.2068081753
Short name	T2007
Test name
Test status
Simulation time	155332543 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:02 PM PDT 24
Finished	Aug 01 06:18:03 PM PDT 24
Peak memory	206940 kb
Host	smart-5b13cdb8-7421-43d0-8e67-5f9706d9fc12
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20680 81753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2068081753
Directory	/workspace/37.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/37.usbdev_pending_in_trans.696941259
Short name	T1209
Test name
Test status
Simulation time	160871779 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:13 PM PDT 24
Finished	Aug 01 06:18:14 PM PDT 24
Peak memory	206968 kb
Host	smart-d1896976-2d5a-48d7-9958-1b1bc18e1216
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69694 1259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.696941259
Directory	/workspace/37.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/37.usbdev_phy_config_pinflip.2232702272
Short name	T2903
Test name
Test status
Simulation time	313027296 ps
CPU time	1.1 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206944 kb
Host	smart-e72e6656-967c-4154-aaa3-039c117916b6
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2232702272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2232702272
Directory	/workspace/37.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2923958014
Short name	T2777
Test name
Test status
Simulation time	146010355 ps
CPU time	0.84 seconds
Started	Aug 01 06:18:05 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206876 kb
Host	smart-eb6f425e-7f07-4f0c-8199-615aded13a03
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29239 58014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2923958014
Directory	/workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/37.usbdev_phy_pins_sense.3794210027
Short name	T1559
Test name
Test status
Simulation time	36177467 ps
CPU time	0.68 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:04 PM PDT 24
Peak memory	206844 kb
Host	smart-3546ceb9-09da-4b40-b529-e047242809a7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37942 10027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3794210027
Directory	/workspace/37.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/37.usbdev_pkt_buffer.1024036607
Short name	T2653
Test name
Test status
Simulation time	13655100377 ps
CPU time	36.86 seconds
Started	Aug 01 06:18:10 PM PDT 24
Finished	Aug 01 06:18:47 PM PDT 24
Peak memory	214792 kb
Host	smart-d42180ea-76f7-42a6-a8bc-d52cb85006c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10240 36607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1024036607
Directory	/workspace/37.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/37.usbdev_pkt_received.4055970996
Short name	T842
Test name
Test status
Simulation time	166381759 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:05 PM PDT 24
Peak memory	206944 kb
Host	smart-5a7bb9ad-83d2-4192-b9dd-73ba82a8187c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40559 70996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.4055970996
Directory	/workspace/37.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/37.usbdev_pkt_sent.3539768348
Short name	T2614
Test name
Test status
Simulation time	189870582 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:03 PM PDT 24
Finished	Aug 01 06:18:04 PM PDT 24
Peak memory	206944 kb
Host	smart-3692a98a-e96a-423f-9c91-c97963aaf2fb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35397 68348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3539768348
Directory	/workspace/37.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/37.usbdev_random_length_in_transaction.2276253685
Short name	T1684
Test name
Test status
Simulation time	198061388 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206960 kb
Host	smart-8274c481-82a2-4d6c-8394-05d75bb03359
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22762 53685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2276253685
Directory	/workspace/37.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/37.usbdev_random_length_out_transaction.1693397030
Short name	T2516
Test name
Test status
Simulation time	183736439 ps
CPU time	0.95 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:05 PM PDT 24
Peak memory	206948 kb
Host	smart-d35b33fb-a697-4691-9a7d-c4284b46dec8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16933 97030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1693397030
Directory	/workspace/37.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/37.usbdev_rx_crc_err.1812059326
Short name	T58
Test name
Test status
Simulation time	196868471 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:13 PM PDT 24
Peak memory	206924 kb
Host	smart-b3ae27c7-e62a-4f7e-a5b0-5e03a22ec8af
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18120 59326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.1812059326
Directory	/workspace/37.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/37.usbdev_rx_full.3215799372
Short name	T2809
Test name
Test status
Simulation time	248484196 ps
CPU time	1.11 seconds
Started	Aug 01 06:18:03 PM PDT 24
Finished	Aug 01 06:18:04 PM PDT 24
Peak memory	206880 kb
Host	smart-8ede0f93-398b-430e-b7f1-57ebc9ad44db
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32157 99372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.3215799372
Directory	/workspace/37.usbdev_rx_full/latest

Test location	/workspace/coverage/default/37.usbdev_setup_stage.350040707
Short name	T2522
Test name
Test status
Simulation time	142796899 ps
CPU time	0.84 seconds
Started	Aug 01 06:18:00 PM PDT 24
Finished	Aug 01 06:18:01 PM PDT 24
Peak memory	206888 kb
Host	smart-78b095c0-57bc-458b-a4e3-aa415dd56bbf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35004 0707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.350040707
Directory	/workspace/37.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/37.usbdev_setup_trans_ignored.1014159339
Short name	T2800
Test name
Test status
Simulation time	155966340 ps
CPU time	0.83 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:13 PM PDT 24
Peak memory	206948 kb
Host	smart-97add6c2-6882-43be-af62-91e3c0be4221
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10141 59339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.1014159339
Directory	/workspace/37.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/37.usbdev_smoke.295459959
Short name	T1912
Test name
Test status
Simulation time	260479957 ps
CPU time	1.09 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:05 PM PDT 24
Peak memory	206920 kb
Host	smart-547d4a88-f872-4209-8ae8-1cecc663bde5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29545 9959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.295459959
Directory	/workspace/37.usbdev_smoke/latest

Test location	/workspace/coverage/default/37.usbdev_spurious_pids_ignored.389574928
Short name	T2069
Test name
Test status
Simulation time	2059469232 ps
CPU time	15.14 seconds
Started	Aug 01 06:18:02 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	207164 kb
Host	smart-f0416f55-c211-4204-9749-b79f31a2df82
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=389574928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.389574928
Directory	/workspace/37.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/37.usbdev_stall_priority_over_nak.679493477
Short name	T1052
Test name
Test status
Simulation time	149227640 ps
CPU time	0.8 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:13 PM PDT 24
Peak memory	206948 kb
Host	smart-9d613540-bf81-4c59-8f77-e5e49042352f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67949 3477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.679493477
Directory	/workspace/37.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/37.usbdev_stall_trans.4055475373
Short name	T1429
Test name
Test status
Simulation time	171514630 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:13 PM PDT 24
Peak memory	206920 kb
Host	smart-ace103d0-4ed6-4ce2-bf2c-cb5f8da58d82
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40554 75373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.4055475373
Directory	/workspace/37.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/37.usbdev_stream_len_max.2800479675
Short name	T2140
Test name
Test status
Simulation time	749479496 ps
CPU time	2.08 seconds
Started	Aug 01 06:18:00 PM PDT 24
Finished	Aug 01 06:18:03 PM PDT 24
Peak memory	206864 kb
Host	smart-ba8c8b30-bc6a-4a38-9632-279c924e1be3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28004 79675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2800479675
Directory	/workspace/37.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/37.usbdev_streaming_out.1590847382
Short name	T480
Test name
Test status
Simulation time	1793224305 ps
CPU time	12.88 seconds
Started	Aug 01 06:18:14 PM PDT 24
Finished	Aug 01 06:18:27 PM PDT 24
Peak memory	207152 kb
Host	smart-113c7243-6313-4753-a886-a65d61387820
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15908 47382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.1590847382
Directory	/workspace/37.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.343491223
Short name	T1808
Test name
Test status
Simulation time	1003199709 ps
CPU time	22.18 seconds
Started	Aug 01 06:17:59 PM PDT 24
Finished	Aug 01 06:18:21 PM PDT 24
Peak memory	207196 kb
Host	smart-c0f072ad-c51c-4eae-98ed-0dcc3830e9ea
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343491223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_host _handshake.343491223
Directory	/workspace/37.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/38.usbdev_alert_test.3064876212
Short name	T117
Test name
Test status
Simulation time	51552345 ps
CPU time	0.68 seconds
Started	Aug 01 06:18:18 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	206968 kb
Host	smart-d981686b-5e1a-48b9-9cbc-dd5a502a2ee7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3064876212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.3064876212
Directory	/workspace/38.usbdev_alert_test/latest

Test location	/workspace/coverage/default/38.usbdev_av_buffer.579034945
Short name	T1359
Test name
Test status
Simulation time	181819563 ps
CPU time	0.91 seconds
Started	Aug 01 06:18:00 PM PDT 24
Finished	Aug 01 06:18:01 PM PDT 24
Peak memory	206952 kb
Host	smart-5a573dbc-ca85-4e53-9871-b8c0c8753364
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57903 4945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.579034945
Directory	/workspace/38.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/38.usbdev_bitstuff_err.2119463308
Short name	T1805
Test name
Test status
Simulation time	171478216 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:11 PM PDT 24
Finished	Aug 01 06:18:12 PM PDT 24
Peak memory	206884 kb
Host	smart-2fac6e0f-406c-4ec0-bf2d-d11bc66f22ad
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21194 63308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.2119463308
Directory	/workspace/38.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/38.usbdev_data_toggle_clear.656465865
Short name	T632
Test name
Test status
Simulation time	228153494 ps
CPU time	1.03 seconds
Started	Aug 01 06:18:06 PM PDT 24
Finished	Aug 01 06:18:07 PM PDT 24
Peak memory	206932 kb
Host	smart-2673fcd8-6acc-4e32-ae12-e9dc27d6a8c4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65646 5865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.656465865
Directory	/workspace/38.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/38.usbdev_data_toggle_restore.875360883
Short name	T2541
Test name
Test status
Simulation time	480714509 ps
CPU time	1.62 seconds
Started	Aug 01 06:18:02 PM PDT 24
Finished	Aug 01 06:18:03 PM PDT 24
Peak memory	206800 kb
Host	smart-4c045ab1-5843-4a89-8972-960b8c937ca2
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=875360883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.875360883
Directory	/workspace/38.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/38.usbdev_device_address.1457816366
Short name	T353
Test name
Test status
Simulation time	44658398174 ps
CPU time	69.45 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:19:22 PM PDT 24
Peak memory	207180 kb
Host	smart-010acfd4-013e-4313-ac6f-19b46c13031e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14578 16366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1457816366
Directory	/workspace/38.usbdev_device_address/latest

Test location	/workspace/coverage/default/38.usbdev_device_timeout.2733281074
Short name	T625
Test name
Test status
Simulation time	1024656469 ps
CPU time	21.16 seconds
Started	Aug 01 06:18:11 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	207108 kb
Host	smart-bf3221f2-50a6-46c5-9cb7-20ae1aa533cc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733281074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.2733281074
Directory	/workspace/38.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/38.usbdev_disable_endpoint.2782626232
Short name	T2608
Test name
Test status
Simulation time	627340188 ps
CPU time	1.62 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206940 kb
Host	smart-88123d55-363d-4768-bd31-a56f62751137
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27826 26232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2782626232
Directory	/workspace/38.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/38.usbdev_disconnected.1353753890
Short name	T1753
Test name
Test status
Simulation time	170953498 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:07 PM PDT 24
Finished	Aug 01 06:18:08 PM PDT 24
Peak memory	206912 kb
Host	smart-b1eb651a-ada2-48f9-b499-7ef9644ab24e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13537 53890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.1353753890
Directory	/workspace/38.usbdev_disconnected/latest

Test location	/workspace/coverage/default/38.usbdev_enable.1367912850
Short name	T2208
Test name
Test status
Simulation time	44361311 ps
CPU time	0.7 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:05 PM PDT 24
Peak memory	206916 kb
Host	smart-a9aaffca-c692-42e1-85f7-dd7d5a982a81
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13679 12850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1367912850
Directory	/workspace/38.usbdev_enable/latest

Test location	/workspace/coverage/default/38.usbdev_endpoint_access.976500156
Short name	T1073
Test name
Test status
Simulation time	983481355 ps
CPU time	2.72 seconds
Started	Aug 01 06:18:03 PM PDT 24
Finished	Aug 01 06:18:05 PM PDT 24
Peak memory	207144 kb
Host	smart-81750602-0c92-4a01-b919-42fb763ab486
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97650 0156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.976500156
Directory	/workspace/38.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/38.usbdev_endpoint_types.3314575470
Short name	T312
Test name
Test status
Simulation time	382838843 ps
CPU time	1.25 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:13 PM PDT 24
Peak memory	206900 kb
Host	smart-496e740d-5c9c-4d92-b95b-991597a76ab7
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3314575470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.3314575470
Directory	/workspace/38.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/38.usbdev_fifo_rst.2155495737
Short name	T2276
Test name
Test status
Simulation time	418121326 ps
CPU time	2.96 seconds
Started	Aug 01 06:18:10 PM PDT 24
Finished	Aug 01 06:18:13 PM PDT 24
Peak memory	207068 kb
Host	smart-7c2f9374-9fa6-4075-8ef6-54f8541f16bf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21554 95737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2155495737
Directory	/workspace/38.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/38.usbdev_in_iso.4194818395
Short name	T2111
Test name
Test status
Simulation time	168930581 ps
CPU time	0.91 seconds
Started	Aug 01 06:18:10 PM PDT 24
Finished	Aug 01 06:18:11 PM PDT 24
Peak memory	206928 kb
Host	smart-7c66f4a9-79b9-4f34-9349-0b76d44ff25d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4194818395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.4194818395
Directory	/workspace/38.usbdev_in_iso/latest

Test location	/workspace/coverage/default/38.usbdev_in_stall.3695451308
Short name	T2106
Test name
Test status
Simulation time	175943746 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:13 PM PDT 24
Finished	Aug 01 06:18:14 PM PDT 24
Peak memory	206932 kb
Host	smart-b2271e28-a0ba-4f66-9340-0ae34f99179b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36954 51308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3695451308
Directory	/workspace/38.usbdev_in_stall/latest

Test location	/workspace/coverage/default/38.usbdev_in_trans.3025336416
Short name	T650
Test name
Test status
Simulation time	240659828 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:13 PM PDT 24
Peak memory	206928 kb
Host	smart-40a619f7-186f-4408-8223-75fa65e3cbb8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30253 36416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3025336416
Directory	/workspace/38.usbdev_in_trans/latest

Test location	/workspace/coverage/default/38.usbdev_invalid_sync.2030206566
Short name	T2287
Test name
Test status
Simulation time	3652386988 ps
CPU time	28.12 seconds
Started	Aug 01 06:18:10 PM PDT 24
Finished	Aug 01 06:18:38 PM PDT 24
Peak memory	217528 kb
Host	smart-04dc9122-3729-4f39-b649-526dfbde808e
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2030206566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.2030206566
Directory	/workspace/38.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/38.usbdev_iso_retraction.442126190
Short name	T2846
Test name
Test status
Simulation time	3483224516 ps
CPU time	42.91 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:56 PM PDT 24
Peak memory	207144 kb
Host	smart-54b63699-cd04-4951-86f8-909de5319127
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=442126190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.442126190
Directory	/workspace/38.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/38.usbdev_link_in_err.4265300196
Short name	T2589
Test name
Test status
Simulation time	194963713 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:11 PM PDT 24
Finished	Aug 01 06:18:12 PM PDT 24
Peak memory	206952 kb
Host	smart-a58ce9fc-dce3-4e64-800e-3730d715807a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42653 00196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.4265300196
Directory	/workspace/38.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/38.usbdev_link_suspend.4221835572
Short name	T1990
Test name
Test status
Simulation time	4323879081 ps
CPU time	5.52 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	207108 kb
Host	smart-4a4e9216-57be-42e3-a6e4-a9c56b6d2026
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218 35572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.4221835572
Directory	/workspace/38.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/38.usbdev_low_speed_traffic.2534976386
Short name	T1026
Test name
Test status
Simulation time	3002192943 ps
CPU time	84.94 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:19:37 PM PDT 24
Peak memory	217908 kb
Host	smart-7bad44a9-abaa-4340-8aed-d43174737b15
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25349 76386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2534976386
Directory	/workspace/38.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/38.usbdev_max_inter_pkt_delay.19285507
Short name	T2883
Test name
Test status
Simulation time	2218520225 ps
CPU time	16.58 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:21 PM PDT 24
Peak memory	223540 kb
Host	smart-9b48e164-d090-4d2c-9665-369788d590dd
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=19285507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.19285507
Directory	/workspace/38.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/38.usbdev_max_length_in_transaction.4035104043
Short name	T1095
Test name
Test status
Simulation time	248508467 ps
CPU time	0.98 seconds
Started	Aug 01 06:18:06 PM PDT 24
Finished	Aug 01 06:18:07 PM PDT 24
Peak memory	206948 kb
Host	smart-00f99589-0a8d-4e7c-999a-1cf2201f4b31
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=4035104043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.4035104043
Directory	/workspace/38.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/38.usbdev_max_length_out_transaction.1494569718
Short name	T1865
Test name
Test status
Simulation time	249176500 ps
CPU time	1.08 seconds
Started	Aug 01 06:18:12 PM PDT 24
Finished	Aug 01 06:18:14 PM PDT 24
Peak memory	206948 kb
Host	smart-951e10e7-7d4b-4821-99d9-277753e84ee6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14945 69718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1494569718
Directory	/workspace/38.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/38.usbdev_min_inter_pkt_delay.1080699448
Short name	T874
Test name
Test status
Simulation time	2717773452 ps
CPU time	75.29 seconds
Started	Aug 01 06:18:09 PM PDT 24
Finished	Aug 01 06:19:25 PM PDT 24
Peak memory	215408 kb
Host	smart-a442b96e-b1d3-4e9e-b20d-138f3bf09223
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1080699448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.1080699448
Directory	/workspace/38.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/38.usbdev_min_length_in_transaction.3374041321
Short name	T1156
Test name
Test status
Simulation time	157127692 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:16 PM PDT 24
Peak memory	206956 kb
Host	smart-323b46a6-0fbd-4a0b-8371-1872bb69d16c
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3374041321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3374041321
Directory	/workspace/38.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/38.usbdev_min_length_out_transaction.1582694763
Short name	T2010
Test name
Test status
Simulation time	203549773 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:11 PM PDT 24
Finished	Aug 01 06:18:12 PM PDT 24
Peak memory	206948 kb
Host	smart-7567b6df-e80c-47b8-8e94-7d36720157d7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15826 94763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.1582694763
Directory	/workspace/38.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/38.usbdev_nak_trans.4166390073
Short name	T194
Test name
Test status
Simulation time	211551926 ps
CPU time	0.95 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:05 PM PDT 24
Peak memory	206944 kb
Host	smart-270cfe78-4b4e-4861-8d95-8e37c02db695
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41663 90073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.4166390073
Directory	/workspace/38.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/38.usbdev_out_iso.3393628929
Short name	T1091
Test name
Test status
Simulation time	175268861 ps
CPU time	0.93 seconds
Started	Aug 01 06:18:10 PM PDT 24
Finished	Aug 01 06:18:11 PM PDT 24
Peak memory	206968 kb
Host	smart-5fd10c01-ba7b-47e0-83ff-ff7e70ad5d2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33936 28929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3393628929
Directory	/workspace/38.usbdev_out_iso/latest

Test location	/workspace/coverage/default/38.usbdev_out_stall.2852905902
Short name	T1267
Test name
Test status
Simulation time	185889120 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:11 PM PDT 24
Finished	Aug 01 06:18:12 PM PDT 24
Peak memory	206964 kb
Host	smart-533ab3ea-7b57-4024-92c9-d23f8b09920e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28529 05902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2852905902
Directory	/workspace/38.usbdev_out_stall/latest

Test location	/workspace/coverage/default/38.usbdev_out_trans_nak.438769752
Short name	T1716
Test name
Test status
Simulation time	157443437 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:10 PM PDT 24
Finished	Aug 01 06:18:11 PM PDT 24
Peak memory	206960 kb
Host	smart-0cc19f49-8749-41c6-9fab-c89284f97e34
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43876 9752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.438769752
Directory	/workspace/38.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/38.usbdev_pending_in_trans.2488005940
Short name	T830
Test name
Test status
Simulation time	188224288 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:10 PM PDT 24
Finished	Aug 01 06:18:11 PM PDT 24
Peak memory	206972 kb
Host	smart-7e993db2-c845-4c38-9fa4-654f2411d203
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24880 05940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2488005940
Directory	/workspace/38.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/38.usbdev_phy_config_pinflip.296972872
Short name	T2273
Test name
Test status
Simulation time	244583538 ps
CPU time	1.04 seconds
Started	Aug 01 06:18:11 PM PDT 24
Finished	Aug 01 06:18:12 PM PDT 24
Peak memory	206920 kb
Host	smart-feaa2f30-69e3-412b-9ac8-c1dd6d99f556
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=296972872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.296972872
Directory	/workspace/38.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1423739947
Short name	T1307
Test name
Test status
Simulation time	158886310 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:05 PM PDT 24
Finished	Aug 01 06:18:06 PM PDT 24
Peak memory	206868 kb
Host	smart-dd6cf4ef-01b8-4f08-a054-ef7b0d7beace
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14237 39947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1423739947
Directory	/workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/38.usbdev_phy_pins_sense.768220155
Short name	T2001
Test name
Test status
Simulation time	37200237 ps
CPU time	0.68 seconds
Started	Aug 01 06:18:04 PM PDT 24
Finished	Aug 01 06:18:05 PM PDT 24
Peak memory	206916 kb
Host	smart-3d2d84b4-5a48-42fc-acea-78c44d5da03d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76822 0155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.768220155
Directory	/workspace/38.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/38.usbdev_pkt_buffer.132820328
Short name	T2322
Test name
Test status
Simulation time	17040462629 ps
CPU time	40.2 seconds
Started	Aug 01 06:18:01 PM PDT 24
Finished	Aug 01 06:18:42 PM PDT 24
Peak memory	220024 kb
Host	smart-24593006-e643-4dc1-95a6-3af627cb86e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13282 0328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.132820328
Directory	/workspace/38.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/38.usbdev_pkt_received.3488415916
Short name	T1866
Test name
Test status
Simulation time	143375405 ps
CPU time	0.87 seconds
Started	Aug 01 06:18:18 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	206948 kb
Host	smart-cee27130-4fda-4986-82bc-5591809bbc7b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34884 15916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3488415916
Directory	/workspace/38.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/38.usbdev_pkt_sent.584428176
Short name	T11
Test name
Test status
Simulation time	199648982 ps
CPU time	0.98 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	206916 kb
Host	smart-9eeb3f93-341b-4219-becc-53e0ad4c0231
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58442 8176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.584428176
Directory	/workspace/38.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/38.usbdev_random_length_in_transaction.3856019349
Short name	T620
Test name
Test status
Simulation time	213482153 ps
CPU time	1.12 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	206972 kb
Host	smart-950594d2-4492-40e3-91e4-1d6d25809826
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38560 19349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3856019349
Directory	/workspace/38.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/38.usbdev_random_length_out_transaction.1484490563
Short name	T978
Test name
Test status
Simulation time	193062285 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:18 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	206956 kb
Host	smart-1e311ada-ecec-4176-a032-74a11e82bd67
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14844 90563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1484490563
Directory	/workspace/38.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/38.usbdev_rx_crc_err.3541567958
Short name	T979
Test name
Test status
Simulation time	191626604 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:18:20 PM PDT 24
Peak memory	206900 kb
Host	smart-1dab84b5-e399-4a0b-bdfb-bb9df5741402
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35415 67958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3541567958
Directory	/workspace/38.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/38.usbdev_rx_full.2643813029
Short name	T2528
Test name
Test status
Simulation time	297994861 ps
CPU time	1.21 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	206952 kb
Host	smart-94d3e8a6-35b9-4ea0-ae6c-a30e606ea4e4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26438 13029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.2643813029
Directory	/workspace/38.usbdev_rx_full/latest

Test location	/workspace/coverage/default/38.usbdev_setup_stage.1680705901
Short name	T825
Test name
Test status
Simulation time	173838553 ps
CPU time	0.97 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:17 PM PDT 24
Peak memory	206764 kb
Host	smart-3e9ba39a-7bf2-468e-bb57-6ad12dccb6a4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16807 05901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.1680705901
Directory	/workspace/38.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/38.usbdev_setup_trans_ignored.821109051
Short name	T1982
Test name
Test status
Simulation time	150004921 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:16 PM PDT 24
Peak memory	206924 kb
Host	smart-7ba29a5e-7ce1-455b-8e32-dfc8f7c5c08a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82110 9051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.821109051
Directory	/workspace/38.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/38.usbdev_smoke.3171185217
Short name	T2369
Test name
Test status
Simulation time	220032550 ps
CPU time	1.06 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:18:20 PM PDT 24
Peak memory	206964 kb
Host	smart-890a09e9-4d80-4589-a92c-fc205ca982f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31711 85217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3171185217
Directory	/workspace/38.usbdev_smoke/latest

Test location	/workspace/coverage/default/38.usbdev_spurious_pids_ignored.878891186
Short name	T1968
Test name
Test status
Simulation time	2645308893 ps
CPU time	26.6 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:42 PM PDT 24
Peak memory	223472 kb
Host	smart-b7698072-3b79-401a-8567-a3512fd23df0
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=878891186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.878891186
Directory	/workspace/38.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/38.usbdev_stall_priority_over_nak.3340670115
Short name	T1363
Test name
Test status
Simulation time	178056374 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	206932 kb
Host	smart-235e7f90-8936-4e39-b8aa-ba2738d09c46
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33406 70115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3340670115
Directory	/workspace/38.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/38.usbdev_stall_trans.521513418
Short name	T1053
Test name
Test status
Simulation time	177314290 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:17 PM PDT 24
Peak memory	206948 kb
Host	smart-8980fd6c-2440-4dac-b392-757906190cd8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52151 3418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.521513418
Directory	/workspace/38.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/38.usbdev_stream_len_max.2198946037
Short name	T920
Test name
Test status
Simulation time	328146766 ps
CPU time	1.2 seconds
Started	Aug 01 06:18:18 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	206876 kb
Host	smart-f2a4abb0-4200-42cd-ab63-2a1ba36b6d25
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21989 46037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2198946037
Directory	/workspace/38.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/38.usbdev_streaming_out.1290509482
Short name	T2782
Test name
Test status
Simulation time	3455484136 ps
CPU time	37.52 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:54 PM PDT 24
Peak memory	215392 kb
Host	smart-e8a17e47-48a3-40e1-84c6-635e553f3f2b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12905 09482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1290509482
Directory	/workspace/38.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.878219847
Short name	T608
Test name
Test status
Simulation time	416850898 ps
CPU time	8.08 seconds
Started	Aug 01 06:18:03 PM PDT 24
Finished	Aug 01 06:18:12 PM PDT 24
Peak memory	207124 kb
Host	smart-7e77d892-f855-42ec-9a01-56d68f96b4a7
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878219847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_host _handshake.878219847
Directory	/workspace/38.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/39.usbdev_alert_test.3353826262
Short name	T2646
Test name
Test status
Simulation time	84447172 ps
CPU time	0.7 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	206984 kb
Host	smart-7ac6a1bf-d74b-404f-90c1-39f460e9b506
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3353826262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3353826262
Directory	/workspace/39.usbdev_alert_test/latest

Test location	/workspace/coverage/default/39.usbdev_av_buffer.1334886729
Short name	T2321
Test name
Test status
Simulation time	161485189 ps
CPU time	0.93 seconds
Started	Aug 01 06:18:14 PM PDT 24
Finished	Aug 01 06:18:15 PM PDT 24
Peak memory	207168 kb
Host	smart-19214fc0-0c8d-4d7e-ad5d-ea3b4c33f590
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13348 86729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1334886729
Directory	/workspace/39.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/39.usbdev_bitstuff_err.2717476843
Short name	T1624
Test name
Test status
Simulation time	150869891 ps
CPU time	0.83 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:18:20 PM PDT 24
Peak memory	206892 kb
Host	smart-542ac24c-9429-453b-b820-d38da50f635b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27174 76843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2717476843
Directory	/workspace/39.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/39.usbdev_data_toggle_clear.719477440
Short name	T1966
Test name
Test status
Simulation time	436459286 ps
CPU time	1.47 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:16 PM PDT 24
Peak memory	206912 kb
Host	smart-3b4fc03e-6a6c-4f1b-9530-08b50eb39f1c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71947 7440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.719477440
Directory	/workspace/39.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/39.usbdev_data_toggle_restore.2019124272
Short name	T448
Test name
Test status
Simulation time	1265805188 ps
CPU time	3.11 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	207196 kb
Host	smart-ad4c4221-a1b7-4df8-8084-d115066b710a
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2019124272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.2019124272
Directory	/workspace/39.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/39.usbdev_device_timeout.3591594629
Short name	T2553
Test name
Test status
Simulation time	3911587957 ps
CPU time	34.97 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	207132 kb
Host	smart-394b862a-012b-4af4-b193-d12f2ef2d6b0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591594629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.3591594629
Directory	/workspace/39.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/39.usbdev_disable_endpoint.2093184034
Short name	T1388
Test name
Test status
Simulation time	729904733 ps
CPU time	1.91 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	206948 kb
Host	smart-58c08083-fa79-4689-ad72-6bb060134479
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20931 84034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2093184034
Directory	/workspace/39.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/39.usbdev_disconnected.1001960792
Short name	T1071
Test name
Test status
Simulation time	141319439 ps
CPU time	0.83 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:17 PM PDT 24
Peak memory	206872 kb
Host	smart-67d63d5e-6e7e-42bf-8006-5a1c545d87cd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10019 60792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1001960792
Directory	/workspace/39.usbdev_disconnected/latest

Test location	/workspace/coverage/default/39.usbdev_enable.2598482648
Short name	T2767
Test name
Test status
Simulation time	48395264 ps
CPU time	0.72 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	206884 kb
Host	smart-4ee62842-11c2-4570-ac7e-28b2ede23cc0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25984 82648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2598482648
Directory	/workspace/39.usbdev_enable/latest

Test location	/workspace/coverage/default/39.usbdev_endpoint_access.2552664617
Short name	T1377
Test name
Test status
Simulation time	979070406 ps
CPU time	2.86 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	207160 kb
Host	smart-4bf61f82-1aab-4773-9e3c-60a707d5d90b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25526 64617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.2552664617
Directory	/workspace/39.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/39.usbdev_endpoint_types.2459116057
Short name	T392
Test name
Test status
Simulation time	417902594 ps
CPU time	1.36 seconds
Started	Aug 01 06:18:14 PM PDT 24
Finished	Aug 01 06:18:16 PM PDT 24
Peak memory	206904 kb
Host	smart-82d6af28-a9eb-45d8-a8d0-8af8da32ee12
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2459116057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.2459116057
Directory	/workspace/39.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/39.usbdev_fifo_rst.2710058677
Short name	T2427
Test name
Test status
Simulation time	311807418 ps
CPU time	1.97 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	207100 kb
Host	smart-98246178-23da-48d5-b06c-f65fff60e077
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27100 58677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.2710058677
Directory	/workspace/39.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/39.usbdev_in_iso.850428639
Short name	T974
Test name
Test status
Simulation time	248169846 ps
CPU time	1.08 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	215360 kb
Host	smart-4294d31a-1b21-4b46-84fc-19f6b00eef72
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=850428639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.850428639
Directory	/workspace/39.usbdev_in_iso/latest

Test location	/workspace/coverage/default/39.usbdev_in_stall.1250636930
Short name	T2360
Test name
Test status
Simulation time	173734472 ps
CPU time	0.87 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:18:20 PM PDT 24
Peak memory	206916 kb
Host	smart-3e615ffa-cc39-461c-bf03-70ca57e5bc0e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506 36930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.1250636930
Directory	/workspace/39.usbdev_in_stall/latest

Test location	/workspace/coverage/default/39.usbdev_in_trans.613781070
Short name	T2670
Test name
Test status
Simulation time	233101486 ps
CPU time	0.99 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:16 PM PDT 24
Peak memory	206924 kb
Host	smart-e76d239c-8a3a-4680-bcd2-04dde4107381
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61378 1070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.613781070
Directory	/workspace/39.usbdev_in_trans/latest

Test location	/workspace/coverage/default/39.usbdev_invalid_sync.1455570493
Short name	T591
Test name
Test status
Simulation time	2816046252 ps
CPU time	78.43 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:19:38 PM PDT 24
Peak memory	223496 kb
Host	smart-8009cdc8-eb8f-4116-a88b-0164553f2e28
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1455570493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.1455570493
Directory	/workspace/39.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/39.usbdev_link_in_err.2040416510
Short name	T2542
Test name
Test status
Simulation time	200325228 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:16 PM PDT 24
Peak memory	206944 kb
Host	smart-c7f20626-4804-43e5-aa39-532be1f09498
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20404 16510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2040416510
Directory	/workspace/39.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/39.usbdev_link_suspend.3034015005
Short name	T91
Test name
Test status
Simulation time	10015199396 ps
CPU time	13.49 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:18:33 PM PDT 24
Peak memory	207152 kb
Host	smart-784e7eb5-cf31-4689-95d7-8c81ea7a0845
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30340 15005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3034015005
Directory	/workspace/39.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/39.usbdev_low_speed_traffic.134657859
Short name	T2545
Test name
Test status
Simulation time	2173902916 ps
CPU time	58.55 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	217724 kb
Host	smart-b3b4d14b-7974-4d4d-9a21-cff0c3977785
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13465 7859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.134657859
Directory	/workspace/39.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2206621989
Short name	T2362
Test name
Test status
Simulation time	3608522910 ps
CPU time	38.14 seconds
Started	Aug 01 06:18:15 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	216880 kb
Host	smart-9a0fa110-370a-4933-a41a-b4d37945a18f
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2206621989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2206621989
Directory	/workspace/39.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/39.usbdev_max_length_in_transaction.425673274
Short name	T2080
Test name
Test status
Simulation time	245215504 ps
CPU time	0.99 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:17 PM PDT 24
Peak memory	206944 kb
Host	smart-8c027a6e-a1e8-42e1-a15d-05b169078c65
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=425673274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.425673274
Directory	/workspace/39.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/39.usbdev_max_length_out_transaction.3338555504
Short name	T1935
Test name
Test status
Simulation time	194777244 ps
CPU time	0.91 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:17 PM PDT 24
Peak memory	206948 kb
Host	smart-ba24fa88-6cb6-491e-b8b4-f55673ed46fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33385 55504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3338555504
Directory	/workspace/39.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1477190800
Short name	T927
Test name
Test status
Simulation time	1669984292 ps
CPU time	15.33 seconds
Started	Aug 01 06:18:18 PM PDT 24
Finished	Aug 01 06:18:34 PM PDT 24
Peak memory	216656 kb
Host	smart-bed050c2-5a23-4a9f-bf13-72d748345aff
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1477190800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1477190800
Directory	/workspace/39.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/39.usbdev_min_length_in_transaction.3155260557
Short name	T1799
Test name
Test status
Simulation time	158909319 ps
CPU time	0.87 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:17 PM PDT 24
Peak memory	206944 kb
Host	smart-61e3866b-042b-4e44-bec3-9c04e6e8c502
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3155260557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.3155260557
Directory	/workspace/39.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/39.usbdev_min_length_out_transaction.2846580362
Short name	T2744
Test name
Test status
Simulation time	140838923 ps
CPU time	0.82 seconds
Started	Aug 01 06:18:18 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	206928 kb
Host	smart-280b5dfa-c3c6-48b9-8776-5eb898d276bc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28465 80362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2846580362
Directory	/workspace/39.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/39.usbdev_nak_trans.1374813895
Short name	T1931
Test name
Test status
Simulation time	189019338 ps
CPU time	0.91 seconds
Started	Aug 01 06:18:18 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	206920 kb
Host	smart-755e6a1f-9879-4c30-8b2c-1adb30b57621
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13748 13895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1374813895
Directory	/workspace/39.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/39.usbdev_out_iso.2529584147
Short name	T2340
Test name
Test status
Simulation time	256265771 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	206880 kb
Host	smart-71a2d7d7-c113-4003-9404-2ba393cc2fee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25295 84147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2529584147
Directory	/workspace/39.usbdev_out_iso/latest

Test location	/workspace/coverage/default/39.usbdev_out_stall.2475655605
Short name	T1527
Test name
Test status
Simulation time	172742496 ps
CPU time	0.9 seconds
Started	Aug 01 06:18:18 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	206944 kb
Host	smart-a9578457-95e4-42ae-8775-871ca31c73f7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24756 55605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2475655605
Directory	/workspace/39.usbdev_out_stall/latest

Test location	/workspace/coverage/default/39.usbdev_out_trans_nak.88468343
Short name	T745
Test name
Test status
Simulation time	182404906 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:18 PM PDT 24
Peak memory	206928 kb
Host	smart-1f53af77-bd44-4ace-8c65-10444f4cccf1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88468 343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.88468343
Directory	/workspace/39.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/39.usbdev_pending_in_trans.94725895
Short name	T1693
Test name
Test status
Simulation time	147233762 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:16 PM PDT 24
Finished	Aug 01 06:18:17 PM PDT 24
Peak memory	206940 kb
Host	smart-1f1aa504-5ee9-49ba-994f-74f15c4b1cb3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94725 895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.94725895
Directory	/workspace/39.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/39.usbdev_phy_config_pinflip.3060541211
Short name	T2414
Test name
Test status
Simulation time	254460113 ps
CPU time	1.12 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:18:21 PM PDT 24
Peak memory	206904 kb
Host	smart-d776f11c-fd74-49c6-97e6-1fb52a156bdd
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3060541211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3060541211
Directory	/workspace/39.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.623050505
Short name	T2017
Test name
Test status
Simulation time	143079494 ps
CPU time	0.82 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:18:20 PM PDT 24
Peak memory	206944 kb
Host	smart-51c6ad10-d48a-4fbd-8104-9f116b8255d6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62305 0505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.623050505
Directory	/workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/39.usbdev_phy_pins_sense.2855660134
Short name	T2787
Test name
Test status
Simulation time	38588408 ps
CPU time	0.73 seconds
Started	Aug 01 06:18:18 PM PDT 24
Finished	Aug 01 06:18:19 PM PDT 24
Peak memory	206896 kb
Host	smart-9811247b-60bd-4b45-bcce-a15ea2cf568b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28556 60134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2855660134
Directory	/workspace/39.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/39.usbdev_pkt_buffer.1952513474
Short name	T247
Test name
Test status
Simulation time	20015376044 ps
CPU time	49.05 seconds
Started	Aug 01 06:18:20 PM PDT 24
Finished	Aug 01 06:19:09 PM PDT 24
Peak memory	219608 kb
Host	smart-b6841479-6356-4a99-ae29-f4216f0c03d6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19525 13474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1952513474
Directory	/workspace/39.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/39.usbdev_pkt_received.3882964496
Short name	T1516
Test name
Test status
Simulation time	162551091 ps
CPU time	0.99 seconds
Started	Aug 01 06:18:19 PM PDT 24
Finished	Aug 01 06:18:21 PM PDT 24
Peak memory	206944 kb
Host	smart-7835ce1a-c2e1-4c02-b2f2-16edca77e530
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38829 64496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.3882964496
Directory	/workspace/39.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/39.usbdev_pkt_sent.4225280757
Short name	T827
Test name
Test status
Simulation time	229982060 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:45 PM PDT 24
Finished	Aug 01 06:18:46 PM PDT 24
Peak memory	206944 kb
Host	smart-88dc1671-c195-4268-a4fd-9d4eb529c90c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42252 80757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.4225280757
Directory	/workspace/39.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/39.usbdev_random_length_in_transaction.2284029564
Short name	T2878
Test name
Test status
Simulation time	191498097 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:32 PM PDT 24
Finished	Aug 01 06:18:33 PM PDT 24
Peak memory	206852 kb
Host	smart-57adb459-2134-41a4-8077-ec3eba12ccca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22840 29564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.2284029564
Directory	/workspace/39.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/39.usbdev_random_length_out_transaction.3385653010
Short name	T1955
Test name
Test status
Simulation time	153950383 ps
CPU time	0.94 seconds
Started	Aug 01 06:18:32 PM PDT 24
Finished	Aug 01 06:18:33 PM PDT 24
Peak memory	206912 kb
Host	smart-01567091-9448-4eef-842d-e129629047db
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33856 53010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3385653010
Directory	/workspace/39.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/39.usbdev_rx_crc_err.2133053472
Short name	T1101
Test name
Test status
Simulation time	148478263 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:33 PM PDT 24
Finished	Aug 01 06:18:34 PM PDT 24
Peak memory	206912 kb
Host	smart-90b15c3a-0f0b-44b0-a04c-cca4562046c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21330 53472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2133053472
Directory	/workspace/39.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/39.usbdev_rx_full.4163003035
Short name	T2823
Test name
Test status
Simulation time	252635652 ps
CPU time	1.05 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	206948 kb
Host	smart-31e8f68c-7627-45ac-b91b-b10867023ed2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41630 03035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.4163003035
Directory	/workspace/39.usbdev_rx_full/latest

Test location	/workspace/coverage/default/39.usbdev_setup_stage.3413426823
Short name	T1127
Test name
Test status
Simulation time	170687355 ps
CPU time	0.84 seconds
Started	Aug 01 06:18:47 PM PDT 24
Finished	Aug 01 06:18:48 PM PDT 24
Peak memory	206912 kb
Host	smart-2accbe1b-6055-47a9-a16b-5b79ed8a9f3f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34134 26823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3413426823
Directory	/workspace/39.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/39.usbdev_setup_trans_ignored.4060538523
Short name	T1345
Test name
Test status
Simulation time	224537211 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	206000 kb
Host	smart-5c404851-34ce-4ce4-83f7-b6d7c85909b8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40605 38523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.4060538523
Directory	/workspace/39.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/39.usbdev_smoke.4171164911
Short name	T1113
Test name
Test status
Simulation time	227721545 ps
CPU time	1.05 seconds
Started	Aug 01 06:18:30 PM PDT 24
Finished	Aug 01 06:18:31 PM PDT 24
Peak memory	206804 kb
Host	smart-c58aa685-5dca-46c4-a985-1d2edfd7d45a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41711 64911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.4171164911
Directory	/workspace/39.usbdev_smoke/latest

Test location	/workspace/coverage/default/39.usbdev_spurious_pids_ignored.839838902
Short name	T2754
Test name
Test status
Simulation time	2452971291 ps
CPU time	18.24 seconds
Started	Aug 01 06:18:28 PM PDT 24
Finished	Aug 01 06:18:47 PM PDT 24
Peak memory	223552 kb
Host	smart-04df8578-db2b-4ac6-90a0-71ada29bd83f
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=839838902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.839838902
Directory	/workspace/39.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/39.usbdev_stall_priority_over_nak.4200465775
Short name	T2217
Test name
Test status
Simulation time	228452838 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:33 PM PDT 24
Finished	Aug 01 06:18:34 PM PDT 24
Peak memory	206960 kb
Host	smart-7e67c908-4914-45de-ae10-a2211767bce1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42004 65775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.4200465775
Directory	/workspace/39.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/39.usbdev_stall_trans.1392391121
Short name	T1462
Test name
Test status
Simulation time	207270010 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:44 PM PDT 24
Finished	Aug 01 06:18:45 PM PDT 24
Peak memory	206904 kb
Host	smart-85f88415-e0dc-4196-9a74-8606f04c4b90
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13923 91121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1392391121
Directory	/workspace/39.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/39.usbdev_stream_len_max.2159457353
Short name	T1690
Test name
Test status
Simulation time	515019124 ps
CPU time	1.58 seconds
Started	Aug 01 06:18:29 PM PDT 24
Finished	Aug 01 06:18:31 PM PDT 24
Peak memory	207132 kb
Host	smart-b42844d1-c44d-4405-8200-27b3c079cd28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21594 57353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.2159457353
Directory	/workspace/39.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/39.usbdev_streaming_out.2631692105
Short name	T1864
Test name
Test status
Simulation time	2529295287 ps
CPU time	71.72 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:19:43 PM PDT 24
Peak memory	216780 kb
Host	smart-d8220a50-7f40-480c-aa86-010c1e3cce54
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26316 92105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2631692105
Directory	/workspace/39.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.1481226739
Short name	T740
Test name
Test status
Simulation time	738335662 ps
CPU time	15.94 seconds
Started	Aug 01 06:18:17 PM PDT 24
Finished	Aug 01 06:18:34 PM PDT 24
Peak memory	207160 kb
Host	smart-da5c94bd-44eb-4412-8fb6-398005bd00f6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481226739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_hos t_handshake.1481226739
Directory	/workspace/39.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/4.usbdev_alert_test.2832255204
Short name	T1135
Test name
Test status
Simulation time	36167807 ps
CPU time	0.64 seconds
Started	Aug 01 06:12:11 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	207136 kb
Host	smart-a62d5fc4-0d2f-4abf-b81f-341f02c3399b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2832255204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2832255204
Directory	/workspace/4.usbdev_alert_test/latest

Test location	/workspace/coverage/default/4.usbdev_av_buffer.206935005
Short name	T1309
Test name
Test status
Simulation time	185031210 ps
CPU time	0.97 seconds
Started	Aug 01 06:11:35 PM PDT 24
Finished	Aug 01 06:11:36 PM PDT 24
Peak memory	205996 kb
Host	smart-16e20d18-a96a-488a-86e9-4a961ebed05c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20693 5005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.206935005
Directory	/workspace/4.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/4.usbdev_av_empty.3709413590
Short name	T34
Test name
Test status
Simulation time	157081738 ps
CPU time	0.91 seconds
Started	Aug 01 06:11:40 PM PDT 24
Finished	Aug 01 06:11:41 PM PDT 24
Peak memory	206952 kb
Host	smart-626795dc-8c02-41bd-85e8-19d5fe88b85e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37094 13590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3709413590
Directory	/workspace/4.usbdev_av_empty/latest

Test location	/workspace/coverage/default/4.usbdev_av_overflow.1998359378
Short name	T47
Test name
Test status
Simulation time	153660270 ps
CPU time	0.82 seconds
Started	Aug 01 06:11:40 PM PDT 24
Finished	Aug 01 06:11:41 PM PDT 24
Peak memory	206888 kb
Host	smart-321ceb95-eb15-4aae-8bf3-7a7a0361706e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19983 59378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.1998359378
Directory	/workspace/4.usbdev_av_overflow/latest

Test location	/workspace/coverage/default/4.usbdev_bitstuff_err.419867155
Short name	T1086
Test name
Test status
Simulation time	149022022 ps
CPU time	0.89 seconds
Started	Aug 01 06:11:39 PM PDT 24
Finished	Aug 01 06:11:40 PM PDT 24
Peak memory	206920 kb
Host	smart-7d764fe8-1ea3-42b4-9f4d-efed457c03c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41986 7155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.419867155
Directory	/workspace/4.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/4.usbdev_data_toggle_clear.4161799154
Short name	T1848
Test name
Test status
Simulation time	458745268 ps
CPU time	1.51 seconds
Started	Aug 01 06:11:41 PM PDT 24
Finished	Aug 01 06:11:43 PM PDT 24
Peak memory	206928 kb
Host	smart-d0abdb60-6beb-40c3-b5e7-02389bf67e1c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617 99154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.4161799154
Directory	/workspace/4.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/4.usbdev_data_toggle_restore.189142873
Short name	T1190
Test name
Test status
Simulation time	493484126 ps
CPU time	1.5 seconds
Started	Aug 01 06:11:46 PM PDT 24
Finished	Aug 01 06:11:47 PM PDT 24
Peak memory	206980 kb
Host	smart-9499d91e-79c9-4520-aec2-58b007974b04
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=189142873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.189142873
Directory	/workspace/4.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/4.usbdev_device_address.2921835101
Short name	T456
Test name
Test status
Simulation time	40664930779 ps
CPU time	62.4 seconds
Started	Aug 01 06:11:46 PM PDT 24
Finished	Aug 01 06:12:49 PM PDT 24
Peak memory	207184 kb
Host	smart-e2c36589-61f0-4234-8d4b-363326550a5e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29218 35101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2921835101
Directory	/workspace/4.usbdev_device_address/latest

Test location	/workspace/coverage/default/4.usbdev_device_timeout.518803717
Short name	T803
Test name
Test status
Simulation time	948510055 ps
CPU time	20.18 seconds
Started	Aug 01 06:11:47 PM PDT 24
Finished	Aug 01 06:12:07 PM PDT 24
Peak memory	207116 kb
Host	smart-3992e177-0a72-45e5-90c9-9a5d44124799
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518803717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.518803717
Directory	/workspace/4.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/4.usbdev_disable_endpoint.564656234
Short name	T2447
Test name
Test status
Simulation time	995070466 ps
CPU time	2.21 seconds
Started	Aug 01 06:11:46 PM PDT 24
Finished	Aug 01 06:11:49 PM PDT 24
Peak memory	206884 kb
Host	smart-b7a2f390-441b-4c29-8585-c0ef8c51db09
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56465 6234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.564656234
Directory	/workspace/4.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/4.usbdev_disconnected.2916530542
Short name	T1423
Test name
Test status
Simulation time	155584271 ps
CPU time	0.85 seconds
Started	Aug 01 06:11:45 PM PDT 24
Finished	Aug 01 06:11:46 PM PDT 24
Peak memory	206860 kb
Host	smart-cc61f65b-2275-4522-b9ca-7bb3287921d3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29165 30542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2916530542
Directory	/workspace/4.usbdev_disconnected/latest

Test location	/workspace/coverage/default/4.usbdev_enable.3488709463
Short name	T243
Test name
Test status
Simulation time	86483915 ps
CPU time	0.76 seconds
Started	Aug 01 06:11:45 PM PDT 24
Finished	Aug 01 06:11:45 PM PDT 24
Peak memory	206908 kb
Host	smart-f81aead1-7e02-450a-82a6-67519acc8339
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34887 09463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3488709463
Directory	/workspace/4.usbdev_enable/latest

Test location	/workspace/coverage/default/4.usbdev_endpoint_access.4148045244
Short name	T752
Test name
Test status
Simulation time	826113886 ps
CPU time	2.31 seconds
Started	Aug 01 06:11:46 PM PDT 24
Finished	Aug 01 06:11:48 PM PDT 24
Peak memory	207152 kb
Host	smart-3836dfba-367e-41d9-9a2f-5adf83550721
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41480 45244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.4148045244
Directory	/workspace/4.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/4.usbdev_endpoint_types.4265857276
Short name	T2780
Test name
Test status
Simulation time	333886246 ps
CPU time	1.09 seconds
Started	Aug 01 06:11:44 PM PDT 24
Finished	Aug 01 06:11:46 PM PDT 24
Peak memory	206928 kb
Host	smart-8fae610d-5c69-462f-85a1-21589aff884e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4265857276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.4265857276
Directory	/workspace/4.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/4.usbdev_fifo_rst.3774537988
Short name	T1183
Test name
Test status
Simulation time	181438680 ps
CPU time	1.95 seconds
Started	Aug 01 06:11:47 PM PDT 24
Finished	Aug 01 06:11:49 PM PDT 24
Peak memory	207084 kb
Host	smart-edc1210e-ca63-40d0-b4c8-f735f6bebc1a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37745 37988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3774537988
Directory	/workspace/4.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/4.usbdev_freq_hiclk.1083480897
Short name	T467
Test name
Test status
Simulation time	96184585820 ps
CPU time	178.04 seconds
Started	Aug 01 06:11:45 PM PDT 24
Finished	Aug 01 06:14:44 PM PDT 24
Peak memory	207120 kb
Host	smart-053d81b5-6c5e-413b-a98e-0db24bd37fcd
User	root
Command	/workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1083480897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.1083480897
Directory	/workspace/4.usbdev_freq_hiclk/latest

Test location	/workspace/coverage/default/4.usbdev_freq_hiclk_max.667630264
Short name	T2065
Test name
Test status
Simulation time	84268897938 ps
CPU time	146.88 seconds
Started	Aug 01 06:11:52 PM PDT 24
Finished	Aug 01 06:14:20 PM PDT 24
Peak memory	207176 kb
Host	smart-aa9f2a65-d6f9-4bde-ae08-9e49631a33c2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667630264 -assert no postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.667630264
Directory	/workspace/4.usbdev_freq_hiclk_max/latest

Test location	/workspace/coverage/default/4.usbdev_freq_loclk_max.3342609916
Short name	T1984
Test name
Test status
Simulation time	121207997521 ps
CPU time	174.13 seconds
Started	Aug 01 06:11:45 PM PDT 24
Finished	Aug 01 06:14:39 PM PDT 24
Peak memory	207136 kb
Host	smart-57663ef0-03e9-4509-91bc-d5c5b18488dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12 0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342609916 -assert n opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.3342609916
Directory	/workspace/4.usbdev_freq_loclk_max/latest

Test location	/workspace/coverage/default/4.usbdev_freq_phase.2479437222
Short name	T1472
Test name
Test status
Simulation time	116215955035 ps
CPU time	166.56 seconds
Started	Aug 01 06:11:53 PM PDT 24
Finished	Aug 01 06:14:39 PM PDT 24
Peak memory	207188 kb
Host	smart-b3bee373-372c-41a8-a5e7-e5f94f76deb8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24794 37222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.2479437222
Directory	/workspace/4.usbdev_freq_phase/latest

Test location	/workspace/coverage/default/4.usbdev_in_iso.2017631111
Short name	T1496
Test name
Test status
Simulation time	191657769 ps
CPU time	0.95 seconds
Started	Aug 01 06:11:52 PM PDT 24
Finished	Aug 01 06:11:54 PM PDT 24
Peak memory	207008 kb
Host	smart-ce9986cd-4b29-4dac-bd42-e0d71804d595
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2017631111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.2017631111
Directory	/workspace/4.usbdev_in_iso/latest

Test location	/workspace/coverage/default/4.usbdev_in_stall.3085793691
Short name	T1096
Test name
Test status
Simulation time	141358308 ps
CPU time	0.82 seconds
Started	Aug 01 06:11:44 PM PDT 24
Finished	Aug 01 06:11:45 PM PDT 24
Peak memory	206904 kb
Host	smart-b5284b26-73aa-4f38-bee5-1eb92c076008
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857 93691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3085793691
Directory	/workspace/4.usbdev_in_stall/latest

Test location	/workspace/coverage/default/4.usbdev_in_trans.66193880
Short name	T1308
Test name
Test status
Simulation time	179337848 ps
CPU time	0.89 seconds
Started	Aug 01 06:11:44 PM PDT 24
Finished	Aug 01 06:11:45 PM PDT 24
Peak memory	206940 kb
Host	smart-ce9105cf-e1c0-497f-a023-a57a977faa5b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66193 880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.66193880
Directory	/workspace/4.usbdev_in_trans/latest

Test location	/workspace/coverage/default/4.usbdev_invalid_sync.4088607941
Short name	T731
Test name
Test status
Simulation time	2926589385 ps
CPU time	80.67 seconds
Started	Aug 01 06:11:45 PM PDT 24
Finished	Aug 01 06:13:06 PM PDT 24
Peak memory	223188 kb
Host	smart-f4426cb2-1f06-490b-addd-aef17ad29e9b
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=4088607941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.4088607941
Directory	/workspace/4.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/4.usbdev_iso_retraction.2827086260
Short name	T863
Test name
Test status
Simulation time	12448958587 ps
CPU time	91.55 seconds
Started	Aug 01 06:11:49 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	207132 kb
Host	smart-191cadbf-b6f0-4bae-a5b1-fb35636e958f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2827086260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.2827086260
Directory	/workspace/4.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/4.usbdev_link_in_err.3077038263
Short name	T1913
Test name
Test status
Simulation time	198524617 ps
CPU time	1.01 seconds
Started	Aug 01 06:11:45 PM PDT 24
Finished	Aug 01 06:11:47 PM PDT 24
Peak memory	206932 kb
Host	smart-86dc2363-3521-4b33-9c3d-85c043f37407
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30770 38263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.3077038263
Directory	/workspace/4.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/4.usbdev_link_suspend.630904013
Short name	T1980
Test name
Test status
Simulation time	9799974928 ps
CPU time	12.01 seconds
Started	Aug 01 06:11:45 PM PDT 24
Finished	Aug 01 06:11:58 PM PDT 24
Peak memory	207136 kb
Host	smart-2e05fe7b-c3d5-47f4-b883-a938a734bdc8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63090 4013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.630904013
Directory	/workspace/4.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/4.usbdev_low_speed_traffic.3132747054
Short name	T1391
Test name
Test status
Simulation time	4673010328 ps
CPU time	129.51 seconds
Started	Aug 01 06:11:45 PM PDT 24
Finished	Aug 01 06:13:54 PM PDT 24
Peak memory	217784 kb
Host	smart-fd4fa3f5-f4c4-4c36-ac53-69c438728758
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31327 47054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3132747054
Directory	/workspace/4.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/4.usbdev_max_inter_pkt_delay.1137400722
Short name	T1206
Test name
Test status
Simulation time	3163519895 ps
CPU time	92.06 seconds
Started	Aug 01 06:11:46 PM PDT 24
Finished	Aug 01 06:13:18 PM PDT 24
Peak memory	216848 kb
Host	smart-8ac56cfa-74ec-47a3-90d2-b3aae811ca9a
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1137400722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.1137400722
Directory	/workspace/4.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/4.usbdev_max_length_in_transaction.3119412349
Short name	T2250
Test name
Test status
Simulation time	248182434 ps
CPU time	1.04 seconds
Started	Aug 01 06:11:45 PM PDT 24
Finished	Aug 01 06:11:46 PM PDT 24
Peak memory	206924 kb
Host	smart-d4259727-34a4-4a8c-8c91-493515d56d63
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3119412349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3119412349
Directory	/workspace/4.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/4.usbdev_max_length_out_transaction.903799865
Short name	T2629
Test name
Test status
Simulation time	189401693 ps
CPU time	0.91 seconds
Started	Aug 01 06:11:47 PM PDT 24
Finished	Aug 01 06:11:48 PM PDT 24
Peak memory	206924 kb
Host	smart-173d8967-4cc9-438f-8e6f-5307e14012f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90379 9865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.903799865
Directory	/workspace/4.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.2660846349
Short name	T206
Test name
Test status
Simulation time	1967680596 ps
CPU time	55.93 seconds
Started	Aug 01 06:11:46 PM PDT 24
Finished	Aug 01 06:12:42 PM PDT 24
Peak memory	216852 kb
Host	smart-12073df7-4210-4be0-8272-666cefc8c957
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26608 46349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.2660846349
Directory	/workspace/4.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/4.usbdev_max_usb_traffic.3278964317
Short name	T2476
Test name
Test status
Simulation time	2118594511 ps
CPU time	17.07 seconds
Started	Aug 01 06:11:48 PM PDT 24
Finished	Aug 01 06:12:06 PM PDT 24
Peak memory	223488 kb
Host	smart-6edf602f-0491-448a-8cae-026daebd54db
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3278964317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3278964317
Directory	/workspace/4.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/4.usbdev_min_inter_pkt_delay.1657495501
Short name	T908
Test name
Test status
Simulation time	2623744828 ps
CPU time	19.93 seconds
Started	Aug 01 06:11:52 PM PDT 24
Finished	Aug 01 06:12:12 PM PDT 24
Peak memory	217168 kb
Host	smart-bda671ba-b3cd-4e85-833c-f3ffacbdebc8
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1657495501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.1657495501
Directory	/workspace/4.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/4.usbdev_min_length_in_transaction.261318772
Short name	T572
Test name
Test status
Simulation time	164906282 ps
CPU time	0.89 seconds
Started	Aug 01 06:11:48 PM PDT 24
Finished	Aug 01 06:11:49 PM PDT 24
Peak memory	206888 kb
Host	smart-90d6f647-7974-4e7a-b95b-02ec61fca37e
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=261318772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.261318772
Directory	/workspace/4.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/4.usbdev_min_length_out_transaction.1540378557
Short name	T2210
Test name
Test status
Simulation time	169838380 ps
CPU time	0.86 seconds
Started	Aug 01 06:11:48 PM PDT 24
Finished	Aug 01 06:11:49 PM PDT 24
Peak memory	206972 kb
Host	smart-d2e74572-fc63-421e-82e3-d9906613f671
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15403 78557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1540378557
Directory	/workspace/4.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/4.usbdev_nak_trans.2889394612
Short name	T167
Test name
Test status
Simulation time	230211027 ps
CPU time	0.99 seconds
Started	Aug 01 06:11:54 PM PDT 24
Finished	Aug 01 06:11:55 PM PDT 24
Peak memory	206952 kb
Host	smart-16ad262b-cd67-430e-b1dc-6703ff37ec74
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893 94612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2889394612
Directory	/workspace/4.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/4.usbdev_out_iso.1289912733
Short name	T531
Test name
Test status
Simulation time	182071348 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:01 PM PDT 24
Finished	Aug 01 06:12:02 PM PDT 24
Peak memory	206924 kb
Host	smart-093d3753-30b2-49a6-b360-a419625fd6a1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12899 12733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.1289912733
Directory	/workspace/4.usbdev_out_iso/latest

Test location	/workspace/coverage/default/4.usbdev_out_stall.2680621572
Short name	T999
Test name
Test status
Simulation time	144570700 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:02 PM PDT 24
Finished	Aug 01 06:12:03 PM PDT 24
Peak memory	206968 kb
Host	smart-c1b83803-943c-48c2-8501-074b070e280e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26806 21572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2680621572
Directory	/workspace/4.usbdev_out_stall/latest

Test location	/workspace/coverage/default/4.usbdev_out_trans_nak.3015960658
Short name	T1953
Test name
Test status
Simulation time	152163872 ps
CPU time	0.84 seconds
Started	Aug 01 06:11:58 PM PDT 24
Finished	Aug 01 06:11:59 PM PDT 24
Peak memory	206952 kb
Host	smart-ec001704-8741-4fcd-badf-14275b7e97f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30159 60658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.3015960658
Directory	/workspace/4.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/4.usbdev_pending_in_trans.2763264464
Short name	T1961
Test name
Test status
Simulation time	154879244 ps
CPU time	0.87 seconds
Started	Aug 01 06:12:02 PM PDT 24
Finished	Aug 01 06:12:04 PM PDT 24
Peak memory	206868 kb
Host	smart-c10bd711-31f8-4f4d-b175-19a76410a31d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27632 64464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2763264464
Directory	/workspace/4.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/4.usbdev_phy_config_pinflip.2712036837
Short name	T1131
Test name
Test status
Simulation time	261020394 ps
CPU time	1.06 seconds
Started	Aug 01 06:11:57 PM PDT 24
Finished	Aug 01 06:11:59 PM PDT 24
Peak memory	206952 kb
Host	smart-a6cd7a77-8ebb-46cd-9dab-bedeaa58b0b7
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2712036837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2712036837
Directory	/workspace/4.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3458121333
Short name	T131
Test name
Test status
Simulation time	226418494 ps
CPU time	0.99 seconds
Started	Aug 01 06:11:57 PM PDT 24
Finished	Aug 01 06:11:58 PM PDT 24
Peak memory	206884 kb
Host	smart-e0977fb6-5f82-44d9-98dc-3a005402906b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34581 21333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3458121333
Directory	/workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location	/workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3002446418
Short name	T2284
Test name
Test status
Simulation time	188939729 ps
CPU time	0.87 seconds
Started	Aug 01 06:12:02 PM PDT 24
Finished	Aug 01 06:12:03 PM PDT 24
Peak memory	206944 kb
Host	smart-3ffcc9c0-bee3-4e4f-803e-6fc85971175a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30024 46418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3002446418
Directory	/workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/4.usbdev_phy_pins_sense.2278242495
Short name	T25
Test name
Test status
Simulation time	39043464 ps
CPU time	0.71 seconds
Started	Aug 01 06:12:03 PM PDT 24
Finished	Aug 01 06:12:04 PM PDT 24
Peak memory	206892 kb
Host	smart-374e625f-8e9a-489e-bbd0-dc6663666eb3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22782 42495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2278242495
Directory	/workspace/4.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/4.usbdev_pkt_buffer.3467493013
Short name	T1518
Test name
Test status
Simulation time	7940779744 ps
CPU time	19.45 seconds
Started	Aug 01 06:11:58 PM PDT 24
Finished	Aug 01 06:12:18 PM PDT 24
Peak memory	215388 kb
Host	smart-fd24453f-fe85-42d9-9918-f180f1cb82dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34674 93013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3467493013
Directory	/workspace/4.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/4.usbdev_pkt_received.1872571424
Short name	T1182
Test name
Test status
Simulation time	154727057 ps
CPU time	0.91 seconds
Started	Aug 01 06:11:57 PM PDT 24
Finished	Aug 01 06:11:58 PM PDT 24
Peak memory	206952 kb
Host	smart-277d4036-aaba-4b3e-9af7-2fc822a20bd0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18725 71424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1872571424
Directory	/workspace/4.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/4.usbdev_pkt_sent.3221919881
Short name	T2281
Test name
Test status
Simulation time	194705475 ps
CPU time	0.91 seconds
Started	Aug 01 06:11:59 PM PDT 24
Finished	Aug 01 06:12:00 PM PDT 24
Peak memory	206948 kb
Host	smart-20e49f77-429f-42e3-bb70-45271489850e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32219 19881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.3221919881
Directory	/workspace/4.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/4.usbdev_rand_bus_resets.2465554161
Short name	T2845
Test name
Test status
Simulation time	6668520097 ps
CPU time	103.74 seconds
Started	Aug 01 06:11:58 PM PDT 24
Finished	Aug 01 06:13:42 PM PDT 24
Peak memory	218380 kb
Host	smart-b234c524-c7be-488f-b9b7-936d2b4fe115
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465554161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2465554161
Directory	/workspace/4.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/4.usbdev_rand_suspends.2242235583
Short name	T947
Test name
Test status
Simulation time	17706470517 ps
CPU time	428.98 seconds
Started	Aug 01 06:11:59 PM PDT 24
Finished	Aug 01 06:19:09 PM PDT 24
Peak memory	215212 kb
Host	smart-50fb97bf-ea46-4203-b0d4-41aafe879c3b
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242235583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2242235583
Directory	/workspace/4.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/4.usbdev_random_length_in_transaction.1687874109
Short name	T2241
Test name
Test status
Simulation time	228742904 ps
CPU time	0.99 seconds
Started	Aug 01 06:12:04 PM PDT 24
Finished	Aug 01 06:12:05 PM PDT 24
Peak memory	206940 kb
Host	smart-a831459b-07aa-4c97-b2db-d5f94b3a6287
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16878 74109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.1687874109
Directory	/workspace/4.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/4.usbdev_random_length_out_transaction.773911369
Short name	T2278
Test name
Test status
Simulation time	221362965 ps
CPU time	0.92 seconds
Started	Aug 01 06:12:01 PM PDT 24
Finished	Aug 01 06:12:02 PM PDT 24
Peak memory	206924 kb
Host	smart-2e07a642-8714-4534-b52a-1b28d0aafc4d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77391 1369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.773911369
Directory	/workspace/4.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/4.usbdev_rx_full.859716733
Short name	T1103
Test name
Test status
Simulation time	376578961 ps
CPU time	1.28 seconds
Started	Aug 01 06:11:56 PM PDT 24
Finished	Aug 01 06:11:57 PM PDT 24
Peak memory	206956 kb
Host	smart-d3cd864a-4bc3-4149-aaf3-3eecad12f2d9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85971 6733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.859716733
Directory	/workspace/4.usbdev_rx_full/latest

Test location	/workspace/coverage/default/4.usbdev_rx_pid_err.8759126
Short name	T2436
Test name
Test status
Simulation time	191891913 ps
CPU time	0.97 seconds
Started	Aug 01 06:11:59 PM PDT 24
Finished	Aug 01 06:12:00 PM PDT 24
Peak memory	206960 kb
Host	smart-a52ea763-d3e2-4917-b3bc-ed896918307d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87591 26 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.8759126
Directory	/workspace/4.usbdev_rx_pid_err/latest

Test location	/workspace/coverage/default/4.usbdev_sec_cm.2861395059
Short name	T138
Test name
Test status
Simulation time	889732225 ps
CPU time	1.67 seconds
Started	Aug 01 06:12:11 PM PDT 24
Finished	Aug 01 06:12:12 PM PDT 24
Peak memory	223884 kb
Host	smart-ef563866-4fb5-4a1a-96f6-52d570c9fe37
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2861395059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2861395059
Directory	/workspace/4.usbdev_sec_cm/latest

Test location	/workspace/coverage/default/4.usbdev_setup_priority.2041908765
Short name	T2180
Test name
Test status
Simulation time	343509747 ps
CPU time	1.25 seconds
Started	Aug 01 06:11:59 PM PDT 24
Finished	Aug 01 06:12:01 PM PDT 24
Peak memory	206928 kb
Host	smart-ddaaccc8-2428-45d2-91de-94a9fc5b2d77
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20419 08765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2041908765
Directory	/workspace/4.usbdev_setup_priority/latest

Test location	/workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3928585402
Short name	T1692
Test name
Test status
Simulation time	337292658 ps
CPU time	1.19 seconds
Started	Aug 01 06:12:00 PM PDT 24
Finished	Aug 01 06:12:01 PM PDT 24
Peak memory	206936 kb
Host	smart-10a39558-e394-423e-ad1f-143f6e2d0aba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39285 85402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3928585402
Directory	/workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location	/workspace/coverage/default/4.usbdev_setup_stage.4106827549
Short name	T479
Test name
Test status
Simulation time	196049273 ps
CPU time	0.88 seconds
Started	Aug 01 06:12:04 PM PDT 24
Finished	Aug 01 06:12:05 PM PDT 24
Peak memory	206936 kb
Host	smart-b0278cd4-c72c-4dbd-92ec-a310261b5a1d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41068 27549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.4106827549
Directory	/workspace/4.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/4.usbdev_setup_trans_ignored.1099775486
Short name	T2029
Test name
Test status
Simulation time	147808345 ps
CPU time	0.84 seconds
Started	Aug 01 06:12:00 PM PDT 24
Finished	Aug 01 06:12:01 PM PDT 24
Peak memory	206948 kb
Host	smart-9e92e872-ae7c-4423-8b13-b9d5548e1ec0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10997 75486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.1099775486
Directory	/workspace/4.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/4.usbdev_smoke.1330789024
Short name	T935
Test name
Test status
Simulation time	254106775 ps
CPU time	1.07 seconds
Started	Aug 01 06:12:01 PM PDT 24
Finished	Aug 01 06:12:02 PM PDT 24
Peak memory	206924 kb
Host	smart-4f39ee29-164c-46d7-950c-00231af33e08
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13307 89024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1330789024
Directory	/workspace/4.usbdev_smoke/latest

Test location	/workspace/coverage/default/4.usbdev_spurious_pids_ignored.3071620137
Short name	T1877
Test name
Test status
Simulation time	2117134887 ps
CPU time	59.29 seconds
Started	Aug 01 06:11:56 PM PDT 24
Finished	Aug 01 06:12:56 PM PDT 24
Peak memory	215320 kb
Host	smart-61cad87f-7344-45d1-bfa2-27fd2c7c0d27
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3071620137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3071620137
Directory	/workspace/4.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/4.usbdev_stall_priority_over_nak.1051951282
Short name	T2309
Test name
Test status
Simulation time	179621563 ps
CPU time	0.97 seconds
Started	Aug 01 06:12:01 PM PDT 24
Finished	Aug 01 06:12:02 PM PDT 24
Peak memory	206908 kb
Host	smart-683c4cba-3a3c-4321-8812-44c936b06f37
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10519 51282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1051951282
Directory	/workspace/4.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/4.usbdev_stall_trans.365692183
Short name	T1348
Test name
Test status
Simulation time	221674310 ps
CPU time	0.92 seconds
Started	Aug 01 06:11:57 PM PDT 24
Finished	Aug 01 06:11:58 PM PDT 24
Peak memory	206932 kb
Host	smart-c72f1437-3543-4085-bdbd-5f3fbd56570c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36569 2183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.365692183
Directory	/workspace/4.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/4.usbdev_stream_len_max.3899249716
Short name	T2451
Test name
Test status
Simulation time	990926119 ps
CPU time	2.81 seconds
Started	Aug 01 06:12:02 PM PDT 24
Finished	Aug 01 06:12:06 PM PDT 24
Peak memory	207008 kb
Host	smart-a49f429f-3af1-48f0-ac33-0ea06f2631b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38992 49716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.3899249716
Directory	/workspace/4.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/4.usbdev_streaming_out.207503944
Short name	T2127
Test name
Test status
Simulation time	1702119704 ps
CPU time	14.26 seconds
Started	Aug 01 06:11:57 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	223412 kb
Host	smart-0a1f5371-70a8-41f9-aeae-82806a1bd468
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20750 3944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.207503944
Directory	/workspace/4.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.3279998389
Short name	T499
Test name
Test status
Simulation time	1434090838 ps
CPU time	32.92 seconds
Started	Aug 01 06:11:47 PM PDT 24
Finished	Aug 01 06:12:20 PM PDT 24
Peak memory	207156 kb
Host	smart-199ab0ae-30cf-4128-ab57-dcfd6381f21e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279998389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host _handshake.3279998389
Directory	/workspace/4.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/40.usbdev_alert_test.3259209926
Short name	T2380
Test name
Test status
Simulation time	47413253 ps
CPU time	0.67 seconds
Started	Aug 01 06:18:47 PM PDT 24
Finished	Aug 01 06:18:48 PM PDT 24
Peak memory	206996 kb
Host	smart-844f5bf9-6dae-4b7b-9745-32042f738d10
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3259209926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3259209926
Directory	/workspace/40.usbdev_alert_test/latest

Test location	/workspace/coverage/default/40.usbdev_av_buffer.197709362
Short name	T15
Test name
Test status
Simulation time	174219811 ps
CPU time	0.87 seconds
Started	Aug 01 06:18:32 PM PDT 24
Finished	Aug 01 06:18:33 PM PDT 24
Peak memory	206900 kb
Host	smart-bdca1174-1f29-4a03-909a-12d0625d3eed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19770 9362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.197709362
Directory	/workspace/40.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/40.usbdev_bitstuff_err.1236252706
Short name	T816
Test name
Test status
Simulation time	150891502 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:30 PM PDT 24
Finished	Aug 01 06:18:31 PM PDT 24
Peak memory	206916 kb
Host	smart-0b771c74-dc2e-4d09-8634-3dcf6fbca506
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12362 52706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.1236252706
Directory	/workspace/40.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/40.usbdev_data_toggle_clear.771670040
Short name	T1295
Test name
Test status
Simulation time	679624876 ps
CPU time	2.01 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:38 PM PDT 24
Peak memory	206160 kb
Host	smart-623b6986-5f1a-4b1c-94ac-8f72e4e4a0b3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77167 0040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.771670040
Directory	/workspace/40.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/40.usbdev_data_toggle_restore.1109774116
Short name	T630
Test name
Test status
Simulation time	814979515 ps
CPU time	2.35 seconds
Started	Aug 01 06:18:32 PM PDT 24
Finished	Aug 01 06:18:34 PM PDT 24
Peak memory	207148 kb
Host	smart-092ab105-23a0-4858-aad0-82c20ed6a649
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1109774116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.1109774116
Directory	/workspace/40.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/40.usbdev_device_address.1172289245
Short name	T1706
Test name
Test status
Simulation time	46943228261 ps
CPU time	65.6 seconds
Started	Aug 01 06:18:45 PM PDT 24
Finished	Aug 01 06:19:51 PM PDT 24
Peak memory	207140 kb
Host	smart-c6243fb5-820d-4048-8e55-d02b9aaadacf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722 89245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1172289245
Directory	/workspace/40.usbdev_device_address/latest

Test location	/workspace/coverage/default/40.usbdev_device_timeout.4134581772
Short name	T2269
Test name
Test status
Simulation time	1551490122 ps
CPU time	13.82 seconds
Started	Aug 01 06:18:33 PM PDT 24
Finished	Aug 01 06:18:47 PM PDT 24
Peak memory	207184 kb
Host	smart-c23dd097-4897-4e2d-a0ba-7b901bc4fbec
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134581772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.4134581772
Directory	/workspace/40.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/40.usbdev_disable_endpoint.1436741700
Short name	T1570
Test name
Test status
Simulation time	889434713 ps
CPU time	1.88 seconds
Started	Aug 01 06:18:35 PM PDT 24
Finished	Aug 01 06:18:37 PM PDT 24
Peak memory	206936 kb
Host	smart-d03baddb-01fc-4131-b007-1c2a789f344c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14367 41700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1436741700
Directory	/workspace/40.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/40.usbdev_disconnected.988672491
Short name	T1210
Test name
Test status
Simulation time	155819987 ps
CPU time	0.83 seconds
Started	Aug 01 06:18:29 PM PDT 24
Finished	Aug 01 06:18:30 PM PDT 24
Peak memory	206884 kb
Host	smart-4094c390-d721-486f-a2b7-6a70dccffe8a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98867 2491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.988672491
Directory	/workspace/40.usbdev_disconnected/latest

Test location	/workspace/coverage/default/40.usbdev_enable.3122736879
Short name	T541
Test name
Test status
Simulation time	62425884 ps
CPU time	0.73 seconds
Started	Aug 01 06:18:28 PM PDT 24
Finished	Aug 01 06:18:29 PM PDT 24
Peak memory	206892 kb
Host	smart-70e5e6bd-84a6-49e0-b302-aaebe3449290
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31227 36879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3122736879
Directory	/workspace/40.usbdev_enable/latest

Test location	/workspace/coverage/default/40.usbdev_endpoint_access.2913634705
Short name	T2416
Test name
Test status
Simulation time	817997876 ps
CPU time	2.53 seconds
Started	Aug 01 06:18:34 PM PDT 24
Finished	Aug 01 06:18:37 PM PDT 24
Peak memory	207228 kb
Host	smart-161d63d0-b5e2-409b-8125-7ed4c2cf28b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29136 34705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2913634705
Directory	/workspace/40.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/40.usbdev_endpoint_types.4067627076
Short name	T342
Test name
Test status
Simulation time	649551496 ps
CPU time	1.71 seconds
Started	Aug 01 06:18:32 PM PDT 24
Finished	Aug 01 06:18:34 PM PDT 24
Peak memory	206928 kb
Host	smart-e81c8d05-519f-4d2b-8b08-f1cb86e37a0d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4067627076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.4067627076
Directory	/workspace/40.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/40.usbdev_fifo_rst.3157031802
Short name	T2324
Test name
Test status
Simulation time	159344015 ps
CPU time	1.61 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:33 PM PDT 24
Peak memory	207068 kb
Host	smart-6ef24195-765d-42e9-b569-7873481aa04f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31570 31802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3157031802
Directory	/workspace/40.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/40.usbdev_in_iso.2847608329
Short name	T2365
Test name
Test status
Simulation time	153307584 ps
CPU time	0.84 seconds
Started	Aug 01 06:18:30 PM PDT 24
Finished	Aug 01 06:18:31 PM PDT 24
Peak memory	206004 kb
Host	smart-47f1994b-818e-4ba4-ae97-19d473731cbe
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2847608329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.2847608329
Directory	/workspace/40.usbdev_in_iso/latest

Test location	/workspace/coverage/default/40.usbdev_in_stall.4212172996
Short name	T1122
Test name
Test status
Simulation time	142532079 ps
CPU time	0.83 seconds
Started	Aug 01 06:18:32 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	206868 kb
Host	smart-70992c61-9658-498d-8d38-bba5e7824b4a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42121 72996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.4212172996
Directory	/workspace/40.usbdev_in_stall/latest

Test location	/workspace/coverage/default/40.usbdev_in_trans.1783906381
Short name	T2125
Test name
Test status
Simulation time	238848661 ps
CPU time	1.07 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	206900 kb
Host	smart-50285a8a-d143-4dea-9318-e0dca4e57686
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17839 06381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1783906381
Directory	/workspace/40.usbdev_in_trans/latest

Test location	/workspace/coverage/default/40.usbdev_invalid_sync.1658422881
Short name	T1004
Test name
Test status
Simulation time	4638679327 ps
CPU time	45.21 seconds
Started	Aug 01 06:18:30 PM PDT 24
Finished	Aug 01 06:19:15 PM PDT 24
Peak memory	223524 kb
Host	smart-1101edb7-2bd1-4e4c-ab78-f797dfba0dc2
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1658422881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.1658422881
Directory	/workspace/40.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/40.usbdev_iso_retraction.514639309
Short name	T838
Test name
Test status
Simulation time	5298234905 ps
CPU time	32.98 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:19:04 PM PDT 24
Peak memory	207132 kb
Host	smart-b060ca3a-d0a8-45b2-b0b2-2e33def82b05
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=514639309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.514639309
Directory	/workspace/40.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/40.usbdev_link_in_err.469667555
Short name	T1540
Test name
Test status
Simulation time	212998871 ps
CPU time	0.99 seconds
Started	Aug 01 06:18:30 PM PDT 24
Finished	Aug 01 06:18:31 PM PDT 24
Peak memory	206920 kb
Host	smart-fd058ef1-1955-47c7-b7b1-a6eeee0bfe39
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46966 7555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.469667555
Directory	/workspace/40.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/40.usbdev_link_suspend.135236184
Short name	T1498
Test name
Test status
Simulation time	10046290077 ps
CPU time	14.74 seconds
Started	Aug 01 06:18:27 PM PDT 24
Finished	Aug 01 06:18:42 PM PDT 24
Peak memory	207160 kb
Host	smart-31ec92ba-d7a9-4206-b2a7-09b0f7d1d788
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13523 6184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.135236184
Directory	/workspace/40.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/40.usbdev_low_speed_traffic.3974485604
Short name	T2872
Test name
Test status
Simulation time	4437560183 ps
CPU time	35.46 seconds
Started	Aug 01 06:18:32 PM PDT 24
Finished	Aug 01 06:19:08 PM PDT 24
Peak memory	217744 kb
Host	smart-029300c3-b249-44ff-a8ac-2b51169f2386
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39744 85604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.3974485604
Directory	/workspace/40.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/40.usbdev_max_inter_pkt_delay.939030464
Short name	T912
Test name
Test status
Simulation time	3629814419 ps
CPU time	26.4 seconds
Started	Aug 01 06:18:40 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	215344 kb
Host	smart-cbd67969-a5e4-49bc-a5e8-3a8168ae7bbe
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=939030464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.939030464
Directory	/workspace/40.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/40.usbdev_max_length_in_transaction.3406110927
Short name	T476
Test name
Test status
Simulation time	231810631 ps
CPU time	0.97 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	206968 kb
Host	smart-f1967e49-b33b-4358-98ad-5e50ae35b7f3
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3406110927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3406110927
Directory	/workspace/40.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/40.usbdev_max_length_out_transaction.1850355573
Short name	T691
Test name
Test status
Simulation time	194038797 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:39 PM PDT 24
Finished	Aug 01 06:18:40 PM PDT 24
Peak memory	206952 kb
Host	smart-b2654ce6-1297-44e0-bbd8-aa67e5f67015
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18503 55573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1850355573
Directory	/workspace/40.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/40.usbdev_min_inter_pkt_delay.3120567203
Short name	T1492
Test name
Test status
Simulation time	2110098726 ps
CPU time	19.36 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:19:09 PM PDT 24
Peak memory	215888 kb
Host	smart-09cd111c-de1c-4ef3-8476-e15dd2778281
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3120567203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.3120567203
Directory	/workspace/40.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/40.usbdev_min_length_in_transaction.2015946311
Short name	T488
Test name
Test status
Simulation time	174423190 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:30 PM PDT 24
Finished	Aug 01 06:18:31 PM PDT 24
Peak memory	206884 kb
Host	smart-8fe9c784-80ef-4dc6-be98-db67152737e7
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2015946311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2015946311
Directory	/workspace/40.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/40.usbdev_min_length_out_transaction.977268919
Short name	T649
Test name
Test status
Simulation time	160808600 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:39 PM PDT 24
Finished	Aug 01 06:18:40 PM PDT 24
Peak memory	206952 kb
Host	smart-2f83eff2-6da9-45ed-86d9-f1e3c230a38d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97726 8919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.977268919
Directory	/workspace/40.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/40.usbdev_nak_trans.3546933676
Short name	T1463
Test name
Test status
Simulation time	202809327 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206948 kb
Host	smart-8a838f66-bfad-4f65-ad1e-31353b8532ed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35469 33676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3546933676
Directory	/workspace/40.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/40.usbdev_out_iso.773320645
Short name	T2529
Test name
Test status
Simulation time	172114655 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	207008 kb
Host	smart-f237c0d5-5905-4657-911e-626d2a96813f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77332 0645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.773320645
Directory	/workspace/40.usbdev_out_iso/latest

Test location	/workspace/coverage/default/40.usbdev_out_stall.3822722099
Short name	T693
Test name
Test status
Simulation time	199869839 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:43 PM PDT 24
Finished	Aug 01 06:18:44 PM PDT 24
Peak memory	206948 kb
Host	smart-4684d775-a249-4d94-9f17-34db9c4ef602
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227 22099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3822722099
Directory	/workspace/40.usbdev_out_stall/latest

Test location	/workspace/coverage/default/40.usbdev_out_trans_nak.2055692635
Short name	T2402
Test name
Test status
Simulation time	162153240 ps
CPU time	0.82 seconds
Started	Aug 01 06:18:39 PM PDT 24
Finished	Aug 01 06:18:40 PM PDT 24
Peak memory	206916 kb
Host	smart-9d1fcca5-38b4-4a80-964a-fcfebf5a51af
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20556 92635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2055692635
Directory	/workspace/40.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/40.usbdev_pending_in_trans.1205459946
Short name	T1583
Test name
Test status
Simulation time	158413182 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:48 PM PDT 24
Finished	Aug 01 06:18:49 PM PDT 24
Peak memory	206956 kb
Host	smart-9c9591e7-3810-4ab3-bb5a-a170a8daa81f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12054 59946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1205459946
Directory	/workspace/40.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/40.usbdev_phy_config_pinflip.3208556443
Short name	T113
Test name
Test status
Simulation time	243198162 ps
CPU time	1.13 seconds
Started	Aug 01 06:18:33 PM PDT 24
Finished	Aug 01 06:18:34 PM PDT 24
Peak memory	206912 kb
Host	smart-b1c57ca4-3dfa-4621-a4bc-d93632607f36
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3208556443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3208556443
Directory	/workspace/40.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3678872730
Short name	T1781
Test name
Test status
Simulation time	206446688 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	206932 kb
Host	smart-ed292d11-5d65-4273-81c5-b1443601f28d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36788 72730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3678872730
Directory	/workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/40.usbdev_phy_pins_sense.3970542009
Short name	T2406
Test name
Test status
Simulation time	40258950 ps
CPU time	0.69 seconds
Started	Aug 01 06:18:39 PM PDT 24
Finished	Aug 01 06:18:40 PM PDT 24
Peak memory	206928 kb
Host	smart-6d559e81-4dfc-49a6-9da0-56eea662162c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39705 42009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3970542009
Directory	/workspace/40.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/40.usbdev_pkt_buffer.2072256207
Short name	T2350
Test name
Test status
Simulation time	6423937187 ps
CPU time	16.36 seconds
Started	Aug 01 06:18:34 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	215360 kb
Host	smart-b5a34399-3357-49be-8296-f3bc5f77c82d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20722 56207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2072256207
Directory	/workspace/40.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/40.usbdev_pkt_received.2894779257
Short name	T679
Test name
Test status
Simulation time	173444332 ps
CPU time	0.95 seconds
Started	Aug 01 06:18:31 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	206936 kb
Host	smart-bcdd1ea0-4583-475e-b834-420b399d7aad
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28947 79257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2894779257
Directory	/workspace/40.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/40.usbdev_pkt_sent.1288680104
Short name	T2135
Test name
Test status
Simulation time	224360132 ps
CPU time	0.93 seconds
Started	Aug 01 06:18:34 PM PDT 24
Finished	Aug 01 06:18:35 PM PDT 24
Peak memory	206940 kb
Host	smart-5ec8a973-2340-4800-8484-61386bd638ed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12886 80104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1288680104
Directory	/workspace/40.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/40.usbdev_random_length_in_transaction.3557290499
Short name	T2169
Test name
Test status
Simulation time	228566842 ps
CPU time	0.97 seconds
Started	Aug 01 06:18:30 PM PDT 24
Finished	Aug 01 06:18:32 PM PDT 24
Peak memory	206956 kb
Host	smart-1f9cd603-4c0c-436e-9fb3-8ff357d3191c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35572 90499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.3557290499
Directory	/workspace/40.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/40.usbdev_random_length_out_transaction.1263545901
Short name	T2776
Test name
Test status
Simulation time	161928245 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:44 PM PDT 24
Finished	Aug 01 06:18:45 PM PDT 24
Peak memory	206948 kb
Host	smart-dc53753d-df32-49b1-bffe-b27be7b6097e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12635 45901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1263545901
Directory	/workspace/40.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/40.usbdev_rx_crc_err.286771729
Short name	T2667
Test name
Test status
Simulation time	140593933 ps
CPU time	0.84 seconds
Started	Aug 01 06:18:42 PM PDT 24
Finished	Aug 01 06:18:43 PM PDT 24
Peak memory	206932 kb
Host	smart-3cce9f8b-83be-4c2f-878d-cc0e7c5b6361
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28677 1729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.286771729
Directory	/workspace/40.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/40.usbdev_rx_full.813593804
Short name	T281
Test name
Test status
Simulation time	326769808 ps
CPU time	1.31 seconds
Started	Aug 01 06:18:33 PM PDT 24
Finished	Aug 01 06:18:35 PM PDT 24
Peak memory	206896 kb
Host	smart-c19d16ee-4d00-4fc4-80c0-176dc6fb447f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81359 3804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.813593804
Directory	/workspace/40.usbdev_rx_full/latest

Test location	/workspace/coverage/default/40.usbdev_setup_stage.837679666
Short name	T524
Test name
Test status
Simulation time	227907857 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:44 PM PDT 24
Finished	Aug 01 06:18:46 PM PDT 24
Peak memory	206916 kb
Host	smart-89917a27-e3ef-4107-b2c3-853988ca9007
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83767 9666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.837679666
Directory	/workspace/40.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/40.usbdev_setup_trans_ignored.4183982309
Short name	T635
Test name
Test status
Simulation time	187356002 ps
CPU time	0.9 seconds
Started	Aug 01 06:18:40 PM PDT 24
Finished	Aug 01 06:18:41 PM PDT 24
Peak memory	206948 kb
Host	smart-193d9918-394b-4662-a56a-1d6ad61439f9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41839 82309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4183982309
Directory	/workspace/40.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/40.usbdev_smoke.2654563642
Short name	T804
Test name
Test status
Simulation time	218191193 ps
CPU time	0.95 seconds
Started	Aug 01 06:18:29 PM PDT 24
Finished	Aug 01 06:18:30 PM PDT 24
Peak memory	207004 kb
Host	smart-f4c131a4-2864-4c6a-a4f6-9600a12641e7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26545 63642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2654563642
Directory	/workspace/40.usbdev_smoke/latest

Test location	/workspace/coverage/default/40.usbdev_spurious_pids_ignored.3768812353
Short name	T2866
Test name
Test status
Simulation time	2177231349 ps
CPU time	17.17 seconds
Started	Aug 01 06:18:40 PM PDT 24
Finished	Aug 01 06:18:57 PM PDT 24
Peak memory	223532 kb
Host	smart-a2721cc7-980a-4b77-bb97-3d9db71127e9
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3768812353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.3768812353
Directory	/workspace/40.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/40.usbdev_stall_priority_over_nak.2010386250
Short name	T1691
Test name
Test status
Simulation time	179280765 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:40 PM PDT 24
Finished	Aug 01 06:18:41 PM PDT 24
Peak memory	206956 kb
Host	smart-d3fa0e33-9b44-4060-b419-d3e58c02eb08
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20103 86250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2010386250
Directory	/workspace/40.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/40.usbdev_stall_trans.1582632678
Short name	T1599
Test name
Test status
Simulation time	169118032 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:32 PM PDT 24
Finished	Aug 01 06:18:33 PM PDT 24
Peak memory	206904 kb
Host	smart-d7c9dbfa-12f7-423f-bfac-f3dca07d8864
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15826 32678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1582632678
Directory	/workspace/40.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/40.usbdev_stream_len_max.1520314691
Short name	T2089
Test name
Test status
Simulation time	306486297 ps
CPU time	1.13 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:54 PM PDT 24
Peak memory	206916 kb
Host	smart-2380d101-cb8e-42de-a1eb-473153a94c27
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15203 14691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.1520314691
Directory	/workspace/40.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/40.usbdev_streaming_out.1151247786
Short name	T81
Test name
Test status
Simulation time	2444367646 ps
CPU time	18.97 seconds
Started	Aug 01 06:18:30 PM PDT 24
Finished	Aug 01 06:18:49 PM PDT 24
Peak memory	217012 kb
Host	smart-0b52925d-723f-4ad4-87f6-480d50c11daf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11512 47786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1151247786
Directory	/workspace/40.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.2402452579
Short name	T1998
Test name
Test status
Simulation time	1589229568 ps
CPU time	9.87 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:19:02 PM PDT 24
Peak memory	207188 kb
Host	smart-63a4feb9-0903-460e-8d16-e5a5af08275c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402452579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos t_handshake.2402452579
Directory	/workspace/40.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/41.usbdev_alert_test.1984041349
Short name	T2544
Test name
Test status
Simulation time	115628559 ps
CPU time	0.74 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	206972 kb
Host	smart-e51a4b3a-5c12-4157-9ebd-bb49dceb62cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1984041349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1984041349
Directory	/workspace/41.usbdev_alert_test/latest

Test location	/workspace/coverage/default/41.usbdev_av_buffer.2031945802
Short name	T1505
Test name
Test status
Simulation time	230774311 ps
CPU time	0.93 seconds
Started	Aug 01 06:18:48 PM PDT 24
Finished	Aug 01 06:18:49 PM PDT 24
Peak memory	206912 kb
Host	smart-74fb1cde-6e60-43be-a052-daf931a439ca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20319 45802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2031945802
Directory	/workspace/41.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/41.usbdev_bitstuff_err.1752808840
Short name	T1341
Test name
Test status
Simulation time	144172683 ps
CPU time	0.84 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206872 kb
Host	smart-ffd68e64-e948-400b-91c2-9eab5323d40a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528 08840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1752808840
Directory	/workspace/41.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/41.usbdev_data_toggle_clear.1868456198
Short name	T2267
Test name
Test status
Simulation time	316183490 ps
CPU time	1.19 seconds
Started	Aug 01 06:18:48 PM PDT 24
Finished	Aug 01 06:18:50 PM PDT 24
Peak memory	206940 kb
Host	smart-bb2a778e-7339-4b65-9983-d81062a151d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18684 56198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1868456198
Directory	/workspace/41.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/41.usbdev_data_toggle_restore.3882863015
Short name	T1686
Test name
Test status
Simulation time	789511430 ps
CPU time	2.19 seconds
Started	Aug 01 06:18:55 PM PDT 24
Finished	Aug 01 06:18:57 PM PDT 24
Peak memory	207176 kb
Host	smart-71c9d799-ef59-4fc6-8b2f-22e2ab22660b
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3882863015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.3882863015
Directory	/workspace/41.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/41.usbdev_device_address.2427978207
Short name	T2411
Test name
Test status
Simulation time	60699051617 ps
CPU time	99.17 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:20:29 PM PDT 24
Peak memory	207192 kb
Host	smart-9b4e674d-c47c-4a83-b723-17c90544ae15
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24279 78207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2427978207
Directory	/workspace/41.usbdev_device_address/latest

Test location	/workspace/coverage/default/41.usbdev_device_timeout.251134367
Short name	T2686
Test name
Test status
Simulation time	1107163605 ps
CPU time	8.77 seconds
Started	Aug 01 06:18:48 PM PDT 24
Finished	Aug 01 06:18:57 PM PDT 24
Peak memory	207324 kb
Host	smart-6d3b94f0-b94f-41fb-bb13-f4da71196b9e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251134367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.251134367
Directory	/workspace/41.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/41.usbdev_disable_endpoint.3242894863
Short name	T1689
Test name
Test status
Simulation time	766763407 ps
CPU time	2.03 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206912 kb
Host	smart-c933436a-6893-4382-8ae5-f5ded82bcd61
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32428 94863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3242894863
Directory	/workspace/41.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/41.usbdev_disconnected.1710603827
Short name	T1649
Test name
Test status
Simulation time	150038145 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	206860 kb
Host	smart-cd54c4b8-5dd2-4990-8dc3-3719e7704abb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106 03827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1710603827
Directory	/workspace/41.usbdev_disconnected/latest

Test location	/workspace/coverage/default/41.usbdev_enable.2418111523
Short name	T2723
Test name
Test status
Simulation time	36418343 ps
CPU time	0.7 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206920 kb
Host	smart-849d723d-28fe-4c94-affa-45e953fb9993
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24181 11523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2418111523
Directory	/workspace/41.usbdev_enable/latest

Test location	/workspace/coverage/default/41.usbdev_endpoint_access.1629223046
Short name	T2543
Test name
Test status
Simulation time	957528529 ps
CPU time	2.61 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:54 PM PDT 24
Peak memory	207152 kb
Host	smart-b2bc7e68-b802-4012-bba7-3d9ad7c7badd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16292 23046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.1629223046
Directory	/workspace/41.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/41.usbdev_endpoint_types.2858731924
Short name	T292
Test name
Test status
Simulation time	754652762 ps
CPU time	1.8 seconds
Started	Aug 01 06:18:45 PM PDT 24
Finished	Aug 01 06:18:47 PM PDT 24
Peak memory	206900 kb
Host	smart-e3b5a803-2521-4097-8c30-6d9bf4e03219
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2858731924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.2858731924
Directory	/workspace/41.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/41.usbdev_fifo_rst.1091845027
Short name	T84
Test name
Test status
Simulation time	267526352 ps
CPU time	2.1 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	207100 kb
Host	smart-ff8dba88-c17a-429e-bf22-c2aeffad42cb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10918 45027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1091845027
Directory	/workspace/41.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/41.usbdev_in_iso.1078680314
Short name	T2635
Test name
Test status
Simulation time	262021432 ps
CPU time	1.2 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	207080 kb
Host	smart-4ee231e9-abaf-4da3-8e20-4fa972772a1b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1078680314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1078680314
Directory	/workspace/41.usbdev_in_iso/latest

Test location	/workspace/coverage/default/41.usbdev_in_stall.3124981381
Short name	T1921
Test name
Test status
Simulation time	145437925 ps
CPU time	0.84 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:50 PM PDT 24
Peak memory	206920 kb
Host	smart-c2b23df5-0037-4c78-b867-e3c1a742787f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31249 81381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.3124981381
Directory	/workspace/41.usbdev_in_stall/latest

Test location	/workspace/coverage/default/41.usbdev_in_trans.1763797280
Short name	T2359
Test name
Test status
Simulation time	181242258 ps
CPU time	0.87 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206964 kb
Host	smart-3915b93b-5f36-49f3-8d7c-0b2bb316b32b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17637 97280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1763797280
Directory	/workspace/41.usbdev_in_trans/latest

Test location	/workspace/coverage/default/41.usbdev_invalid_sync.2491374269
Short name	T666
Test name
Test status
Simulation time	4019784906 ps
CPU time	29.82 seconds
Started	Aug 01 06:18:57 PM PDT 24
Finished	Aug 01 06:19:27 PM PDT 24
Peak memory	223544 kb
Host	smart-49a3d751-2c27-4900-bd75-a94b6480f7cd
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2491374269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2491374269
Directory	/workspace/41.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/41.usbdev_iso_retraction.552906161
Short name	T1473
Test name
Test status
Simulation time	12583142115 ps
CPU time	89.29 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:20:21 PM PDT 24
Peak memory	207132 kb
Host	smart-0403ef5f-d838-4704-bb3f-dc5586c46fc4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=552906161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.552906161
Directory	/workspace/41.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/41.usbdev_link_in_err.2361111498
Short name	T2726
Test name
Test status
Simulation time	178548281 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:47 PM PDT 24
Finished	Aug 01 06:18:48 PM PDT 24
Peak memory	206928 kb
Host	smart-67b6793b-6a18-4679-8cb0-f744ed4e4c07
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23611 11498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2361111498
Directory	/workspace/41.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/41.usbdev_link_suspend.2957949990
Short name	T1694
Test name
Test status
Simulation time	11221456868 ps
CPU time	15.18 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:19:08 PM PDT 24
Peak memory	207120 kb
Host	smart-b45f255d-2e05-4f8a-b016-2d63464b312c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29579 49990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2957949990
Directory	/workspace/41.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/41.usbdev_low_speed_traffic.4281827827
Short name	T2639
Test name
Test status
Simulation time	2253953213 ps
CPU time	16.3 seconds
Started	Aug 01 06:18:55 PM PDT 24
Finished	Aug 01 06:19:11 PM PDT 24
Peak memory	216288 kb
Host	smart-2a9a97cf-6cd3-4b37-bc52-6a5c7156f666
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42818 27827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.4281827827
Directory	/workspace/41.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3767171167
Short name	T1019
Test name
Test status
Simulation time	2722600163 ps
CPU time	77.52 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:20:08 PM PDT 24
Peak memory	216840 kb
Host	smart-1054247b-180f-455e-a38a-3a294afab4b5
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3767171167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3767171167
Directory	/workspace/41.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/41.usbdev_max_length_in_transaction.1045078778
Short name	T2623
Test name
Test status
Simulation time	231031519 ps
CPU time	1 seconds
Started	Aug 01 06:18:55 PM PDT 24
Finished	Aug 01 06:18:56 PM PDT 24
Peak memory	206956 kb
Host	smart-8d99b321-6728-45c1-9733-7a267fb1f804
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1045078778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1045078778
Directory	/workspace/41.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/41.usbdev_max_length_out_transaction.527280600
Short name	T2012
Test name
Test status
Simulation time	187406215 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206924 kb
Host	smart-809ff79a-f23b-4714-9f93-3d0e7580304a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52728 0600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.527280600
Directory	/workspace/41.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/41.usbdev_min_inter_pkt_delay.511984097
Short name	T592
Test name
Test status
Simulation time	2582625716 ps
CPU time	76.04 seconds
Started	Aug 01 06:18:46 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	215212 kb
Host	smart-a4a9230b-affa-4ed8-9c81-081bc5983408
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=511984097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.511984097
Directory	/workspace/41.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/41.usbdev_min_length_in_transaction.3260801176
Short name	T2413
Test name
Test status
Simulation time	150376189 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	206968 kb
Host	smart-1fdde19d-1a1d-4780-a6b1-048b46c3ae84
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3260801176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3260801176
Directory	/workspace/41.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/41.usbdev_min_length_out_transaction.2709302687
Short name	T1316
Test name
Test status
Simulation time	142565070 ps
CPU time	0.81 seconds
Started	Aug 01 06:18:53 PM PDT 24
Finished	Aug 01 06:18:54 PM PDT 24
Peak memory	206912 kb
Host	smart-bfcd02b1-4dfb-4783-a202-d6cc4613681e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27093 02687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2709302687
Directory	/workspace/41.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/41.usbdev_nak_trans.1270620879
Short name	T168
Test name
Test status
Simulation time	155356770 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:44 PM PDT 24
Finished	Aug 01 06:18:45 PM PDT 24
Peak memory	206984 kb
Host	smart-6d2425dc-a08b-47f6-a27d-a8f31d4584ef
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12706 20879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1270620879
Directory	/workspace/41.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/41.usbdev_out_iso.295748381
Short name	T2100
Test name
Test status
Simulation time	216805082 ps
CPU time	0.99 seconds
Started	Aug 01 06:18:48 PM PDT 24
Finished	Aug 01 06:18:49 PM PDT 24
Peak memory	206884 kb
Host	smart-c3cce767-fd87-4fac-9e9a-33c853f64109
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29574 8381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.295748381
Directory	/workspace/41.usbdev_out_iso/latest

Test location	/workspace/coverage/default/41.usbdev_out_stall.815517243
Short name	T508
Test name
Test status
Simulation time	175028013 ps
CPU time	0.91 seconds
Started	Aug 01 06:18:56 PM PDT 24
Finished	Aug 01 06:18:57 PM PDT 24
Peak memory	206928 kb
Host	smart-52303e26-49f9-4ea1-a26e-8e019b0a9496
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81551 7243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.815517243
Directory	/workspace/41.usbdev_out_stall/latest

Test location	/workspace/coverage/default/41.usbdev_out_trans_nak.532244484
Short name	T2426
Test name
Test status
Simulation time	185432041 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:54 PM PDT 24
Finished	Aug 01 06:18:55 PM PDT 24
Peak memory	206952 kb
Host	smart-506177d8-c04b-4821-8943-0402fd630689
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53224 4484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.532244484
Directory	/workspace/41.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/41.usbdev_pending_in_trans.3808573151
Short name	T1272
Test name
Test status
Simulation time	185453197 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:54 PM PDT 24
Peak memory	206968 kb
Host	smart-b086a871-b383-4b36-90db-eba30ed8a2b0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38085 73151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3808573151
Directory	/workspace/41.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/41.usbdev_phy_config_pinflip.3439074457
Short name	T1940
Test name
Test status
Simulation time	234781920 ps
CPU time	0.99 seconds
Started	Aug 01 06:18:56 PM PDT 24
Finished	Aug 01 06:18:58 PM PDT 24
Peak memory	206952 kb
Host	smart-ffda808f-24b2-4a69-a128-c9289516e784
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3439074457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.3439074457
Directory	/workspace/41.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2738764392
Short name	T1460
Test name
Test status
Simulation time	153762543 ps
CPU time	0.81 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206944 kb
Host	smart-5c8abc13-7665-4ee9-b6e2-8accec4c4089
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27387 64392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2738764392
Directory	/workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/41.usbdev_phy_pins_sense.703288798
Short name	T2498
Test name
Test status
Simulation time	34436237 ps
CPU time	0.68 seconds
Started	Aug 01 06:18:46 PM PDT 24
Finished	Aug 01 06:18:46 PM PDT 24
Peak memory	206844 kb
Host	smart-41682098-6fff-4bd3-ae8c-e76135c4b7eb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70328 8798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.703288798
Directory	/workspace/41.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/41.usbdev_pkt_buffer.2745912671
Short name	T1368
Test name
Test status
Simulation time	11393748495 ps
CPU time	29.2 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:19:21 PM PDT 24
Peak memory	223520 kb
Host	smart-4a6cbb4a-1f00-4fcc-96ea-8c244d0acc8c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27459 12671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2745912671
Directory	/workspace/41.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/41.usbdev_pkt_received.1836606299
Short name	T1083
Test name
Test status
Simulation time	175319055 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206848 kb
Host	smart-f47ab3e5-c32a-4f86-ae65-ffcd57d3abed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18366 06299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1836606299
Directory	/workspace/41.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/41.usbdev_pkt_sent.2123701215
Short name	T1748
Test name
Test status
Simulation time	205560067 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:47 PM PDT 24
Finished	Aug 01 06:18:48 PM PDT 24
Peak memory	206856 kb
Host	smart-6bf31ed1-6591-4ad1-a936-868ad27c0da2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21237 01215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2123701215
Directory	/workspace/41.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/41.usbdev_random_length_in_transaction.1201417688
Short name	T1572
Test name
Test status
Simulation time	171669856 ps
CPU time	0.83 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206932 kb
Host	smart-5cf54a72-5b4f-4680-8599-8df75ad61d8f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12014 17688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.1201417688
Directory	/workspace/41.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/41.usbdev_random_length_out_transaction.3893951971
Short name	T600
Test name
Test status
Simulation time	180499791 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:48 PM PDT 24
Finished	Aug 01 06:18:49 PM PDT 24
Peak memory	206912 kb
Host	smart-786779b1-b246-4346-b53c-a35c152ac9a7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38939 51971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3893951971
Directory	/workspace/41.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/41.usbdev_rx_crc_err.1047575873
Short name	T2862
Test name
Test status
Simulation time	134404477 ps
CPU time	0.83 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:50 PM PDT 24
Peak memory	206896 kb
Host	smart-b26b849f-944c-4648-8c79-2fc242a0db77
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10475 75873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1047575873
Directory	/workspace/41.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/41.usbdev_rx_full.4081143193
Short name	T37
Test name
Test status
Simulation time	271153905 ps
CPU time	1.12 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206952 kb
Host	smart-48773a37-4340-490b-96f5-0dcbc02f5381
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40811 43193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.4081143193
Directory	/workspace/41.usbdev_rx_full/latest

Test location	/workspace/coverage/default/41.usbdev_setup_stage.616961829
Short name	T1201
Test name
Test status
Simulation time	163670775 ps
CPU time	0.94 seconds
Started	Aug 01 06:18:48 PM PDT 24
Finished	Aug 01 06:18:49 PM PDT 24
Peak memory	206916 kb
Host	smart-d95d63a9-e813-4848-96c3-3b70fb9c6082
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61696 1829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.616961829
Directory	/workspace/41.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/41.usbdev_setup_trans_ignored.2108336266
Short name	T2534
Test name
Test status
Simulation time	147784615 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	206952 kb
Host	smart-62206420-1c40-416e-ae61-6741d6a88fc2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21083 36266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2108336266
Directory	/workspace/41.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/41.usbdev_smoke.2783957331
Short name	T205
Test name
Test status
Simulation time	204775132 ps
CPU time	1.05 seconds
Started	Aug 01 06:18:58 PM PDT 24
Finished	Aug 01 06:18:59 PM PDT 24
Peak memory	206964 kb
Host	smart-3caf4c88-0349-4c69-a3e3-969536298a0f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27839 57331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2783957331
Directory	/workspace/41.usbdev_smoke/latest

Test location	/workspace/coverage/default/41.usbdev_spurious_pids_ignored.3139336706
Short name	T2672
Test name
Test status
Simulation time	2599565502 ps
CPU time	24.79 seconds
Started	Aug 01 06:18:57 PM PDT 24
Finished	Aug 01 06:19:21 PM PDT 24
Peak memory	223480 kb
Host	smart-33ce8e24-5e9e-4997-920e-2672f4b543ef
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3139336706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3139336706
Directory	/workspace/41.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/41.usbdev_stall_priority_over_nak.3998749839
Short name	T2763
Test name
Test status
Simulation time	188984060 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:54 PM PDT 24
Finished	Aug 01 06:18:56 PM PDT 24
Peak memory	206956 kb
Host	smart-7d8328c5-2129-4123-a8af-800bf9a98fde
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39987 49839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3998749839
Directory	/workspace/41.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/41.usbdev_stall_trans.257342323
Short name	T749
Test name
Test status
Simulation time	151767772 ps
CPU time	0.9 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206932 kb
Host	smart-e07c9dfa-7e63-455d-aa9a-6979f744eac6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25734 2323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.257342323
Directory	/workspace/41.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/41.usbdev_stream_len_max.2100726267
Short name	T1178
Test name
Test status
Simulation time	256941029 ps
CPU time	1.02 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:50 PM PDT 24
Peak memory	206900 kb
Host	smart-d7c4af99-87bb-4e94-b7a7-a12bd184e81e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21007 26267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2100726267
Directory	/workspace/41.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/41.usbdev_streaming_out.4033288440
Short name	T2081
Test name
Test status
Simulation time	2268750976 ps
CPU time	62.17 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:19:53 PM PDT 24
Peak memory	215356 kb
Host	smart-62c3da2e-64b5-4b80-8000-b5fae0f84464
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40332 88440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.4033288440
Directory	/workspace/41.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.3245464527
Short name	T2072
Test name
Test status
Simulation time	1692979895 ps
CPU time	39.19 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:19:28 PM PDT 24
Peak memory	207100 kb
Host	smart-e6604fd2-e4ab-45b9-9a80-91b5f08a6e9b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245464527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos t_handshake.3245464527
Directory	/workspace/41.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/42.usbdev_alert_test.4253105303
Short name	T699
Test name
Test status
Simulation time	54342922 ps
CPU time	0.69 seconds
Started	Aug 01 06:19:01 PM PDT 24
Finished	Aug 01 06:19:02 PM PDT 24
Peak memory	206960 kb
Host	smart-30e6f0e3-4d01-4d2a-a176-f6ecebf39460
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=4253105303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.4253105303
Directory	/workspace/42.usbdev_alert_test/latest

Test location	/workspace/coverage/default/42.usbdev_av_buffer.766578834
Short name	T1544
Test name
Test status
Simulation time	162146962 ps
CPU time	0.91 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206928 kb
Host	smart-ca2c57c1-9bce-4a4f-a737-f93240c2cc0b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76657 8834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.766578834
Directory	/workspace/42.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/42.usbdev_bitstuff_err.1111118833
Short name	T2592
Test name
Test status
Simulation time	145860279 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206908 kb
Host	smart-9db38c9a-d810-4051-8de0-3c7467f27760
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11111 18833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.1111118833
Directory	/workspace/42.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/42.usbdev_data_toggle_clear.920710994
Short name	T734
Test name
Test status
Simulation time	268450763 ps
CPU time	1.08 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206932 kb
Host	smart-b619f0e8-971e-4172-8f61-b442b1deb0e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92071 0994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.920710994
Directory	/workspace/42.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/42.usbdev_data_toggle_restore.1373577533
Short name	T2221
Test name
Test status
Simulation time	963893645 ps
CPU time	2.8 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	207140 kb
Host	smart-dcbe25fd-4a49-4e8c-9083-42041c49aa28
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1373577533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.1373577533
Directory	/workspace/42.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/42.usbdev_device_address.2929269073
Short name	T1561
Test name
Test status
Simulation time	23833595596 ps
CPU time	43.11 seconds
Started	Aug 01 06:18:54 PM PDT 24
Finished	Aug 01 06:19:37 PM PDT 24
Peak memory	207156 kb
Host	smart-a135dde4-3e43-4aaa-97e3-a7b62f8112c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29292 69073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.2929269073
Directory	/workspace/42.usbdev_device_address/latest

Test location	/workspace/coverage/default/42.usbdev_device_timeout.3248850583
Short name	T564
Test name
Test status
Simulation time	3559535354 ps
CPU time	22.74 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:19:12 PM PDT 24
Peak memory	207240 kb
Host	smart-b3cc53a6-5c24-4b02-bc02-3d8b7c0e3c8a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248850583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.3248850583
Directory	/workspace/42.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/42.usbdev_disable_endpoint.781893170
Short name	T2257
Test name
Test status
Simulation time	968722445 ps
CPU time	2.04 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	206948 kb
Host	smart-14c5ecfe-b2f4-4f94-b9d0-f61dcd8cdbaa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78189 3170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.781893170
Directory	/workspace/42.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/42.usbdev_disconnected.77450578
Short name	T2171
Test name
Test status
Simulation time	134633876 ps
CPU time	0.82 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206932 kb
Host	smart-20ab7c33-c445-4cd6-a6de-d0a22a2ff460
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77450 578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.77450578
Directory	/workspace/42.usbdev_disconnected/latest

Test location	/workspace/coverage/default/42.usbdev_enable.1496618191
Short name	T1256
Test name
Test status
Simulation time	39687900 ps
CPU time	0.68 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	206836 kb
Host	smart-656959fa-c2e5-4292-b05f-38daec09166f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14966 18191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1496618191
Directory	/workspace/42.usbdev_enable/latest

Test location	/workspace/coverage/default/42.usbdev_endpoint_access.463900449
Short name	T489
Test name
Test status
Simulation time	950929113 ps
CPU time	2.43 seconds
Started	Aug 01 06:18:58 PM PDT 24
Finished	Aug 01 06:19:01 PM PDT 24
Peak memory	207152 kb
Host	smart-faede94b-9572-458f-9b86-0456ecb422a4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46390 0449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.463900449
Directory	/workspace/42.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/42.usbdev_endpoint_types.3916099902
Short name	T161
Test name
Test status
Simulation time	425221650 ps
CPU time	1.36 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206920 kb
Host	smart-e574ba82-5224-4eb9-a05c-a7393e19fcb1
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3916099902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.3916099902
Directory	/workspace/42.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/42.usbdev_fifo_rst.1558009972
Short name	T2228
Test name
Test status
Simulation time	410385260 ps
CPU time	2.86 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:54 PM PDT 24
Peak memory	207148 kb
Host	smart-604be270-0808-4faf-ad17-f08fe497600e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15580 09972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.1558009972
Directory	/workspace/42.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/42.usbdev_in_iso.4077526053
Short name	T1875
Test name
Test status
Simulation time	209306176 ps
CPU time	1.15 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:50 PM PDT 24
Peak memory	215272 kb
Host	smart-2ea96889-c60a-424b-bdf0-d36692157a16
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4077526053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.4077526053
Directory	/workspace/42.usbdev_in_iso/latest

Test location	/workspace/coverage/default/42.usbdev_in_stall.992392659
Short name	T2172
Test name
Test status
Simulation time	204742999 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	206916 kb
Host	smart-af13c4f7-344a-4a9e-bee2-d61473199ea7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99239 2659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.992392659
Directory	/workspace/42.usbdev_in_stall/latest

Test location	/workspace/coverage/default/42.usbdev_in_trans.88848591
Short name	T1495
Test name
Test status
Simulation time	283362938 ps
CPU time	1.04 seconds
Started	Aug 01 06:18:57 PM PDT 24
Finished	Aug 01 06:18:58 PM PDT 24
Peak memory	206952 kb
Host	smart-a015b2c5-fcbf-4404-ae34-d319a1c10b13
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88848 591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.88848591
Directory	/workspace/42.usbdev_in_trans/latest

Test location	/workspace/coverage/default/42.usbdev_invalid_sync.3030974844
Short name	T2189
Test name
Test status
Simulation time	4069851142 ps
CPU time	111.84 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:20:43 PM PDT 24
Peak memory	217184 kb
Host	smart-1149e0e7-1c7a-4ad8-9bd9-3955e25bb317
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3030974844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.3030974844
Directory	/workspace/42.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/42.usbdev_iso_retraction.2012683806
Short name	T75
Test name
Test status
Simulation time	6799496367 ps
CPU time	42.93 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:19:33 PM PDT 24
Peak memory	207096 kb
Host	smart-eae8d93b-ebcc-421e-a020-e1d66f4e0198
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2012683806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.2012683806
Directory	/workspace/42.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/42.usbdev_link_in_err.388186574
Short name	T697
Test name
Test status
Simulation time	245439156 ps
CPU time	0.99 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206896 kb
Host	smart-89ebf058-829f-45f8-8810-c4c33c17f44e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38818 6574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.388186574
Directory	/workspace/42.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/42.usbdev_link_suspend.1057562615
Short name	T90
Test name
Test status
Simulation time	3609810357 ps
CPU time	5.26 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:54 PM PDT 24
Peak memory	207116 kb
Host	smart-42da0ac9-a597-4611-b72b-392b1c4c9b0a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10575 62615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1057562615
Directory	/workspace/42.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/42.usbdev_low_speed_traffic.3556145985
Short name	T845
Test name
Test status
Simulation time	3182919034 ps
CPU time	32.01 seconds
Started	Aug 01 06:18:55 PM PDT 24
Finished	Aug 01 06:19:27 PM PDT 24
Peak memory	223500 kb
Host	smart-026b31e3-784d-456d-8272-d9e4bde097e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35561 45985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3556145985
Directory	/workspace/42.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1585904083
Short name	T1501
Test name
Test status
Simulation time	1746059292 ps
CPU time	49.07 seconds
Started	Aug 01 06:18:45 PM PDT 24
Finished	Aug 01 06:19:34 PM PDT 24
Peak memory	215300 kb
Host	smart-e15e9e3a-9e70-4dfc-b96b-69fa5954dd5f
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1585904083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1585904083
Directory	/workspace/42.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/42.usbdev_max_length_in_transaction.1468393505
Short name	T706
Test name
Test status
Simulation time	239366760 ps
CPU time	1.03 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206956 kb
Host	smart-ca96b4e1-90e8-44fb-b2cd-9c21405b6ef4
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1468393505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1468393505
Directory	/workspace/42.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/42.usbdev_max_length_out_transaction.1174723027
Short name	T1601
Test name
Test status
Simulation time	226209673 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:54 PM PDT 24
Finished	Aug 01 06:18:55 PM PDT 24
Peak memory	206960 kb
Host	smart-92c84807-bc78-441f-8d77-feca66103cad
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11747 23027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1174723027
Directory	/workspace/42.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/42.usbdev_min_inter_pkt_delay.635792734
Short name	T725
Test name
Test status
Simulation time	2907427840 ps
CPU time	79.93 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:20:11 PM PDT 24
Peak memory	216988 kb
Host	smart-9bd41ad3-8d37-4265-b877-dadf978ff239
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=635792734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.635792734
Directory	/workspace/42.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/42.usbdev_min_length_in_transaction.643575062
Short name	T1339
Test name
Test status
Simulation time	152568711 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:54 PM PDT 24
Peak memory	206932 kb
Host	smart-3637193c-a50f-4291-8479-e35660b47931
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=643575062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.643575062
Directory	/workspace/42.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/42.usbdev_min_length_out_transaction.258159868
Short name	T1969
Test name
Test status
Simulation time	172558055 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:54 PM PDT 24
Finished	Aug 01 06:18:55 PM PDT 24
Peak memory	206976 kb
Host	smart-e0d98006-77f4-4c64-8a34-cd7c9abf9a01
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25815 9868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.258159868
Directory	/workspace/42.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/42.usbdev_out_iso.1814864412
Short name	T543
Test name
Test status
Simulation time	205724502 ps
CPU time	0.94 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:50 PM PDT 24
Peak memory	206908 kb
Host	smart-2cc74229-4972-4929-8dab-562b14fc4c44
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18148 64412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.1814864412
Directory	/workspace/42.usbdev_out_iso/latest

Test location	/workspace/coverage/default/42.usbdev_out_stall.3429260546
Short name	T970
Test name
Test status
Simulation time	160389629 ps
CPU time	0.88 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:50 PM PDT 24
Peak memory	206912 kb
Host	smart-66995683-58d2-4c2d-975a-a28cfad05466
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34292 60546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3429260546
Directory	/workspace/42.usbdev_out_stall/latest

Test location	/workspace/coverage/default/42.usbdev_out_trans_nak.1251772561
Short name	T2390
Test name
Test status
Simulation time	159369262 ps
CPU time	0.84 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206948 kb
Host	smart-d6826375-73aa-466f-b594-1a4a807ceb79
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12517 72561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1251772561
Directory	/workspace/42.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/42.usbdev_pending_in_trans.3929880922
Short name	T868
Test name
Test status
Simulation time	147726552 ps
CPU time	0.86 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206808 kb
Host	smart-2afefdfe-708a-461d-8a9a-c6df14667968
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39298 80922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3929880922
Directory	/workspace/42.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/42.usbdev_phy_config_pinflip.122380912
Short name	T1175
Test name
Test status
Simulation time	227169454 ps
CPU time	1.03 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206788 kb
Host	smart-156f9331-86ed-456b-9aa7-dcb68bc0d2ab
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=122380912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.122380912
Directory	/workspace/42.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.2140425293
Short name	T1836
Test name
Test status
Simulation time	187094648 ps
CPU time	0.91 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206856 kb
Host	smart-2fd3ade7-bfeb-481f-b0af-d0cf135a929c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21404 25293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.2140425293
Directory	/workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/42.usbdev_phy_pins_sense.3409696429
Short name	T2249
Test name
Test status
Simulation time	42362659 ps
CPU time	0.69 seconds
Started	Aug 01 06:18:54 PM PDT 24
Finished	Aug 01 06:18:55 PM PDT 24
Peak memory	206912 kb
Host	smart-f4893eeb-b925-4af9-83ba-ab5636f11421
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34096 96429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3409696429
Directory	/workspace/42.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/42.usbdev_pkt_buffer.3084005941
Short name	T2061
Test name
Test status
Simulation time	9828398476 ps
CPU time	25.55 seconds
Started	Aug 01 06:18:56 PM PDT 24
Finished	Aug 01 06:19:21 PM PDT 24
Peak memory	215392 kb
Host	smart-1ca2591c-a07e-49b4-8a8c-5c85926ddc52
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30840 05941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3084005941
Directory	/workspace/42.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/42.usbdev_pkt_received.3103398727
Short name	T1441
Test name
Test status
Simulation time	153443545 ps
CPU time	0.83 seconds
Started	Aug 01 06:18:51 PM PDT 24
Finished	Aug 01 06:18:52 PM PDT 24
Peak memory	206932 kb
Host	smart-f2c5dee6-e4a9-40d9-8503-1d5192e6b5e8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31033 98727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3103398727
Directory	/workspace/42.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/42.usbdev_pkt_sent.22803889
Short name	T701
Test name
Test status
Simulation time	209430180 ps
CPU time	0.92 seconds
Started	Aug 01 06:18:54 PM PDT 24
Finished	Aug 01 06:18:55 PM PDT 24
Peak memory	206936 kb
Host	smart-be35f1bc-d675-45ba-af49-96dd85035620
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22803 889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.22803889
Directory	/workspace/42.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/42.usbdev_random_length_in_transaction.1551215104
Short name	T1949
Test name
Test status
Simulation time	246305326 ps
CPU time	0.96 seconds
Started	Aug 01 06:18:52 PM PDT 24
Finished	Aug 01 06:18:53 PM PDT 24
Peak memory	206960 kb
Host	smart-af5fdfe9-c590-45d1-a28b-66860753f2df
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15512 15104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.1551215104
Directory	/workspace/42.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/42.usbdev_random_length_out_transaction.4254448742
Short name	T1013
Test name
Test status
Simulation time	151560510 ps
CPU time	0.89 seconds
Started	Aug 01 06:18:56 PM PDT 24
Finished	Aug 01 06:18:57 PM PDT 24
Peak memory	206948 kb
Host	smart-4eecf986-e7cf-46ea-9bee-33ffe1e40918
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42544 48742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.4254448742
Directory	/workspace/42.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/42.usbdev_rx_crc_err.3809679616
Short name	T886
Test name
Test status
Simulation time	143666975 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:50 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206900 kb
Host	smart-89d97669-80ab-46f7-9457-f6a2e526ade2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38096 79616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.3809679616
Directory	/workspace/42.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/42.usbdev_rx_full.561455048
Short name	T2034
Test name
Test status
Simulation time	306735678 ps
CPU time	1.17 seconds
Started	Aug 01 06:18:49 PM PDT 24
Finished	Aug 01 06:18:51 PM PDT 24
Peak memory	206956 kb
Host	smart-4afd8724-2f63-4aa2-8a58-b11eb43ccdfa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56145 5048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.561455048
Directory	/workspace/42.usbdev_rx_full/latest

Test location	/workspace/coverage/default/42.usbdev_setup_stage.3181060445
Short name	T511
Test name
Test status
Simulation time	149151345 ps
CPU time	0.82 seconds
Started	Aug 01 06:18:54 PM PDT 24
Finished	Aug 01 06:18:55 PM PDT 24
Peak memory	206928 kb
Host	smart-6267071c-5165-4556-880e-f11a92f42fd7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31810 60445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3181060445
Directory	/workspace/42.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/42.usbdev_setup_trans_ignored.894625867
Short name	T1023
Test name
Test status
Simulation time	150383250 ps
CPU time	0.91 seconds
Started	Aug 01 06:18:57 PM PDT 24
Finished	Aug 01 06:18:58 PM PDT 24
Peak memory	206952 kb
Host	smart-ed235e6b-9803-4af6-b786-d02601c6e728
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89462 5867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.894625867
Directory	/workspace/42.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/42.usbdev_smoke.124328083
Short name	T2892
Test name
Test status
Simulation time	243200506 ps
CPU time	1.1 seconds
Started	Aug 01 06:18:53 PM PDT 24
Finished	Aug 01 06:18:55 PM PDT 24
Peak memory	206940 kb
Host	smart-15183ae0-2305-4c06-a3cd-fa698aa9134a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12432 8083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.124328083
Directory	/workspace/42.usbdev_smoke/latest

Test location	/workspace/coverage/default/42.usbdev_spurious_pids_ignored.715243279
Short name	T2894
Test name
Test status
Simulation time	2166109054 ps
CPU time	61.52 seconds
Started	Aug 01 06:18:53 PM PDT 24
Finished	Aug 01 06:19:55 PM PDT 24
Peak memory	223300 kb
Host	smart-7fb822ad-4263-416f-a189-a3926178abf0
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=715243279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.715243279
Directory	/workspace/42.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/42.usbdev_stall_priority_over_nak.316692433
Short name	T1412
Test name
Test status
Simulation time	165382019 ps
CPU time	0.86 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:19:05 PM PDT 24
Peak memory	206952 kb
Host	smart-d00771c0-b4b6-490d-a2bd-2a6a60c14bbb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31669 2433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.316692433
Directory	/workspace/42.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/42.usbdev_stall_trans.1206214121
Short name	T1927
Test name
Test status
Simulation time	153019278 ps
CPU time	0.86 seconds
Started	Aug 01 06:19:00 PM PDT 24
Finished	Aug 01 06:19:02 PM PDT 24
Peak memory	206940 kb
Host	smart-e22eede8-67fb-4fcb-a056-82a5ed0c1183
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12062 14121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.1206214121
Directory	/workspace/42.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/42.usbdev_stream_len_max.2511661341
Short name	T1529
Test name
Test status
Simulation time	1065859460 ps
CPU time	2.73 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:19:07 PM PDT 24
Peak memory	207160 kb
Host	smart-43ab967e-5076-45da-aa27-423af2be9502
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25116 61341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.2511661341
Directory	/workspace/42.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/42.usbdev_streaming_out.1516609339
Short name	T1452
Test name
Test status
Simulation time	3070114736 ps
CPU time	31.57 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:35 PM PDT 24
Peak memory	223540 kb
Host	smart-8c441f8f-4bb1-4107-a1a6-7f5a4f2826e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15166 09339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1516609339
Directory	/workspace/42.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.2686329688
Short name	T815
Test name
Test status
Simulation time	709271077 ps
CPU time	14.41 seconds
Started	Aug 01 06:18:47 PM PDT 24
Finished	Aug 01 06:19:02 PM PDT 24
Peak memory	207092 kb
Host	smart-ba19b2cb-bee0-43a1-a1ba-1b3dfddf8218
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686329688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos t_handshake.2686329688
Directory	/workspace/42.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/43.usbdev_alert_test.4208526502
Short name	T119
Test name
Test status
Simulation time	38778330 ps
CPU time	0.66 seconds
Started	Aug 01 06:19:02 PM PDT 24
Finished	Aug 01 06:19:03 PM PDT 24
Peak memory	206960 kb
Host	smart-e7ba4edc-999c-4921-a66d-a1996a095cc1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=4208526502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.4208526502
Directory	/workspace/43.usbdev_alert_test/latest

Test location	/workspace/coverage/default/43.usbdev_av_buffer.4055084582
Short name	T949
Test name
Test status
Simulation time	163883789 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	206920 kb
Host	smart-cb319723-e1b7-410c-bc9e-22b4ecdd624d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40550 84582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.4055084582
Directory	/workspace/43.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/43.usbdev_bitstuff_err.94190519
Short name	T1056
Test name
Test status
Simulation time	147440159 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:04 PM PDT 24
Peak memory	206932 kb
Host	smart-e5b50e08-8966-4af8-ac24-655abcaf869f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94190 519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.94190519
Directory	/workspace/43.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/43.usbdev_data_toggle_clear.4201100354
Short name	T981
Test name
Test status
Simulation time	236113068 ps
CPU time	1.09 seconds
Started	Aug 01 06:19:01 PM PDT 24
Finished	Aug 01 06:19:02 PM PDT 24
Peak memory	206912 kb
Host	smart-16b54b13-e5fd-4dd6-bc3a-ef6f9b7c0d6e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42011 00354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.4201100354
Directory	/workspace/43.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/43.usbdev_data_toggle_restore.2634343441
Short name	T612
Test name
Test status
Simulation time	299750458 ps
CPU time	1.12 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	206952 kb
Host	smart-40eb2ced-1ff3-450f-bfaa-912b25d2e087
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2634343441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.2634343441
Directory	/workspace/43.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/43.usbdev_device_address.2397575320
Short name	T451
Test name
Test status
Simulation time	47653447954 ps
CPU time	85.27 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:20:30 PM PDT 24
Peak memory	207124 kb
Host	smart-9c824d65-cf79-4dfa-8600-db182f46c213
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23975 75320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2397575320
Directory	/workspace/43.usbdev_device_address/latest

Test location	/workspace/coverage/default/43.usbdev_device_timeout.4294796944
Short name	T2559
Test name
Test status
Simulation time	2096501325 ps
CPU time	17.66 seconds
Started	Aug 01 06:18:59 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	207140 kb
Host	smart-8187eb44-26cf-4569-a9be-3116fb70f75e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294796944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.4294796944
Directory	/workspace/43.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/43.usbdev_disable_endpoint.2828850964
Short name	T2366
Test name
Test status
Simulation time	744986765 ps
CPU time	1.8 seconds
Started	Aug 01 06:19:01 PM PDT 24
Finished	Aug 01 06:19:03 PM PDT 24
Peak memory	206908 kb
Host	smart-59ffc8e6-a0b8-4763-ab7f-5f426915f7f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28288 50964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.2828850964
Directory	/workspace/43.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/43.usbdev_disconnected.625005565
Short name	T1104
Test name
Test status
Simulation time	142506596 ps
CPU time	0.79 seconds
Started	Aug 01 06:19:02 PM PDT 24
Finished	Aug 01 06:19:03 PM PDT 24
Peak memory	206884 kb
Host	smart-b2c42f12-1894-43fd-9581-2f204f4d03b7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62500 5565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.625005565
Directory	/workspace/43.usbdev_disconnected/latest

Test location	/workspace/coverage/default/43.usbdev_enable.2687943455
Short name	T661
Test name
Test status
Simulation time	60293598 ps
CPU time	0.83 seconds
Started	Aug 01 06:19:06 PM PDT 24
Finished	Aug 01 06:19:07 PM PDT 24
Peak memory	206860 kb
Host	smart-88d2bb12-c266-4331-8150-28483d849a04
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26879 43455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2687943455
Directory	/workspace/43.usbdev_enable/latest

Test location	/workspace/coverage/default/43.usbdev_endpoint_access.1525129273
Short name	T903
Test name
Test status
Simulation time	944171804 ps
CPU time	2.4 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:05 PM PDT 24
Peak memory	207128 kb
Host	smart-f1176338-516a-42e7-abc6-7d90500d3776
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15251 29273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.1525129273
Directory	/workspace/43.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/43.usbdev_fifo_rst.1848656892
Short name	T146
Test name
Test status
Simulation time	152188259 ps
CPU time	1.41 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:07 PM PDT 24
Peak memory	207100 kb
Host	smart-9a10df74-28e0-41d7-a50f-a0089441c07f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18486 56892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1848656892
Directory	/workspace/43.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/43.usbdev_in_iso.804734046
Short name	T80
Test name
Test status
Simulation time	188814156 ps
CPU time	0.95 seconds
Started	Aug 01 06:18:59 PM PDT 24
Finished	Aug 01 06:19:00 PM PDT 24
Peak memory	206956 kb
Host	smart-df3b1928-76d9-4d34-a697-44471040acd0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=804734046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.804734046
Directory	/workspace/43.usbdev_in_iso/latest

Test location	/workspace/coverage/default/43.usbdev_in_stall.342507882
Short name	T2634
Test name
Test status
Simulation time	142454276 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:59 PM PDT 24
Finished	Aug 01 06:19:00 PM PDT 24
Peak memory	206900 kb
Host	smart-bb7f5780-c297-4367-978a-d80585cea4c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34250 7882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.342507882
Directory	/workspace/43.usbdev_in_stall/latest

Test location	/workspace/coverage/default/43.usbdev_in_trans.872445099
Short name	T1282
Test name
Test status
Simulation time	162650716 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:04 PM PDT 24
Peak memory	206948 kb
Host	smart-47d60c65-6183-4851-b30e-c0da525a7313
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87244 5099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.872445099
Directory	/workspace/43.usbdev_in_trans/latest

Test location	/workspace/coverage/default/43.usbdev_invalid_sync.3120130295
Short name	T149
Test name
Test status
Simulation time	2758603122 ps
CPU time	20.86 seconds
Started	Aug 01 06:19:01 PM PDT 24
Finished	Aug 01 06:19:22 PM PDT 24
Peak memory	223556 kb
Host	smart-681cfd29-16d5-424c-b316-3305d7a247d2
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3120130295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.3120130295
Directory	/workspace/43.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/43.usbdev_link_in_err.1497024501
Short name	T2006
Test name
Test status
Simulation time	174673464 ps
CPU time	0.89 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:05 PM PDT 24
Peak memory	206928 kb
Host	smart-29ca2db1-df20-45b6-98a4-f82bca35834c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14970 24501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.1497024501
Directory	/workspace/43.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/43.usbdev_link_suspend.1969002513
Short name	T678
Test name
Test status
Simulation time	4344829227 ps
CPU time	5.72 seconds
Started	Aug 01 06:19:02 PM PDT 24
Finished	Aug 01 06:19:07 PM PDT 24
Peak memory	216288 kb
Host	smart-95d6dcfc-8de3-494f-9e24-92ed4e883d06
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19690 02513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.1969002513
Directory	/workspace/43.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/43.usbdev_low_speed_traffic.2823727491
Short name	T2297
Test name
Test status
Simulation time	3941703824 ps
CPU time	27.99 seconds
Started	Aug 01 06:18:58 PM PDT 24
Finished	Aug 01 06:19:26 PM PDT 24
Peak memory	215340 kb
Host	smart-5667ab84-c22b-4504-a4d6-546ea039fd56
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28237 27491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2823727491
Directory	/workspace/43.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/43.usbdev_max_inter_pkt_delay.987295929
Short name	T1007
Test name
Test status
Simulation time	2398952657 ps
CPU time	23.59 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:19:28 PM PDT 24
Peak memory	215376 kb
Host	smart-609a5011-5308-4518-be94-d0a96f9238e4
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=987295929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.987295929
Directory	/workspace/43.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/43.usbdev_max_length_in_transaction.3105103876
Short name	T758
Test name
Test status
Simulation time	267073265 ps
CPU time	1.02 seconds
Started	Aug 01 06:18:59 PM PDT 24
Finished	Aug 01 06:19:00 PM PDT 24
Peak memory	206904 kb
Host	smart-6605f82c-c79f-4296-9c4e-bb56684eb0b6
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3105103876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3105103876
Directory	/workspace/43.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/43.usbdev_max_length_out_transaction.809089009
Short name	T477
Test name
Test status
Simulation time	189097579 ps
CPU time	0.97 seconds
Started	Aug 01 06:19:00 PM PDT 24
Finished	Aug 01 06:19:01 PM PDT 24
Peak memory	206948 kb
Host	smart-ba972f26-71fc-4917-b954-f46df7475615
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80908 9009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.809089009
Directory	/workspace/43.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3073088703
Short name	T2882
Test name
Test status
Simulation time	2650763450 ps
CPU time	78.4 seconds
Started	Aug 01 06:18:57 PM PDT 24
Finished	Aug 01 06:20:16 PM PDT 24
Peak memory	216868 kb
Host	smart-6aac9d42-eadb-4533-a182-0f1515a97c1a
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3073088703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3073088703
Directory	/workspace/43.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/43.usbdev_min_length_in_transaction.3542486517
Short name	T2
Test name
Test status
Simulation time	185038108 ps
CPU time	0.86 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	206976 kb
Host	smart-2b205fe7-fc32-4307-80f4-f245e9d1ed87
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3542486517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.3542486517
Directory	/workspace/43.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/43.usbdev_min_length_out_transaction.2228879067
Short name	T1905
Test name
Test status
Simulation time	155370667 ps
CPU time	0.9 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:04 PM PDT 24
Peak memory	206944 kb
Host	smart-c856be3e-0455-4d24-926e-1eaf70f10af6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22288 79067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2228879067
Directory	/workspace/43.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/43.usbdev_nak_trans.1838468140
Short name	T1917
Test name
Test status
Simulation time	220730497 ps
CPU time	0.95 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:19:05 PM PDT 24
Peak memory	206928 kb
Host	smart-b427387e-f0f7-4666-acbd-e533e671f217
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18384 68140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1838468140
Directory	/workspace/43.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/43.usbdev_out_iso.1203919618
Short name	T2363
Test name
Test status
Simulation time	180469821 ps
CPU time	0.9 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	206920 kb
Host	smart-c693621d-e489-4f8a-a5b2-3cb81c5e1d74
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12039 19618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1203919618
Directory	/workspace/43.usbdev_out_iso/latest

Test location	/workspace/coverage/default/43.usbdev_out_stall.2140652381
Short name	T692
Test name
Test status
Simulation time	195060577 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:01 PM PDT 24
Finished	Aug 01 06:19:03 PM PDT 24
Peak memory	206956 kb
Host	smart-54532b72-83f4-408f-ab36-b95dea50d9ce
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21406 52381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2140652381
Directory	/workspace/43.usbdev_out_stall/latest

Test location	/workspace/coverage/default/43.usbdev_out_trans_nak.455973684
Short name	T668
Test name
Test status
Simulation time	161269160 ps
CPU time	0.91 seconds
Started	Aug 01 06:18:58 PM PDT 24
Finished	Aug 01 06:18:59 PM PDT 24
Peak memory	206800 kb
Host	smart-cdc0b03b-e43d-4369-88dc-128bc1619dea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45597 3684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.455973684
Directory	/workspace/43.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/43.usbdev_pending_in_trans.57628351
Short name	T2710
Test name
Test status
Simulation time	155728833 ps
CPU time	0.89 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:19:05 PM PDT 24
Peak memory	206940 kb
Host	smart-599fe7d3-fc26-402b-b7f8-4ad38dcfe498
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57628 351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.57628351
Directory	/workspace/43.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/43.usbdev_phy_config_pinflip.2415369322
Short name	T523
Test name
Test status
Simulation time	278779536 ps
CPU time	1.05 seconds
Started	Aug 01 06:18:58 PM PDT 24
Finished	Aug 01 06:18:59 PM PDT 24
Peak memory	206936 kb
Host	smart-22a91575-63d5-41fd-af05-09a924d3cb5f
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2415369322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2415369322
Directory	/workspace/43.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3902635750
Short name	T2039
Test name
Test status
Simulation time	147969223 ps
CPU time	0.8 seconds
Started	Aug 01 06:19:00 PM PDT 24
Finished	Aug 01 06:19:01 PM PDT 24
Peak memory	206904 kb
Host	smart-63bbc53a-61de-4c3e-8426-0fb17fbe82fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39026 35750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3902635750
Directory	/workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/43.usbdev_phy_pins_sense.1494008977
Short name	T1924
Test name
Test status
Simulation time	58829417 ps
CPU time	0.71 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:04 PM PDT 24
Peak memory	206912 kb
Host	smart-f00ce4f1-3bd0-4351-8b0c-ed1a1e78e9b0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14940 08977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.1494008977
Directory	/workspace/43.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/43.usbdev_pkt_buffer.703928642
Short name	T2154
Test name
Test status
Simulation time	20700884467 ps
CPU time	50.62 seconds
Started	Aug 01 06:18:58 PM PDT 24
Finished	Aug 01 06:19:49 PM PDT 24
Peak memory	215416 kb
Host	smart-9e92c26c-cffa-4489-b969-23e2d4eb0cad
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70392 8642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.703928642
Directory	/workspace/43.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/43.usbdev_pkt_received.893885291
Short name	T2681
Test name
Test status
Simulation time	167731178 ps
CPU time	0.89 seconds
Started	Aug 01 06:19:02 PM PDT 24
Finished	Aug 01 06:19:03 PM PDT 24
Peak memory	206944 kb
Host	smart-04e546ca-8ad2-449d-bcac-5e1ccd9fcf64
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89388 5291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.893885291
Directory	/workspace/43.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/43.usbdev_pkt_sent.3528074482
Short name	T1825
Test name
Test status
Simulation time	160192174 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:07 PM PDT 24
Finished	Aug 01 06:19:08 PM PDT 24
Peak memory	206980 kb
Host	smart-5d7c3746-64c2-4e9f-b057-d2767b6ef43d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35280 74482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3528074482
Directory	/workspace/43.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/43.usbdev_random_length_in_transaction.2543506001
Short name	T2328
Test name
Test status
Simulation time	251764010 ps
CPU time	0.96 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	206928 kb
Host	smart-f136ebc7-c493-4949-b609-4de1f97e1a02
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25435 06001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2543506001
Directory	/workspace/43.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/43.usbdev_random_length_out_transaction.820652411
Short name	T1800
Test name
Test status
Simulation time	193436311 ps
CPU time	0.98 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:04 PM PDT 24
Peak memory	206948 kb
Host	smart-256a4839-0dfd-4735-8e42-932d5942f53c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82065 2411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.820652411
Directory	/workspace/43.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/43.usbdev_rx_crc_err.3126531154
Short name	T928
Test name
Test status
Simulation time	164023050 ps
CPU time	0.9 seconds
Started	Aug 01 06:19:02 PM PDT 24
Finished	Aug 01 06:19:03 PM PDT 24
Peak memory	206964 kb
Host	smart-1e254c28-2556-4e04-8030-e2c79fe27a79
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31265 31154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3126531154
Directory	/workspace/43.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/43.usbdev_rx_full.1050621148
Short name	T2096
Test name
Test status
Simulation time	301387328 ps
CPU time	1.13 seconds
Started	Aug 01 06:19:01 PM PDT 24
Finished	Aug 01 06:19:02 PM PDT 24
Peak memory	206944 kb
Host	smart-a1e81c31-2ba5-4ea3-ab50-d9560a8665a4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10506 21148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.1050621148
Directory	/workspace/43.usbdev_rx_full/latest

Test location	/workspace/coverage/default/43.usbdev_setup_stage.2392453319
Short name	T1186
Test name
Test status
Simulation time	160228682 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	206740 kb
Host	smart-e3ca4005-5722-4b12-8bfd-ded6ab2375c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23924 53319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2392453319
Directory	/workspace/43.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/43.usbdev_setup_trans_ignored.947509827
Short name	T2887
Test name
Test status
Simulation time	170811005 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:02 PM PDT 24
Finished	Aug 01 06:19:03 PM PDT 24
Peak memory	206956 kb
Host	smart-d38417fe-776a-4244-87aa-1fb8efd7b694
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94750 9827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.947509827
Directory	/workspace/43.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/43.usbdev_smoke.73654236
Short name	T2546
Test name
Test status
Simulation time	252276683 ps
CPU time	1.06 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:05 PM PDT 24
Peak memory	206948 kb
Host	smart-0f128a80-87f7-4aca-8751-0c00233243aa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73654 236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.73654236
Directory	/workspace/43.usbdev_smoke/latest

Test location	/workspace/coverage/default/43.usbdev_spurious_pids_ignored.3374000501
Short name	T461
Test name
Test status
Simulation time	2183888143 ps
CPU time	21.76 seconds
Started	Aug 01 06:19:06 PM PDT 24
Finished	Aug 01 06:19:28 PM PDT 24
Peak memory	223216 kb
Host	smart-b5a7bfe2-a11b-4dac-893d-ed273b88b2f7
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3374000501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.3374000501
Directory	/workspace/43.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/43.usbdev_stall_priority_over_nak.2977830701
Short name	T607
Test name
Test status
Simulation time	211065653 ps
CPU time	0.97 seconds
Started	Aug 01 06:19:06 PM PDT 24
Finished	Aug 01 06:19:07 PM PDT 24
Peak memory	206968 kb
Host	smart-6b6126d1-9690-4da1-9ebe-2b7c30de1e59
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29778 30701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2977830701
Directory	/workspace/43.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/43.usbdev_stall_trans.384833853
Short name	T2129
Test name
Test status
Simulation time	174532371 ps
CPU time	0.84 seconds
Started	Aug 01 06:18:58 PM PDT 24
Finished	Aug 01 06:18:59 PM PDT 24
Peak memory	206952 kb
Host	smart-6872d641-9397-414c-94fc-24a06fbd05b1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38483 3853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.384833853
Directory	/workspace/43.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/43.usbdev_stream_len_max.407443912
Short name	T1654
Test name
Test status
Simulation time	506444148 ps
CPU time	1.46 seconds
Started	Aug 01 06:19:06 PM PDT 24
Finished	Aug 01 06:19:08 PM PDT 24
Peak memory	206936 kb
Host	smart-846b4634-8ef4-4c5a-bc8c-edc54826a1b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40744 3912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.407443912
Directory	/workspace/43.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/43.usbdev_streaming_out.785305061
Short name	T1938
Test name
Test status
Simulation time	3099660593 ps
CPU time	92.09 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:20:37 PM PDT 24
Peak memory	216800 kb
Host	smart-e57bf4ad-007b-490f-8df4-f11bb801500f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78530 5061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.785305061
Directory	/workspace/43.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.2754395217
Short name	T1138
Test name
Test status
Simulation time	2003196961 ps
CPU time	47.36 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:50 PM PDT 24
Peak memory	207164 kb
Host	smart-c54d9ab3-7245-4871-bb4e-9d2c1a2476ba
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754395217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos t_handshake.2754395217
Directory	/workspace/43.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/44.usbdev_alert_test.312069454
Short name	T1410
Test name
Test status
Simulation time	50751668 ps
CPU time	0.71 seconds
Started	Aug 01 06:19:10 PM PDT 24
Finished	Aug 01 06:19:11 PM PDT 24
Peak memory	206984 kb
Host	smart-489c3832-4778-48ae-9d5c-4062b09ffe62
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=312069454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.312069454
Directory	/workspace/44.usbdev_alert_test/latest

Test location	/workspace/coverage/default/44.usbdev_av_buffer.1995146071
Short name	T721
Test name
Test status
Simulation time	157965842 ps
CPU time	0.86 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:19:05 PM PDT 24
Peak memory	206972 kb
Host	smart-e0d3df91-83b9-4860-9db2-34b3629f97e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19951 46071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1995146071
Directory	/workspace/44.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/44.usbdev_bitstuff_err.3533326130
Short name	T1904
Test name
Test status
Simulation time	222918984 ps
CPU time	0.93 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	206928 kb
Host	smart-fef843e4-010c-43e5-8b66-8d381e66d707
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35333 26130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3533326130
Directory	/workspace/44.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/44.usbdev_data_toggle_clear.817454173
Short name	T690
Test name
Test status
Simulation time	471202456 ps
CPU time	1.6 seconds
Started	Aug 01 06:19:07 PM PDT 24
Finished	Aug 01 06:19:09 PM PDT 24
Peak memory	206968 kb
Host	smart-beba2c96-17ea-486b-9d8f-754bf54c176a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81745 4173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.817454173
Directory	/workspace/44.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/44.usbdev_data_toggle_restore.348639570
Short name	T1815
Test name
Test status
Simulation time	729931962 ps
CPU time	1.98 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:19:07 PM PDT 24
Peak memory	207092 kb
Host	smart-2886e091-f21d-4eed-90ce-3ad6269f89a9
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=348639570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.348639570
Directory	/workspace/44.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/44.usbdev_device_address.1877570656
Short name	T1405
Test name
Test status
Simulation time	39262614668 ps
CPU time	62.51 seconds
Started	Aug 01 06:19:07 PM PDT 24
Finished	Aug 01 06:20:10 PM PDT 24
Peak memory	207184 kb
Host	smart-302521e4-99bd-4c25-92c3-7e885da76d66
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18775 70656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.1877570656
Directory	/workspace/44.usbdev_device_address/latest

Test location	/workspace/coverage/default/44.usbdev_device_timeout.690202830
Short name	T2092
Test name
Test status
Simulation time	1053136285 ps
CPU time	23.63 seconds
Started	Aug 01 06:18:58 PM PDT 24
Finished	Aug 01 06:19:22 PM PDT 24
Peak memory	207088 kb
Host	smart-8b2c2152-dbea-4156-8c9a-9d0af57c8df8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690202830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.690202830
Directory	/workspace/44.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/44.usbdev_disable_endpoint.1204409340
Short name	T2085
Test name
Test status
Simulation time	1267339838 ps
CPU time	2.42 seconds
Started	Aug 01 06:19:06 PM PDT 24
Finished	Aug 01 06:19:09 PM PDT 24
Peak memory	206880 kb
Host	smart-73b5090e-671b-4506-bd7f-6b6b7bdd1636
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12044 09340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.1204409340
Directory	/workspace/44.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/44.usbdev_disconnected.418192158
Short name	T2738
Test name
Test status
Simulation time	198686372 ps
CPU time	0.85 seconds
Started	Aug 01 06:18:58 PM PDT 24
Finished	Aug 01 06:18:59 PM PDT 24
Peak memory	206888 kb
Host	smart-8bbfe928-9ec8-4067-9dcd-a0a8d182f786
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41819 2158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.418192158
Directory	/workspace/44.usbdev_disconnected/latest

Test location	/workspace/coverage/default/44.usbdev_enable.2340106352
Short name	T2379
Test name
Test status
Simulation time	41829990 ps
CPU time	0.73 seconds
Started	Aug 01 06:18:59 PM PDT 24
Finished	Aug 01 06:19:00 PM PDT 24
Peak memory	207152 kb
Host	smart-9e291940-7043-4fe9-bdd3-2e99edba2189
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23401 06352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2340106352
Directory	/workspace/44.usbdev_enable/latest

Test location	/workspace/coverage/default/44.usbdev_endpoint_access.4129862325
Short name	T546
Test name
Test status
Simulation time	889114523 ps
CPU time	2.42 seconds
Started	Aug 01 06:19:06 PM PDT 24
Finished	Aug 01 06:19:08 PM PDT 24
Peak memory	207076 kb
Host	smart-70765bfc-f038-4e02-907c-9dbbe0926009
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41298 62325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.4129862325
Directory	/workspace/44.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/44.usbdev_fifo_rst.212086559
Short name	T1548
Test name
Test status
Simulation time	225916105 ps
CPU time	1.49 seconds
Started	Aug 01 06:19:07 PM PDT 24
Finished	Aug 01 06:19:09 PM PDT 24
Peak memory	207088 kb
Host	smart-4139f9bf-6a13-4d4c-bfca-a3942a51ecd2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21208 6559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.212086559
Directory	/workspace/44.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/44.usbdev_in_iso.3885975193
Short name	T2753
Test name
Test status
Simulation time	164260621 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	206928 kb
Host	smart-ea76b488-9d5e-491e-b58f-258e7236a3d6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3885975193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.3885975193
Directory	/workspace/44.usbdev_in_iso/latest

Test location	/workspace/coverage/default/44.usbdev_in_stall.1524115672
Short name	T78
Test name
Test status
Simulation time	142882614 ps
CPU time	0.81 seconds
Started	Aug 01 06:19:03 PM PDT 24
Finished	Aug 01 06:19:04 PM PDT 24
Peak memory	206928 kb
Host	smart-91b14eae-c36b-4415-bd71-0ff84f624454
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15241 15672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.1524115672
Directory	/workspace/44.usbdev_in_stall/latest

Test location	/workspace/coverage/default/44.usbdev_in_trans.4008997788
Short name	T1606
Test name
Test status
Simulation time	185312243 ps
CPU time	0.97 seconds
Started	Aug 01 06:19:02 PM PDT 24
Finished	Aug 01 06:19:03 PM PDT 24
Peak memory	206968 kb
Host	smart-5080a80f-f403-4980-af3a-662994ea8fec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40089 97788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.4008997788
Directory	/workspace/44.usbdev_in_trans/latest

Test location	/workspace/coverage/default/44.usbdev_invalid_sync.1610578873
Short name	T2854
Test name
Test status
Simulation time	4560039039 ps
CPU time	134.19 seconds
Started	Aug 01 06:19:00 PM PDT 24
Finished	Aug 01 06:21:14 PM PDT 24
Peak memory	217016 kb
Host	smart-652bdde8-7265-4cd8-90c3-271d3ab1e631
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1610578873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.1610578873
Directory	/workspace/44.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/44.usbdev_iso_retraction.1388123789
Short name	T1421
Test name
Test status
Simulation time	5954947962 ps
CPU time	37.76 seconds
Started	Aug 01 06:19:01 PM PDT 24
Finished	Aug 01 06:19:39 PM PDT 24
Peak memory	207120 kb
Host	smart-8929b343-fa0f-4b1e-ae01-97b5d52f62f8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1388123789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.1388123789
Directory	/workspace/44.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/44.usbdev_link_in_err.2743889539
Short name	T1411
Test name
Test status
Simulation time	160633166 ps
CPU time	0.87 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:19:05 PM PDT 24
Peak memory	206948 kb
Host	smart-6b9f6731-6ed5-4225-b5ad-324f034e938f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27438 89539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2743889539
Directory	/workspace/44.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/44.usbdev_link_suspend.2244281484
Short name	T92
Test name
Test status
Simulation time	8785988850 ps
CPU time	11.04 seconds
Started	Aug 01 06:19:02 PM PDT 24
Finished	Aug 01 06:19:13 PM PDT 24
Peak memory	207140 kb
Host	smart-676d076c-abe2-428b-ac74-ac96016b9aa3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22442 81484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2244281484
Directory	/workspace/44.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/44.usbdev_low_speed_traffic.4225368302
Short name	T1538
Test name
Test status
Simulation time	3165050304 ps
CPU time	24.37 seconds
Started	Aug 01 06:19:00 PM PDT 24
Finished	Aug 01 06:19:24 PM PDT 24
Peak memory	223516 kb
Host	smart-53d3bb8c-b3d3-41a9-ad73-1a56ed6c8506
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42253 68302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.4225368302
Directory	/workspace/44.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3444590271
Short name	T1841
Test name
Test status
Simulation time	1413015265 ps
CPU time	38.3 seconds
Started	Aug 01 06:19:06 PM PDT 24
Finished	Aug 01 06:19:44 PM PDT 24
Peak memory	215308 kb
Host	smart-850fb6f5-1c94-47ca-9d57-c0f21686d150
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3444590271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3444590271
Directory	/workspace/44.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/44.usbdev_max_length_in_transaction.1065187438
Short name	T2239
Test name
Test status
Simulation time	241254653 ps
CPU time	1.02 seconds
Started	Aug 01 06:19:07 PM PDT 24
Finished	Aug 01 06:19:08 PM PDT 24
Peak memory	206964 kb
Host	smart-44df9121-4d40-462c-8325-e9d4f96f1907
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1065187438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1065187438
Directory	/workspace/44.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/44.usbdev_max_length_out_transaction.898568556
Short name	T956
Test name
Test status
Simulation time	199290116 ps
CPU time	0.95 seconds
Started	Aug 01 06:19:04 PM PDT 24
Finished	Aug 01 06:19:05 PM PDT 24
Peak memory	206924 kb
Host	smart-b97b7e1b-7c6d-43b0-9870-182193092960
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89856 8556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.898568556
Directory	/workspace/44.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/44.usbdev_min_inter_pkt_delay.4289348985
Short name	T2329
Test name
Test status
Simulation time	2090193629 ps
CPU time	56.14 seconds
Started	Aug 01 06:19:06 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	223500 kb
Host	smart-21be103a-7dfe-460c-a4ba-daa788117942
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=4289348985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.4289348985
Directory	/workspace/44.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/44.usbdev_min_length_in_transaction.1155760650
Short name	T2385
Test name
Test status
Simulation time	159950621 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:06 PM PDT 24
Finished	Aug 01 06:19:07 PM PDT 24
Peak memory	206708 kb
Host	smart-cd92f7e9-cb00-4169-b865-f1f8dcee6237
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1155760650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1155760650
Directory	/workspace/44.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/44.usbdev_min_length_out_transaction.4004573128
Short name	T636
Test name
Test status
Simulation time	140044593 ps
CPU time	0.83 seconds
Started	Aug 01 06:18:59 PM PDT 24
Finished	Aug 01 06:19:00 PM PDT 24
Peak memory	206928 kb
Host	smart-83359b09-26a7-49af-b748-a296d38f8b49
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40045 73128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.4004573128
Directory	/workspace/44.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/44.usbdev_nak_trans.3385305508
Short name	T192
Test name
Test status
Simulation time	236507209 ps
CPU time	0.96 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:07 PM PDT 24
Peak memory	206960 kb
Host	smart-f0ab2a36-7c15-4907-aab7-4bb7d26f9c8d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33853 05508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3385305508
Directory	/workspace/44.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/44.usbdev_out_iso.1119744898
Short name	T709
Test name
Test status
Simulation time	175481747 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:06 PM PDT 24
Peak memory	206792 kb
Host	smart-a9a929cf-332e-4559-962b-aeab7efc99da
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11197 44898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1119744898
Directory	/workspace/44.usbdev_out_iso/latest

Test location	/workspace/coverage/default/44.usbdev_out_stall.1086392750
Short name	T831
Test name
Test status
Simulation time	202148398 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:19 PM PDT 24
Finished	Aug 01 06:19:20 PM PDT 24
Peak memory	206972 kb
Host	smart-77621df2-0899-49c4-b265-c8c985368cf7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10863 92750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1086392750
Directory	/workspace/44.usbdev_out_stall/latest

Test location	/workspace/coverage/default/44.usbdev_out_trans_nak.2698757951
Short name	T943
Test name
Test status
Simulation time	183204664 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:10 PM PDT 24
Finished	Aug 01 06:19:11 PM PDT 24
Peak memory	206952 kb
Host	smart-6ced32b8-af4f-401a-bee9-e8d6d256cee4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26987 57951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.2698757951
Directory	/workspace/44.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/44.usbdev_pending_in_trans.1382848406
Short name	T2781
Test name
Test status
Simulation time	172705974 ps
CPU time	0.87 seconds
Started	Aug 01 06:19:12 PM PDT 24
Finished	Aug 01 06:19:14 PM PDT 24
Peak memory	206928 kb
Host	smart-d3a11578-1518-4b6e-bf6d-5271a72f0a15
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13828 48406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.1382848406
Directory	/workspace/44.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/44.usbdev_phy_config_pinflip.202258588
Short name	T2641
Test name
Test status
Simulation time	247174485 ps
CPU time	1.04 seconds
Started	Aug 01 06:19:11 PM PDT 24
Finished	Aug 01 06:19:12 PM PDT 24
Peak memory	206972 kb
Host	smart-09d04e5d-6ea4-464d-b3c8-9c4e4482becd
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=202258588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.202258588
Directory	/workspace/44.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1884207912
Short name	T1356
Test name
Test status
Simulation time	139912915 ps
CPU time	0.83 seconds
Started	Aug 01 06:19:09 PM PDT 24
Finished	Aug 01 06:19:10 PM PDT 24
Peak memory	206948 kb
Host	smart-3d9f6dd5-e4b2-4728-b9ca-ae190979309e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18842 07912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1884207912
Directory	/workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/44.usbdev_phy_pins_sense.3500885595
Short name	T2699
Test name
Test status
Simulation time	69378955 ps
CPU time	0.73 seconds
Started	Aug 01 06:19:14 PM PDT 24
Finished	Aug 01 06:19:15 PM PDT 24
Peak memory	206896 kb
Host	smart-88d53212-c19a-48e6-a12a-cfa8892d246e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35008 85595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3500885595
Directory	/workspace/44.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/44.usbdev_pkt_buffer.3937558501
Short name	T269
Test name
Test status
Simulation time	7179578501 ps
CPU time	19.04 seconds
Started	Aug 01 06:19:18 PM PDT 24
Finished	Aug 01 06:19:37 PM PDT 24
Peak memory	215424 kb
Host	smart-2a197273-49e5-45ff-85cb-0b262ff1be4b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39375 58501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3937558501
Directory	/workspace/44.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/44.usbdev_pkt_received.3287710401
Short name	T1761
Test name
Test status
Simulation time	152949240 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:16 PM PDT 24
Finished	Aug 01 06:19:17 PM PDT 24
Peak memory	206948 kb
Host	smart-3645e3d9-53e3-4043-af9a-109ae77e89da
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32877 10401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3287710401
Directory	/workspace/44.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/44.usbdev_pkt_sent.1488543609
Short name	T1929
Test name
Test status
Simulation time	214447642 ps
CPU time	0.96 seconds
Started	Aug 01 06:19:11 PM PDT 24
Finished	Aug 01 06:19:12 PM PDT 24
Peak memory	206896 kb
Host	smart-895cf920-4ebd-4fe0-aab5-c316f26d5b49
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14885 43609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1488543609
Directory	/workspace/44.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/44.usbdev_random_length_in_transaction.1576862837
Short name	T2253
Test name
Test status
Simulation time	228660250 ps
CPU time	0.98 seconds
Started	Aug 01 06:19:12 PM PDT 24
Finished	Aug 01 06:19:13 PM PDT 24
Peak memory	206956 kb
Host	smart-ed850104-8093-4c7b-9147-d00e3f6eb860
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15768 62837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.1576862837
Directory	/workspace/44.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/44.usbdev_random_length_out_transaction.984651185
Short name	T1289
Test name
Test status
Simulation time	173439681 ps
CPU time	0.9 seconds
Started	Aug 01 06:19:11 PM PDT 24
Finished	Aug 01 06:19:12 PM PDT 24
Peak memory	206916 kb
Host	smart-9c940296-f47a-4e40-af57-23ba85f0f687
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98465 1185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.984651185
Directory	/workspace/44.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/44.usbdev_rx_crc_err.2497618015
Short name	T1000
Test name
Test status
Simulation time	197223408 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:11 PM PDT 24
Finished	Aug 01 06:19:12 PM PDT 24
Peak memory	206920 kb
Host	smart-c0b7bc59-844b-4d7a-a8ec-0c273237ab45
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24976 18015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2497618015
Directory	/workspace/44.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/44.usbdev_rx_full.161880697
Short name	T276
Test name
Test status
Simulation time	301553642 ps
CPU time	1.12 seconds
Started	Aug 01 06:19:10 PM PDT 24
Finished	Aug 01 06:19:11 PM PDT 24
Peak memory	206944 kb
Host	smart-3c841be8-6ea1-4989-9067-58fec41a0d24
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16188 0697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.161880697
Directory	/workspace/44.usbdev_rx_full/latest

Test location	/workspace/coverage/default/44.usbdev_setup_stage.2867521267
Short name	T2098
Test name
Test status
Simulation time	153758040 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206860 kb
Host	smart-24c9859c-016d-48ad-a180-3aae39c87662
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28675 21267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2867521267
Directory	/workspace/44.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/44.usbdev_setup_trans_ignored.1693423700
Short name	T2112
Test name
Test status
Simulation time	167384388 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:18 PM PDT 24
Finished	Aug 01 06:19:19 PM PDT 24
Peak memory	206908 kb
Host	smart-e879d9d3-d316-4f59-97c9-4f5fb27ac899
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16934 23700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1693423700
Directory	/workspace/44.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/44.usbdev_smoke.1268388374
Short name	T516
Test name
Test status
Simulation time	217990905 ps
CPU time	1.06 seconds
Started	Aug 01 06:19:22 PM PDT 24
Finished	Aug 01 06:19:23 PM PDT 24
Peak memory	207004 kb
Host	smart-716dc7fa-3420-4790-a5f8-d1124db66e6b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12683 88374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.1268388374
Directory	/workspace/44.usbdev_smoke/latest

Test location	/workspace/coverage/default/44.usbdev_spurious_pids_ignored.1258637396
Short name	T2105
Test name
Test status
Simulation time	3136914977 ps
CPU time	88.51 seconds
Started	Aug 01 06:19:12 PM PDT 24
Finished	Aug 01 06:20:40 PM PDT 24
Peak memory	223752 kb
Host	smart-d5a3e7f4-8cc8-4c38-b667-dd666667202c
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1258637396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1258637396
Directory	/workspace/44.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/44.usbdev_stall_priority_over_nak.3535374700
Short name	T2430
Test name
Test status
Simulation time	171116442 ps
CPU time	0.99 seconds
Started	Aug 01 06:19:13 PM PDT 24
Finished	Aug 01 06:19:14 PM PDT 24
Peak memory	206916 kb
Host	smart-69524f2e-9b65-4af6-b40d-cef91c95f4ff
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35353 74700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3535374700
Directory	/workspace/44.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/44.usbdev_stall_trans.2957048571
Short name	T1896
Test name
Test status
Simulation time	170027976 ps
CPU time	0.97 seconds
Started	Aug 01 06:19:16 PM PDT 24
Finished	Aug 01 06:19:18 PM PDT 24
Peak memory	206996 kb
Host	smart-ad9ee7cb-56b3-4d45-993e-aff00d5dc7be
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29570 48571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2957048571
Directory	/workspace/44.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/44.usbdev_stream_len_max.1289165632
Short name	T2421
Test name
Test status
Simulation time	1253291762 ps
CPU time	3.07 seconds
Started	Aug 01 06:19:12 PM PDT 24
Finished	Aug 01 06:19:15 PM PDT 24
Peak memory	207108 kb
Host	smart-f4c3a3ab-3c3a-4e01-9db0-979a4f78d5ca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12891 65632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1289165632
Directory	/workspace/44.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/44.usbdev_streaming_out.349373044
Short name	T627
Test name
Test status
Simulation time	3600277901 ps
CPU time	27.32 seconds
Started	Aug 01 06:19:17 PM PDT 24
Finished	Aug 01 06:19:44 PM PDT 24
Peak memory	215460 kb
Host	smart-ab90aeff-273f-467a-8c38-1006201ccf84
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34937 3044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.349373044
Directory	/workspace/44.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.2644258409
Short name	T1589
Test name
Test status
Simulation time	2521809016 ps
CPU time	21.29 seconds
Started	Aug 01 06:19:05 PM PDT 24
Finished	Aug 01 06:19:26 PM PDT 24
Peak memory	207212 kb
Host	smart-8bc43d64-31c0-49c9-9ad4-84c421c2b360
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644258409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos t_handshake.2644258409
Directory	/workspace/44.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/45.usbdev_alert_test.565496521
Short name	T1727
Test name
Test status
Simulation time	40348254 ps
CPU time	0.68 seconds
Started	Aug 01 06:19:23 PM PDT 24
Finished	Aug 01 06:19:24 PM PDT 24
Peak memory	206984 kb
Host	smart-cd4e4743-a8fc-49a1-9f09-f53f8990539d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=565496521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.565496521
Directory	/workspace/45.usbdev_alert_test/latest

Test location	/workspace/coverage/default/45.usbdev_av_buffer.1257533601
Short name	T735
Test name
Test status
Simulation time	163280030 ps
CPU time	0.83 seconds
Started	Aug 01 06:19:11 PM PDT 24
Finished	Aug 01 06:19:12 PM PDT 24
Peak memory	206964 kb
Host	smart-85ea8e89-679a-4db0-9448-5ad7642b6864
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12575 33601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1257533601
Directory	/workspace/45.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/45.usbdev_bitstuff_err.336514497
Short name	T1776
Test name
Test status
Simulation time	215314967 ps
CPU time	0.97 seconds
Started	Aug 01 06:19:17 PM PDT 24
Finished	Aug 01 06:19:19 PM PDT 24
Peak memory	206964 kb
Host	smart-524b81fb-49e9-4f8d-aee9-be5fb2176682
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33651 4497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.336514497
Directory	/workspace/45.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/45.usbdev_data_toggle_clear.3277056356
Short name	T2507
Test name
Test status
Simulation time	176163054 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:11 PM PDT 24
Finished	Aug 01 06:19:12 PM PDT 24
Peak memory	206992 kb
Host	smart-a53a4466-3fe1-42a7-b58a-5f0b8ffe49bc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32770 56356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.3277056356
Directory	/workspace/45.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/45.usbdev_data_toggle_restore.58645530
Short name	T1121
Test name
Test status
Simulation time	552790913 ps
CPU time	1.58 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206944 kb
Host	smart-fc9cce87-c36f-4c1f-9c31-0487cd057d5a
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=58645530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.58645530
Directory	/workspace/45.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/45.usbdev_device_address.1311520987
Short name	T2586
Test name
Test status
Simulation time	50923020844 ps
CPU time	82.84 seconds
Started	Aug 01 06:19:12 PM PDT 24
Finished	Aug 01 06:20:35 PM PDT 24
Peak memory	207196 kb
Host	smart-8f32f699-7371-40ab-ad5b-ef5ecb2a8e9a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13115 20987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.1311520987
Directory	/workspace/45.usbdev_device_address/latest

Test location	/workspace/coverage/default/45.usbdev_device_timeout.3969142502
Short name	T851
Test name
Test status
Simulation time	4978093094 ps
CPU time	31.79 seconds
Started	Aug 01 06:19:11 PM PDT 24
Finished	Aug 01 06:19:43 PM PDT 24
Peak memory	207068 kb
Host	smart-a4ec600a-b4e6-44a9-8f21-6d4c9a49dba4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969142502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.3969142502
Directory	/workspace/45.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/45.usbdev_disable_endpoint.1751771138
Short name	T942
Test name
Test status
Simulation time	842375365 ps
CPU time	1.82 seconds
Started	Aug 01 06:19:14 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206896 kb
Host	smart-86ad5b86-a003-40e3-ac2a-e2a37b738e59
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17517 71138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.1751771138
Directory	/workspace/45.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/45.usbdev_disconnected.2352955768
Short name	T2073
Test name
Test status
Simulation time	176897298 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:18 PM PDT 24
Finished	Aug 01 06:19:19 PM PDT 24
Peak memory	206908 kb
Host	smart-62a909df-da04-4602-834b-49572821196a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23529 55768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2352955768
Directory	/workspace/45.usbdev_disconnected/latest

Test location	/workspace/coverage/default/45.usbdev_enable.4264631950
Short name	T2146
Test name
Test status
Simulation time	32594375 ps
CPU time	0.67 seconds
Started	Aug 01 06:19:10 PM PDT 24
Finished	Aug 01 06:19:10 PM PDT 24
Peak memory	206952 kb
Host	smart-8720063f-2d8c-4723-a6d3-3f19e6c53b9b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42646 31950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.4264631950
Directory	/workspace/45.usbdev_enable/latest

Test location	/workspace/coverage/default/45.usbdev_endpoint_access.1137258587
Short name	T2663
Test name
Test status
Simulation time	985578623 ps
CPU time	2.59 seconds
Started	Aug 01 06:19:12 PM PDT 24
Finished	Aug 01 06:19:15 PM PDT 24
Peak memory	207180 kb
Host	smart-52f4a4de-51a2-403b-99ed-c535ef27786f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11372 58587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1137258587
Directory	/workspace/45.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/45.usbdev_endpoint_types.108157076
Short name	T403
Test name
Test status
Simulation time	258948873 ps
CPU time	1.02 seconds
Started	Aug 01 06:19:12 PM PDT 24
Finished	Aug 01 06:19:13 PM PDT 24
Peak memory	206916 kb
Host	smart-741c8ef0-1dab-4e79-a8a3-47a6b8f37cac
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=108157076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.108157076
Directory	/workspace/45.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/45.usbdev_fifo_rst.2720245881
Short name	T2719
Test name
Test status
Simulation time	398343307 ps
CPU time	2.96 seconds
Started	Aug 01 06:19:13 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	207004 kb
Host	smart-26ea0f05-f09e-4f81-8cd4-53a7fd00d5d6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202 45881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2720245881
Directory	/workspace/45.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/45.usbdev_in_iso.91679913
Short name	T961
Test name
Test status
Simulation time	206284813 ps
CPU time	1.11 seconds
Started	Aug 01 06:19:12 PM PDT 24
Finished	Aug 01 06:19:13 PM PDT 24
Peak memory	215312 kb
Host	smart-05221d1a-e39a-4c5d-9c6d-69c6f16c0a6e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=91679913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.91679913
Directory	/workspace/45.usbdev_in_iso/latest

Test location	/workspace/coverage/default/45.usbdev_in_stall.2894248732
Short name	T1063
Test name
Test status
Simulation time	134925152 ps
CPU time	0.81 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206924 kb
Host	smart-68af8508-9003-479e-a020-fd9a45298318
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942 48732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.2894248732
Directory	/workspace/45.usbdev_in_stall/latest

Test location	/workspace/coverage/default/45.usbdev_in_trans.3434445225
Short name	T726
Test name
Test status
Simulation time	249661466 ps
CPU time	1.06 seconds
Started	Aug 01 06:19:16 PM PDT 24
Finished	Aug 01 06:19:17 PM PDT 24
Peak memory	206964 kb
Host	smart-bb3e8dfa-5a3e-4675-9a9d-e72f7fdd6ee9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34344 45225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3434445225
Directory	/workspace/45.usbdev_in_trans/latest

Test location	/workspace/coverage/default/45.usbdev_invalid_sync.1568796326
Short name	T1787
Test name
Test status
Simulation time	3455629692 ps
CPU time	34.96 seconds
Started	Aug 01 06:19:10 PM PDT 24
Finished	Aug 01 06:19:45 PM PDT 24
Peak memory	222560 kb
Host	smart-12e4313b-e040-45f1-ad00-cf7f15b4610f
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1568796326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.1568796326
Directory	/workspace/45.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/45.usbdev_iso_retraction.3632663913
Short name	T921
Test name
Test status
Simulation time	11771474366 ps
CPU time	136.64 seconds
Started	Aug 01 06:19:19 PM PDT 24
Finished	Aug 01 06:21:36 PM PDT 24
Peak memory	207148 kb
Host	smart-a88a355b-60d7-4e75-ba5e-73c53b9c6aa6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3632663913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.3632663913
Directory	/workspace/45.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/45.usbdev_link_in_err.1324740930
Short name	T2891
Test name
Test status
Simulation time	161724484 ps
CPU time	0.87 seconds
Started	Aug 01 06:19:16 PM PDT 24
Finished	Aug 01 06:19:22 PM PDT 24
Peak memory	206956 kb
Host	smart-2d5e000d-a847-470d-9bb9-531188083b54
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13247 40930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1324740930
Directory	/workspace/45.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/45.usbdev_low_speed_traffic.1249236
Short name	T1376
Test name
Test status
Simulation time	2838655410 ps
CPU time	78.1 seconds
Started	Aug 01 06:19:19 PM PDT 24
Finished	Aug 01 06:20:37 PM PDT 24
Peak memory	215408 kb
Host	smart-4c758d93-d001-412b-a1ee-1acab3c76cc9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12492 36 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.1249236
Directory	/workspace/45.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/45.usbdev_max_inter_pkt_delay.275975454
Short name	T856
Test name
Test status
Simulation time	2958711660 ps
CPU time	29.39 seconds
Started	Aug 01 06:19:13 PM PDT 24
Finished	Aug 01 06:19:43 PM PDT 24
Peak memory	216944 kb
Host	smart-e216f5f2-d104-42cb-a4f4-c8e7e6eefa0e
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=275975454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.275975454
Directory	/workspace/45.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/45.usbdev_max_length_in_transaction.3346538317
Short name	T1574
Test name
Test status
Simulation time	246925797 ps
CPU time	1.08 seconds
Started	Aug 01 06:19:18 PM PDT 24
Finished	Aug 01 06:19:20 PM PDT 24
Peak memory	206956 kb
Host	smart-d9196c65-7eeb-438d-8dec-494550f1e31b
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3346538317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3346538317
Directory	/workspace/45.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/45.usbdev_max_length_out_transaction.1250660710
Short name	T1394
Test name
Test status
Simulation time	187309665 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206904 kb
Host	smart-4f285355-5dea-477a-9d89-5ba68d711e17
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12506 60710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1250660710
Directory	/workspace/45.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/45.usbdev_min_inter_pkt_delay.22041005
Short name	T674
Test name
Test status
Simulation time	2511824352 ps
CPU time	18.8 seconds
Started	Aug 01 06:19:14 PM PDT 24
Finished	Aug 01 06:19:34 PM PDT 24
Peak memory	215332 kb
Host	smart-27eb77ca-3eaa-4906-b9c0-ca58d1980c28
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=22041005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.22041005
Directory	/workspace/45.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/45.usbdev_min_length_in_transaction.2503683078
Short name	T2347
Test name
Test status
Simulation time	179378541 ps
CPU time	0.89 seconds
Started	Aug 01 06:19:14 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206864 kb
Host	smart-090b6b50-941c-4dea-a918-810c746de421
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2503683078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.2503683078
Directory	/workspace/45.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/45.usbdev_min_length_out_transaction.1411873125
Short name	T1332
Test name
Test status
Simulation time	179578692 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206980 kb
Host	smart-5d6e979b-6c68-4e40-a39f-dd6052c881b4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14118 73125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.1411873125
Directory	/workspace/45.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/45.usbdev_nak_trans.1653677145
Short name	T178
Test name
Test status
Simulation time	281973281 ps
CPU time	1.13 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206972 kb
Host	smart-edf7eeac-cb8f-4b2f-bec8-d96ce063ff75
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16536 77145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1653677145
Directory	/workspace/45.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/45.usbdev_out_iso.706026129
Short name	T2647
Test name
Test status
Simulation time	242575845 ps
CPU time	1.02 seconds
Started	Aug 01 06:19:14 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206896 kb
Host	smart-730d4354-4eaf-4996-bff9-fb0c1c684ed3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70602 6129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.706026129
Directory	/workspace/45.usbdev_out_iso/latest

Test location	/workspace/coverage/default/45.usbdev_out_stall.115612634
Short name	T492
Test name
Test status
Simulation time	169289279 ps
CPU time	0.87 seconds
Started	Aug 01 06:19:18 PM PDT 24
Finished	Aug 01 06:19:20 PM PDT 24
Peak memory	206912 kb
Host	smart-9cf5686b-6744-4086-b18c-172ece92a40d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11561 2634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.115612634
Directory	/workspace/45.usbdev_out_stall/latest

Test location	/workspace/coverage/default/45.usbdev_out_trans_nak.1980789788
Short name	T162
Test name
Test status
Simulation time	170862782 ps
CPU time	0.87 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206948 kb
Host	smart-001f7424-0c79-470f-a2f2-4cdc1b149ab7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19807 89788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1980789788
Directory	/workspace/45.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/45.usbdev_pending_in_trans.660100891
Short name	T1989
Test name
Test status
Simulation time	161387993 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206972 kb
Host	smart-450edb57-57df-4f45-a91b-d2b7cd419334
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66010 0891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.660100891
Directory	/workspace/45.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/45.usbdev_phy_config_pinflip.3322288279
Short name	T631
Test name
Test status
Simulation time	254850982 ps
CPU time	1.06 seconds
Started	Aug 01 06:19:17 PM PDT 24
Finished	Aug 01 06:19:18 PM PDT 24
Peak memory	206956 kb
Host	smart-79f22b3e-713d-476c-affa-e921a1f78c96
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3322288279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.3322288279
Directory	/workspace/45.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3332086579
Short name	T1006
Test name
Test status
Simulation time	142457736 ps
CPU time	0.78 seconds
Started	Aug 01 06:19:24 PM PDT 24
Finished	Aug 01 06:19:25 PM PDT 24
Peak memory	206920 kb
Host	smart-e858e8cf-2a74-4607-924a-92918552e6f5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33320 86579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3332086579
Directory	/workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/45.usbdev_phy_pins_sense.1895993065
Short name	T2633
Test name
Test status
Simulation time	41074623 ps
CPU time	0.68 seconds
Started	Aug 01 06:19:19 PM PDT 24
Finished	Aug 01 06:19:20 PM PDT 24
Peak memory	206888 kb
Host	smart-97c0b3d2-d90b-4fbc-ae28-035b9e892645
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18959 93065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1895993065
Directory	/workspace/45.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/45.usbdev_pkt_buffer.2677018345
Short name	T1964
Test name
Test status
Simulation time	11558168122 ps
CPU time	29.27 seconds
Started	Aug 01 06:19:20 PM PDT 24
Finished	Aug 01 06:19:49 PM PDT 24
Peak memory	215364 kb
Host	smart-92cbcd9d-3394-4b1a-89ff-895fe67b640e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26770 18345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2677018345
Directory	/workspace/45.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/45.usbdev_pkt_received.2007612969
Short name	T1251
Test name
Test status
Simulation time	193315237 ps
CPU time	0.93 seconds
Started	Aug 01 06:19:16 PM PDT 24
Finished	Aug 01 06:19:17 PM PDT 24
Peak memory	206956 kb
Host	smart-d5f7e0b5-d778-404c-86eb-456ea65dc038
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20076 12969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.2007612969
Directory	/workspace/45.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/45.usbdev_pkt_sent.2722366900
Short name	T1628
Test name
Test status
Simulation time	167255077 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:24 PM PDT 24
Finished	Aug 01 06:19:26 PM PDT 24
Peak memory	206944 kb
Host	smart-fad2f59d-036c-491a-8e28-3f16f78412a4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27223 66900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.2722366900
Directory	/workspace/45.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/45.usbdev_random_length_in_transaction.2456241301
Short name	T777
Test name
Test status
Simulation time	224033602 ps
CPU time	0.94 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:17 PM PDT 24
Peak memory	206940 kb
Host	smart-756b2b25-07f4-4f5d-9366-dc372dfcfe59
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24562 41301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.2456241301
Directory	/workspace/45.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/45.usbdev_random_length_out_transaction.431914722
Short name	T2299
Test name
Test status
Simulation time	178221348 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:12 PM PDT 24
Finished	Aug 01 06:19:13 PM PDT 24
Peak memory	206920 kb
Host	smart-47e4389b-5441-4668-a0f1-0a2c2d3af08d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43191 4722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.431914722
Directory	/workspace/45.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/45.usbdev_rx_crc_err.1801628029
Short name	T69
Test name
Test status
Simulation time	157483156 ps
CPU time	0.83 seconds
Started	Aug 01 06:19:15 PM PDT 24
Finished	Aug 01 06:19:16 PM PDT 24
Peak memory	206908 kb
Host	smart-b22be626-c2c8-49b6-b5e0-90c6a2732e50
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18016 28029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1801628029
Directory	/workspace/45.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/45.usbdev_rx_full.362116277
Short name	T1015
Test name
Test status
Simulation time	332462293 ps
CPU time	1.18 seconds
Started	Aug 01 06:19:24 PM PDT 24
Finished	Aug 01 06:19:26 PM PDT 24
Peak memory	206928 kb
Host	smart-d32e5355-54d9-4ff2-aad4-2ebf569c1b34
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36211 6277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.362116277
Directory	/workspace/45.usbdev_rx_full/latest

Test location	/workspace/coverage/default/45.usbdev_setup_stage.499888162
Short name	T573
Test name
Test status
Simulation time	219862779 ps
CPU time	0.99 seconds
Started	Aug 01 06:19:20 PM PDT 24
Finished	Aug 01 06:19:21 PM PDT 24
Peak memory	206912 kb
Host	smart-bdef9f63-7c9d-4617-b7c7-c994fa03b11b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49988 8162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.499888162
Directory	/workspace/45.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/45.usbdev_setup_trans_ignored.2227202849
Short name	T1111
Test name
Test status
Simulation time	160750742 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:14 PM PDT 24
Finished	Aug 01 06:19:15 PM PDT 24
Peak memory	206912 kb
Host	smart-3812a964-7882-4ecf-9562-a1479cefe852
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22272 02849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2227202849
Directory	/workspace/45.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/45.usbdev_smoke.3981810650
Short name	T31
Test name
Test status
Simulation time	224284486 ps
CPU time	0.99 seconds
Started	Aug 01 06:19:24 PM PDT 24
Finished	Aug 01 06:19:25 PM PDT 24
Peak memory	206928 kb
Host	smart-4f3c5ee8-2d0e-4ac9-92cb-9addcdcada08
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39818 10650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3981810650
Directory	/workspace/45.usbdev_smoke/latest

Test location	/workspace/coverage/default/45.usbdev_spurious_pids_ignored.491094994
Short name	T703
Test name
Test status
Simulation time	2790541834 ps
CPU time	21.75 seconds
Started	Aug 01 06:19:14 PM PDT 24
Finished	Aug 01 06:19:36 PM PDT 24
Peak memory	207148 kb
Host	smart-ada3f1c1-753b-4571-a08a-fc520190cf49
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=491094994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.491094994
Directory	/workspace/45.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/45.usbdev_stall_priority_over_nak.459210650
Short name	T615
Test name
Test status
Simulation time	193114340 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:18 PM PDT 24
Finished	Aug 01 06:19:19 PM PDT 24
Peak memory	206960 kb
Host	smart-0d3d743e-b5b5-452f-a438-60dfbc535a84
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45921 0650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.459210650
Directory	/workspace/45.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/45.usbdev_stall_trans.2785013095
Short name	T2571
Test name
Test status
Simulation time	160978300 ps
CPU time	0.87 seconds
Started	Aug 01 06:19:17 PM PDT 24
Finished	Aug 01 06:19:18 PM PDT 24
Peak memory	206892 kb
Host	smart-87ab15c7-c51c-4173-8c41-e31951d5eafa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27850 13095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.2785013095
Directory	/workspace/45.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/45.usbdev_stream_len_max.2339636523
Short name	T2814
Test name
Test status
Simulation time	550634214 ps
CPU time	1.49 seconds
Started	Aug 01 06:19:10 PM PDT 24
Finished	Aug 01 06:19:12 PM PDT 24
Peak memory	206872 kb
Host	smart-9e6c5d98-ef06-496b-ac85-609037b7ee93
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23396 36523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.2339636523
Directory	/workspace/45.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/45.usbdev_streaming_out.1563018299
Short name	T948
Test name
Test status
Simulation time	1745004903 ps
CPU time	47.14 seconds
Started	Aug 01 06:19:14 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	223412 kb
Host	smart-d0cbe31a-325e-44d3-8ceb-ad626639e6b0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15630 18299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1563018299
Directory	/workspace/45.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.1102103072
Short name	T2627
Test name
Test status
Simulation time	2236078252 ps
CPU time	13.72 seconds
Started	Aug 01 06:19:17 PM PDT 24
Finished	Aug 01 06:19:30 PM PDT 24
Peak memory	207248 kb
Host	smart-d8f01872-3f7b-4727-9226-8b1e303dd0cd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102103072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos t_handshake.1102103072
Directory	/workspace/45.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/46.usbdev_alert_test.3345710782
Short name	T2880
Test name
Test status
Simulation time	59010728 ps
CPU time	0.69 seconds
Started	Aug 01 06:19:24 PM PDT 24
Finished	Aug 01 06:19:25 PM PDT 24
Peak memory	206016 kb
Host	smart-04c5d650-e3b4-4e82-b900-8ab68e49d61e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3345710782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.3345710782
Directory	/workspace/46.usbdev_alert_test/latest

Test location	/workspace/coverage/default/46.usbdev_av_buffer.3884467998
Short name	T2706
Test name
Test status
Simulation time	209916802 ps
CPU time	0.99 seconds
Started	Aug 01 06:19:41 PM PDT 24
Finished	Aug 01 06:19:43 PM PDT 24
Peak memory	206956 kb
Host	smart-98dcb27d-2750-4820-b49d-d2d94454f3a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38844 67998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3884467998
Directory	/workspace/46.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/46.usbdev_bitstuff_err.2724992931
Short name	T2630
Test name
Test status
Simulation time	161643395 ps
CPU time	0.83 seconds
Started	Aug 01 06:19:38 PM PDT 24
Finished	Aug 01 06:19:39 PM PDT 24
Peak memory	206900 kb
Host	smart-15d14901-0532-43e2-b8ff-c2eff1e05907
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27249 92931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2724992931
Directory	/workspace/46.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/46.usbdev_data_toggle_clear.2195988446
Short name	T1533
Test name
Test status
Simulation time	407942301 ps
CPU time	1.43 seconds
Started	Aug 01 06:19:38 PM PDT 24
Finished	Aug 01 06:19:40 PM PDT 24
Peak memory	206952 kb
Host	smart-65afa440-50ab-44ad-ae75-d4c8941f4eb4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21959 88446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.2195988446
Directory	/workspace/46.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/46.usbdev_data_toggle_restore.3803550836
Short name	T1710
Test name
Test status
Simulation time	862988398 ps
CPU time	2.33 seconds
Started	Aug 01 06:19:35 PM PDT 24
Finished	Aug 01 06:19:37 PM PDT 24
Peak memory	207128 kb
Host	smart-d676ec4b-b400-47a0-90d3-c8cccf839b78
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3803550836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3803550836
Directory	/workspace/46.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/46.usbdev_device_address.2549452215
Short name	T1981
Test name
Test status
Simulation time	24269107132 ps
CPU time	35.63 seconds
Started	Aug 01 06:19:43 PM PDT 24
Finished	Aug 01 06:20:19 PM PDT 24
Peak memory	207180 kb
Host	smart-af315514-de18-4d3a-a0ee-b87079d2ccba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25494 52215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2549452215
Directory	/workspace/46.usbdev_device_address/latest

Test location	/workspace/coverage/default/46.usbdev_device_timeout.850391412
Short name	T730
Test name
Test status
Simulation time	1248299649 ps
CPU time	28.23 seconds
Started	Aug 01 06:19:21 PM PDT 24
Finished	Aug 01 06:19:49 PM PDT 24
Peak memory	207064 kb
Host	smart-c595e7df-764b-4842-810a-c5354cb5efb1
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850391412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.850391412
Directory	/workspace/46.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/46.usbdev_disable_endpoint.3878623507
Short name	T854
Test name
Test status
Simulation time	815206265 ps
CPU time	2.04 seconds
Started	Aug 01 06:19:38 PM PDT 24
Finished	Aug 01 06:19:41 PM PDT 24
Peak memory	206916 kb
Host	smart-11e1cfe7-8618-40b0-9984-85f3183e97c9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38786 23507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3878623507
Directory	/workspace/46.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/46.usbdev_disconnected.304957083
Short name	T2640
Test name
Test status
Simulation time	147699798 ps
CPU time	0.8 seconds
Started	Aug 01 06:19:24 PM PDT 24
Finished	Aug 01 06:19:25 PM PDT 24
Peak memory	206868 kb
Host	smart-698cad4e-29bf-4657-a578-12a68ab59f3f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30495 7083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.304957083
Directory	/workspace/46.usbdev_disconnected/latest

Test location	/workspace/coverage/default/46.usbdev_enable.3914184641
Short name	T707
Test name
Test status
Simulation time	38342745 ps
CPU time	0.71 seconds
Started	Aug 01 06:19:30 PM PDT 24
Finished	Aug 01 06:19:30 PM PDT 24
Peak memory	206920 kb
Host	smart-84ce50ae-3b5b-4af2-8d23-a0396a321d98
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39141 84641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3914184641
Directory	/workspace/46.usbdev_enable/latest

Test location	/workspace/coverage/default/46.usbdev_endpoint_access.3962192402
Short name	T2315
Test name
Test status
Simulation time	815818747 ps
CPU time	2.28 seconds
Started	Aug 01 06:19:41 PM PDT 24
Finished	Aug 01 06:19:44 PM PDT 24
Peak memory	207108 kb
Host	smart-b92b0524-6dfc-4a33-84a8-4d679c552e73
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39621 92402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3962192402
Directory	/workspace/46.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/46.usbdev_fifo_rst.706090238
Short name	T1988
Test name
Test status
Simulation time	164386016 ps
CPU time	1.31 seconds
Started	Aug 01 06:19:30 PM PDT 24
Finished	Aug 01 06:19:31 PM PDT 24
Peak memory	207108 kb
Host	smart-a3dc178a-3c9a-4ad6-8155-7592050a4c8b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70609 0238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.706090238
Directory	/workspace/46.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/46.usbdev_in_iso.3605588795
Short name	T2268
Test name
Test status
Simulation time	175363008 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:36 PM PDT 24
Finished	Aug 01 06:19:37 PM PDT 24
Peak memory	206984 kb
Host	smart-586077a5-a733-432d-b64f-18616ba4161b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3605588795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3605588795
Directory	/workspace/46.usbdev_in_iso/latest

Test location	/workspace/coverage/default/46.usbdev_in_stall.4010815395
Short name	T808
Test name
Test status
Simulation time	157407120 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:33 PM PDT 24
Finished	Aug 01 06:19:34 PM PDT 24
Peak memory	206932 kb
Host	smart-ebc02bb3-ee18-4a49-86f0-65a334970c07
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40108 15395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.4010815395
Directory	/workspace/46.usbdev_in_stall/latest

Test location	/workspace/coverage/default/46.usbdev_in_trans.1318777777
Short name	T1480
Test name
Test status
Simulation time	258320188 ps
CPU time	1.04 seconds
Started	Aug 01 06:19:40 PM PDT 24
Finished	Aug 01 06:19:42 PM PDT 24
Peak memory	206928 kb
Host	smart-1b8332be-9358-42a7-8314-c4f0f8623082
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13187 77777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.1318777777
Directory	/workspace/46.usbdev_in_trans/latest

Test location	/workspace/coverage/default/46.usbdev_invalid_sync.2782872678
Short name	T2207
Test name
Test status
Simulation time	3939481179 ps
CPU time	29.04 seconds
Started	Aug 01 06:19:23 PM PDT 24
Finished	Aug 01 06:19:52 PM PDT 24
Peak memory	223584 kb
Host	smart-f9aa6812-ce40-406f-810b-cb804257d594
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2782872678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.2782872678
Directory	/workspace/46.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/46.usbdev_link_in_err.2868855705
Short name	T1475
Test name
Test status
Simulation time	233659840 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:35 PM PDT 24
Finished	Aug 01 06:19:36 PM PDT 24
Peak memory	206864 kb
Host	smart-2279f761-1928-4c4e-877e-19cb665ed862
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28688 55705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2868855705
Directory	/workspace/46.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/46.usbdev_link_suspend.1143622925
Short name	T45
Test name
Test status
Simulation time	10244001536 ps
CPU time	13.11 seconds
Started	Aug 01 06:19:25 PM PDT 24
Finished	Aug 01 06:19:38 PM PDT 24
Peak memory	207164 kb
Host	smart-031b5895-2aa6-4747-bba2-bde46d826a6e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11436 22925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1143622925
Directory	/workspace/46.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/46.usbdev_low_speed_traffic.3623905633
Short name	T1402
Test name
Test status
Simulation time	4029517040 ps
CPU time	111.93 seconds
Started	Aug 01 06:19:21 PM PDT 24
Finished	Aug 01 06:21:13 PM PDT 24
Peak memory	223552 kb
Host	smart-9928260c-df04-44cc-b878-857fc430f6f4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36239 05633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3623905633
Directory	/workspace/46.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/46.usbdev_max_inter_pkt_delay.1731139089
Short name	T634
Test name
Test status
Simulation time	1909479141 ps
CPU time	50.81 seconds
Started	Aug 01 06:19:21 PM PDT 24
Finished	Aug 01 06:20:12 PM PDT 24
Peak memory	216644 kb
Host	smart-97945d4e-2808-474a-891c-cb6169baec66
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1731139089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.1731139089
Directory	/workspace/46.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/46.usbdev_max_length_in_transaction.2782713039
Short name	T1476
Test name
Test status
Simulation time	255088775 ps
CPU time	0.96 seconds
Started	Aug 01 06:19:36 PM PDT 24
Finished	Aug 01 06:19:37 PM PDT 24
Peak memory	206920 kb
Host	smart-80a8a1e0-090a-440d-aadd-d7f92e040f1c
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2782713039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2782713039
Directory	/workspace/46.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/46.usbdev_max_length_out_transaction.82161282
Short name	T1293
Test name
Test status
Simulation time	206602878 ps
CPU time	0.96 seconds
Started	Aug 01 06:19:23 PM PDT 24
Finished	Aug 01 06:19:24 PM PDT 24
Peak memory	206916 kb
Host	smart-8e492e15-e19c-420e-8996-5248269f40c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82161 282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.82161282
Directory	/workspace/46.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2559791006
Short name	T757
Test name
Test status
Simulation time	2411612980 ps
CPU time	23.69 seconds
Started	Aug 01 06:19:24 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	223468 kb
Host	smart-dc1d3b26-05c0-40f2-a4b6-fca3e9a16840
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2559791006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2559791006
Directory	/workspace/46.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/46.usbdev_min_length_in_transaction.3551601520
Short name	T1179
Test name
Test status
Simulation time	151932011 ps
CPU time	0.89 seconds
Started	Aug 01 06:19:39 PM PDT 24
Finished	Aug 01 06:19:40 PM PDT 24
Peak memory	206928 kb
Host	smart-0520e3fc-8e70-49bc-9976-c52da54ecff2
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3551601520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3551601520
Directory	/workspace/46.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/46.usbdev_min_length_out_transaction.1524100971
Short name	T1046
Test name
Test status
Simulation time	142922125 ps
CPU time	0.83 seconds
Started	Aug 01 06:19:29 PM PDT 24
Finished	Aug 01 06:19:30 PM PDT 24
Peak memory	206988 kb
Host	smart-b9c39086-10e7-4e1c-a2a5-f39e2d9a726a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15241 00971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1524100971
Directory	/workspace/46.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/46.usbdev_nak_trans.2032593964
Short name	T199
Test name
Test status
Simulation time	209273009 ps
CPU time	0.95 seconds
Started	Aug 01 06:19:35 PM PDT 24
Finished	Aug 01 06:19:36 PM PDT 24
Peak memory	207168 kb
Host	smart-9285c8b7-5caf-45d5-a422-724abc170f9b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20325 93964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.2032593964
Directory	/workspace/46.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/46.usbdev_out_iso.3054313931
Short name	T933
Test name
Test status
Simulation time	149035039 ps
CPU time	0.81 seconds
Started	Aug 01 06:19:35 PM PDT 24
Finished	Aug 01 06:19:36 PM PDT 24
Peak memory	206916 kb
Host	smart-1df1822a-7473-4bdb-a28c-4cdb6dc3c3e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30543 13931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3054313931
Directory	/workspace/46.usbdev_out_iso/latest

Test location	/workspace/coverage/default/46.usbdev_out_stall.3482293450
Short name	T2773
Test name
Test status
Simulation time	170867146 ps
CPU time	0.9 seconds
Started	Aug 01 06:19:34 PM PDT 24
Finished	Aug 01 06:19:35 PM PDT 24
Peak memory	206928 kb
Host	smart-24bc3f0c-0982-4624-b8bd-f2c3e17f38b8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34822 93450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.3482293450
Directory	/workspace/46.usbdev_out_stall/latest

Test location	/workspace/coverage/default/46.usbdev_out_trans_nak.527158379
Short name	T1274
Test name
Test status
Simulation time	189281674 ps
CPU time	0.9 seconds
Started	Aug 01 06:19:24 PM PDT 24
Finished	Aug 01 06:19:25 PM PDT 24
Peak memory	206960 kb
Host	smart-12aecc0b-600b-4583-abdc-8b980db55d24
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52715 8379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.527158379
Directory	/workspace/46.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/46.usbdev_pending_in_trans.3383988658
Short name	T226
Test name
Test status
Simulation time	157706303 ps
CPU time	0.89 seconds
Started	Aug 01 06:19:30 PM PDT 24
Finished	Aug 01 06:19:31 PM PDT 24
Peak memory	206940 kb
Host	smart-eb7fbb9d-cdef-4c5e-9c59-705c31c715c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33839 88658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.3383988658
Directory	/workspace/46.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/46.usbdev_phy_config_pinflip.502704171
Short name	T2659
Test name
Test status
Simulation time	219482777 ps
CPU time	1 seconds
Started	Aug 01 06:19:23 PM PDT 24
Finished	Aug 01 06:19:25 PM PDT 24
Peak memory	206912 kb
Host	smart-099857eb-6cec-4021-98d0-7d8c98c26548
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=502704171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.502704171
Directory	/workspace/46.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3312398439
Short name	T1335
Test name
Test status
Simulation time	170424168 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:23 PM PDT 24
Finished	Aug 01 06:19:24 PM PDT 24
Peak memory	206920 kb
Host	smart-8318ef40-f1b6-41b3-8ec2-e636b7f7954b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33123 98439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3312398439
Directory	/workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/46.usbdev_phy_pins_sense.433337986
Short name	T2159
Test name
Test status
Simulation time	41473901 ps
CPU time	0.71 seconds
Started	Aug 01 06:19:27 PM PDT 24
Finished	Aug 01 06:19:28 PM PDT 24
Peak memory	206924 kb
Host	smart-44fe15d0-a4cf-4424-ba28-b1e56aeaaa37
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43333 7986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.433337986
Directory	/workspace/46.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/46.usbdev_pkt_buffer.3139359189
Short name	T2432
Test name
Test status
Simulation time	23199640432 ps
CPU time	62.65 seconds
Started	Aug 01 06:19:34 PM PDT 24
Finished	Aug 01 06:20:36 PM PDT 24
Peak memory	223616 kb
Host	smart-9bc4daf4-c96a-4725-8e05-bac2ee521139
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31393 59189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3139359189
Directory	/workspace/46.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/46.usbdev_pkt_received.4073208687
Short name	T2721
Test name
Test status
Simulation time	180599251 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:22 PM PDT 24
Finished	Aug 01 06:19:24 PM PDT 24
Peak memory	206944 kb
Host	smart-65b179b0-3ab7-443d-8dbe-1960a07f7c80
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40732 08687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.4073208687
Directory	/workspace/46.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/46.usbdev_pkt_sent.2664728108
Short name	T2301
Test name
Test status
Simulation time	256573021 ps
CPU time	1 seconds
Started	Aug 01 06:19:24 PM PDT 24
Finished	Aug 01 06:19:25 PM PDT 24
Peak memory	206900 kb
Host	smart-fdedc3d6-7d0a-48f9-8537-8dc64268df14
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26647 28108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2664728108
Directory	/workspace/46.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/46.usbdev_random_length_in_transaction.2504488619
Short name	T2875
Test name
Test status
Simulation time	252084207 ps
CPU time	1.02 seconds
Started	Aug 01 06:19:23 PM PDT 24
Finished	Aug 01 06:19:24 PM PDT 24
Peak memory	206920 kb
Host	smart-e2433850-7a7f-4e0c-8ff3-74447a2087a1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25044 88619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2504488619
Directory	/workspace/46.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/46.usbdev_random_length_out_transaction.3554262469
Short name	T1899
Test name
Test status
Simulation time	184331719 ps
CPU time	0.95 seconds
Started	Aug 01 06:19:42 PM PDT 24
Finished	Aug 01 06:19:43 PM PDT 24
Peak memory	206956 kb
Host	smart-5f43cb68-9e8c-45ab-811e-87be21a84f77
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542 62469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3554262469
Directory	/workspace/46.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/46.usbdev_rx_crc_err.1586043175
Short name	T2703
Test name
Test status
Simulation time	187661845 ps
CPU time	0.94 seconds
Started	Aug 01 06:19:37 PM PDT 24
Finished	Aug 01 06:19:38 PM PDT 24
Peak memory	206968 kb
Host	smart-3ab51262-1700-4f4b-976c-947b4e36a0e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15860 43175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.1586043175
Directory	/workspace/46.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/46.usbdev_rx_full.3392048839
Short name	T39
Test name
Test status
Simulation time	411206907 ps
CPU time	1.33 seconds
Started	Aug 01 06:19:37 PM PDT 24
Finished	Aug 01 06:19:39 PM PDT 24
Peak memory	206960 kb
Host	smart-664e8d0f-ea34-4462-9557-014e0648f76b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33920 48839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.3392048839
Directory	/workspace/46.usbdev_rx_full/latest

Test location	/workspace/coverage/default/46.usbdev_setup_stage.1626670483
Short name	T1936
Test name
Test status
Simulation time	146696298 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:41 PM PDT 24
Finished	Aug 01 06:19:42 PM PDT 24
Peak memory	206872 kb
Host	smart-56bb2b44-be4e-464d-88b1-9576b5b39282
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16266 70483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1626670483
Directory	/workspace/46.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/46.usbdev_setup_trans_ignored.961251316
Short name	T2488
Test name
Test status
Simulation time	146716937 ps
CPU time	0.82 seconds
Started	Aug 01 06:19:39 PM PDT 24
Finished	Aug 01 06:19:40 PM PDT 24
Peak memory	206936 kb
Host	smart-9985e88b-c3a2-4f78-8c70-96cc23769714
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96125 1316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.961251316
Directory	/workspace/46.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/46.usbdev_smoke.311575738
Short name	T626
Test name
Test status
Simulation time	197701769 ps
CPU time	1.02 seconds
Started	Aug 01 06:19:22 PM PDT 24
Finished	Aug 01 06:19:23 PM PDT 24
Peak memory	206944 kb
Host	smart-a5bc5f1d-2c3c-4366-b9d2-6eb9fb600d09
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31157 5738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.311575738
Directory	/workspace/46.usbdev_smoke/latest

Test location	/workspace/coverage/default/46.usbdev_spurious_pids_ignored.2069837996
Short name	T2334
Test name
Test status
Simulation time	3337944090 ps
CPU time	101.63 seconds
Started	Aug 01 06:19:35 PM PDT 24
Finished	Aug 01 06:21:17 PM PDT 24
Peak memory	223504 kb
Host	smart-d4cc3e36-4ad1-42c7-8d8f-1cd76614f5f6
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2069837996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.2069837996
Directory	/workspace/46.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/46.usbdev_stall_priority_over_nak.2406284292
Short name	T2151
Test name
Test status
Simulation time	193258898 ps
CPU time	0.86 seconds
Started	Aug 01 06:19:31 PM PDT 24
Finished	Aug 01 06:19:32 PM PDT 24
Peak memory	206932 kb
Host	smart-cf6d8605-ab1c-4734-b79c-ba13c3e6cb2d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24062 84292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2406284292
Directory	/workspace/46.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/46.usbdev_stall_trans.1754706088
Short name	T746
Test name
Test status
Simulation time	198005251 ps
CPU time	0.9 seconds
Started	Aug 01 06:19:28 PM PDT 24
Finished	Aug 01 06:19:30 PM PDT 24
Peak memory	206848 kb
Host	smart-8453ad9d-c716-4d3b-83e3-50cf2a49917a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17547 06088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1754706088
Directory	/workspace/46.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/46.usbdev_stream_len_max.3878708311
Short name	T1324
Test name
Test status
Simulation time	957323986 ps
CPU time	2.42 seconds
Started	Aug 01 06:19:39 PM PDT 24
Finished	Aug 01 06:19:41 PM PDT 24
Peak memory	207084 kb
Host	smart-54a53b2b-5a9c-4246-83ba-015642a37191
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38787 08311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3878708311
Directory	/workspace/46.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/46.usbdev_streaming_out.2439809761
Short name	T2622
Test name
Test status
Simulation time	2063580729 ps
CPU time	20.14 seconds
Started	Aug 01 06:19:25 PM PDT 24
Finished	Aug 01 06:19:46 PM PDT 24
Peak memory	222524 kb
Host	smart-580da552-834c-4cd7-9bbb-0f0b99d391f3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24398 09761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.2439809761
Directory	/workspace/46.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.2366895478
Short name	T2409
Test name
Test status
Simulation time	5499601349 ps
CPU time	38.03 seconds
Started	Aug 01 06:19:30 PM PDT 24
Finished	Aug 01 06:20:08 PM PDT 24
Peak memory	207204 kb
Host	smart-3706b4bd-42b7-4337-9055-79ff1c0aa110
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366895478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos t_handshake.2366895478
Directory	/workspace/46.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/47.usbdev_alert_test.2209545237
Short name	T810
Test name
Test status
Simulation time	37363928 ps
CPU time	0.65 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:46 PM PDT 24
Peak memory	206996 kb
Host	smart-c9d015f5-1798-4c93-9f9b-98baf3338786
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2209545237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.2209545237
Directory	/workspace/47.usbdev_alert_test/latest

Test location	/workspace/coverage/default/47.usbdev_av_buffer.1228250787
Short name	T1762
Test name
Test status
Simulation time	157251860 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:39 PM PDT 24
Finished	Aug 01 06:19:40 PM PDT 24
Peak memory	206940 kb
Host	smart-56362046-3040-4e62-9ae8-04658616ec9b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12282 50787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1228250787
Directory	/workspace/47.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/47.usbdev_bitstuff_err.4195529122
Short name	T1488
Test name
Test status
Simulation time	148608643 ps
CPU time	0.81 seconds
Started	Aug 01 06:19:49 PM PDT 24
Finished	Aug 01 06:19:50 PM PDT 24
Peak memory	206912 kb
Host	smart-89fae8cd-c584-4ad2-bf50-cfc9005e201c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41955 29122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.4195529122
Directory	/workspace/47.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/47.usbdev_data_toggle_clear.1808770470
Short name	T1196
Test name
Test status
Simulation time	279952518 ps
CPU time	1.3 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:48 PM PDT 24
Peak memory	206976 kb
Host	smart-2ab1bf08-f17a-498b-b619-133bd418121b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18087 70470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1808770470
Directory	/workspace/47.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/47.usbdev_data_toggle_restore.3607447772
Short name	T2708
Test name
Test status
Simulation time	344904564 ps
CPU time	1.18 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206984 kb
Host	smart-d865de64-ff98-4bb4-b0fa-98552a7fa7ab
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3607447772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3607447772
Directory	/workspace/47.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/47.usbdev_device_address.82946387
Short name	T222
Test name
Test status
Simulation time	35453299813 ps
CPU time	57.31 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:20:43 PM PDT 24
Peak memory	207088 kb
Host	smart-7eacbe9b-dcc3-45e9-bf0f-16e1f5845348
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82946 387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.82946387
Directory	/workspace/47.usbdev_device_address/latest

Test location	/workspace/coverage/default/47.usbdev_device_timeout.1639037474
Short name	T2538
Test name
Test status
Simulation time	7077854993 ps
CPU time	45.26 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:20:30 PM PDT 24
Peak memory	207160 kb
Host	smart-e0d2b300-a2c9-4030-b552-1687d81872ec
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639037474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.1639037474
Directory	/workspace/47.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/47.usbdev_disable_endpoint.1027255990
Short name	T2493
Test name
Test status
Simulation time	895883445 ps
CPU time	2.02 seconds
Started	Aug 01 06:19:43 PM PDT 24
Finished	Aug 01 06:19:45 PM PDT 24
Peak memory	206880 kb
Host	smart-90ff98ee-85bc-4ad9-9e24-0cb8ff1f302f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10272 55990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1027255990
Directory	/workspace/47.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/47.usbdev_disconnected.144984754
Short name	T1703
Test name
Test status
Simulation time	184074138 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206912 kb
Host	smart-1dd367d5-06fe-4458-8148-04848ccfcfee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14498 4754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.144984754
Directory	/workspace/47.usbdev_disconnected/latest

Test location	/workspace/coverage/default/47.usbdev_enable.1737343265
Short name	T2013
Test name
Test status
Simulation time	46730043 ps
CPU time	0.69 seconds
Started	Aug 01 06:19:47 PM PDT 24
Finished	Aug 01 06:19:48 PM PDT 24
Peak memory	206876 kb
Host	smart-e78fa7ad-2514-4017-9016-cefffb46add1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17373 43265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1737343265
Directory	/workspace/47.usbdev_enable/latest

Test location	/workspace/coverage/default/47.usbdev_endpoint_access.1183336446
Short name	T2760
Test name
Test status
Simulation time	950025195 ps
CPU time	2.76 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:48 PM PDT 24
Peak memory	207132 kb
Host	smart-f80d73d7-5a2e-4de8-aac7-92cf587fb830
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11833 36446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1183336446
Directory	/workspace/47.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/47.usbdev_endpoint_types.3603994121
Short name	T2078
Test name
Test status
Simulation time	402656027 ps
CPU time	1.24 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206896 kb
Host	smart-264a80d9-ff2c-4d85-aa89-917bbc2c1c90
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3603994121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.3603994121
Directory	/workspace/47.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/47.usbdev_fifo_rst.4292771762
Short name	T2768
Test name
Test status
Simulation time	295964373 ps
CPU time	2.36 seconds
Started	Aug 01 06:19:47 PM PDT 24
Finished	Aug 01 06:19:50 PM PDT 24
Peak memory	207072 kb
Host	smart-6fd7a3fb-ac38-4a1d-9903-090b5d617a23
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42927 71762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.4292771762
Directory	/workspace/47.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/47.usbdev_in_iso.1392108639
Short name	T1464
Test name
Test status
Simulation time	176615053 ps
CPU time	0.93 seconds
Started	Aug 01 06:19:42 PM PDT 24
Finished	Aug 01 06:19:43 PM PDT 24
Peak memory	207176 kb
Host	smart-69e852dd-af45-417c-b86d-75d6012ae3eb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1392108639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1392108639
Directory	/workspace/47.usbdev_in_iso/latest

Test location	/workspace/coverage/default/47.usbdev_in_stall.3865887795
Short name	T1739
Test name
Test status
Simulation time	163238878 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206888 kb
Host	smart-01f13a62-8895-454c-ad92-bf12960b9a22
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38658 87795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.3865887795
Directory	/workspace/47.usbdev_in_stall/latest

Test location	/workspace/coverage/default/47.usbdev_in_trans.2768478015
Short name	T1530
Test name
Test status
Simulation time	198137407 ps
CPU time	0.9 seconds
Started	Aug 01 06:19:41 PM PDT 24
Finished	Aug 01 06:19:42 PM PDT 24
Peak memory	206936 kb
Host	smart-94a455b7-0452-4ac0-9d8e-db0f01af2e6a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27684 78015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2768478015
Directory	/workspace/47.usbdev_in_trans/latest

Test location	/workspace/coverage/default/47.usbdev_invalid_sync.3961148552
Short name	T2769
Test name
Test status
Simulation time	3646995468 ps
CPU time	102.84 seconds
Started	Aug 01 06:19:43 PM PDT 24
Finished	Aug 01 06:21:26 PM PDT 24
Peak memory	217648 kb
Host	smart-d1f77e2e-cd01-4ccf-8d3b-91f660c5f6ff
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3961148552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3961148552
Directory	/workspace/47.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/47.usbdev_iso_retraction.2995907252
Short name	T2196
Test name
Test status
Simulation time	5762654188 ps
CPU time	36.34 seconds
Started	Aug 01 06:19:43 PM PDT 24
Finished	Aug 01 06:20:20 PM PDT 24
Peak memory	207132 kb
Host	smart-ee111d2a-6f7d-4896-940e-440fc2f7f866
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2995907252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.2995907252
Directory	/workspace/47.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/47.usbdev_link_in_err.1016093991
Short name	T871
Test name
Test status
Simulation time	262985669 ps
CPU time	1.02 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:45 PM PDT 24
Peak memory	206944 kb
Host	smart-3cb3b41b-9c78-4cb5-8b52-ed9f5f47e6c8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10160 93991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1016093991
Directory	/workspace/47.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/47.usbdev_link_suspend.8058376
Short name	T94
Test name
Test status
Simulation time	10423399779 ps
CPU time	12.68 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	207152 kb
Host	smart-c2f59862-75e3-4758-ba29-e29508dd1d41
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80583 76 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.8058376
Directory	/workspace/47.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/47.usbdev_low_speed_traffic.1737840510
Short name	T1958
Test name
Test status
Simulation time	4410687858 ps
CPU time	31.82 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:20:16 PM PDT 24
Peak memory	223452 kb
Host	smart-7ffbfab8-e589-499d-9c75-3cca7e27aaef
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378 40510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.1737840510
Directory	/workspace/47.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2906333078
Short name	T1076
Test name
Test status
Simulation time	1843694169 ps
CPU time	51.68 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:20:36 PM PDT 24
Peak memory	215336 kb
Host	smart-bb97648d-ed5a-413c-bbcf-ea697357a672
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2906333078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2906333078
Directory	/workspace/47.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/47.usbdev_max_length_in_transaction.1492297787
Short name	T639
Test name
Test status
Simulation time	305002818 ps
CPU time	1.13 seconds
Started	Aug 01 06:19:43 PM PDT 24
Finished	Aug 01 06:19:45 PM PDT 24
Peak memory	206956 kb
Host	smart-41e4a41d-9a03-4bed-9eb7-a0fc30f6396d
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1492297787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.1492297787
Directory	/workspace/47.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/47.usbdev_max_length_out_transaction.1339711802
Short name	T2808
Test name
Test status
Simulation time	190286764 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:46 PM PDT 24
Peak memory	206992 kb
Host	smart-3737a52f-e083-49a5-8f82-290a9754883f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13397 11802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1339711802
Directory	/workspace/47.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/47.usbdev_min_inter_pkt_delay.4138324393
Short name	T2292
Test name
Test status
Simulation time	2102566292 ps
CPU time	15.31 seconds
Started	Aug 01 06:19:47 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	207096 kb
Host	smart-87a12923-2bab-40ab-b8cd-1d7d54d3f448
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=4138324393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.4138324393
Directory	/workspace/47.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/47.usbdev_min_length_in_transaction.2731884003
Short name	T1859
Test name
Test status
Simulation time	159433589 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:46 PM PDT 24
Peak memory	206804 kb
Host	smart-9c769819-6705-44c8-b5bf-acc564f9807e
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2731884003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.2731884003
Directory	/workspace/47.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/47.usbdev_min_length_out_transaction.1828409532
Short name	T843
Test name
Test status
Simulation time	148433989 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:48 PM PDT 24
Finished	Aug 01 06:19:49 PM PDT 24
Peak memory	206900 kb
Host	smart-ab665d9a-cbe3-4cf4-b54f-b2306b2463a3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284 09532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1828409532
Directory	/workspace/47.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/47.usbdev_nak_trans.4064274000
Short name	T195
Test name
Test status
Simulation time	205902959 ps
CPU time	0.95 seconds
Started	Aug 01 06:19:42 PM PDT 24
Finished	Aug 01 06:19:43 PM PDT 24
Peak memory	206948 kb
Host	smart-d884e23b-14eb-4190-836c-f72520d19646
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40642 74000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.4064274000
Directory	/workspace/47.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/47.usbdev_out_iso.947080309
Short name	T1996
Test name
Test status
Simulation time	180838298 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:47 PM PDT 24
Finished	Aug 01 06:19:48 PM PDT 24
Peak memory	206956 kb
Host	smart-d2b0f5a9-4e0e-43b0-8c74-d3922a07420e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94708 0309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.947080309
Directory	/workspace/47.usbdev_out_iso/latest

Test location	/workspace/coverage/default/47.usbdev_out_stall.551968997
Short name	T2482
Test name
Test status
Simulation time	203968246 ps
CPU time	0.89 seconds
Started	Aug 01 06:19:50 PM PDT 24
Finished	Aug 01 06:19:51 PM PDT 24
Peak memory	206924 kb
Host	smart-9e44c9a2-c591-47b2-b92a-44f9a715f194
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55196 8997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.551968997
Directory	/workspace/47.usbdev_out_stall/latest

Test location	/workspace/coverage/default/47.usbdev_out_trans_nak.2314829871
Short name	T1798
Test name
Test status
Simulation time	203260736 ps
CPU time	0.89 seconds
Started	Aug 01 06:19:43 PM PDT 24
Finished	Aug 01 06:19:44 PM PDT 24
Peak memory	206932 kb
Host	smart-04f158b0-3607-43fd-a537-41cbd322f6d0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23148 29871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2314829871
Directory	/workspace/47.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/47.usbdev_pending_in_trans.1830052536
Short name	T1930
Test name
Test status
Simulation time	163073274 ps
CPU time	0.98 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206964 kb
Host	smart-442563a1-b3c1-4918-9d76-dee76298cb34
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18300 52536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1830052536
Directory	/workspace/47.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/47.usbdev_phy_config_pinflip.1224468992
Short name	T2554
Test name
Test status
Simulation time	227027952 ps
CPU time	1.04 seconds
Started	Aug 01 06:19:42 PM PDT 24
Finished	Aug 01 06:19:43 PM PDT 24
Peak memory	206956 kb
Host	smart-648c82cd-97d9-4ed5-9400-7f9eb2b9985f
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1224468992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1224468992
Directory	/workspace/47.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.517607876
Short name	T1511
Test name
Test status
Simulation time	153084637 ps
CPU time	0.82 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206824 kb
Host	smart-d9926dc4-4444-4e44-82ce-85c6b36bb8bc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51760 7876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.517607876
Directory	/workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/47.usbdev_phy_pins_sense.1921477456
Short name	T1416
Test name
Test status
Simulation time	49723637 ps
CPU time	0.75 seconds
Started	Aug 01 06:19:40 PM PDT 24
Finished	Aug 01 06:19:41 PM PDT 24
Peak memory	206912 kb
Host	smart-5fa486ab-82c0-4c7f-98d4-0aef231771e7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19214 77456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.1921477456
Directory	/workspace/47.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/47.usbdev_pkt_buffer.2999517396
Short name	T2477
Test name
Test status
Simulation time	15953801323 ps
CPU time	47.43 seconds
Started	Aug 01 06:19:47 PM PDT 24
Finished	Aug 01 06:20:35 PM PDT 24
Peak memory	215388 kb
Host	smart-90a73c23-aede-4579-9d11-43aa3ce228a3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29995 17396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.2999517396
Directory	/workspace/47.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/47.usbdev_pkt_received.90866560
Short name	T304
Test name
Test status
Simulation time	213280357 ps
CPU time	0.91 seconds
Started	Aug 01 06:19:43 PM PDT 24
Finished	Aug 01 06:19:44 PM PDT 24
Peak memory	206956 kb
Host	smart-6de596c7-111f-4b1f-85ac-6dfcf4c977a6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90866 560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.90866560
Directory	/workspace/47.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/47.usbdev_pkt_sent.205698272
Short name	T685
Test name
Test status
Simulation time	221245264 ps
CPU time	1 seconds
Started	Aug 01 06:19:48 PM PDT 24
Finished	Aug 01 06:19:50 PM PDT 24
Peak memory	206960 kb
Host	smart-0d254e3e-c125-48c2-a786-9c99f15b2bd5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20569 8272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.205698272
Directory	/workspace/47.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/47.usbdev_random_length_in_transaction.1882469904
Short name	T1317
Test name
Test status
Simulation time	217846743 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	207192 kb
Host	smart-d147d96f-9bfb-4928-99ba-68107c9d0571
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18824 69904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1882469904
Directory	/workspace/47.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/47.usbdev_random_length_out_transaction.915295718
Short name	T2063
Test name
Test status
Simulation time	178324794 ps
CPU time	0.86 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206952 kb
Host	smart-65063ce5-5e70-4b93-8d8c-a0fb16aa7f5d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91529 5718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.915295718
Directory	/workspace/47.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/47.usbdev_rx_crc_err.1902964348
Short name	T1207
Test name
Test status
Simulation time	148662268 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206920 kb
Host	smart-763ab796-12cc-4a7f-a3ba-6a4e718cfec7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19029 64348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1902964348
Directory	/workspace/47.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/47.usbdev_rx_full.2746306722
Short name	T2200
Test name
Test status
Simulation time	386080113 ps
CPU time	1.29 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206948 kb
Host	smart-f7b739e5-056e-482e-bbce-543b00dbcb2b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27463 06722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.2746306722
Directory	/workspace/47.usbdev_rx_full/latest

Test location	/workspace/coverage/default/47.usbdev_setup_stage.1626414304
Short name	T1448
Test name
Test status
Simulation time	154295469 ps
CPU time	0.82 seconds
Started	Aug 01 06:19:47 PM PDT 24
Finished	Aug 01 06:19:48 PM PDT 24
Peak memory	206900 kb
Host	smart-3fac94de-2cc3-4167-8938-f7138edad1a4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16264 14304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.1626414304
Directory	/workspace/47.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/47.usbdev_setup_trans_ignored.2067284116
Short name	T30
Test name
Test status
Simulation time	160445584 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:46 PM PDT 24
Peak memory	206956 kb
Host	smart-bacbd21c-c2db-49b1-b3e9-d99fe3cc1980
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20672 84116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2067284116
Directory	/workspace/47.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/47.usbdev_smoke.3464315585
Short name	T2225
Test name
Test status
Simulation time	262051083 ps
CPU time	1.06 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206948 kb
Host	smart-d6bdcad7-6a85-45c0-b2b8-20ef1b3a2bb7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34643 15585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.3464315585
Directory	/workspace/47.usbdev_smoke/latest

Test location	/workspace/coverage/default/47.usbdev_spurious_pids_ignored.101420156
Short name	T795
Test name
Test status
Simulation time	3227507456 ps
CPU time	91.98 seconds
Started	Aug 01 06:19:42 PM PDT 24
Finished	Aug 01 06:21:14 PM PDT 24
Peak memory	217220 kb
Host	smart-44154d7a-1bf1-40a3-b131-6c6737a94097
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=101420156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.101420156
Directory	/workspace/47.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/47.usbdev_stall_priority_over_nak.3211555895
Short name	T2242
Test name
Test status
Simulation time	249373772 ps
CPU time	1.07 seconds
Started	Aug 01 06:19:40 PM PDT 24
Finished	Aug 01 06:19:42 PM PDT 24
Peak memory	206948 kb
Host	smart-c68e3cab-fd6d-48a4-842e-da931d65c67f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32115 55895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3211555895
Directory	/workspace/47.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/47.usbdev_stall_trans.3336540782
Short name	T166
Test name
Test status
Simulation time	206554203 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:19:46 PM PDT 24
Peak memory	206904 kb
Host	smart-a7f54591-4bdd-4916-8db5-eddefbc39a47
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33365 40782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3336540782
Directory	/workspace/47.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/47.usbdev_stream_len_max.920231529
Short name	T1749
Test name
Test status
Simulation time	1022364040 ps
CPU time	2.48 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	207120 kb
Host	smart-3a772750-2fee-4012-992d-d2754eb0de57
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92023 1529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.920231529
Directory	/workspace/47.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/47.usbdev_streaming_out.672980180
Short name	T2562
Test name
Test status
Simulation time	2582149781 ps
CPU time	19.67 seconds
Started	Aug 01 06:19:43 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	223520 kb
Host	smart-d857d71c-2dab-4312-8c5f-d2c6e5726ca7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67298 0180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.672980180
Directory	/workspace/47.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.2791769137
Short name	T767
Test name
Test status
Simulation time	749745801 ps
CPU time	15.76 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:20:01 PM PDT 24
Peak memory	207148 kb
Host	smart-0caf61e7-eb2a-4a8d-89dd-ffe1b0c6b08c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791769137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_hos t_handshake.2791769137
Directory	/workspace/47.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/48.usbdev_alert_test.1192296571
Short name	T659
Test name
Test status
Simulation time	98956727 ps
CPU time	0.69 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206992 kb
Host	smart-f7f2b797-019d-4b94-bcca-b453d02ba538
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1192296571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.1192296571
Directory	/workspace/48.usbdev_alert_test/latest

Test location	/workspace/coverage/default/48.usbdev_av_buffer.1388514413
Short name	T2621
Test name
Test status
Simulation time	159574756 ps
CPU time	0.83 seconds
Started	Aug 01 06:19:43 PM PDT 24
Finished	Aug 01 06:19:45 PM PDT 24
Peak memory	206952 kb
Host	smart-54646f3e-df4e-4a4f-8358-e7f30b1a102e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13885 14413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1388514413
Directory	/workspace/48.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/48.usbdev_bitstuff_err.4096249757
Short name	T2857
Test name
Test status
Simulation time	208466784 ps
CPU time	0.93 seconds
Started	Aug 01 06:19:49 PM PDT 24
Finished	Aug 01 06:19:50 PM PDT 24
Peak memory	206908 kb
Host	smart-b284d892-988b-470d-894b-44ce6ca852ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40962 49757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.4096249757
Directory	/workspace/48.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/48.usbdev_data_toggle_clear.2808012619
Short name	T2694
Test name
Test status
Simulation time	502160809 ps
CPU time	1.65 seconds
Started	Aug 01 06:19:42 PM PDT 24
Finished	Aug 01 06:19:44 PM PDT 24
Peak memory	206968 kb
Host	smart-11695a8f-cf29-4b65-8815-780ee2702c8d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28080 12619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.2808012619
Directory	/workspace/48.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/48.usbdev_data_toggle_restore.2665156019
Short name	T2401
Test name
Test status
Simulation time	777734353 ps
CPU time	2.02 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:46 PM PDT 24
Peak memory	206976 kb
Host	smart-9b2a5920-d0c4-4475-a9e1-e8de96e94239
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2665156019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2665156019
Directory	/workspace/48.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/48.usbdev_device_address.3837082665
Short name	T74
Test name
Test status
Simulation time	18286194608 ps
CPU time	31.2 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:20:16 PM PDT 24
Peak memory	207196 kb
Host	smart-843903e2-3991-4e81-ae73-8d5d7d284e31
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38370 82665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3837082665
Directory	/workspace/48.usbdev_device_address/latest

Test location	/workspace/coverage/default/48.usbdev_device_timeout.2345210397
Short name	T1371
Test name
Test status
Simulation time	1146796683 ps
CPU time	24.94 seconds
Started	Aug 01 06:19:52 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	207140 kb
Host	smart-8047a58c-b04e-436f-ab1a-95a7b694122f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345210397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.2345210397
Directory	/workspace/48.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/48.usbdev_disable_endpoint.332726467
Short name	T352
Test name
Test status
Simulation time	914865508 ps
CPU time	2.14 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:19:48 PM PDT 24
Peak memory	206956 kb
Host	smart-0d219b0b-4d24-4c3c-8705-5dd61e46f8dc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33272 6467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.332726467
Directory	/workspace/48.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/48.usbdev_disconnected.2244523472
Short name	T49
Test name
Test status
Simulation time	143021011 ps
CPU time	0.81 seconds
Started	Aug 01 06:19:50 PM PDT 24
Finished	Aug 01 06:19:51 PM PDT 24
Peak memory	206884 kb
Host	smart-47574454-c455-466d-90ef-2fddea2eeb1d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22445 23472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.2244523472
Directory	/workspace/48.usbdev_disconnected/latest

Test location	/workspace/coverage/default/48.usbdev_enable.1802456049
Short name	T2600
Test name
Test status
Simulation time	75329223 ps
CPU time	0.72 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206920 kb
Host	smart-17394da2-d262-4c60-b823-d408236486f9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18024 56049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1802456049
Directory	/workspace/48.usbdev_enable/latest

Test location	/workspace/coverage/default/48.usbdev_endpoint_access.1962102409
Short name	T2077
Test name
Test status
Simulation time	844557684 ps
CPU time	2.48 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:19:48 PM PDT 24
Peak memory	207152 kb
Host	smart-479a5a88-07da-4168-bf44-8b7d442d28de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19621 02409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1962102409
Directory	/workspace/48.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/48.usbdev_endpoint_types.1697500112
Short name	T316
Test name
Test status
Simulation time	964924553 ps
CPU time	1.86 seconds
Started	Aug 01 06:19:48 PM PDT 24
Finished	Aug 01 06:19:50 PM PDT 24
Peak memory	206936 kb
Host	smart-a48fe60f-df4a-4eea-916b-16d69e40f71c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1697500112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.1697500112
Directory	/workspace/48.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/48.usbdev_fifo_rst.1482436843
Short name	T2117
Test name
Test status
Simulation time	186056509 ps
CPU time	2.38 seconds
Started	Aug 01 06:19:45 PM PDT 24
Finished	Aug 01 06:19:48 PM PDT 24
Peak memory	207120 kb
Host	smart-b924ba22-e2ed-406a-9c6f-64fd457167c1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14824 36843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1482436843
Directory	/workspace/48.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/48.usbdev_in_iso.2711049878
Short name	T1754
Test name
Test status
Simulation time	247168946 ps
CPU time	1.19 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:48 PM PDT 24
Peak memory	215324 kb
Host	smart-f5511752-17cf-4cb8-8326-0b2a11a371df
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2711049878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2711049878
Directory	/workspace/48.usbdev_in_iso/latest

Test location	/workspace/coverage/default/48.usbdev_in_stall.1511964289
Short name	T623
Test name
Test status
Simulation time	166699174 ps
CPU time	0.81 seconds
Started	Aug 01 06:19:46 PM PDT 24
Finished	Aug 01 06:19:47 PM PDT 24
Peak memory	206932 kb
Host	smart-b8b1be68-8f21-4c1a-908f-081f30353b5c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15119 64289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1511964289
Directory	/workspace/48.usbdev_in_stall/latest

Test location	/workspace/coverage/default/48.usbdev_in_trans.3407526754
Short name	T720
Test name
Test status
Simulation time	187375274 ps
CPU time	0.93 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:19:45 PM PDT 24
Peak memory	206912 kb
Host	smart-77ceee68-70e9-4068-a8b7-c39047c66e89
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34075 26754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.3407526754
Directory	/workspace/48.usbdev_in_trans/latest

Test location	/workspace/coverage/default/48.usbdev_invalid_sync.3049813110
Short name	T1301
Test name
Test status
Simulation time	3621770082 ps
CPU time	101.04 seconds
Started	Aug 01 06:19:49 PM PDT 24
Finished	Aug 01 06:21:30 PM PDT 24
Peak memory	217048 kb
Host	smart-64b688b2-0da7-4a9e-82d0-d34d4d4d43d1
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3049813110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.3049813110
Directory	/workspace/48.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/48.usbdev_iso_retraction.3455117370
Short name	T2564
Test name
Test status
Simulation time	10242714162 ps
CPU time	61.97 seconds
Started	Aug 01 06:19:51 PM PDT 24
Finished	Aug 01 06:20:53 PM PDT 24
Peak memory	207148 kb
Host	smart-c91704f2-0e5b-4fb3-903f-5a1c947e50e4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3455117370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.3455117370
Directory	/workspace/48.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/48.usbdev_link_in_err.166871350
Short name	T2739
Test name
Test status
Simulation time	210306085 ps
CPU time	0.95 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206960 kb
Host	smart-1df6eb35-75aa-4466-a9f1-6bc5a25aa04e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16687 1350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.166871350
Directory	/workspace/48.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/48.usbdev_link_suspend.2725666287
Short name	T966
Test name
Test status
Simulation time	5955537063 ps
CPU time	7.87 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	207128 kb
Host	smart-457299b9-8562-4904-9101-12cdcbb8b8cb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27256 66287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.2725666287
Directory	/workspace/48.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/48.usbdev_low_speed_traffic.150767561
Short name	T1612
Test name
Test status
Simulation time	3281333917 ps
CPU time	93.19 seconds
Started	Aug 01 06:19:57 PM PDT 24
Finished	Aug 01 06:21:30 PM PDT 24
Peak memory	215380 kb
Host	smart-0098cae3-0276-434a-8e71-e9cb8232a6c5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15076 7561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.150767561
Directory	/workspace/48.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/48.usbdev_max_inter_pkt_delay.2196753745
Short name	T2420
Test name
Test status
Simulation time	2464004954 ps
CPU time	66.88 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:21:03 PM PDT 24
Peak memory	223512 kb
Host	smart-c08dd2b8-dfdf-4d30-95ef-f875dee899f3
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2196753745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.2196753745
Directory	/workspace/48.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/48.usbdev_max_length_in_transaction.1584077405
Short name	T2109
Test name
Test status
Simulation time	239427244 ps
CPU time	1.06 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206956 kb
Host	smart-71be12a6-060b-4d9e-8419-556c8b98eed0
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1584077405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1584077405
Directory	/workspace/48.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/48.usbdev_max_length_out_transaction.2985977642
Short name	T1419
Test name
Test status
Simulation time	271497820 ps
CPU time	1 seconds
Started	Aug 01 06:19:53 PM PDT 24
Finished	Aug 01 06:19:54 PM PDT 24
Peak memory	206964 kb
Host	smart-df4b3ae1-8b40-4eb4-acc8-c1b325588cfb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29859 77642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2985977642
Directory	/workspace/48.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2970502294
Short name	T1285
Test name
Test status
Simulation time	2823087043 ps
CPU time	21.01 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:20:16 PM PDT 24
Peak memory	215388 kb
Host	smart-6d886b59-288b-4f89-99d1-75fcbfb69f2e
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2970502294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2970502294
Directory	/workspace/48.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/48.usbdev_min_length_in_transaction.675322397
Short name	T2460
Test name
Test status
Simulation time	160976606 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:53 PM PDT 24
Finished	Aug 01 06:19:54 PM PDT 24
Peak memory	206800 kb
Host	smart-e2039160-3c14-41ec-a650-41923b037572
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=675322397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.675322397
Directory	/workspace/48.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/48.usbdev_min_length_out_transaction.3881542860
Short name	T2368
Test name
Test status
Simulation time	170802839 ps
CPU time	0.87 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206988 kb
Host	smart-6deb61fc-e1ab-4caa-bade-eaeb7e7aa0d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38815 42860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3881542860
Directory	/workspace/48.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/48.usbdev_nak_trans.1037254245
Short name	T2325
Test name
Test status
Simulation time	156831455 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:57 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206920 kb
Host	smart-0e15621c-abe5-4b31-8750-830ce4789f99
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10372 54245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1037254245
Directory	/workspace/48.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/48.usbdev_out_iso.1915728855
Short name	T1170
Test name
Test status
Simulation time	157255845 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:51 PM PDT 24
Finished	Aug 01 06:19:52 PM PDT 24
Peak memory	206936 kb
Host	smart-58e13dbe-244b-4b77-847e-b024ac5863d7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19157 28855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.1915728855
Directory	/workspace/48.usbdev_out_iso/latest

Test location	/workspace/coverage/default/48.usbdev_out_stall.2298316151
Short name	T1325
Test name
Test status
Simulation time	218189488 ps
CPU time	0.95 seconds
Started	Aug 01 06:19:59 PM PDT 24
Finished	Aug 01 06:20:00 PM PDT 24
Peak memory	206928 kb
Host	smart-c269058e-8c1a-48d2-a7e7-713c1bfbeb3d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22983 16151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.2298316151
Directory	/workspace/48.usbdev_out_stall/latest

Test location	/workspace/coverage/default/48.usbdev_out_trans_nak.2018442390
Short name	T2216
Test name
Test status
Simulation time	195078145 ps
CPU time	0.94 seconds
Started	Aug 01 06:20:01 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206924 kb
Host	smart-71633ed4-a6bd-4881-abe1-52f5aa1516fd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20184 42390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2018442390
Directory	/workspace/48.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/48.usbdev_pending_in_trans.1383404990
Short name	T1344
Test name
Test status
Simulation time	156146631 ps
CPU time	0.83 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:01 PM PDT 24
Peak memory	206972 kb
Host	smart-35ec48b7-0557-4d70-9717-7b383e4bc661
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13834 04990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1383404990
Directory	/workspace/48.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/48.usbdev_phy_config_pinflip.793657139
Short name	T2388
Test name
Test status
Simulation time	187605016 ps
CPU time	1.02 seconds
Started	Aug 01 06:20:01 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206964 kb
Host	smart-f5be56a6-f75b-4150-ad0d-947a2c6cfa8e
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=793657139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.793657139
Directory	/workspace/48.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3949974948
Short name	T2182
Test name
Test status
Simulation time	163533369 ps
CPU time	0.87 seconds
Started	Aug 01 06:19:53 PM PDT 24
Finished	Aug 01 06:19:54 PM PDT 24
Peak memory	206880 kb
Host	smart-bf2626af-5043-4462-beb8-b53e2a8eb41a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39499 74948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3949974948
Directory	/workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/48.usbdev_phy_pins_sense.2416331933
Short name	T1329
Test name
Test status
Simulation time	88049466 ps
CPU time	0.75 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:19:56 PM PDT 24
Peak memory	206908 kb
Host	smart-ed3c106b-8f41-4541-8ca9-0c762af371b5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24163 31933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2416331933
Directory	/workspace/48.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/48.usbdev_pkt_buffer.504027178
Short name	T2384
Test name
Test status
Simulation time	7952393076 ps
CPU time	22.24 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:20:18 PM PDT 24
Peak memory	219588 kb
Host	smart-7da5625f-399b-447a-b5da-e7210c6f0f9c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50402 7178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.504027178
Directory	/workspace/48.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/48.usbdev_pkt_received.3569458937
Short name	T1845
Test name
Test status
Simulation time	166412686 ps
CPU time	0.88 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206948 kb
Host	smart-edbbe129-3b0a-4992-9047-9cb97d17fbe9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35694 58937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3569458937
Directory	/workspace/48.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/48.usbdev_pkt_sent.861559188
Short name	T968
Test name
Test status
Simulation time	214525895 ps
CPU time	1 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:19:56 PM PDT 24
Peak memory	206880 kb
Host	smart-083b36e6-83a4-41ac-a190-9bdb9efdfd2d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86155 9188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.861559188
Directory	/workspace/48.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/48.usbdev_random_length_in_transaction.3795626355
Short name	T2147
Test name
Test status
Simulation time	191661414 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206960 kb
Host	smart-bd0ba04e-4b32-4d30-baab-cf47ad4a0d0c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37956 26355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.3795626355
Directory	/workspace/48.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/48.usbdev_random_length_out_transaction.2864577385
Short name	T849
Test name
Test status
Simulation time	214699037 ps
CPU time	0.98 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:19:56 PM PDT 24
Peak memory	206904 kb
Host	smart-ba2a924b-5bb3-4e9f-a25f-ae2f455c60c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28645 77385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.2864577385
Directory	/workspace/48.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/48.usbdev_rx_crc_err.1740013965
Short name	T1166
Test name
Test status
Simulation time	134584712 ps
CPU time	0.8 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206912 kb
Host	smart-e8b5c983-3d45-4103-9be7-696f6e69cda8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17400 13965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1740013965
Directory	/workspace/48.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/48.usbdev_rx_full.659868260
Short name	T901
Test name
Test status
Simulation time	358534183 ps
CPU time	1.27 seconds
Started	Aug 01 06:19:59 PM PDT 24
Finished	Aug 01 06:20:00 PM PDT 24
Peak memory	206956 kb
Host	smart-82d1be51-55ba-49a8-8594-d5473d8f897f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65986 8260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.659868260
Directory	/workspace/48.usbdev_rx_full/latest

Test location	/workspace/coverage/default/48.usbdev_setup_stage.3536466823
Short name	T1806
Test name
Test status
Simulation time	149734858 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206884 kb
Host	smart-f9de6251-0ded-4427-b0cb-0ac3e2fd0b4b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35364 66823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3536466823
Directory	/workspace/48.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/48.usbdev_setup_trans_ignored.2118278881
Short name	T1740
Test name
Test status
Simulation time	172083759 ps
CPU time	0.82 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:19:56 PM PDT 24
Peak memory	206964 kb
Host	smart-bf3faa00-7306-4a47-b4ee-9b809103d4e9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21182 78881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2118278881
Directory	/workspace/48.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/48.usbdev_smoke.4290620091
Short name	T1934
Test name
Test status
Simulation time	233768035 ps
CPU time	1 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206912 kb
Host	smart-9f72cb92-4d44-4b9a-87c0-e95dfa8d16a7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42906 20091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.4290620091
Directory	/workspace/48.usbdev_smoke/latest

Test location	/workspace/coverage/default/48.usbdev_spurious_pids_ignored.4116899299
Short name	T1303
Test name
Test status
Simulation time	2775821984 ps
CPU time	21.14 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	217212 kb
Host	smart-b8425355-fc5b-4db8-bcef-5859b2cc3ddf
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=4116899299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.4116899299
Directory	/workspace/48.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/48.usbdev_stall_priority_over_nak.2915886618
Short name	T1351
Test name
Test status
Simulation time	162130777 ps
CPU time	0.84 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206924 kb
Host	smart-cc55dc93-5294-4538-81f8-1baf97b4491e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29158 86618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2915886618
Directory	/workspace/48.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/48.usbdev_stall_trans.26812813
Short name	T2689
Test name
Test status
Simulation time	226836776 ps
CPU time	0.92 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206980 kb
Host	smart-cf06dd57-f0b5-42ef-9646-44234bff3db7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26812 813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.26812813
Directory	/workspace/48.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/48.usbdev_stream_len_max.4171675646
Short name	T1028
Test name
Test status
Simulation time	1122178504 ps
CPU time	2.73 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	207136 kb
Host	smart-0817ca25-d238-4ba5-97fb-3ecf4c52e66d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41716 75646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.4171675646
Directory	/workspace/48.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/48.usbdev_streaming_out.3734504295
Short name	T1428
Test name
Test status
Simulation time	2447210564 ps
CPU time	24.48 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:20:22 PM PDT 24
Peak memory	215408 kb
Host	smart-db0ad4e9-6290-40c1-91bb-08d919806b28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37345 04295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.3734504295
Directory	/workspace/48.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.1523387353
Short name	T1962
Test name
Test status
Simulation time	1204820060 ps
CPU time	25.67 seconds
Started	Aug 01 06:19:44 PM PDT 24
Finished	Aug 01 06:20:11 PM PDT 24
Peak memory	207160 kb
Host	smart-4775a6c3-a51d-4a83-ab01-8aa68d1ad9c5
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523387353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos t_handshake.1523387353
Directory	/workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/49.usbdev_alert_test.2246580612
Short name	T2319
Test name
Test status
Simulation time	38369310 ps
CPU time	0.68 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206992 kb
Host	smart-f1c86a6a-7b2c-4258-83bb-f499bc337f96
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2246580612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.2246580612
Directory	/workspace/49.usbdev_alert_test/latest

Test location	/workspace/coverage/default/49.usbdev_av_buffer.1082938823
Short name	T712
Test name
Test status
Simulation time	153281663 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206940 kb
Host	smart-aa817194-f418-48ce-a6d0-7a96c4444a07
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10829 38823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1082938823
Directory	/workspace/49.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/49.usbdev_bitstuff_err.429829380
Short name	T828
Test name
Test status
Simulation time	154384092 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:51 PM PDT 24
Finished	Aug 01 06:19:52 PM PDT 24
Peak memory	206920 kb
Host	smart-55d3d996-d22e-425a-8263-6a28a218035e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42982 9380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.429829380
Directory	/workspace/49.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/49.usbdev_data_toggle_clear.730105166
Short name	T1024
Test name
Test status
Simulation time	405824177 ps
CPU time	1.58 seconds
Started	Aug 01 06:19:57 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206924 kb
Host	smart-185279f7-6bbb-48df-bd84-a550a90c7f65
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73010 5166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.730105166
Directory	/workspace/49.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/49.usbdev_data_toggle_restore.2567580605
Short name	T2230
Test name
Test status
Simulation time	893151823 ps
CPU time	2.43 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	207096 kb
Host	smart-2187f408-f5cb-4aaa-ae92-36c6916c7c05
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2567580605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2567580605
Directory	/workspace/49.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/49.usbdev_device_address.2376968003
Short name	T215
Test name
Test status
Simulation time	57215128768 ps
CPU time	90.01 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:21:25 PM PDT 24
Peak memory	207188 kb
Host	smart-471c05a9-b01e-4f69-b1f3-c8f93fa00935
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23769 68003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.2376968003
Directory	/workspace/49.usbdev_device_address/latest

Test location	/workspace/coverage/default/49.usbdev_device_timeout.3388605733
Short name	T236
Test name
Test status
Simulation time	4947141150 ps
CPU time	34 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:20:32 PM PDT 24
Peak memory	207208 kb
Host	smart-6aea7e8c-f37e-46a3-a845-179ab9b7bcca
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388605733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.3388605733
Directory	/workspace/49.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/49.usbdev_disable_endpoint.1883760080
Short name	T2593
Test name
Test status
Simulation time	674081354 ps
CPU time	1.61 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206912 kb
Host	smart-e0f51686-d078-4f3c-b61c-8cef59974465
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18837 60080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1883760080
Directory	/workspace/49.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/49.usbdev_disconnected.3379967259
Short name	T922
Test name
Test status
Simulation time	141879837 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206892 kb
Host	smart-013351c5-7fd3-48fe-9f6d-17b2cc082d0a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33799 67259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.3379967259
Directory	/workspace/49.usbdev_disconnected/latest

Test location	/workspace/coverage/default/49.usbdev_enable.3525760259
Short name	T855
Test name
Test status
Simulation time	40246604 ps
CPU time	0.7 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206868 kb
Host	smart-0124e570-f360-4bc8-8f5d-850f050dffd1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35257 60259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3525760259
Directory	/workspace/49.usbdev_enable/latest

Test location	/workspace/coverage/default/49.usbdev_endpoint_access.209173827
Short name	T1785
Test name
Test status
Simulation time	890361368 ps
CPU time	2.37 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	207164 kb
Host	smart-b9133a76-3389-4fb5-a3c9-88bc15effb98
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20917 3827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.209173827
Directory	/workspace/49.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/49.usbdev_endpoint_types.141570987
Short name	T1320
Test name
Test status
Simulation time	367408145 ps
CPU time	1.21 seconds
Started	Aug 01 06:19:59 PM PDT 24
Finished	Aug 01 06:20:00 PM PDT 24
Peak memory	206940 kb
Host	smart-0ca180af-e669-4506-871a-99a37d89940c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=141570987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.141570987
Directory	/workspace/49.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/49.usbdev_fifo_rst.4171164921
Short name	T2830
Test name
Test status
Simulation time	255894395 ps
CPU time	1.96 seconds
Started	Aug 01 06:19:59 PM PDT 24
Finished	Aug 01 06:20:01 PM PDT 24
Peak memory	207112 kb
Host	smart-b59b6bd4-e919-4c88-948d-f2f538eb453c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41711 64921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4171164921
Directory	/workspace/49.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/49.usbdev_in_iso.774234898
Short name	T812
Test name
Test status
Simulation time	279757896 ps
CPU time	1.09 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	215348 kb
Host	smart-ae7c2ef7-0097-4957-8c5a-5f2e0cefcf99
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=774234898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.774234898
Directory	/workspace/49.usbdev_in_iso/latest

Test location	/workspace/coverage/default/49.usbdev_in_stall.3419091613
Short name	T811
Test name
Test status
Simulation time	200865275 ps
CPU time	0.87 seconds
Started	Aug 01 06:19:59 PM PDT 24
Finished	Aug 01 06:20:00 PM PDT 24
Peak memory	206928 kb
Host	smart-e85d87aa-1428-40df-bf08-4b627ff4990a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34190 91613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3419091613
Directory	/workspace/49.usbdev_in_stall/latest

Test location	/workspace/coverage/default/49.usbdev_in_trans.1837840750
Short name	T1928
Test name
Test status
Simulation time	198251179 ps
CPU time	0.94 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206960 kb
Host	smart-de55e9e8-213f-4af2-bf3d-a14cf95c95f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18378 40750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1837840750
Directory	/workspace/49.usbdev_in_trans/latest

Test location	/workspace/coverage/default/49.usbdev_invalid_sync.3357118762
Short name	T2688
Test name
Test status
Simulation time	3705720790 ps
CPU time	38.36 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:20:34 PM PDT 24
Peak memory	217132 kb
Host	smart-0b738664-381e-4db7-8057-d584133710dd
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3357118762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.3357118762
Directory	/workspace/49.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/49.usbdev_iso_retraction.59085326
Short name	T2124
Test name
Test status
Simulation time	10465087613 ps
CPU time	120.84 seconds
Started	Aug 01 06:19:57 PM PDT 24
Finished	Aug 01 06:21:58 PM PDT 24
Peak memory	207168 kb
Host	smart-27fdde3e-a098-429f-a67d-7567a4a4c575
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=59085326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.59085326
Directory	/workspace/49.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/49.usbdev_link_in_err.3854530686
Short name	T1002
Test name
Test status
Simulation time	202335119 ps
CPU time	0.94 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206964 kb
Host	smart-dcac8296-9cfd-4317-b544-fddbfb25e27c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38545 30686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.3854530686
Directory	/workspace/49.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/49.usbdev_link_suspend.1685051424
Short name	T2771
Test name
Test status
Simulation time	3292390173 ps
CPU time	5.4 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:07 PM PDT 24
Peak memory	215348 kb
Host	smart-50a1ade0-d628-4469-89b5-f41ffa458ad0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16850 51424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1685051424
Directory	/workspace/49.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/49.usbdev_low_speed_traffic.2113357104
Short name	T946
Test name
Test status
Simulation time	4510766895 ps
CPU time	41.17 seconds
Started	Aug 01 06:20:01 PM PDT 24
Finished	Aug 01 06:20:42 PM PDT 24
Peak memory	223492 kb
Host	smart-3e05b266-3a50-4b5e-aa4c-cd3247a808ff
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21133 57104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2113357104
Directory	/workspace/49.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/49.usbdev_max_inter_pkt_delay.2674170675
Short name	T806
Test name
Test status
Simulation time	2425952271 ps
CPU time	19.4 seconds
Started	Aug 01 06:20:05 PM PDT 24
Finished	Aug 01 06:20:25 PM PDT 24
Peak memory	223488 kb
Host	smart-6e42634a-6538-4b06-9baa-9f65eba5dcbc
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2674170675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.2674170675
Directory	/workspace/49.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/49.usbdev_max_length_in_transaction.2067249624
Short name	T2418
Test name
Test status
Simulation time	255625482 ps
CPU time	1.04 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:20:00 PM PDT 24
Peak memory	206956 kb
Host	smart-d719da22-f3e5-4d43-b139-ba322c9f3178
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2067249624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2067249624
Directory	/workspace/49.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/49.usbdev_max_length_out_transaction.500429273
Short name	T2157
Test name
Test status
Simulation time	202148631 ps
CPU time	0.95 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206976 kb
Host	smart-17001cc5-b0eb-4cd8-9b60-153b3fc76298
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50042 9273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.500429273
Directory	/workspace/49.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/49.usbdev_min_inter_pkt_delay.415425381
Short name	T877
Test name
Test status
Simulation time	2661979433 ps
CPU time	19.36 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:20 PM PDT 24
Peak memory	223492 kb
Host	smart-9fa7f93d-177f-46fc-9274-a10a9a12e3de
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=415425381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.415425381
Directory	/workspace/49.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/49.usbdev_min_length_in_transaction.3590539117
Short name	T1440
Test name
Test status
Simulation time	156188171 ps
CPU time	0.84 seconds
Started	Aug 01 06:19:57 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206944 kb
Host	smart-c10e9119-ada9-42db-8213-a08cedd8f132
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3590539117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.3590539117
Directory	/workspace/49.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/49.usbdev_min_length_out_transaction.3539282834
Short name	T2155
Test name
Test status
Simulation time	172601234 ps
CPU time	0.84 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206972 kb
Host	smart-2820e5d8-eb87-42b9-b989-3cf299572988
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35392 82834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3539282834
Directory	/workspace/49.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/49.usbdev_nak_trans.277204
Short name	T1287
Test name
Test status
Simulation time	215380991 ps
CPU time	1.07 seconds
Started	Aug 01 06:19:55 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206952 kb
Host	smart-de6416de-e7be-467c-8a1f-f76fa6de149f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27720 4 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.277204
Directory	/workspace/49.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/49.usbdev_out_iso.2582373935
Short name	T775
Test name
Test status
Simulation time	202041032 ps
CPU time	0.97 seconds
Started	Aug 01 06:19:57 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206952 kb
Host	smart-8e96a57f-f23e-49cd-bcb9-0cf998b1e64a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25823 73935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2582373935
Directory	/workspace/49.usbdev_out_iso/latest

Test location	/workspace/coverage/default/49.usbdev_out_stall.1843017533
Short name	T2206
Test name
Test status
Simulation time	226813948 ps
CPU time	0.96 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206940 kb
Host	smart-b0a20a30-401c-485c-8026-d2b81eec21df
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18430 17533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1843017533
Directory	/workspace/49.usbdev_out_stall/latest

Test location	/workspace/coverage/default/49.usbdev_out_trans_nak.2399889797
Short name	T527
Test name
Test status
Simulation time	155732329 ps
CPU time	0.83 seconds
Started	Aug 01 06:19:53 PM PDT 24
Finished	Aug 01 06:19:54 PM PDT 24
Peak memory	206928 kb
Host	smart-7f1a7522-1e36-487d-85d0-d7df5418af5c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23998 89797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2399889797
Directory	/workspace/49.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/49.usbdev_pending_in_trans.3270949989
Short name	T2395
Test name
Test status
Simulation time	150530136 ps
CPU time	0.88 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206980 kb
Host	smart-936a7238-0d84-4bee-a539-2c20ebe2516b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32709 49989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3270949989
Directory	/workspace/49.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/49.usbdev_phy_config_pinflip.1357200707
Short name	T1132
Test name
Test status
Simulation time	269557749 ps
CPU time	1.07 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206956 kb
Host	smart-52e8cac8-ad24-45ce-b293-7ec9c664de1f
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1357200707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1357200707
Directory	/workspace/49.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2648479740
Short name	T143
Test name
Test status
Simulation time	166150763 ps
CPU time	0.95 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206956 kb
Host	smart-68d773cf-8f68-46a7-b2f4-b853c32bb141
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26484 79740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2648479740
Directory	/workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/49.usbdev_pkt_buffer.3967472286
Short name	T2828
Test name
Test status
Simulation time	15034571860 ps
CPU time	34.71 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:20:31 PM PDT 24
Peak memory	219876 kb
Host	smart-a1ffe59e-1206-4cf1-a2ff-a789dd020dbb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39674 72286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3967472286
Directory	/workspace/49.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/49.usbdev_pkt_received.2671174062
Short name	T1535
Test name
Test status
Simulation time	183477786 ps
CPU time	0.94 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206988 kb
Host	smart-0f537643-3b6e-4541-beac-fd264e2bcbbd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26711 74062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2671174062
Directory	/workspace/49.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/49.usbdev_pkt_sent.1755525923
Short name	T1380
Test name
Test status
Simulation time	240996142 ps
CPU time	1.01 seconds
Started	Aug 01 06:19:54 PM PDT 24
Finished	Aug 01 06:19:55 PM PDT 24
Peak memory	206888 kb
Host	smart-c93275df-fccd-4650-a390-ae26782a2449
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17555 25923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1755525923
Directory	/workspace/49.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/49.usbdev_random_length_in_transaction.4099266095
Short name	T1457
Test name
Test status
Simulation time	168915945 ps
CPU time	0.9 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206916 kb
Host	smart-67628a74-d28a-4151-b86d-d070e0ce1523
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40992 66095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.4099266095
Directory	/workspace/49.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/49.usbdev_random_length_out_transaction.1029470069
Short name	T496
Test name
Test status
Simulation time	174824393 ps
CPU time	0.93 seconds
Started	Aug 01 06:19:54 PM PDT 24
Finished	Aug 01 06:19:55 PM PDT 24
Peak memory	206952 kb
Host	smart-68f2c24b-9e54-479f-b02f-22d659353ce2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10294 70069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1029470069
Directory	/workspace/49.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/49.usbdev_rx_crc_err.676366275
Short name	T2598
Test name
Test status
Simulation time	177059899 ps
CPU time	0.93 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206968 kb
Host	smart-78285b4c-2ed4-4cef-9e4e-b182632dae9a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67636 6275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.676366275
Directory	/workspace/49.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/49.usbdev_rx_full.3905091156
Short name	T2240
Test name
Test status
Simulation time	252916751 ps
CPU time	1.03 seconds
Started	Aug 01 06:19:54 PM PDT 24
Finished	Aug 01 06:19:55 PM PDT 24
Peak memory	206940 kb
Host	smart-c33742f8-a617-4da2-b332-80dbb8e5ceb6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39050 91156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.3905091156
Directory	/workspace/49.usbdev_rx_full/latest

Test location	/workspace/coverage/default/49.usbdev_setup_stage.299238816
Short name	T2682
Test name
Test status
Simulation time	170601024 ps
CPU time	0.89 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206916 kb
Host	smart-54f40d20-5615-4912-8faa-828e6aa3aefd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29923 8816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.299238816
Directory	/workspace/49.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/49.usbdev_setup_trans_ignored.460275945
Short name	T2259
Test name
Test status
Simulation time	172389291 ps
CPU time	0.86 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206960 kb
Host	smart-d9bfa924-dbc1-4c8b-bdf2-df233616b71a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46027 5945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.460275945
Directory	/workspace/49.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/49.usbdev_smoke.3665494304
Short name	T1278
Test name
Test status
Simulation time	223833838 ps
CPU time	1.02 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206952 kb
Host	smart-5e50c2c1-dfe2-4de3-8820-87f36344c70b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36654 94304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3665494304
Directory	/workspace/49.usbdev_smoke/latest

Test location	/workspace/coverage/default/49.usbdev_spurious_pids_ignored.2802579337
Short name	T1192
Test name
Test status
Simulation time	2882972103 ps
CPU time	28.6 seconds
Started	Aug 01 06:19:54 PM PDT 24
Finished	Aug 01 06:20:23 PM PDT 24
Peak memory	217084 kb
Host	smart-5ef3e7b3-7d0e-4375-a2c1-02c6ed3a1938
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2802579337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.2802579337
Directory	/workspace/49.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/49.usbdev_stall_priority_over_nak.2518874662
Short name	T165
Test name
Test status
Simulation time	164126733 ps
CPU time	0.85 seconds
Started	Aug 01 06:19:57 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206928 kb
Host	smart-0823bb29-5e00-47d4-a2fe-9c7a52662feb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25188 74662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2518874662
Directory	/workspace/49.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/49.usbdev_stall_trans.1543792101
Short name	T1895
Test name
Test status
Simulation time	218254599 ps
CPU time	0.95 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206948 kb
Host	smart-1d5445a8-c5ae-4cb4-830e-b19492106e79
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15437 92101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1543792101
Directory	/workspace/49.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/49.usbdev_stream_len_max.1262409607
Short name	T1568
Test name
Test status
Simulation time	1202940200 ps
CPU time	2.9 seconds
Started	Aug 01 06:19:54 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	207112 kb
Host	smart-efbb1faa-7905-426e-9f85-0af9e31aed36
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12624 09607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1262409607
Directory	/workspace/49.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/49.usbdev_streaming_out.2643822086
Short name	T2187
Test name
Test status
Simulation time	4086270592 ps
CPU time	31.07 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:33 PM PDT 24
Peak memory	215428 kb
Host	smart-749e74fa-13f9-4834-8dce-5e5f39c659c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26438 22086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2643822086
Directory	/workspace/49.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.998136304
Short name	T1211
Test name
Test status
Simulation time	874141203 ps
CPU time	19 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:20:15 PM PDT 24
Peak memory	207080 kb
Host	smart-0008e964-1b7f-44a4-b30f-c218446df977
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998136304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_host _handshake.998136304
Directory	/workspace/49.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/5.usbdev_alert_test.3859647301
Short name	T1590
Test name
Test status
Simulation time	91530195 ps
CPU time	0.76 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	206984 kb
Host	smart-25f1dc7c-2863-4b27-8b77-231fc208cc93
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=3859647301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3859647301
Directory	/workspace/5.usbdev_alert_test/latest

Test location	/workspace/coverage/default/5.usbdev_av_buffer.497765868
Short name	T1484
Test name
Test status
Simulation time	162505653 ps
CPU time	0.86 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	206968 kb
Host	smart-c830634b-657c-443d-a7ae-33ef543886d1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49776 5868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.497765868
Directory	/workspace/5.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/5.usbdev_bitstuff_err.2717165337
Short name	T1704
Test name
Test status
Simulation time	140541987 ps
CPU time	0.91 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:10 PM PDT 24
Peak memory	206872 kb
Host	smart-c367bf95-eb49-4523-8043-f6e7671adfd1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27171 65337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2717165337
Directory	/workspace/5.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/5.usbdev_data_toggle_clear.180765469
Short name	T2654
Test name
Test status
Simulation time	224470873 ps
CPU time	1.01 seconds
Started	Aug 01 06:12:06 PM PDT 24
Finished	Aug 01 06:12:07 PM PDT 24
Peak memory	206948 kb
Host	smart-b3e7fb29-f46b-4f72-ab2a-7fbf053f0851
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18076 5469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.180765469
Directory	/workspace/5.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/5.usbdev_data_toggle_restore.1022701146
Short name	T1312
Test name
Test status
Simulation time	317742499 ps
CPU time	1.16 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:12 PM PDT 24
Peak memory	206904 kb
Host	smart-f9e631dd-919c-48ab-b06f-2e120bbd9165
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1022701146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1022701146
Directory	/workspace/5.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/5.usbdev_device_address.1562458903
Short name	T2448
Test name
Test status
Simulation time	52580745290 ps
CPU time	82.5 seconds
Started	Aug 01 06:12:13 PM PDT 24
Finished	Aug 01 06:13:36 PM PDT 24
Peak memory	207180 kb
Host	smart-d7f6bbb2-6029-46fb-a1d5-a961b365c872
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15624 58903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1562458903
Directory	/workspace/5.usbdev_device_address/latest

Test location	/workspace/coverage/default/5.usbdev_device_timeout.3463496658
Short name	T1067
Test name
Test status
Simulation time	2935636659 ps
CPU time	24.79 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:34 PM PDT 24
Peak memory	207232 kb
Host	smart-22688089-4b9d-4859-a35e-72a1078cc013
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463496658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.3463496658
Directory	/workspace/5.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/5.usbdev_disable_endpoint.256874045
Short name	T2734
Test name
Test status
Simulation time	647053078 ps
CPU time	1.67 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:12 PM PDT 24
Peak memory	206872 kb
Host	smart-3f55caba-a408-40d4-a44a-2e84d80d2a2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25687 4045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.256874045
Directory	/workspace/5.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/5.usbdev_disconnected.1756767686
Short name	T1241
Test name
Test status
Simulation time	176897383 ps
CPU time	0.87 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:10 PM PDT 24
Peak memory	206872 kb
Host	smart-b450d09d-9b44-4450-9c97-70c90613d1c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17567 67686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1756767686
Directory	/workspace/5.usbdev_disconnected/latest

Test location	/workspace/coverage/default/5.usbdev_enable.2551489610
Short name	T2209
Test name
Test status
Simulation time	46469233 ps
CPU time	0.7 seconds
Started	Aug 01 06:12:15 PM PDT 24
Finished	Aug 01 06:12:16 PM PDT 24
Peak memory	206896 kb
Host	smart-a1d01821-9463-40cc-b8a5-9457b8ee7c67
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25514 89610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2551489610
Directory	/workspace/5.usbdev_enable/latest

Test location	/workspace/coverage/default/5.usbdev_endpoint_access.3687530276
Short name	T1361
Test name
Test status
Simulation time	1005280869 ps
CPU time	2.79 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:13 PM PDT 24
Peak memory	207072 kb
Host	smart-f74f7ff9-4e2d-49db-b8b2-799cbaa7cfa5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36875 30276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3687530276
Directory	/workspace/5.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/5.usbdev_endpoint_types.1088395221
Short name	T373
Test name
Test status
Simulation time	525966579 ps
CPU time	1.47 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	206948 kb
Host	smart-52d75ad7-3c0c-47ca-83a6-763cb1e46f47
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1088395221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.1088395221
Directory	/workspace/5.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/5.usbdev_fifo_rst.1228334457
Short name	T2265
Test name
Test status
Simulation time	162729939 ps
CPU time	1.62 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	207112 kb
Host	smart-1091b5d7-c8ce-4df9-8f09-139393393543
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12283 34457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1228334457
Directory	/workspace/5.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/5.usbdev_in_iso.1055092019
Short name	T2618
Test name
Test status
Simulation time	191860261 ps
CPU time	0.91 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:10 PM PDT 24
Peak memory	206920 kb
Host	smart-0f3e8003-3236-4969-9527-1c1b359791d9
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1055092019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.1055092019
Directory	/workspace/5.usbdev_in_iso/latest

Test location	/workspace/coverage/default/5.usbdev_in_stall.3160445525
Short name	T2114
Test name
Test status
Simulation time	191145433 ps
CPU time	0.85 seconds
Started	Aug 01 06:12:15 PM PDT 24
Finished	Aug 01 06:12:16 PM PDT 24
Peak memory	206904 kb
Host	smart-7c132d97-552d-43de-836c-934b58bd0af8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31604 45525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.3160445525
Directory	/workspace/5.usbdev_in_stall/latest

Test location	/workspace/coverage/default/5.usbdev_in_trans.2572879982
Short name	T1364
Test name
Test status
Simulation time	211956136 ps
CPU time	1 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:12:14 PM PDT 24
Peak memory	206964 kb
Host	smart-a3e85f17-efae-49e1-85cd-60772524048c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25728 79982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.2572879982
Directory	/workspace/5.usbdev_in_trans/latest

Test location	/workspace/coverage/default/5.usbdev_invalid_sync.3621295829
Short name	T1850
Test name
Test status
Simulation time	4861771952 ps
CPU time	47.95 seconds
Started	Aug 01 06:12:08 PM PDT 24
Finished	Aug 01 06:12:57 PM PDT 24
Peak memory	223488 kb
Host	smart-f6958237-c2f3-4ee0-a4a3-2af0384d955a
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3621295829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3621295829
Directory	/workspace/5.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/5.usbdev_iso_retraction.201093470
Short name	T1849
Test name
Test status
Simulation time	10682722626 ps
CPU time	137.91 seconds
Started	Aug 01 06:12:07 PM PDT 24
Finished	Aug 01 06:14:25 PM PDT 24
Peak memory	207104 kb
Host	smart-7a884c77-bc1f-4487-a12f-a11a3386d437
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=201093470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.201093470
Directory	/workspace/5.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/5.usbdev_link_in_err.1805018851
Short name	T1259
Test name
Test status
Simulation time	196793101 ps
CPU time	0.97 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:12:13 PM PDT 24
Peak memory	206920 kb
Host	smart-b360e113-cbd3-40a1-b89d-eb1ec6206b8d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18050 18851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1805018851
Directory	/workspace/5.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/5.usbdev_link_suspend.588394388
Short name	T93
Test name
Test status
Simulation time	9159489391 ps
CPU time	12.53 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:22 PM PDT 24
Peak memory	207156 kb
Host	smart-78d37c7c-59de-48de-bfc7-1c2c8e19de01
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58839 4388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.588394388
Directory	/workspace/5.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/5.usbdev_low_speed_traffic.2216017199
Short name	T2558
Test name
Test status
Simulation time	4112370697 ps
CPU time	41.56 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:51 PM PDT 24
Peak memory	217768 kb
Host	smart-42c94681-d675-411e-b6fa-dce8c66de74b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22160 17199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.2216017199
Directory	/workspace/5.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3978775985
Short name	T1239
Test name
Test status
Simulation time	4153619209 ps
CPU time	119.67 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:14:09 PM PDT 24
Peak memory	216756 kb
Host	smart-e16fea7a-268d-43b9-8b93-2aee77f910f0
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3978775985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3978775985
Directory	/workspace/5.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/5.usbdev_max_length_in_transaction.206514920
Short name	T1746
Test name
Test status
Simulation time	243006742 ps
CPU time	1.08 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:10 PM PDT 24
Peak memory	206952 kb
Host	smart-81a47cd8-c4d1-4122-852d-0b9cf6c85f0f
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=206514920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.206514920
Directory	/workspace/5.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/5.usbdev_max_length_out_transaction.2490327167
Short name	T1696
Test name
Test status
Simulation time	190094909 ps
CPU time	0.94 seconds
Started	Aug 01 06:12:08 PM PDT 24
Finished	Aug 01 06:12:09 PM PDT 24
Peak memory	206928 kb
Host	smart-cdcd307d-7cf1-4d2e-8ba4-3cf42874fdf7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24903 27167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.2490327167
Directory	/workspace/5.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.645317283
Short name	T5
Test name
Test status
Simulation time	2921264149 ps
CPU time	91.35 seconds
Started	Aug 01 06:12:13 PM PDT 24
Finished	Aug 01 06:13:44 PM PDT 24
Peak memory	217112 kb
Host	smart-bd4e8382-7634-4838-88d3-f3567a9ea064
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64531 7283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.645317283
Directory	/workspace/5.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/5.usbdev_min_inter_pkt_delay.2162920847
Short name	T1374
Test name
Test status
Simulation time	3599831037 ps
CPU time	36.15 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:46 PM PDT 24
Peak memory	216976 kb
Host	smart-b33dcea7-566d-4393-b911-435cdb4bed95
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2162920847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.2162920847
Directory	/workspace/5.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/5.usbdev_min_length_in_transaction.3759736348
Short name	T1148
Test name
Test status
Simulation time	188642663 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:07 PM PDT 24
Finished	Aug 01 06:12:08 PM PDT 24
Peak memory	206932 kb
Host	smart-b1a0472c-f1d2-44a5-86b3-1856c16e2391
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3759736348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3759736348
Directory	/workspace/5.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/5.usbdev_min_length_out_transaction.4053700861
Short name	T1999
Test name
Test status
Simulation time	168546528 ps
CPU time	0.84 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:12:14 PM PDT 24
Peak memory	206936 kb
Host	smart-401fe1fb-90ca-434e-b196-15c9eaaf800b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40537 00861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.4053700861
Directory	/workspace/5.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/5.usbdev_nak_trans.1536925653
Short name	T1304
Test name
Test status
Simulation time	198349083 ps
CPU time	0.9 seconds
Started	Aug 01 06:12:11 PM PDT 24
Finished	Aug 01 06:12:12 PM PDT 24
Peak memory	206964 kb
Host	smart-da1ae171-314a-4372-b745-489da5523304
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15369 25653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1536925653
Directory	/workspace/5.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/5.usbdev_out_iso.865640425
Short name	T2514
Test name
Test status
Simulation time	205070979 ps
CPU time	1 seconds
Started	Aug 01 06:12:11 PM PDT 24
Finished	Aug 01 06:12:12 PM PDT 24
Peak memory	206920 kb
Host	smart-d1a42c8c-0997-403c-8b37-894b60005848
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86564 0425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.865640425
Directory	/workspace/5.usbdev_out_iso/latest

Test location	/workspace/coverage/default/5.usbdev_out_stall.2505734972
Short name	T1277
Test name
Test status
Simulation time	174120445 ps
CPU time	0.93 seconds
Started	Aug 01 06:12:13 PM PDT 24
Finished	Aug 01 06:12:14 PM PDT 24
Peak memory	206964 kb
Host	smart-8cffa7a4-dcc2-4393-a0be-5c515b2d524d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25057 34972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2505734972
Directory	/workspace/5.usbdev_out_stall/latest

Test location	/workspace/coverage/default/5.usbdev_out_trans_nak.2218826475
Short name	T672
Test name
Test status
Simulation time	168244744 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:12 PM PDT 24
Peak memory	206880 kb
Host	smart-97fc3782-d1bb-446c-82b0-c70a49eb4477
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22188 26475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2218826475
Directory	/workspace/5.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/5.usbdev_pending_in_trans.3530970050
Short name	T217
Test name
Test status
Simulation time	144586962 ps
CPU time	0.85 seconds
Started	Aug 01 06:12:11 PM PDT 24
Finished	Aug 01 06:12:12 PM PDT 24
Peak memory	206968 kb
Host	smart-5c75e183-563e-4c6b-89ee-14a13ba75e04
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35309 70050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3530970050
Directory	/workspace/5.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/5.usbdev_phy_config_pinflip.2104043763
Short name	T539
Test name
Test status
Simulation time	192504890 ps
CPU time	0.96 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	206928 kb
Host	smart-0bbb561e-eddf-4206-81f9-98faba5ef354
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2104043763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2104043763
Directory	/workspace/5.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.3948216930
Short name	T2070
Test name
Test status
Simulation time	147202665 ps
CPU time	0.88 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:12:13 PM PDT 24
Peak memory	206944 kb
Host	smart-cfc60d9b-aa5b-4829-b3ad-e0cd45f8bd91
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39482 16930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.3948216930
Directory	/workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/5.usbdev_phy_pins_sense.3896275857
Short name	T2662
Test name
Test status
Simulation time	56309297 ps
CPU time	0.71 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	206864 kb
Host	smart-ab102da8-9776-412e-8179-87935c6a2c4c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38962 75857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.3896275857
Directory	/workspace/5.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/5.usbdev_pkt_buffer.3981243344
Short name	T1482
Test name
Test status
Simulation time	16272567693 ps
CPU time	46.06 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:12:58 PM PDT 24
Peak memory	223564 kb
Host	smart-1591a7ad-f90b-4f0f-a135-5987efe98726
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39812 43344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3981243344
Directory	/workspace/5.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/5.usbdev_pkt_received.2632791999
Short name	T2733
Test name
Test status
Simulation time	163137647 ps
CPU time	0.88 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:12:13 PM PDT 24
Peak memory	206944 kb
Host	smart-35ddc7ac-4ab0-49f0-a644-86b56b13af84
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26327 91999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2632791999
Directory	/workspace/5.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/5.usbdev_pkt_sent.3375418736
Short name	T2796
Test name
Test status
Simulation time	255352658 ps
CPU time	1.01 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:12:13 PM PDT 24
Peak memory	206924 kb
Host	smart-a7f9c3e4-cc46-4a94-98f3-6a62a4e75d36
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33754 18736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3375418736
Directory	/workspace/5.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/5.usbdev_rand_bus_disconnects.1513212795
Short name	T2160
Test name
Test status
Simulation time	5394520140 ps
CPU time	23.88 seconds
Started	Aug 01 06:12:15 PM PDT 24
Finished	Aug 01 06:12:39 PM PDT 24
Peak memory	223576 kb
Host	smart-8b872f76-7ed9-49e2-b0a4-8f1fd47fd6d7
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513212795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1513212795
Directory	/workspace/5.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/5.usbdev_rand_bus_resets.604517626
Short name	T2355
Test name
Test status
Simulation time	10864891820 ps
CPU time	79.04 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:13:31 PM PDT 24
Peak memory	223580 kb
Host	smart-bd163f82-e19d-4b41-be26-b09bf3ca3c0a
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604517626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.604517626
Directory	/workspace/5.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/5.usbdev_random_length_in_transaction.4160429073
Short name	T788
Test name
Test status
Simulation time	155127958 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:13 PM PDT 24
Finished	Aug 01 06:12:14 PM PDT 24
Peak memory	206944 kb
Host	smart-1a0bc85c-86d3-4491-a2d6-c1e39f386568
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41604 29073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.4160429073
Directory	/workspace/5.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/5.usbdev_random_length_out_transaction.277749165
Short name	T1328
Test name
Test status
Simulation time	183837164 ps
CPU time	0.9 seconds
Started	Aug 01 06:12:14 PM PDT 24
Finished	Aug 01 06:12:15 PM PDT 24
Peak memory	206912 kb
Host	smart-3ebeff3e-661a-4074-848a-78170912d783
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27774 9165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.277749165
Directory	/workspace/5.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/5.usbdev_rx_crc_err.652920206
Short name	T68
Test name
Test status
Simulation time	144109815 ps
CPU time	0.81 seconds
Started	Aug 01 06:12:13 PM PDT 24
Finished	Aug 01 06:12:14 PM PDT 24
Peak memory	206936 kb
Host	smart-05d50d20-06ea-4f20-9ede-c647c7e79860
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65292 0206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.652920206
Directory	/workspace/5.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/5.usbdev_rx_full.1469840057
Short name	T1500
Test name
Test status
Simulation time	306303918 ps
CPU time	1.22 seconds
Started	Aug 01 06:12:14 PM PDT 24
Finished	Aug 01 06:12:15 PM PDT 24
Peak memory	206908 kb
Host	smart-8bfc3edb-12f4-487c-a6bb-8ff64da378e4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14698 40057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.1469840057
Directory	/workspace/5.usbdev_rx_full/latest

Test location	/workspace/coverage/default/5.usbdev_setup_stage.4021651921
Short name	T207
Test name
Test status
Simulation time	147334041 ps
CPU time	0.8 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	206888 kb
Host	smart-186232a3-8b36-4612-9b00-8884529abfb8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40216 51921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.4021651921
Directory	/workspace/5.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/5.usbdev_setup_trans_ignored.3415546152
Short name	T1844
Test name
Test status
Simulation time	162651932 ps
CPU time	0.83 seconds
Started	Aug 01 06:12:09 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	206936 kb
Host	smart-d14baccc-48e0-440e-a3cf-5a816415e149
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34155 46152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3415546152
Directory	/workspace/5.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/5.usbdev_smoke.5059059
Short name	T902
Test name
Test status
Simulation time	187967871 ps
CPU time	0.92 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:12:13 PM PDT 24
Peak memory	206912 kb
Host	smart-2ef70317-f756-4fa9-82da-0d4d008468d6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50590 59 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.5059059
Directory	/workspace/5.usbdev_smoke/latest

Test location	/workspace/coverage/default/5.usbdev_spurious_pids_ignored.947998365
Short name	T677
Test name
Test status
Simulation time	2560814141 ps
CPU time	69.55 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	215388 kb
Host	smart-808ba0e8-de87-443c-9ead-0b2689601260
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=947998365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.947998365
Directory	/workspace/5.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/5.usbdev_stall_priority_over_nak.3068516270
Short name	T717
Test name
Test status
Simulation time	166276428 ps
CPU time	0.84 seconds
Started	Aug 01 06:12:14 PM PDT 24
Finished	Aug 01 06:12:15 PM PDT 24
Peak memory	206916 kb
Host	smart-d58bc4fd-da00-489c-ad72-ffd3b7acffca
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30685 16270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3068516270
Directory	/workspace/5.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/5.usbdev_stall_trans.130755775
Short name	T823
Test name
Test status
Simulation time	175123906 ps
CPU time	0.86 seconds
Started	Aug 01 06:12:14 PM PDT 24
Finished	Aug 01 06:12:15 PM PDT 24
Peak memory	206972 kb
Host	smart-33704253-4f12-462e-b2f0-d1c6e2971b06
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13075 5775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.130755775
Directory	/workspace/5.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/5.usbdev_stream_len_max.2904318267
Short name	T1976
Test name
Test status
Simulation time	1067079836 ps
CPU time	2.61 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:13 PM PDT 24
Peak memory	207184 kb
Host	smart-fee80aad-82dc-4107-9d3a-aee2147cbf38
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29043 18267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2904318267
Directory	/workspace/5.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/5.usbdev_streaming_out.4223986698
Short name	T2470
Test name
Test status
Simulation time	2028623284 ps
CPU time	54.14 seconds
Started	Aug 01 06:12:15 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	215272 kb
Host	smart-93abe71f-89a1-4f8a-9438-d1ebe8b1e019
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42239 86698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.4223986698
Directory	/workspace/5.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.361773916
Short name	T2837
Test name
Test status
Simulation time	6323706605 ps
CPU time	42.99 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:53 PM PDT 24
Peak memory	207148 kb
Host	smart-6c5f31db-e7f1-466c-b449-64c5d6b3e415
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361773916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host_ handshake.361773916
Directory	/workspace/5.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/50.usbdev_endpoint_types.2515496423
Short name	T295
Test name
Test status
Simulation time	412619531 ps
CPU time	1.19 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206892 kb
Host	smart-642567ce-7306-41ac-b9ea-55d4652eadd9
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2515496423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.2515496423
Directory	/workspace/50.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/51.usbdev_endpoint_types.866177503
Short name	T2747
Test name
Test status
Simulation time	465278786 ps
CPU time	1.33 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206940 kb
Host	smart-32eb99be-94f9-49d2-9a58-e9e01bd6c168
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=866177503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.866177503
Directory	/workspace/51.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/52.usbdev_endpoint_types.3527074357
Short name	T2748
Test name
Test status
Simulation time	231382145 ps
CPU time	0.97 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206924 kb
Host	smart-22c3e04d-a37f-448f-a095-980edb1392b8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3527074357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.3527074357
Directory	/workspace/52.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/53.usbdev_endpoint_types.1200687895
Short name	T394
Test name
Test status
Simulation time	315029208 ps
CPU time	1.1 seconds
Started	Aug 01 06:20:06 PM PDT 24
Finished	Aug 01 06:20:07 PM PDT 24
Peak memory	206872 kb
Host	smart-d8dd2118-fe67-4944-9d70-3cc1d16ae4d0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1200687895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.1200687895
Directory	/workspace/53.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/54.usbdev_endpoint_types.1026428939
Short name	T366
Test name
Test status
Simulation time	482138471 ps
CPU time	1.5 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206896 kb
Host	smart-b4b18a2a-6715-427f-98da-39ae41fdb33a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1026428939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.1026428939
Directory	/workspace/54.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/55.usbdev_endpoint_types.1140854976
Short name	T317
Test name
Test status
Simulation time	463708435 ps
CPU time	1.48 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206920 kb
Host	smart-8efbf551-5dab-4ee8-bcb4-2092d172b1ec
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1140854976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.1140854976
Directory	/workspace/55.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/57.usbdev_endpoint_types.1545626515
Short name	T434
Test name
Test status
Simulation time	380255809 ps
CPU time	1.23 seconds
Started	Aug 01 06:19:59 PM PDT 24
Finished	Aug 01 06:20:01 PM PDT 24
Peak memory	206940 kb
Host	smart-8f67f25b-d84a-4d7c-bb7c-0c362216c3dd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1545626515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.1545626515
Directory	/workspace/57.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/58.usbdev_endpoint_types.4260944811
Short name	T332
Test name
Test status
Simulation time	476721659 ps
CPU time	1.41 seconds
Started	Aug 01 06:20:01 PM PDT 24
Finished	Aug 01 06:20:02 PM PDT 24
Peak memory	206896 kb
Host	smart-6389c49f-3969-4323-bb7e-693e052809e5
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4260944811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.4260944811
Directory	/workspace/58.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/59.usbdev_endpoint_types.3167593201
Short name	T2445
Test name
Test status
Simulation time	577598836 ps
CPU time	1.65 seconds
Started	Aug 01 06:20:08 PM PDT 24
Finished	Aug 01 06:20:10 PM PDT 24
Peak memory	206944 kb
Host	smart-5372f76d-7afb-42b3-8ddc-ecd05d47527d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3167593201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.3167593201
Directory	/workspace/59.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/6.usbdev_alert_test.953478119
Short name	T941
Test name
Test status
Simulation time	38712103 ps
CPU time	0.69 seconds
Started	Aug 01 06:12:20 PM PDT 24
Finished	Aug 01 06:12:20 PM PDT 24
Peak memory	206988 kb
Host	smart-d67b764e-8fc0-4e83-870d-34224719e9c7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=953478119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.953478119
Directory	/workspace/6.usbdev_alert_test/latest

Test location	/workspace/coverage/default/6.usbdev_av_buffer.3991171738
Short name	T991
Test name
Test status
Simulation time	154750273 ps
CPU time	0.83 seconds
Started	Aug 01 06:12:12 PM PDT 24
Finished	Aug 01 06:12:14 PM PDT 24
Peak memory	206984 kb
Host	smart-8b4ac172-c774-4bf2-a9b8-7aec0754b955
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39911 71738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3991171738
Directory	/workspace/6.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/6.usbdev_bitstuff_err.3026840709
Short name	T975
Test name
Test status
Simulation time	148513325 ps
CPU time	0.84 seconds
Started	Aug 01 06:12:11 PM PDT 24
Finished	Aug 01 06:12:12 PM PDT 24
Peak memory	206876 kb
Host	smart-9879fc50-8f7e-4cbe-a0a9-f9872462bda2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30268 40709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.3026840709
Directory	/workspace/6.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/6.usbdev_data_toggle_clear.3870683954
Short name	T1854
Test name
Test status
Simulation time	175592622 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:10 PM PDT 24
Finished	Aug 01 06:12:11 PM PDT 24
Peak memory	206972 kb
Host	smart-843614b4-75c5-41dc-8f51-dd8ff2cb4bb9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38706 83954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3870683954
Directory	/workspace/6.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/6.usbdev_data_toggle_restore.3524973084
Short name	T642
Test name
Test status
Simulation time	1178500139 ps
CPU time	3.2 seconds
Started	Aug 01 06:12:11 PM PDT 24
Finished	Aug 01 06:12:14 PM PDT 24
Peak memory	207132 kb
Host	smart-b3453113-163a-4c96-a916-ab8480c4a6ac
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3524973084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3524973084
Directory	/workspace/6.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/6.usbdev_device_address.2715456111
Short name	T220
Test name
Test status
Simulation time	34588761104 ps
CPU time	50.46 seconds
Started	Aug 01 06:12:14 PM PDT 24
Finished	Aug 01 06:13:05 PM PDT 24
Peak memory	207136 kb
Host	smart-a1488c87-2dc7-42fe-865e-08b3ff421ae9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27154 56111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.2715456111
Directory	/workspace/6.usbdev_device_address/latest

Test location	/workspace/coverage/default/6.usbdev_device_timeout.5853048
Short name	T1022
Test name
Test status
Simulation time	2926442898 ps
CPU time	27.19 seconds
Started	Aug 01 06:12:20 PM PDT 24
Finished	Aug 01 06:12:47 PM PDT 24
Peak memory	207216 kb
Host	smart-24dabb9c-6943-4991-a8ca-d0afd3fa20c9
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5853048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.5853048
Directory	/workspace/6.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/6.usbdev_disable_endpoint.1624364195
Short name	T888
Test name
Test status
Simulation time	1090209929 ps
CPU time	2.22 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:25 PM PDT 24
Peak memory	206892 kb
Host	smart-50d72cc6-53aa-47e4-a241-9b792f104603
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16243 64195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.1624364195
Directory	/workspace/6.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/6.usbdev_disconnected.3302547791
Short name	T613
Test name
Test status
Simulation time	212628398 ps
CPU time	0.86 seconds
Started	Aug 01 06:12:20 PM PDT 24
Finished	Aug 01 06:12:22 PM PDT 24
Peak memory	206888 kb
Host	smart-925045c7-b3ef-4bb3-bd12-f2a3cde5abf7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33025 47791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3302547791
Directory	/workspace/6.usbdev_disconnected/latest

Test location	/workspace/coverage/default/6.usbdev_enable.2950159696
Short name	T2779
Test name
Test status
Simulation time	38563415 ps
CPU time	0.73 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:21 PM PDT 24
Peak memory	206916 kb
Host	smart-458ce3bc-8537-4809-b871-23f4bbc389f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29501 59696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2950159696
Directory	/workspace/6.usbdev_enable/latest

Test location	/workspace/coverage/default/6.usbdev_endpoint_access.3442964907
Short name	T2711
Test name
Test status
Simulation time	786316756 ps
CPU time	2.2 seconds
Started	Aug 01 06:12:24 PM PDT 24
Finished	Aug 01 06:12:26 PM PDT 24
Peak memory	207184 kb
Host	smart-94cd5b61-6ab2-4f1e-a10c-24a86b40623c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34429 64907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.3442964907
Directory	/workspace/6.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/6.usbdev_endpoint_types.3323231369
Short name	T423
Test name
Test status
Simulation time	426661272 ps
CPU time	1.36 seconds
Started	Aug 01 06:12:20 PM PDT 24
Finished	Aug 01 06:12:22 PM PDT 24
Peak memory	206940 kb
Host	smart-f9e14ec9-f1c3-42ce-a8ee-cb1c40ef2838
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3323231369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.3323231369
Directory	/workspace/6.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/6.usbdev_fifo_rst.2971528400
Short name	T1765
Test name
Test status
Simulation time	195335016 ps
CPU time	2.32 seconds
Started	Aug 01 06:12:23 PM PDT 24
Finished	Aug 01 06:12:26 PM PDT 24
Peak memory	206988 kb
Host	smart-b11acc10-1222-42df-b6a0-d36224801ab0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29715 28400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2971528400
Directory	/workspace/6.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/6.usbdev_in_iso.1342495371
Short name	T1674
Test name
Test status
Simulation time	213406588 ps
CPU time	1.08 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:23 PM PDT 24
Peak memory	207164 kb
Host	smart-25d8b4c7-a82e-494e-ab37-df1eae787f07
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1342495371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1342495371
Directory	/workspace/6.usbdev_in_iso/latest

Test location	/workspace/coverage/default/6.usbdev_in_stall.3447135184
Short name	T1918
Test name
Test status
Simulation time	138565483 ps
CPU time	0.82 seconds
Started	Aug 01 06:12:24 PM PDT 24
Finished	Aug 01 06:12:25 PM PDT 24
Peak memory	206936 kb
Host	smart-70c1a7eb-fc40-4884-9294-cd36fd31c20d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34471 35184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3447135184
Directory	/workspace/6.usbdev_in_stall/latest

Test location	/workspace/coverage/default/6.usbdev_in_trans.3867230777
Short name	T2031
Test name
Test status
Simulation time	202533123 ps
CPU time	0.98 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:22 PM PDT 24
Peak memory	206804 kb
Host	smart-ac39bd68-9fde-4477-95fc-59939a1a2e59
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38672 30777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3867230777
Directory	/workspace/6.usbdev_in_trans/latest

Test location	/workspace/coverage/default/6.usbdev_invalid_sync.3611525304
Short name	T772
Test name
Test status
Simulation time	3102722681 ps
CPU time	86.68 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:13:49 PM PDT 24
Peak memory	217248 kb
Host	smart-905d31a9-64c9-4659-8e1e-e06732ae250c
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3611525304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.3611525304
Directory	/workspace/6.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/6.usbdev_iso_retraction.1775036533
Short name	T993
Test name
Test status
Simulation time	7390688280 ps
CPU time	50.62 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:13:12 PM PDT 24
Peak memory	207172 kb
Host	smart-0c01647c-d9c8-45c2-a8ea-934a44dfc309
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1775036533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.1775036533
Directory	/workspace/6.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/6.usbdev_link_in_err.2122330008
Short name	T2570
Test name
Test status
Simulation time	255083191 ps
CPU time	1.08 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:23 PM PDT 24
Peak memory	207168 kb
Host	smart-0f50da4d-0e7d-4964-93ef-7cf29c2c6a6d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21223 30008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2122330008
Directory	/workspace/6.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/6.usbdev_link_suspend.2124508535
Short name	T2149
Test name
Test status
Simulation time	9593096217 ps
CPU time	11.33 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:33 PM PDT 24
Peak memory	207096 kb
Host	smart-0b6f310f-6c16-4c8b-ab89-1bd33c522998
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21245 08535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.2124508535
Directory	/workspace/6.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/6.usbdev_low_speed_traffic.1375378973
Short name	T1009
Test name
Test status
Simulation time	2729445709 ps
CPU time	25.03 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:48 PM PDT 24
Peak memory	223460 kb
Host	smart-ece58400-2438-48ee-a66a-255edbf2feee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753 78973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.1375378973
Directory	/workspace/6.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/6.usbdev_max_inter_pkt_delay.424956510
Short name	T1858
Test name
Test status
Simulation time	2379669611 ps
CPU time	22.58 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:44 PM PDT 24
Peak memory	217064 kb
Host	smart-1afc9e7b-39aa-49a3-9fcb-44a22c659c39
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=424956510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.424956510
Directory	/workspace/6.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/6.usbdev_max_length_in_transaction.557131454
Short name	T1673
Test name
Test status
Simulation time	249982475 ps
CPU time	1.03 seconds
Started	Aug 01 06:12:23 PM PDT 24
Finished	Aug 01 06:12:24 PM PDT 24
Peak memory	206952 kb
Host	smart-10282a05-76df-4d83-b56b-0859e6f7fe9f
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=557131454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.557131454
Directory	/workspace/6.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/6.usbdev_max_length_out_transaction.4142878113
Short name	T506
Test name
Test status
Simulation time	186845525 ps
CPU time	0.93 seconds
Started	Aug 01 06:12:23 PM PDT 24
Finished	Aug 01 06:12:25 PM PDT 24
Peak memory	206936 kb
Host	smart-9ddc1548-7e22-4bf4-9a77-3523619d0588
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41428 78113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.4142878113
Directory	/workspace/6.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.3716390392
Short name	T202
Test name
Test status
Simulation time	3036120999 ps
CPU time	86.25 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:13:47 PM PDT 24
Peak memory	223244 kb
Host	smart-6a44b3a7-9e24-4c26-b9ae-a7cfee24044c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37163 90392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.3716390392
Directory	/workspace/6.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/6.usbdev_max_usb_traffic.2099546112
Short name	T2792
Test name
Test status
Simulation time	2654810213 ps
CPU time	21.12 seconds
Started	Aug 01 06:12:23 PM PDT 24
Finished	Aug 01 06:12:44 PM PDT 24
Peak memory	223572 kb
Host	smart-fb90e9a7-ab79-4981-81b7-158904fceea5
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2099546112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2099546112
Directory	/workspace/6.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/6.usbdev_min_inter_pkt_delay.142419884
Short name	T1759
Test name
Test status
Simulation time	3139240000 ps
CPU time	88.71 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:13:51 PM PDT 24
Peak memory	216724 kb
Host	smart-c9dc7c01-2638-4cb4-aa6f-c8cec541c0d0
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=142419884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.142419884
Directory	/workspace/6.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/6.usbdev_min_length_in_transaction.2995340809
Short name	T2121
Test name
Test status
Simulation time	218395319 ps
CPU time	1.03 seconds
Started	Aug 01 06:12:25 PM PDT 24
Finished	Aug 01 06:12:27 PM PDT 24
Peak memory	206960 kb
Host	smart-f61a2bc4-1435-48b7-820f-f2fa2931006a
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2995340809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2995340809
Directory	/workspace/6.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/6.usbdev_min_length_out_transaction.2438709322
Short name	T899
Test name
Test status
Simulation time	189936668 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:22 PM PDT 24
Peak memory	206964 kb
Host	smart-9b7a2fa0-d8a9-4751-b5c7-0ba07a18dc86
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24387 09322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2438709322
Directory	/workspace/6.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/6.usbdev_nak_trans.3919370981
Short name	T177
Test name
Test status
Simulation time	205635648 ps
CPU time	0.92 seconds
Started	Aug 01 06:12:23 PM PDT 24
Finished	Aug 01 06:12:24 PM PDT 24
Peak memory	206920 kb
Host	smart-06d3da21-36e8-458f-9d3b-e2dd35b32602
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39193 70981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3919370981
Directory	/workspace/6.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/6.usbdev_out_iso.1023537726
Short name	T1720
Test name
Test status
Simulation time	177332880 ps
CPU time	0.92 seconds
Started	Aug 01 06:12:20 PM PDT 24
Finished	Aug 01 06:12:22 PM PDT 24
Peak memory	206908 kb
Host	smart-790f3a17-b437-4ec4-842b-1f31d803ceb4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10235 37726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.1023537726
Directory	/workspace/6.usbdev_out_iso/latest

Test location	/workspace/coverage/default/6.usbdev_out_stall.4192060275
Short name	T436
Test name
Test status
Simulation time	200419408 ps
CPU time	0.91 seconds
Started	Aug 01 06:12:28 PM PDT 24
Finished	Aug 01 06:12:29 PM PDT 24
Peak memory	206944 kb
Host	smart-15d1f8c4-6446-48fe-86b9-a49ae05d5ed5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41920 60275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.4192060275
Directory	/workspace/6.usbdev_out_stall/latest

Test location	/workspace/coverage/default/6.usbdev_out_trans_nak.786137444
Short name	T1586
Test name
Test status
Simulation time	212352998 ps
CPU time	0.97 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:23 PM PDT 24
Peak memory	206904 kb
Host	smart-466ed8ff-ae69-42fd-b30a-d1cc37fc4132
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78613 7444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.786137444
Directory	/workspace/6.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/6.usbdev_pending_in_trans.832028725
Short name	T2037
Test name
Test status
Simulation time	150871745 ps
CPU time	0.85 seconds
Started	Aug 01 06:12:20 PM PDT 24
Finished	Aug 01 06:12:21 PM PDT 24
Peak memory	206932 kb
Host	smart-ddd71d4b-443c-4474-be64-714c57691f63
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83202 8725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.832028725
Directory	/workspace/6.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/6.usbdev_phy_config_pinflip.2624609844
Short name	T2014
Test name
Test status
Simulation time	262186046 ps
CPU time	1.05 seconds
Started	Aug 01 06:12:27 PM PDT 24
Finished	Aug 01 06:12:28 PM PDT 24
Peak memory	206972 kb
Host	smart-b2771a8e-3b17-4beb-9366-d0dff2565cdc
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2624609844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.2624609844
Directory	/workspace/6.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.437860068
Short name	T994
Test name
Test status
Simulation time	149870883 ps
CPU time	0.84 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:22 PM PDT 24
Peak memory	206848 kb
Host	smart-c7ddafd4-9d1c-41fb-abf2-ca8959607c20
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43786 0068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.437860068
Directory	/workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/6.usbdev_phy_pins_sense.1707235394
Short name	T1436
Test name
Test status
Simulation time	28183894 ps
CPU time	0.7 seconds
Started	Aug 01 06:12:23 PM PDT 24
Finished	Aug 01 06:12:24 PM PDT 24
Peak memory	207128 kb
Host	smart-6107c7a0-9318-47c1-8ae6-3e95812a949d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17072 35394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1707235394
Directory	/workspace/6.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/6.usbdev_pkt_buffer.1410315255
Short name	T2071
Test name
Test status
Simulation time	6634059428 ps
CPU time	16.73 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:38 PM PDT 24
Peak memory	219856 kb
Host	smart-4c409427-23bd-45e1-918c-c06bceee6829
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14103 15255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1410315255
Directory	/workspace/6.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/6.usbdev_pkt_received.2752633286
Short name	T2296
Test name
Test status
Simulation time	219993181 ps
CPU time	0.97 seconds
Started	Aug 01 06:12:23 PM PDT 24
Finished	Aug 01 06:12:24 PM PDT 24
Peak memory	206960 kb
Host	smart-d41ea4cb-ed2e-4a20-9c77-2edbdd36193e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27526 33286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2752633286
Directory	/workspace/6.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/6.usbdev_pkt_sent.2295678679
Short name	T1700
Test name
Test status
Simulation time	173495126 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:24 PM PDT 24
Peak memory	206936 kb
Host	smart-cf019c05-38a8-45ea-a7a4-05533b18c17a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956 78679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2295678679
Directory	/workspace/6.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/6.usbdev_rand_bus_disconnects.3534551142
Short name	T2201
Test name
Test status
Simulation time	6912126420 ps
CPU time	41.49 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:13:03 PM PDT 24
Peak memory	223516 kb
Host	smart-31f66430-fe9a-43ac-be51-b63f56747a15
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534551142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.3534551142
Directory	/workspace/6.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/6.usbdev_rand_bus_resets.875365019
Short name	T44
Test name
Test status
Simulation time	6743754077 ps
CPU time	33.29 seconds
Started	Aug 01 06:12:20 PM PDT 24
Finished	Aug 01 06:12:54 PM PDT 24
Peak memory	218508 kb
Host	smart-33f9f40c-02e6-42eb-bbea-3b76bf5982dd
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875365019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.875365019
Directory	/workspace/6.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/6.usbdev_rand_suspends.2063260078
Short name	T457
Test name
Test status
Simulation time	10812035431 ps
CPU time	62.46 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:13:24 PM PDT 24
Peak memory	215344 kb
Host	smart-ad0e32c5-72fe-45a7-bc7e-5d5a15c495a7
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063260078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2063260078
Directory	/workspace/6.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/6.usbdev_random_length_in_transaction.545494281
Short name	T1885
Test name
Test status
Simulation time	255654823 ps
CPU time	1.06 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:24 PM PDT 24
Peak memory	206964 kb
Host	smart-c006173d-4455-482e-8ab1-e42d354d7636
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54549 4281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.545494281
Directory	/workspace/6.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/6.usbdev_random_length_out_transaction.4148299039
Short name	T857
Test name
Test status
Simulation time	207726785 ps
CPU time	0.91 seconds
Started	Aug 01 06:12:27 PM PDT 24
Finished	Aug 01 06:12:28 PM PDT 24
Peak memory	206968 kb
Host	smart-9947a857-b046-4799-9c76-3dd7691694fe
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41482 99039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.4148299039
Directory	/workspace/6.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/6.usbdev_rx_crc_err.1722398148
Short name	T1881
Test name
Test status
Simulation time	163269190 ps
CPU time	0.84 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:22 PM PDT 24
Peak memory	206956 kb
Host	smart-c5297518-2d8f-424c-a958-7e1a656f7598
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17223 98148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1722398148
Directory	/workspace/6.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/6.usbdev_rx_full.3528802667
Short name	T1231
Test name
Test status
Simulation time	318797406 ps
CPU time	1.25 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:23 PM PDT 24
Peak memory	206948 kb
Host	smart-95c55777-549c-44f9-9096-d32f8d7322d9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35288 02667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.3528802667
Directory	/workspace/6.usbdev_rx_full/latest

Test location	/workspace/coverage/default/6.usbdev_setup_stage.375510211
Short name	T2691
Test name
Test status
Simulation time	177741279 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:23 PM PDT 24
Peak memory	206900 kb
Host	smart-cbf0a29a-be4d-470b-a90e-8e8573156021
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551 0211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.375510211
Directory	/workspace/6.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/6.usbdev_setup_trans_ignored.1334454467
Short name	T2720
Test name
Test status
Simulation time	152722480 ps
CPU time	0.83 seconds
Started	Aug 01 06:12:23 PM PDT 24
Finished	Aug 01 06:12:24 PM PDT 24
Peak memory	206880 kb
Host	smart-123bd052-9fd0-44db-b62a-8af36dc5edb3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13344 54467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1334454467
Directory	/workspace/6.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/6.usbdev_smoke.2604149486
Short name	T653
Test name
Test status
Simulation time	207228901 ps
CPU time	1 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:22 PM PDT 24
Peak memory	206932 kb
Host	smart-bafd3444-30c5-420e-b677-b10785421b0d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26041 49486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.2604149486
Directory	/workspace/6.usbdev_smoke/latest

Test location	/workspace/coverage/default/6.usbdev_spurious_pids_ignored.1046966225
Short name	T937
Test name
Test status
Simulation time	2856463589 ps
CPU time	83.61 seconds
Started	Aug 01 06:12:25 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	217252 kb
Host	smart-9a0e54ea-6f9a-4096-b673-9a63600ed608
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1046966225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.1046966225
Directory	/workspace/6.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/6.usbdev_stall_priority_over_nak.3878953670
Short name	T1489
Test name
Test status
Simulation time	146871000 ps
CPU time	0.88 seconds
Started	Aug 01 06:12:20 PM PDT 24
Finished	Aug 01 06:12:21 PM PDT 24
Peak memory	206928 kb
Host	smart-4b5bf414-de46-4598-9c7b-a0abb4e2cf31
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38789 53670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3878953670
Directory	/workspace/6.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/6.usbdev_stall_trans.1682723091
Short name	T1147
Test name
Test status
Simulation time	182675044 ps
CPU time	0.9 seconds
Started	Aug 01 06:12:25 PM PDT 24
Finished	Aug 01 06:12:26 PM PDT 24
Peak memory	206948 kb
Host	smart-cf9b624b-4fc2-4603-9080-2f588d9b5a69
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16827 23091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1682723091
Directory	/workspace/6.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/6.usbdev_stream_len_max.2178273934
Short name	T1142
Test name
Test status
Simulation time	243508326 ps
CPU time	1 seconds
Started	Aug 01 06:12:27 PM PDT 24
Finished	Aug 01 06:12:28 PM PDT 24
Peak memory	206932 kb
Host	smart-6bc87294-8703-4122-ab0c-bba536cf828d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21782 73934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.2178273934
Directory	/workspace/6.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/6.usbdev_streaming_out.1349190103
Short name	T563
Test name
Test status
Simulation time	2195834824 ps
CPU time	59.8 seconds
Started	Aug 01 06:12:25 PM PDT 24
Finished	Aug 01 06:13:25 PM PDT 24
Peak memory	216512 kb
Host	smart-1ca8401d-d0a3-465a-8244-3ec2970817f9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13491 90103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.1349190103
Directory	/workspace/6.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.2730166269
Short name	T2474
Test name
Test status
Simulation time	828471450 ps
CPU time	19.41 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:40 PM PDT 24
Peak memory	207088 kb
Host	smart-1b44da87-44c4-46e8-baed-0ada3b4d68fd
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730166269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host _handshake.2730166269
Directory	/workspace/6.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/60.usbdev_endpoint_types.3553617172
Short name	T369
Test name
Test status
Simulation time	568090388 ps
CPU time	1.63 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:06 PM PDT 24
Peak memory	206876 kb
Host	smart-616d31e6-7d19-43ed-887c-be20eec237e8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3553617172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.3553617172
Directory	/workspace/60.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/61.usbdev_endpoint_types.2480719329
Short name	T2861
Test name
Test status
Simulation time	322030281 ps
CPU time	1.07 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206872 kb
Host	smart-b75623da-a927-4b93-9d34-8c536a195d87
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2480719329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.2480719329
Directory	/workspace/61.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/62.usbdev_endpoint_types.503886607
Short name	T425
Test name
Test status
Simulation time	323446830 ps
CPU time	1.19 seconds
Started	Aug 01 06:20:05 PM PDT 24
Finished	Aug 01 06:20:06 PM PDT 24
Peak memory	206896 kb
Host	smart-a9501cd3-4871-45f3-bc58-21aaca23be36
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=503886607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.503886607
Directory	/workspace/62.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/63.usbdev_endpoint_types.538533825
Short name	T313
Test name
Test status
Simulation time	701258804 ps
CPU time	1.77 seconds
Started	Aug 01 06:20:08 PM PDT 24
Finished	Aug 01 06:20:10 PM PDT 24
Peak memory	206944 kb
Host	smart-389ca7cc-fa9e-4898-b4bb-3fa6efcb857a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=538533825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.538533825
Directory	/workspace/63.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/65.usbdev_endpoint_types.895110977
Short name	T334
Test name
Test status
Simulation time	420973030 ps
CPU time	1.34 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206972 kb
Host	smart-dbc14a5c-d126-454e-95d8-176e3be33668
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=895110977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.895110977
Directory	/workspace/65.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/66.usbdev_endpoint_types.3904237655
Short name	T350
Test name
Test status
Simulation time	497507410 ps
CPU time	1.44 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206972 kb
Host	smart-797d6b54-40eb-4719-a641-cbdf9882e0aa
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3904237655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.3904237655
Directory	/workspace/66.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/67.usbdev_endpoint_types.2346831805
Short name	T324
Test name
Test status
Simulation time	660919141 ps
CPU time	1.68 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206916 kb
Host	smart-25284477-9acc-47df-ab86-3e47a7ff81d0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2346831805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.2346831805
Directory	/workspace/67.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/68.usbdev_endpoint_types.3968693055
Short name	T391
Test name
Test status
Simulation time	200862584 ps
CPU time	0.94 seconds
Started	Aug 01 06:19:56 PM PDT 24
Finished	Aug 01 06:19:57 PM PDT 24
Peak memory	206908 kb
Host	smart-a495975a-e309-4612-9147-6177561a35de
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3968693055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.3968693055
Directory	/workspace/68.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/69.usbdev_endpoint_types.997965983
Short name	T2578
Test name
Test status
Simulation time	298572331 ps
CPU time	1.06 seconds
Started	Aug 01 06:20:05 PM PDT 24
Finished	Aug 01 06:20:06 PM PDT 24
Peak memory	206908 kb
Host	smart-3736586d-415c-44ca-8da3-6233beb59170
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=997965983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.997965983
Directory	/workspace/69.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/7.usbdev_alert_test.1266812834
Short name	T1534
Test name
Test status
Simulation time	37110979 ps
CPU time	0.64 seconds
Started	Aug 01 06:12:35 PM PDT 24
Finished	Aug 01 06:12:36 PM PDT 24
Peak memory	206908 kb
Host	smart-24a9e82a-762e-4445-b2c3-c4cc67841e2e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1266812834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1266812834
Directory	/workspace/7.usbdev_alert_test/latest

Test location	/workspace/coverage/default/7.usbdev_av_buffer.2818448934
Short name	T2346
Test name
Test status
Simulation time	196511565 ps
CPU time	0.98 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:23 PM PDT 24
Peak memory	206964 kb
Host	smart-5f484b1e-5803-4924-9c44-5c4b30e49d46
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184 48934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2818448934
Directory	/workspace/7.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/7.usbdev_bitstuff_err.2188355055
Short name	T2178
Test name
Test status
Simulation time	150536363 ps
CPU time	0.81 seconds
Started	Aug 01 06:12:26 PM PDT 24
Finished	Aug 01 06:12:27 PM PDT 24
Peak memory	206888 kb
Host	smart-7c44aa3c-c8d5-4474-82e8-ce963a32d365
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21883 55055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.2188355055
Directory	/workspace/7.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/7.usbdev_data_toggle_clear.3971554729
Short name	T713
Test name
Test status
Simulation time	505736678 ps
CPU time	1.64 seconds
Started	Aug 01 06:12:24 PM PDT 24
Finished	Aug 01 06:12:26 PM PDT 24
Peak memory	206976 kb
Host	smart-683d4e70-7f35-49da-907d-f35913db6b96
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715 54729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3971554729
Directory	/workspace/7.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/7.usbdev_data_toggle_restore.3547208104
Short name	T1831
Test name
Test status
Simulation time	827309385 ps
CPU time	2.23 seconds
Started	Aug 01 06:12:26 PM PDT 24
Finished	Aug 01 06:12:29 PM PDT 24
Peak memory	207168 kb
Host	smart-4eec9841-939b-4d35-9e34-f9fc040a2a12
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3547208104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3547208104
Directory	/workspace/7.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/7.usbdev_device_address.3718924387
Short name	T2422
Test name
Test status
Simulation time	48090213901 ps
CPU time	71.38 seconds
Started	Aug 01 06:12:20 PM PDT 24
Finished	Aug 01 06:13:32 PM PDT 24
Peak memory	207124 kb
Host	smart-3caa1599-b77d-4180-abb8-eadaac62c8c4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37189 24387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.3718924387
Directory	/workspace/7.usbdev_device_address/latest

Test location	/workspace/coverage/default/7.usbdev_device_timeout.2879821358
Short name	T2107
Test name
Test status
Simulation time	2604567575 ps
CPU time	18.26 seconds
Started	Aug 01 06:12:21 PM PDT 24
Finished	Aug 01 06:12:39 PM PDT 24
Peak memory	207160 kb
Host	smart-fd98c7cb-cfb3-433e-b83b-83d0ec50d7ad
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879821358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.2879821358
Directory	/workspace/7.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/7.usbdev_disable_endpoint.869932029
Short name	T2658
Test name
Test status
Simulation time	957666988 ps
CPU time	2.34 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:24 PM PDT 24
Peak memory	206968 kb
Host	smart-831e6dd3-de84-4bc1-a8c4-c649c192e865
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86993 2029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.869932029
Directory	/workspace/7.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/7.usbdev_disconnected.3560086911
Short name	T2532
Test name
Test status
Simulation time	137523983 ps
CPU time	0.85 seconds
Started	Aug 01 06:12:26 PM PDT 24
Finished	Aug 01 06:12:27 PM PDT 24
Peak memory	206928 kb
Host	smart-b510aa35-196a-46bf-a402-9a6dc83672bf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35600 86911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.3560086911
Directory	/workspace/7.usbdev_disconnected/latest

Test location	/workspace/coverage/default/7.usbdev_enable.1898999123
Short name	T1447
Test name
Test status
Simulation time	43246213 ps
CPU time	0.74 seconds
Started	Aug 01 06:12:23 PM PDT 24
Finished	Aug 01 06:12:24 PM PDT 24
Peak memory	206920 kb
Host	smart-3a3b4b61-39a0-48e1-80d0-451fc1656f5d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18989 99123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.1898999123
Directory	/workspace/7.usbdev_enable/latest

Test location	/workspace/coverage/default/7.usbdev_endpoint_access.1879376512
Short name	T2222
Test name
Test status
Simulation time	859137475 ps
CPU time	2.31 seconds
Started	Aug 01 06:12:28 PM PDT 24
Finished	Aug 01 06:12:31 PM PDT 24
Peak memory	207092 kb
Host	smart-0a26ae70-f54c-4cae-b287-2a723a1994ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18793 76512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1879376512
Directory	/workspace/7.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/7.usbdev_endpoint_types.570736177
Short name	T330
Test name
Test status
Simulation time	389247828 ps
CPU time	1.19 seconds
Started	Aug 01 06:12:22 PM PDT 24
Finished	Aug 01 06:12:23 PM PDT 24
Peak memory	206828 kb
Host	smart-d973285b-74b7-4c8e-983f-9e25b31111a4
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=570736177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.570736177
Directory	/workspace/7.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/7.usbdev_fifo_rst.764855156
Short name	T2870
Test name
Test status
Simulation time	219933582 ps
CPU time	2.28 seconds
Started	Aug 01 06:12:36 PM PDT 24
Finished	Aug 01 06:12:38 PM PDT 24
Peak memory	206984 kb
Host	smart-0518b8d1-38a4-48fd-9d23-4b3a5745ceed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76485 5156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.764855156
Directory	/workspace/7.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/7.usbdev_in_iso.2728499355
Short name	T670
Test name
Test status
Simulation time	239666179 ps
CPU time	1.13 seconds
Started	Aug 01 06:12:32 PM PDT 24
Finished	Aug 01 06:12:33 PM PDT 24
Peak memory	215372 kb
Host	smart-816ab565-a7cc-4742-a478-346828999ae5
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2728499355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2728499355
Directory	/workspace/7.usbdev_in_iso/latest

Test location	/workspace/coverage/default/7.usbdev_in_stall.4187248510
Short name	T1236
Test name
Test status
Simulation time	181356284 ps
CPU time	0.83 seconds
Started	Aug 01 06:12:29 PM PDT 24
Finished	Aug 01 06:12:30 PM PDT 24
Peak memory	206912 kb
Host	smart-a17733a1-6273-407e-aa5b-47a00bc1787a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41872 48510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.4187248510
Directory	/workspace/7.usbdev_in_stall/latest

Test location	/workspace/coverage/default/7.usbdev_in_trans.3180070977
Short name	T860
Test name
Test status
Simulation time	228508891 ps
CPU time	0.96 seconds
Started	Aug 01 06:12:33 PM PDT 24
Finished	Aug 01 06:12:34 PM PDT 24
Peak memory	206912 kb
Host	smart-6e84950d-e7f9-437e-a936-eb60d6ac6aa6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31800 70977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3180070977
Directory	/workspace/7.usbdev_in_trans/latest

Test location	/workspace/coverage/default/7.usbdev_invalid_sync.2959479911
Short name	T1415
Test name
Test status
Simulation time	3446700231 ps
CPU time	26.13 seconds
Started	Aug 01 06:12:31 PM PDT 24
Finished	Aug 01 06:12:58 PM PDT 24
Peak memory	217316 kb
Host	smart-ad961e65-a6f1-46ae-b161-e0d144bd580a
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2959479911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.2959479911
Directory	/workspace/7.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/7.usbdev_iso_retraction.2254156703
Short name	T1151
Test name
Test status
Simulation time	12531198904 ps
CPU time	160.03 seconds
Started	Aug 01 06:12:34 PM PDT 24
Finished	Aug 01 06:15:14 PM PDT 24
Peak memory	207076 kb
Host	smart-4b3f4aa5-d185-4662-84c9-44292b2fa524
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2254156703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2254156703
Directory	/workspace/7.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/7.usbdev_link_in_err.687120435
Short name	T689
Test name
Test status
Simulation time	181454308 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:32 PM PDT 24
Finished	Aug 01 06:12:33 PM PDT 24
Peak memory	206932 kb
Host	smart-f552e004-3259-4b31-8044-d86a2cc98938
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68712 0435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.687120435
Directory	/workspace/7.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/7.usbdev_link_suspend.669995828
Short name	T1352
Test name
Test status
Simulation time	5089873192 ps
CPU time	6.54 seconds
Started	Aug 01 06:12:31 PM PDT 24
Finished	Aug 01 06:12:38 PM PDT 24
Peak memory	215284 kb
Host	smart-787a111a-5099-4d14-bbd7-be80ab09da0e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66999 5828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.669995828
Directory	/workspace/7.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/7.usbdev_low_speed_traffic.3501247573
Short name	T1149
Test name
Test status
Simulation time	3262909872 ps
CPU time	25.19 seconds
Started	Aug 01 06:12:42 PM PDT 24
Finished	Aug 01 06:13:07 PM PDT 24
Peak memory	223548 kb
Host	smart-9b4700d2-e3a5-43db-98bb-c2df79e79a1e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35012 47573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3501247573
Directory	/workspace/7.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3592076995
Short name	T2263
Test name
Test status
Simulation time	3667990807 ps
CPU time	101.5 seconds
Started	Aug 01 06:12:34 PM PDT 24
Finished	Aug 01 06:14:15 PM PDT 24
Peak memory	216720 kb
Host	smart-ec5cb011-a791-4703-95f4-375848c29213
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3592076995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3592076995
Directory	/workspace/7.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/7.usbdev_max_length_in_transaction.3056429825
Short name	T1546
Test name
Test status
Simulation time	270573625 ps
CPU time	1.08 seconds
Started	Aug 01 06:12:34 PM PDT 24
Finished	Aug 01 06:12:35 PM PDT 24
Peak memory	206948 kb
Host	smart-9d0dbb0b-538c-4a3b-9ea1-ae3a42f5440f
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3056429825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.3056429825
Directory	/workspace/7.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/7.usbdev_max_length_out_transaction.4159103163
Short name	T2130
Test name
Test status
Simulation time	190390107 ps
CPU time	0.93 seconds
Started	Aug 01 06:12:32 PM PDT 24
Finished	Aug 01 06:12:33 PM PDT 24
Peak memory	206948 kb
Host	smart-4d65ec5b-6426-4ca5-891d-401b59967524
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41591 03163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.4159103163
Directory	/workspace/7.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.3835925452
Short name	T2905
Test name
Test status
Simulation time	3396302889 ps
CPU time	25.06 seconds
Started	Aug 01 06:12:33 PM PDT 24
Finished	Aug 01 06:12:59 PM PDT 24
Peak memory	223544 kb
Host	smart-c3c39bc4-3663-4a96-a351-05baa8a7f097
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38359 25452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.3835925452
Directory	/workspace/7.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/7.usbdev_max_usb_traffic.449664639
Short name	T2812
Test name
Test status
Simulation time	1974377628 ps
CPU time	54.57 seconds
Started	Aug 01 06:12:35 PM PDT 24
Finished	Aug 01 06:13:30 PM PDT 24
Peak memory	215272 kb
Host	smart-fe63236b-bb82-4bba-b52d-fa378197caa7
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=449664639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.449664639
Directory	/workspace/7.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3930041899
Short name	T2684
Test name
Test status
Simulation time	1945331567 ps
CPU time	18.96 seconds
Started	Aug 01 06:12:36 PM PDT 24
Finished	Aug 01 06:12:56 PM PDT 24
Peak memory	216180 kb
Host	smart-2e3aee43-4c51-4120-9f43-cbea0e1ff395
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3930041899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3930041899
Directory	/workspace/7.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/7.usbdev_min_length_in_transaction.535872912
Short name	T1481
Test name
Test status
Simulation time	156496947 ps
CPU time	0.86 seconds
Started	Aug 01 06:12:32 PM PDT 24
Finished	Aug 01 06:12:34 PM PDT 24
Peak memory	206952 kb
Host	smart-c1bbb148-fefd-49e1-b958-09080e888312
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=535872912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.535872912
Directory	/workspace/7.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/7.usbdev_min_length_out_transaction.905142660
Short name	T542
Test name
Test status
Simulation time	185151857 ps
CPU time	0.86 seconds
Started	Aug 01 06:12:34 PM PDT 24
Finished	Aug 01 06:12:35 PM PDT 24
Peak memory	206952 kb
Host	smart-810a2ec2-38ad-40c7-acfa-a27dd8671b3f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90514 2660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.905142660
Directory	/workspace/7.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/7.usbdev_nak_trans.2558004743
Short name	T179
Test name
Test status
Simulation time	282701565 ps
CPU time	1.04 seconds
Started	Aug 01 06:12:42 PM PDT 24
Finished	Aug 01 06:12:44 PM PDT 24
Peak memory	206980 kb
Host	smart-800910fe-377a-4099-abf9-fd2629baf6bb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25580 04743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2558004743
Directory	/workspace/7.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/7.usbdev_out_iso.811357885
Short name	T1564
Test name
Test status
Simulation time	204456477 ps
CPU time	0.92 seconds
Started	Aug 01 06:12:35 PM PDT 24
Finished	Aug 01 06:12:36 PM PDT 24
Peak memory	206948 kb
Host	smart-80a669e0-374f-4ccb-b224-40f2bf3373ac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81135 7885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.811357885
Directory	/workspace/7.usbdev_out_iso/latest

Test location	/workspace/coverage/default/7.usbdev_out_stall.4243291363
Short name	T2898
Test name
Test status
Simulation time	178970426 ps
CPU time	0.87 seconds
Started	Aug 01 06:12:33 PM PDT 24
Finished	Aug 01 06:12:34 PM PDT 24
Peak memory	206968 kb
Host	smart-1e5579fa-e70d-4776-a5a9-6e5225830eb2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42432 91363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.4243291363
Directory	/workspace/7.usbdev_out_stall/latest

Test location	/workspace/coverage/default/7.usbdev_out_trans_nak.3524023071
Short name	T2021
Test name
Test status
Simulation time	181072293 ps
CPU time	0.87 seconds
Started	Aug 01 06:12:34 PM PDT 24
Finished	Aug 01 06:12:35 PM PDT 24
Peak memory	206968 kb
Host	smart-fa6aa8fd-9a7e-4c9e-a337-7d97e320ef63
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35240 23071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.3524023071
Directory	/workspace/7.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/7.usbdev_pending_in_trans.2450042736
Short name	T1205
Test name
Test status
Simulation time	156134234 ps
CPU time	0.84 seconds
Started	Aug 01 06:12:33 PM PDT 24
Finished	Aug 01 06:12:34 PM PDT 24
Peak memory	206956 kb
Host	smart-1707b3b6-4ae7-41d1-8212-25b2d83a3d18
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24500 42736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2450042736
Directory	/workspace/7.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/7.usbdev_phy_config_pinflip.3036909447
Short name	T944
Test name
Test status
Simulation time	249997460 ps
CPU time	0.98 seconds
Started	Aug 01 06:12:32 PM PDT 24
Finished	Aug 01 06:12:33 PM PDT 24
Peak memory	206932 kb
Host	smart-3ea44910-989a-49c7-aeef-6522e53d54ab
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3036909447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.3036909447
Directory	/workspace/7.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.3189030182
Short name	T1270
Test name
Test status
Simulation time	157183302 ps
CPU time	0.85 seconds
Started	Aug 01 06:12:33 PM PDT 24
Finished	Aug 01 06:12:34 PM PDT 24
Peak memory	206884 kb
Host	smart-834dfde0-b599-4102-8bcf-fe02cbb253ae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31890 30182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.3189030182
Directory	/workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/7.usbdev_phy_pins_sense.479103924
Short name	T1478
Test name
Test status
Simulation time	85393760 ps
CPU time	0.71 seconds
Started	Aug 01 06:12:31 PM PDT 24
Finished	Aug 01 06:12:32 PM PDT 24
Peak memory	206908 kb
Host	smart-6bdc78e7-9859-44d3-ac4c-a01329fcdb33
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47910 3924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.479103924
Directory	/workspace/7.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/7.usbdev_pkt_buffer.3761486097
Short name	T463
Test name
Test status
Simulation time	20081596433 ps
CPU time	50.11 seconds
Started	Aug 01 06:12:33 PM PDT 24
Finished	Aug 01 06:13:24 PM PDT 24
Peak memory	215384 kb
Host	smart-8082fd7e-ead2-410d-a111-2f231c2d5ba5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37614 86097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3761486097
Directory	/workspace/7.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/7.usbdev_pkt_received.2547091034
Short name	T1434
Test name
Test status
Simulation time	207485714 ps
CPU time	0.92 seconds
Started	Aug 01 06:12:41 PM PDT 24
Finished	Aug 01 06:12:42 PM PDT 24
Peak memory	206956 kb
Host	smart-e8fc29a1-afa1-48e6-8c5a-9343e3f5580d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25470 91034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.2547091034
Directory	/workspace/7.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/7.usbdev_pkt_sent.1970654209
Short name	T959
Test name
Test status
Simulation time	200321889 ps
CPU time	0.95 seconds
Started	Aug 01 06:12:32 PM PDT 24
Finished	Aug 01 06:12:33 PM PDT 24
Peak memory	206924 kb
Host	smart-c645f56d-4aa4-40e5-9f41-8da719e9c864
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19706 54209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1970654209
Directory	/workspace/7.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/7.usbdev_rand_bus_disconnects.2310323350
Short name	T2027
Test name
Test status
Simulation time	5811470840 ps
CPU time	29.58 seconds
Started	Aug 01 06:12:36 PM PDT 24
Finished	Aug 01 06:13:06 PM PDT 24
Peak memory	223576 kb
Host	smart-bb99e6f1-dac6-4f7e-b111-8b49604d1445
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310323350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2310323350
Directory	/workspace/7.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/7.usbdev_rand_bus_resets.3082198082
Short name	T602
Test name
Test status
Simulation time	5167016751 ps
CPU time	20.53 seconds
Started	Aug 01 06:12:33 PM PDT 24
Finished	Aug 01 06:12:54 PM PDT 24
Peak memory	218492 kb
Host	smart-7e9d63f5-4e11-4655-83b8-f519d6b18b54
User	root
Command	/workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082198082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3082198082
Directory	/workspace/7.usbdev_rand_bus_resets/latest

Test location	/workspace/coverage/default/7.usbdev_rand_suspends.1038026978
Short name	T2756
Test name
Test status
Simulation time	6595612750 ps
CPU time	100.1 seconds
Started	Aug 01 06:12:33 PM PDT 24
Finished	Aug 01 06:14:13 PM PDT 24
Peak memory	218464 kb
Host	smart-74fc751f-7c6e-406c-9d10-ca1fb749cd1e
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038026978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.1038026978
Directory	/workspace/7.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/7.usbdev_random_length_in_transaction.2492223320
Short name	T2044
Test name
Test status
Simulation time	211471156 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:29 PM PDT 24
Finished	Aug 01 06:12:30 PM PDT 24
Peak memory	206948 kb
Host	smart-76be1bfa-71ca-4c21-acee-df36d6afa092
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24922 23320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.2492223320
Directory	/workspace/7.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/7.usbdev_random_length_out_transaction.1737263865
Short name	T1389
Test name
Test status
Simulation time	181026912 ps
CPU time	0.95 seconds
Started	Aug 01 06:12:32 PM PDT 24
Finished	Aug 01 06:12:33 PM PDT 24
Peak memory	206948 kb
Host	smart-917a23ee-e2e2-453e-b89f-305402002870
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17372 63865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1737263865
Directory	/workspace/7.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/7.usbdev_rx_crc_err.3880662114
Short name	T2333
Test name
Test status
Simulation time	144602882 ps
CPU time	0.86 seconds
Started	Aug 01 06:12:42 PM PDT 24
Finished	Aug 01 06:12:43 PM PDT 24
Peak memory	206948 kb
Host	smart-640f900c-2d18-4113-8fbb-9a5aae1956cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38806 62114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3880662114
Directory	/workspace/7.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/7.usbdev_rx_full.878601560
Short name	T282
Test name
Test status
Simulation time	340237161 ps
CPU time	1.2 seconds
Started	Aug 01 06:12:36 PM PDT 24
Finished	Aug 01 06:12:37 PM PDT 24
Peak memory	206876 kb
Host	smart-665efe83-b60e-445c-9202-cdb6ac94ab7f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87860 1560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.878601560
Directory	/workspace/7.usbdev_rx_full/latest

Test location	/workspace/coverage/default/7.usbdev_setup_stage.4069765942
Short name	T2052
Test name
Test status
Simulation time	146890528 ps
CPU time	0.81 seconds
Started	Aug 01 06:12:34 PM PDT 24
Finished	Aug 01 06:12:35 PM PDT 24
Peak memory	206908 kb
Host	smart-670b4e0b-bf2a-461e-9ef7-e256c6409e7d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40697 65942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.4069765942
Directory	/workspace/7.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/7.usbdev_setup_trans_ignored.3626749964
Short name	T2523
Test name
Test status
Simulation time	192205790 ps
CPU time	0.88 seconds
Started	Aug 01 06:12:36 PM PDT 24
Finished	Aug 01 06:12:37 PM PDT 24
Peak memory	206880 kb
Host	smart-d79dfc92-630e-4d5d-ae1d-e4dbfc1560d7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36267 49964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3626749964
Directory	/workspace/7.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/7.usbdev_smoke.188161885
Short name	T724
Test name
Test status
Simulation time	248193486 ps
CPU time	1.1 seconds
Started	Aug 01 06:12:37 PM PDT 24
Finished	Aug 01 06:12:38 PM PDT 24
Peak memory	206856 kb
Host	smart-4aa09386-f516-4b45-b3a8-105e373a8fba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18816 1885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.188161885
Directory	/workspace/7.usbdev_smoke/latest

Test location	/workspace/coverage/default/7.usbdev_spurious_pids_ignored.3824778478
Short name	T2790
Test name
Test status
Simulation time	2073483628 ps
CPU time	20.25 seconds
Started	Aug 01 06:12:42 PM PDT 24
Finished	Aug 01 06:13:03 PM PDT 24
Peak memory	223496 kb
Host	smart-b2ca20bf-8146-4b6b-aecc-12e7f83913b1
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3824778478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3824778478
Directory	/workspace/7.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/7.usbdev_stall_priority_over_nak.753508719
Short name	T2101
Test name
Test status
Simulation time	228314452 ps
CPU time	0.93 seconds
Started	Aug 01 06:12:31 PM PDT 24
Finished	Aug 01 06:12:32 PM PDT 24
Peak memory	206908 kb
Host	smart-5849974e-822d-43d0-a1f0-c216a137dc44
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75350 8719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.753508719
Directory	/workspace/7.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/7.usbdev_stall_trans.860321924
Short name	T805
Test name
Test status
Simulation time	172591412 ps
CPU time	0.86 seconds
Started	Aug 01 06:12:35 PM PDT 24
Finished	Aug 01 06:12:36 PM PDT 24
Peak memory	206880 kb
Host	smart-e4cd5ad7-bccd-4d60-8543-0e6718ccec6f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86032 1924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.860321924
Directory	/workspace/7.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/7.usbdev_stream_len_max.2039800353
Short name	T481
Test name
Test status
Simulation time	460868320 ps
CPU time	1.49 seconds
Started	Aug 01 06:12:42 PM PDT 24
Finished	Aug 01 06:12:44 PM PDT 24
Peak memory	206928 kb
Host	smart-ee03a27c-c0b5-43c4-b1b4-83e0336211df
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20398 00353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2039800353
Directory	/workspace/7.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/7.usbdev_streaming_out.1180850329
Short name	T1941
Test name
Test status
Simulation time	2436758452 ps
CPU time	18.4 seconds
Started	Aug 01 06:12:41 PM PDT 24
Finished	Aug 01 06:13:00 PM PDT 24
Peak memory	207168 kb
Host	smart-22e841dc-9805-43fe-bfd9-a9e1481cd951
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11808 50329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1180850329
Directory	/workspace/7.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.1326959264
Short name	T235
Test name
Test status
Simulation time	1040358582 ps
CPU time	22.13 seconds
Started	Aug 01 06:12:24 PM PDT 24
Finished	Aug 01 06:12:46 PM PDT 24
Peak memory	207156 kb
Host	smart-2e584a14-5f8f-4d0e-981d-acd1036dbaeb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326959264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host _handshake.1326959264
Directory	/workspace/7.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/70.usbdev_endpoint_types.4258371775
Short name	T411
Test name
Test status
Simulation time	533499637 ps
CPU time	1.34 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206884 kb
Host	smart-d9bd9b78-b822-450b-9f84-a8be911ef512
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4258371775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.4258371775
Directory	/workspace/70.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/71.usbdev_endpoint_types.1254935090
Short name	T1450
Test name
Test status
Simulation time	401725094 ps
CPU time	1.34 seconds
Started	Aug 01 06:19:59 PM PDT 24
Finished	Aug 01 06:20:00 PM PDT 24
Peak memory	206908 kb
Host	smart-a5023154-5083-4d8c-b96a-6e1084cdd932
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1254935090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.1254935090
Directory	/workspace/71.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/72.usbdev_endpoint_types.523389991
Short name	T329
Test name
Test status
Simulation time	858567125 ps
CPU time	1.74 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206928 kb
Host	smart-21e38520-c2d9-44fc-91a0-898a294e6e3c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=523389991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.523389991
Directory	/workspace/72.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/73.usbdev_endpoint_types.269252916
Short name	T1093
Test name
Test status
Simulation time	280141771 ps
CPU time	0.98 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206912 kb
Host	smart-2e3835a0-ff71-4427-9fb9-2be48cf321ed
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=269252916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.269252916
Directory	/workspace/73.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/74.usbdev_endpoint_types.2248016509
Short name	T360
Test name
Test status
Simulation time	405508564 ps
CPU time	1.35 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206908 kb
Host	smart-5379202f-86ea-4478-a6fc-df90637a518d
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2248016509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.2248016509
Directory	/workspace/74.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/75.usbdev_endpoint_types.107963271
Short name	T348
Test name
Test status
Simulation time	251392759 ps
CPU time	0.96 seconds
Started	Aug 01 06:19:59 PM PDT 24
Finished	Aug 01 06:20:00 PM PDT 24
Peak memory	206944 kb
Host	smart-72d9f588-9f6d-418f-9f08-153812601931
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=107963271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.107963271
Directory	/workspace/75.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/76.usbdev_endpoint_types.3096140907
Short name	T409
Test name
Test status
Simulation time	365130471 ps
CPU time	1.3 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206920 kb
Host	smart-2a3ed751-05aa-48e7-a44e-47487773b91c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3096140907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.3096140907
Directory	/workspace/76.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/77.usbdev_endpoint_types.4060452114
Short name	T401
Test name
Test status
Simulation time	283637419 ps
CPU time	1.14 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206972 kb
Host	smart-33e4572b-4c3d-4db0-b4b7-959cfacad2c0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4060452114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.4060452114
Directory	/workspace/77.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/78.usbdev_endpoint_types.4200927422
Short name	T441
Test name
Test status
Simulation time	580316712 ps
CPU time	1.61 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206924 kb
Host	smart-411f180d-14e4-4ff6-9518-c4ffff2aeda0
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4200927422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.4200927422
Directory	/workspace/78.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/79.usbdev_endpoint_types.1103214734
Short name	T629
Test name
Test status
Simulation time	176365919 ps
CPU time	0.94 seconds
Started	Aug 01 06:20:24 PM PDT 24
Finished	Aug 01 06:20:25 PM PDT 24
Peak memory	206916 kb
Host	smart-aa1e58c3-7f3c-479f-b8f7-c97cfe2d4649
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1103214734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.1103214734
Directory	/workspace/79.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/8.usbdev_alert_test.1185724419
Short name	T116
Test name
Test status
Simulation time	40266197 ps
CPU time	0.7 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	207208 kb
Host	smart-fff92e6d-d7f6-46d2-a3b3-84ebc9f0578c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1185724419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1185724419
Directory	/workspace/8.usbdev_alert_test/latest

Test location	/workspace/coverage/default/8.usbdev_av_buffer.2477283606
Short name	T1033
Test name
Test status
Simulation time	181104093 ps
CPU time	0.87 seconds
Started	Aug 01 06:12:46 PM PDT 24
Finished	Aug 01 06:12:47 PM PDT 24
Peak memory	206972 kb
Host	smart-25690b2e-e234-4d52-93be-0cbd8d2b43fd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24772 83606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2477283606
Directory	/workspace/8.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/8.usbdev_bitstuff_err.887342274
Short name	T864
Test name
Test status
Simulation time	144071036 ps
CPU time	0.79 seconds
Started	Aug 01 06:12:49 PM PDT 24
Finished	Aug 01 06:12:50 PM PDT 24
Peak memory	206868 kb
Host	smart-678b84fc-c936-4efc-86c3-f8a4d42a4fa7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88734 2274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.887342274
Directory	/workspace/8.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/8.usbdev_data_toggle_clear.382627329
Short name	T2285
Test name
Test status
Simulation time	243173841 ps
CPU time	1 seconds
Started	Aug 01 06:12:47 PM PDT 24
Finished	Aug 01 06:12:48 PM PDT 24
Peak memory	206952 kb
Host	smart-612fe69a-9290-40fe-b6fb-24cfb74d1a33
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38262 7329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.382627329
Directory	/workspace/8.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/8.usbdev_data_toggle_restore.2178225681
Short name	T1193
Test name
Test status
Simulation time	1402001672 ps
CPU time	3.64 seconds
Started	Aug 01 06:12:49 PM PDT 24
Finished	Aug 01 06:12:53 PM PDT 24
Peak memory	207148 kb
Host	smart-13a30482-9847-4e5d-ad26-838645b8670f
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2178225681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.2178225681
Directory	/workspace/8.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/8.usbdev_device_address.2419036676
Short name	T1037
Test name
Test status
Simulation time	22512891327 ps
CPU time	42.42 seconds
Started	Aug 01 06:12:47 PM PDT 24
Finished	Aug 01 06:13:30 PM PDT 24
Peak memory	207180 kb
Host	smart-379e9448-7124-46fe-a6a5-fdbc7cfb6945
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24190 36676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.2419036676
Directory	/workspace/8.usbdev_device_address/latest

Test location	/workspace/coverage/default/8.usbdev_device_timeout.1334667298
Short name	T1782
Test name
Test status
Simulation time	704943431 ps
CPU time	14.67 seconds
Started	Aug 01 06:12:45 PM PDT 24
Finished	Aug 01 06:13:00 PM PDT 24
Peak memory	207096 kb
Host	smart-8aa7b26f-c955-4ff1-8d91-693ab3694095
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334667298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.1334667298
Directory	/workspace/8.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/8.usbdev_disable_endpoint.1865998149
Short name	T2019
Test name
Test status
Simulation time	516309635 ps
CPU time	1.51 seconds
Started	Aug 01 06:12:45 PM PDT 24
Finished	Aug 01 06:12:47 PM PDT 24
Peak memory	206896 kb
Host	smart-b227f789-b7aa-472f-9528-07ac077759fd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18659 98149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1865998149
Directory	/workspace/8.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/8.usbdev_disconnected.944354449
Short name	T27
Test name
Test status
Simulation time	145537612 ps
CPU time	0.85 seconds
Started	Aug 01 06:12:49 PM PDT 24
Finished	Aug 01 06:12:50 PM PDT 24
Peak memory	206924 kb
Host	smart-fdabdb57-05e1-4af8-86e3-063accd60ab2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94435 4449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.944354449
Directory	/workspace/8.usbdev_disconnected/latest

Test location	/workspace/coverage/default/8.usbdev_enable.4007173009
Short name	T1541
Test name
Test status
Simulation time	55465134 ps
CPU time	0.7 seconds
Started	Aug 01 06:12:48 PM PDT 24
Finished	Aug 01 06:12:49 PM PDT 24
Peak memory	206876 kb
Host	smart-b89d92a2-50a1-48ff-b300-64733e62499b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40071 73009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.4007173009
Directory	/workspace/8.usbdev_enable/latest

Test location	/workspace/coverage/default/8.usbdev_endpoint_access.3789821172
Short name	T1855
Test name
Test status
Simulation time	876978899 ps
CPU time	2.48 seconds
Started	Aug 01 06:12:52 PM PDT 24
Finished	Aug 01 06:12:55 PM PDT 24
Peak memory	207176 kb
Host	smart-fdaab225-968e-402c-8933-337280b7f819
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37898 21172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3789821172
Directory	/workspace/8.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/8.usbdev_endpoint_types.3773189376
Short name	T1752
Test name
Test status
Simulation time	653340183 ps
CPU time	1.42 seconds
Started	Aug 01 06:12:46 PM PDT 24
Finished	Aug 01 06:12:47 PM PDT 24
Peak memory	206940 kb
Host	smart-ecbaae22-954a-465c-b723-9694bb938c6e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3773189376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.3773189376
Directory	/workspace/8.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/8.usbdev_fifo_rst.512472824
Short name	T2504
Test name
Test status
Simulation time	188221391 ps
CPU time	2.52 seconds
Started	Aug 01 06:12:49 PM PDT 24
Finished	Aug 01 06:12:52 PM PDT 24
Peak memory	207040 kb
Host	smart-167ab90c-e777-43eb-b93a-e6c5d72fd0f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51247 2824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.512472824
Directory	/workspace/8.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/8.usbdev_in_iso.2997358433
Short name	T1168
Test name
Test status
Simulation time	223153038 ps
CPU time	1.13 seconds
Started	Aug 01 06:12:50 PM PDT 24
Finished	Aug 01 06:12:52 PM PDT 24
Peak memory	207116 kb
Host	smart-e027bf18-ac1a-4fa9-bdf9-68e7c23ae721
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2997358433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2997358433
Directory	/workspace/8.usbdev_in_iso/latest

Test location	/workspace/coverage/default/8.usbdev_in_stall.565046523
Short name	T2068
Test name
Test status
Simulation time	142333842 ps
CPU time	0.84 seconds
Started	Aug 01 06:12:49 PM PDT 24
Finished	Aug 01 06:12:50 PM PDT 24
Peak memory	206912 kb
Host	smart-b9f9af20-30f4-4014-b870-d9c4911d0810
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56504 6523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.565046523
Directory	/workspace/8.usbdev_in_stall/latest

Test location	/workspace/coverage/default/8.usbdev_in_trans.4262955688
Short name	T870
Test name
Test status
Simulation time	184303097 ps
CPU time	0.96 seconds
Started	Aug 01 06:12:46 PM PDT 24
Finished	Aug 01 06:12:47 PM PDT 24
Peak memory	206936 kb
Host	smart-dce0ba6b-b460-4da8-b260-fdfc0afbc16e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42629 55688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.4262955688
Directory	/workspace/8.usbdev_in_trans/latest

Test location	/workspace/coverage/default/8.usbdev_invalid_sync.3191176301
Short name	T1657
Test name
Test status
Simulation time	4378252881 ps
CPU time	127.72 seconds
Started	Aug 01 06:12:49 PM PDT 24
Finished	Aug 01 06:14:57 PM PDT 24
Peak memory	217176 kb
Host	smart-0ee8f23b-db29-4a98-8fa3-84946e8095da
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3191176301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.3191176301
Directory	/workspace/8.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/8.usbdev_iso_retraction.1023878093
Short name	T1266
Test name
Test status
Simulation time	4310041555 ps
CPU time	50.3 seconds
Started	Aug 01 06:12:47 PM PDT 24
Finished	Aug 01 06:13:38 PM PDT 24
Peak memory	207136 kb
Host	smart-032654fa-13ec-4199-baa5-5b4ed84000a6
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1023878093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.1023878093
Directory	/workspace/8.usbdev_iso_retraction/latest

Test location	/workspace/coverage/default/8.usbdev_link_in_err.2396786968
Short name	T1552
Test name
Test status
Simulation time	179707632 ps
CPU time	0.91 seconds
Started	Aug 01 06:12:47 PM PDT 24
Finished	Aug 01 06:12:48 PM PDT 24
Peak memory	206948 kb
Host	smart-08752ed7-badc-4812-b38d-18da6439823f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23967 86968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.2396786968
Directory	/workspace/8.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/8.usbdev_link_suspend.805034705
Short name	T1718
Test name
Test status
Simulation time	3986069848 ps
CPU time	5.55 seconds
Started	Aug 01 06:12:51 PM PDT 24
Finished	Aug 01 06:12:56 PM PDT 24
Peak memory	215208 kb
Host	smart-f86c0fd1-fb7d-4f86-831f-8d5d3f4d037e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80503 4705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.805034705
Directory	/workspace/8.usbdev_link_suspend/latest

Test location	/workspace/coverage/default/8.usbdev_low_speed_traffic.105449011
Short name	T2339
Test name
Test status
Simulation time	4806155529 ps
CPU time	47.15 seconds
Started	Aug 01 06:12:50 PM PDT 24
Finished	Aug 01 06:13:38 PM PDT 24
Peak memory	217876 kb
Host	smart-94cd2f0e-6170-44c5-8a8b-199f68a50c75
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10544 9011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.105449011
Directory	/workspace/8.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2679849371
Short name	T2323
Test name
Test status
Simulation time	3816637958 ps
CPU time	37.52 seconds
Started	Aug 01 06:12:46 PM PDT 24
Finished	Aug 01 06:13:24 PM PDT 24
Peak memory	215312 kb
Host	smart-dc25b301-dd0b-411b-95e6-14911ae80dac
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2679849371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2679849371
Directory	/workspace/8.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/8.usbdev_max_length_in_transaction.1755642404
Short name	T683
Test name
Test status
Simulation time	240714051 ps
CPU time	0.97 seconds
Started	Aug 01 06:12:48 PM PDT 24
Finished	Aug 01 06:12:50 PM PDT 24
Peak memory	206912 kb
Host	smart-3294eaf6-90d7-48e2-b5e7-8b58ed8999a3
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1755642404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1755642404
Directory	/workspace/8.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/8.usbdev_max_length_out_transaction.2780795995
Short name	T1646
Test name
Test status
Simulation time	195979496 ps
CPU time	0.95 seconds
Started	Aug 01 06:12:44 PM PDT 24
Finished	Aug 01 06:12:45 PM PDT 24
Peak memory	206944 kb
Host	smart-1252cb0a-8d0b-45bd-bb2e-6044d912bf77
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27807 95995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2780795995
Directory	/workspace/8.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.4137354400
Short name	T2372
Test name
Test status
Simulation time	2939836913 ps
CPU time	29.82 seconds
Started	Aug 01 06:12:52 PM PDT 24
Finished	Aug 01 06:13:22 PM PDT 24
Peak memory	223504 kb
Host	smart-3ab431a1-0b94-45c1-b65d-4c369ff7865e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41373 54400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.4137354400
Directory	/workspace/8.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/8.usbdev_max_usb_traffic.676268176
Short name	T156
Test name
Test status
Simulation time	2814033167 ps
CPU time	84.62 seconds
Started	Aug 01 06:12:50 PM PDT 24
Finished	Aug 01 06:14:15 PM PDT 24
Peak memory	217456 kb
Host	smart-a2152d08-f836-4cf3-ac57-317831119371
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=676268176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.676268176
Directory	/workspace/8.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3492844169
Short name	T716
Test name
Test status
Simulation time	2995772518 ps
CPU time	84.47 seconds
Started	Aug 01 06:12:48 PM PDT 24
Finished	Aug 01 06:14:12 PM PDT 24
Peak memory	216676 kb
Host	smart-ba0f1b18-07e5-4589-921f-f973041d0f74
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3492844169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3492844169
Directory	/workspace/8.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/8.usbdev_min_length_in_transaction.3973268991
Short name	T1510
Test name
Test status
Simulation time	173001181 ps
CPU time	0.89 seconds
Started	Aug 01 06:12:51 PM PDT 24
Finished	Aug 01 06:12:52 PM PDT 24
Peak memory	206924 kb
Host	smart-e301064a-bda8-478e-b4a8-2472271dea89
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3973268991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3973268991
Directory	/workspace/8.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/8.usbdev_min_length_out_transaction.3395146173
Short name	T1120
Test name
Test status
Simulation time	151548277 ps
CPU time	0.87 seconds
Started	Aug 01 06:12:49 PM PDT 24
Finished	Aug 01 06:12:50 PM PDT 24
Peak memory	206888 kb
Host	smart-4502cf45-8e88-41ee-8c97-7c6546ced99f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33951 46173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3395146173
Directory	/workspace/8.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/8.usbdev_nak_trans.162189378
Short name	T196
Test name
Test status
Simulation time	199120455 ps
CPU time	0.98 seconds
Started	Aug 01 06:12:51 PM PDT 24
Finished	Aug 01 06:12:52 PM PDT 24
Peak memory	206948 kb
Host	smart-f5c1cd1f-1f66-45af-9a05-8d75c883d0d3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16218 9378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.162189378
Directory	/workspace/8.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/8.usbdev_out_iso.1448629924
Short name	T1398
Test name
Test status
Simulation time	193615572 ps
CPU time	0.98 seconds
Started	Aug 01 06:12:49 PM PDT 24
Finished	Aug 01 06:12:50 PM PDT 24
Peak memory	206944 kb
Host	smart-f184155a-9c98-411c-bc46-605d19dae718
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14486 29924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.1448629924
Directory	/workspace/8.usbdev_out_iso/latest

Test location	/workspace/coverage/default/8.usbdev_out_stall.2230991391
Short name	T2252
Test name
Test status
Simulation time	171743845 ps
CPU time	0.87 seconds
Started	Aug 01 06:12:53 PM PDT 24
Finished	Aug 01 06:12:54 PM PDT 24
Peak memory	206960 kb
Host	smart-536e33bd-b16a-4510-a6e0-20308aee8953
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22309 91391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2230991391
Directory	/workspace/8.usbdev_out_stall/latest

Test location	/workspace/coverage/default/8.usbdev_out_trans_nak.1809492237
Short name	T2255
Test name
Test status
Simulation time	147876145 ps
CPU time	0.84 seconds
Started	Aug 01 06:12:49 PM PDT 24
Finished	Aug 01 06:12:50 PM PDT 24
Peak memory	206860 kb
Host	smart-624e13a1-6c43-4c26-b487-3c7a022c4c64
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18094 92237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.1809492237
Directory	/workspace/8.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/8.usbdev_pending_in_trans.4209526589
Short name	T2018
Test name
Test status
Simulation time	164829468 ps
CPU time	0.88 seconds
Started	Aug 01 06:12:51 PM PDT 24
Finished	Aug 01 06:12:52 PM PDT 24
Peak memory	206864 kb
Host	smart-394ad934-0b70-43ba-b76d-5694ef8892af
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42095 26589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.4209526589
Directory	/workspace/8.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/8.usbdev_phy_config_pinflip.3609314002
Short name	T1297
Test name
Test status
Simulation time	222868184 ps
CPU time	1.1 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	206928 kb
Host	smart-968232b1-5c0d-487e-8990-70833e43102e
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3609314002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3609314002
Directory	/workspace/8.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2896873687
Short name	T2041
Test name
Test status
Simulation time	185074974 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:05 PM PDT 24
Finished	Aug 01 06:13:06 PM PDT 24
Peak memory	206796 kb
Host	smart-8599e1ea-40bd-4dff-adbb-00cf763d3b55
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28968 73687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2896873687
Directory	/workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/8.usbdev_phy_pins_sense.3823090801
Short name	T2283
Test name
Test status
Simulation time	80372678 ps
CPU time	0.73 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:08 PM PDT 24
Peak memory	206868 kb
Host	smart-7932c80e-92e0-4971-a75d-65dd926ae6c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38230 90801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.3823090801
Directory	/workspace/8.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/8.usbdev_pkt_buffer.1935299173
Short name	T2799
Test name
Test status
Simulation time	16470976489 ps
CPU time	41.87 seconds
Started	Aug 01 06:13:06 PM PDT 24
Finished	Aug 01 06:13:48 PM PDT 24
Peak memory	215376 kb
Host	smart-088b903f-c762-44ae-8f1b-91c5ede65995
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19352 99173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.1935299173
Directory	/workspace/8.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/8.usbdev_pkt_received.2482944599
Short name	T2636
Test name
Test status
Simulation time	174309107 ps
CPU time	0.95 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206928 kb
Host	smart-9a7eb516-b4bd-4d3f-99c9-19076f60b5c8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24829 44599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2482944599
Directory	/workspace/8.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/8.usbdev_pkt_sent.17745737
Short name	T1162
Test name
Test status
Simulation time	244607429 ps
CPU time	1.02 seconds
Started	Aug 01 06:13:06 PM PDT 24
Finished	Aug 01 06:13:07 PM PDT 24
Peak memory	206952 kb
Host	smart-8906f013-7efc-4e29-bea3-c12ca71fb811
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17745 737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.17745737
Directory	/workspace/8.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/8.usbdev_rand_bus_disconnects.605237344
Short name	T211
Test name
Test status
Simulation time	4353465983 ps
CPU time	35.22 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:43 PM PDT 24
Peak memory	217680 kb
Host	smart-c4f8eadd-a8d0-49ea-bb43-04a01e54f2d2
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=605237344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.605237344
Directory	/workspace/8.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/8.usbdev_rand_suspends.2945812495
Short name	T1536
Test name
Test status
Simulation time	9591866795 ps
CPU time	47.66 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:56 PM PDT 24
Peak memory	215360 kb
Host	smart-185f7d31-3bdf-47a9-b46e-212df43c43a8
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945812495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.2945812495
Directory	/workspace/8.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/8.usbdev_random_length_in_transaction.549016572
Short name	T1003
Test name
Test status
Simulation time	156803264 ps
CPU time	0.92 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206920 kb
Host	smart-65dd8d31-389c-44b9-b057-c927122b6c36
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54901 6572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.549016572
Directory	/workspace/8.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/8.usbdev_random_length_out_transaction.2494930507
Short name	T1005
Test name
Test status
Simulation time	166026224 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	206924 kb
Host	smart-fd5c0e64-6d75-40cb-b3bd-676faf60b13a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24949 30507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2494930507
Directory	/workspace/8.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/8.usbdev_rx_crc_err.2530035459
Short name	T930
Test name
Test status
Simulation time	147149610 ps
CPU time	0.84 seconds
Started	Aug 01 06:13:11 PM PDT 24
Finished	Aug 01 06:13:12 PM PDT 24
Peak memory	207136 kb
Host	smart-35b30923-6491-4a98-ac3f-fdd76dd0fbdc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25300 35459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.2530035459
Directory	/workspace/8.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/8.usbdev_rx_full.1706812962
Short name	T1265
Test name
Test status
Simulation time	296068654 ps
CPU time	1.23 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206924 kb
Host	smart-203ba1b3-067a-412c-a54c-2533bcce1cb4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17068 12962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.1706812962
Directory	/workspace/8.usbdev_rx_full/latest

Test location	/workspace/coverage/default/8.usbdev_setup_stage.3482754189
Short name	T2000
Test name
Test status
Simulation time	156146277 ps
CPU time	0.86 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	206924 kb
Host	smart-2b65de13-6835-4514-99b8-aa67c9e8669c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34827 54189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3482754189
Directory	/workspace/8.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/8.usbdev_setup_trans_ignored.1626072255
Short name	T1721
Test name
Test status
Simulation time	150348296 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:04 PM PDT 24
Finished	Aug 01 06:13:05 PM PDT 24
Peak memory	206888 kb
Host	smart-ece016ea-6d6a-4767-a1ba-21aa5345bb2a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16260 72255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1626072255
Directory	/workspace/8.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/8.usbdev_smoke.2022845583
Short name	T681
Test name
Test status
Simulation time	224936559 ps
CPU time	1.06 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206944 kb
Host	smart-396f7ae5-13b5-4044-b779-25e51b49de2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20228 45583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2022845583
Directory	/workspace/8.usbdev_smoke/latest

Test location	/workspace/coverage/default/8.usbdev_spurious_pids_ignored.2168242794
Short name	T2536
Test name
Test status
Simulation time	2189823322 ps
CPU time	18.24 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:26 PM PDT 24
Peak memory	215384 kb
Host	smart-4208a957-7f9e-4d08-9764-bb05ea8a70b0
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2168242794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.2168242794
Directory	/workspace/8.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/8.usbdev_stall_priority_over_nak.1376200784
Short name	T1655
Test name
Test status
Simulation time	264003007 ps
CPU time	1 seconds
Started	Aug 01 06:13:05 PM PDT 24
Finished	Aug 01 06:13:06 PM PDT 24
Peak memory	206928 kb
Host	smart-7a47b6ce-bfd8-4c4f-bf7d-bf9f0822166d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13762 00784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1376200784
Directory	/workspace/8.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/8.usbdev_stall_trans.589722146
Short name	T536
Test name
Test status
Simulation time	263431110 ps
CPU time	1 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	206972 kb
Host	smart-ee6c2ddf-9f65-4851-89c0-704b32edf97c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58972 2146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.589722146
Directory	/workspace/8.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/8.usbdev_stream_len_max.2739299114
Short name	T1393
Test name
Test status
Simulation time	1265914585 ps
CPU time	3.25 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:12 PM PDT 24
Peak memory	207160 kb
Host	smart-cfad6464-7ca8-41c9-8258-6b139f4d081b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27392 99114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2739299114
Directory	/workspace/8.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/8.usbdev_streaming_out.1646717705
Short name	T938
Test name
Test status
Simulation time	1738593340 ps
CPU time	14.31 seconds
Started	Aug 01 06:13:06 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	207144 kb
Host	smart-32c93bc1-e89c-4fbd-bdc0-5b6050adc568
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16467 17705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1646717705
Directory	/workspace/8.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.3676988345
Short name	T1119
Test name
Test status
Simulation time	414732021 ps
CPU time	8.19 seconds
Started	Aug 01 06:12:46 PM PDT 24
Finished	Aug 01 06:12:54 PM PDT 24
Peak memory	207168 kb
Host	smart-d5b2af31-28c4-4363-9711-8e66a0a9c872
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676988345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host _handshake.3676988345
Directory	/workspace/8.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/80.usbdev_endpoint_types.3185814507
Short name	T2873
Test name
Test status
Simulation time	378090200 ps
CPU time	1.21 seconds
Started	Aug 01 06:20:04 PM PDT 24
Finished	Aug 01 06:20:05 PM PDT 24
Peak memory	206872 kb
Host	smart-5e77c579-afd8-4ec4-978e-93df7b08244f
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3185814507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.3185814507
Directory	/workspace/80.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/81.usbdev_endpoint_types.2735674233
Short name	T397
Test name
Test status
Simulation time	353473915 ps
CPU time	1.13 seconds
Started	Aug 01 06:20:16 PM PDT 24
Finished	Aug 01 06:20:17 PM PDT 24
Peak memory	206916 kb
Host	smart-a2df8218-ee1d-4faa-a853-95779a224b43
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2735674233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.2735674233
Directory	/workspace/81.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/82.usbdev_endpoint_types.2463213532
Short name	T427
Test name
Test status
Simulation time	494577277 ps
CPU time	1.45 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206900 kb
Host	smart-42ec033e-ecb6-4a35-a21d-c74935690ecb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2463213532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.2463213532
Directory	/workspace/82.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/83.usbdev_endpoint_types.2360369932
Short name	T428
Test name
Test status
Simulation time	179840786 ps
CPU time	0.9 seconds
Started	Aug 01 06:20:07 PM PDT 24
Finished	Aug 01 06:20:08 PM PDT 24
Peak memory	206920 kb
Host	smart-76e11533-e514-41aa-8e3d-4269fd43cf9b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2360369932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.2360369932
Directory	/workspace/83.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/84.usbdev_endpoint_types.3534887634
Short name	T390
Test name
Test status
Simulation time	364103336 ps
CPU time	1.23 seconds
Started	Aug 01 06:19:57 PM PDT 24
Finished	Aug 01 06:19:58 PM PDT 24
Peak memory	206924 kb
Host	smart-9c3d4271-1cf3-4a67-b6f4-5885d0c43f6b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3534887634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.3534887634
Directory	/workspace/84.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/85.usbdev_endpoint_types.1862573373
Short name	T1943
Test name
Test status
Simulation time	427997947 ps
CPU time	1.2 seconds
Started	Aug 01 06:20:05 PM PDT 24
Finished	Aug 01 06:20:06 PM PDT 24
Peak memory	206872 kb
Host	smart-64127bac-c622-4071-9752-465d98f5a33a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1862573373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.1862573373
Directory	/workspace/85.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/86.usbdev_endpoint_types.1153490650
Short name	T314
Test name
Test status
Simulation time	244317156 ps
CPU time	1 seconds
Started	Aug 01 06:20:08 PM PDT 24
Finished	Aug 01 06:20:09 PM PDT 24
Peak memory	206944 kb
Host	smart-9fb9ca4f-8c2b-44ac-a789-4eb79143f0d1
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1153490650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.1153490650
Directory	/workspace/86.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/87.usbdev_endpoint_types.4105573365
Short name	T422
Test name
Test status
Simulation time	302895707 ps
CPU time	1.12 seconds
Started	Aug 01 06:20:19 PM PDT 24
Finished	Aug 01 06:20:20 PM PDT 24
Peak memory	206836 kb
Host	smart-010ead5d-7c5d-4740-8645-d7d0e3b6b293
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=4105573365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.4105573365
Directory	/workspace/87.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/88.usbdev_endpoint_types.3638133415
Short name	T2501
Test name
Test status
Simulation time	341995489 ps
CPU time	1.22 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:01 PM PDT 24
Peak memory	206928 kb
Host	smart-c7b684f3-de79-408d-8eac-441ef2a915eb
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3638133415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.3638133415
Directory	/workspace/88.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/89.usbdev_endpoint_types.1742134144
Short name	T1745
Test name
Test status
Simulation time	177604899 ps
CPU time	0.87 seconds
Started	Aug 01 06:20:02 PM PDT 24
Finished	Aug 01 06:20:03 PM PDT 24
Peak memory	206920 kb
Host	smart-abb76181-15c1-46ae-84ae-426249707753
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1742134144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.1742134144
Directory	/workspace/89.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/9.usbdev_alert_test.1345133033
Short name	T2604
Test name
Test status
Simulation time	85070736 ps
CPU time	0.73 seconds
Started	Aug 01 06:13:20 PM PDT 24
Finished	Aug 01 06:13:21 PM PDT 24
Peak memory	206936 kb
Host	smart-86363eaa-57ad-4c60-8e1d-65c024a2997a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=1345133033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.1345133033
Directory	/workspace/9.usbdev_alert_test/latest

Test location	/workspace/coverage/default/9.usbdev_av_buffer.2188521179
Short name	T2224
Test name
Test status
Simulation time	182936684 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:05 PM PDT 24
Finished	Aug 01 06:13:06 PM PDT 24
Peak memory	206880 kb
Host	smart-301d81c4-2cf4-4868-ac70-4f08959c35d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885 21179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2188521179
Directory	/workspace/9.usbdev_av_buffer/latest

Test location	/workspace/coverage/default/9.usbdev_bitstuff_err.336613482
Short name	T2204
Test name
Test status
Simulation time	143101945 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206928 kb
Host	smart-73e7b659-c8d4-467c-98d9-18f530276d94
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661 3482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.336613482
Directory	/workspace/9.usbdev_bitstuff_err/latest

Test location	/workspace/coverage/default/9.usbdev_data_toggle_clear.3363846574
Short name	T882
Test name
Test status
Simulation time	433055140 ps
CPU time	1.63 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206960 kb
Host	smart-91c33a67-abca-4b8d-865a-9ea85e9ebc01
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33638 46574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.3363846574
Directory	/workspace/9.usbdev_data_toggle_clear/latest

Test location	/workspace/coverage/default/9.usbdev_data_toggle_restore.522713896
Short name	T2772
Test name
Test status
Simulation time	681121089 ps
CPU time	1.85 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	207012 kb
Host	smart-30b6c3b7-3464-4374-af17-833749b13ebb
User	root
Command	/workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=522713896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.522713896
Directory	/workspace/9.usbdev_data_toggle_restore/latest

Test location	/workspace/coverage/default/9.usbdev_device_address.1825769245
Short name	T1456
Test name
Test status
Simulation time	23014940008 ps
CPU time	34.56 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:44 PM PDT 24
Peak memory	207184 kb
Host	smart-fa813029-a74f-43de-992c-2440c03e4a2e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18257 69245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1825769245
Directory	/workspace/9.usbdev_device_address/latest

Test location	/workspace/coverage/default/9.usbdev_device_timeout.2390951220
Short name	T1161
Test name
Test status
Simulation time	2943501387 ps
CPU time	25.05 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:32 PM PDT 24
Peak memory	207148 kb
Host	smart-7909ca0a-a83b-46c4-895f-b8d7e1ad849e
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390951220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.2390951220
Directory	/workspace/9.usbdev_device_timeout/latest

Test location	/workspace/coverage/default/9.usbdev_disable_endpoint.2743011749
Short name	T779
Test name
Test status
Simulation time	795772051 ps
CPU time	1.99 seconds
Started	Aug 01 06:13:05 PM PDT 24
Finished	Aug 01 06:13:07 PM PDT 24
Peak memory	206936 kb
Host	smart-3368f084-4493-4ee8-8277-17cb2b828d55
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27430 11749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.2743011749
Directory	/workspace/9.usbdev_disable_endpoint/latest

Test location	/workspace/coverage/default/9.usbdev_disconnected.1015802118
Short name	T466
Test name
Test status
Simulation time	142333974 ps
CPU time	0.83 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:08 PM PDT 24
Peak memory	206920 kb
Host	smart-27d96b44-2b3e-4b3b-b675-31a4cca6faf8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10158 02118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1015802118
Directory	/workspace/9.usbdev_disconnected/latest

Test location	/workspace/coverage/default/9.usbdev_enable.2379059783
Short name	T510
Test name
Test status
Simulation time	92752340 ps
CPU time	0.78 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:08 PM PDT 24
Peak memory	206920 kb
Host	smart-879c8981-ca2a-4025-9957-f5f2ca640fde
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790 59783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2379059783
Directory	/workspace/9.usbdev_enable/latest

Test location	/workspace/coverage/default/9.usbdev_endpoint_access.74851764
Short name	T1375
Test name
Test status
Simulation time	1022215251 ps
CPU time	2.98 seconds
Started	Aug 01 06:13:11 PM PDT 24
Finished	Aug 01 06:13:14 PM PDT 24
Peak memory	207020 kb
Host	smart-73080e80-ec71-4434-a758-1d33b4707be5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74851 764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.74851764
Directory	/workspace/9.usbdev_endpoint_access/latest

Test location	/workspace/coverage/default/9.usbdev_endpoint_types.1363708850
Short name	T1662
Test name
Test status
Simulation time	242854286 ps
CPU time	0.97 seconds
Started	Aug 01 06:13:04 PM PDT 24
Finished	Aug 01 06:13:05 PM PDT 24
Peak memory	206960 kb
Host	smart-a831af75-210f-45ab-acbe-b35b05cbfe9a
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1363708850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.1363708850
Directory	/workspace/9.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/9.usbdev_fifo_rst.1284489215
Short name	T1513
Test name
Test status
Simulation time	191315770 ps
CPU time	1.59 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	207128 kb
Host	smart-8b228d1c-470a-427b-af2b-1e88d534a769
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12844 89215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1284489215
Directory	/workspace/9.usbdev_fifo_rst/latest

Test location	/workspace/coverage/default/9.usbdev_in_iso.353635483
Short name	T79
Test name
Test status
Simulation time	223599406 ps
CPU time	1.06 seconds
Started	Aug 01 06:13:06 PM PDT 24
Finished	Aug 01 06:13:08 PM PDT 24
Peak memory	207112 kb
Host	smart-e53ce145-3cd7-41c8-a278-d6c9bf29b409
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=353635483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.353635483
Directory	/workspace/9.usbdev_in_iso/latest

Test location	/workspace/coverage/default/9.usbdev_in_stall.592666828
Short name	T1011
Test name
Test status
Simulation time	144189981 ps
CPU time	0.83 seconds
Started	Aug 01 06:13:06 PM PDT 24
Finished	Aug 01 06:13:07 PM PDT 24
Peak memory	206904 kb
Host	smart-a3301ff4-6315-4c93-9f83-aa5b6fd0bd00
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59266 6828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.592666828
Directory	/workspace/9.usbdev_in_stall/latest

Test location	/workspace/coverage/default/9.usbdev_in_trans.3247304598
Short name	T449
Test name
Test status
Simulation time	209719709 ps
CPU time	0.93 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206924 kb
Host	smart-d47dca68-cbf6-446f-ae8e-0e502b1aaba5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473 04598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3247304598
Directory	/workspace/9.usbdev_in_trans/latest

Test location	/workspace/coverage/default/9.usbdev_invalid_sync.3929846480
Short name	T1853
Test name
Test status
Simulation time	4964341154 ps
CPU time	36.73 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:46 PM PDT 24
Peak memory	215264 kb
Host	smart-220bb684-1e64-4f8e-b8fa-620a2debeac4
User	root
Command	/workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3929846480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.3929846480
Directory	/workspace/9.usbdev_invalid_sync/latest

Test location	/workspace/coverage/default/9.usbdev_link_in_err.3413069186
Short name	T1923
Test name
Test status
Simulation time	176308384 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:05 PM PDT 24
Finished	Aug 01 06:13:06 PM PDT 24
Peak memory	206928 kb
Host	smart-bc2bd5e7-2d39-45e6-b18e-1b63ad9fd121
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34130 69186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.3413069186
Directory	/workspace/9.usbdev_link_in_err/latest

Test location	/workspace/coverage/default/9.usbdev_low_speed_traffic.574098908
Short name	T1319
Test name
Test status
Simulation time	4033636976 ps
CPU time	28.65 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:36 PM PDT 24
Peak memory	223560 kb
Host	smart-92a2ce94-07d8-4b8a-87bb-22d452aec622
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57409 8908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.574098908
Directory	/workspace/9.usbdev_low_speed_traffic/latest

Test location	/workspace/coverage/default/9.usbdev_max_inter_pkt_delay.353620618
Short name	T2649
Test name
Test status
Simulation time	2815228616 ps
CPU time	82.92 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:14:31 PM PDT 24
Peak memory	216708 kb
Host	smart-303b6225-9087-40b8-aa88-a8860f676464
User	root
Command	/workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=353620618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.353620618
Directory	/workspace/9.usbdev_max_inter_pkt_delay/latest

Test location	/workspace/coverage/default/9.usbdev_max_length_in_transaction.3405886193
Short name	T2186
Test name
Test status
Simulation time	244276117 ps
CPU time	1.03 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206956 kb
Host	smart-7ac714d1-1c48-43eb-a0ff-9d3b71389199
User	root
Command	/workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3405886193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3405886193
Directory	/workspace/9.usbdev_max_length_in_transaction/latest

Test location	/workspace/coverage/default/9.usbdev_max_length_out_transaction.3696611554
Short name	T736
Test name
Test status
Simulation time	202099489 ps
CPU time	0.94 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	206952 kb
Host	smart-1b2f3e3d-4989-481d-830c-64cc9f84d919
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36966 11554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3696611554
Directory	/workspace/9.usbdev_max_length_out_transaction/latest

Test location	/workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.1027936400
Short name	T963
Test name
Test status
Simulation time	2767259315 ps
CPU time	20.79 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:30 PM PDT 24
Peak memory	207408 kb
Host	smart-fdbd833e-7965-4de3-b2d3-29de56e8d77c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10279 36400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.1027936400
Directory	/workspace/9.usbdev_max_non_iso_usb_traffic/latest

Test location	/workspace/coverage/default/9.usbdev_max_usb_traffic.3981281794
Short name	T837
Test name
Test status
Simulation time	2601095263 ps
CPU time	21.5 seconds
Started	Aug 01 06:13:10 PM PDT 24
Finished	Aug 01 06:13:32 PM PDT 24
Peak memory	223732 kb
Host	smart-57218898-64fe-4072-b232-4895f20a9ced
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3981281794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3981281794
Directory	/workspace/9.usbdev_max_usb_traffic/latest

Test location	/workspace/coverage/default/9.usbdev_min_inter_pkt_delay.540485020
Short name	T628
Test name
Test status
Simulation time	1789782449 ps
CPU time	48.43 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:55 PM PDT 24
Peak memory	215284 kb
Host	smart-8472b6d9-1c7f-45e7-87af-dd392a6e2717
User	root
Command	/workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=540485020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.540485020
Directory	/workspace/9.usbdev_min_inter_pkt_delay/latest

Test location	/workspace/coverage/default/9.usbdev_min_length_in_transaction.1405316950
Short name	T794
Test name
Test status
Simulation time	171475223 ps
CPU time	0.88 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:08 PM PDT 24
Peak memory	206924 kb
Host	smart-66b807a5-2029-43c4-990e-c6b452645ea9
User	root
Command	/workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1405316950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.1405316950
Directory	/workspace/9.usbdev_min_length_in_transaction/latest

Test location	/workspace/coverage/default/9.usbdev_min_length_out_transaction.1305690515
Short name	T1507
Test name
Test status
Simulation time	216738966 ps
CPU time	0.93 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:08 PM PDT 24
Peak memory	206972 kb
Host	smart-80243653-1977-400f-895b-63a35d080086
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13056 90515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1305690515
Directory	/workspace/9.usbdev_min_length_out_transaction/latest

Test location	/workspace/coverage/default/9.usbdev_nak_trans.1338665443
Short name	T186
Test name
Test status
Simulation time	185681704 ps
CPU time	0.9 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	206936 kb
Host	smart-0f8a5dd0-19cb-43f1-954c-af79087ebfcc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13386 65443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1338665443
Directory	/workspace/9.usbdev_nak_trans/latest

Test location	/workspace/coverage/default/9.usbdev_out_iso.828982911
Short name	T159
Test name
Test status
Simulation time	170449603 ps
CPU time	0.83 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206920 kb
Host	smart-d1e18ff8-2479-4b6c-a7d6-c0a1a30d3320
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82898 2911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.828982911
Directory	/workspace/9.usbdev_out_iso/latest

Test location	/workspace/coverage/default/9.usbdev_out_stall.2371198934
Short name	T1596
Test name
Test status
Simulation time	181807928 ps
CPU time	0.91 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:08 PM PDT 24
Peak memory	206916 kb
Host	smart-de4e2be5-bdee-4a40-8e60-42c85cafbc21
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23711 98934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2371198934
Directory	/workspace/9.usbdev_out_stall/latest

Test location	/workspace/coverage/default/9.usbdev_out_trans_nak.2829166275
Short name	T1732
Test name
Test status
Simulation time	173454103 ps
CPU time	0.95 seconds
Started	Aug 01 06:13:10 PM PDT 24
Finished	Aug 01 06:13:11 PM PDT 24
Peak memory	206944 kb
Host	smart-dd72a5aa-216d-40fd-af3e-909304dfa3dd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28291 66275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2829166275
Directory	/workspace/9.usbdev_out_trans_nak/latest

Test location	/workspace/coverage/default/9.usbdev_pending_in_trans.429377388
Short name	T833
Test name
Test status
Simulation time	157835902 ps
CPU time	0.88 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	206924 kb
Host	smart-fcc20046-1db8-4933-b32f-696c6e6a98a7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42937 7388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.429377388
Directory	/workspace/9.usbdev_pending_in_trans/latest

Test location	/workspace/coverage/default/9.usbdev_phy_config_pinflip.1544670432
Short name	T1658
Test name
Test status
Simulation time	274337223 ps
CPU time	1.08 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:11 PM PDT 24
Peak memory	207008 kb
Host	smart-e04bd86c-517c-4e48-a9d2-62df3e5c52b9
User	root
Command	/workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1544670432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.1544670432
Directory	/workspace/9.usbdev_phy_config_pinflip/latest

Test location	/workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3424143386
Short name	T1791
Test name
Test status
Simulation time	163980335 ps
CPU time	0.89 seconds
Started	Aug 01 06:13:06 PM PDT 24
Finished	Aug 01 06:13:07 PM PDT 24
Peak memory	206944 kb
Host	smart-f56166d6-cf39-4d5d-904e-74a44c8a3e80
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34241 43386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3424143386
Directory	/workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location	/workspace/coverage/default/9.usbdev_phy_pins_sense.1980428535
Short name	T1760
Test name
Test status
Simulation time	127657809 ps
CPU time	0.79 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206972 kb
Host	smart-00f78f40-105a-48a3-9db9-4c4de23cd2d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19804 28535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1980428535
Directory	/workspace/9.usbdev_phy_pins_sense/latest

Test location	/workspace/coverage/default/9.usbdev_pkt_buffer.3489172746
Short name	T248
Test name
Test status
Simulation time	7007272455 ps
CPU time	20.53 seconds
Started	Aug 01 06:13:11 PM PDT 24
Finished	Aug 01 06:13:32 PM PDT 24
Peak memory	215416 kb
Host	smart-c3d7fc04-a276-4fa5-a986-5f565d1e6c9d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34891 72746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3489172746
Directory	/workspace/9.usbdev_pkt_buffer/latest

Test location	/workspace/coverage/default/9.usbdev_pkt_received.900198084
Short name	T1784
Test name
Test status
Simulation time	222747133 ps
CPU time	0.97 seconds
Started	Aug 01 06:13:08 PM PDT 24
Finished	Aug 01 06:13:09 PM PDT 24
Peak memory	206932 kb
Host	smart-99f97d79-06c9-4a80-b069-180b69dd3732
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90019 8084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.900198084
Directory	/workspace/9.usbdev_pkt_received/latest

Test location	/workspace/coverage/default/9.usbdev_pkt_sent.1547661704
Short name	T1399
Test name
Test status
Simulation time	191322343 ps
CPU time	0.98 seconds
Started	Aug 01 06:13:10 PM PDT 24
Finished	Aug 01 06:13:11 PM PDT 24
Peak memory	206932 kb
Host	smart-3bfc2185-f4a5-404e-96fe-4998247305ef
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476 61704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.1547661704
Directory	/workspace/9.usbdev_pkt_sent/latest

Test location	/workspace/coverage/default/9.usbdev_rand_bus_disconnects.446420797
Short name	T210
Test name
Test status
Simulation time	6294108301 ps
CPU time	32.96 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:42 PM PDT 24
Peak memory	218600 kb
Host	smart-de40e14e-3915-4102-a8c6-be0cf279b1f0
User	root
Command	/workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=446420797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.446420797
Directory	/workspace/9.usbdev_rand_bus_disconnects/latest

Test location	/workspace/coverage/default/9.usbdev_rand_suspends.2723460772
Short name	T2877
Test name
Test status
Simulation time	5581303947 ps
CPU time	19.01 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:28 PM PDT 24
Peak memory	218652 kb
Host	smart-c664afed-e08c-495c-b364-9b1429bafb8e
User	root
Command	/workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723460772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2723460772
Directory	/workspace/9.usbdev_rand_suspends/latest

Test location	/workspace/coverage/default/9.usbdev_random_length_in_transaction.72082978
Short name	T2840
Test name
Test status
Simulation time	220464770 ps
CPU time	1.01 seconds
Started	Aug 01 06:13:09 PM PDT 24
Finished	Aug 01 06:13:10 PM PDT 24
Peak memory	206976 kb
Host	smart-f4130e3e-865b-4c57-88a8-29eee76ace6a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72082 978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.72082978
Directory	/workspace/9.usbdev_random_length_in_transaction/latest

Test location	/workspace/coverage/default/9.usbdev_random_length_out_transaction.3350261227
Short name	T1021
Test name
Test status
Simulation time	175013225 ps
CPU time	0.9 seconds
Started	Aug 01 06:13:10 PM PDT 24
Finished	Aug 01 06:13:11 PM PDT 24
Peak memory	206924 kb
Host	smart-74a6d3cd-330f-40f4-bbbc-43a880d5c045
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33502 61227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3350261227
Directory	/workspace/9.usbdev_random_length_out_transaction/latest

Test location	/workspace/coverage/default/9.usbdev_rx_crc_err.3847024196
Short name	T1291
Test name
Test status
Simulation time	148586285 ps
CPU time	0.81 seconds
Started	Aug 01 06:13:11 PM PDT 24
Finished	Aug 01 06:13:12 PM PDT 24
Peak memory	206896 kb
Host	smart-8d3b0c23-4d1c-48aa-bb75-f2377d875223
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38470 24196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3847024196
Directory	/workspace/9.usbdev_rx_crc_err/latest

Test location	/workspace/coverage/default/9.usbdev_rx_full.953508680
Short name	T1598
Test name
Test status
Simulation time	256347940 ps
CPU time	1.23 seconds
Started	Aug 01 06:13:11 PM PDT 24
Finished	Aug 01 06:13:12 PM PDT 24
Peak memory	206956 kb
Host	smart-7896a38d-2533-49de-bfd9-91ded9fb5297
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95350 8680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.953508680
Directory	/workspace/9.usbdev_rx_full/latest

Test location	/workspace/coverage/default/9.usbdev_setup_stage.1073000476
Short name	T528
Test name
Test status
Simulation time	155839496 ps
CPU time	0.88 seconds
Started	Aug 01 06:13:10 PM PDT 24
Finished	Aug 01 06:13:11 PM PDT 24
Peak memory	206912 kb
Host	smart-0b93e7a4-ef05-4370-b080-96a8679e4adb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10730 00476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1073000476
Directory	/workspace/9.usbdev_setup_stage/latest

Test location	/workspace/coverage/default/9.usbdev_setup_trans_ignored.1191624388
Short name	T2791
Test name
Test status
Simulation time	149281957 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:10 PM PDT 24
Finished	Aug 01 06:13:11 PM PDT 24
Peak memory	206948 kb
Host	smart-b7c56d63-dd73-4b55-aa89-979eb8b082ed
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11916 24388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1191624388
Directory	/workspace/9.usbdev_setup_trans_ignored/latest

Test location	/workspace/coverage/default/9.usbdev_smoke.1880450405
Short name	T1979
Test name
Test status
Simulation time	318251546 ps
CPU time	1.12 seconds
Started	Aug 01 06:13:11 PM PDT 24
Finished	Aug 01 06:13:13 PM PDT 24
Peak memory	206896 kb
Host	smart-15e42f76-6055-436f-b612-de54b30467b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18804 50405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1880450405
Directory	/workspace/9.usbdev_smoke/latest

Test location	/workspace/coverage/default/9.usbdev_spurious_pids_ignored.210636505
Short name	T889
Test name
Test status
Simulation time	2964860551 ps
CPU time	83.66 seconds
Started	Aug 01 06:13:03 PM PDT 24
Finished	Aug 01 06:14:27 PM PDT 24
Peak memory	216948 kb
Host	smart-ad4bdbf0-d96f-448c-a853-3ef0f98d5704
User	root
Command	/workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=210636505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.210636505
Directory	/workspace/9.usbdev_spurious_pids_ignored/latest

Test location	/workspace/coverage/default/9.usbdev_stall_priority_over_nak.2935343646
Short name	T976
Test name
Test status
Simulation time	214097836 ps
CPU time	0.96 seconds
Started	Aug 01 06:13:11 PM PDT 24
Finished	Aug 01 06:13:13 PM PDT 24
Peak memory	206900 kb
Host	smart-4b483ff4-9fb8-4e04-a935-14cb850e89b8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29353 43646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2935343646
Directory	/workspace/9.usbdev_stall_priority_over_nak/latest

Test location	/workspace/coverage/default/9.usbdev_stall_trans.3293452934
Short name	T1029
Test name
Test status
Simulation time	193360161 ps
CPU time	0.87 seconds
Started	Aug 01 06:13:24 PM PDT 24
Finished	Aug 01 06:13:25 PM PDT 24
Peak memory	206948 kb
Host	smart-9073521f-dd15-4906-83a1-c7439612c059
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32934 52934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3293452934
Directory	/workspace/9.usbdev_stall_trans/latest

Test location	/workspace/coverage/default/9.usbdev_stream_len_max.4132319132
Short name	T2810
Test name
Test status
Simulation time	644089124 ps
CPU time	1.84 seconds
Started	Aug 01 06:13:26 PM PDT 24
Finished	Aug 01 06:13:28 PM PDT 24
Peak memory	206876 kb
Host	smart-0f8f25eb-a9fd-472b-8eb0-24753783f9a9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41323 19132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.4132319132
Directory	/workspace/9.usbdev_stream_len_max/latest

Test location	/workspace/coverage/default/9.usbdev_streaming_out.4289749137
Short name	T862
Test name
Test status
Simulation time	1925959458 ps
CPU time	53.36 seconds
Started	Aug 01 06:13:24 PM PDT 24
Finished	Aug 01 06:14:17 PM PDT 24
Peak memory	216688 kb
Host	smart-318cffa2-72fe-433b-bccf-1f8c4a696ce7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42897 49137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.4289749137
Directory	/workspace/9.usbdev_streaming_out/latest

Test location	/workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.717237828
Short name	T813
Test name
Test status
Simulation time	992629374 ps
CPU time	21.18 seconds
Started	Aug 01 06:13:07 PM PDT 24
Finished	Aug 01 06:13:28 PM PDT 24
Peak memory	207148 kb
Host	smart-e0740e16-210e-47d4-805e-48a16ed88405
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717237828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host_ handshake.717237828
Directory	/workspace/9.usbdev_timeout_missing_host_handshake/latest

Test location	/workspace/coverage/default/90.usbdev_endpoint_types.815541224
Short name	T2465
Test name
Test status
Simulation time	614522878 ps
CPU time	1.59 seconds
Started	Aug 01 06:20:05 PM PDT 24
Finished	Aug 01 06:20:06 PM PDT 24
Peak memory	206896 kb
Host	smart-34a211ad-c74d-44d7-9483-ef8dda35cd6c
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=815541224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.815541224
Directory	/workspace/90.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/91.usbdev_endpoint_types.3851668805
Short name	T164
Test name
Test status
Simulation time	352088872 ps
CPU time	1.14 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:01 PM PDT 24
Peak memory	206976 kb
Host	smart-d036c4ef-d476-45db-a552-8c3355c7ff56
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3851668805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.3851668805
Directory	/workspace/91.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/92.usbdev_endpoint_types.2332876710
Short name	T393
Test name
Test status
Simulation time	530003742 ps
CPU time	1.52 seconds
Started	Aug 01 06:19:58 PM PDT 24
Finished	Aug 01 06:19:59 PM PDT 24
Peak memory	206884 kb
Host	smart-4729377f-0226-4782-bca4-a975a44df9cc
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2332876710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.2332876710
Directory	/workspace/92.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/93.usbdev_endpoint_types.741376876
Short name	T2835
Test name
Test status
Simulation time	594419367 ps
CPU time	1.59 seconds
Started	Aug 01 06:19:59 PM PDT 24
Finished	Aug 01 06:20:01 PM PDT 24
Peak memory	206900 kb
Host	smart-913a7aae-46ea-477e-921c-ccf3a67d16c8
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=741376876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.741376876
Directory	/workspace/93.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/94.usbdev_endpoint_types.3475540661
Short name	T2696
Test name
Test status
Simulation time	177786176 ps
CPU time	0.95 seconds
Started	Aug 01 06:20:00 PM PDT 24
Finished	Aug 01 06:20:01 PM PDT 24
Peak memory	206976 kb
Host	smart-0352ca24-00dc-4e95-ae85-74a131260b95
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3475540661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.3475540661
Directory	/workspace/94.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/95.usbdev_endpoint_types.250924953
Short name	T163
Test name
Test status
Simulation time	485921707 ps
CPU time	1.55 seconds
Started	Aug 01 06:20:06 PM PDT 24
Finished	Aug 01 06:20:07 PM PDT 24
Peak memory	206920 kb
Host	smart-c16c131c-e82e-4df4-8e8c-02223daa902b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=250924953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.250924953
Directory	/workspace/95.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/97.usbdev_endpoint_types.2073519050
Short name	T357
Test name
Test status
Simulation time	244167810 ps
CPU time	0.97 seconds
Started	Aug 01 06:20:03 PM PDT 24
Finished	Aug 01 06:20:04 PM PDT 24
Peak memory	206912 kb
Host	smart-5995f1f6-750a-4652-b881-152888cbe590
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2073519050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.2073519050
Directory	/workspace/97.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/98.usbdev_endpoint_types.1343089130
Short name	T2467
Test name
Test status
Simulation time	414016816 ps
CPU time	1.27 seconds
Started	Aug 01 06:20:25 PM PDT 24
Finished	Aug 01 06:20:26 PM PDT 24
Peak memory	206920 kb
Host	smart-58019e72-5d89-4414-8151-cd59b31c7f1b
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1343089130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.1343089130
Directory	/workspace/98.usbdev_endpoint_types/latest

Test location	/workspace/coverage/default/99.usbdev_endpoint_types.906718057
Short name	T335
Test name
Test status
Simulation time	892889741 ps
CPU time	1.93 seconds
Started	Aug 01 06:20:13 PM PDT 24
Finished	Aug 01 06:20:16 PM PDT 24
Peak memory	206924 kb
Host	smart-1aff58fa-f401-420a-be7a-24c36d3d4ca2
User	root
Command	/workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=906718057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.906718057
Directory	/workspace/99.usbdev_endpoint_types/latest

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