Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	167799	1		T1	2		T2	2		T3	13
all_values[1]	167799	1		T1	2		T2	2		T3	13
all_values[2]	167799	1		T1	2		T2	2		T3	13
all_values[3]	167799	1		T1	2		T2	2		T3	13
all_values[4]	167799	1		T1	2		T2	2		T3	13
all_values[5]	167799	1		T1	2		T2	2		T3	13
all_values[6]	167799	1		T1	2		T2	2		T3	13
all_values[7]	167799	1		T1	2		T2	2		T3	13
all_values[8]	167799	1		T1	2		T2	2		T3	13
all_values[9]	167799	1		T1	2		T2	2		T3	13
all_values[10]	167799	1		T1	2		T2	2		T3	13
all_values[11]	167799	1		T1	2		T2	2		T3	13
all_values[12]	167799	1		T1	2		T2	2		T3	13
all_values[13]	167799	1		T1	2		T2	2		T3	13
all_values[14]	167799	1		T1	2		T2	2		T3	13
all_values[15]	167799	1		T1	2		T2	2		T3	13
all_values[16]	167799	1		T1	2		T2	2		T3	13
all_values[17]	167799	1		T1	2		T2	2		T3	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5362226	1		T1	64		T2	64		T3	405
auto[1]	7342	1		T3	11		T30	14		T32	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4606159	1		T1	57		T2	58		T3	389
auto[1]	763409	1		T1	7		T2	6		T3	27

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142349	1		T1	2		T2	2		T3	5
all_values[0]	auto[0]	auto[1]	24600	1		T3	8		T83	4		T188	2
all_values[0]	auto[1]	auto[0]	742	1		T23	3		T43	3		T44	3
all_values[0]	auto[1]	auto[1]	108	1		T326	1		T327	1		T328	1
all_values[1]	auto[0]	auto[0]	164767	1		T1	2		T2	2		T3	13
all_values[1]	auto[0]	auto[1]	1600	1		T5	2		T6	2		T35	2
all_values[1]	auto[1]	auto[0]	549	1		T30	2		T32	2		T7	1
all_values[1]	auto[1]	auto[1]	883	1		T30	12		T32	1		T7	1
all_values[2]	auto[0]	auto[0]	3714	1		T1	1		T2	1		T3	12
all_values[2]	auto[0]	auto[1]	163814	1		T1	1		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	146	1		T24	1		T42	1		T61	1
all_values[2]	auto[1]	auto[1]	125	1		T24	1		T42	1		T61	1
all_values[3]	auto[0]	auto[0]	165852	1		T1	2		T2	2		T3	13
all_values[3]	auto[0]	auto[1]	293	1		T62	1		T63	1		T64	1
all_values[3]	auto[1]	auto[0]	1583	1		T65	1483		T213	1		T218	1
all_values[3]	auto[1]	auto[1]	71	1		T65	1		T213	3		T216	2
all_values[4]	auto[0]	auto[0]	3693	1		T1	1		T2	1		T3	12
all_values[4]	auto[0]	auto[1]	163929	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	101	1		T66	1		T213	2		T216	1
all_values[4]	auto[1]	auto[1]	76	1		T66	1		T213	2		T214	5
all_values[5]	auto[0]	auto[0]	167273	1		T1	2		T2	2		T3	13
all_values[5]	auto[0]	auto[1]	358	1		T7	1		T56	1		T8	1
all_values[5]	auto[1]	auto[0]	88	1		T213	1		T218	5		T216	2
all_values[5]	auto[1]	auto[1]	80	1		T213	3		T216	2		T217	1
all_values[6]	auto[0]	auto[0]	167380	1		T1	2		T2	2		T3	13
all_values[6]	auto[0]	auto[1]	192	1		T56	1		T8	1		T62	1
all_values[6]	auto[1]	auto[0]	105	1		T216	2		T214	1		T219	1
all_values[6]	auto[1]	auto[1]	122	1		T41	1		T67	1		T68	1
all_values[7]	auto[0]	auto[0]	114925	1		T2	2		T4	2		T5	2
all_values[7]	auto[0]	auto[1]	52707	1		T1	2		T3	13		T30	14
all_values[7]	auto[1]	auto[0]	102	1		T46	1		T47	1		T48	1
all_values[7]	auto[1]	auto[1]	65	1		T46	1		T47	1		T48	1
all_values[8]	auto[0]	auto[0]	167063	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	51	1		T213	1		T214	2		T217	1
all_values[8]	auto[1]	auto[0]	602	1		T3	10		T49	10		T50	10
all_values[8]	auto[1]	auto[1]	83	1		T3	1		T49	1		T50	1
all_values[9]	auto[0]	auto[0]	167533	1		T1	2		T2	2		T3	13
all_values[9]	auto[0]	auto[1]	75	1		T213	1		T216	2		T214	4
all_values[9]	auto[1]	auto[0]	109	1		T58	3		T59	3		T60	3
all_values[9]	auto[1]	auto[1]	82	1		T58	2		T59	2		T60	2
all_values[10]	auto[0]	auto[0]	167328	1		T1	2		T2	2		T3	13
all_values[10]	auto[0]	auto[1]	307	1		T19	1		T25	1		T57	1
all_values[10]	auto[1]	auto[0]	97	1		T213	1		T214	2		T217	2
all_values[10]	auto[1]	auto[1]	67	1		T213	1		T218	1		T214	4
all_values[11]	auto[0]	auto[0]	167394	1		T1	2		T2	2		T3	13
all_values[11]	auto[0]	auto[1]	145	1		T62	1		T74	1		T75	1
all_values[11]	auto[1]	auto[0]	142	1		T20	1		T72	1		T73	1
all_values[11]	auto[1]	auto[1]	118	1		T20	1		T72	1		T73	1
all_values[12]	auto[0]	auto[0]	167520	1		T1	2		T2	2		T3	13
all_values[12]	auto[0]	auto[1]	97	1		T62	1		T77	1		T80	1
all_values[12]	auto[1]	auto[0]	108	1		T76	2		T78	2		T79	2
all_values[12]	auto[1]	auto[1]	74	1		T76	1		T78	1		T79	1
all_values[13]	auto[0]	auto[0]	167482	1		T1	2		T2	2		T3	13
all_values[13]	auto[0]	auto[1]	75	1		T62	1		T77	1		T80	1
all_values[13]	auto[1]	auto[0]	131	1		T74	1		T75	1		T81	1
all_values[13]	auto[1]	auto[1]	111	1		T74	1		T75	1		T81	1
all_values[14]	auto[0]	auto[0]	32970	1		T1	2		T2	1		T3	13
all_values[14]	auto[0]	auto[1]	134669	1		T2	1		T4	1		T5	1
all_values[14]	auto[1]	auto[0]	117	1		T213	3		T218	3		T216	3
all_values[14]	auto[1]	auto[1]	43	1		T216	1		T219	1		T322	1
all_values[15]	auto[0]	auto[0]	3731	1		T1	1		T2	1		T3	12
all_values[15]	auto[0]	auto[1]	163899	1		T1	1		T2	1		T3	1
all_values[15]	auto[1]	auto[0]	98	1		T213	1		T216	2		T214	2
all_values[15]	auto[1]	auto[1]	71	1		T214	4		T215	2		T321	2
all_values[16]	auto[0]	auto[0]	167139	1		T1	2		T2	2		T3	13
all_values[16]	auto[0]	auto[1]	486	1		T33	1		T34	1		T36	1
all_values[16]	auto[1]	auto[0]	99	1		T69	4		T70	4		T71	4
all_values[16]	auto[1]	auto[1]	75	1		T69	4		T70	4		T71	4
all_values[17]	auto[0]	auto[0]	113829	1		T3	11		T4	2		T5	2
all_values[17]	auto[0]	auto[1]	53801	1		T1	2		T2	2		T3	2
all_values[17]	auto[1]	auto[0]	112	1		T54	1		T55	1		T213	2
all_values[17]	auto[1]	auto[1]	57	1		T54	1		T55	1		T213	2