Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	110697	1		T3	8		T30	12		T32	1
auto[1]	43238	1		T30	12		T32	1		T4	45

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	28738	1		T6	2		T35	2		T92	2
max_len_m1	801	1		T5	6		T6	2		T35	2
max_len_m2	793	1		T30	2		T4	2		T5	4
max_len_m3	779	1		T5	2		T35	2		T17	1
five	1128	1		T30	2		T4	4		T5	6
four	1080	1		T30	2		T4	2		T164	3
three	711	1		T35	2		T164	1		T166	1
one	739	1		T4	1		T35	1		T164	2
zero	11094	1		T30	2		T35	1		T19	8

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23492	1		T6	1		T35	1		T92	1
max_len	auto[1]	5246	1		T6	1		T35	1		T92	1
max_len_m1	auto[0]	546	1		T5	3		T6	1		T35	1
max_len_m1	auto[1]	255	1		T5	3		T6	1		T35	1
max_len_m2	auto[0]	552	1		T30	1		T4	1		T5	2
max_len_m2	auto[1]	241	1		T30	1		T4	1		T5	2
max_len_m3	auto[0]	537	1		T5	1		T35	2		T17	1
max_len_m3	auto[1]	242	1		T5	1		T352	1		T239	2
five	auto[0]	615	1		T30	1		T4	2		T5	3
five	auto[1]	513	1		T30	1		T4	2		T5	3
four	auto[0]	557	1		T30	1		T4	2		T164	2
four	auto[1]	523	1		T30	1		T164	1		T92	1
three	auto[0]	318	1		T35	2		T164	1		T166	1
three	auto[1]	393	1		T353	1		T110	8		T354	1
one	auto[0]	345	1		T4	1		T35	1		T164	2
one	auto[1]	394	1		T351	1		T110	7		T14	1
zero	auto[0]	547	1		T30	1		T35	1		T164	1
zero	auto[1]	10547	1		T30	1		T19	8		T25	3