Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
56.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	96	48	48	50.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	48	48	50.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	65764	1		T3	8		T30	12		T32	1
auto[1]	37798	1		T30	12		T32	1		T4	45

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	9966	1		T30	2		T32	2		T4	18
endpoints[0x1]	8796	1		T30	2		T4	18		T34	2
endpoints[0x2]	8895	1		T30	2		T4	18		T5	18
endpoints[0x3]	6889	1		T30	2		T5	18		T35	10
endpoints[0x4]	6607	1		T30	2		T6	86		T19	1
endpoints[0x5]	8169	1		T30	2		T4	18		T5	18
endpoints[0x6]	8009	1		T30	2		T35	10		T7	2
endpoints[0x7]	8268	1		T3	8		T30	2		T35	10
endpoints[0x8]	8620	1		T30	2		T35	10		T19	3
endpoints[0x9]	10866	1		T30	2		T4	18		T5	18
endpoints[0xa]	10389	1		T30	2		T33	1		T35	10
endpoints[0xb]	8088	1		T30	2		T5	18		T109	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	47711	1		T4	42		T5	50		T6	43
data0	55841	1		T3	8		T30	24		T32	2

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	48	48	50.00	48

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	48

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	endpoints[0x0]	2916	1		T4	4		T5	4		T19	1
data1	auto[0]	endpoints[0x1]	2437	1		T4	4		T34	1		T35	1
data1	auto[0]	endpoints[0x2]	2375	1		T4	4		T5	4		T35	2
data1	auto[0]	endpoints[0x3]	1423	1		T5	3		T35	2		T107	1
data1	auto[0]	endpoints[0x4]	1348	1		T6	14		T107	3		T92	3
data1	auto[0]	endpoints[0x5]	2263	1		T4	3		T5	4		T19	2
data1	auto[0]	endpoints[0x6]	2209	1		T35	2		T19	1		T164	3
data1	auto[0]	endpoints[0x7]	2185	1		T35	2		T19	1		T107	2
data1	auto[0]	endpoints[0x8]	2376	1		T35	1		T19	1		T166	3
data1	auto[0]	endpoints[0x9]	3428	1		T4	3		T5	4		T164	3
data1	auto[0]	endpoints[0xa]	3175	1		T35	2		T166	1		T92	1
data1	auto[0]	endpoints[0xb]	2032	1		T5	4		T35	2		T19	1
data1	auto[1]	endpoints[0x0]	1729	1		T4	4		T5	4		T164	4
data1	auto[1]	endpoints[0x1]	1671	1		T4	4		T35	3		T107	3
data1	auto[1]	endpoints[0x2]	1706	1		T4	5		T5	4		T35	2
data1	auto[1]	endpoints[0x3]	1678	1		T5	6		T35	2		T107	5
data1	auto[1]	endpoints[0x4]	1605	1		T6	29		T57	1		T107	3
data1	auto[1]	endpoints[0x5]	1508	1		T4	6		T5	4		T19	2
data1	auto[1]	endpoints[0x6]	1499	1		T35	2		T164	3		T62	6
data1	auto[1]	endpoints[0x7]	1602	1		T35	2		T107	5		T164	3
data1	auto[1]	endpoints[0x8]	1558	1		T35	4		T25	2		T166	3
data1	auto[1]	endpoints[0x9]	1631	1		T4	5		T5	4		T19	1
data1	auto[1]	endpoints[0xa]	1646	1		T35	3		T19	1		T166	4
data1	auto[1]	endpoints[0xb]	1711	1		T5	5		T35	2		T107	5
data0	auto[0]	endpoints[0x0]	3700	1		T30	1		T32	1		T4	5
data0	auto[0]	endpoints[0x1]	3146	1		T30	1		T4	5		T34	1
data0	auto[0]	endpoints[0x2]	3217	1		T30	1		T4	5		T5	5
data0	auto[0]	endpoints[0x3]	2249	1		T30	1		T5	6		T35	3
data0	auto[0]	endpoints[0x4]	2187	1		T30	1		T6	29		T20	1
data0	auto[0]	endpoints[0x5]	3019	1		T30	1		T4	6		T5	5
data0	auto[0]	endpoints[0x6]	2905	1		T30	1		T35	3		T7	1
data0	auto[0]	endpoints[0x7]	2970	1		T3	8		T30	1		T35	3
data0	auto[0]	endpoints[0x8]	3182	1		T30	1		T35	4		T19	1
data0	auto[0]	endpoints[0x9]	4317	1		T30	1		T4	6		T5	5
data0	auto[0]	endpoints[0xa]	4001	1		T30	1		T33	1		T35	3
data0	auto[0]	endpoints[0xb]	2694	1		T30	1		T5	5		T109	1
data0	auto[1]	endpoints[0x0]	1621	1		T30	1		T32	1		T4	5
data0	auto[1]	endpoints[0x1]	1542	1		T30	1		T4	5		T35	2
data0	auto[1]	endpoints[0x2]	1597	1		T30	1		T4	4		T5	5
data0	auto[1]	endpoints[0x3]	1538	1		T30	1		T5	3		T35	3
data0	auto[1]	endpoints[0x4]	1465	1		T30	1		T6	14		T19	1
data0	auto[1]	endpoints[0x5]	1378	1		T30	1		T4	3		T5	5
data0	auto[1]	endpoints[0x6]	1396	1		T30	1		T35	3		T7	1
data0	auto[1]	endpoints[0x7]	1509	1		T30	1		T35	3		T19	2
data0	auto[1]	endpoints[0x8]	1503	1		T30	1		T35	1		T19	1
data0	auto[1]	endpoints[0x9]	1489	1		T30	1		T4	4		T5	5
data0	auto[1]	endpoints[0xa]	1565	1		T30	1		T35	2		T56	1
data0	auto[1]	endpoints[0xb]	1651	1		T30	1		T5	4		T35	3