Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
75.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	6	10	62.50

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	6	10	62.50	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6456	1		T4	5		T18	1		T86	2
auto[1]	49100	1		T1	1		T30	12		T31	1

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	49709	1		T1	1		T30	12		T31	1
auto[1]	5847	1		T18	1		T100	1		T95	1

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	51344	1		T30	12		T32	1		T4	57
auto[1]	4212	1		T1	1		T31	1		T18	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	332	1		T4	7		T164	10		T166	8
pkt_types[PidTypeInToken]	55224	1		T1	1		T30	12		T31	1

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	6	10	62.50	6

Automatically Generated Cross Bins for cr_pid_x_epconfig

Element holes

cp_pid	cp_in_enable	cp_in_iso	cp_in_stall	COUNT	AT LEAST	NUMBER
[ignore_pre[PidTypePre]]	*	[auto[0]]	[auto[1]]	--	--	2
[ignore_pre[PidTypePre]]	*	[auto[1]]	*	--	--	4

Covered bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

166

1

T4

5

T164

3

T166

4

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

166

1

T4

2

T164

7

T166

4

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

4151

1

T18

1

T86

2

T100

3

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

2038

1

T100

1

T305

3

T88

50

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

55

1

T311

1

T312

1

T313

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

46

1

T101

1

T314

1

T315

4

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

41099

1

T30

12

T32

1

T4

50

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2089

1

T1

1

T31

1

T86

1

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

5707

1

T95

1

T96

1

T64

130

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

39

1

T18

1

T100

1

T311

1