Summary for Variable cp_avout
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_avout
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full |
19835 |
1 |
|
T4 |
45 |
|
T5 |
54 |
|
T6 |
43 |
solo |
71772 |
1 |
|
T30 |
12 |
|
T32 |
1 |
|
T33 |
1 |
empty |
2315 |
1 |
|
T3 |
8 |
|
T23 |
1 |
|
T86 |
1 |
Summary for Variable cp_avsetup
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for cp_avsetup
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full |
19870 |
1 |
|
T3 |
1 |
|
T4 |
45 |
|
T5 |
54 |
solo |
30484 |
1 |
|
T18 |
4 |
|
T86 |
10 |
|
T43 |
1 |
empty |
43611 |
1 |
|
T30 |
12 |
|
T32 |
1 |
|
T33 |
1 |
Summary for Variable cp_pid
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_pid
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
out |
73316 |
1 |
|
T30 |
12 |
|
T32 |
1 |
|
T4 |
31 |
setup |
20806 |
1 |
|
T3 |
8 |
|
T4 |
14 |
|
T5 |
7 |
Summary for Variable cp_rx
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
1 |
2 |
66.67 |
User Defined Bins for cp_rx
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER |
full |
0 |
1 |
1 |
Covered bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
solo |
41 |
1 |
|
T3 |
1 |
|
T49 |
1 |
|
T50 |
1 |
empty |
78776 |
1 |
|
T3 |
1 |
|
T30 |
12 |
|
T32 |
1 |
Summary for Cross cr_fifo_X_pid
Samples crossed: cp_avsetup cp_avout cp_rx cp_pid
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
54 |
39 |
15 |
27.78 |
39 |
Automatically Generated Cross Bins for cr_fifo_X_pid
Element holes
cp_avsetup | cp_avout | cp_rx | cp_pid | COUNT | AT LEAST | NUMBER |
[full] |
[full] |
[full , solo] |
* |
-- |
-- |
4 |
[full] |
[solo] |
* |
* |
-- |
-- |
6 |
[full] |
[empty] |
[full] |
* |
-- |
-- |
2 |
[solo] |
[full] |
[full , solo] |
* |
-- |
-- |
4 |
[solo] |
[solo] |
[full] |
* |
-- |
-- |
2 |
[solo] |
[empty] |
[full] |
* |
-- |
-- |
2 |
[empty] |
[full , solo] |
[full , solo] |
* |
-- |
-- |
8 |
[empty] |
[empty] |
[full , solo] |
* |
-- |
-- |
4 |
Uncovered bins
cp_avsetup | cp_avout | cp_rx | cp_pid | COUNT | AT LEAST | NUMBER |
[full] |
[empty] |
[solo , empty] |
[out] |
-- |
-- |
2 |
[solo] |
[full] |
[empty] |
[setup] |
0 |
1 |
1 |
[solo] |
[empty] |
[solo , empty] |
[out] |
-- |
-- |
2 |
[empty] |
[full , solo] |
[empty] |
[setup] |
-- |
-- |
2 |
Covered bins
cp_avsetup | cp_avout | cp_rx | cp_pid | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
full |
full |
empty |
out |
15641 |
1 |
|
T4 |
31 |
|
T5 |
47 |
|
T6 |
20 |
full |
full |
empty |
setup |
4179 |
1 |
|
T4 |
14 |
|
T5 |
7 |
|
T6 |
23 |
full |
empty |
solo |
setup |
6 |
1 |
|
T50 |
1 |
|
T301 |
1 |
|
T302 |
1 |
full |
empty |
empty |
setup |
6 |
1 |
|
T303 |
1 |
|
T301 |
1 |
|
T304 |
1 |
solo |
full |
empty |
out |
5 |
1 |
|
T51 |
1 |
|
T52 |
1 |
|
T53 |
1 |
solo |
solo |
solo |
out |
5 |
1 |
|
T51 |
1 |
|
T52 |
1 |
|
T53 |
1 |
solo |
solo |
solo |
setup |
5 |
1 |
|
T51 |
1 |
|
T52 |
1 |
|
T53 |
1 |
solo |
solo |
empty |
out |
8356 |
1 |
|
T86 |
6 |
|
T100 |
7 |
|
T305 |
9 |
solo |
solo |
empty |
setup |
8299 |
1 |
|
T18 |
4 |
|
T86 |
3 |
|
T100 |
2 |
solo |
empty |
solo |
setup |
4 |
1 |
|
T49 |
1 |
|
T306 |
1 |
|
T304 |
1 |
solo |
empty |
empty |
setup |
561 |
1 |
|
T86 |
1 |
|
T43 |
1 |
|
T188 |
1 |
empty |
full |
empty |
out |
3 |
1 |
|
T307 |
1 |
|
T308 |
1 |
|
T309 |
1 |
empty |
solo |
empty |
out |
41504 |
1 |
|
T30 |
12 |
|
T32 |
1 |
|
T33 |
1 |
empty |
empty |
empty |
out |
132 |
1 |
|
T69 |
1 |
|
T70 |
1 |
|
T65 |
129 |
empty |
empty |
empty |
setup |
50 |
1 |
|
T23 |
1 |
|
T124 |
1 |
|
T310 |
1 |