Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
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Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
38.46 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 11 1 10 90.91
Crosses 54 39 15 27.78


Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_avout 3 0 3 100.00 100 1 1 0
cp_avsetup 3 0 3 100.00 100 1 1 0
cp_pid 2 0 2 100.00 100 1 1 0
cp_rx 3 1 2 66.67 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_fifo_X_pid 54 39 15 27.78 100 1 1 0


Summary for Variable cp_avout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_avout

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
full 19835 1 T4 45 T5 54 T6 43
solo 71772 1 T30 12 T32 1 T33 1
empty 2315 1 T3 8 T23 1 T86 1



Summary for Variable cp_avsetup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_avsetup

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
full 19870 1 T3 1 T4 45 T5 54
solo 30484 1 T18 4 T86 10 T43 1
empty 43611 1 T30 12 T32 1 T33 1



Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
out 73316 1 T30 12 T32 1 T4 31
setup 20806 1 T3 8 T4 14 T5 7



Summary for Variable cp_rx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 1 2 66.67


User Defined Bins for cp_rx

Uncovered bins
NAMECOUNTAT LEASTNUMBER
full 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
solo 41 1 T3 1 T49 1 T50 1
empty 78776 1 T3 1 T30 12 T32 1



Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 54 39 15 27.78 39


Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes
cp_avsetupcp_avoutcp_rxcp_pidCOUNTAT LEASTNUMBER
[full] [full] [full , solo] * -- -- 4
[full] [solo] * * -- -- 6
[full] [empty] [full] * -- -- 2
[solo] [full] [full , solo] * -- -- 4
[solo] [solo] [full] * -- -- 2
[solo] [empty] [full] * -- -- 2
[empty] [full , solo] [full , solo] * -- -- 8
[empty] [empty] [full , solo] * -- -- 4


Uncovered bins
cp_avsetupcp_avoutcp_rxcp_pidCOUNTAT LEASTNUMBER
[full] [empty] [solo , empty] [out] -- -- 2
[solo] [full] [empty] [setup] 0 1 1
[solo] [empty] [solo , empty] [out] -- -- 2
[empty] [full , solo] [empty] [setup] -- -- 2


Covered bins
cp_avsetupcp_avoutcp_rxcp_pidCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
full full empty out 15641 1 T4 31 T5 47 T6 20
full full empty setup 4179 1 T4 14 T5 7 T6 23
full empty solo setup 6 1 T50 1 T301 1 T302 1
full empty empty setup 6 1 T303 1 T301 1 T304 1
solo full empty out 5 1 T51 1 T52 1 T53 1
solo solo solo out 5 1 T51 1 T52 1 T53 1
solo solo solo setup 5 1 T51 1 T52 1 T53 1
solo solo empty out 8356 1 T86 6 T100 7 T305 9
solo solo empty setup 8299 1 T18 4 T86 3 T100 2
solo empty solo setup 4 1 T49 1 T306 1 T304 1
solo empty empty setup 561 1 T86 1 T43 1 T188 1
empty full empty out 3 1 T307 1 T308 1 T309 1
empty solo empty out 41504 1 T30 12 T32 1 T33 1
empty empty empty out 132 1 T69 1 T70 1 T65 129
empty empty empty setup 50 1 T23 1 T124 1 T310 1

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