Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	167799	1		T1	2		T2	2		T3	13
all_pins[1]	167799	1		T1	2		T2	2		T3	13
all_pins[2]	167799	1		T1	2		T2	2		T3	13
all_pins[3]	167799	1		T1	2		T2	2		T3	13
all_pins[4]	167799	1		T1	2		T2	2		T3	13
all_pins[5]	167799	1		T1	2		T2	2		T3	13
all_pins[6]	167799	1		T1	2		T2	2		T3	13
all_pins[7]	167799	1		T1	2		T2	2		T3	13
all_pins[8]	167799	1		T1	2		T2	2		T3	13
all_pins[9]	167799	1		T1	2		T2	2		T3	13
all_pins[10]	167799	1		T1	2		T2	2		T3	13
all_pins[11]	167799	1		T1	2		T2	2		T3	13
all_pins[12]	167799	1		T1	2		T2	2		T3	13
all_pins[13]	167799	1		T1	2		T2	2		T3	13
all_pins[14]	167799	1		T1	2		T2	2		T3	13
all_pins[15]	167799	1		T1	2		T2	2		T3	13
all_pins[16]	167799	1		T1	2		T2	2		T3	13
all_pins[17]	167799	1		T1	2		T2	2		T3	13

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5367257	1		T1	64		T2	64		T3	415
values[0x1]	2311	1		T3	1		T30	12		T32	1
transitions[0x0=>0x1]	2014	1		T3	1		T30	12		T32	1
transitions[0x1=>0x0]	2014	1		T3	1		T30	12		T32	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	167691	1		T1	2		T2	2		T3	13
all_pins[0]	values[0x1]	108	1		T326	1		T327	1		T328	1
all_pins[0]	transitions[0x0=>0x1]	97	1		T326	1		T327	1		T328	1
all_pins[0]	transitions[0x1=>0x0]	872	1		T30	12		T32	1		T7	1
all_pins[1]	values[0x0]	166916	1		T1	2		T2	2		T3	13
all_pins[1]	values[0x1]	883	1		T30	12		T32	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	868	1		T30	12		T32	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	110	1		T24	1		T42	1		T61	1
all_pins[2]	values[0x0]	167674	1		T1	2		T2	2		T3	13
all_pins[2]	values[0x1]	125	1		T24	1		T42	1		T61	1
all_pins[2]	transitions[0x0=>0x1]	101	1		T24	1		T42	1		T61	1
all_pins[2]	transitions[0x1=>0x0]	47	1		T65	1		T216	2		T322	2
all_pins[3]	values[0x0]	167728	1		T1	2		T2	2		T3	13
all_pins[3]	values[0x1]	71	1		T65	1		T213	3		T216	2
all_pins[3]	transitions[0x0=>0x1]	54	1		T65	1		T213	1		T216	2
all_pins[3]	transitions[0x1=>0x0]	59	1		T66	1		T214	5		T219	3
all_pins[4]	values[0x0]	167723	1		T1	2		T2	2		T3	13
all_pins[4]	values[0x1]	76	1		T66	1		T213	2		T214	5
all_pins[4]	transitions[0x0=>0x1]	52	1		T66	1		T214	5		T219	4
all_pins[4]	transitions[0x1=>0x0]	56	1		T213	1		T216	2		T217	1
all_pins[5]	values[0x0]	167719	1		T1	2		T2	2		T3	13
all_pins[5]	values[0x1]	80	1		T213	3		T216	2		T217	1
all_pins[5]	transitions[0x0=>0x1]	59	1		T213	2		T215	1		T321	2
all_pins[5]	transitions[0x1=>0x0]	101	1		T41	1		T67	1		T68	1
all_pins[6]	values[0x0]	167677	1		T1	2		T2	2		T3	13
all_pins[6]	values[0x1]	122	1		T41	1		T67	1		T68	1
all_pins[6]	transitions[0x0=>0x1]	103	1		T41	1		T67	1		T68	1
all_pins[6]	transitions[0x1=>0x0]	46	1		T46	1		T47	1		T48	1
all_pins[7]	values[0x0]	167734	1		T1	2		T2	2		T3	13
all_pins[7]	values[0x1]	65	1		T46	1		T47	1		T48	1
all_pins[7]	transitions[0x0=>0x1]	54	1		T46	1		T47	1		T48	1
all_pins[7]	transitions[0x1=>0x0]	72	1		T3	1		T49	1		T50	1
all_pins[8]	values[0x0]	167716	1		T1	2		T2	2		T3	12
all_pins[8]	values[0x1]	83	1		T3	1		T49	1		T50	1
all_pins[8]	transitions[0x0=>0x1]	70	1		T3	1		T49	1		T50	1
all_pins[8]	transitions[0x1=>0x0]	69	1		T58	2		T59	2		T60	2
all_pins[9]	values[0x0]	167717	1		T1	2		T2	2		T3	13
all_pins[9]	values[0x1]	82	1		T58	2		T59	2		T60	2
all_pins[9]	transitions[0x0=>0x1]	58	1		T58	2		T59	2		T60	2
all_pins[9]	transitions[0x1=>0x0]	43	1		T213	1		T218	1		T214	1
all_pins[10]	values[0x0]	167732	1		T1	2		T2	2		T3	13
all_pins[10]	values[0x1]	67	1		T213	1		T218	1		T214	4
all_pins[10]	transitions[0x0=>0x1]	49	1		T213	1		T218	1		T214	4
all_pins[10]	transitions[0x1=>0x0]	100	1		T20	1		T72	1		T73	1
all_pins[11]	values[0x0]	167681	1		T1	2		T2	2		T3	13
all_pins[11]	values[0x1]	118	1		T20	1		T72	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	100	1		T20	1		T72	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	56	1		T76	1		T78	1		T79	1
all_pins[12]	values[0x0]	167725	1		T1	2		T2	2		T3	13
all_pins[12]	values[0x1]	74	1		T76	1		T78	1		T79	1
all_pins[12]	transitions[0x0=>0x1]	53	1		T76	1		T78	1		T79	1
all_pins[12]	transitions[0x1=>0x0]	90	1		T74	1		T75	1		T81	1
all_pins[13]	values[0x0]	167688	1		T1	2		T2	2		T3	13
all_pins[13]	values[0x1]	111	1		T74	1		T75	1		T81	1
all_pins[13]	transitions[0x0=>0x1]	96	1		T74	1		T75	1		T81	1
all_pins[13]	transitions[0x1=>0x0]	28	1		T216	1		T323	1		T299	1
all_pins[14]	values[0x0]	167756	1		T1	2		T2	2		T3	13
all_pins[14]	values[0x1]	43	1		T216	1		T219	1		T322	1
all_pins[14]	transitions[0x0=>0x1]	32	1		T216	1		T219	1		T322	1
all_pins[14]	transitions[0x1=>0x0]	60	1		T214	4		T215	2		T321	2
all_pins[15]	values[0x0]	167728	1		T1	2		T2	2		T3	13
all_pins[15]	values[0x1]	71	1		T214	4		T215	2		T321	2
all_pins[15]	transitions[0x0=>0x1]	48	1		T214	3		T215	2		T321	2
all_pins[15]	transitions[0x1=>0x0]	52	1		T69	4		T70	4		T71	4
all_pins[16]	values[0x0]	167724	1		T1	2		T2	2		T3	13
all_pins[16]	values[0x1]	75	1		T69	4		T70	4		T71	4
all_pins[16]	transitions[0x0=>0x1]	63	1		T69	4		T70	4		T71	4
all_pins[16]	transitions[0x1=>0x0]	45	1		T54	1		T55	1		T213	2
all_pins[17]	values[0x0]	167742	1		T1	2		T2	2		T3	13
all_pins[17]	values[0x1]	57	1		T54	1		T55	1		T213	2
all_pins[17]	transitions[0x0=>0x1]	57	1		T54	1		T55	1		T213	2