Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4369	1		T35	8		T18	1		T86	1
invalid_ep[0xd]	4552	1		T35	8		T18	2		T86	1
invalid_ep[0xe]	4423	1		T35	12		T86	2		T121	1
invalid_ep[0xf]	4533	1		T35	10		T18	1		T86	2
endpoints[0x0]	14461	1		T30	2		T32	2		T4	20
endpoints[0x1]	12597	1		T30	2		T4	20		T34	2
endpoints[0x2]	12562	1		T30	2		T4	21		T5	19
endpoints[0x3]	10874	1		T30	2		T4	2		T5	19
endpoints[0x4]	10743	1		T30	2		T4	1		T6	87
endpoints[0x5]	12088	1		T30	2		T31	1		T4	21
endpoints[0x6]	12531	1		T30	2		T4	2		T35	11
endpoints[0x7]	12442	1		T3	8		T30	2		T4	2
endpoints[0x8]	12585	1		T30	2		T4	2		T35	11
endpoints[0x9]	14962	1		T1	1		T30	2		T4	23
endpoints[0xa]	14165	1		T30	2		T4	2		T33	1
endpoints[0xb]	12324	1		T30	2		T5	19		T109	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	20806	1		T3	8		T4	14		T5	7
pkt_types[PidTypeOutToken]	73316	1		T30	12		T32	1		T4	31
pkt_types[PidTypeInToken]	59163	1		T1	1		T30	12		T31	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	935	1		T342	1		T88	9		T90	21
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1023	1		T18	2		T342	1		T88	14
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1001	1		T88	10		T376	1		T364	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1004	1		T88	9		T385	1		T430	1
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1391	1		T86	1		T164	3		T62	1
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1420	1		T35	3		T164	4		T166	3
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1413	1		T4	4		T164	2		T166	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1463	1		T5	5		T23	1		T107	4
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1482	1		T6	23		T100	1		T62	6
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1416	1		T4	5		T106	34		T305	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1365	1		T18	1		T62	6		T121	1
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1417	1		T3	8		T107	3		T166	2
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1308	1		T35	4		T62	5		T168	27
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1481	1		T4	5		T18	1		T92	2
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1392	1		T35	2		T86	1		T166	3
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1295	1		T5	2		T107	4		T86	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1511	1		T35	8		T86	1		T100	1
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1544	1		T35	8		T62	3		T123	7
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1502	1		T35	12		T86	1		T123	6
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1520	1		T35	10		T18	1		T86	1
pkt_types[PidTypeOutToken]	endpoints[0x0]	6789	1		T30	1		T32	1		T4	9
pkt_types[PidTypeOutToken]	endpoints[0x1]	5691	1		T30	1		T4	9		T34	2
pkt_types[PidTypeOutToken]	endpoints[0x2]	5551	1		T30	1		T4	5		T5	9
pkt_types[PidTypeOutToken]	endpoints[0x3]	3863	1		T30	1		T5	4		T35	5
pkt_types[PidTypeOutToken]	endpoints[0x4]	3653	1		T30	1		T6	20		T20	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	5387	1		T30	1		T4	4		T5	9
pkt_types[PidTypeOutToken]	endpoints[0x6]	5253	1		T30	1		T35	5		T7	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	5343	1		T30	1		T35	5		T19	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5654	1		T30	1		T35	1		T19	2
pkt_types[PidTypeOutToken]	endpoints[0x9]	7863	1		T30	1		T4	4		T5	9
pkt_types[PidTypeOutToken]	endpoints[0xa]	7207	1		T30	1		T33	1		T35	3
pkt_types[PidTypeOutToken]	endpoints[0xb]	4985	1		T30	1		T5	7		T109	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	955	1		T121	1		T88	11		T312	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1013	1		T86	1		T88	11		T312	1
pkt_types[PidTypeInToken]	invalid_ep[0xe]	982	1		T121	1		T88	12		T385	1
pkt_types[PidTypeInToken]	invalid_ep[0xf]	989	1		T86	1		T88	12		T90	28
pkt_types[PidTypeInToken]	endpoints[0x0]	5208	1		T30	1		T32	1		T4	10
pkt_types[PidTypeInToken]	endpoints[0x1]	4377	1		T30	1		T4	10		T35	6
pkt_types[PidTypeInToken]	endpoints[0x2]	4514	1		T30	1		T4	10		T5	10
pkt_types[PidTypeInToken]	endpoints[0x3]	4460	1		T30	1		T5	10		T35	6
pkt_types[PidTypeInToken]	endpoints[0x4]	4499	1		T30	1		T6	44		T18	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4181	1		T30	1		T31	1		T4	10
pkt_types[PidTypeInToken]	endpoints[0x6]	4831	1		T30	1		T35	6		T7	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4584	1		T30	1		T35	6		T19	2
pkt_types[PidTypeInToken]	endpoints[0x8]	4583	1		T30	1		T35	6		T19	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4541	1		T1	1		T30	1		T4	10
pkt_types[PidTypeInToken]	endpoints[0xa]	4492	1		T30	1		T35	6		T19	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4954	1		T30	1		T5	10		T35	6