Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T213	4		T218	4		T216	4
all_values[1]	281	1		T213	4		T218	4		T216	4
all_values[2]	281	1		T213	4		T218	4		T216	4
all_values[3]	281	1		T213	4		T218	4		T216	4
all_values[4]	281	1		T213	4		T218	4		T216	4
all_values[5]	281	1		T213	4		T218	4		T216	4
all_values[6]	281	1		T213	4		T218	4		T216	4
all_values[7]	281	1		T213	4		T218	4		T216	4
all_values[8]	281	1		T213	4		T218	4		T216	4
all_values[9]	281	1		T213	4		T218	4		T216	4
all_values[10]	281	1		T213	4		T218	4		T216	4
all_values[11]	281	1		T213	4		T218	4		T216	4
all_values[12]	281	1		T213	4		T218	4		T216	4
all_values[13]	281	1		T213	4		T218	4		T216	4
all_values[14]	281	1		T213	4		T218	4		T216	4
all_values[15]	281	1		T213	4		T218	4		T216	4
all_values[16]	281	1		T213	4		T218	4		T216	4
all_values[17]	281	1		T213	4		T218	4		T216	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6731	1		T213	103		T218	100		T216	90
auto[1]	2261	1		T213	25		T218	28		T216	38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6157	1		T213	84		T218	97		T216	104
auto[1]	2835	1		T213	44		T218	31		T216	24

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5333	1		T213	79		T218	95		T216	91
auto[1]	3659	1		T213	49		T218	33		T216	37

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	81	1		T213	1		T218	1		T216	3
all_values[0]	auto[0]	auto[1]	auto[0]	83	1		T213	2		T218	1		T214	1
all_values[0]	auto[1]	auto[0]	auto[1]	69	1		T213	1		T218	2		T216	1
all_values[0]	auto[1]	auto[1]	auto[1]	48	1		T214	4		T219	1		T321	1
all_values[1]	auto[0]	auto[0]	auto[0]	95	1		T213	2		T218	1		T214	2
all_values[1]	auto[0]	auto[1]	auto[0]	83	1		T213	1		T218	1		T216	2
all_values[1]	auto[1]	auto[0]	auto[1]	64	1		T213	1		T218	2		T214	1
all_values[1]	auto[1]	auto[1]	auto[1]	39	1		T216	2		T214	1		T217	1
all_values[2]	auto[0]	auto[0]	auto[0]	43	1		T214	3		T219	2		T321	1
all_values[2]	auto[0]	auto[0]	auto[1]	44	1		T218	3		T214	3		T215	1
all_values[2]	auto[0]	auto[1]	auto[0]	52	1		T216	4		T217	1		T322	2
all_values[2]	auto[0]	auto[1]	auto[1]	35	1		T213	1		T218	1		T219	1
all_values[2]	auto[1]	auto[0]	auto[1]	59	1		T213	2		T217	3		T219	1
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T213	1		T214	1		T215	1
all_values[3]	auto[0]	auto[0]	auto[0]	60	1		T216	1		T214	3		T217	3
all_values[3]	auto[0]	auto[0]	auto[1]	27	1		T218	2		T214	1		T323	3
all_values[3]	auto[0]	auto[1]	auto[0]	50	1		T214	2		T321	3		T296	1
all_values[3]	auto[0]	auto[1]	auto[1]	35	1		T213	2		T216	1		T219	1
all_values[3]	auto[1]	auto[0]	auto[1]	64	1		T213	2		T218	2		T216	1
all_values[3]	auto[1]	auto[1]	auto[1]	45	1		T216	1		T214	1		T215	1
all_values[4]	auto[0]	auto[0]	auto[0]	58	1		T218	4		T214	2		T217	1
all_values[4]	auto[0]	auto[0]	auto[1]	23	1		T213	1		T216	2		T322	2
all_values[4]	auto[0]	auto[1]	auto[0]	59	1		T216	1		T217	2		T321	1
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T213	1		T214	1		T219	1
all_values[4]	auto[1]	auto[0]	auto[1]	61	1		T213	1		T214	1		T217	1
all_values[4]	auto[1]	auto[1]	auto[1]	56	1		T213	1		T216	1		T214	3
all_values[5]	auto[0]	auto[0]	auto[0]	48	1		T218	1		T214	1		T219	1
all_values[5]	auto[0]	auto[0]	auto[1]	34	1		T217	1		T219	2		T321	3
all_values[5]	auto[0]	auto[1]	auto[0]	36	1		T218	3		T216	1		T214	4
all_values[5]	auto[0]	auto[1]	auto[1]	25	1		T213	1		T216	1		T215	1
all_values[5]	auto[1]	auto[0]	auto[1]	72	1		T213	2		T214	2		T217	1
all_values[5]	auto[1]	auto[1]	auto[1]	66	1		T213	1		T216	2		T217	2
all_values[6]	auto[0]	auto[0]	auto[0]	57	1		T218	1		T216	2		T214	1
all_values[6]	auto[0]	auto[0]	auto[1]	27	1		T213	1		T218	2		T214	1
all_values[6]	auto[0]	auto[1]	auto[0]	44	1		T214	1		T215	1		T321	2
all_values[6]	auto[0]	auto[1]	auto[1]	28	1		T216	1		T322	1		T324	1
all_values[6]	auto[1]	auto[0]	auto[1]	70	1		T213	2		T218	1		T214	2
all_values[6]	auto[1]	auto[1]	auto[1]	55	1		T213	1		T216	1		T214	2
all_values[7]	auto[0]	auto[0]	auto[0]	92	1		T213	3		T218	2		T216	2
all_values[7]	auto[0]	auto[1]	auto[0]	67	1		T213	1		T218	1		T216	1
all_values[7]	auto[1]	auto[0]	auto[1]	68	1		T218	1		T214	3		T217	1
all_values[7]	auto[1]	auto[1]	auto[1]	54	1		T216	1		T214	1		T217	2
all_values[8]	auto[0]	auto[0]	auto[0]	98	1		T213	3		T216	3		T214	2
all_values[8]	auto[0]	auto[1]	auto[0]	77	1		T218	3		T214	2		T217	3
all_values[8]	auto[1]	auto[0]	auto[1]	66	1		T213	1		T218	1		T216	1
all_values[8]	auto[1]	auto[1]	auto[1]	40	1		T215	1		T321	2		T323	2
all_values[9]	auto[0]	auto[0]	auto[0]	49	1		T213	1		T218	1		T217	1
all_values[9]	auto[0]	auto[0]	auto[1]	38	1		T213	1		T216	1		T214	2
all_values[9]	auto[0]	auto[1]	auto[0]	51	1		T213	1		T218	3		T216	2
all_values[9]	auto[0]	auto[1]	auto[1]	29	1		T214	1		T219	1		T296	2
all_values[9]	auto[1]	auto[0]	auto[1]	60	1		T213	1		T216	1		T214	2
all_values[9]	auto[1]	auto[1]	auto[1]	54	1		T214	2		T219	1		T296	2
all_values[10]	auto[0]	auto[0]	auto[0]	63	1		T216	4		T214	1		T217	2
all_values[10]	auto[0]	auto[0]	auto[1]	28	1		T213	1		T218	1		T298	2
all_values[10]	auto[0]	auto[1]	auto[0]	54	1		T214	1		T217	2		T215	2
all_values[10]	auto[0]	auto[1]	auto[1]	23	1		T213	1		T218	1		T214	1
all_values[10]	auto[1]	auto[0]	auto[1]	53	1		T213	1		T218	1		T214	2
all_values[10]	auto[1]	auto[1]	auto[1]	60	1		T213	1		T218	1		T214	2
all_values[11]	auto[0]	auto[0]	auto[0]	60	1		T213	1		T218	1		T216	2
all_values[11]	auto[0]	auto[0]	auto[1]	33	1		T213	1		T214	2		T215	2
all_values[11]	auto[0]	auto[1]	auto[0]	44	1		T213	1		T218	3		T216	2
all_values[11]	auto[0]	auto[1]	auto[1]	25	1		T217	1		T321	1		T324	1
all_values[11]	auto[1]	auto[0]	auto[1]	69	1		T214	2		T217	1		T219	1
all_values[11]	auto[1]	auto[1]	auto[1]	50	1		T213	1		T214	1		T217	1
all_values[12]	auto[0]	auto[0]	auto[0]	51	1		T218	1		T216	2		T217	2
all_values[12]	auto[0]	auto[0]	auto[1]	38	1		T213	1		T214	2		T215	1
all_values[12]	auto[0]	auto[1]	auto[0]	41	1		T218	1		T216	2		T214	3
all_values[12]	auto[0]	auto[1]	auto[1]	29	1		T219	1		T296	1		T322	1
all_values[12]	auto[1]	auto[0]	auto[1]	72	1		T213	2		T214	1		T217	1
all_values[12]	auto[1]	auto[1]	auto[1]	50	1		T213	1		T218	2		T214	1
all_values[13]	auto[0]	auto[0]	auto[0]	72	1		T216	1		T214	3		T217	2
all_values[13]	auto[0]	auto[0]	auto[1]	35	1		T213	1		T215	1		T321	1
all_values[13]	auto[0]	auto[1]	auto[0]	40	1		T213	2		T218	1		T216	2
all_values[13]	auto[0]	auto[1]	auto[1]	27	1		T214	1		T217	1		T219	1
all_values[13]	auto[1]	auto[0]	auto[1]	68	1		T213	1		T218	3		T216	1
all_values[13]	auto[1]	auto[1]	auto[1]	39	1		T214	1		T219	1		T215	1
all_values[14]	auto[0]	auto[0]	auto[0]	79	1		T213	3		T218	2		T214	1
all_values[14]	auto[0]	auto[0]	auto[1]	24	1		T214	1		T217	1		T321	1
all_values[14]	auto[0]	auto[1]	auto[0]	59	1		T213	1		T218	1		T216	2
all_values[14]	auto[0]	auto[1]	auto[1]	21	1		T323	1		T299	3		T325	1
all_values[14]	auto[1]	auto[0]	auto[1]	57	1		T218	1		T214	3		T217	1
all_values[14]	auto[1]	auto[1]	auto[1]	41	1		T216	2		T219	1		T215	1
all_values[15]	auto[0]	auto[0]	auto[0]	53	1		T213	3		T218	1		T216	2
all_values[15]	auto[0]	auto[0]	auto[1]	36	1		T218	2		T217	1		T219	1
all_values[15]	auto[0]	auto[1]	auto[0]	44	1		T216	2		T322	1		T324	1
all_values[15]	auto[0]	auto[1]	auto[1]	36	1		T214	2		T215	1		T321	2
all_values[15]	auto[1]	auto[0]	auto[1]	62	1		T218	1		T214	1		T217	3
all_values[15]	auto[1]	auto[1]	auto[1]	50	1		T213	1		T214	2		T321	1
all_values[16]	auto[0]	auto[0]	auto[0]	70	1		T213	1		T218	1		T214	1
all_values[16]	auto[0]	auto[0]	auto[1]	24	1		T213	1		T216	1		T214	2
all_values[16]	auto[0]	auto[1]	auto[0]	42	1		T218	3		T216	2		T296	1
all_values[16]	auto[0]	auto[1]	auto[1]	23	1		T321	1		T322	2		T297	1
all_values[16]	auto[1]	auto[0]	auto[1]	76	1		T213	2		T216	1		T214	3
all_values[16]	auto[1]	auto[1]	auto[1]	46	1		T214	1		T219	1		T215	2
all_values[17]	auto[0]	auto[0]	auto[0]	87	1		T218	2		T216	2		T214	3
all_values[17]	auto[0]	auto[1]	auto[0]	81	1		T213	1		T218	1		T216	1
all_values[17]	auto[1]	auto[0]	auto[1]	60	1		T213	2		T214	1		T215	2
all_values[17]	auto[1]	auto[1]	auto[1]	53	1		T213	1		T218	1		T216	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal