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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.61 97.96 93.90 97.44 81.25 96.42 98.17 90.14


Total test records in report: 3213
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T3073 /workspace/coverage/default/1.usbdev_freq_phase.2466122116 Aug 02 05:26:42 PM PDT 24 Aug 02 05:29:31 PM PDT 24 104135112145 ps
T3074 /workspace/coverage/default/14.usbdev_pkt_sent.1757047005 Aug 02 05:30:04 PM PDT 24 Aug 02 05:30:05 PM PDT 24 268717786 ps
T3075 /workspace/coverage/default/2.usbdev_device_address.6714385 Aug 02 05:27:06 PM PDT 24 Aug 02 05:28:07 PM PDT 24 43756144191 ps
T3076 /workspace/coverage/default/41.usbdev_stall_trans.3596890774 Aug 02 05:33:55 PM PDT 24 Aug 02 05:33:56 PM PDT 24 182696543 ps
T3077 /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2754572201 Aug 02 05:26:16 PM PDT 24 Aug 02 05:26:17 PM PDT 24 226799667 ps
T3078 /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.861284656 Aug 02 05:32:42 PM PDT 24 Aug 02 05:33:53 PM PDT 24 2531406408 ps
T3079 /workspace/coverage/default/49.usbdev_link_resume.3623299316 Aug 02 05:34:58 PM PDT 24 Aug 02 05:35:44 PM PDT 24 30663369616 ps
T3080 /workspace/coverage/default/18.usbdev_in_trans.2938655414 Aug 02 05:30:31 PM PDT 24 Aug 02 05:30:32 PM PDT 24 198157606 ps
T3081 /workspace/coverage/default/4.usbdev_in_stall.3374854563 Aug 02 05:27:51 PM PDT 24 Aug 02 05:27:52 PM PDT 24 144398265 ps
T3082 /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1574485561 Aug 02 05:27:07 PM PDT 24 Aug 02 05:27:39 PM PDT 24 3233934788 ps
T3083 /workspace/coverage/default/26.usbdev_max_length_in_transaction.1074843309 Aug 02 05:31:59 PM PDT 24 Aug 02 05:32:00 PM PDT 24 294552100 ps
T3084 /workspace/coverage/default/96.usbdev_endpoint_types.1287261369 Aug 02 05:35:01 PM PDT 24 Aug 02 05:35:02 PM PDT 24 260147212 ps
T3085 /workspace/coverage/default/24.usbdev_smoke.3890129895 Aug 02 05:31:41 PM PDT 24 Aug 02 05:31:42 PM PDT 24 222124307 ps
T3086 /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2903584817 Aug 02 05:33:53 PM PDT 24 Aug 02 05:34:14 PM PDT 24 2727895653 ps
T3087 /workspace/coverage/default/42.usbdev_aon_wake_resume.1589183060 Aug 02 05:33:47 PM PDT 24 Aug 02 05:34:20 PM PDT 24 24629768221 ps
T3088 /workspace/coverage/default/22.usbdev_streaming_out.1700508722 Aug 02 05:31:20 PM PDT 24 Aug 02 05:31:38 PM PDT 24 2602165314 ps
T3089 /workspace/coverage/default/2.usbdev_setup_stage.3722455927 Aug 02 05:27:25 PM PDT 24 Aug 02 05:27:26 PM PDT 24 161991945 ps
T3090 /workspace/coverage/default/38.usbdev_in_trans.560898884 Aug 02 05:33:19 PM PDT 24 Aug 02 05:33:20 PM PDT 24 234743882 ps
T3091 /workspace/coverage/default/22.usbdev_rx_crc_err.1418082861 Aug 02 05:31:15 PM PDT 24 Aug 02 05:31:16 PM PDT 24 184843891 ps
T3092 /workspace/coverage/default/22.usbdev_max_length_out_transaction.465902358 Aug 02 05:31:06 PM PDT 24 Aug 02 05:31:07 PM PDT 24 225179895 ps
T3093 /workspace/coverage/default/19.usbdev_link_suspend.1996313720 Aug 02 05:30:41 PM PDT 24 Aug 02 05:30:49 PM PDT 24 5432601003 ps
T3094 /workspace/coverage/default/44.usbdev_data_toggle_restore.1851551203 Aug 02 05:34:00 PM PDT 24 Aug 02 05:34:03 PM PDT 24 799167527 ps
T3095 /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2687841455 Aug 02 05:33:28 PM PDT 24 Aug 02 05:33:29 PM PDT 24 146009020 ps
T3096 /workspace/coverage/default/11.usbdev_max_usb_traffic.1879218108 Aug 02 05:29:26 PM PDT 24 Aug 02 05:30:41 PM PDT 24 2505633066 ps
T3097 /workspace/coverage/default/49.usbdev_endpoint_access.3081458099 Aug 02 05:34:57 PM PDT 24 Aug 02 05:34:59 PM PDT 24 877564004 ps
T3098 /workspace/coverage/default/1.usbdev_data_toggle_restore.1902194431 Aug 02 05:26:36 PM PDT 24 Aug 02 05:26:39 PM PDT 24 891375470 ps
T3099 /workspace/coverage/default/46.usbdev_random_length_in_transaction.3940341556 Aug 02 05:34:33 PM PDT 24 Aug 02 05:34:34 PM PDT 24 218839288 ps
T3100 /workspace/coverage/default/37.usbdev_nak_trans.502009989 Aug 02 05:33:12 PM PDT 24 Aug 02 05:33:13 PM PDT 24 200990326 ps
T3101 /workspace/coverage/default/15.usbdev_disable_endpoint.3799624510 Aug 02 05:30:05 PM PDT 24 Aug 02 05:30:07 PM PDT 24 752995977 ps
T3102 /workspace/coverage/default/24.usbdev_phy_pins_sense.2379460562 Aug 02 05:31:28 PM PDT 24 Aug 02 05:31:29 PM PDT 24 44960794 ps
T3103 /workspace/coverage/default/13.usbdev_pending_in_trans.2520704074 Aug 02 05:29:47 PM PDT 24 Aug 02 05:29:48 PM PDT 24 159858480 ps
T3104 /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.3362096593 Aug 02 05:28:17 PM PDT 24 Aug 02 05:28:39 PM PDT 24 977790920 ps
T412 /workspace/coverage/default/179.usbdev_endpoint_types.1162699285 Aug 02 05:35:16 PM PDT 24 Aug 02 05:35:17 PM PDT 24 386176087 ps
T3105 /workspace/coverage/default/26.usbdev_rx_crc_err.2739412019 Aug 02 05:31:39 PM PDT 24 Aug 02 05:31:40 PM PDT 24 201117648 ps
T3106 /workspace/coverage/default/25.usbdev_link_in_err.1749513365 Aug 02 05:31:39 PM PDT 24 Aug 02 05:31:40 PM PDT 24 228618862 ps
T3107 /workspace/coverage/default/14.usbdev_min_length_in_transaction.2845690107 Aug 02 05:29:52 PM PDT 24 Aug 02 05:29:53 PM PDT 24 153282350 ps
T3108 /workspace/coverage/default/26.usbdev_link_in_err.1813331142 Aug 02 05:31:39 PM PDT 24 Aug 02 05:31:40 PM PDT 24 233279038 ps
T3109 /workspace/coverage/default/5.usbdev_pkt_received.3459373084 Aug 02 05:28:16 PM PDT 24 Aug 02 05:28:17 PM PDT 24 172724332 ps
T209 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3380901021 Aug 02 05:00:54 PM PDT 24 Aug 02 05:00:55 PM PDT 24 173013353 ps
T233 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1409337501 Aug 02 05:00:48 PM PDT 24 Aug 02 05:00:49 PM PDT 24 84299136 ps
T206 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3511601099 Aug 02 05:00:55 PM PDT 24 Aug 02 05:00:57 PM PDT 24 258358313 ps
T213 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2793233108 Aug 02 05:01:04 PM PDT 24 Aug 02 05:01:05 PM PDT 24 70141970 ps
T207 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1692126208 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:08 PM PDT 24 172870812 ps
T208 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3474413955 Aug 02 05:00:58 PM PDT 24 Aug 02 05:01:00 PM PDT 24 49466582 ps
T268 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3172903684 Aug 02 05:01:04 PM PDT 24 Aug 02 05:01:11 PM PDT 24 566864946 ps
T269 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3937928545 Aug 02 05:00:46 PM PDT 24 Aug 02 05:00:49 PM PDT 24 74731709 ps
T218 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4292699029 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:08 PM PDT 24 31766355 ps
T216 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2774232143 Aug 02 05:01:01 PM PDT 24 Aug 02 05:01:02 PM PDT 24 69699142 ps
T230 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1043162249 Aug 02 05:00:54 PM PDT 24 Aug 02 05:00:56 PM PDT 24 108349072 ps
T231 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3027146747 Aug 02 05:01:01 PM PDT 24 Aug 02 05:01:03 PM PDT 24 117568525 ps
T232 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2524866268 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:59 PM PDT 24 782543837 ps
T281 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3216979659 Aug 02 05:01:01 PM PDT 24 Aug 02 05:01:03 PM PDT 24 81279321 ps
T214 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1145477163 Aug 02 05:00:43 PM PDT 24 Aug 02 05:00:44 PM PDT 24 38759231 ps
T217 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2665943206 Aug 02 05:00:57 PM PDT 24 Aug 02 05:00:58 PM PDT 24 30734165 ps
T235 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2554359446 Aug 02 05:00:41 PM PDT 24 Aug 02 05:00:43 PM PDT 24 331391431 ps
T219 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4069964296 Aug 02 05:01:09 PM PDT 24 Aug 02 05:01:10 PM PDT 24 105296829 ps
T215 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.550143707 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:57 PM PDT 24 71301363 ps
T236 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4075810208 Aug 02 05:00:57 PM PDT 24 Aug 02 05:00:59 PM PDT 24 77731893 ps
T270 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3323860265 Aug 02 05:01:02 PM PDT 24 Aug 02 05:01:03 PM PDT 24 79821118 ps
T251 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.313179986 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:09 PM PDT 24 106497832 ps
T321 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2397366628 Aug 02 05:01:02 PM PDT 24 Aug 02 05:01:03 PM PDT 24 55158938 ps
T271 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3710107328 Aug 02 05:01:00 PM PDT 24 Aug 02 05:01:01 PM PDT 24 316526234 ps
T296 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.560557850 Aug 02 05:00:57 PM PDT 24 Aug 02 05:00:58 PM PDT 24 62134731 ps
T282 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.923934554 Aug 02 05:00:52 PM PDT 24 Aug 02 05:00:54 PM PDT 24 328534707 ps
T237 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1951339596 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:11 PM PDT 24 649673496 ps
T241 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2691063066 Aug 02 05:00:57 PM PDT 24 Aug 02 05:00:59 PM PDT 24 86679152 ps
T322 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.159139851 Aug 02 05:01:10 PM PDT 24 Aug 02 05:01:11 PM PDT 24 106872630 ps
T283 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1880169016 Aug 02 05:00:54 PM PDT 24 Aug 02 05:00:56 PM PDT 24 192214343 ps
T284 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1811721335 Aug 02 05:00:57 PM PDT 24 Aug 02 05:00:58 PM PDT 24 91011996 ps
T272 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2526868375 Aug 02 05:00:51 PM PDT 24 Aug 02 05:00:53 PM PDT 24 93074143 ps
T324 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2930667614 Aug 02 05:01:03 PM PDT 24 Aug 02 05:01:03 PM PDT 24 49311237 ps
T285 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3843816787 Aug 02 05:01:04 PM PDT 24 Aug 02 05:01:06 PM PDT 24 336977232 ps
T245 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.687714934 Aug 02 05:00:58 PM PDT 24 Aug 02 05:01:00 PM PDT 24 217069896 ps
T252 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2605519151 Aug 02 05:00:55 PM PDT 24 Aug 02 05:00:56 PM PDT 24 105692692 ps
T286 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3006277768 Aug 02 05:01:00 PM PDT 24 Aug 02 05:01:01 PM PDT 24 101785985 ps
T3110 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1976137865 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:58 PM PDT 24 122051939 ps
T273 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4092268593 Aug 02 05:00:42 PM PDT 24 Aug 02 05:00:50 PM PDT 24 654417732 ps
T3111 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2699230930 Aug 02 05:00:42 PM PDT 24 Aug 02 05:00:45 PM PDT 24 285153741 ps
T274 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.526094654 Aug 02 05:00:43 PM PDT 24 Aug 02 05:00:44 PM PDT 24 163616136 ps
T242 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1248340891 Aug 02 05:00:58 PM PDT 24 Aug 02 05:01:00 PM PDT 24 174971210 ps
T323 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3902156664 Aug 02 05:01:00 PM PDT 24 Aug 02 05:01:01 PM PDT 24 45453444 ps
T297 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.628695644 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:08 PM PDT 24 41838836 ps
T298 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2994971112 Aug 02 05:01:02 PM PDT 24 Aug 02 05:01:03 PM PDT 24 57932994 ps
T243 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.105678264 Aug 02 05:00:55 PM PDT 24 Aug 02 05:00:57 PM PDT 24 98532629 ps
T329 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3040771280 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:11 PM PDT 24 444115395 ps
T299 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3196107769 Aug 02 05:01:05 PM PDT 24 Aug 02 05:01:06 PM PDT 24 49923878 ps
T3112 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4283371287 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:07 PM PDT 24 47155671 ps
T3113 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2084787910 Aug 02 05:01:04 PM PDT 24 Aug 02 05:01:04 PM PDT 24 41342580 ps
T3114 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2439511086 Aug 02 05:01:05 PM PDT 24 Aug 02 05:01:06 PM PDT 24 80152774 ps
T3115 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.55895801 Aug 02 05:01:08 PM PDT 24 Aug 02 05:01:09 PM PDT 24 70784549 ps
T325 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.506059377 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:07 PM PDT 24 71054230 ps
T3116 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3153737292 Aug 02 05:00:56 PM PDT 24 Aug 02 05:01:00 PM PDT 24 168939077 ps
T337 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2596037858 Aug 02 05:00:49 PM PDT 24 Aug 02 05:00:54 PM PDT 24 552136168 ps
T3117 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4133349646 Aug 02 05:00:46 PM PDT 24 Aug 02 05:00:49 PM PDT 24 132873443 ps
T330 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2958964050 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:12 PM PDT 24 526937380 ps
T275 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2995881290 Aug 02 05:00:45 PM PDT 24 Aug 02 05:00:47 PM PDT 24 196179093 ps
T3118 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2486530769 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:57 PM PDT 24 71243513 ps
T276 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2181107911 Aug 02 05:00:55 PM PDT 24 Aug 02 05:00:56 PM PDT 24 121955563 ps
T277 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.900373992 Aug 02 05:00:52 PM PDT 24 Aug 02 05:00:54 PM PDT 24 119582771 ps
T244 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.621346197 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:59 PM PDT 24 206928262 ps
T278 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1302880969 Aug 02 05:00:42 PM PDT 24 Aug 02 05:00:44 PM PDT 24 104207309 ps
T3119 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.857887117 Aug 02 05:01:09 PM PDT 24 Aug 02 05:01:09 PM PDT 24 70895145 ps
T3120 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1825102009 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:08 PM PDT 24 61837227 ps
T3121 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.143526812 Aug 02 05:01:05 PM PDT 24 Aug 02 05:01:06 PM PDT 24 54473866 ps
T3122 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.211286125 Aug 02 05:00:58 PM PDT 24 Aug 02 05:00:59 PM PDT 24 65467291 ps
T293 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3394952234 Aug 02 05:00:52 PM PDT 24 Aug 02 05:00:54 PM PDT 24 201467024 ps
T279 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2455761275 Aug 02 05:00:44 PM PDT 24 Aug 02 05:00:46 PM PDT 24 226509030 ps
T3123 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.761386715 Aug 02 05:00:38 PM PDT 24 Aug 02 05:00:42 PM PDT 24 162508372 ps
T3124 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3506112412 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:08 PM PDT 24 123058723 ps
T3125 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4197063696 Aug 02 05:01:04 PM PDT 24 Aug 02 05:01:05 PM PDT 24 37833385 ps
T294 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1004905861 Aug 02 05:00:55 PM PDT 24 Aug 02 05:00:57 PM PDT 24 204960422 ps
T280 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4020117631 Aug 02 05:01:00 PM PDT 24 Aug 02 05:01:02 PM PDT 24 45793263 ps
T3126 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4166656122 Aug 02 05:00:51 PM PDT 24 Aug 02 05:00:54 PM PDT 24 107768904 ps
T3127 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.733390151 Aug 02 05:01:04 PM PDT 24 Aug 02 05:01:06 PM PDT 24 55106166 ps
T3128 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.408834330 Aug 02 05:00:51 PM PDT 24 Aug 02 05:00:52 PM PDT 24 45589742 ps
T3129 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2861459453 Aug 02 05:00:52 PM PDT 24 Aug 02 05:00:53 PM PDT 24 61360192 ps
T3130 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1128842445 Aug 02 05:00:48 PM PDT 24 Aug 02 05:00:49 PM PDT 24 48820438 ps
T3131 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2777495377 Aug 02 05:00:49 PM PDT 24 Aug 02 05:00:52 PM PDT 24 164097987 ps
T295 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3493291017 Aug 02 05:01:02 PM PDT 24 Aug 02 05:01:03 PM PDT 24 147025535 ps
T3132 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1039793482 Aug 02 05:00:51 PM PDT 24 Aug 02 05:00:52 PM PDT 24 47522326 ps
T3133 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.962624289 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:57 PM PDT 24 106138037 ps
T3134 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1131480285 Aug 02 05:00:58 PM PDT 24 Aug 02 05:01:00 PM PDT 24 262124046 ps
T3135 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3553319154 Aug 02 05:00:40 PM PDT 24 Aug 02 05:00:41 PM PDT 24 46077312 ps
T3136 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3642792574 Aug 02 05:01:00 PM PDT 24 Aug 02 05:01:01 PM PDT 24 82583981 ps
T3137 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3977276785 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:08 PM PDT 24 181167885 ps
T3138 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1459761646 Aug 02 05:00:55 PM PDT 24 Aug 02 05:00:56 PM PDT 24 50485665 ps
T3139 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3593986466 Aug 02 05:01:10 PM PDT 24 Aug 02 05:01:11 PM PDT 24 76251887 ps
T300 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2531726960 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:57 PM PDT 24 138033103 ps
T3140 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2123665689 Aug 02 05:01:08 PM PDT 24 Aug 02 05:01:10 PM PDT 24 62637118 ps
T246 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3629054136 Aug 02 05:00:58 PM PDT 24 Aug 02 05:01:02 PM PDT 24 288764855 ps
T3141 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3695831054 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:07 PM PDT 24 42927253 ps
T3142 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.722521786 Aug 02 05:01:08 PM PDT 24 Aug 02 05:01:09 PM PDT 24 33773103 ps
T3143 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.285029093 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:07 PM PDT 24 40841808 ps
T335 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.756383182 Aug 02 05:00:58 PM PDT 24 Aug 02 05:01:01 PM PDT 24 341700793 ps
T3144 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3738765841 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:08 PM PDT 24 114156068 ps
T3145 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1650448780 Aug 02 05:01:05 PM PDT 24 Aug 02 05:01:06 PM PDT 24 41425363 ps
T3146 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3446233155 Aug 02 05:00:52 PM PDT 24 Aug 02 05:00:54 PM PDT 24 98780060 ps
T3147 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.873324551 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:57 PM PDT 24 51838304 ps
T247 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3044497336 Aug 02 05:00:49 PM PDT 24 Aug 02 05:00:52 PM PDT 24 160255908 ps
T3148 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2514735584 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:08 PM PDT 24 34674567 ps
T249 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1753098318 Aug 02 05:00:54 PM PDT 24 Aug 02 05:00:56 PM PDT 24 188280615 ps
T3149 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.823004378 Aug 02 05:00:49 PM PDT 24 Aug 02 05:00:50 PM PDT 24 112281613 ps
T3150 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3605079101 Aug 02 05:00:53 PM PDT 24 Aug 02 05:00:55 PM PDT 24 127624954 ps
T3151 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3179843577 Aug 02 05:01:11 PM PDT 24 Aug 02 05:01:12 PM PDT 24 48318353 ps
T333 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3349325828 Aug 02 05:00:49 PM PDT 24 Aug 02 05:00:54 PM PDT 24 1080630071 ps
T3152 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1503677103 Aug 02 05:01:05 PM PDT 24 Aug 02 05:01:06 PM PDT 24 86979416 ps
T3153 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1135281578 Aug 02 05:00:50 PM PDT 24 Aug 02 05:00:51 PM PDT 24 58232085 ps
T338 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.916451367 Aug 02 05:01:01 PM PDT 24 Aug 02 05:01:07 PM PDT 24 1931376339 ps
T248 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2758540991 Aug 02 05:00:45 PM PDT 24 Aug 02 05:00:49 PM PDT 24 200758499 ps
T3154 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3530419836 Aug 02 05:00:49 PM PDT 24 Aug 02 05:00:50 PM PDT 24 48047786 ps
T3155 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.102154561 Aug 02 05:00:45 PM PDT 24 Aug 02 05:00:47 PM PDT 24 104987412 ps
T3156 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2162875457 Aug 02 05:00:41 PM PDT 24 Aug 02 05:00:43 PM PDT 24 108727852 ps
T331 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4222739256 Aug 02 05:00:58 PM PDT 24 Aug 02 05:01:03 PM PDT 24 837899671 ps
T3157 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1127584292 Aug 02 05:00:59 PM PDT 24 Aug 02 05:01:00 PM PDT 24 63740696 ps
T3158 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3865056312 Aug 02 05:01:09 PM PDT 24 Aug 02 05:01:10 PM PDT 24 89067665 ps
T3159 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3092420100 Aug 02 05:01:01 PM PDT 24 Aug 02 05:01:03 PM PDT 24 210827389 ps
T3160 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3722651236 Aug 02 05:00:55 PM PDT 24 Aug 02 05:00:58 PM PDT 24 502470499 ps
T3161 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1979119650 Aug 02 05:00:51 PM PDT 24 Aug 02 05:00:53 PM PDT 24 90255229 ps
T3162 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2789783817 Aug 02 05:01:08 PM PDT 24 Aug 02 05:01:11 PM PDT 24 131754668 ps
T3163 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.573026238 Aug 02 05:01:01 PM PDT 24 Aug 02 05:01:05 PM PDT 24 352568604 ps
T3164 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1609284104 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:58 PM PDT 24 196024714 ps
T3165 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3293558475 Aug 02 05:00:53 PM PDT 24 Aug 02 05:00:55 PM PDT 24 85629355 ps
T3166 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4013271124 Aug 02 05:00:41 PM PDT 24 Aug 02 05:00:44 PM PDT 24 380600954 ps
T3167 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2486638948 Aug 02 05:00:42 PM PDT 24 Aug 02 05:00:44 PM PDT 24 185110421 ps
T3168 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.592420271 Aug 02 05:00:52 PM PDT 24 Aug 02 05:00:55 PM PDT 24 416485235 ps
T3169 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3590780505 Aug 02 05:00:55 PM PDT 24 Aug 02 05:00:59 PM PDT 24 504065378 ps
T3170 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4098873166 Aug 02 05:01:05 PM PDT 24 Aug 02 05:01:08 PM PDT 24 267201573 ps
T3171 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2238463210 Aug 02 05:00:58 PM PDT 24 Aug 02 05:01:00 PM PDT 24 358875768 ps
T3172 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.235216068 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:08 PM PDT 24 261184845 ps
T334 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2426041168 Aug 02 05:00:59 PM PDT 24 Aug 02 05:01:04 PM PDT 24 917001003 ps
T3173 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1196973079 Aug 02 05:01:04 PM PDT 24 Aug 02 05:01:06 PM PDT 24 111727047 ps
T3174 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.617352704 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:06 PM PDT 24 47232998 ps
T3175 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2601927097 Aug 02 05:00:54 PM PDT 24 Aug 02 05:00:55 PM PDT 24 53283260 ps
T3176 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3430827388 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:13 PM PDT 24 34539796 ps
T3177 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.227039705 Aug 02 05:00:49 PM PDT 24 Aug 02 05:00:51 PM PDT 24 146787873 ps
T3178 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3645019939 Aug 02 05:00:53 PM PDT 24 Aug 02 05:00:54 PM PDT 24 87921228 ps
T3179 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3543121333 Aug 02 05:01:07 PM PDT 24 Aug 02 05:01:09 PM PDT 24 77837994 ps
T3180 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.622468446 Aug 02 05:00:51 PM PDT 24 Aug 02 05:00:53 PM PDT 24 363794805 ps
T3181 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.213890887 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:07 PM PDT 24 51890193 ps
T3182 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1742254696 Aug 02 05:00:40 PM PDT 24 Aug 02 05:00:43 PM PDT 24 236961976 ps
T3183 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2224382688 Aug 02 05:00:42 PM PDT 24 Aug 02 05:00:51 PM PDT 24 1523881986 ps
T3184 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3300293694 Aug 02 05:00:57 PM PDT 24 Aug 02 05:00:58 PM PDT 24 210110452 ps
T3185 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2673104693 Aug 02 05:00:54 PM PDT 24 Aug 02 05:00:57 PM PDT 24 109079998 ps
T3186 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1504447957 Aug 02 05:00:44 PM PDT 24 Aug 02 05:00:54 PM PDT 24 1991854477 ps
T3187 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3459874059 Aug 02 05:00:52 PM PDT 24 Aug 02 05:00:53 PM PDT 24 61073993 ps
T3188 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.788609829 Aug 02 05:00:52 PM PDT 24 Aug 02 05:01:00 PM PDT 24 528754295 ps
T3189 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3106214278 Aug 02 05:00:56 PM PDT 24 Aug 02 05:00:58 PM PDT 24 216972022 ps
T3190 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3891304534 Aug 02 05:00:51 PM PDT 24 Aug 02 05:00:52 PM PDT 24 48843731 ps
T3191 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1577494024 Aug 02 05:01:02 PM PDT 24 Aug 02 05:01:03 PM PDT 24 37616117 ps
T3192 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3400074682 Aug 02 05:00:58 PM PDT 24 Aug 02 05:00:59 PM PDT 24 112692899 ps
T3193 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2196119476 Aug 02 05:00:53 PM PDT 24 Aug 02 05:00:55 PM PDT 24 84044883 ps
T332 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1591682929 Aug 02 05:00:57 PM PDT 24 Aug 02 05:01:02 PM PDT 24 1167965170 ps
T3194 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1672813501 Aug 02 05:00:51 PM PDT 24 Aug 02 05:00:54 PM PDT 24 695221375 ps
T3195 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1139172646 Aug 02 05:00:54 PM PDT 24 Aug 02 05:00:55 PM PDT 24 86603262 ps
T336 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2125712296 Aug 02 05:00:57 PM PDT 24 Aug 02 05:01:00 PM PDT 24 463116455 ps
T3196 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3457363677 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:07 PM PDT 24 41347249 ps
T3197 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.865119901 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:08 PM PDT 24 180305413 ps
T3198 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3276249850 Aug 02 05:00:57 PM PDT 24 Aug 02 05:00:59 PM PDT 24 65121245 ps
T3199 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.957751267 Aug 02 05:00:49 PM PDT 24 Aug 02 05:00:50 PM PDT 24 64437296 ps
T3200 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2437490918 Aug 02 05:01:08 PM PDT 24 Aug 02 05:01:10 PM PDT 24 85556306 ps
T3201 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3007740325 Aug 02 05:00:52 PM PDT 24 Aug 02 05:00:53 PM PDT 24 63841057 ps
T3202 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.201467136 Aug 02 05:00:50 PM PDT 24 Aug 02 05:00:51 PM PDT 24 128164252 ps
T3203 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1817982438 Aug 02 05:00:59 PM PDT 24 Aug 02 05:01:01 PM PDT 24 145907465 ps
T3204 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4213940804 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:07 PM PDT 24 81675327 ps
T3205 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2505289370 Aug 02 05:00:57 PM PDT 24 Aug 02 05:00:58 PM PDT 24 52371020 ps
T3206 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1709863411 Aug 02 05:00:54 PM PDT 24 Aug 02 05:00:57 PM PDT 24 859797139 ps
T3207 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.982689669 Aug 02 05:01:05 PM PDT 24 Aug 02 05:01:06 PM PDT 24 59165934 ps
T3208 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1122349851 Aug 02 05:00:57 PM PDT 24 Aug 02 05:00:58 PM PDT 24 43083350 ps
T3209 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2474837053 Aug 02 05:00:59 PM PDT 24 Aug 02 05:01:01 PM PDT 24 96461860 ps
T3210 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1060961909 Aug 02 05:00:50 PM PDT 24 Aug 02 05:00:53 PM PDT 24 142370920 ps
T3211 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2399486110 Aug 02 05:00:55 PM PDT 24 Aug 02 05:00:57 PM PDT 24 163365098 ps
T3212 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3611132816 Aug 02 05:01:06 PM PDT 24 Aug 02 05:01:07 PM PDT 24 57858615 ps
T3213 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3340936024 Aug 02 05:00:53 PM PDT 24 Aug 02 05:00:55 PM PDT 24 55842365 ps


Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.4200170753
Short name T6
Test name
Test status
Simulation time 2207005441 ps
CPU time 60.9 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:30:34 PM PDT 24
Peak memory 215760 kb
Host smart-ff2da6bb-3d36-4246-93c6-7e01c69e9191
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4200170753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.4200170753
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/21.usbdev_endpoint_access.4072673535
Short name T30
Test name
Test status
Simulation time 800406090 ps
CPU time 2.22 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:57 PM PDT 24
Peak memory 207596 kb
Host smart-4e82b782-e538-49d4-aaf4-1c996b5ed849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40726
73535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.4072673535
Directory /workspace/21.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.2446224243
Short name T8
Test name
Test status
Simulation time 11208075417 ps
CPU time 14.27 seconds
Started Aug 02 05:33:48 PM PDT 24
Finished Aug 02 05:34:03 PM PDT 24
Peak memory 207636 kb
Host smart-c5f852b1-dde0-42c6-86c5-80548e424521
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446224243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_disconnect.2446224243
Directory /workspace/43.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2397366628
Short name T321
Test name
Test status
Simulation time 55158938 ps
CPU time 0.73 seconds
Started Aug 02 05:01:02 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 206868 kb
Host smart-c0e1e90a-f9e8-4e40-8762-112ff2f8526d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2397366628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2397366628
Directory /workspace/38.usbdev_intr_test/latest


Test location /workspace/coverage/default/84.usbdev_endpoint_types.1893997294
Short name T86
Test name
Test status
Simulation time 580176652 ps
CPU time 1.57 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207304 kb
Host smart-17c6c01c-b912-4c5a-941e-aa757a58d10c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1893997294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.usbdev_endpoint_types.1893997294
Directory /workspace/84.usbdev_endpoint_types/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1692126208
Short name T207
Test name
Test status
Simulation time 172870812 ps
CPU time 1.94 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 215408 kb
Host smart-6ea134ed-7a38-4c5f-a0f0-daa901e3029c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692126208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1692126208
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.2698624173
Short name T125
Test name
Test status
Simulation time 2719026375 ps
CPU time 27.63 seconds
Started Aug 02 05:28:43 PM PDT 24
Finished Aug 02 05:29:11 PM PDT 24
Peak memory 224004 kb
Host smart-84c1b026-dd4f-4f2a-8592-eb7f99428f4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2698624173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.2698624173
Directory /workspace/7.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/15.usbdev_device_address.1649619290
Short name T88
Test name
Test status
Simulation time 20390271623 ps
CPU time 33.78 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:37 PM PDT 24
Peak memory 207664 kb
Host smart-f410816c-2c9b-49f0-83be-a1514f66518f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16496
19290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.1649619290
Directory /workspace/15.usbdev_device_address/latest


Test location /workspace/coverage/default/36.usbdev_link_resume.4088660006
Short name T41
Test name
Test status
Simulation time 22393691364 ps
CPU time 26.42 seconds
Started Aug 02 05:33:14 PM PDT 24
Finished Aug 02 05:33:41 PM PDT 24
Peak memory 207584 kb
Host smart-3cc3b8ff-f01d-41b3-8da4-2f79cf6fa9b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40886
60006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.4088660006
Directory /workspace/36.usbdev_link_resume/latest


Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.666779908
Short name T84
Test name
Test status
Simulation time 1098053605 ps
CPU time 2.81 seconds
Started Aug 02 05:28:46 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 207560 kb
Host smart-11e7d9f1-f31b-4921-a2c2-4a70612b0467
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=666779908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.666779908
Directory /workspace/8.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.326106692
Short name T114
Test name
Test status
Simulation time 9665567427 ps
CPU time 11.9 seconds
Started Aug 02 05:34:18 PM PDT 24
Finished Aug 02 05:34:30 PM PDT 24
Peak memory 207688 kb
Host smart-5b3a113b-d34a-4486-a3b1-f3baa463d9ec
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326106692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_ao
n_wake_disconnect.326106692
Directory /workspace/46.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/4.usbdev_sec_cm.3268465405
Short name T203
Test name
Test status
Simulation time 369644482 ps
CPU time 1.23 seconds
Started Aug 02 05:28:05 PM PDT 24
Finished Aug 02 05:28:06 PM PDT 24
Peak memory 223536 kb
Host smart-9d30ac4e-caee-4065-bacc-238325080682
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3268465405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3268465405
Directory /workspace/4.usbdev_sec_cm/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3239047023
Short name T112
Test name
Test status
Simulation time 347438101 ps
CPU time 1.12 seconds
Started Aug 02 05:26:13 PM PDT 24
Finished Aug 02 05:26:14 PM PDT 24
Peak memory 207324 kb
Host smart-bb372b33-dd1e-4919-beb4-7bd2397edf4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32390
47023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3239047023
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest


Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2666783834
Short name T26
Test name
Test status
Simulation time 34421361 ps
CPU time 0.69 seconds
Started Aug 02 05:34:53 PM PDT 24
Finished Aug 02 05:34:54 PM PDT 24
Peak memory 207356 kb
Host smart-d5007036-05a5-4477-8518-af43eeb5c399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
83834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2666783834
Directory /workspace/49.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.159139851
Short name T322
Test name
Test status
Simulation time 106872630 ps
CPU time 0.79 seconds
Started Aug 02 05:01:10 PM PDT 24
Finished Aug 02 05:01:11 PM PDT 24
Peak memory 206868 kb
Host smart-b1437b13-fc30-43fe-9a52-f493bd1c313c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=159139851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.159139851
Directory /workspace/49.usbdev_intr_test/latest


Test location /workspace/coverage/default/31.usbdev_disconnected.269896670
Short name T716
Test name
Test status
Simulation time 146296657 ps
CPU time 0.88 seconds
Started Aug 02 05:32:20 PM PDT 24
Finished Aug 02 05:32:22 PM PDT 24
Peak memory 207356 kb
Host smart-0a69b307-7aee-4c7d-aec3-602614b14d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26989
6670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.269896670
Directory /workspace/31.usbdev_disconnected/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2958964050
Short name T330
Test name
Test status
Simulation time 526937380 ps
CPU time 4.14 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:12 PM PDT 24
Peak memory 207252 kb
Host smart-6cb36d33-b381-4632-944e-bb1c592a0fff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2958964050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2958964050
Directory /workspace/15.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/23.usbdev_device_address.3200299025
Short name T90
Test name
Test status
Simulation time 42818296049 ps
CPU time 64.69 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:32:39 PM PDT 24
Peak memory 207468 kb
Host smart-858a1d38-6dc1-4414-907c-d13a3cbec44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32002
99025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.3200299025
Directory /workspace/23.usbdev_device_address/latest


Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2904945515
Short name T119
Test name
Test status
Simulation time 14998289373 ps
CPU time 15.67 seconds
Started Aug 02 05:31:37 PM PDT 24
Finished Aug 02 05:31:53 PM PDT 24
Peak memory 215848 kb
Host smart-48d119d1-d795-45cf-b5c5-6b5f79142c02
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904945515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2904945515
Directory /workspace/27.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1468982470
Short name T62
Test name
Test status
Simulation time 6851556151 ps
CPU time 33.41 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:53 PM PDT 24
Peak memory 219524 kb
Host smart-3a7500bd-2f35-4db6-8ba9-9108d1446aa9
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468982470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1468982470
Directory /workspace/2.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3323860265
Short name T270
Test name
Test status
Simulation time 79821118 ps
CPU time 1.03 seconds
Started Aug 02 05:01:02 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 206868 kb
Host smart-8a820675-2ce4-4492-b7b9-046bb62983c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3323860265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3323860265
Directory /workspace/18.usbdev_csr_rw/latest


Test location /workspace/coverage/default/33.usbdev_rx_full.102755820
Short name T3
Test name
Test status
Simulation time 268264968 ps
CPU time 1.11 seconds
Started Aug 02 05:32:29 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 207432 kb
Host smart-b18637b9-731b-4bc3-b1f0-22f718a4bfa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10275
5820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_full.102755820
Directory /workspace/33.usbdev_rx_full/latest


Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3028987010
Short name T110
Test name
Test status
Simulation time 15246968922 ps
CPU time 35.9 seconds
Started Aug 02 05:27:16 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 215684 kb
Host smart-8f72b989-c58c-41af-8a93-8f1c7d6ff7b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30289
87010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3028987010
Directory /workspace/2.usbdev_pkt_buffer/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1145477163
Short name T214
Test name
Test status
Simulation time 38759231 ps
CPU time 0.76 seconds
Started Aug 02 05:00:43 PM PDT 24
Finished Aug 02 05:00:44 PM PDT 24
Peak memory 206860 kb
Host smart-8eabda48-45e5-44d5-92c1-b418af71df58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1145477163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1145477163
Directory /workspace/0.usbdev_intr_test/latest


Test location /workspace/coverage/default/12.usbdev_rx_crc_err.317213915
Short name T72
Test name
Test status
Simulation time 158629791 ps
CPU time 0.89 seconds
Started Aug 02 05:29:41 PM PDT 24
Finished Aug 02 05:29:42 PM PDT 24
Peak memory 207416 kb
Host smart-8ee685f2-9efd-43c4-bdcb-c843fafd0e50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31721
3915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.317213915
Directory /workspace/12.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/42.usbdev_endpoint_types.1551242287
Short name T374
Test name
Test status
Simulation time 539761029 ps
CPU time 1.58 seconds
Started Aug 02 05:33:52 PM PDT 24
Finished Aug 02 05:33:53 PM PDT 24
Peak memory 207380 kb
Host smart-9abe204e-69d2-4f60-a7ce-3acd9b6a466a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1551242287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_types.1551242287
Directory /workspace/42.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/85.usbdev_endpoint_types.2817001118
Short name T439
Test name
Test status
Simulation time 928659100 ps
CPU time 1.78 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207268 kb
Host smart-b48dfbd4-cf54-41ba-8b5a-6f6e58229746
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2817001118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.usbdev_endpoint_types.2817001118
Directory /workspace/85.usbdev_endpoint_types/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1248340891
Short name T242
Test name
Test status
Simulation time 174971210 ps
CPU time 2.21 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:01:00 PM PDT 24
Peak memory 223320 kb
Host smart-b2d60d90-9172-45a3-a043-7a7624a892cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1248340891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1248340891
Directory /workspace/7.usbdev_tl_errors/latest


Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1665287731
Short name T164
Test name
Test status
Simulation time 3323524181 ps
CPU time 24.33 seconds
Started Aug 02 05:33:41 PM PDT 24
Finished Aug 02 05:34:05 PM PDT 24
Peak memory 218596 kb
Host smart-5459b725-1570-467e-a6d4-fede2e4a015b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16652
87731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1665287731
Directory /workspace/41.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/32.usbdev_endpoint_types.129616226
Short name T429
Test name
Test status
Simulation time 640358040 ps
CPU time 1.63 seconds
Started Aug 02 05:32:28 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 207392 kb
Host smart-1938cb04-3ed7-438c-af10-f7874456a9bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=129616226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_types.129616226
Directory /workspace/32.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/156.usbdev_endpoint_types.3993789744
Short name T406
Test name
Test status
Simulation time 472443141 ps
CPU time 1.34 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207356 kb
Host smart-af067633-e6ba-49bc-a203-26244b541731
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3993789744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.usbdev_endpoint_types.3993789744
Directory /workspace/156.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/0.usbdev_bitstuff_err.2810295618
Short name T841
Test name
Test status
Simulation time 187303815 ps
CPU time 0.85 seconds
Started Aug 02 05:25:47 PM PDT 24
Finished Aug 02 05:25:48 PM PDT 24
Peak memory 207372 kb
Host smart-5f501671-fb6f-455d-aa4a-d11eac89f4fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28102
95618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.2810295618
Directory /workspace/0.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/36.usbdev_endpoint_types.1664657932
Short name T363
Test name
Test status
Simulation time 615007123 ps
CPU time 1.49 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 207344 kb
Host smart-b50f24a0-a72e-4048-83a7-4d660e236fcc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1664657932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_types.1664657932
Directory /workspace/36.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/92.usbdev_endpoint_types.3021996944
Short name T475
Test name
Test status
Simulation time 729604116 ps
CPU time 2 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207360 kb
Host smart-b7597519-88a5-4bd4-aa58-3359117d716f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3021996944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.usbdev_endpoint_types.3021996944
Directory /workspace/92.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/20.usbdev_pkt_received.1601002758
Short name T326
Test name
Test status
Simulation time 275739518 ps
CPU time 0.98 seconds
Started Aug 02 05:31:02 PM PDT 24
Finished Aug 02 05:31:03 PM PDT 24
Peak memory 207392 kb
Host smart-9d136ddd-3cbf-463e-9b4a-4d072c6c1b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16010
02758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.1601002758
Directory /workspace/20.usbdev_pkt_received/latest


Test location /workspace/coverage/default/120.usbdev_endpoint_types.935188460
Short name T100
Test name
Test status
Simulation time 652975890 ps
CPU time 1.59 seconds
Started Aug 02 05:35:12 PM PDT 24
Finished Aug 02 05:35:13 PM PDT 24
Peak memory 207360 kb
Host smart-d13b6e1b-ede6-4ad6-9e0a-ca6014ee5c05
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=935188460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.usbdev_endpoint_types.935188460
Directory /workspace/120.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/44.usbdev_device_address.3966631188
Short name T184
Test name
Test status
Simulation time 56836527411 ps
CPU time 91.56 seconds
Started Aug 02 05:34:03 PM PDT 24
Finished Aug 02 05:35:35 PM PDT 24
Peak memory 207672 kb
Host smart-7ca37593-f433-421b-bcea-578e6b9afef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39666
31188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3966631188
Directory /workspace/44.usbdev_device_address/latest


Test location /workspace/coverage/default/170.usbdev_endpoint_types.1825859191
Short name T443
Test name
Test status
Simulation time 591036503 ps
CPU time 1.52 seconds
Started Aug 02 05:35:19 PM PDT 24
Finished Aug 02 05:35:20 PM PDT 24
Peak memory 207344 kb
Host smart-81788500-6e36-4254-b42f-ff6c242556c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1825859191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.usbdev_endpoint_types.1825859191
Directory /workspace/170.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.1352043269
Short name T82
Test name
Test status
Simulation time 10404473948 ps
CPU time 101.47 seconds
Started Aug 02 05:26:31 PM PDT 24
Finished Aug 02 05:28:13 PM PDT 24
Peak memory 224044 kb
Host smart-27754f9b-9b32-4424-908c-087c343d5d8e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352043269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.1352043269
Directory /workspace/0.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/141.usbdev_endpoint_types.3352059377
Short name T315
Test name
Test status
Simulation time 448267846 ps
CPU time 1.31 seconds
Started Aug 02 05:35:13 PM PDT 24
Finished Aug 02 05:35:14 PM PDT 24
Peak memory 207180 kb
Host smart-059a36a2-438e-4c4f-b69d-936d1cb87a80
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3352059377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.usbdev_endpoint_types.3352059377
Directory /workspace/141.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/148.usbdev_endpoint_types.3720513137
Short name T379
Test name
Test status
Simulation time 437454743 ps
CPU time 1.43 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207376 kb
Host smart-c493187b-dd01-4fdf-b111-3835b9aa7b99
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3720513137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.usbdev_endpoint_types.3720513137
Directory /workspace/148.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/152.usbdev_endpoint_types.2665003953
Short name T381
Test name
Test status
Simulation time 617599983 ps
CPU time 1.46 seconds
Started Aug 02 05:35:11 PM PDT 24
Finished Aug 02 05:35:13 PM PDT 24
Peak memory 207180 kb
Host smart-79b662bc-5e23-41fa-9c2c-0259428f2617
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2665003953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.usbdev_endpoint_types.2665003953
Directory /workspace/152.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/153.usbdev_endpoint_types.3883780302
Short name T384
Test name
Test status
Simulation time 811401450 ps
CPU time 1.77 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207376 kb
Host smart-ce804641-8f7b-46d6-b5f1-fdd53d1570b3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3883780302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.usbdev_endpoint_types.3883780302
Directory /workspace/153.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/15.usbdev_nak_trans.1119847348
Short name T131
Test name
Test status
Simulation time 226108271 ps
CPU time 0.97 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207344 kb
Host smart-6f966b80-afcc-4884-9679-59b7936f40df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11198
47348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1119847348
Directory /workspace/15.usbdev_nak_trans/latest


Test location /workspace/coverage/default/0.usbdev_setup_priority.2329281782
Short name T2929
Test name
Test status
Simulation time 400778878 ps
CPU time 1.47 seconds
Started Aug 02 05:26:28 PM PDT 24
Finished Aug 02 05:26:29 PM PDT 24
Peak memory 207384 kb
Host smart-e2392135-c780-4799-bb08-5d755e469f1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23292
81782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.2329281782
Directory /workspace/0.usbdev_setup_priority/latest


Test location /workspace/coverage/default/112.usbdev_endpoint_types.3828758474
Short name T446
Test name
Test status
Simulation time 346875895 ps
CPU time 1.27 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207356 kb
Host smart-c3e13cc1-e0d4-4a02-9eb5-aecf2ee74041
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3828758474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.usbdev_endpoint_types.3828758474
Directory /workspace/112.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/67.usbdev_endpoint_types.3242990060
Short name T453
Test name
Test status
Simulation time 636777302 ps
CPU time 1.49 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207308 kb
Host smart-2a218885-200c-4b3b-a3d5-77115d73a6f9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3242990060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.usbdev_endpoint_types.3242990060
Directory /workspace/67.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/10.usbdev_alert_test.1659954766
Short name T620
Test name
Test status
Simulation time 86687423 ps
CPU time 0.72 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207480 kb
Host smart-63294c43-0500-474a-a59d-78b18b63dada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1659954766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.1659954766
Directory /workspace/10.usbdev_alert_test/latest


Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.2102654356
Short name T14
Test name
Test status
Simulation time 20464090293 ps
CPU time 29.41 seconds
Started Aug 02 05:30:15 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 207656 kb
Host smart-34e74679-27ca-4fdc-af48-64310cd02aff
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102654356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.2102654356
Directory /workspace/15.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.3196107769
Short name T299
Test name
Test status
Simulation time 49923878 ps
CPU time 0.72 seconds
Started Aug 02 05:01:05 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 206944 kb
Host smart-3893cef9-1bbf-4d5b-ae1f-b21973b20f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3196107769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.3196107769
Directory /workspace/36.usbdev_intr_test/latest


Test location /workspace/coverage/default/0.usbdev_endpoint_types.1161281644
Short name T404
Test name
Test status
Simulation time 885137519 ps
CPU time 1.89 seconds
Started Aug 02 05:25:56 PM PDT 24
Finished Aug 02 05:25:58 PM PDT 24
Peak memory 207360 kb
Host smart-437b2578-6459-4a05-88da-ad1dff31ee8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1161281644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_types.1161281644
Directory /workspace/0.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/107.usbdev_endpoint_types.1344428309
Short name T397
Test name
Test status
Simulation time 485580459 ps
CPU time 1.38 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207388 kb
Host smart-7593cd2a-2783-45bd-a85f-7eb76db58a52
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1344428309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.usbdev_endpoint_types.1344428309
Directory /workspace/107.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/128.usbdev_endpoint_types.3227487914
Short name T448
Test name
Test status
Simulation time 534406941 ps
CPU time 1.49 seconds
Started Aug 02 05:35:13 PM PDT 24
Finished Aug 02 05:35:15 PM PDT 24
Peak memory 207292 kb
Host smart-57cb3cf2-f5a0-4e50-b63f-a03232c1c24b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3227487914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.usbdev_endpoint_types.3227487914
Directory /workspace/128.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/136.usbdev_endpoint_types.1049312534
Short name T466
Test name
Test status
Simulation time 804771621 ps
CPU time 2.02 seconds
Started Aug 02 05:35:07 PM PDT 24
Finished Aug 02 05:35:09 PM PDT 24
Peak memory 207388 kb
Host smart-fc3c39f4-5ff3-4ab1-be18-9607084097de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1049312534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.usbdev_endpoint_types.1049312534
Directory /workspace/136.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/192.usbdev_endpoint_types.2344889087
Short name T372
Test name
Test status
Simulation time 531815339 ps
CPU time 1.31 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:35:17 PM PDT 24
Peak memory 207396 kb
Host smart-a4a0a49c-83a2-4831-93c0-fecf4b9da51c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2344889087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.usbdev_endpoint_types.2344889087
Directory /workspace/192.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/25.usbdev_endpoint_types.2782635805
Short name T396
Test name
Test status
Simulation time 919825807 ps
CPU time 1.9 seconds
Started Aug 02 05:31:32 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 207328 kb
Host smart-0bb7b032-c4fc-458e-85b8-dcd90fc0aae1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2782635805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_types.2782635805
Directory /workspace/25.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/54.usbdev_endpoint_types.1439546073
Short name T367
Test name
Test status
Simulation time 383046952 ps
CPU time 1.18 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207388 kb
Host smart-61e129e2-7cc1-494e-93b9-dd5dbc36d175
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1439546073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.usbdev_endpoint_types.1439546073
Directory /workspace/54.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3005741344
Short name T70
Test name
Test status
Simulation time 472065069 ps
CPU time 1.4 seconds
Started Aug 02 05:26:09 PM PDT 24
Finished Aug 02 05:26:10 PM PDT 24
Peak memory 207372 kb
Host smart-2f52583e-b9a3-4457-8ec8-8e14322df774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
41344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3005741344
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2596037858
Short name T337
Test name
Test status
Simulation time 552136168 ps
CPU time 3.99 seconds
Started Aug 02 05:00:49 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 207156 kb
Host smart-9231c5c4-2c75-4b64-9307-6ef9178032dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2596037858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2596037858
Directory /workspace/3.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/49.usbdev_device_address.413717226
Short name T1970
Test name
Test status
Simulation time 33322220134 ps
CPU time 54.89 seconds
Started Aug 02 05:34:31 PM PDT 24
Finished Aug 02 05:35:26 PM PDT 24
Peak memory 207504 kb
Host smart-6ce30c24-9908-401d-b7eb-3b36ae8d67a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41371
7226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.413717226
Directory /workspace/49.usbdev_device_address/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.573026238
Short name T3163
Test name
Test status
Simulation time 352568604 ps
CPU time 3.78 seconds
Started Aug 02 05:01:01 PM PDT 24
Finished Aug 02 05:01:05 PM PDT 24
Peak memory 220984 kb
Host smart-85dc39ca-d3c1-4666-8c35-84849571a38f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=573026238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.573026238
Directory /workspace/11.usbdev_tl_errors/latest


Test location /workspace/coverage/default/0.usbdev_av_overflow.1190759796
Short name T59
Test name
Test status
Simulation time 144609210 ps
CPU time 0.81 seconds
Started Aug 02 05:25:49 PM PDT 24
Finished Aug 02 05:25:50 PM PDT 24
Peak memory 207340 kb
Host smart-405afefa-4fdd-4175-bff0-8aa8e5ee28d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11907
59796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1190759796
Directory /workspace/0.usbdev_av_overflow/latest


Test location /workspace/coverage/default/0.usbdev_dpi_config_host.869082867
Short name T318
Test name
Test status
Simulation time 5117087556 ps
CPU time 143.85 seconds
Started Aug 02 05:25:58 PM PDT 24
Finished Aug 02 05:28:22 PM PDT 24
Peak memory 215936 kb
Host smart-b6868292-ce28-46fb-b37a-e564f95f993d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86908
2867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.869082867
Directory /workspace/0.usbdev_dpi_config_host/latest


Test location /workspace/coverage/default/137.usbdev_endpoint_types.1616291718
Short name T403
Test name
Test status
Simulation time 483000987 ps
CPU time 1.34 seconds
Started Aug 02 05:35:07 PM PDT 24
Finished Aug 02 05:35:09 PM PDT 24
Peak memory 207364 kb
Host smart-ad472c15-fa3b-4ce3-abb4-61abd4ea586b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1616291718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.usbdev_endpoint_types.1616291718
Directory /workspace/137.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/166.usbdev_endpoint_types.3696242462
Short name T385
Test name
Test status
Simulation time 580591258 ps
CPU time 1.47 seconds
Started Aug 02 05:35:10 PM PDT 24
Finished Aug 02 05:35:11 PM PDT 24
Peak memory 207292 kb
Host smart-a46f1207-98ce-457c-a7af-fcea5b384803
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3696242462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.usbdev_endpoint_types.3696242462
Directory /workspace/166.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/169.usbdev_endpoint_types.1094270748
Short name T400
Test name
Test status
Simulation time 542512614 ps
CPU time 1.45 seconds
Started Aug 02 05:35:13 PM PDT 24
Finished Aug 02 05:35:14 PM PDT 24
Peak memory 207176 kb
Host smart-6242fc33-f5a5-4590-a974-7e40c61e7f7d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1094270748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.usbdev_endpoint_types.1094270748
Directory /workspace/169.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/175.usbdev_endpoint_types.2308503311
Short name T405
Test name
Test status
Simulation time 523380379 ps
CPU time 1.32 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207340 kb
Host smart-bacf1ccb-ebef-45ae-bcce-80569f4e8955
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2308503311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.usbdev_endpoint_types.2308503311
Directory /workspace/175.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/177.usbdev_endpoint_types.172342067
Short name T436
Test name
Test status
Simulation time 374488463 ps
CPU time 1.25 seconds
Started Aug 02 05:35:11 PM PDT 24
Finished Aug 02 05:35:12 PM PDT 24
Peak memory 207364 kb
Host smart-c6be1f78-fb45-4979-99a2-4c130d6f8fd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=172342067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.usbdev_endpoint_types.172342067
Directory /workspace/177.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/20.usbdev_endpoint_types.1899274030
Short name T487
Test name
Test status
Simulation time 408623705 ps
CPU time 1.25 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:56 PM PDT 24
Peak memory 207384 kb
Host smart-b0c8eb63-7579-4476-82e4-198b2e118386
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1899274030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_types.1899274030
Directory /workspace/20.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.1622862332
Short name T33
Test name
Test status
Simulation time 256530131 ps
CPU time 0.93 seconds
Started Aug 02 05:32:13 PM PDT 24
Finished Aug 02 05:32:14 PM PDT 24
Peak memory 207460 kb
Host smart-a4023240-f535-4646-8868-78dd328cabb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
62332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.1622862332
Directory /workspace/29.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/32.usbdev_rx_full.3734962396
Short name T301
Test name
Test status
Simulation time 240523325 ps
CPU time 1.02 seconds
Started Aug 02 05:32:27 PM PDT 24
Finished Aug 02 05:32:28 PM PDT 24
Peak memory 207376 kb
Host smart-c197e228-1d9d-4a34-8bcc-53f73fbbcd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37349
62396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_full.3734962396
Directory /workspace/32.usbdev_rx_full/latest


Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.2056341947
Short name T175
Test name
Test status
Simulation time 7884069706 ps
CPU time 35.75 seconds
Started Aug 02 05:28:39 PM PDT 24
Finished Aug 02 05:29:15 PM PDT 24
Peak memory 215900 kb
Host smart-43bea4eb-0fce-4ce9-bea2-950728875344
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056341947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.2056341947
Directory /workspace/7.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.4013077561
Short name T5
Test name
Test status
Simulation time 3554705848 ps
CPU time 27.54 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:44 PM PDT 24
Peak memory 224040 kb
Host smart-76519140-3ad2-4b4f-b303-b5fb0537fb2d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013077561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.4013077561
Directory /workspace/5.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/69.usbdev_endpoint_types.381853333
Short name T154
Test name
Test status
Simulation time 416606492 ps
CPU time 1.21 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207300 kb
Host smart-69625343-c97e-4003-99a2-016dead2c1ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=381853333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.usbdev_endpoint_types.381853333
Directory /workspace/69.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.146758790
Short name T28
Test name
Test status
Simulation time 44569974 ps
CPU time 0.68 seconds
Started Aug 02 05:29:38 PM PDT 24
Finished Aug 02 05:29:39 PM PDT 24
Peak memory 207388 kb
Host smart-18889b41-142a-4a3a-a2fb-9326b8da96b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14675
8790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.146758790
Directory /workspace/12.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4222739256
Short name T331
Test name
Test status
Simulation time 837899671 ps
CPU time 4.77 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 207268 kb
Host smart-40276876-e0f3-47b1-b3cc-cfc6e3d8c47d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4222739256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.4222739256
Directory /workspace/12.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.756383182
Short name T335
Test name
Test status
Simulation time 341700793 ps
CPU time 2.46 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:01:01 PM PDT 24
Peak memory 207264 kb
Host smart-7c4712bf-4d29-4b5c-b0bf-64f9347972b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=756383182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.756383182
Directory /workspace/13.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/1.usbdev_freq_hiclk.2368698329
Short name T98
Test name
Test status
Simulation time 108198709927 ps
CPU time 172.73 seconds
Started Aug 02 05:26:40 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207692 kb
Host smart-a860914d-82ea-4632-8e46-f8dec6b5679a
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2368698329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.2368698329
Directory /workspace/1.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/100.usbdev_endpoint_types.3024102442
Short name T358
Test name
Test status
Simulation time 574383801 ps
CPU time 1.51 seconds
Started Aug 02 05:34:50 PM PDT 24
Finished Aug 02 05:34:52 PM PDT 24
Peak memory 207376 kb
Host smart-1a22083f-0c1c-4a0f-a180-dee11b03fc95
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3024102442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.usbdev_endpoint_types.3024102442
Directory /workspace/100.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/101.usbdev_endpoint_types.1491627086
Short name T418
Test name
Test status
Simulation time 582767545 ps
CPU time 1.44 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207376 kb
Host smart-c71ea107-26f0-42b8-8453-46ff667b036d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1491627086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.usbdev_endpoint_types.1491627086
Directory /workspace/101.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/102.usbdev_endpoint_types.2556465864
Short name T364
Test name
Test status
Simulation time 478979008 ps
CPU time 1.41 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207348 kb
Host smart-0ffd2c2f-efd8-4c03-9963-763c1a432e37
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2556465864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.usbdev_endpoint_types.2556465864
Directory /workspace/102.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/106.usbdev_endpoint_types.2561249635
Short name T467
Test name
Test status
Simulation time 447858542 ps
CPU time 1.3 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207176 kb
Host smart-52165dc2-2359-43bb-a225-7b62f4216f2e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2561249635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.usbdev_endpoint_types.2561249635
Directory /workspace/106.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/117.usbdev_endpoint_types.4100925382
Short name T424
Test name
Test status
Simulation time 533092276 ps
CPU time 1.53 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207376 kb
Host smart-5dfde3a9-2179-430f-8896-cfca6e318e46
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4100925382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.usbdev_endpoint_types.4100925382
Directory /workspace/117.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/14.usbdev_endpoint_types.466720977
Short name T463
Test name
Test status
Simulation time 352969882 ps
CPU time 1.22 seconds
Started Aug 02 05:29:56 PM PDT 24
Finished Aug 02 05:29:57 PM PDT 24
Peak memory 207384 kb
Host smart-4ee05be4-5974-4e0a-9e6b-4eaa86b8e0b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=466720977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_types.466720977
Directory /workspace/14.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/140.usbdev_endpoint_types.3925676420
Short name T2906
Test name
Test status
Simulation time 434003936 ps
CPU time 1.24 seconds
Started Aug 02 05:35:20 PM PDT 24
Finished Aug 02 05:35:22 PM PDT 24
Peak memory 207380 kb
Host smart-8e75181a-5f41-4355-a852-7ce5a11547b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3925676420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.usbdev_endpoint_types.3925676420
Directory /workspace/140.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/19.usbdev_rx_full.2112755909
Short name T307
Test name
Test status
Simulation time 376506667 ps
CPU time 1.28 seconds
Started Aug 02 05:30:49 PM PDT 24
Finished Aug 02 05:30:51 PM PDT 24
Peak memory 207340 kb
Host smart-a5cbed52-99a3-4d5a-8201-e67de6ac2f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21127
55909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_full.2112755909
Directory /workspace/19.usbdev_rx_full/latest


Test location /workspace/coverage/default/197.usbdev_endpoint_types.2155946203
Short name T426
Test name
Test status
Simulation time 440178939 ps
CPU time 1.21 seconds
Started Aug 02 05:35:26 PM PDT 24
Finished Aug 02 05:35:27 PM PDT 24
Peak memory 207424 kb
Host smart-aa0459ae-b607-4cb5-bf50-b37a13630652
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2155946203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.usbdev_endpoint_types.2155946203
Directory /workspace/197.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/22.usbdev_rx_full.1288145198
Short name T306
Test name
Test status
Simulation time 265714687 ps
CPU time 1.06 seconds
Started Aug 02 05:31:33 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 207416 kb
Host smart-23e61aac-1d6e-4e41-8f00-75775ff88a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12881
45198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_full.1288145198
Directory /workspace/22.usbdev_rx_full/latest


Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.305193662
Short name T767
Test name
Test status
Simulation time 150346906 ps
CPU time 0.82 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:31:42 PM PDT 24
Peak memory 207364 kb
Host smart-cc42141b-1973-496a-8052-e951cf4a3d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30519
3662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.305193662
Directory /workspace/25.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/4.usbdev_endpoint_types.912860911
Short name T410
Test name
Test status
Simulation time 588124233 ps
CPU time 1.61 seconds
Started Aug 02 05:27:52 PM PDT 24
Finished Aug 02 05:27:54 PM PDT 24
Peak memory 207252 kb
Host smart-3d46465b-e658-412b-a4cb-b933b99c08cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=912860911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_types.912860911
Directory /workspace/4.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2334960746
Short name T579
Test name
Test status
Simulation time 204450647 ps
CPU time 0.9 seconds
Started Aug 02 05:29:32 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207328 kb
Host smart-40404b28-3cdc-427a-8c31-4edbc23274f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23349
60746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2334960746
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/2.usbdev_av_overflow.2225797332
Short name T58
Test name
Test status
Simulation time 190523461 ps
CPU time 0.83 seconds
Started Aug 02 05:26:59 PM PDT 24
Finished Aug 02 05:27:00 PM PDT 24
Peak memory 207368 kb
Host smart-bef27396-e7db-416a-a84a-e16f0f42c1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22257
97332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2225797332
Directory /workspace/2.usbdev_av_overflow/latest


Test location /workspace/coverage/default/0.usbdev_av_empty.1113579902
Short name T54
Test name
Test status
Simulation time 174967645 ps
CPU time 0.91 seconds
Started Aug 02 05:25:51 PM PDT 24
Finished Aug 02 05:25:52 PM PDT 24
Peak memory 207416 kb
Host smart-e15c75e3-f90f-49fb-b77d-b2103192e7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11135
79902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.1113579902
Directory /workspace/0.usbdev_av_empty/latest


Test location /workspace/coverage/default/0.usbdev_host_lost.906283882
Short name T65
Test name
Test status
Simulation time 4153711158 ps
CPU time 10.12 seconds
Started Aug 02 05:26:06 PM PDT 24
Finished Aug 02 05:26:16 PM PDT 24
Peak memory 207612 kb
Host smart-84e7c957-df4f-4e01-be56-7057ba63588e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90628
3882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.906283882
Directory /workspace/0.usbdev_host_lost/latest


Test location /workspace/coverage/default/0.usbdev_link_reset.3056267626
Short name T66
Test name
Test status
Simulation time 157380173 ps
CPU time 0.8 seconds
Started Aug 02 05:26:06 PM PDT 24
Finished Aug 02 05:26:07 PM PDT 24
Peak memory 207376 kb
Host smart-70f7f933-e165-4cac-a256-2e675d417ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30562
67626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3056267626
Directory /workspace/0.usbdev_link_reset/latest


Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3152543663
Short name T2115
Test name
Test status
Simulation time 205365668 ps
CPU time 0.9 seconds
Started Aug 02 05:26:26 PM PDT 24
Finished Aug 02 05:26:27 PM PDT 24
Peak memory 207372 kb
Host smart-861a3b0c-021b-41dd-8b36-5ac63a66f594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31525
43663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3152543663
Directory /workspace/0.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/18.usbdev_device_address.1959495096
Short name T1543
Test name
Test status
Simulation time 43173012036 ps
CPU time 76.05 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207720 kb
Host smart-ceed8686-e91e-4194-ada3-61d471aee53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19594
95096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1959495096
Directory /workspace/18.usbdev_device_address/latest


Test location /workspace/coverage/default/2.usbdev_av_empty.3732696195
Short name T48
Test name
Test status
Simulation time 184341887 ps
CPU time 0.87 seconds
Started Aug 02 05:26:58 PM PDT 24
Finished Aug 02 05:26:59 PM PDT 24
Peak memory 207336 kb
Host smart-fb3be996-c59d-4e38-86e7-ce2f32c93013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37326
96195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.3732696195
Directory /workspace/2.usbdev_av_empty/latest


Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1454919797
Short name T166
Test name
Test status
Simulation time 3038610083 ps
CPU time 85.44 seconds
Started Aug 02 05:31:00 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 218584 kb
Host smart-ea2a453b-a9aa-44d4-94c1-c54252fd060d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14549
19797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1454919797
Directory /workspace/22.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/0.usbdev_fifo_rst.3868103733
Short name T709
Test name
Test status
Simulation time 269227019 ps
CPU time 1.97 seconds
Started Aug 02 05:26:09 PM PDT 24
Finished Aug 02 05:26:11 PM PDT 24
Peak memory 207528 kb
Host smart-edae8604-51e7-4172-8d66-318dba6f678b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38681
03733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3868103733
Directory /workspace/0.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/0.usbdev_nak_trans.3690798999
Short name T2447
Test name
Test status
Simulation time 277727101 ps
CPU time 1.05 seconds
Started Aug 02 05:26:14 PM PDT 24
Finished Aug 02 05:26:15 PM PDT 24
Peak memory 207396 kb
Host smart-c3572ff6-9da0-4fef-90b1-c09ba05dd0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36907
98999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3690798999
Directory /workspace/0.usbdev_nak_trans/latest


Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2434440060
Short name T1651
Test name
Test status
Simulation time 156284224 ps
CPU time 0.82 seconds
Started Aug 02 05:26:14 PM PDT 24
Finished Aug 02 05:26:15 PM PDT 24
Peak memory 207352 kb
Host smart-ab704c95-07ca-42f3-b8e4-9c2efdd3390d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24344
40060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2434440060
Directory /workspace/0.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_nak_trans.659388391
Short name T136
Test name
Test status
Simulation time 231625514 ps
CPU time 0.92 seconds
Started Aug 02 05:26:41 PM PDT 24
Finished Aug 02 05:26:42 PM PDT 24
Peak memory 207416 kb
Host smart-544da6cb-7403-4403-91ce-4143661882fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65938
8391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.659388391
Directory /workspace/1.usbdev_nak_trans/latest


Test location /workspace/coverage/default/11.usbdev_nak_trans.802752517
Short name T145
Test name
Test status
Simulation time 236739921 ps
CPU time 0.88 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:32 PM PDT 24
Peak memory 207352 kb
Host smart-a5d556c1-830a-446d-80cd-8ee7d7b3d4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80275
2517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.802752517
Directory /workspace/11.usbdev_nak_trans/latest


Test location /workspace/coverage/default/12.usbdev_nak_trans.2794916170
Short name T3013
Test name
Test status
Simulation time 231919888 ps
CPU time 0.94 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:41 PM PDT 24
Peak memory 207404 kb
Host smart-11955f4f-11e5-49ca-ad9a-af51dae3097d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27949
16170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2794916170
Directory /workspace/12.usbdev_nak_trans/latest


Test location /workspace/coverage/default/13.usbdev_nak_trans.2599098024
Short name T157
Test name
Test status
Simulation time 213817969 ps
CPU time 0.94 seconds
Started Aug 02 05:29:48 PM PDT 24
Finished Aug 02 05:29:49 PM PDT 24
Peak memory 207340 kb
Host smart-c635d72c-c583-441d-805c-95e79726c67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25990
98024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.2599098024
Directory /workspace/13.usbdev_nak_trans/latest


Test location /workspace/coverage/default/14.usbdev_nak_trans.3114757464
Short name T137
Test name
Test status
Simulation time 202195275 ps
CPU time 0.94 seconds
Started Aug 02 05:29:54 PM PDT 24
Finished Aug 02 05:29:55 PM PDT 24
Peak memory 207384 kb
Host smart-27e46005-22d1-45e7-b6b0-d831e8f3499c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31147
57464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3114757464
Directory /workspace/14.usbdev_nak_trans/latest


Test location /workspace/coverage/default/21.usbdev_nak_trans.379088336
Short name T139
Test name
Test status
Simulation time 163725593 ps
CPU time 0.86 seconds
Started Aug 02 05:30:57 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 207420 kb
Host smart-6daf548c-694f-41b1-bd86-b8cd8f515fe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37908
8336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.379088336
Directory /workspace/21.usbdev_nak_trans/latest


Test location /workspace/coverage/default/35.usbdev_nak_trans.194640358
Short name T143
Test name
Test status
Simulation time 224244777 ps
CPU time 0.96 seconds
Started Aug 02 05:33:07 PM PDT 24
Finished Aug 02 05:33:08 PM PDT 24
Peak memory 207380 kb
Host smart-33651421-4947-4f65-abaa-89e5087b8254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19464
0358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.194640358
Directory /workspace/35.usbdev_nak_trans/latest


Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3061761887
Short name T130
Test name
Test status
Simulation time 4026791225 ps
CPU time 25.69 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:28:27 PM PDT 24
Peak memory 223980 kb
Host smart-c7ecd653-3d93-4caf-a60b-1b2627c7548e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061761887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3061761887
Directory /workspace/4.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/44.usbdev_nak_trans.3090925758
Short name T159
Test name
Test status
Simulation time 189804849 ps
CPU time 0.85 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 207384 kb
Host smart-3eead666-3485-47be-8e9f-0a9fb5ee8c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30909
25758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3090925758
Directory /workspace/44.usbdev_nak_trans/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2455761275
Short name T279
Test name
Test status
Simulation time 226509030 ps
CPU time 2.13 seconds
Started Aug 02 05:00:44 PM PDT 24
Finished Aug 02 05:00:46 PM PDT 24
Peak memory 207204 kb
Host smart-e0143935-7663-4f9b-9b9f-67b72931446b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2455761275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2455761275
Directory /workspace/0.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2224382688
Short name T3183
Test name
Test status
Simulation time 1523881986 ps
CPU time 9.07 seconds
Started Aug 02 05:00:42 PM PDT 24
Finished Aug 02 05:00:51 PM PDT 24
Peak memory 207168 kb
Host smart-3e983615-9fd8-4adb-a223-59d860a80591
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2224382688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2224382688
Directory /workspace/0.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.526094654
Short name T274
Test name
Test status
Simulation time 163616136 ps
CPU time 0.95 seconds
Started Aug 02 05:00:43 PM PDT 24
Finished Aug 02 05:00:44 PM PDT 24
Peak memory 206900 kb
Host smart-783ca7e6-a3bb-46d8-b838-80a7a61f9b2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=526094654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.526094654
Directory /workspace/0.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2162875457
Short name T3156
Test name
Test status
Simulation time 108727852 ps
CPU time 1.32 seconds
Started Aug 02 05:00:41 PM PDT 24
Finished Aug 02 05:00:43 PM PDT 24
Peak memory 215468 kb
Host smart-b79c0fd6-f19e-4280-b485-37956a020573
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162875457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.2162875457
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1409337501
Short name T233
Test name
Test status
Simulation time 84299136 ps
CPU time 1.03 seconds
Started Aug 02 05:00:48 PM PDT 24
Finished Aug 02 05:00:49 PM PDT 24
Peak memory 206872 kb
Host smart-6219fc68-cb9a-4ecb-a8dd-29fa49d6b7cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1409337501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1409337501
Directory /workspace/0.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3937928545
Short name T269
Test name
Test status
Simulation time 74731709 ps
CPU time 2.16 seconds
Started Aug 02 05:00:46 PM PDT 24
Finished Aug 02 05:00:49 PM PDT 24
Peak memory 215292 kb
Host smart-a1ec6649-55d8-4b26-b26a-d73407bcc4f8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3937928545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3937928545
Directory /workspace/0.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.761386715
Short name T3123
Test name
Test status
Simulation time 162508372 ps
CPU time 4.01 seconds
Started Aug 02 05:00:38 PM PDT 24
Finished Aug 02 05:00:42 PM PDT 24
Peak memory 206996 kb
Host smart-d4576348-0b1c-47bd-b058-1dce0c734eb5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=761386715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.761386715
Directory /workspace/0.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.227039705
Short name T3177
Test name
Test status
Simulation time 146787873 ps
CPU time 1.43 seconds
Started Aug 02 05:00:49 PM PDT 24
Finished Aug 02 05:00:51 PM PDT 24
Peak memory 207228 kb
Host smart-47a63006-9842-41ef-a211-3487193bc1b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=227039705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.227039705
Directory /workspace/0.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2758540991
Short name T248
Test name
Test status
Simulation time 200758499 ps
CPU time 2.72 seconds
Started Aug 02 05:00:45 PM PDT 24
Finished Aug 02 05:00:49 PM PDT 24
Peak memory 223464 kb
Host smart-753f7617-ab06-4954-a28c-c12ec313419d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2758540991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2758540991
Directory /workspace/0.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2238463210
Short name T3171
Test name
Test status
Simulation time 358875768 ps
CPU time 2.27 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:01:00 PM PDT 24
Peak memory 207252 kb
Host smart-cb4d98ac-ca77-44f7-891f-e6a9e7de7fec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2238463210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2238463210
Directory /workspace/0.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.1742254696
Short name T3182
Test name
Test status
Simulation time 236961976 ps
CPU time 2.2 seconds
Started Aug 02 05:00:40 PM PDT 24
Finished Aug 02 05:00:43 PM PDT 24
Peak memory 207124 kb
Host smart-5abbe89e-3032-4927-aa59-f6990875d5b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1742254696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.1742254696
Directory /workspace/1.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1504447957
Short name T3186
Test name
Test status
Simulation time 1991854477 ps
CPU time 10.54 seconds
Started Aug 02 05:00:44 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 207064 kb
Host smart-a8a8931f-33db-4175-adf1-efe008e3d337
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1504447957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1504447957
Directory /workspace/1.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2526868375
Short name T272
Test name
Test status
Simulation time 93074143 ps
CPU time 1.02 seconds
Started Aug 02 05:00:51 PM PDT 24
Finished Aug 02 05:00:53 PM PDT 24
Peak memory 207040 kb
Host smart-20d10347-c2fb-4c7b-9ccf-ced477f362ad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2526868375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2526868375
Directory /workspace/1.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2486638948
Short name T3167
Test name
Test status
Simulation time 185110421 ps
CPU time 1.88 seconds
Started Aug 02 05:00:42 PM PDT 24
Finished Aug 02 05:00:44 PM PDT 24
Peak memory 215456 kb
Host smart-7ad4ebb4-cfa3-4733-8be3-1989e1b98748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486638948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.2486638948
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.823004378
Short name T3149
Test name
Test status
Simulation time 112281613 ps
CPU time 0.95 seconds
Started Aug 02 05:00:49 PM PDT 24
Finished Aug 02 05:00:50 PM PDT 24
Peak memory 207072 kb
Host smart-03a53910-7181-4bf7-bab5-83a8d88ad43b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=823004378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.823004378
Directory /workspace/1.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.3553319154
Short name T3135
Test name
Test status
Simulation time 46077312 ps
CPU time 0.7 seconds
Started Aug 02 05:00:40 PM PDT 24
Finished Aug 02 05:00:41 PM PDT 24
Peak memory 206840 kb
Host smart-962bab83-fea5-4fc6-ad6f-ee984bf21e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3553319154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.3553319154
Directory /workspace/1.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2995881290
Short name T275
Test name
Test status
Simulation time 196179093 ps
CPU time 2.38 seconds
Started Aug 02 05:00:45 PM PDT 24
Finished Aug 02 05:00:47 PM PDT 24
Peak memory 215232 kb
Host smart-d08e7745-dbbc-4022-b1e0-1098c95664ed
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2995881290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2995881290
Directory /workspace/1.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.4013271124
Short name T3166
Test name
Test status
Simulation time 380600954 ps
CPU time 2.71 seconds
Started Aug 02 05:00:41 PM PDT 24
Finished Aug 02 05:00:44 PM PDT 24
Peak memory 207156 kb
Host smart-f3eaf6dd-180e-44e7-b736-f50ce4d75587
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4013271124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.4013271124
Directory /workspace/1.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1976137865
Short name T3110
Test name
Test status
Simulation time 122051939 ps
CPU time 1.64 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 207304 kb
Host smart-49291922-3dd2-47a2-9c62-eb9b9c53f100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1976137865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1976137865
Directory /workspace/1.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3044497336
Short name T247
Test name
Test status
Simulation time 160255908 ps
CPU time 2.07 seconds
Started Aug 02 05:00:49 PM PDT 24
Finished Aug 02 05:00:52 PM PDT 24
Peak memory 207088 kb
Host smart-c1e9c16a-e116-4857-b4bc-84e121977c24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3044497336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3044497336
Directory /workspace/1.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.2554359446
Short name T235
Test name
Test status
Simulation time 331391431 ps
CPU time 2.43 seconds
Started Aug 02 05:00:41 PM PDT 24
Finished Aug 02 05:00:43 PM PDT 24
Peak memory 207164 kb
Host smart-649f1586-3e4a-4780-9288-1e46103fc564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2554359446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.2554359446
Directory /workspace/1.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2605519151
Short name T252
Test name
Test status
Simulation time 105692692 ps
CPU time 1.25 seconds
Started Aug 02 05:00:55 PM PDT 24
Finished Aug 02 05:00:56 PM PDT 24
Peak memory 215508 kb
Host smart-8c2c21f7-fac5-4a50-ab5c-0ea8a0c82f84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605519151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2605519151
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1039793482
Short name T3132
Test name
Test status
Simulation time 47522326 ps
CPU time 0.85 seconds
Started Aug 02 05:00:51 PM PDT 24
Finished Aug 02 05:00:52 PM PDT 24
Peak memory 207016 kb
Host smart-5901187a-81fb-49d4-9193-adba2819d0a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1039793482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1039793482
Directory /workspace/10.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.560557850
Short name T296
Test name
Test status
Simulation time 62134731 ps
CPU time 0.76 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 206904 kb
Host smart-e59626a3-b843-4a3e-9971-94c67e9505e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=560557850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.560557850
Directory /workspace/10.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1979119650
Short name T3161
Test name
Test status
Simulation time 90255229 ps
CPU time 1.14 seconds
Started Aug 02 05:00:51 PM PDT 24
Finished Aug 02 05:00:53 PM PDT 24
Peak memory 207220 kb
Host smart-1511a065-3494-4ccf-aa68-9ae4a1f3b524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1979119650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.1979119650
Directory /workspace/10.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.105678264
Short name T243
Test name
Test status
Simulation time 98532629 ps
CPU time 1.39 seconds
Started Aug 02 05:00:55 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 207144 kb
Host smart-01b6b2b2-d55e-4901-a2b7-fa3ca4b23aaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=105678264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.105678264
Directory /workspace/10.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3590780505
Short name T3169
Test name
Test status
Simulation time 504065378 ps
CPU time 4.25 seconds
Started Aug 02 05:00:55 PM PDT 24
Finished Aug 02 05:00:59 PM PDT 24
Peak memory 207164 kb
Host smart-fde40c97-6a22-44a6-8056-8e7af8233a6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3590780505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3590780505
Directory /workspace/10.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3493291017
Short name T295
Test name
Test status
Simulation time 147025535 ps
CPU time 1.32 seconds
Started Aug 02 05:01:02 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 215372 kb
Host smart-d0d18171-278b-4b15-8595-74e432113700
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493291017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3493291017
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2505289370
Short name T3205
Test name
Test status
Simulation time 52371020 ps
CPU time 1.01 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 206984 kb
Host smart-803ce07c-1e42-43a9-87d6-cd26fd7618f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2505289370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2505289370
Directory /workspace/11.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3891304534
Short name T3190
Test name
Test status
Simulation time 48843731 ps
CPU time 0.75 seconds
Started Aug 02 05:00:51 PM PDT 24
Finished Aug 02 05:00:52 PM PDT 24
Peak memory 206844 kb
Host smart-fcfee7a9-7358-4694-a1fe-9425e0746b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3891304534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3891304534
Directory /workspace/11.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3380901021
Short name T209
Test name
Test status
Simulation time 173013353 ps
CPU time 1.6 seconds
Started Aug 02 05:00:54 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 207068 kb
Host smart-265ce27c-6e29-4398-9f49-3d70b9ad310b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3380901021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3380901021
Directory /workspace/11.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1709863411
Short name T3206
Test name
Test status
Simulation time 859797139 ps
CPU time 2.86 seconds
Started Aug 02 05:00:54 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 207096 kb
Host smart-7c79ac0b-eac2-48f7-9995-2d10d38e030d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1709863411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1709863411
Directory /workspace/11.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.4166656122
Short name T3126
Test name
Test status
Simulation time 107768904 ps
CPU time 2.07 seconds
Started Aug 02 05:00:51 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 215440 kb
Host smart-731ac173-acee-464f-bb19-77c9a5429183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166656122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.4166656122
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2486530769
Short name T3118
Test name
Test status
Simulation time 71243513 ps
CPU time 0.86 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 206960 kb
Host smart-c70f371d-8d09-4e57-ad33-31ab7ff6e245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2486530769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2486530769
Directory /workspace/12.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2665943206
Short name T217
Test name
Test status
Simulation time 30734165 ps
CPU time 0.74 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 206808 kb
Host smart-28c50d81-e10e-4f6e-89d8-b37937707477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2665943206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2665943206
Directory /workspace/12.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3300293694
Short name T3184
Test name
Test status
Simulation time 210110452 ps
CPU time 1.35 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 206996 kb
Host smart-9ee4ad2c-ee1c-43f0-a748-f53bdaad055a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3300293694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3300293694
Directory /workspace/12.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.621346197
Short name T244
Test name
Test status
Simulation time 206928262 ps
CPU time 2.3 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:59 PM PDT 24
Peak memory 207104 kb
Host smart-131b3c63-9a34-47c9-b6c3-3f5e688321e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=621346197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.621346197
Directory /workspace/12.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1043162249
Short name T230
Test name
Test status
Simulation time 108349072 ps
CPU time 1.28 seconds
Started Aug 02 05:00:54 PM PDT 24
Finished Aug 02 05:00:56 PM PDT 24
Peak memory 215472 kb
Host smart-6d20a0e0-812a-43ca-9626-c85b5a27c921
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043162249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1043162249
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2601927097
Short name T3175
Test name
Test status
Simulation time 53283260 ps
CPU time 0.79 seconds
Started Aug 02 05:00:54 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 206852 kb
Host smart-e0ca764f-075a-456d-b34e-24f70c6f1244
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2601927097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2601927097
Directory /workspace/13.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1122349851
Short name T3208
Test name
Test status
Simulation time 43083350 ps
CPU time 0.73 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 206808 kb
Host smart-0b46fa18-da90-434c-825b-5908d036242a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1122349851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1122349851
Directory /workspace/13.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3340936024
Short name T3213
Test name
Test status
Simulation time 55842365 ps
CPU time 1.01 seconds
Started Aug 02 05:00:53 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 206864 kb
Host smart-2b7f71f0-0db6-44d8-ab6d-edaa4cf3f4a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3340936024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3340936024
Directory /workspace/13.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2691063066
Short name T241
Test name
Test status
Simulation time 86679152 ps
CPU time 2.08 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:00:59 PM PDT 24
Peak memory 207148 kb
Host smart-d97071b5-3c90-4cd7-be24-2e2de0b2d3da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2691063066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2691063066
Directory /workspace/13.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2437490918
Short name T3200
Test name
Test status
Simulation time 85556306 ps
CPU time 1.28 seconds
Started Aug 02 05:01:08 PM PDT 24
Finished Aug 02 05:01:10 PM PDT 24
Peak memory 215464 kb
Host smart-6beeac23-458b-44af-81a3-601af595edd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437490918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.2437490918
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3865056312
Short name T3158
Test name
Test status
Simulation time 89067665 ps
CPU time 0.99 seconds
Started Aug 02 05:01:09 PM PDT 24
Finished Aug 02 05:01:10 PM PDT 24
Peak memory 207024 kb
Host smart-e2c0c965-74ab-4342-b18d-8a0cc11d1bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3865056312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3865056312
Directory /workspace/14.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3902156664
Short name T323
Test name
Test status
Simulation time 45453444 ps
CPU time 0.75 seconds
Started Aug 02 05:01:00 PM PDT 24
Finished Aug 02 05:01:01 PM PDT 24
Peak memory 206768 kb
Host smart-84042010-ed1e-4ebc-b84d-83579e81a274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3902156664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3902156664
Directory /workspace/14.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3216979659
Short name T281
Test name
Test status
Simulation time 81279321 ps
CPU time 1.44 seconds
Started Aug 02 05:01:01 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 207252 kb
Host smart-ee33125c-aa5a-456a-9aad-6463f030b3b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3216979659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3216979659
Directory /workspace/14.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3276249850
Short name T3198
Test name
Test status
Simulation time 65121245 ps
CPU time 1.89 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:00:59 PM PDT 24
Peak memory 215372 kb
Host smart-688c365b-188b-433a-91c8-079139228900
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3276249850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3276249850
Directory /workspace/14.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.2125712296
Short name T336
Test name
Test status
Simulation time 463116455 ps
CPU time 2.87 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:01:00 PM PDT 24
Peak memory 207192 kb
Host smart-868d64f4-0b2f-4bb6-a303-5c4c7141a434
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2125712296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.2125712296
Directory /workspace/14.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3543121333
Short name T3179
Test name
Test status
Simulation time 77837994 ps
CPU time 1.76 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:09 PM PDT 24
Peak memory 215544 kb
Host smart-72162d54-d4e6-4a7d-b5f0-73695dd44c04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543121333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3543121333
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.211286125
Short name T3122
Test name
Test status
Simulation time 65467291 ps
CPU time 0.97 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:00:59 PM PDT 24
Peak memory 207012 kb
Host smart-1964f78f-ee35-4b5e-a1d1-882b3f527b14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=211286125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.211286125
Directory /workspace/15.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.1503677103
Short name T3152
Test name
Test status
Simulation time 86979416 ps
CPU time 0.81 seconds
Started Aug 02 05:01:05 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 206844 kb
Host smart-740e28f2-8ff1-4946-bdc0-79524384a0d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1503677103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1503677103
Directory /workspace/15.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3843816787
Short name T285
Test name
Test status
Simulation time 336977232 ps
CPU time 1.64 seconds
Started Aug 02 05:01:04 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 207160 kb
Host smart-f353dedd-cf1d-4319-9d9a-ca3e33ed492e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3843816787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3843816787
Directory /workspace/15.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2789783817
Short name T3162
Test name
Test status
Simulation time 131754668 ps
CPU time 2.45 seconds
Started Aug 02 05:01:08 PM PDT 24
Finished Aug 02 05:01:11 PM PDT 24
Peak memory 207204 kb
Host smart-db8ec635-fdd0-46c3-ab85-02293deb5b77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2789783817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2789783817
Directory /workspace/15.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2123665689
Short name T3140
Test name
Test status
Simulation time 62637118 ps
CPU time 1.59 seconds
Started Aug 02 05:01:08 PM PDT 24
Finished Aug 02 05:01:10 PM PDT 24
Peak memory 215444 kb
Host smart-3dfd8eb9-b9f8-4bd2-9bf0-a355f65289b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123665689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2123665689
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3593986466
Short name T3139
Test name
Test status
Simulation time 76251887 ps
CPU time 1 seconds
Started Aug 02 05:01:10 PM PDT 24
Finished Aug 02 05:01:11 PM PDT 24
Peak memory 207044 kb
Host smart-0066b6e4-eff3-4336-9d8d-1647a381e8dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3593986466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3593986466
Directory /workspace/16.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1650448780
Short name T3145
Test name
Test status
Simulation time 41425363 ps
CPU time 0.68 seconds
Started Aug 02 05:01:05 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 206908 kb
Host smart-a08589c4-c00d-450b-8321-d0e0bfdf1096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1650448780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1650448780
Directory /workspace/16.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3642792574
Short name T3136
Test name
Test status
Simulation time 82583981 ps
CPU time 0.97 seconds
Started Aug 02 05:01:00 PM PDT 24
Finished Aug 02 05:01:01 PM PDT 24
Peak memory 206988 kb
Host smart-2e3a4bd5-fcf6-404c-929c-c88476c29fdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3642792574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3642792574
Directory /workspace/16.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4213940804
Short name T3204
Test name
Test status
Simulation time 81675327 ps
CPU time 1.38 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:07 PM PDT 24
Peak memory 207156 kb
Host smart-9a699040-8e22-4494-9120-9652fc2d9dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4213940804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.4213940804
Directory /workspace/16.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2426041168
Short name T334
Test name
Test status
Simulation time 917001003 ps
CPU time 4.94 seconds
Started Aug 02 05:00:59 PM PDT 24
Finished Aug 02 05:01:04 PM PDT 24
Peak memory 207112 kb
Host smart-b3bc072f-7afb-4307-87bc-37530efca237
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2426041168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2426041168
Directory /workspace/16.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2439511086
Short name T3114
Test name
Test status
Simulation time 80152774 ps
CPU time 0.88 seconds
Started Aug 02 05:01:05 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 206984 kb
Host smart-4ce3e656-882b-4e4a-84b3-4e2dc66fb639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2439511086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2439511086
Directory /workspace/17.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3506112412
Short name T3124
Test name
Test status
Simulation time 123058723 ps
CPU time 0.8 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 206764 kb
Host smart-7f25c8fb-ef3d-48ad-8cac-4b53151ff71d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3506112412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3506112412
Directory /workspace/17.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.235216068
Short name T3172
Test name
Test status
Simulation time 261184845 ps
CPU time 1.76 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 207184 kb
Host smart-14275688-c0b2-4544-b3f0-9f1780ee893a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=235216068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.235216068
Directory /workspace/17.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.4098873166
Short name T3170
Test name
Test status
Simulation time 267201573 ps
CPU time 2.83 seconds
Started Aug 02 05:01:05 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 223416 kb
Host smart-4a6d6c8a-1a53-4e91-9d09-59e0a92a9ba1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4098873166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.4098873166
Directory /workspace/17.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1951339596
Short name T237
Test name
Test status
Simulation time 649673496 ps
CPU time 4.23 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:11 PM PDT 24
Peak memory 207232 kb
Host smart-317b88fd-62ef-45cc-b30a-a66dfd5efe68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1951339596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1951339596
Directory /workspace/17.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.313179986
Short name T251
Test name
Test status
Simulation time 106497832 ps
CPU time 2.5 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:09 PM PDT 24
Peak memory 215360 kb
Host smart-25da3391-c0c6-4304-b254-cc1fcab7b0a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313179986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbde
v_csr_mem_rw_with_rand_reset.313179986
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1825102009
Short name T3120
Test name
Test status
Simulation time 61837227 ps
CPU time 0.72 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 206844 kb
Host smart-d8fc95a0-d8e2-4368-908f-b096336f3af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1825102009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1825102009
Directory /workspace/18.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3092420100
Short name T3159
Test name
Test status
Simulation time 210827389 ps
CPU time 1.61 seconds
Started Aug 02 05:01:01 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 207144 kb
Host smart-07b16570-0a2c-4712-acd2-553205b64802
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3092420100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3092420100
Directory /workspace/18.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.865119901
Short name T3197
Test name
Test status
Simulation time 180305413 ps
CPU time 1.96 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 207260 kb
Host smart-365a52fd-8346-46dc-9cc0-ff953a1a58df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=865119901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.865119901
Directory /workspace/18.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.916451367
Short name T338
Test name
Test status
Simulation time 1931376339 ps
CPU time 5.9 seconds
Started Aug 02 05:01:01 PM PDT 24
Finished Aug 02 05:01:07 PM PDT 24
Peak memory 207204 kb
Host smart-99ad432d-7c36-469b-a57e-93e04204c424
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=916451367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.916451367
Directory /workspace/18.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1196973079
Short name T3173
Test name
Test status
Simulation time 111727047 ps
CPU time 1.42 seconds
Started Aug 02 05:01:04 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 215500 kb
Host smart-c785ce37-d596-4124-afef-289d7c2c8512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196973079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1196973079
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4020117631
Short name T280
Test name
Test status
Simulation time 45793263 ps
CPU time 0.94 seconds
Started Aug 02 05:01:00 PM PDT 24
Finished Aug 02 05:01:02 PM PDT 24
Peak memory 207036 kb
Host smart-b982a8ac-3b93-4f79-bc90-b896ef59ca1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4020117631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4020117631
Directory /workspace/19.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1577494024
Short name T3191
Test name
Test status
Simulation time 37616117 ps
CPU time 0.72 seconds
Started Aug 02 05:01:02 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 206784 kb
Host smart-cd75b11e-0d27-4fb8-9bd2-be654750d184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1577494024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1577494024
Directory /workspace/19.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3977276785
Short name T3137
Test name
Test status
Simulation time 181167885 ps
CPU time 1.46 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 207136 kb
Host smart-8f2e4ec8-5988-4ea2-8670-5ee77d22648c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3977276785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3977276785
Directory /workspace/19.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3027146747
Short name T231
Test name
Test status
Simulation time 117568525 ps
CPU time 1.53 seconds
Started Aug 02 05:01:01 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 207276 kb
Host smart-28ccc8ad-bbd9-4826-9d97-6ffdebbce3fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3027146747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3027146747
Directory /workspace/19.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3040771280
Short name T329
Test name
Test status
Simulation time 444115395 ps
CPU time 3.82 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:11 PM PDT 24
Peak memory 207164 kb
Host smart-2b4aad1f-15c2-4b41-83b7-ca0bd7204cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3040771280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3040771280
Directory /workspace/19.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.4133349646
Short name T3117
Test name
Test status
Simulation time 132873443 ps
CPU time 3.27 seconds
Started Aug 02 05:00:46 PM PDT 24
Finished Aug 02 05:00:49 PM PDT 24
Peak memory 207200 kb
Host smart-af3af690-d01b-44d1-a6a4-94fbc23efd7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4133349646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.4133349646
Directory /workspace/2.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4092268593
Short name T273
Test name
Test status
Simulation time 654417732 ps
CPU time 7.83 seconds
Started Aug 02 05:00:42 PM PDT 24
Finished Aug 02 05:00:50 PM PDT 24
Peak memory 207128 kb
Host smart-d4830364-e59b-400e-bc5f-08aa62f3f435
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4092268593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4092268593
Directory /workspace/2.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1302880969
Short name T278
Test name
Test status
Simulation time 104207309 ps
CPU time 0.96 seconds
Started Aug 02 05:00:42 PM PDT 24
Finished Aug 02 05:00:44 PM PDT 24
Peak memory 207048 kb
Host smart-133fe77c-e18a-4303-aaac-e0c5d9984315
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1302880969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1302880969
Directory /workspace/2.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2673104693
Short name T3185
Test name
Test status
Simulation time 109079998 ps
CPU time 2.8 seconds
Started Aug 02 05:00:54 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 215484 kb
Host smart-c13bb76f-4875-470e-99f3-e8337ccf7830
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673104693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2673104693
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.957751267
Short name T3199
Test name
Test status
Simulation time 64437296 ps
CPU time 0.92 seconds
Started Aug 02 05:00:49 PM PDT 24
Finished Aug 02 05:00:50 PM PDT 24
Peak memory 207004 kb
Host smart-bad547c0-e020-4e20-9931-9e422cc3e39b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=957751267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.957751267
Directory /workspace/2.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.550143707
Short name T215
Test name
Test status
Simulation time 71301363 ps
CPU time 0.72 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 206872 kb
Host smart-ee1ef8b2-bdd8-4379-aad6-5531209b8111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=550143707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.550143707
Directory /workspace/2.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2777495377
Short name T3131
Test name
Test status
Simulation time 164097987 ps
CPU time 2.34 seconds
Started Aug 02 05:00:49 PM PDT 24
Finished Aug 02 05:00:52 PM PDT 24
Peak memory 207116 kb
Host smart-0c604a60-91f6-405d-8b6e-c6815fdd6bb1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2777495377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2777495377
Directory /workspace/2.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2699230930
Short name T3111
Test name
Test status
Simulation time 285153741 ps
CPU time 2.61 seconds
Started Aug 02 05:00:42 PM PDT 24
Finished Aug 02 05:00:45 PM PDT 24
Peak memory 207060 kb
Host smart-8f4d2937-59b0-49c6-8c22-086dc84f1e9e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2699230930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2699230930
Directory /workspace/2.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.923934554
Short name T282
Test name
Test status
Simulation time 328534707 ps
CPU time 1.71 seconds
Started Aug 02 05:00:52 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 207160 kb
Host smart-200bc4d0-baf5-4450-9ede-396bfdda4dbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=923934554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.923934554
Directory /workspace/2.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.102154561
Short name T3155
Test name
Test status
Simulation time 104987412 ps
CPU time 1.86 seconds
Started Aug 02 05:00:45 PM PDT 24
Finished Aug 02 05:00:47 PM PDT 24
Peak memory 215396 kb
Host smart-8a5e98d6-5c2d-40ac-a02b-2091e31170fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=102154561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.102154561
Directory /workspace/2.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.592420271
Short name T3168
Test name
Test status
Simulation time 416485235 ps
CPU time 3.02 seconds
Started Aug 02 05:00:52 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 207144 kb
Host smart-ab80a773-74d3-4e96-b17a-082b3db68bf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=592420271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.592420271
Directory /workspace/2.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3611132816
Short name T3212
Test name
Test status
Simulation time 57858615 ps
CPU time 0.72 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:07 PM PDT 24
Peak memory 206776 kb
Host smart-427bfc65-3ac1-41c4-8213-321cc32f5021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3611132816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3611132816
Directory /workspace/20.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.982689669
Short name T3207
Test name
Test status
Simulation time 59165934 ps
CPU time 0.72 seconds
Started Aug 02 05:01:05 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 206780 kb
Host smart-8cb4631f-3b73-4470-9cd6-eafb4b6ca45f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=982689669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.982689669
Directory /workspace/21.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.4197063696
Short name T3125
Test name
Test status
Simulation time 37833385 ps
CPU time 0.71 seconds
Started Aug 02 05:01:04 PM PDT 24
Finished Aug 02 05:01:05 PM PDT 24
Peak memory 206908 kb
Host smart-65cfb868-9978-438a-9353-92fff7eb035a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4197063696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.4197063696
Directory /workspace/22.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.213890887
Short name T3181
Test name
Test status
Simulation time 51890193 ps
CPU time 0.72 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:07 PM PDT 24
Peak memory 206888 kb
Host smart-e770047a-d8a9-478e-bce4-01b8f25d10b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=213890887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.213890887
Directory /workspace/23.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2774232143
Short name T216
Test name
Test status
Simulation time 69699142 ps
CPU time 0.72 seconds
Started Aug 02 05:01:01 PM PDT 24
Finished Aug 02 05:01:02 PM PDT 24
Peak memory 206848 kb
Host smart-551d9612-e0ae-4286-a61b-4d45f2eb30cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2774232143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2774232143
Directory /workspace/24.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4292699029
Short name T218
Test name
Test status
Simulation time 31766355 ps
CPU time 0.67 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 206884 kb
Host smart-35c549fb-4d21-416b-bd63-75ef73021506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4292699029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4292699029
Directory /workspace/25.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.3179843577
Short name T3151
Test name
Test status
Simulation time 48318353 ps
CPU time 0.71 seconds
Started Aug 02 05:01:11 PM PDT 24
Finished Aug 02 05:01:12 PM PDT 24
Peak memory 206780 kb
Host smart-cd22bb19-b7b0-42e1-98a3-6df306d3edf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3179843577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.3179843577
Directory /workspace/26.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2084787910
Short name T3113
Test name
Test status
Simulation time 41342580 ps
CPU time 0.73 seconds
Started Aug 02 05:01:04 PM PDT 24
Finished Aug 02 05:01:04 PM PDT 24
Peak memory 206908 kb
Host smart-c13b46d1-93f7-4a2c-8571-f64d2babb37f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2084787910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2084787910
Directory /workspace/27.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.617352704
Short name T3174
Test name
Test status
Simulation time 47232998 ps
CPU time 0.75 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 206816 kb
Host smart-e608fc6d-ff8d-4f60-89b3-f70814281525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=617352704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.617352704
Directory /workspace/28.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3457363677
Short name T3196
Test name
Test status
Simulation time 41347249 ps
CPU time 0.7 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:07 PM PDT 24
Peak memory 206776 kb
Host smart-ef2460d0-7083-4514-8109-45589b10b660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3457363677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3457363677
Directory /workspace/29.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2399486110
Short name T3211
Test name
Test status
Simulation time 163365098 ps
CPU time 1.99 seconds
Started Aug 02 05:00:55 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 207044 kb
Host smart-521cd6b6-47a8-400e-b37b-2a74ae9db9fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2399486110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2399486110
Directory /workspace/3.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3172903684
Short name T268
Test name
Test status
Simulation time 566864946 ps
CPU time 6.79 seconds
Started Aug 02 05:01:04 PM PDT 24
Finished Aug 02 05:01:11 PM PDT 24
Peak memory 207092 kb
Host smart-169e03da-c4ef-4e28-af9a-840cc1408ecb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3172903684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3172903684
Directory /workspace/3.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3710107328
Short name T271
Test name
Test status
Simulation time 316526234 ps
CPU time 1.21 seconds
Started Aug 02 05:01:00 PM PDT 24
Finished Aug 02 05:01:01 PM PDT 24
Peak memory 206988 kb
Host smart-428256a3-0f04-42f7-808a-9d7ef3dc10a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3710107328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3710107328
Directory /workspace/3.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3446233155
Short name T3146
Test name
Test status
Simulation time 98780060 ps
CPU time 1.36 seconds
Started Aug 02 05:00:52 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 215436 kb
Host smart-938ef9b4-9f6e-4f75-8e76-bdec96112d1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446233155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3446233155
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1127584292
Short name T3157
Test name
Test status
Simulation time 63740696 ps
CPU time 0.91 seconds
Started Aug 02 05:00:59 PM PDT 24
Finished Aug 02 05:01:00 PM PDT 24
Peak memory 206892 kb
Host smart-5cf89b72-72f9-4a3a-86de-c85817f1a5d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1127584292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1127584292
Directory /workspace/3.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3530419836
Short name T3154
Test name
Test status
Simulation time 48047786 ps
CPU time 0.75 seconds
Started Aug 02 05:00:49 PM PDT 24
Finished Aug 02 05:00:50 PM PDT 24
Peak memory 206868 kb
Host smart-685115d0-ac18-4ba2-8389-423adca7abf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3530419836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3530419836
Directory /workspace/3.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3106214278
Short name T3189
Test name
Test status
Simulation time 216972022 ps
CPU time 2.37 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 215432 kb
Host smart-3d6bba3b-8e23-4201-85d5-a7a22cf2902e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3106214278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3106214278
Directory /workspace/3.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3153737292
Short name T3116
Test name
Test status
Simulation time 168939077 ps
CPU time 3.84 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:01:00 PM PDT 24
Peak memory 207084 kb
Host smart-58bd1c62-c0ee-469c-bdba-b5bc516553dd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3153737292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3153737292
Directory /workspace/3.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.622468446
Short name T3180
Test name
Test status
Simulation time 363794805 ps
CPU time 1.98 seconds
Started Aug 02 05:00:51 PM PDT 24
Finished Aug 02 05:00:53 PM PDT 24
Peak memory 207176 kb
Host smart-479b6e45-e57d-48b1-a1d4-b6c0f45e829d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=622468446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.622468446
Directory /workspace/3.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.1060961909
Short name T3210
Test name
Test status
Simulation time 142370920 ps
CPU time 1.8 seconds
Started Aug 02 05:00:50 PM PDT 24
Finished Aug 02 05:00:53 PM PDT 24
Peak memory 219196 kb
Host smart-5667664d-608f-4244-a9f6-2a57426f9655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1060961909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.1060961909
Directory /workspace/3.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3430827388
Short name T3176
Test name
Test status
Simulation time 34539796 ps
CPU time 0.66 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:13 PM PDT 24
Peak memory 206844 kb
Host smart-0b53bcc0-97b1-49f9-9a9f-451fed6eaec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3430827388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3430827388
Directory /workspace/30.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.4069964296
Short name T219
Test name
Test status
Simulation time 105296829 ps
CPU time 0.77 seconds
Started Aug 02 05:01:09 PM PDT 24
Finished Aug 02 05:01:10 PM PDT 24
Peak memory 206892 kb
Host smart-6a738e11-90d3-42e2-9708-c0134bef8c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4069964296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.4069964296
Directory /workspace/31.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2930667614
Short name T324
Test name
Test status
Simulation time 49311237 ps
CPU time 0.7 seconds
Started Aug 02 05:01:03 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 206868 kb
Host smart-fe7693e1-74a7-4a4c-998a-649b9bf462ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2930667614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2930667614
Directory /workspace/32.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.628695644
Short name T297
Test name
Test status
Simulation time 41838836 ps
CPU time 0.72 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 206768 kb
Host smart-6820c3d9-544e-4829-9de1-ebd2e8842c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=628695644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.628695644
Directory /workspace/33.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3738765841
Short name T3144
Test name
Test status
Simulation time 114156068 ps
CPU time 0.83 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 206944 kb
Host smart-5909feab-ca84-4ba0-a5c1-f29a87aa4bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3738765841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3738765841
Directory /workspace/34.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.143526812
Short name T3121
Test name
Test status
Simulation time 54473866 ps
CPU time 0.74 seconds
Started Aug 02 05:01:05 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 206848 kb
Host smart-1df53602-45f2-43b8-ab80-74ae7b552c0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=143526812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.143526812
Directory /workspace/35.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.506059377
Short name T325
Test name
Test status
Simulation time 71054230 ps
CPU time 0.71 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:07 PM PDT 24
Peak memory 206916 kb
Host smart-da88f820-367a-4e40-873a-9a0189b89059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=506059377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.506059377
Directory /workspace/37.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.733390151
Short name T3127
Test name
Test status
Simulation time 55106166 ps
CPU time 0.74 seconds
Started Aug 02 05:01:04 PM PDT 24
Finished Aug 02 05:01:06 PM PDT 24
Peak memory 206832 kb
Host smart-7e430fbb-bcf2-44ce-9b52-2bd27c9fbf8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=733390151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.733390151
Directory /workspace/39.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.900373992
Short name T277
Test name
Test status
Simulation time 119582771 ps
CPU time 2.07 seconds
Started Aug 02 05:00:52 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 207148 kb
Host smart-36a51726-1815-4c23-b89c-76a391dd63dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=900373992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.900373992
Directory /workspace/4.usbdev_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.788609829
Short name T3188
Test name
Test status
Simulation time 528754295 ps
CPU time 7.77 seconds
Started Aug 02 05:00:52 PM PDT 24
Finished Aug 02 05:01:00 PM PDT 24
Peak memory 207020 kb
Host smart-52bf43a3-1876-46dc-9a54-04ccf34b9096
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=788609829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.788609829
Directory /workspace/4.usbdev_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2181107911
Short name T276
Test name
Test status
Simulation time 121955563 ps
CPU time 0.93 seconds
Started Aug 02 05:00:55 PM PDT 24
Finished Aug 02 05:00:56 PM PDT 24
Peak memory 206968 kb
Host smart-128177d8-64c5-4482-a1a3-dfc6de6ca987
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2181107911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2181107911
Directory /workspace/4.usbdev_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3474413955
Short name T208
Test name
Test status
Simulation time 49466582 ps
CPU time 1.23 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:01:00 PM PDT 24
Peak memory 215444 kb
Host smart-009befc2-7676-4389-8215-8820b6d1a622
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474413955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3474413955
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1811721335
Short name T284
Test name
Test status
Simulation time 91011996 ps
CPU time 0.86 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 206924 kb
Host smart-234f7323-95dc-49c8-8605-e965bb638aea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1811721335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1811721335
Directory /workspace/4.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.408834330
Short name T3128
Test name
Test status
Simulation time 45589742 ps
CPU time 0.73 seconds
Started Aug 02 05:00:51 PM PDT 24
Finished Aug 02 05:00:52 PM PDT 24
Peak memory 206848 kb
Host smart-01f7feb0-2b02-4da6-a5f1-420d48caea33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=408834330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.408834330
Directory /workspace/4.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1609284104
Short name T3164
Test name
Test status
Simulation time 196024714 ps
CPU time 2.45 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 215272 kb
Host smart-e4ab30d7-690a-40c5-9c58-c052278645cf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1609284104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1609284104
Directory /workspace/4.usbdev_mem_partial_access/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1131480285
Short name T3134
Test name
Test status
Simulation time 262124046 ps
CPU time 2.52 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:01:00 PM PDT 24
Peak memory 207128 kb
Host smart-7bc85ea0-3a70-46cb-acce-4853241583bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1131480285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1131480285
Directory /workspace/4.usbdev_mem_walk/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3394952234
Short name T293
Test name
Test status
Simulation time 201467024 ps
CPU time 1.65 seconds
Started Aug 02 05:00:52 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 207200 kb
Host smart-1067d826-56ce-430d-adf8-31cbecadf504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3394952234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3394952234
Directory /workspace/4.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3629054136
Short name T246
Test name
Test status
Simulation time 288764855 ps
CPU time 3.61 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:01:02 PM PDT 24
Peak memory 215464 kb
Host smart-ced36b67-ddeb-492e-bdfa-52e1e76be567
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3629054136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3629054136
Directory /workspace/4.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3511601099
Short name T206
Test name
Test status
Simulation time 258358313 ps
CPU time 2.36 seconds
Started Aug 02 05:00:55 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 207216 kb
Host smart-d85f61ba-f45d-48ec-a09d-87858056ca11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3511601099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3511601099
Directory /workspace/4.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.55895801
Short name T3115
Test name
Test status
Simulation time 70784549 ps
CPU time 0.79 seconds
Started Aug 02 05:01:08 PM PDT 24
Finished Aug 02 05:01:09 PM PDT 24
Peak memory 206828 kb
Host smart-5e0cf4ac-1c83-49eb-b62e-41fc08a9118b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=55895801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.55895801
Directory /workspace/40.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3695831054
Short name T3141
Test name
Test status
Simulation time 42927253 ps
CPU time 0.72 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:07 PM PDT 24
Peak memory 206776 kb
Host smart-cdef490d-6e9e-47e1-83b1-5f10021c50fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3695831054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3695831054
Directory /workspace/41.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2514735584
Short name T3148
Test name
Test status
Simulation time 34674567 ps
CPU time 0.7 seconds
Started Aug 02 05:01:07 PM PDT 24
Finished Aug 02 05:01:08 PM PDT 24
Peak memory 206760 kb
Host smart-6eaf6517-1c7b-48cb-b981-012c9bf3c1a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2514735584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2514735584
Directory /workspace/42.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.2793233108
Short name T213
Test name
Test status
Simulation time 70141970 ps
CPU time 0.71 seconds
Started Aug 02 05:01:04 PM PDT 24
Finished Aug 02 05:01:05 PM PDT 24
Peak memory 206864 kb
Host smart-eadb849f-8760-474d-942f-99c81e5ba630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2793233108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.2793233108
Directory /workspace/43.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4283371287
Short name T3112
Test name
Test status
Simulation time 47155671 ps
CPU time 0.68 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:07 PM PDT 24
Peak memory 206908 kb
Host smart-631cc8f0-1aa4-4387-ae06-9611db1dce1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4283371287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.4283371287
Directory /workspace/44.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.722521786
Short name T3142
Test name
Test status
Simulation time 33773103 ps
CPU time 0.7 seconds
Started Aug 02 05:01:08 PM PDT 24
Finished Aug 02 05:01:09 PM PDT 24
Peak memory 206768 kb
Host smart-46a34cf0-a7e0-44bc-89ee-b69f5d6ce8a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=722521786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.722521786
Directory /workspace/45.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.857887117
Short name T3119
Test name
Test status
Simulation time 70895145 ps
CPU time 0.74 seconds
Started Aug 02 05:01:09 PM PDT 24
Finished Aug 02 05:01:09 PM PDT 24
Peak memory 206892 kb
Host smart-10650858-4a16-4258-ad98-e03cdf4dc27d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=857887117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.857887117
Directory /workspace/46.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.285029093
Short name T3143
Test name
Test status
Simulation time 40841808 ps
CPU time 0.71 seconds
Started Aug 02 05:01:06 PM PDT 24
Finished Aug 02 05:01:07 PM PDT 24
Peak memory 206916 kb
Host smart-f59e1476-dc22-4448-bb83-c32915dea57f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=285029093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.285029093
Directory /workspace/47.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2994971112
Short name T298
Test name
Test status
Simulation time 57932994 ps
CPU time 0.72 seconds
Started Aug 02 05:01:02 PM PDT 24
Finished Aug 02 05:01:03 PM PDT 24
Peak memory 206868 kb
Host smart-8570f7ae-d97f-4f6f-8135-e1b1f69f39c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2994971112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2994971112
Directory /workspace/48.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1139172646
Short name T3195
Test name
Test status
Simulation time 86603262 ps
CPU time 1.22 seconds
Started Aug 02 05:00:54 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 215468 kb
Host smart-a2e50d92-1460-4b67-93ac-46f767eebb08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139172646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1139172646
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.201467136
Short name T3202
Test name
Test status
Simulation time 128164252 ps
CPU time 1.07 seconds
Started Aug 02 05:00:50 PM PDT 24
Finished Aug 02 05:00:51 PM PDT 24
Peak memory 206856 kb
Host smart-7244cdde-97ab-4633-b057-d04d7b2d2aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=201467136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.201467136
Directory /workspace/5.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.1128842445
Short name T3130
Test name
Test status
Simulation time 48820438 ps
CPU time 0.71 seconds
Started Aug 02 05:00:48 PM PDT 24
Finished Aug 02 05:00:49 PM PDT 24
Peak memory 206836 kb
Host smart-16efa4b6-ef12-49e4-a203-56621c9cb477
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1128842445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1128842445
Directory /workspace/5.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1004905861
Short name T294
Test name
Test status
Simulation time 204960422 ps
CPU time 1.6 seconds
Started Aug 02 05:00:55 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 207188 kb
Host smart-3af2a5ae-52a7-42d8-b3b3-894211907518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1004905861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1004905861
Directory /workspace/5.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.4075810208
Short name T236
Test name
Test status
Simulation time 77731893 ps
CPU time 1.71 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:00:59 PM PDT 24
Peak memory 207164 kb
Host smart-460d5cb1-c0a3-4ebf-958e-d05a4384dd82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4075810208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.4075810208
Directory /workspace/5.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.2524866268
Short name T232
Test name
Test status
Simulation time 782543837 ps
CPU time 2.84 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:59 PM PDT 24
Peak memory 207276 kb
Host smart-2f3b4573-3630-43b1-8072-a52b8b1825a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2524866268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.2524866268
Directory /workspace/5.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2474837053
Short name T3209
Test name
Test status
Simulation time 96461860 ps
CPU time 1.35 seconds
Started Aug 02 05:00:59 PM PDT 24
Finished Aug 02 05:01:01 PM PDT 24
Peak memory 215380 kb
Host smart-f3b7660b-00cd-46ce-8d77-53075a0a369d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474837053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2474837053
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2861459453
Short name T3129
Test name
Test status
Simulation time 61360192 ps
CPU time 1.02 seconds
Started Aug 02 05:00:52 PM PDT 24
Finished Aug 02 05:00:53 PM PDT 24
Peak memory 207056 kb
Host smart-de2cd0c6-51f3-43d1-912c-abb677fe9493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2861459453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2861459453
Directory /workspace/6.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1135281578
Short name T3153
Test name
Test status
Simulation time 58232085 ps
CPU time 0.72 seconds
Started Aug 02 05:00:50 PM PDT 24
Finished Aug 02 05:00:51 PM PDT 24
Peak memory 206812 kb
Host smart-0329582e-1e60-462b-b577-5a1bb0f44a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1135281578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1135281578
Directory /workspace/6.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3400074682
Short name T3192
Test name
Test status
Simulation time 112692899 ps
CPU time 1.16 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:00:59 PM PDT 24
Peak memory 207240 kb
Host smart-1a2b0146-c4fa-4af3-b3de-21b27b92cdf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3400074682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3400074682
Directory /workspace/6.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1753098318
Short name T249
Test name
Test status
Simulation time 188280615 ps
CPU time 2 seconds
Started Aug 02 05:00:54 PM PDT 24
Finished Aug 02 05:00:56 PM PDT 24
Peak memory 207188 kb
Host smart-17f159a4-ee5f-42c8-85e4-8b5217bcf047
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1753098318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1753098318
Directory /workspace/6.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3722651236
Short name T3160
Test name
Test status
Simulation time 502470499 ps
CPU time 2.64 seconds
Started Aug 02 05:00:55 PM PDT 24
Finished Aug 02 05:00:58 PM PDT 24
Peak memory 207204 kb
Host smart-daef9684-92a6-4316-82ba-7181780b4c1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3722651236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3722651236
Directory /workspace/6.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1817982438
Short name T3203
Test name
Test status
Simulation time 145907465 ps
CPU time 1.66 seconds
Started Aug 02 05:00:59 PM PDT 24
Finished Aug 02 05:01:01 PM PDT 24
Peak memory 219780 kb
Host smart-c0843b8b-d11f-41ed-a8d9-dab31c15f513
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817982438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1817982438
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2531726960
Short name T300
Test name
Test status
Simulation time 138033103 ps
CPU time 1.05 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 206972 kb
Host smart-be02e221-6b79-41d7-9173-9d854578a765
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2531726960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2531726960
Directory /workspace/7.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3459874059
Short name T3187
Test name
Test status
Simulation time 61073993 ps
CPU time 0.74 seconds
Started Aug 02 05:00:52 PM PDT 24
Finished Aug 02 05:00:53 PM PDT 24
Peak memory 206848 kb
Host smart-642f3ad1-87d7-464a-a1e1-6cec9cca6149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3459874059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3459874059
Directory /workspace/7.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1880169016
Short name T283
Test name
Test status
Simulation time 192214343 ps
CPU time 1.35 seconds
Started Aug 02 05:00:54 PM PDT 24
Finished Aug 02 05:00:56 PM PDT 24
Peak memory 207148 kb
Host smart-4980a8c7-4f08-4b08-8380-09c7e8d6482c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1880169016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1880169016
Directory /workspace/7.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1672813501
Short name T3194
Test name
Test status
Simulation time 695221375 ps
CPU time 2.98 seconds
Started Aug 02 05:00:51 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 207172 kb
Host smart-0309d93d-d816-4e2e-a80e-7617f781697b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1672813501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1672813501
Directory /workspace/7.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2196119476
Short name T3193
Test name
Test status
Simulation time 84044883 ps
CPU time 1.26 seconds
Started Aug 02 05:00:53 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 215292 kb
Host smart-38c436e3-acbf-49c1-a95d-ea89b1afdc05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196119476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2196119476
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3007740325
Short name T3201
Test name
Test status
Simulation time 63841057 ps
CPU time 0.87 seconds
Started Aug 02 05:00:52 PM PDT 24
Finished Aug 02 05:00:53 PM PDT 24
Peak memory 206896 kb
Host smart-18e95f38-d657-4038-9489-8c8bc9aab3f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3007740325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3007740325
Directory /workspace/8.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.873324551
Short name T3147
Test name
Test status
Simulation time 51838304 ps
CPU time 0.74 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 206968 kb
Host smart-5326c370-3e50-4df4-895a-00383d230091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=873324551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.873324551
Directory /workspace/8.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.962624289
Short name T3133
Test name
Test status
Simulation time 106138037 ps
CPU time 1.07 seconds
Started Aug 02 05:00:56 PM PDT 24
Finished Aug 02 05:00:57 PM PDT 24
Peak memory 207124 kb
Host smart-27d7042c-3055-449f-83a8-7d4b3412a39a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=962624289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.962624289
Directory /workspace/8.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.687714934
Short name T245
Test name
Test status
Simulation time 217069896 ps
CPU time 2.32 seconds
Started Aug 02 05:00:58 PM PDT 24
Finished Aug 02 05:01:00 PM PDT 24
Peak memory 207180 kb
Host smart-c1cf985c-7b42-4e76-aa87-5cced7e09802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=687714934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.687714934
Directory /workspace/8.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1591682929
Short name T332
Test name
Test status
Simulation time 1167965170 ps
CPU time 5.04 seconds
Started Aug 02 05:00:57 PM PDT 24
Finished Aug 02 05:01:02 PM PDT 24
Peak memory 207232 kb
Host smart-a8b31154-45b9-40cb-9cf6-20362dd32ce9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1591682929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1591682929
Directory /workspace/8.usbdev_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3645019939
Short name T3178
Test name
Test status
Simulation time 87921228 ps
CPU time 1.22 seconds
Started Aug 02 05:00:53 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 215444 kb
Host smart-68d193c9-aab0-47da-b947-fd2da180f6c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645019939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3645019939
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.3605079101
Short name T3150
Test name
Test status
Simulation time 127624954 ps
CPU time 0.9 seconds
Started Aug 02 05:00:53 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 206944 kb
Host smart-fc1b7a59-3f62-485e-9135-d8c5eac33013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3605079101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.3605079101
Directory /workspace/9.usbdev_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1459761646
Short name T3138
Test name
Test status
Simulation time 50485665 ps
CPU time 0.74 seconds
Started Aug 02 05:00:55 PM PDT 24
Finished Aug 02 05:00:56 PM PDT 24
Peak memory 206876 kb
Host smart-8afb7eb4-61ca-4d7f-ad32-def2dcb15014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1459761646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1459761646
Directory /workspace/9.usbdev_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3006277768
Short name T286
Test name
Test status
Simulation time 101785985 ps
CPU time 1.08 seconds
Started Aug 02 05:01:00 PM PDT 24
Finished Aug 02 05:01:01 PM PDT 24
Peak memory 207212 kb
Host smart-b3739c2a-0360-453c-9054-329911eea3f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3006277768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3006277768
Directory /workspace/9.usbdev_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3293558475
Short name T3165
Test name
Test status
Simulation time 85629355 ps
CPU time 2.3 seconds
Started Aug 02 05:00:53 PM PDT 24
Finished Aug 02 05:00:55 PM PDT 24
Peak memory 220680 kb
Host smart-8fc38cc1-ecf6-48f2-88e8-1e4229024ebb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3293558475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3293558475
Directory /workspace/9.usbdev_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3349325828
Short name T333
Test name
Test status
Simulation time 1080630071 ps
CPU time 4.59 seconds
Started Aug 02 05:00:49 PM PDT 24
Finished Aug 02 05:00:54 PM PDT 24
Peak memory 207172 kb
Host smart-07bbe181-cf3a-4ce5-a9b9-45cf840dae62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3349325828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3349325828
Directory /workspace/9.usbdev_tl_intg_err/latest


Test location /workspace/coverage/default/0.usbdev_alert_test.2894898940
Short name T2299
Test name
Test status
Simulation time 37860203 ps
CPU time 0.67 seconds
Started Aug 02 05:26:38 PM PDT 24
Finished Aug 02 05:26:39 PM PDT 24
Peak memory 207412 kb
Host smart-6747a3c8-f4a2-4e27-80bf-7efb9f97eb25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2894898940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2894898940
Directory /workspace/0.usbdev_alert_test/latest


Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1208344266
Short name T594
Test name
Test status
Simulation time 11382667410 ps
CPU time 14.53 seconds
Started Aug 02 05:25:49 PM PDT 24
Finished Aug 02 05:26:04 PM PDT 24
Peak memory 207652 kb
Host smart-5fd5bf52-c245-44e4-9ac1-824cada2b3e2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208344266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_disconnect.1208344266
Directory /workspace/0.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.2593643517
Short name T904
Test name
Test status
Simulation time 18833272942 ps
CPU time 21.39 seconds
Started Aug 02 05:25:48 PM PDT 24
Finished Aug 02 05:26:09 PM PDT 24
Peak memory 207612 kb
Host smart-ab9f5341-2135-4f84-b9ad-aa81fae5f589
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593643517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.2593643517
Directory /workspace/0.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2559790500
Short name T2911
Test name
Test status
Simulation time 28385668635 ps
CPU time 33.99 seconds
Started Aug 02 05:25:50 PM PDT 24
Finished Aug 02 05:26:24 PM PDT 24
Peak memory 207628 kb
Host smart-3e124305-8781-444e-9e2d-e324e195afdc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559790500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_ao
n_wake_resume.2559790500
Directory /workspace/0.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/0.usbdev_av_buffer.3079174308
Short name T1054
Test name
Test status
Simulation time 161045328 ps
CPU time 0.83 seconds
Started Aug 02 05:25:51 PM PDT 24
Finished Aug 02 05:25:52 PM PDT 24
Peak memory 207344 kb
Host smart-338ad95b-fe0b-40d9-bfe5-e5628d89735f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30791
74308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.3079174308
Directory /workspace/0.usbdev_av_buffer/latest


Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3110492064
Short name T1336
Test name
Test status
Simulation time 261058752 ps
CPU time 1.02 seconds
Started Aug 02 05:25:59 PM PDT 24
Finished Aug 02 05:26:00 PM PDT 24
Peak memory 207408 kb
Host smart-da2ebdef-29ef-4e1d-94b3-fa97cf59fd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31104
92064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3110492064
Directory /workspace/0.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.278885463
Short name T2012
Test name
Test status
Simulation time 678740353 ps
CPU time 1.7 seconds
Started Aug 02 05:25:59 PM PDT 24
Finished Aug 02 05:26:01 PM PDT 24
Peak memory 207468 kb
Host smart-9e270252-f84c-4aca-8cef-94fcda8ee33d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=278885463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.278885463
Directory /workspace/0.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/0.usbdev_device_address.4060458122
Short name T2028
Test name
Test status
Simulation time 19599146374 ps
CPU time 32.59 seconds
Started Aug 02 05:25:57 PM PDT 24
Finished Aug 02 05:26:30 PM PDT 24
Peak memory 207716 kb
Host smart-02657349-54e4-4295-bc63-a4bf39d75718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40604
58122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.4060458122
Directory /workspace/0.usbdev_device_address/latest


Test location /workspace/coverage/default/0.usbdev_device_timeout.1795292761
Short name T1207
Test name
Test status
Simulation time 4768863130 ps
CPU time 40.63 seconds
Started Aug 02 05:25:58 PM PDT 24
Finished Aug 02 05:26:39 PM PDT 24
Peak memory 207672 kb
Host smart-a620684a-215b-4242-a76c-8d2afdb7b30b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795292761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_timeout.1795292761
Directory /workspace/0.usbdev_device_timeout/latest


Test location /workspace/coverage/default/0.usbdev_disable_endpoint.4268777936
Short name T1685
Test name
Test status
Simulation time 891386554 ps
CPU time 1.86 seconds
Started Aug 02 05:25:58 PM PDT 24
Finished Aug 02 05:26:00 PM PDT 24
Peak memory 207360 kb
Host smart-0571613d-c681-48b7-b65c-9ee56b19f319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42687
77936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.4268777936
Directory /workspace/0.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/0.usbdev_disconnected.1362195846
Short name T2282
Test name
Test status
Simulation time 162346274 ps
CPU time 0.82 seconds
Started Aug 02 05:25:58 PM PDT 24
Finished Aug 02 05:25:59 PM PDT 24
Peak memory 207376 kb
Host smart-451cbe13-75ef-499b-bd65-5f5866ce9375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13621
95846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1362195846
Directory /workspace/0.usbdev_disconnected/latest


Test location /workspace/coverage/default/0.usbdev_enable.1443191782
Short name T1879
Test name
Test status
Simulation time 31245464 ps
CPU time 0.67 seconds
Started Aug 02 05:25:57 PM PDT 24
Finished Aug 02 05:25:58 PM PDT 24
Peak memory 207384 kb
Host smart-adf89dad-4759-49ea-b6f7-fbc2c96c52e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14431
91782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1443191782
Directory /workspace/0.usbdev_enable/latest


Test location /workspace/coverage/default/0.usbdev_endpoint_access.2665869297
Short name T2205
Test name
Test status
Simulation time 1009469828 ps
CPU time 2.56 seconds
Started Aug 02 05:26:00 PM PDT 24
Finished Aug 02 05:26:03 PM PDT 24
Peak memory 207532 kb
Host smart-55bfa6fc-a226-48c3-bd47-a2224902e9ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26658
69297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2665869297
Directory /workspace/0.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3567892779
Short name T1709
Test name
Test status
Simulation time 110188141382 ps
CPU time 156.9 seconds
Started Aug 02 05:26:12 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 207636 kb
Host smart-499a8083-43b2-4fe5-a75d-6ebed48580c9
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3567892779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3567892779
Directory /workspace/0.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2997059718
Short name T2774
Test name
Test status
Simulation time 84231046161 ps
CPU time 130.66 seconds
Started Aug 02 05:26:08 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 207644 kb
Host smart-69e6a575-dbac-4265-8357-6539ddd23318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997059718 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2997059718
Directory /workspace/0.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/0.usbdev_freq_loclk.2816844932
Short name T2955
Test name
Test status
Simulation time 116095793385 ps
CPU time 180.43 seconds
Started Aug 02 05:26:08 PM PDT 24
Finished Aug 02 05:29:09 PM PDT 24
Peak memory 207672 kb
Host smart-a56de2c2-ed57-4018-942a-b70750b14af1
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2816844932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.2816844932
Directory /workspace/0.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.2716365414
Short name T2644
Test name
Test status
Simulation time 97169498729 ps
CPU time 152.1 seconds
Started Aug 02 05:26:09 PM PDT 24
Finished Aug 02 05:28:41 PM PDT 24
Peak memory 207700 kb
Host smart-8e471468-4e40-4d98-9d5f-9d540955ef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716365414 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.2716365414
Directory /workspace/0.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/0.usbdev_freq_phase.1850031320
Short name T2442
Test name
Test status
Simulation time 81143215182 ps
CPU time 127.85 seconds
Started Aug 02 05:26:07 PM PDT 24
Finished Aug 02 05:28:15 PM PDT 24
Peak memory 207676 kb
Host smart-43cb5b7c-f4c3-4457-b266-698f5072367f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18500
31320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.1850031320
Directory /workspace/0.usbdev_freq_phase/latest


Test location /workspace/coverage/default/0.usbdev_in_iso.2391579797
Short name T2034
Test name
Test status
Simulation time 153124350 ps
CPU time 0.92 seconds
Started Aug 02 05:26:08 PM PDT 24
Finished Aug 02 05:26:09 PM PDT 24
Peak memory 207384 kb
Host smart-45720f3f-0b65-4a4a-b829-7a311fb17723
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2391579797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2391579797
Directory /workspace/0.usbdev_in_iso/latest


Test location /workspace/coverage/default/0.usbdev_in_stall.1660540922
Short name T660
Test name
Test status
Simulation time 170463492 ps
CPU time 0.81 seconds
Started Aug 02 05:26:06 PM PDT 24
Finished Aug 02 05:26:07 PM PDT 24
Peak memory 207380 kb
Host smart-17f62bf2-36e5-492a-ba8b-3b42d82e6cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16605
40922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1660540922
Directory /workspace/0.usbdev_in_stall/latest


Test location /workspace/coverage/default/0.usbdev_in_trans.3799345246
Short name T1596
Test name
Test status
Simulation time 228899799 ps
CPU time 0.98 seconds
Started Aug 02 05:26:08 PM PDT 24
Finished Aug 02 05:26:09 PM PDT 24
Peak memory 207372 kb
Host smart-b8f9b6f8-0f40-4568-babd-fdeaec6accd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37993
45246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.3799345246
Directory /workspace/0.usbdev_in_trans/latest


Test location /workspace/coverage/default/0.usbdev_invalid_sync.490746876
Short name T2664
Test name
Test status
Simulation time 3291787370 ps
CPU time 91.51 seconds
Started Aug 02 05:26:08 PM PDT 24
Finished Aug 02 05:27:39 PM PDT 24
Peak memory 218468 kb
Host smart-c3936eb9-6e90-40cc-bf98-6de4bcec10f5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=490746876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.490746876
Directory /workspace/0.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/0.usbdev_iso_retraction.1645163014
Short name T64
Test name
Test status
Simulation time 10193407053 ps
CPU time 116.18 seconds
Started Aug 02 05:26:06 PM PDT 24
Finished Aug 02 05:28:03 PM PDT 24
Peak memory 207652 kb
Host smart-ad3e3398-5ead-4a70-b926-b36463ea1888
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1645163014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1645163014
Directory /workspace/0.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/0.usbdev_link_in_err.974413308
Short name T2387
Test name
Test status
Simulation time 207117752 ps
CPU time 0.9 seconds
Started Aug 02 05:26:04 PM PDT 24
Finished Aug 02 05:26:06 PM PDT 24
Peak memory 207328 kb
Host smart-62be7c4e-d6f1-45ab-b140-a8e3daf5f214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97441
3308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.974413308
Directory /workspace/0.usbdev_link_in_err/latest


Test location /workspace/coverage/default/0.usbdev_link_out_err.2569757006
Short name T71
Test name
Test status
Simulation time 539685938 ps
CPU time 1.47 seconds
Started Aug 02 05:26:06 PM PDT 24
Finished Aug 02 05:26:07 PM PDT 24
Peak memory 207432 kb
Host smart-3cacaaf4-83ad-48fe-8afd-831a3d268635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25697
57006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.2569757006
Directory /workspace/0.usbdev_link_out_err/latest


Test location /workspace/coverage/default/0.usbdev_link_resume.2769004477
Short name T1043
Test name
Test status
Simulation time 32641511517 ps
CPU time 45.52 seconds
Started Aug 02 05:26:06 PM PDT 24
Finished Aug 02 05:26:51 PM PDT 24
Peak memory 207676 kb
Host smart-2a064816-f1a0-44de-8cde-0a0df1f8ff54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27690
04477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2769004477
Directory /workspace/0.usbdev_link_resume/latest


Test location /workspace/coverage/default/0.usbdev_link_suspend.1924917532
Short name T2592
Test name
Test status
Simulation time 9626113946 ps
CPU time 11.2 seconds
Started Aug 02 05:26:04 PM PDT 24
Finished Aug 02 05:26:16 PM PDT 24
Peak memory 207692 kb
Host smart-163661a8-7610-46b8-b113-c69e05df1d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19249
17532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.1924917532
Directory /workspace/0.usbdev_link_suspend/latest


Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3762726438
Short name T1079
Test name
Test status
Simulation time 3115226223 ps
CPU time 28.91 seconds
Started Aug 02 05:26:06 PM PDT 24
Finished Aug 02 05:26:35 PM PDT 24
Peak memory 224056 kb
Host smart-995da2f6-31c9-4b39-872e-efb443918c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37627
26438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3762726438
Directory /workspace/0.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3764131666
Short name T2375
Test name
Test status
Simulation time 4011990795 ps
CPU time 31.56 seconds
Started Aug 02 05:26:06 PM PDT 24
Finished Aug 02 05:26:38 PM PDT 24
Peak memory 215828 kb
Host smart-8fb5b6dc-acd9-4b5c-8e71-6636d0619883
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3764131666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3764131666
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.487401477
Short name T727
Test name
Test status
Simulation time 252330001 ps
CPU time 1.03 seconds
Started Aug 02 05:26:07 PM PDT 24
Finished Aug 02 05:26:09 PM PDT 24
Peak memory 207408 kb
Host smart-c5676620-0e70-4bf0-affe-4e8fa3462f46
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=487401477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.487401477
Directory /workspace/0.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.3919473550
Short name T2556
Test name
Test status
Simulation time 205893725 ps
CPU time 0.96 seconds
Started Aug 02 05:26:07 PM PDT 24
Finished Aug 02 05:26:08 PM PDT 24
Peak memory 207400 kb
Host smart-a26ed703-7677-459c-bbed-9a061ef2e663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39194
73550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.3919473550
Directory /workspace/0.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_max_non_iso_usb_traffic.510422935
Short name T2425
Test name
Test status
Simulation time 3699699263 ps
CPU time 106.6 seconds
Started Aug 02 05:26:08 PM PDT 24
Finished Aug 02 05:27:55 PM PDT 24
Peak memory 217656 kb
Host smart-2e3b9fbf-823b-4d9e-b21c-9fdd4b5c13f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51042
2935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_non_iso_usb_traffic.510422935
Directory /workspace/0.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2830460512
Short name T2549
Test name
Test status
Simulation time 3137414736 ps
CPU time 91.78 seconds
Started Aug 02 05:26:15 PM PDT 24
Finished Aug 02 05:27:46 PM PDT 24
Peak memory 218016 kb
Host smart-e3870fa0-7648-4983-9943-4f6cae00c273
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2830460512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2830460512
Directory /workspace/0.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3071576362
Short name T560
Test name
Test status
Simulation time 1821906873 ps
CPU time 49.92 seconds
Started Aug 02 05:26:15 PM PDT 24
Finished Aug 02 05:27:05 PM PDT 24
Peak memory 215660 kb
Host smart-6a51bf1a-aa68-4ac7-ac54-d1e0114ea25e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3071576362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3071576362
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1358848409
Short name T1064
Test name
Test status
Simulation time 181281584 ps
CPU time 0.87 seconds
Started Aug 02 05:26:14 PM PDT 24
Finished Aug 02 05:26:15 PM PDT 24
Peak memory 207352 kb
Host smart-ac9eee4b-2226-44b6-ab7c-53a1835bec67
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1358848409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1358848409
Directory /workspace/0.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2603640236
Short name T1992
Test name
Test status
Simulation time 185338508 ps
CPU time 0.87 seconds
Started Aug 02 05:26:14 PM PDT 24
Finished Aug 02 05:26:15 PM PDT 24
Peak memory 207312 kb
Host smart-763741e7-7e4e-43b5-a036-a45da91c63f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26036
40236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2603640236
Directory /workspace/0.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3543315065
Short name T69
Test name
Test status
Simulation time 427048773 ps
CPU time 1.36 seconds
Started Aug 02 05:26:14 PM PDT 24
Finished Aug 02 05:26:16 PM PDT 24
Peak memory 207296 kb
Host smart-5ea4665c-0e57-48b6-9aef-72bb59399288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35433
15065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3543315065
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest


Test location /workspace/coverage/default/0.usbdev_out_iso.2415307440
Short name T1383
Test name
Test status
Simulation time 148232849 ps
CPU time 0.87 seconds
Started Aug 02 05:26:15 PM PDT 24
Finished Aug 02 05:26:16 PM PDT 24
Peak memory 207320 kb
Host smart-419ba2a1-1ce3-4e61-8067-5bdc7da85b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24153
07440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2415307440
Directory /workspace/0.usbdev_out_iso/latest


Test location /workspace/coverage/default/0.usbdev_out_stall.3534892453
Short name T2832
Test name
Test status
Simulation time 143476539 ps
CPU time 0.8 seconds
Started Aug 02 05:26:11 PM PDT 24
Finished Aug 02 05:26:12 PM PDT 24
Peak memory 207400 kb
Host smart-fad7b225-801a-42d6-98c6-6cf29062cd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35348
92453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.3534892453
Directory /workspace/0.usbdev_out_stall/latest


Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1596207392
Short name T1913
Test name
Test status
Simulation time 175868250 ps
CPU time 0.91 seconds
Started Aug 02 05:26:14 PM PDT 24
Finished Aug 02 05:26:15 PM PDT 24
Peak memory 207360 kb
Host smart-c8d8e078-e9d1-46a5-b388-451f49cfcd72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15962
07392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1596207392
Directory /workspace/0.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2754572201
Short name T3077
Test name
Test status
Simulation time 226799667 ps
CPU time 1 seconds
Started Aug 02 05:26:16 PM PDT 24
Finished Aug 02 05:26:17 PM PDT 24
Peak memory 207408 kb
Host smart-e916bd49-0b90-469a-a38f-7d122085f3b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27545
72201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2754572201
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.675670348
Short name T2389
Test name
Test status
Simulation time 224793499 ps
CPU time 0.97 seconds
Started Aug 02 05:26:13 PM PDT 24
Finished Aug 02 05:26:14 PM PDT 24
Peak memory 207384 kb
Host smart-deb20c18-f942-4d9f-bf35-c32b6a8212ad
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=675670348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.675670348
Directory /workspace/0.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.3884231582
Short name T211
Test name
Test status
Simulation time 245025134 ps
CPU time 1.07 seconds
Started Aug 02 05:26:13 PM PDT 24
Finished Aug 02 05:26:15 PM PDT 24
Peak memory 207432 kb
Host smart-e60a63ab-c8b5-4576-81cd-6fd03fb9c2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842
31582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.3884231582
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1798810014
Short name T991
Test name
Test status
Simulation time 193170702 ps
CPU time 1.04 seconds
Started Aug 02 05:26:13 PM PDT 24
Finished Aug 02 05:26:14 PM PDT 24
Peak memory 207324 kb
Host smart-c88209b4-8cbb-4aa1-8e25-2f1ee6940e07
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1798810014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1798810014
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.1432826021
Short name T210
Test name
Test status
Simulation time 208911195 ps
CPU time 1.04 seconds
Started Aug 02 05:26:17 PM PDT 24
Finished Aug 02 05:26:18 PM PDT 24
Peak memory 207396 kb
Host smart-e840bcf4-831a-45ce-ab78-16bcac4ff8b1
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1432826021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.1432826021
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest


Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.4146421760
Short name T1584
Test name
Test status
Simulation time 155159727 ps
CPU time 0.8 seconds
Started Aug 02 05:26:19 PM PDT 24
Finished Aug 02 05:26:20 PM PDT 24
Peak memory 207304 kb
Host smart-5b85c3ce-cb55-4440-bc4e-a741f7b00119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464
21760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.4146421760
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2204007231
Short name T2411
Test name
Test status
Simulation time 38105149 ps
CPU time 0.67 seconds
Started Aug 02 05:26:21 PM PDT 24
Finished Aug 02 05:26:22 PM PDT 24
Peak memory 207340 kb
Host smart-62e97381-a5b1-49cb-86f3-d6c83ac06ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22040
07231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2204007231
Directory /workspace/0.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/0.usbdev_pkt_buffer.4035589718
Short name T1888
Test name
Test status
Simulation time 19093216908 ps
CPU time 46.35 seconds
Started Aug 02 05:26:20 PM PDT 24
Finished Aug 02 05:27:07 PM PDT 24
Peak memory 215856 kb
Host smart-2a687835-d45e-4f41-9742-367edda67c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40355
89718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.4035589718
Directory /workspace/0.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/0.usbdev_pkt_received.2487694063
Short name T1696
Test name
Test status
Simulation time 151846858 ps
CPU time 0.85 seconds
Started Aug 02 05:26:25 PM PDT 24
Finished Aug 02 05:26:26 PM PDT 24
Peak memory 207156 kb
Host smart-71c307e4-ed1e-4bc6-a366-48381c46360a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24876
94063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2487694063
Directory /workspace/0.usbdev_pkt_received/latest


Test location /workspace/coverage/default/0.usbdev_pkt_sent.1454039538
Short name T745
Test name
Test status
Simulation time 214529184 ps
CPU time 0.94 seconds
Started Aug 02 05:26:25 PM PDT 24
Finished Aug 02 05:26:26 PM PDT 24
Peak memory 207424 kb
Host smart-335279db-9c18-4ec4-8ea6-ccf95c98e0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14540
39538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1454039538
Directory /workspace/0.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.415780873
Short name T548
Test name
Test status
Simulation time 2071454063 ps
CPU time 15.1 seconds
Started Aug 02 05:26:26 PM PDT 24
Finished Aug 02 05:26:41 PM PDT 24
Peak memory 223976 kb
Host smart-345542dd-054b-4069-b50d-66c25b571866
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=415780873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.415780873
Directory /workspace/0.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.4166344584
Short name T1391
Test name
Test status
Simulation time 2872662872 ps
CPU time 16.45 seconds
Started Aug 02 05:26:19 PM PDT 24
Finished Aug 02 05:26:36 PM PDT 24
Peak memory 217900 kb
Host smart-41cdd6c8-5a1e-44b0-a828-b2e89fe48274
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4166344584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.4166344584
Directory /workspace/0.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/0.usbdev_rand_suspends.3843143201
Short name T1433
Test name
Test status
Simulation time 7090502650 ps
CPU time 37.38 seconds
Started Aug 02 05:26:20 PM PDT 24
Finished Aug 02 05:26:58 PM PDT 24
Peak memory 219120 kb
Host smart-a82e4ddd-1a77-4785-8347-da4e2ceeafd8
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843143201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3843143201
Directory /workspace/0.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.4100137354
Short name T2331
Test name
Test status
Simulation time 197277119 ps
CPU time 0.93 seconds
Started Aug 02 05:26:22 PM PDT 24
Finished Aug 02 05:26:23 PM PDT 24
Peak memory 207368 kb
Host smart-e17a8f76-b80e-4013-8d33-09dd79a5fb57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41001
37354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.4100137354
Directory /workspace/0.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3618564490
Short name T1395
Test name
Test status
Simulation time 197667904 ps
CPU time 1 seconds
Started Aug 02 05:26:25 PM PDT 24
Finished Aug 02 05:26:26 PM PDT 24
Peak memory 207204 kb
Host smart-b3fffe90-4df6-4e95-a866-f9a711e247a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36185
64490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3618564490
Directory /workspace/0.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/0.usbdev_resume_link_active.2998847063
Short name T810
Test name
Test status
Simulation time 20211689086 ps
CPU time 23.42 seconds
Started Aug 02 05:26:24 PM PDT 24
Finished Aug 02 05:26:48 PM PDT 24
Peak memory 207508 kb
Host smart-e6174846-d10e-4d5a-9567-c2614f1dac4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29988
47063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.2998847063
Directory /workspace/0.usbdev_resume_link_active/latest


Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2481488093
Short name T240
Test name
Test status
Simulation time 160176833 ps
CPU time 0.82 seconds
Started Aug 02 05:26:22 PM PDT 24
Finished Aug 02 05:26:23 PM PDT 24
Peak memory 207436 kb
Host smart-50291927-a912-4619-8fe3-9fca6bbc0538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24814
88093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2481488093
Directory /workspace/0.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/0.usbdev_rx_full.149991886
Short name T2812
Test name
Test status
Simulation time 371565812 ps
CPU time 1.19 seconds
Started Aug 02 05:26:19 PM PDT 24
Finished Aug 02 05:26:20 PM PDT 24
Peak memory 207328 kb
Host smart-53dd8294-b9bd-439f-8d8b-8c254adb97fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14999
1886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.149991886
Directory /workspace/0.usbdev_rx_full/latest


Test location /workspace/coverage/default/0.usbdev_sec_cm.1527749649
Short name T204
Test name
Test status
Simulation time 235855319 ps
CPU time 1.05 seconds
Started Aug 02 05:26:35 PM PDT 24
Finished Aug 02 05:26:36 PM PDT 24
Peak memory 223368 kb
Host smart-6568091b-d8a5-4a08-b85f-a21fb80b4d38
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1527749649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.1527749649
Directory /workspace/0.usbdev_sec_cm/latest


Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.2215353707
Short name T2475
Test name
Test status
Simulation time 300478432 ps
CPU time 1.11 seconds
Started Aug 02 05:26:29 PM PDT 24
Finished Aug 02 05:26:31 PM PDT 24
Peak memory 207392 kb
Host smart-0b52d43a-006a-491a-b37b-bf50972a5d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22153
53707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.2215353707
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/0.usbdev_setup_stage.2337629220
Short name T2738
Test name
Test status
Simulation time 154868981 ps
CPU time 0.85 seconds
Started Aug 02 05:26:28 PM PDT 24
Finished Aug 02 05:26:29 PM PDT 24
Peak memory 207372 kb
Host smart-2c5936fc-50d6-427b-bdc9-1fc0af442972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23376
29220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2337629220
Directory /workspace/0.usbdev_setup_stage/latest


Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3603980244
Short name T2865
Test name
Test status
Simulation time 180528529 ps
CPU time 0.91 seconds
Started Aug 02 05:26:29 PM PDT 24
Finished Aug 02 05:26:30 PM PDT 24
Peak memory 207328 kb
Host smart-76b6783d-cf42-4628-9686-8a8e1cdb9cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36039
80244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3603980244
Directory /workspace/0.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/0.usbdev_smoke.3715207013
Short name T2649
Test name
Test status
Simulation time 192368847 ps
CPU time 1 seconds
Started Aug 02 05:26:31 PM PDT 24
Finished Aug 02 05:26:32 PM PDT 24
Peak memory 207404 kb
Host smart-37edb1ed-aeb9-4fd7-bc48-38a9f1c134f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37152
07013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3715207013
Directory /workspace/0.usbdev_smoke/latest


Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.746891689
Short name T1464
Test name
Test status
Simulation time 3557116743 ps
CPU time 25.94 seconds
Started Aug 02 05:26:29 PM PDT 24
Finished Aug 02 05:26:55 PM PDT 24
Peak memory 224036 kb
Host smart-6b447ae1-42bc-46aa-baf8-362623b03309
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=746891689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.746891689
Directory /workspace/0.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.1651849889
Short name T1818
Test name
Test status
Simulation time 208793619 ps
CPU time 0.86 seconds
Started Aug 02 05:26:28 PM PDT 24
Finished Aug 02 05:26:29 PM PDT 24
Peak memory 207396 kb
Host smart-c5527f42-1e7d-43b4-b807-27244f169f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16518
49889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.1651849889
Directory /workspace/0.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/0.usbdev_stall_trans.2013846241
Short name T1726
Test name
Test status
Simulation time 218728656 ps
CPU time 0.94 seconds
Started Aug 02 05:26:29 PM PDT 24
Finished Aug 02 05:26:30 PM PDT 24
Peak memory 207340 kb
Host smart-3ea97cd2-90b4-4fa1-81dc-12e46bcef5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20138
46241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2013846241
Directory /workspace/0.usbdev_stall_trans/latest


Test location /workspace/coverage/default/0.usbdev_stream_len_max.1389677613
Short name T717
Test name
Test status
Simulation time 1178519454 ps
CPU time 2.9 seconds
Started Aug 02 05:26:28 PM PDT 24
Finished Aug 02 05:26:31 PM PDT 24
Peak memory 207608 kb
Host smart-c5da6364-f761-4c3b-902c-3b2387f8cbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13896
77613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1389677613
Directory /workspace/0.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/0.usbdev_streaming_out.2607783754
Short name T2970
Test name
Test status
Simulation time 4055042302 ps
CPU time 41.98 seconds
Started Aug 02 05:26:29 PM PDT 24
Finished Aug 02 05:27:11 PM PDT 24
Peak memory 215876 kb
Host smart-19c36167-af59-40dd-bd3a-a7baaa1c1a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26077
83754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2607783754
Directory /workspace/0.usbdev_streaming_out/latest


Test location /workspace/coverage/default/0.usbdev_timeout_missing_host_handshake.2283260441
Short name T1342
Test name
Test status
Simulation time 3373044679 ps
CPU time 30.18 seconds
Started Aug 02 05:25:59 PM PDT 24
Finished Aug 02 05:26:29 PM PDT 24
Peak memory 207588 kb
Host smart-a041c416-1283-481a-b44e-25d6017c0875
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283260441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_timeout_missing_host
_handshake.2283260441
Directory /workspace/0.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/1.usbdev_alert_test.2199170228
Short name T2196
Test name
Test status
Simulation time 102823901 ps
CPU time 0.74 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:08 PM PDT 24
Peak memory 207460 kb
Host smart-7f446a76-4749-43c3-a3c7-0ccd2b71efab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2199170228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2199170228
Directory /workspace/1.usbdev_alert_test/latest


Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.4126417298
Short name T1599
Test name
Test status
Simulation time 10595747341 ps
CPU time 15.66 seconds
Started Aug 02 05:26:36 PM PDT 24
Finished Aug 02 05:26:52 PM PDT 24
Peak memory 207672 kb
Host smart-fe3779d4-40b6-431f-92e3-6c199ebad0cd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126417298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_ao
n_wake_disconnect.4126417298
Directory /workspace/1.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1652143118
Short name T1954
Test name
Test status
Simulation time 19851560154 ps
CPU time 25.25 seconds
Started Aug 02 05:26:37 PM PDT 24
Finished Aug 02 05:27:02 PM PDT 24
Peak memory 207664 kb
Host smart-2aba8516-0ccb-4664-a87b-26988b7d800d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652143118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1652143118
Directory /workspace/1.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.477961244
Short name T118
Test name
Test status
Simulation time 25314089857 ps
CPU time 27.79 seconds
Started Aug 02 05:26:38 PM PDT 24
Finished Aug 02 05:27:05 PM PDT 24
Peak memory 215836 kb
Host smart-c47657d7-8c2d-4a83-9a41-a4a8994c5b69
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477961244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon
_wake_resume.477961244
Directory /workspace/1.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/1.usbdev_av_buffer.1302614058
Short name T2529
Test name
Test status
Simulation time 166115310 ps
CPU time 0.87 seconds
Started Aug 02 05:26:35 PM PDT 24
Finished Aug 02 05:26:36 PM PDT 24
Peak memory 207380 kb
Host smart-f7a8ec73-d345-4a21-adf1-3f12c28ac6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13026
14058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1302614058
Directory /workspace/1.usbdev_av_buffer/latest


Test location /workspace/coverage/default/1.usbdev_av_empty.4126694917
Short name T55
Test name
Test status
Simulation time 146735538 ps
CPU time 0.86 seconds
Started Aug 02 05:26:39 PM PDT 24
Finished Aug 02 05:26:40 PM PDT 24
Peak memory 207320 kb
Host smart-3e263705-b560-4211-8145-3afed1db634f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41266
94917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.4126694917
Directory /workspace/1.usbdev_av_empty/latest


Test location /workspace/coverage/default/1.usbdev_av_overflow.3848849138
Short name T104
Test name
Test status
Simulation time 131319836 ps
CPU time 0.82 seconds
Started Aug 02 05:26:34 PM PDT 24
Finished Aug 02 05:26:35 PM PDT 24
Peak memory 206788 kb
Host smart-5556fdd6-4fb1-4221-ac24-9515bfa61fc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38488
49138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.3848849138
Directory /workspace/1.usbdev_av_overflow/latest


Test location /workspace/coverage/default/1.usbdev_bitstuff_err.762094904
Short name T2294
Test name
Test status
Simulation time 164055543 ps
CPU time 0.85 seconds
Started Aug 02 05:26:39 PM PDT 24
Finished Aug 02 05:26:40 PM PDT 24
Peak memory 207288 kb
Host smart-65cebe94-1271-45fe-8881-26106bbb5387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76209
4904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.762094904
Directory /workspace/1.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.3958038384
Short name T2490
Test name
Test status
Simulation time 287759625 ps
CPU time 1.23 seconds
Started Aug 02 05:26:40 PM PDT 24
Finished Aug 02 05:26:41 PM PDT 24
Peak memory 207400 kb
Host smart-5058c6ca-0600-497f-a186-e1f9a0104206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39580
38384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.3958038384
Directory /workspace/1.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.1902194431
Short name T3098
Test name
Test status
Simulation time 891375470 ps
CPU time 2.27 seconds
Started Aug 02 05:26:36 PM PDT 24
Finished Aug 02 05:26:39 PM PDT 24
Peak memory 207640 kb
Host smart-01920715-38c0-47de-aff0-317a61d6e736
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1902194431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.1902194431
Directory /workspace/1.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/1.usbdev_device_address.3720397783
Short name T1335
Test name
Test status
Simulation time 21269554100 ps
CPU time 34.65 seconds
Started Aug 02 05:26:35 PM PDT 24
Finished Aug 02 05:27:10 PM PDT 24
Peak memory 207668 kb
Host smart-b156d241-61a1-4a10-9168-9e362ff1f529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37203
97783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.3720397783
Directory /workspace/1.usbdev_device_address/latest


Test location /workspace/coverage/default/1.usbdev_device_timeout.499056397
Short name T2489
Test name
Test status
Simulation time 2922083672 ps
CPU time 25.99 seconds
Started Aug 02 05:26:34 PM PDT 24
Finished Aug 02 05:27:00 PM PDT 24
Peak memory 207696 kb
Host smart-767b6068-d4d7-4fac-a639-fc2c400fcba1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499056397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_timeout.499056397
Directory /workspace/1.usbdev_device_timeout/latest


Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2640711161
Short name T2010
Test name
Test status
Simulation time 983491386 ps
CPU time 1.94 seconds
Started Aug 02 05:26:37 PM PDT 24
Finished Aug 02 05:26:39 PM PDT 24
Peak memory 207296 kb
Host smart-ec3bec23-fa8b-4fc2-846d-254d5b957c83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26407
11161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2640711161
Directory /workspace/1.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/1.usbdev_disconnected.1445791657
Short name T1702
Test name
Test status
Simulation time 141150600 ps
CPU time 0.77 seconds
Started Aug 02 05:26:35 PM PDT 24
Finished Aug 02 05:26:36 PM PDT 24
Peak memory 207380 kb
Host smart-3f3c5f30-1ac0-43a1-82e4-049073ee61e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14457
91657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1445791657
Directory /workspace/1.usbdev_disconnected/latest


Test location /workspace/coverage/default/1.usbdev_enable.1573939823
Short name T2924
Test name
Test status
Simulation time 37591146 ps
CPU time 0.68 seconds
Started Aug 02 05:26:39 PM PDT 24
Finished Aug 02 05:26:40 PM PDT 24
Peak memory 207360 kb
Host smart-5d830ffb-897a-4699-80fd-7cd428fa54ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15739
39823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.1573939823
Directory /workspace/1.usbdev_enable/latest


Test location /workspace/coverage/default/1.usbdev_endpoint_access.2098554834
Short name T2919
Test name
Test status
Simulation time 962469932 ps
CPU time 2.31 seconds
Started Aug 02 05:26:35 PM PDT 24
Finished Aug 02 05:26:37 PM PDT 24
Peak memory 207492 kb
Host smart-92da2407-f249-468a-977b-5a595205e741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20985
54834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2098554834
Directory /workspace/1.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/1.usbdev_endpoint_types.932245996
Short name T1687
Test name
Test status
Simulation time 637620572 ps
CPU time 1.63 seconds
Started Aug 02 05:26:36 PM PDT 24
Finished Aug 02 05:26:38 PM PDT 24
Peak memory 207408 kb
Host smart-2a6a3c8c-6c2d-4c72-8f9c-adee06e42ea7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=932245996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_types.932245996
Directory /workspace/1.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/1.usbdev_fifo_rst.1679489104
Short name T194
Test name
Test status
Simulation time 219130923 ps
CPU time 1.41 seconds
Started Aug 02 05:26:36 PM PDT 24
Finished Aug 02 05:26:38 PM PDT 24
Peak memory 207544 kb
Host smart-f0e91089-4331-48b3-8fac-2630f7b2f1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16794
89104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1679489104
Directory /workspace/1.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.1891480092
Short name T319
Test name
Test status
Simulation time 87042321978 ps
CPU time 142.23 seconds
Started Aug 02 05:26:36 PM PDT 24
Finished Aug 02 05:28:58 PM PDT 24
Peak memory 207736 kb
Host smart-1c4587ea-44d7-4f98-8d7f-d720ea58e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891480092 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1891480092
Directory /workspace/1.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/1.usbdev_freq_loclk.1232295682
Short name T2356
Test name
Test status
Simulation time 119097560374 ps
CPU time 205.66 seconds
Started Aug 02 05:26:39 PM PDT 24
Finished Aug 02 05:30:05 PM PDT 24
Peak memory 207700 kb
Host smart-f284db1f-b339-4fcc-bcf4-cf1d6e9afae3
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1232295682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.1232295682
Directory /workspace/1.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.3577258392
Short name T2804
Test name
Test status
Simulation time 111248349546 ps
CPU time 193.69 seconds
Started Aug 02 05:26:34 PM PDT 24
Finished Aug 02 05:29:48 PM PDT 24
Peak memory 207700 kb
Host smart-eeb00404-3e12-4b80-b459-0ca2a81c74ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577258392 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.3577258392
Directory /workspace/1.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/1.usbdev_freq_phase.2466122116
Short name T3073
Test name
Test status
Simulation time 104135112145 ps
CPU time 168.83 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:29:31 PM PDT 24
Peak memory 207668 kb
Host smart-6a6d9a35-cba6-449a-8c33-1bf9f66f3386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24661
22116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.2466122116
Directory /workspace/1.usbdev_freq_phase/latest


Test location /workspace/coverage/default/1.usbdev_in_iso.323014059
Short name T848
Test name
Test status
Simulation time 218368311 ps
CPU time 1.1 seconds
Started Aug 02 05:26:40 PM PDT 24
Finished Aug 02 05:26:42 PM PDT 24
Peak memory 207556 kb
Host smart-d897cca2-2809-420d-84bc-04798a14d70b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=323014059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.323014059
Directory /workspace/1.usbdev_in_iso/latest


Test location /workspace/coverage/default/1.usbdev_in_stall.3651995720
Short name T2418
Test name
Test status
Simulation time 158384877 ps
CPU time 0.79 seconds
Started Aug 02 05:26:43 PM PDT 24
Finished Aug 02 05:26:44 PM PDT 24
Peak memory 207392 kb
Host smart-f507d098-97f2-46db-b586-a04c5f7eaa97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36519
95720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3651995720
Directory /workspace/1.usbdev_in_stall/latest


Test location /workspace/coverage/default/1.usbdev_in_trans.1078593195
Short name T2867
Test name
Test status
Simulation time 195095014 ps
CPU time 0.87 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:26:43 PM PDT 24
Peak memory 207428 kb
Host smart-d3eb4ab1-8401-4abb-83b5-4530818b60b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10785
93195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1078593195
Directory /workspace/1.usbdev_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_invalid_sync.1464941303
Short name T559
Test name
Test status
Simulation time 3312418985 ps
CPU time 25.17 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:27:07 PM PDT 24
Peak memory 224040 kb
Host smart-2a7612ca-c929-4482-91ac-65f9a2a3901c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1464941303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.1464941303
Directory /workspace/1.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/1.usbdev_iso_retraction.3340165178
Short name T1023
Test name
Test status
Simulation time 12626574046 ps
CPU time 88.31 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 207716 kb
Host smart-fed2169f-0c28-46f2-b774-1b962dcfe0aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3340165178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3340165178
Directory /workspace/1.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/1.usbdev_link_in_err.2699862794
Short name T3010
Test name
Test status
Simulation time 225771968 ps
CPU time 0.93 seconds
Started Aug 02 05:26:41 PM PDT 24
Finished Aug 02 05:26:42 PM PDT 24
Peak memory 207400 kb
Host smart-6038c0bb-e283-46a0-901d-95c000e84e85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26998
62794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.2699862794
Directory /workspace/1.usbdev_link_in_err/latest


Test location /workspace/coverage/default/1.usbdev_link_resume.4169383114
Short name T68
Test name
Test status
Simulation time 29444475790 ps
CPU time 49.68 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:27:32 PM PDT 24
Peak memory 215984 kb
Host smart-50b068e2-b787-425e-9e37-4638eeee96c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41693
83114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.4169383114
Directory /workspace/1.usbdev_link_resume/latest


Test location /workspace/coverage/default/1.usbdev_link_suspend.3974126266
Short name T3052
Test name
Test status
Simulation time 11445937787 ps
CPU time 13 seconds
Started Aug 02 05:26:43 PM PDT 24
Finished Aug 02 05:26:56 PM PDT 24
Peak memory 207616 kb
Host smart-d619e7da-01a5-4c0d-8f15-9dfe5c8180d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39741
26266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3974126266
Directory /workspace/1.usbdev_link_suspend/latest


Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.2772451275
Short name T1550
Test name
Test status
Simulation time 3971641715 ps
CPU time 29.94 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:27:12 PM PDT 24
Peak memory 217748 kb
Host smart-dc847369-bf69-4efc-9479-4af5441a5abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27724
51275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.2772451275
Directory /workspace/1.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.3759004555
Short name T2312
Test name
Test status
Simulation time 3319127115 ps
CPU time 32.83 seconds
Started Aug 02 05:26:40 PM PDT 24
Finished Aug 02 05:27:13 PM PDT 24
Peak memory 217468 kb
Host smart-1c6354c0-5d68-4b3c-aa58-ea5dd5901cef
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3759004555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.3759004555
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.4219729039
Short name T1385
Test name
Test status
Simulation time 261210107 ps
CPU time 1.04 seconds
Started Aug 02 05:27:05 PM PDT 24
Finished Aug 02 05:27:06 PM PDT 24
Peak memory 207396 kb
Host smart-e80066e4-8d63-4eb8-8c88-ef8edbfcd907
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4219729039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.4219729039
Directory /workspace/1.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2498984293
Short name T1551
Test name
Test status
Simulation time 230207629 ps
CPU time 0.93 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:26:44 PM PDT 24
Peak memory 207420 kb
Host smart-e71ab866-3afc-4f37-a101-44c539e3da39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24989
84293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2498984293
Directory /workspace/1.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_max_non_iso_usb_traffic.967133610
Short name T1025
Test name
Test status
Simulation time 3373644390 ps
CPU time 96.26 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:28:18 PM PDT 24
Peak memory 224040 kb
Host smart-a37d0f9b-70e5-4c16-8779-778f75bade4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96713
3610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_non_iso_usb_traffic.967133610
Directory /workspace/1.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1073778268
Short name T2287
Test name
Test status
Simulation time 1971366728 ps
CPU time 14.46 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:26:56 PM PDT 24
Peak memory 223876 kb
Host smart-b427a43d-001c-4b7b-9d58-1406c0c5d780
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1073778268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1073778268
Directory /workspace/1.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.646325529
Short name T571
Test name
Test status
Simulation time 2299591350 ps
CPU time 64.37 seconds
Started Aug 02 05:26:41 PM PDT 24
Finished Aug 02 05:27:46 PM PDT 24
Peak memory 216840 kb
Host smart-bdbab4c9-6744-4bba-8b24-a7f0c02a27c0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=646325529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.646325529
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3016978986
Short name T2808
Test name
Test status
Simulation time 158311394 ps
CPU time 0.87 seconds
Started Aug 02 05:26:43 PM PDT 24
Finished Aug 02 05:26:44 PM PDT 24
Peak memory 207424 kb
Host smart-d2b9cbe5-f7b0-486f-a9b7-67e5f96a3b87
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3016978986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3016978986
Directory /workspace/1.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.269023446
Short name T2055
Test name
Test status
Simulation time 151045937 ps
CPU time 0.85 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:26:43 PM PDT 24
Peak memory 207328 kb
Host smart-3d618624-238c-4e0c-a94e-b1380054a93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26902
3446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.269023446
Directory /workspace/1.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_out_iso.3738598997
Short name T2514
Test name
Test status
Simulation time 153249687 ps
CPU time 0.81 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:26:43 PM PDT 24
Peak memory 207396 kb
Host smart-266c483f-4f7d-4887-a97c-216c0d42a628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37385
98997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3738598997
Directory /workspace/1.usbdev_out_iso/latest


Test location /workspace/coverage/default/1.usbdev_out_stall.4230919613
Short name T2154
Test name
Test status
Simulation time 181087386 ps
CPU time 0.82 seconds
Started Aug 02 05:26:42 PM PDT 24
Finished Aug 02 05:26:43 PM PDT 24
Peak memory 207416 kb
Host smart-7f63860d-b06b-4a5f-82d6-1eca175ef3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42309
19613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.4230919613
Directory /workspace/1.usbdev_out_stall/latest


Test location /workspace/coverage/default/1.usbdev_out_trans_nak.2622253929
Short name T578
Test name
Test status
Simulation time 174005227 ps
CPU time 0.83 seconds
Started Aug 02 05:26:45 PM PDT 24
Finished Aug 02 05:26:46 PM PDT 24
Peak memory 207424 kb
Host smart-ceb9ce40-e9fe-4e0d-8246-6fdd53e7bc47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26222
53929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.2622253929
Directory /workspace/1.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1429194216
Short name T188
Test name
Test status
Simulation time 155317973 ps
CPU time 0.81 seconds
Started Aug 02 05:26:50 PM PDT 24
Finished Aug 02 05:26:51 PM PDT 24
Peak memory 207388 kb
Host smart-b4cb89aa-54f7-43ba-a1ce-451ad350aaf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14291
94216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1429194216
Directory /workspace/1.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3328614276
Short name T223
Test name
Test status
Simulation time 220920228 ps
CPU time 0.98 seconds
Started Aug 02 05:26:51 PM PDT 24
Finished Aug 02 05:26:52 PM PDT 24
Peak memory 207376 kb
Host smart-10be69c7-f8e1-4040-8c17-8a49e62af098
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3328614276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3328614276
Directory /workspace/1.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3792745355
Short name T212
Test name
Test status
Simulation time 228423449 ps
CPU time 0.96 seconds
Started Aug 02 05:26:50 PM PDT 24
Finished Aug 02 05:26:51 PM PDT 24
Peak memory 207316 kb
Host smart-b9a89bd2-b83b-4ccc-9b78-1172c3a5bc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37927
45355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3792745355
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.284112917
Short name T2396
Test name
Test status
Simulation time 143370615 ps
CPU time 0.79 seconds
Started Aug 02 05:26:52 PM PDT 24
Finished Aug 02 05:26:53 PM PDT 24
Peak memory 207364 kb
Host smart-20e4efe4-120b-4ed6-8b9e-d06d9bbd3aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28411
2917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.284112917
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.20686659
Short name T40
Test name
Test status
Simulation time 70306361 ps
CPU time 0.72 seconds
Started Aug 02 05:26:52 PM PDT 24
Finished Aug 02 05:26:53 PM PDT 24
Peak memory 207356 kb
Host smart-bc392fed-97ec-4443-b96b-11f912975f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20686
659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.20686659
Directory /workspace/1.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/1.usbdev_pkt_buffer.624429227
Short name T264
Test name
Test status
Simulation time 24397992456 ps
CPU time 62.44 seconds
Started Aug 02 05:26:52 PM PDT 24
Finished Aug 02 05:27:55 PM PDT 24
Peak memory 215928 kb
Host smart-4be44332-b918-42d8-af81-40b7b7425b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62442
9227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.624429227
Directory /workspace/1.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/1.usbdev_pkt_received.3269161031
Short name T2033
Test name
Test status
Simulation time 171584720 ps
CPU time 0.89 seconds
Started Aug 02 05:26:52 PM PDT 24
Finished Aug 02 05:26:53 PM PDT 24
Peak memory 206500 kb
Host smart-df1aeff1-ea4a-4a64-aa23-f2df25627e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32691
61031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3269161031
Directory /workspace/1.usbdev_pkt_received/latest


Test location /workspace/coverage/default/1.usbdev_pkt_sent.2138954612
Short name T1846
Test name
Test status
Simulation time 264210187 ps
CPU time 1.01 seconds
Started Aug 02 05:26:52 PM PDT 24
Finished Aug 02 05:26:53 PM PDT 24
Peak memory 206400 kb
Host smart-e61dada5-0811-40f7-ab79-262c24d1bdba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21389
54612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2138954612
Directory /workspace/1.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1126591520
Short name T2573
Test name
Test status
Simulation time 2214351600 ps
CPU time 20.31 seconds
Started Aug 02 05:26:52 PM PDT 24
Finished Aug 02 05:27:12 PM PDT 24
Peak memory 223980 kb
Host smart-c55b6024-9cdb-4076-9043-fd2f49081df7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126591520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1126591520
Directory /workspace/1.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.360821719
Short name T2180
Test name
Test status
Simulation time 2748342196 ps
CPU time 54.43 seconds
Started Aug 02 05:26:51 PM PDT 24
Finished Aug 02 05:27:46 PM PDT 24
Peak memory 215836 kb
Host smart-a0add082-4312-431e-a41c-4093d7935511
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=360821719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.360821719
Directory /workspace/1.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/1.usbdev_rand_suspends.1531440617
Short name T1283
Test name
Test status
Simulation time 8814716690 ps
CPU time 155.22 seconds
Started Aug 02 05:26:50 PM PDT 24
Finished Aug 02 05:29:26 PM PDT 24
Peak memory 224000 kb
Host smart-bd0db6d5-5897-4c97-be49-28cecbd7e7e1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531440617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.1531440617
Directory /workspace/1.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3331568659
Short name T2596
Test name
Test status
Simulation time 191750820 ps
CPU time 0.88 seconds
Started Aug 02 05:26:51 PM PDT 24
Finished Aug 02 05:26:52 PM PDT 24
Peak memory 207392 kb
Host smart-85cdc1fa-c6ba-44aa-92bb-f55036578046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33315
68659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3331568659
Directory /workspace/1.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.974402706
Short name T2839
Test name
Test status
Simulation time 148851441 ps
CPU time 0.86 seconds
Started Aug 02 05:26:52 PM PDT 24
Finished Aug 02 05:26:53 PM PDT 24
Peak memory 207460 kb
Host smart-b8733950-c131-4f77-b742-5006fb8bd355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97440
2706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.974402706
Directory /workspace/1.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2908230827
Short name T2894
Test name
Test status
Simulation time 154902830 ps
CPU time 0.82 seconds
Started Aug 02 05:26:50 PM PDT 24
Finished Aug 02 05:26:51 PM PDT 24
Peak memory 207436 kb
Host smart-059f7522-c356-4846-bc9a-c998df0c5ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29082
30827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2908230827
Directory /workspace/1.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/1.usbdev_rx_full.4271875279
Short name T828
Test name
Test status
Simulation time 246483137 ps
CPU time 1.11 seconds
Started Aug 02 05:26:52 PM PDT 24
Finished Aug 02 05:26:53 PM PDT 24
Peak memory 207360 kb
Host smart-0bc72bbc-c20f-440a-99d8-d265a88e03d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42718
75279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_full.4271875279
Directory /workspace/1.usbdev_rx_full/latest


Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2930937638
Short name T78
Test name
Test status
Simulation time 168664721 ps
CPU time 0.89 seconds
Started Aug 02 05:26:52 PM PDT 24
Finished Aug 02 05:26:53 PM PDT 24
Peak memory 207332 kb
Host smart-8da329d8-1a89-417f-aaaa-82b68f303e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29309
37638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2930937638
Directory /workspace/1.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/1.usbdev_sec_cm.208833201
Short name T205
Test name
Test status
Simulation time 268080956 ps
CPU time 1.15 seconds
Started Aug 02 05:27:10 PM PDT 24
Finished Aug 02 05:27:12 PM PDT 24
Peak memory 223376 kb
Host smart-9a7c2d70-83b5-4ef8-abb0-00bc07c8edfc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=208833201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.208833201
Directory /workspace/1.usbdev_sec_cm/latest


Test location /workspace/coverage/default/1.usbdev_setup_priority.776326025
Short name T53
Test name
Test status
Simulation time 358113264 ps
CPU time 1.29 seconds
Started Aug 02 05:26:53 PM PDT 24
Finished Aug 02 05:26:54 PM PDT 24
Peak memory 207332 kb
Host smart-2da1aa48-525c-48fe-90f5-e8f5cd1265fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77632
6025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.776326025
Directory /workspace/1.usbdev_setup_priority/latest


Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.3049510627
Short name T2020
Test name
Test status
Simulation time 307319497 ps
CPU time 1.05 seconds
Started Aug 02 05:26:51 PM PDT 24
Finished Aug 02 05:26:52 PM PDT 24
Peak memory 207428 kb
Host smart-03b1d1e7-3eda-4fdb-b1a6-f3f8eb4c74f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30495
10627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.3049510627
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/1.usbdev_setup_stage.3593007381
Short name T1198
Test name
Test status
Simulation time 162830984 ps
CPU time 0.87 seconds
Started Aug 02 05:26:49 PM PDT 24
Finished Aug 02 05:26:50 PM PDT 24
Peak memory 207372 kb
Host smart-28763a88-f59f-40f7-ae7a-057dd3147e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35930
07381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.3593007381
Directory /workspace/1.usbdev_setup_stage/latest


Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3561762186
Short name T2702
Test name
Test status
Simulation time 160226548 ps
CPU time 0.82 seconds
Started Aug 02 05:26:51 PM PDT 24
Finished Aug 02 05:26:52 PM PDT 24
Peak memory 207336 kb
Host smart-2190f8b6-bccf-447f-bed3-149962133ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35617
62186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3561762186
Directory /workspace/1.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/1.usbdev_smoke.3169128691
Short name T2626
Test name
Test status
Simulation time 241617275 ps
CPU time 0.98 seconds
Started Aug 02 05:26:49 PM PDT 24
Finished Aug 02 05:26:50 PM PDT 24
Peak memory 207356 kb
Host smart-556f9de0-74f7-4f06-8332-27fbd566f88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31691
28691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3169128691
Directory /workspace/1.usbdev_smoke/latest


Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2777504365
Short name T2920
Test name
Test status
Simulation time 1588182027 ps
CPU time 43.79 seconds
Started Aug 02 05:26:50 PM PDT 24
Finished Aug 02 05:27:34 PM PDT 24
Peak memory 215736 kb
Host smart-00dc7f73-3b76-4ae7-9112-e7385f839cdd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2777504365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2777504365
Directory /workspace/1.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2542251084
Short name T1156
Test name
Test status
Simulation time 164659059 ps
CPU time 0.86 seconds
Started Aug 02 05:26:51 PM PDT 24
Finished Aug 02 05:26:51 PM PDT 24
Peak memory 207360 kb
Host smart-7f438dce-4062-4c89-82b8-78cfea8e09c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25422
51084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2542251084
Directory /workspace/1.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/1.usbdev_stall_trans.3818218525
Short name T1186
Test name
Test status
Simulation time 149210315 ps
CPU time 0.81 seconds
Started Aug 02 05:26:49 PM PDT 24
Finished Aug 02 05:26:50 PM PDT 24
Peak memory 207360 kb
Host smart-3f9fca25-d2b5-4ab1-a562-c7cbafa9cc35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38182
18525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.3818218525
Directory /workspace/1.usbdev_stall_trans/latest


Test location /workspace/coverage/default/1.usbdev_stream_len_max.2597588263
Short name T2870
Test name
Test status
Simulation time 1271601203 ps
CPU time 3.07 seconds
Started Aug 02 05:26:53 PM PDT 24
Finished Aug 02 05:26:57 PM PDT 24
Peak memory 207584 kb
Host smart-c52e3c8a-fb1c-4bd4-ac5e-456f839530b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25975
88263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.2597588263
Directory /workspace/1.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/1.usbdev_streaming_out.576325845
Short name T520
Test name
Test status
Simulation time 3133521920 ps
CPU time 32.28 seconds
Started Aug 02 05:26:53 PM PDT 24
Finished Aug 02 05:27:26 PM PDT 24
Peak memory 215784 kb
Host smart-23de839c-05cc-49bc-806c-de6cbc8fc942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57632
5845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.576325845
Directory /workspace/1.usbdev_streaming_out/latest


Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.4204895718
Short name T77
Test name
Test status
Simulation time 7074639130 ps
CPU time 38.98 seconds
Started Aug 02 05:26:57 PM PDT 24
Finished Aug 02 05:27:36 PM PDT 24
Peak memory 224116 kb
Host smart-02db82d7-4513-461c-9502-36d73ac591a3
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204895718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.4204895718
Directory /workspace/1.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/1.usbdev_timeout_missing_host_handshake.3587573083
Short name T1662
Test name
Test status
Simulation time 1923914539 ps
CPU time 46.43 seconds
Started Aug 02 05:26:35 PM PDT 24
Finished Aug 02 05:27:21 PM PDT 24
Peak memory 207600 kb
Host smart-96c1ab47-14aa-496e-94b7-1b6cbbbcf6e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587573083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_timeout_missing_host
_handshake.3587573083
Directory /workspace/1.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.3555614334
Short name T932
Test name
Test status
Simulation time 10735877982 ps
CPU time 13.26 seconds
Started Aug 02 05:29:10 PM PDT 24
Finished Aug 02 05:29:24 PM PDT 24
Peak memory 207632 kb
Host smart-a547faf4-32bd-4276-a3d7-730dec65eb84
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555614334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_disconnect.3555614334
Directory /workspace/10.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.602355047
Short name T2235
Test name
Test status
Simulation time 15792481813 ps
CPU time 19.22 seconds
Started Aug 02 05:29:12 PM PDT 24
Finished Aug 02 05:29:31 PM PDT 24
Peak memory 215796 kb
Host smart-24f6b88f-53da-4a3f-a54c-66bd27ff7542
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=602355047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.602355047
Directory /workspace/10.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.2946648729
Short name T2486
Test name
Test status
Simulation time 25915711303 ps
CPU time 30 seconds
Started Aug 02 05:29:16 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 215880 kb
Host smart-43d78ae1-f939-44df-980a-e30e459b9070
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946648729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_a
on_wake_resume.2946648729
Directory /workspace/10.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/10.usbdev_av_buffer.3041020146
Short name T94
Test name
Test status
Simulation time 145468382 ps
CPU time 0.87 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207384 kb
Host smart-068302c3-4cb3-42b8-bfa7-a4cc0964bb28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30410
20146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3041020146
Directory /workspace/10.usbdev_av_buffer/latest


Test location /workspace/coverage/default/10.usbdev_bitstuff_err.1636546913
Short name T3015
Test name
Test status
Simulation time 146674774 ps
CPU time 0.81 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207400 kb
Host smart-3a2719b8-8601-4508-afeb-a219ce965456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16365
46913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.1636546913
Directory /workspace/10.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1627262028
Short name T2236
Test name
Test status
Simulation time 466234509 ps
CPU time 1.57 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207412 kb
Host smart-c2d6cc99-1db3-4388-87bc-3b2504e9d751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16272
62028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1627262028
Directory /workspace/10.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2079220202
Short name T704
Test name
Test status
Simulation time 419811653 ps
CPU time 1.34 seconds
Started Aug 02 05:29:20 PM PDT 24
Finished Aug 02 05:29:21 PM PDT 24
Peak memory 207432 kb
Host smart-3344398e-6311-48c0-a80d-57c20f3fc8e1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2079220202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2079220202
Directory /workspace/10.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/10.usbdev_device_address.901385682
Short name T174
Test name
Test status
Simulation time 24726515961 ps
CPU time 38.03 seconds
Started Aug 02 05:29:19 PM PDT 24
Finished Aug 02 05:29:57 PM PDT 24
Peak memory 207716 kb
Host smart-7c7bea4d-2323-4079-8d84-44c46ad73b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90138
5682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.901385682
Directory /workspace/10.usbdev_device_address/latest


Test location /workspace/coverage/default/10.usbdev_device_timeout.88332130
Short name T850
Test name
Test status
Simulation time 353519003 ps
CPU time 4.37 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:22 PM PDT 24
Peak memory 207540 kb
Host smart-b4b25e48-eaf8-4865-b79b-64b3b79a3b68
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88332130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_timeout.88332130
Directory /workspace/10.usbdev_device_timeout/latest


Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3345842058
Short name T2764
Test name
Test status
Simulation time 801616049 ps
CPU time 1.72 seconds
Started Aug 02 05:29:21 PM PDT 24
Finished Aug 02 05:29:23 PM PDT 24
Peak memory 207388 kb
Host smart-cbc4a252-568a-4733-9247-ea9a21c9f8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33458
42058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3345842058
Directory /workspace/10.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/10.usbdev_disconnected.2008987551
Short name T2704
Test name
Test status
Simulation time 162501223 ps
CPU time 0.89 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207320 kb
Host smart-6825bc03-d6b1-4573-b5cb-ec0aec6a20ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20089
87551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2008987551
Directory /workspace/10.usbdev_disconnected/latest


Test location /workspace/coverage/default/10.usbdev_enable.3160124388
Short name T1159
Test name
Test status
Simulation time 36586598 ps
CPU time 0.72 seconds
Started Aug 02 05:29:19 PM PDT 24
Finished Aug 02 05:29:20 PM PDT 24
Peak memory 207324 kb
Host smart-d5adc949-4ede-4f97-a149-9565ce9a8533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31601
24388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3160124388
Directory /workspace/10.usbdev_enable/latest


Test location /workspace/coverage/default/10.usbdev_endpoint_access.2720828111
Short name T1780
Test name
Test status
Simulation time 945433016 ps
CPU time 2.44 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:20 PM PDT 24
Peak memory 207608 kb
Host smart-bcda8718-d08a-4e09-8994-7548efdaf04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27208
28111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2720828111
Directory /workspace/10.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/10.usbdev_endpoint_types.1583516177
Short name T382
Test name
Test status
Simulation time 560493694 ps
CPU time 1.39 seconds
Started Aug 02 05:29:16 PM PDT 24
Finished Aug 02 05:29:17 PM PDT 24
Peak memory 207308 kb
Host smart-0aef5090-2653-4df6-8ce4-150b7b93a44f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1583516177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_types.1583516177
Directory /workspace/10.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/10.usbdev_fifo_rst.3143094435
Short name T1381
Test name
Test status
Simulation time 202085261 ps
CPU time 1.47 seconds
Started Aug 02 05:29:16 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207452 kb
Host smart-769b9230-13e2-4615-b931-69a0937395bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31430
94435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3143094435
Directory /workspace/10.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/10.usbdev_in_iso.1624232165
Short name T2502
Test name
Test status
Simulation time 179854800 ps
CPU time 0.99 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207572 kb
Host smart-ee7fd0a4-60fc-4c1a-8f08-48d32b803f6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1624232165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.1624232165
Directory /workspace/10.usbdev_in_iso/latest


Test location /workspace/coverage/default/10.usbdev_in_stall.1428743582
Short name T880
Test name
Test status
Simulation time 206153084 ps
CPU time 0.87 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207296 kb
Host smart-18ca9404-7707-43b0-b179-621fa2e0a352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14287
43582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.1428743582
Directory /workspace/10.usbdev_in_stall/latest


Test location /workspace/coverage/default/10.usbdev_in_trans.3279626617
Short name T1370
Test name
Test status
Simulation time 185969783 ps
CPU time 0.87 seconds
Started Aug 02 05:29:15 PM PDT 24
Finished Aug 02 05:29:16 PM PDT 24
Peak memory 207400 kb
Host smart-f8a608a6-09fd-4896-8f68-96e63fa34d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32796
26617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3279626617
Directory /workspace/10.usbdev_in_trans/latest


Test location /workspace/coverage/default/10.usbdev_invalid_sync.3098807159
Short name T895
Test name
Test status
Simulation time 5283568491 ps
CPU time 150.31 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:31:49 PM PDT 24
Peak memory 215812 kb
Host smart-3dbb84de-7c35-4162-88b5-6794e76cd928
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3098807159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.3098807159
Directory /workspace/10.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/10.usbdev_iso_retraction.4254255120
Short name T1784
Test name
Test status
Simulation time 3910887655 ps
CPU time 43.76 seconds
Started Aug 02 05:29:23 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207688 kb
Host smart-720650cb-fe05-4372-9f54-740ab4ee4a3a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4254255120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.4254255120
Directory /workspace/10.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/10.usbdev_link_in_err.3237195111
Short name T786
Test name
Test status
Simulation time 250307405 ps
CPU time 1.07 seconds
Started Aug 02 05:29:16 PM PDT 24
Finished Aug 02 05:29:17 PM PDT 24
Peak memory 207384 kb
Host smart-d87dddec-ab4d-478b-b6fb-1f04be5dae90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32371
95111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.3237195111
Directory /workspace/10.usbdev_link_in_err/latest


Test location /workspace/coverage/default/10.usbdev_link_resume.3938959426
Short name T1620
Test name
Test status
Simulation time 29379103352 ps
CPU time 42.17 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:59 PM PDT 24
Peak memory 207720 kb
Host smart-ef2d1c90-6056-46e3-9bd2-5df33b42589f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39389
59426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3938959426
Directory /workspace/10.usbdev_link_resume/latest


Test location /workspace/coverage/default/10.usbdev_link_suspend.3693786875
Short name T56
Test name
Test status
Simulation time 10494552544 ps
CPU time 13.8 seconds
Started Aug 02 05:29:19 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207676 kb
Host smart-0d7d032c-c896-41c2-ba7e-e960221de1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36937
86875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.3693786875
Directory /workspace/10.usbdev_link_suspend/latest


Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3782424083
Short name T739
Test name
Test status
Simulation time 2927383442 ps
CPU time 28.56 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 224036 kb
Host smart-02d740cb-2ab3-451c-81bb-ef2ca78a305f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37824
24083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3782424083
Directory /workspace/10.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.572873629
Short name T349
Test name
Test status
Simulation time 2569045596 ps
CPU time 73.61 seconds
Started Aug 02 05:29:19 PM PDT 24
Finished Aug 02 05:30:32 PM PDT 24
Peak memory 217392 kb
Host smart-7a278297-913b-4c96-999e-37e061fd5b88
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=572873629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.572873629
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2868377967
Short name T2887
Test name
Test status
Simulation time 299705370 ps
CPU time 1.11 seconds
Started Aug 02 05:29:16 PM PDT 24
Finished Aug 02 05:29:17 PM PDT 24
Peak memory 207416 kb
Host smart-bde40a2c-209e-4fb0-b26a-68560cf0c149
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2868377967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2868377967
Directory /workspace/10.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3134929563
Short name T573
Test name
Test status
Simulation time 245585684 ps
CPU time 0.98 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207384 kb
Host smart-da14be82-d5b8-4eb6-9968-bee86b74553a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31349
29563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3134929563
Directory /workspace/10.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_max_non_iso_usb_traffic.1495712389
Short name T656
Test name
Test status
Simulation time 2485410559 ps
CPU time 69.78 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:30:28 PM PDT 24
Peak memory 217332 kb
Host smart-2cd4bce0-dc5a-47cb-8028-6c0c87f9f7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14957
12389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_non_iso_usb_traffic.1495712389
Directory /workspace/10.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.1778101480
Short name T2150
Test name
Test status
Simulation time 2354129316 ps
CPU time 20.88 seconds
Started Aug 02 05:29:21 PM PDT 24
Finished Aug 02 05:29:42 PM PDT 24
Peak memory 215900 kb
Host smart-87966e4e-432d-4491-86a6-a63df6939427
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1778101480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.1778101480
Directory /workspace/10.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1582815509
Short name T700
Test name
Test status
Simulation time 3069422304 ps
CPU time 89.85 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:30:47 PM PDT 24
Peak memory 215880 kb
Host smart-a3317d9e-f801-4fbd-a7e7-d1faa5bdb4f6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1582815509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1582815509
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.678236039
Short name T558
Test name
Test status
Simulation time 171023429 ps
CPU time 0.86 seconds
Started Aug 02 05:29:27 PM PDT 24
Finished Aug 02 05:29:28 PM PDT 24
Peak memory 207404 kb
Host smart-73a5df80-48b6-459e-a2bf-ac8824abf873
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=678236039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.678236039
Directory /workspace/10.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.49100828
Short name T2215
Test name
Test status
Simulation time 160158821 ps
CPU time 0.85 seconds
Started Aug 02 05:29:20 PM PDT 24
Finished Aug 02 05:29:21 PM PDT 24
Peak memory 207404 kb
Host smart-568c8c17-4772-4c8b-a6d6-bc6dda4993e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49100
828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.49100828
Directory /workspace/10.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_nak_trans.680550809
Short name T147
Test name
Test status
Simulation time 178408088 ps
CPU time 0.87 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207380 kb
Host smart-2326b89a-9178-433e-9533-368ac9c7b418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68055
0809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.680550809
Directory /workspace/10.usbdev_nak_trans/latest


Test location /workspace/coverage/default/10.usbdev_out_iso.3965147828
Short name T2557
Test name
Test status
Simulation time 162094736 ps
CPU time 0.86 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207396 kb
Host smart-72e0ca56-ff73-4a81-8c04-f50bdd886b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39651
47828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.3965147828
Directory /workspace/10.usbdev_out_iso/latest


Test location /workspace/coverage/default/10.usbdev_out_stall.2292705437
Short name T2310
Test name
Test status
Simulation time 164318174 ps
CPU time 0.85 seconds
Started Aug 02 05:29:16 PM PDT 24
Finished Aug 02 05:29:17 PM PDT 24
Peak memory 207424 kb
Host smart-745409fc-a363-42d6-8134-6adba009075e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22927
05437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2292705437
Directory /workspace/10.usbdev_out_stall/latest


Test location /workspace/coverage/default/10.usbdev_out_trans_nak.2960942070
Short name T482
Test name
Test status
Simulation time 213079992 ps
CPU time 0.9 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207316 kb
Host smart-753e5f46-a04d-423c-8610-bee24bd4ac9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29609
42070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.2960942070
Directory /workspace/10.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/10.usbdev_pending_in_trans.2496039671
Short name T2748
Test name
Test status
Simulation time 154827294 ps
CPU time 0.92 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207388 kb
Host smart-39238fc2-ee2d-4437-aab6-b8ac0ac12130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
39671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.2496039671
Directory /workspace/10.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.71988396
Short name T1834
Test name
Test status
Simulation time 229799586 ps
CPU time 1.11 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207368 kb
Host smart-6e402c59-a3bf-4bd0-b049-2ff2a92fa548
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=71988396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.71988396
Directory /workspace/10.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.527534364
Short name T2048
Test name
Test status
Simulation time 143742059 ps
CPU time 0.82 seconds
Started Aug 02 05:29:20 PM PDT 24
Finished Aug 02 05:29:21 PM PDT 24
Peak memory 207388 kb
Host smart-35847f94-a9c8-4136-865a-ac053679305f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52753
4364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.527534364
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3963791859
Short name T2346
Test name
Test status
Simulation time 48192718 ps
CPU time 0.7 seconds
Started Aug 02 05:29:20 PM PDT 24
Finished Aug 02 05:29:21 PM PDT 24
Peak memory 207372 kb
Host smart-f2b78897-93a4-4f55-87c4-c4edc929121e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39637
91859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3963791859
Directory /workspace/10.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1688220925
Short name T1457
Test name
Test status
Simulation time 20409124139 ps
CPU time 51.97 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:30:09 PM PDT 24
Peak memory 215824 kb
Host smart-c03246a9-a3c0-4f03-b3a9-0dfb0948baff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16882
20925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1688220925
Directory /workspace/10.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/10.usbdev_pkt_received.2349667458
Short name T787
Test name
Test status
Simulation time 157621505 ps
CPU time 0.86 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207348 kb
Host smart-1d7a876b-5759-4708-8e0f-c54dbc483f05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23496
67458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.2349667458
Directory /workspace/10.usbdev_pkt_received/latest


Test location /workspace/coverage/default/10.usbdev_pkt_sent.3410294492
Short name T2872
Test name
Test status
Simulation time 190603817 ps
CPU time 0.89 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207336 kb
Host smart-d5cc08e7-0dff-44fd-b61a-e57b22f3b06a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34102
94492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.3410294492
Directory /workspace/10.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.2999421019
Short name T1179
Test name
Test status
Simulation time 190774902 ps
CPU time 0.94 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207416 kb
Host smart-ed293d46-ddf2-4f2b-ac86-f152becaadac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29994
21019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.2999421019
Directory /workspace/10.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.4111340707
Short name T1384
Test name
Test status
Simulation time 156820869 ps
CPU time 0.82 seconds
Started Aug 02 05:29:16 PM PDT 24
Finished Aug 02 05:29:17 PM PDT 24
Peak memory 207368 kb
Host smart-72c7eab8-516b-4444-b4c0-2e22d4d69956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41113
40707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.4111340707
Directory /workspace/10.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3180323372
Short name T2221
Test name
Test status
Simulation time 186542071 ps
CPU time 0.87 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207352 kb
Host smart-cf8c86b6-3321-4b1a-bad7-115a97bfc5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31803
23372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3180323372
Directory /workspace/10.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/10.usbdev_rx_full.66877830
Short name T2041
Test name
Test status
Simulation time 260219273 ps
CPU time 1.04 seconds
Started Aug 02 05:29:24 PM PDT 24
Finished Aug 02 05:29:25 PM PDT 24
Peak memory 207416 kb
Host smart-31bcaf40-e0c4-491e-892a-8948785f011c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66877
830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_full.66877830
Directory /workspace/10.usbdev_rx_full/latest


Test location /workspace/coverage/default/10.usbdev_setup_stage.2879737713
Short name T2781
Test name
Test status
Simulation time 147530253 ps
CPU time 0.83 seconds
Started Aug 02 05:29:15 PM PDT 24
Finished Aug 02 05:29:15 PM PDT 24
Peak memory 207372 kb
Host smart-fef50adf-96fc-4cb6-9c87-e21199f2ad9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28797
37713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2879737713
Directory /workspace/10.usbdev_setup_stage/latest


Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.1708638282
Short name T2123
Test name
Test status
Simulation time 157137276 ps
CPU time 0.86 seconds
Started Aug 02 05:29:22 PM PDT 24
Finished Aug 02 05:29:23 PM PDT 24
Peak memory 207416 kb
Host smart-a16cfc70-be79-4a63-bfe9-f8cd2f63b1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17086
38282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.1708638282
Directory /workspace/10.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/10.usbdev_smoke.1550389963
Short name T825
Test name
Test status
Simulation time 219611762 ps
CPU time 1.01 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207400 kb
Host smart-9222155f-d181-43e4-a9b4-f0eb3d2e5cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15503
89963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1550389963
Directory /workspace/10.usbdev_smoke/latest


Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.425876526
Short name T2777
Test name
Test status
Simulation time 2385471802 ps
CPU time 21.21 seconds
Started Aug 02 05:29:15 PM PDT 24
Finished Aug 02 05:29:37 PM PDT 24
Peak memory 223904 kb
Host smart-207b03a5-abed-4d6a-a5da-5a16cd9c5454
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=425876526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.425876526
Directory /workspace/10.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2796928278
Short name T655
Test name
Test status
Simulation time 185239357 ps
CPU time 0.9 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207460 kb
Host smart-61e73fb4-6816-4a36-b8bc-7ef6fcb8c5d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27969
28278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2796928278
Directory /workspace/10.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/10.usbdev_stall_trans.329669553
Short name T744
Test name
Test status
Simulation time 242333384 ps
CPU time 0.94 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207396 kb
Host smart-5a8d0a25-2ca3-49a8-be2e-be9ed22650c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32966
9553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.329669553
Directory /workspace/10.usbdev_stall_trans/latest


Test location /workspace/coverage/default/10.usbdev_stream_len_max.1093970946
Short name T990
Test name
Test status
Simulation time 747090964 ps
CPU time 1.92 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207328 kb
Host smart-7336e387-c800-478d-b683-b1e189419384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10939
70946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.1093970946
Directory /workspace/10.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/10.usbdev_streaming_out.3863280115
Short name T2240
Test name
Test status
Simulation time 2225008932 ps
CPU time 62.22 seconds
Started Aug 02 05:29:18 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 215900 kb
Host smart-e4375f3e-c112-4dea-accd-47f3fbba8551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38632
80115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3863280115
Directory /workspace/10.usbdev_streaming_out/latest


Test location /workspace/coverage/default/10.usbdev_timeout_missing_host_handshake.2929105817
Short name T1692
Test name
Test status
Simulation time 437663260 ps
CPU time 8.05 seconds
Started Aug 02 05:29:16 PM PDT 24
Finished Aug 02 05:29:25 PM PDT 24
Peak memory 207572 kb
Host smart-d039e41c-82dc-4a1b-9716-a794fcb41690
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929105817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_timeout_missing_hos
t_handshake.2929105817
Directory /workspace/10.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/103.usbdev_endpoint_types.4153865960
Short name T484
Test name
Test status
Simulation time 202519509 ps
CPU time 0.89 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207340 kb
Host smart-99e222fd-0d51-45a1-b8ac-431fc08154fe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4153865960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.usbdev_endpoint_types.4153865960
Directory /workspace/103.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/104.usbdev_endpoint_types.2360979662
Short name T2195
Test name
Test status
Simulation time 361143818 ps
CPU time 1.18 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207360 kb
Host smart-fdd2c80b-85f7-4014-b658-ef962d53f911
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2360979662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.usbdev_endpoint_types.2360979662
Directory /workspace/104.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/105.usbdev_endpoint_types.2874348827
Short name T434
Test name
Test status
Simulation time 484703416 ps
CPU time 1.31 seconds
Started Aug 02 05:34:59 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207308 kb
Host smart-f82156dc-faca-4052-aabe-915cd33dabea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2874348827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.usbdev_endpoint_types.2874348827
Directory /workspace/105.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/108.usbdev_endpoint_types.1076851091
Short name T432
Test name
Test status
Simulation time 613782132 ps
CPU time 1.71 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207360 kb
Host smart-ac863930-bc2e-474d-8d64-51d9dc82ae43
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1076851091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.usbdev_endpoint_types.1076851091
Directory /workspace/108.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/109.usbdev_endpoint_types.1536080257
Short name T121
Test name
Test status
Simulation time 375596123 ps
CPU time 1.17 seconds
Started Aug 02 05:35:08 PM PDT 24
Finished Aug 02 05:35:10 PM PDT 24
Peak memory 207348 kb
Host smart-a619ba7f-908b-4bb0-989d-f664694235c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1536080257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.usbdev_endpoint_types.1536080257
Directory /workspace/109.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/11.usbdev_alert_test.2297094894
Short name T637
Test name
Test status
Simulation time 46776278 ps
CPU time 0.67 seconds
Started Aug 02 05:29:38 PM PDT 24
Finished Aug 02 05:29:39 PM PDT 24
Peak memory 207448 kb
Host smart-82f72aeb-92ed-407f-b672-063fd6252cbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2297094894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.2297094894
Directory /workspace/11.usbdev_alert_test/latest


Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.1317056908
Short name T2967
Test name
Test status
Simulation time 10220152900 ps
CPU time 12.69 seconds
Started Aug 02 05:29:22 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207688 kb
Host smart-d00d3ba8-0555-49db-af7d-ce1e0e06b349
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317056908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_disconnect.1317056908
Directory /workspace/11.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3328092424
Short name T2126
Test name
Test status
Simulation time 14565289714 ps
CPU time 16.95 seconds
Started Aug 02 05:29:20 PM PDT 24
Finished Aug 02 05:29:37 PM PDT 24
Peak memory 215864 kb
Host smart-9b149875-ecc4-4643-82c7-994e2e0f1e01
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328092424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3328092424
Directory /workspace/11.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3026902176
Short name T894
Test name
Test status
Simulation time 23622103602 ps
CPU time 31.46 seconds
Started Aug 02 05:29:20 PM PDT 24
Finished Aug 02 05:29:51 PM PDT 24
Peak memory 215868 kb
Host smart-495e52b5-13e2-49b7-be5c-df054f88057e
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026902176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_a
on_wake_resume.3026902176
Directory /workspace/11.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/11.usbdev_av_buffer.364168990
Short name T2149
Test name
Test status
Simulation time 153930827 ps
CPU time 0.9 seconds
Started Aug 02 05:29:27 PM PDT 24
Finished Aug 02 05:29:28 PM PDT 24
Peak memory 207356 kb
Host smart-1fc71aca-90da-4187-8af6-751e9ef28424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36416
8990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.364168990
Directory /workspace/11.usbdev_av_buffer/latest


Test location /workspace/coverage/default/11.usbdev_bitstuff_err.1511013229
Short name T2570
Test name
Test status
Simulation time 141918040 ps
CPU time 0.88 seconds
Started Aug 02 05:29:26 PM PDT 24
Finished Aug 02 05:29:27 PM PDT 24
Peak memory 207400 kb
Host smart-cb1abf83-db4e-4868-845c-629f71cca709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15110
13229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.1511013229
Directory /workspace/11.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3731241459
Short name T519
Test name
Test status
Simulation time 298045365 ps
CPU time 1.22 seconds
Started Aug 02 05:29:27 PM PDT 24
Finished Aug 02 05:29:28 PM PDT 24
Peak memory 207412 kb
Host smart-c363d622-738e-4420-91d3-77a2989622ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37312
41459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3731241459
Directory /workspace/11.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1685201805
Short name T737
Test name
Test status
Simulation time 970693966 ps
CPU time 2.57 seconds
Started Aug 02 05:29:29 PM PDT 24
Finished Aug 02 05:29:31 PM PDT 24
Peak memory 207512 kb
Host smart-171ab80c-64af-420e-862b-3e710fa8200d
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1685201805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1685201805
Directory /workspace/11.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/11.usbdev_device_address.2076128494
Short name T2313
Test name
Test status
Simulation time 17907688231 ps
CPU time 29.13 seconds
Started Aug 02 05:29:28 PM PDT 24
Finished Aug 02 05:29:57 PM PDT 24
Peak memory 207620 kb
Host smart-8e7098e9-72dd-4a0a-8403-047c6eb56781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20761
28494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2076128494
Directory /workspace/11.usbdev_device_address/latest


Test location /workspace/coverage/default/11.usbdev_device_timeout.2090313513
Short name T1125
Test name
Test status
Simulation time 1985883170 ps
CPU time 13.33 seconds
Started Aug 02 05:29:28 PM PDT 24
Finished Aug 02 05:29:41 PM PDT 24
Peak memory 207508 kb
Host smart-93edc316-d649-4c46-947d-abde790224f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090313513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_timeout.2090313513
Directory /workspace/11.usbdev_device_timeout/latest


Test location /workspace/coverage/default/11.usbdev_disable_endpoint.2412984349
Short name T2995
Test name
Test status
Simulation time 884690001 ps
CPU time 1.92 seconds
Started Aug 02 05:29:26 PM PDT 24
Finished Aug 02 05:29:28 PM PDT 24
Peak memory 207360 kb
Host smart-48f88211-5858-49d2-84b0-893a13310dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24129
84349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.2412984349
Directory /workspace/11.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/11.usbdev_disconnected.1004787570
Short name T1429
Test name
Test status
Simulation time 202164578 ps
CPU time 0.94 seconds
Started Aug 02 05:29:30 PM PDT 24
Finished Aug 02 05:29:31 PM PDT 24
Peak memory 207348 kb
Host smart-81428a1f-0268-4f07-bd37-4975a7792a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10047
87570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1004787570
Directory /workspace/11.usbdev_disconnected/latest


Test location /workspace/coverage/default/11.usbdev_enable.3952572638
Short name T3050
Test name
Test status
Simulation time 37420454 ps
CPU time 0.66 seconds
Started Aug 02 05:29:23 PM PDT 24
Finished Aug 02 05:29:24 PM PDT 24
Peak memory 207288 kb
Host smart-207a8fa5-0440-44ed-85e6-af1887987051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525
72638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3952572638
Directory /workspace/11.usbdev_enable/latest


Test location /workspace/coverage/default/11.usbdev_endpoint_access.4270778424
Short name T1684
Test name
Test status
Simulation time 742781833 ps
CPU time 2.27 seconds
Started Aug 02 05:29:25 PM PDT 24
Finished Aug 02 05:29:28 PM PDT 24
Peak memory 207636 kb
Host smart-a1f88f9e-5635-4137-b564-bd91c5d82ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42707
78424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.4270778424
Directory /workspace/11.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/11.usbdev_endpoint_types.1402913594
Short name T452
Test name
Test status
Simulation time 880763628 ps
CPU time 1.77 seconds
Started Aug 02 05:29:22 PM PDT 24
Finished Aug 02 05:29:24 PM PDT 24
Peak memory 207344 kb
Host smart-f15d947f-76b4-49d3-8f30-f3e4b48b9f53
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1402913594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_types.1402913594
Directory /workspace/11.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/11.usbdev_fifo_rst.3802633064
Short name T1511
Test name
Test status
Simulation time 244605316 ps
CPU time 1.89 seconds
Started Aug 02 05:29:23 PM PDT 24
Finished Aug 02 05:29:25 PM PDT 24
Peak memory 207576 kb
Host smart-e78533d1-768a-445e-9d9d-36bac100041d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38026
33064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.3802633064
Directory /workspace/11.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/11.usbdev_in_iso.1859962016
Short name T3051
Test name
Test status
Simulation time 209178592 ps
CPU time 1.14 seconds
Started Aug 02 05:29:29 PM PDT 24
Finished Aug 02 05:29:31 PM PDT 24
Peak memory 207564 kb
Host smart-c6911864-7afd-429e-af89-b84c1dae5e31
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1859962016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.1859962016
Directory /workspace/11.usbdev_in_iso/latest


Test location /workspace/coverage/default/11.usbdev_in_stall.550704950
Short name T3028
Test name
Test status
Simulation time 202298706 ps
CPU time 0.86 seconds
Started Aug 02 05:29:25 PM PDT 24
Finished Aug 02 05:29:26 PM PDT 24
Peak memory 207360 kb
Host smart-558cc133-342b-4990-8391-4c825b89cfc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55070
4950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.550704950
Directory /workspace/11.usbdev_in_stall/latest


Test location /workspace/coverage/default/11.usbdev_in_trans.3124761468
Short name T1042
Test name
Test status
Simulation time 226286538 ps
CPU time 0.97 seconds
Started Aug 02 05:29:28 PM PDT 24
Finished Aug 02 05:29:29 PM PDT 24
Peak memory 207312 kb
Host smart-d9d927fd-61ea-44a1-9e68-44e54d39da7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31247
61468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3124761468
Directory /workspace/11.usbdev_in_trans/latest


Test location /workspace/coverage/default/11.usbdev_invalid_sync.1929646061
Short name T793
Test name
Test status
Simulation time 2515197039 ps
CPU time 73.04 seconds
Started Aug 02 05:29:30 PM PDT 24
Finished Aug 02 05:30:43 PM PDT 24
Peak memory 215860 kb
Host smart-bcb4db2d-b7ce-446e-8322-6eb50acfc404
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1929646061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.1929646061
Directory /workspace/11.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/11.usbdev_iso_retraction.2654103868
Short name T954
Test name
Test status
Simulation time 9547733104 ps
CPU time 116.84 seconds
Started Aug 02 05:29:23 PM PDT 24
Finished Aug 02 05:31:20 PM PDT 24
Peak memory 207652 kb
Host smart-bb1793ce-2771-4dcf-a0fc-366d5f235e4c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2654103868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.2654103868
Directory /workspace/11.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/11.usbdev_link_in_err.2153831526
Short name T1585
Test name
Test status
Simulation time 183843510 ps
CPU time 0.89 seconds
Started Aug 02 05:29:29 PM PDT 24
Finished Aug 02 05:29:30 PM PDT 24
Peak memory 207328 kb
Host smart-e0145869-cf78-4474-b48f-b739602ca8b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21538
31526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.2153831526
Directory /workspace/11.usbdev_link_in_err/latest


Test location /workspace/coverage/default/11.usbdev_link_resume.4100116516
Short name T665
Test name
Test status
Simulation time 32290817235 ps
CPU time 48.04 seconds
Started Aug 02 05:29:25 PM PDT 24
Finished Aug 02 05:30:13 PM PDT 24
Peak memory 207620 kb
Host smart-4df338d0-b409-45f6-ac28-a101181626de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41001
16516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.4100116516
Directory /workspace/11.usbdev_link_resume/latest


Test location /workspace/coverage/default/11.usbdev_link_suspend.3242217337
Short name T2751
Test name
Test status
Simulation time 6172875828 ps
CPU time 8.57 seconds
Started Aug 02 05:29:26 PM PDT 24
Finished Aug 02 05:29:35 PM PDT 24
Peak memory 207648 kb
Host smart-b3b2735b-4829-49d7-9135-dce8bed46064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32422
17337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3242217337
Directory /workspace/11.usbdev_link_suspend/latest


Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3327513998
Short name T2642
Test name
Test status
Simulation time 3953326089 ps
CPU time 28.6 seconds
Started Aug 02 05:29:25 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 224000 kb
Host smart-0c252814-3c2e-4522-b0d6-a4483caedbe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33275
13998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3327513998
Directory /workspace/11.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.2897239327
Short name T258
Test name
Test status
Simulation time 1624078038 ps
CPU time 14.88 seconds
Started Aug 02 05:29:29 PM PDT 24
Finished Aug 02 05:29:44 PM PDT 24
Peak memory 217352 kb
Host smart-051cd6f9-860b-4a35-b03e-cc1b2e8db3cc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2897239327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.2897239327
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.668812769
Short name T2192
Test name
Test status
Simulation time 233990826 ps
CPU time 1.02 seconds
Started Aug 02 05:29:26 PM PDT 24
Finished Aug 02 05:29:27 PM PDT 24
Peak memory 207424 kb
Host smart-57e7e030-106b-4f8c-b072-2ef0bdcda1dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=668812769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.668812769
Directory /workspace/11.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.344224722
Short name T2760
Test name
Test status
Simulation time 192633230 ps
CPU time 0.92 seconds
Started Aug 02 05:29:26 PM PDT 24
Finished Aug 02 05:29:27 PM PDT 24
Peak memory 207388 kb
Host smart-a7934982-24ee-4806-bf5e-07928b06d63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34422
4722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.344224722
Directory /workspace/11.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_max_non_iso_usb_traffic.3551181739
Short name T1993
Test name
Test status
Simulation time 1629210887 ps
CPU time 12.91 seconds
Started Aug 02 05:29:27 PM PDT 24
Finished Aug 02 05:29:40 PM PDT 24
Peak memory 217544 kb
Host smart-e9c22721-0aa7-4e32-af22-b7a51c56e905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35511
81739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_non_iso_usb_traffic.3551181739
Directory /workspace/11.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.1879218108
Short name T3096
Test name
Test status
Simulation time 2505633066 ps
CPU time 74.2 seconds
Started Aug 02 05:29:26 PM PDT 24
Finished Aug 02 05:30:41 PM PDT 24
Peak memory 217676 kb
Host smart-a9bab911-d503-4659-b43a-4cd76602a8e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1879218108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.1879218108
Directory /workspace/11.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3209269454
Short name T2372
Test name
Test status
Simulation time 2438070400 ps
CPU time 18.6 seconds
Started Aug 02 05:29:26 PM PDT 24
Finished Aug 02 05:29:45 PM PDT 24
Peak memory 215860 kb
Host smart-7faa3452-2ec3-4ad3-99d1-d296d6f64f0b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3209269454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3209269454
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.1692422128
Short name T628
Test name
Test status
Simulation time 153693739 ps
CPU time 0.83 seconds
Started Aug 02 05:29:41 PM PDT 24
Finished Aug 02 05:29:42 PM PDT 24
Peak memory 207348 kb
Host smart-0bf4deb0-814b-4821-8850-5df60803fb3b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1692422128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.1692422128
Directory /workspace/11.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3547700095
Short name T2850
Test name
Test status
Simulation time 153362747 ps
CPU time 0.84 seconds
Started Aug 02 05:29:29 PM PDT 24
Finished Aug 02 05:29:30 PM PDT 24
Peak memory 207328 kb
Host smart-07c5a6fe-fd96-40fd-832b-a54b57a6743b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35477
00095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3547700095
Directory /workspace/11.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_out_iso.2032460388
Short name T604
Test name
Test status
Simulation time 199395838 ps
CPU time 0.96 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207388 kb
Host smart-9c9d7ab7-9173-47b6-a6ce-28e28cbe4002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20324
60388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2032460388
Directory /workspace/11.usbdev_out_iso/latest


Test location /workspace/coverage/default/11.usbdev_out_stall.3683869496
Short name T2576
Test name
Test status
Simulation time 207384561 ps
CPU time 0.95 seconds
Started Aug 02 05:29:32 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207320 kb
Host smart-eace608f-f976-44e5-9c94-ac5ffff3abdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838
69496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3683869496
Directory /workspace/11.usbdev_out_stall/latest


Test location /workspace/coverage/default/11.usbdev_out_trans_nak.1856606116
Short name T2716
Test name
Test status
Simulation time 171336730 ps
CPU time 0.83 seconds
Started Aug 02 05:29:32 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207356 kb
Host smart-b21fb856-4fd6-4b50-b5c5-0534046bf7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18566
06116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.1856606116
Directory /workspace/11.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/11.usbdev_pending_in_trans.118317628
Short name T1454
Test name
Test status
Simulation time 167323346 ps
CPU time 0.91 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207336 kb
Host smart-85d80894-5b60-4aa5-a02e-68adb4508c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11831
7628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.118317628
Directory /workspace/11.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1665250473
Short name T2893
Test name
Test status
Simulation time 224493977 ps
CPU time 1.01 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:32 PM PDT 24
Peak memory 207424 kb
Host smart-26c11ff2-3e08-483d-ae7e-a646625b5aa8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1665250473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1665250473
Directory /workspace/11.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2530663254
Short name T39
Test name
Test status
Simulation time 34701016 ps
CPU time 0.7 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207308 kb
Host smart-7c9340f0-7998-4aa6-b883-646a56af69b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25306
63254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2530663254
Directory /workspace/11.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/11.usbdev_pkt_buffer.4149193635
Short name T2550
Test name
Test status
Simulation time 21965277171 ps
CPU time 54.8 seconds
Started Aug 02 05:29:30 PM PDT 24
Finished Aug 02 05:30:25 PM PDT 24
Peak memory 220596 kb
Host smart-565e6202-9d21-4284-8667-e6034fbe81c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41491
93635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.4149193635
Directory /workspace/11.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/11.usbdev_pkt_received.3165667596
Short name T1601
Test name
Test status
Simulation time 178706512 ps
CPU time 0.93 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207392 kb
Host smart-b94f0c2e-358e-4b61-9f32-d3ceab1582c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31656
67596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3165667596
Directory /workspace/11.usbdev_pkt_received/latest


Test location /workspace/coverage/default/11.usbdev_pkt_sent.3019053095
Short name T1352
Test name
Test status
Simulation time 169822269 ps
CPU time 0.88 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207352 kb
Host smart-7ba75a67-8063-423e-9823-335c3747d031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30190
53095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.3019053095
Directory /workspace/11.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.3143224433
Short name T1001
Test name
Test status
Simulation time 205564559 ps
CPU time 0.95 seconds
Started Aug 02 05:29:32 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207312 kb
Host smart-2774a9c9-3ad9-4bec-8afa-a557f63dfb83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31432
24433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.3143224433
Directory /workspace/11.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.3960685763
Short name T2104
Test name
Test status
Simulation time 196172451 ps
CPU time 0.92 seconds
Started Aug 02 05:29:35 PM PDT 24
Finished Aug 02 05:29:36 PM PDT 24
Peak memory 207388 kb
Host smart-aaeb1919-fb97-42c1-a5d2-eed37311d21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39606
85763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.3960685763
Directory /workspace/11.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/11.usbdev_rx_crc_err.2258628923
Short name T3065
Test name
Test status
Simulation time 155933962 ps
CPU time 0.87 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:32 PM PDT 24
Peak memory 207392 kb
Host smart-acae1531-82fe-4c9b-ab3d-2cfa0fcbddbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22586
28923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.2258628923
Directory /workspace/11.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/11.usbdev_rx_full.3236446999
Short name T2784
Test name
Test status
Simulation time 309933837 ps
CPU time 1.18 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:32 PM PDT 24
Peak memory 207368 kb
Host smart-bfee91ff-f0b0-4d50-ab93-31e60170e087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32364
46999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_full.3236446999
Directory /workspace/11.usbdev_rx_full/latest


Test location /workspace/coverage/default/11.usbdev_setup_stage.1904692407
Short name T2471
Test name
Test status
Simulation time 154614644 ps
CPU time 0.84 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:32 PM PDT 24
Peak memory 207384 kb
Host smart-8e521617-58e5-4058-a146-fc1ea0646784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19046
92407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.1904692407
Directory /workspace/11.usbdev_setup_stage/latest


Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2295690434
Short name T966
Test name
Test status
Simulation time 164769279 ps
CPU time 0.9 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207384 kb
Host smart-bf9f6d9a-261e-4035-8ff0-c5f8a8c1c75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956
90434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2295690434
Directory /workspace/11.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/11.usbdev_smoke.3516675534
Short name T1711
Test name
Test status
Simulation time 215891186 ps
CPU time 1.02 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207344 kb
Host smart-a04fbd22-40d4-40b8-9822-715b2c01a636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35166
75534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.3516675534
Directory /workspace/11.usbdev_smoke/latest


Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2968317599
Short name T1086
Test name
Test status
Simulation time 2113991502 ps
CPU time 58.33 seconds
Started Aug 02 05:29:30 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 217364 kb
Host smart-8871be97-4276-49cd-9902-01281e8179b9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2968317599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2968317599
Directory /workspace/11.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2286452563
Short name T1760
Test name
Test status
Simulation time 178280207 ps
CPU time 0.92 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:32 PM PDT 24
Peak memory 207392 kb
Host smart-cc8df8f3-50a6-4683-b365-c8a13311ae78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22864
52563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2286452563
Directory /workspace/11.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/11.usbdev_stall_trans.4182273509
Short name T1334
Test name
Test status
Simulation time 181175438 ps
CPU time 0.93 seconds
Started Aug 02 05:29:32 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207424 kb
Host smart-e03f85ac-ee94-48b5-9acc-92fbadd52447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41822
73509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.4182273509
Directory /workspace/11.usbdev_stall_trans/latest


Test location /workspace/coverage/default/11.usbdev_stream_len_max.3547387336
Short name T1608
Test name
Test status
Simulation time 1050009639 ps
CPU time 2.46 seconds
Started Aug 02 05:29:39 PM PDT 24
Finished Aug 02 05:29:42 PM PDT 24
Peak memory 207544 kb
Host smart-59f67ffb-30b8-46b4-8f89-ba0a70e92951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35473
87336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.3547387336
Directory /workspace/11.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/11.usbdev_streaming_out.2441965500
Short name T2742
Test name
Test status
Simulation time 3231140388 ps
CPU time 89.58 seconds
Started Aug 02 05:29:34 PM PDT 24
Finished Aug 02 05:31:04 PM PDT 24
Peak memory 215832 kb
Host smart-6e615731-e7fb-4add-b011-f8af5bb349ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24419
65500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2441965500
Directory /workspace/11.usbdev_streaming_out/latest


Test location /workspace/coverage/default/11.usbdev_timeout_missing_host_handshake.386385823
Short name T761
Test name
Test status
Simulation time 3873002460 ps
CPU time 33.37 seconds
Started Aug 02 05:29:26 PM PDT 24
Finished Aug 02 05:29:59 PM PDT 24
Peak memory 207704 kb
Host smart-0519aa5e-e2e0-43e3-94dc-0dbd7b94caed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386385823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_timeout_missing_host
_handshake.386385823
Directory /workspace/11.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/110.usbdev_endpoint_types.1171687669
Short name T456
Test name
Test status
Simulation time 387508312 ps
CPU time 1.25 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207356 kb
Host smart-7c12fd6b-90e3-42eb-a507-e55d29f657cd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1171687669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.usbdev_endpoint_types.1171687669
Directory /workspace/110.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/111.usbdev_endpoint_types.3248527449
Short name T3007
Test name
Test status
Simulation time 406346431 ps
CPU time 1.23 seconds
Started Aug 02 05:35:08 PM PDT 24
Finished Aug 02 05:35:09 PM PDT 24
Peak memory 207292 kb
Host smart-2eca9c54-0393-48e6-8286-ee4657beb953
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3248527449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.usbdev_endpoint_types.3248527449
Directory /workspace/111.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/113.usbdev_endpoint_types.645813119
Short name T2367
Test name
Test status
Simulation time 429794211 ps
CPU time 1.3 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:08 PM PDT 24
Peak memory 207180 kb
Host smart-53d23d30-2ee4-488c-a953-68eab543f4b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=645813119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.usbdev_endpoint_types.645813119
Directory /workspace/113.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/114.usbdev_endpoint_types.2824048952
Short name T462
Test name
Test status
Simulation time 884435855 ps
CPU time 1.92 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207332 kb
Host smart-033150fd-31fb-42ed-941e-6a5406e40191
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2824048952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.usbdev_endpoint_types.2824048952
Directory /workspace/114.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/115.usbdev_endpoint_types.2245380391
Short name T2892
Test name
Test status
Simulation time 514004216 ps
CPU time 1.35 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207360 kb
Host smart-90926b26-5491-45cc-8fef-717d92df944d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2245380391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.usbdev_endpoint_types.2245380391
Directory /workspace/115.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/116.usbdev_endpoint_types.4181825136
Short name T441
Test name
Test status
Simulation time 347822824 ps
CPU time 1.16 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207288 kb
Host smart-84316376-4b46-4edd-ad9b-5d057ff5a58d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4181825136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.usbdev_endpoint_types.4181825136
Directory /workspace/116.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/118.usbdev_endpoint_types.1315499550
Short name T468
Test name
Test status
Simulation time 415631416 ps
CPU time 1.19 seconds
Started Aug 02 05:34:58 PM PDT 24
Finished Aug 02 05:34:59 PM PDT 24
Peak memory 207288 kb
Host smart-987aa003-1b8f-4579-9b09-e8b5b8deae35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1315499550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.usbdev_endpoint_types.1315499550
Directory /workspace/118.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/119.usbdev_endpoint_types.3277586451
Short name T483
Test name
Test status
Simulation time 196953061 ps
CPU time 0.9 seconds
Started Aug 02 05:34:58 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207440 kb
Host smart-57fa5f56-ba66-46a6-874e-efe487d3b62b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3277586451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.usbdev_endpoint_types.3277586451
Directory /workspace/119.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/12.usbdev_alert_test.3503050365
Short name T2863
Test name
Test status
Simulation time 39986399 ps
CPU time 0.67 seconds
Started Aug 02 05:29:42 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 207468 kb
Host smart-2a5bc81b-f70c-4a93-97c2-64ab439c964d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3503050365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.3503050365
Directory /workspace/12.usbdev_alert_test/latest


Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.13757596
Short name T2001
Test name
Test status
Simulation time 5887997422 ps
CPU time 7.9 seconds
Started Aug 02 05:29:38 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 215808 kb
Host smart-ce3d8b73-be0d-4f33-a3f8-a98249b24be9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13757596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon
_wake_disconnect.13757596
Directory /workspace/12.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.4150545049
Short name T2385
Test name
Test status
Simulation time 15881588959 ps
CPU time 18.73 seconds
Started Aug 02 05:29:38 PM PDT 24
Finished Aug 02 05:29:57 PM PDT 24
Peak memory 215808 kb
Host smart-bf4f3a69-0ac6-4653-bc9c-ad8a6275367a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150545049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.4150545049
Directory /workspace/12.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2110400099
Short name T1359
Test name
Test status
Simulation time 24071258510 ps
CPU time 30.1 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:30:03 PM PDT 24
Peak memory 215844 kb
Host smart-dd161322-f3ec-4904-a799-826af7255cd9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110400099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_a
on_wake_resume.2110400099
Directory /workspace/12.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/12.usbdev_av_buffer.384915043
Short name T886
Test name
Test status
Simulation time 222068169 ps
CPU time 0.98 seconds
Started Aug 02 05:29:32 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207352 kb
Host smart-ef26bdc1-8d30-44d0-9ff3-7bfa487b7dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38491
5043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.384915043
Directory /workspace/12.usbdev_av_buffer/latest


Test location /workspace/coverage/default/12.usbdev_bitstuff_err.4121319960
Short name T1813
Test name
Test status
Simulation time 205323436 ps
CPU time 0.89 seconds
Started Aug 02 05:29:32 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207380 kb
Host smart-34cd1b74-74da-42fa-8916-92dfe80d5212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41213
19960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.4121319960
Directory /workspace/12.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3808065481
Short name T2787
Test name
Test status
Simulation time 305261306 ps
CPU time 1.25 seconds
Started Aug 02 05:29:30 PM PDT 24
Finished Aug 02 05:29:32 PM PDT 24
Peak memory 207360 kb
Host smart-59f881e4-d2ff-475e-8b98-72848e727d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38080
65481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3808065481
Directory /workspace/12.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.65317519
Short name T2444
Test name
Test status
Simulation time 475242705 ps
CPU time 1.49 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:32 PM PDT 24
Peak memory 207436 kb
Host smart-9ef53d10-beaf-4565-b2ea-6a1ee166c690
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=65317519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.65317519
Directory /workspace/12.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/12.usbdev_device_address.2807079171
Short name T2283
Test name
Test status
Simulation time 33192202920 ps
CPU time 52.55 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:30:37 PM PDT 24
Peak memory 207716 kb
Host smart-1dc383f1-def3-409d-bd66-21bc36de418b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28070
79171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.2807079171
Directory /workspace/12.usbdev_device_address/latest


Test location /workspace/coverage/default/12.usbdev_device_timeout.63982425
Short name T2182
Test name
Test status
Simulation time 2217074146 ps
CPU time 14.26 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207712 kb
Host smart-e9314e0f-1971-487a-a59d-92ef09725dd4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63982425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_timeout.63982425
Directory /workspace/12.usbdev_device_timeout/latest


Test location /workspace/coverage/default/12.usbdev_disable_endpoint.2944290680
Short name T340
Test name
Test status
Simulation time 834623651 ps
CPU time 1.96 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207360 kb
Host smart-f7d05973-6d2f-478a-a1fa-b7aa55bccb83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442
90680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2944290680
Directory /workspace/12.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/12.usbdev_disconnected.2787127031
Short name T1168
Test name
Test status
Simulation time 153629741 ps
CPU time 0.82 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207324 kb
Host smart-6b5a316d-5e98-428a-9b1b-7da852b1b9dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27871
27031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.2787127031
Directory /workspace/12.usbdev_disconnected/latest


Test location /workspace/coverage/default/12.usbdev_enable.617598466
Short name T2545
Test name
Test status
Simulation time 54882128 ps
CPU time 0.81 seconds
Started Aug 02 05:29:36 PM PDT 24
Finished Aug 02 05:29:37 PM PDT 24
Peak memory 207372 kb
Host smart-97565edd-4017-4d34-aedf-1f16dcbe5896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61759
8466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.617598466
Directory /workspace/12.usbdev_enable/latest


Test location /workspace/coverage/default/12.usbdev_endpoint_access.3439126846
Short name T2439
Test name
Test status
Simulation time 925283287 ps
CPU time 2.44 seconds
Started Aug 02 05:29:31 PM PDT 24
Finished Aug 02 05:29:33 PM PDT 24
Peak memory 207568 kb
Host smart-309d672a-fd6c-4f58-b1e5-4581474207e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34391
26846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3439126846
Directory /workspace/12.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/12.usbdev_endpoint_types.1723999392
Short name T2884
Test name
Test status
Simulation time 203364369 ps
CPU time 0.96 seconds
Started Aug 02 05:29:36 PM PDT 24
Finished Aug 02 05:29:37 PM PDT 24
Peak memory 207408 kb
Host smart-59cee016-c6d9-4033-a05e-62f244c600e9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1723999392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_types.1723999392
Directory /workspace/12.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/12.usbdev_fifo_rst.2383197534
Short name T1326
Test name
Test status
Simulation time 325152235 ps
CPU time 2.5 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207580 kb
Host smart-09beab13-38eb-473b-aee0-ea03d2ed25f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23831
97534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2383197534
Directory /workspace/12.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/12.usbdev_in_iso.2434890840
Short name T2754
Test name
Test status
Simulation time 237381531 ps
CPU time 1.19 seconds
Started Aug 02 05:29:37 PM PDT 24
Finished Aug 02 05:29:39 PM PDT 24
Peak memory 215716 kb
Host smart-8b5c9ad6-1121-43a3-9d22-e6400c524124
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2434890840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.2434890840
Directory /workspace/12.usbdev_in_iso/latest


Test location /workspace/coverage/default/12.usbdev_in_stall.415787741
Short name T1244
Test name
Test status
Simulation time 153922675 ps
CPU time 0.8 seconds
Started Aug 02 05:29:30 PM PDT 24
Finished Aug 02 05:29:31 PM PDT 24
Peak memory 207360 kb
Host smart-bbf07bb4-b816-4d32-bd0a-19b29da3cc56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41578
7741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.415787741
Directory /workspace/12.usbdev_in_stall/latest


Test location /workspace/coverage/default/12.usbdev_in_trans.2773869568
Short name T1019
Test name
Test status
Simulation time 230964189 ps
CPU time 1.03 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207448 kb
Host smart-55e3038e-5388-40d9-a299-7a165337f1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27738
69568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2773869568
Directory /workspace/12.usbdev_in_trans/latest


Test location /workspace/coverage/default/12.usbdev_invalid_sync.2442140036
Short name T2750
Test name
Test status
Simulation time 4583157883 ps
CPU time 33.96 seconds
Started Aug 02 05:29:35 PM PDT 24
Finished Aug 02 05:30:09 PM PDT 24
Peak memory 218292 kb
Host smart-a47689ad-4217-4117-96cd-5f818cb576eb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2442140036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.2442140036
Directory /workspace/12.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/12.usbdev_iso_retraction.4009094008
Short name T965
Test name
Test status
Simulation time 5824590333 ps
CPU time 68.03 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207560 kb
Host smart-ecff57c9-3ff2-4687-a66d-5d60a0f1c09d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4009094008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.4009094008
Directory /workspace/12.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/12.usbdev_link_in_err.3590324496
Short name T1920
Test name
Test status
Simulation time 230128652 ps
CPU time 1.04 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207404 kb
Host smart-2b87bbc1-9b1b-47ea-aec2-aa24b672ec80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35903
24496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3590324496
Directory /workspace/12.usbdev_link_in_err/latest


Test location /workspace/coverage/default/12.usbdev_link_resume.1996804956
Short name T2963
Test name
Test status
Simulation time 8807721182 ps
CPU time 11.02 seconds
Started Aug 02 05:29:35 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 215848 kb
Host smart-51134543-def9-4397-95b2-6c45f3feb270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19968
04956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1996804956
Directory /workspace/12.usbdev_link_resume/latest


Test location /workspace/coverage/default/12.usbdev_link_suspend.548993991
Short name T1219
Test name
Test status
Simulation time 8382214902 ps
CPU time 11.9 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:29:56 PM PDT 24
Peak memory 207668 kb
Host smart-6278ab49-4200-4985-b188-752251949327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54899
3991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.548993991
Directory /workspace/12.usbdev_link_suspend/latest


Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2319250852
Short name T1070
Test name
Test status
Simulation time 4333200464 ps
CPU time 119 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:31:32 PM PDT 24
Peak memory 215872 kb
Host smart-5975cc8a-f792-4f44-b88b-f47edee79dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23192
50852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2319250852
Directory /workspace/12.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.758765936
Short name T2692
Test name
Test status
Simulation time 3555458005 ps
CPU time 106.9 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 217188 kb
Host smart-52bde227-b034-4467-8c8a-ebd941399acd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=758765936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.758765936
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3518619987
Short name T2446
Test name
Test status
Simulation time 237944825 ps
CPU time 1 seconds
Started Aug 02 05:29:33 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 207416 kb
Host smart-35bff397-90e0-4b59-920d-eb12733ebfc6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3518619987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3518619987
Directory /workspace/12.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.3963905752
Short name T863
Test name
Test status
Simulation time 189787604 ps
CPU time 0.89 seconds
Started Aug 02 05:29:35 PM PDT 24
Finished Aug 02 05:29:36 PM PDT 24
Peak memory 207388 kb
Host smart-25149a6a-7eb7-43b5-81d3-d48ef036edd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39639
05752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.3963905752
Directory /workspace/12.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_max_non_iso_usb_traffic.3904387736
Short name T3045
Test name
Test status
Simulation time 1478001613 ps
CPU time 40.34 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:30:25 PM PDT 24
Peak memory 217336 kb
Host smart-db1882f8-ac0d-4589-a203-bcacd6d5571a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39043
87736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_non_iso_usb_traffic.3904387736
Directory /workspace/12.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.3655075658
Short name T2797
Test name
Test status
Simulation time 2032389380 ps
CPU time 19.83 seconds
Started Aug 02 05:29:36 PM PDT 24
Finished Aug 02 05:29:56 PM PDT 24
Peak memory 217444 kb
Host smart-304c0cba-dd54-400c-b2e4-65472402c47a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3655075658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.3655075658
Directory /workspace/12.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.576003290
Short name T1058
Test name
Test status
Simulation time 157545782 ps
CPU time 0.85 seconds
Started Aug 02 05:29:37 PM PDT 24
Finished Aug 02 05:29:38 PM PDT 24
Peak memory 207360 kb
Host smart-2f1ba354-ba66-4aae-b67b-b5a9a29f6d47
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=576003290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.576003290
Directory /workspace/12.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1434153331
Short name T747
Test name
Test status
Simulation time 169108312 ps
CPU time 0.83 seconds
Started Aug 02 05:29:39 PM PDT 24
Finished Aug 02 05:29:40 PM PDT 24
Peak memory 207412 kb
Host smart-0f47e086-e800-410a-bc86-9af689c4c133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14341
53331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1434153331
Directory /workspace/12.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_out_iso.3874179592
Short name T2769
Test name
Test status
Simulation time 172302513 ps
CPU time 0.94 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:29:45 PM PDT 24
Peak memory 207396 kb
Host smart-1754933a-7e04-4087-abcf-9f2e3d3ddb41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38741
79592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3874179592
Directory /workspace/12.usbdev_out_iso/latest


Test location /workspace/coverage/default/12.usbdev_out_stall.1964798749
Short name T2047
Test name
Test status
Simulation time 193126928 ps
CPU time 0.97 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:42 PM PDT 24
Peak memory 207432 kb
Host smart-2fa1e1eb-163a-408b-af25-53d0f3161099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19647
98749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1964798749
Directory /workspace/12.usbdev_out_stall/latest


Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3345714576
Short name T2896
Test name
Test status
Simulation time 177445863 ps
CPU time 0.92 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 207412 kb
Host smart-922f53fd-e1db-4614-8838-78c24c712b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33457
14576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3345714576
Directory /workspace/12.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2671612287
Short name T183
Test name
Test status
Simulation time 174065213 ps
CPU time 0.91 seconds
Started Aug 02 05:29:41 PM PDT 24
Finished Aug 02 05:29:42 PM PDT 24
Peak memory 207368 kb
Host smart-55c4f6d2-b592-4bea-9398-8f182968cb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26716
12287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2671612287
Directory /workspace/12.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.756284904
Short name T1223
Test name
Test status
Simulation time 284759940 ps
CPU time 1.04 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:41 PM PDT 24
Peak memory 207432 kb
Host smart-9684d1ce-2f13-4892-804a-a069d6442026
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=756284904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.756284904
Directory /workspace/12.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.338123539
Short name T2829
Test name
Test status
Simulation time 145032009 ps
CPU time 0.91 seconds
Started Aug 02 05:29:39 PM PDT 24
Finished Aug 02 05:29:40 PM PDT 24
Peak memory 207344 kb
Host smart-26b43cf9-7766-4641-8286-9bbe0692d9ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33812
3539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.338123539
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2594585196
Short name T1280
Test name
Test status
Simulation time 6777661951 ps
CPU time 16.75 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:56 PM PDT 24
Peak memory 215960 kb
Host smart-c69050e4-8942-49fc-b231-1a8eea07b13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25945
85196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2594585196
Directory /workspace/12.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/12.usbdev_pkt_received.1586010231
Short name T1694
Test name
Test status
Simulation time 146740328 ps
CPU time 0.89 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:41 PM PDT 24
Peak memory 207460 kb
Host smart-a141a9ce-5755-4011-a830-08d83003c99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15860
10231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1586010231
Directory /workspace/12.usbdev_pkt_received/latest


Test location /workspace/coverage/default/12.usbdev_pkt_sent.3926885132
Short name T2916
Test name
Test status
Simulation time 168825651 ps
CPU time 0.91 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:41 PM PDT 24
Peak memory 207380 kb
Host smart-b7df2bb5-f9ba-437d-9680-4b103966290f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39268
85132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3926885132
Directory /workspace/12.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1518519685
Short name T1288
Test name
Test status
Simulation time 257304204 ps
CPU time 0.99 seconds
Started Aug 02 05:29:42 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 207352 kb
Host smart-8d384acb-ee32-4f9a-8218-2e375b696caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15185
19685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1518519685
Directory /workspace/12.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.4108352776
Short name T2719
Test name
Test status
Simulation time 221724882 ps
CPU time 0.9 seconds
Started Aug 02 05:29:50 PM PDT 24
Finished Aug 02 05:29:51 PM PDT 24
Peak memory 207312 kb
Host smart-d0dbd217-e37f-4507-a595-9f02675e91ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41083
52776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.4108352776
Directory /workspace/12.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/12.usbdev_rx_full.337899168
Short name T3070
Test name
Test status
Simulation time 289567196 ps
CPU time 1.17 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207380 kb
Host smart-21257ea0-0113-4b70-bcdf-0cc4afcfc214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33789
9168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_full.337899168
Directory /workspace/12.usbdev_rx_full/latest


Test location /workspace/coverage/default/12.usbdev_setup_stage.1207171518
Short name T1232
Test name
Test status
Simulation time 188010745 ps
CPU time 0.85 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:29:45 PM PDT 24
Peak memory 207372 kb
Host smart-7ca61cf8-2a95-46fe-a474-80729c8da62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12071
71518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1207171518
Directory /workspace/12.usbdev_setup_stage/latest


Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1472579738
Short name T1333
Test name
Test status
Simulation time 162547745 ps
CPU time 0.82 seconds
Started Aug 02 05:29:39 PM PDT 24
Finished Aug 02 05:29:40 PM PDT 24
Peak memory 207400 kb
Host smart-4c27c467-7bd1-46b0-867e-f2a719215bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14725
79738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1472579738
Directory /workspace/12.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/12.usbdev_smoke.1413424593
Short name T684
Test name
Test status
Simulation time 252505478 ps
CPU time 1.02 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:29:54 PM PDT 24
Peak memory 207408 kb
Host smart-fb71f779-4a06-4e29-876a-795240384a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14134
24593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1413424593
Directory /workspace/12.usbdev_smoke/latest


Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2307830344
Short name T1958
Test name
Test status
Simulation time 1775658169 ps
CPU time 12.83 seconds
Started Aug 02 05:29:42 PM PDT 24
Finished Aug 02 05:29:55 PM PDT 24
Peak memory 215792 kb
Host smart-a9d58dd7-672a-4ea3-964b-6eb823128c70
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2307830344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2307830344
Directory /workspace/12.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.2705388410
Short name T756
Test name
Test status
Simulation time 178156374 ps
CPU time 0.9 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207316 kb
Host smart-1143b410-866e-428f-8d03-d270022facdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27053
88410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.2705388410
Directory /workspace/12.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/12.usbdev_stall_trans.2359640115
Short name T1931
Test name
Test status
Simulation time 176576529 ps
CPU time 0.85 seconds
Started Aug 02 05:29:39 PM PDT 24
Finished Aug 02 05:29:40 PM PDT 24
Peak memory 207444 kb
Host smart-a463e311-7dd0-42bd-933e-a0a19a0ada39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23596
40115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2359640115
Directory /workspace/12.usbdev_stall_trans/latest


Test location /workspace/coverage/default/12.usbdev_stream_len_max.3624152608
Short name T1195
Test name
Test status
Simulation time 1209332329 ps
CPU time 2.95 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 207496 kb
Host smart-41520641-3bfb-48d2-8cfa-66fb7ead9d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36241
52608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3624152608
Directory /workspace/12.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/12.usbdev_streaming_out.3070518646
Short name T348
Test name
Test status
Simulation time 3589574103 ps
CPU time 98.8 seconds
Started Aug 02 05:29:42 PM PDT 24
Finished Aug 02 05:31:21 PM PDT 24
Peak memory 217356 kb
Host smart-16fbce2c-1de3-43fc-9f47-bd27edf52c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30705
18646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3070518646
Directory /workspace/12.usbdev_streaming_out/latest


Test location /workspace/coverage/default/12.usbdev_timeout_missing_host_handshake.3093517143
Short name T537
Test name
Test status
Simulation time 1513147122 ps
CPU time 12.93 seconds
Started Aug 02 05:29:30 PM PDT 24
Finished Aug 02 05:29:44 PM PDT 24
Peak memory 207472 kb
Host smart-adcb16d2-c3ba-490d-870f-0789dea73278
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093517143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_timeout_missing_hos
t_handshake.3093517143
Directory /workspace/12.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/121.usbdev_endpoint_types.1291980161
Short name T2827
Test name
Test status
Simulation time 249197232 ps
CPU time 0.95 seconds
Started Aug 02 05:34:59 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 207392 kb
Host smart-24fb7bea-a5c0-4612-b7db-6e08dd125213
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1291980161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.usbdev_endpoint_types.1291980161
Directory /workspace/121.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/122.usbdev_endpoint_types.1711970818
Short name T461
Test name
Test status
Simulation time 358274025 ps
CPU time 1.12 seconds
Started Aug 02 05:34:53 PM PDT 24
Finished Aug 02 05:34:55 PM PDT 24
Peak memory 207396 kb
Host smart-677d3b34-bb01-41a1-94e0-9c878108de08
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1711970818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.usbdev_endpoint_types.1711970818
Directory /workspace/122.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/123.usbdev_endpoint_types.2955247396
Short name T686
Test name
Test status
Simulation time 144937559 ps
CPU time 0.82 seconds
Started Aug 02 05:35:10 PM PDT 24
Finished Aug 02 05:35:11 PM PDT 24
Peak memory 207380 kb
Host smart-469fb7a4-524f-49ac-a316-49e69604cdf9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2955247396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.usbdev_endpoint_types.2955247396
Directory /workspace/123.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/124.usbdev_endpoint_types.2757813385
Short name T430
Test name
Test status
Simulation time 523538824 ps
CPU time 1.35 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207320 kb
Host smart-2e70b72a-fbc9-4b13-936f-3fb4b7f08636
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2757813385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.usbdev_endpoint_types.2757813385
Directory /workspace/124.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/125.usbdev_endpoint_types.3227563105
Short name T422
Test name
Test status
Simulation time 375956666 ps
CPU time 1.23 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207340 kb
Host smart-6e0c80f5-d213-445b-8641-36397f7666de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3227563105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.usbdev_endpoint_types.3227563105
Directory /workspace/125.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/126.usbdev_endpoint_types.4012443457
Short name T2875
Test name
Test status
Simulation time 362990542 ps
CPU time 1.24 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207292 kb
Host smart-3d4a45df-b4d2-4660-93db-6ed47c3243ce
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4012443457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.usbdev_endpoint_types.4012443457
Directory /workspace/126.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/127.usbdev_endpoint_types.633808041
Short name T373
Test name
Test status
Simulation time 510600683 ps
CPU time 1.34 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207308 kb
Host smart-24bbe92b-72f3-4702-9e51-a462070c7d50
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=633808041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.usbdev_endpoint_types.633808041
Directory /workspace/127.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/129.usbdev_endpoint_types.1530503765
Short name T479
Test name
Test status
Simulation time 403335868 ps
CPU time 1.3 seconds
Started Aug 02 05:35:13 PM PDT 24
Finished Aug 02 05:35:14 PM PDT 24
Peak memory 207176 kb
Host smart-07212a03-52d8-49b5-9c85-5ffe4ff8e69f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1530503765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.usbdev_endpoint_types.1530503765
Directory /workspace/129.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/13.usbdev_alert_test.1425138776
Short name T2086
Test name
Test status
Simulation time 76050539 ps
CPU time 0.7 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 207472 kb
Host smart-97f241e5-f4f5-4244-9855-a802a02467be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1425138776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1425138776
Directory /workspace/13.usbdev_alert_test/latest


Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3901510951
Short name T815
Test name
Test status
Simulation time 6201209083 ps
CPU time 8.33 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:48 PM PDT 24
Peak memory 215864 kb
Host smart-f24bf310-1f42-4073-ad68-3915173f660a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901510951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_disconnect.3901510951
Directory /workspace/13.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.2087391603
Short name T1245
Test name
Test status
Simulation time 19332148128 ps
CPU time 22.39 seconds
Started Aug 02 05:29:43 PM PDT 24
Finished Aug 02 05:30:05 PM PDT 24
Peak memory 207632 kb
Host smart-381111c7-2ad3-47e9-92e4-a6d10b6ba238
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087391603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.2087391603
Directory /workspace/13.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3181077107
Short name T1208
Test name
Test status
Simulation time 25682928927 ps
CPU time 31.17 seconds
Started Aug 02 05:29:42 PM PDT 24
Finished Aug 02 05:30:13 PM PDT 24
Peak memory 215848 kb
Host smart-3baa91e5-abec-47cf-89b3-0ab9f41c8d38
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181077107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_a
on_wake_resume.3181077107
Directory /workspace/13.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/13.usbdev_av_buffer.902717896
Short name T2803
Test name
Test status
Simulation time 144678612 ps
CPU time 0.88 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207312 kb
Host smart-1c2bddad-e10d-440a-91a2-f7e2d55dcc25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90271
7896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.902717896
Directory /workspace/13.usbdev_av_buffer/latest


Test location /workspace/coverage/default/13.usbdev_bitstuff_err.4268018475
Short name T2945
Test name
Test status
Simulation time 184353132 ps
CPU time 0.85 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:29:45 PM PDT 24
Peak memory 207360 kb
Host smart-00df0f02-971a-4b5b-bdcb-ddb35cbe23f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42680
18475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.4268018475
Directory /workspace/13.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.1821830589
Short name T752
Test name
Test status
Simulation time 421189955 ps
CPU time 1.5 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:47 PM PDT 24
Peak memory 207404 kb
Host smart-41affeda-ebe7-48e0-a84a-663b15841cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18218
30589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.1821830589
Directory /workspace/13.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.439131582
Short name T19
Test name
Test status
Simulation time 871710592 ps
CPU time 2.26 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 207532 kb
Host smart-307db84e-6cb8-42e3-9e86-b750290b4fd2
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=439131582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.439131582
Directory /workspace/13.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/13.usbdev_device_address.1455299491
Short name T1645
Test name
Test status
Simulation time 27983401255 ps
CPU time 46.18 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:30:26 PM PDT 24
Peak memory 207664 kb
Host smart-bafbde83-d161-47e6-9b7c-d0c2f9ea470a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14552
99491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1455299491
Directory /workspace/13.usbdev_device_address/latest


Test location /workspace/coverage/default/13.usbdev_device_timeout.3195671498
Short name T3049
Test name
Test status
Simulation time 5718953435 ps
CPU time 36.42 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207648 kb
Host smart-9f5897db-130b-4a3b-9d71-3c0410478118
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195671498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_timeout.3195671498
Directory /workspace/13.usbdev_device_timeout/latest


Test location /workspace/coverage/default/13.usbdev_disable_endpoint.4249750505
Short name T720
Test name
Test status
Simulation time 713634171 ps
CPU time 1.87 seconds
Started Aug 02 05:29:41 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 207392 kb
Host smart-614ca7b4-9f6f-4bd4-8d7f-cc17169b8277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42497
50505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.4249750505
Directory /workspace/13.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/13.usbdev_disconnected.2708568214
Short name T2147
Test name
Test status
Simulation time 140664324 ps
CPU time 0.83 seconds
Started Aug 02 05:29:43 PM PDT 24
Finished Aug 02 05:29:44 PM PDT 24
Peak memory 207344 kb
Host smart-99479cbb-ed30-4ef7-88c7-758674149b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27085
68214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.2708568214
Directory /workspace/13.usbdev_disconnected/latest


Test location /workspace/coverage/default/13.usbdev_enable.2954603064
Short name T2567
Test name
Test status
Simulation time 32211151 ps
CPU time 0.69 seconds
Started Aug 02 05:29:40 PM PDT 24
Finished Aug 02 05:29:41 PM PDT 24
Peak memory 207324 kb
Host smart-350c248c-991e-4885-9254-f3636b94ac8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29546
03064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2954603064
Directory /workspace/13.usbdev_enable/latest


Test location /workspace/coverage/default/13.usbdev_endpoint_access.966475572
Short name T2091
Test name
Test status
Simulation time 1071504366 ps
CPU time 2.78 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:29:47 PM PDT 24
Peak memory 207668 kb
Host smart-9bda2e8d-2c85-4468-9cb7-a00cb758feff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96647
5572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.966475572
Directory /workspace/13.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/13.usbdev_endpoint_types.1304354154
Short name T437
Test name
Test status
Simulation time 359698771 ps
CPU time 1.23 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207324 kb
Host smart-254b535f-aecf-4b64-b660-f3a633ee5367
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1304354154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_types.1304354154
Directory /workspace/13.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/13.usbdev_fifo_rst.483358813
Short name T2925
Test name
Test status
Simulation time 163540947 ps
CPU time 1.65 seconds
Started Aug 02 05:29:46 PM PDT 24
Finished Aug 02 05:29:48 PM PDT 24
Peak memory 207552 kb
Host smart-cbab0359-419a-4441-8ef1-cb4f6febd7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48335
8813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.483358813
Directory /workspace/13.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/13.usbdev_in_iso.3661492986
Short name T2407
Test name
Test status
Simulation time 154491481 ps
CPU time 0.82 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:45 PM PDT 24
Peak memory 207340 kb
Host smart-6f30588d-af58-4efc-8f5d-9b0ab158cede
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3661492986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3661492986
Directory /workspace/13.usbdev_in_iso/latest


Test location /workspace/coverage/default/13.usbdev_in_stall.2171332711
Short name T695
Test name
Test status
Simulation time 144570194 ps
CPU time 0.82 seconds
Started Aug 02 05:29:48 PM PDT 24
Finished Aug 02 05:29:49 PM PDT 24
Peak memory 207380 kb
Host smart-dfce86c6-6c3b-4bc2-839f-d9d41cdc7fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21713
32711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2171332711
Directory /workspace/13.usbdev_in_stall/latest


Test location /workspace/coverage/default/13.usbdev_in_trans.527025967
Short name T2107
Test name
Test status
Simulation time 203226420 ps
CPU time 0.97 seconds
Started Aug 02 05:29:48 PM PDT 24
Finished Aug 02 05:29:50 PM PDT 24
Peak memory 207384 kb
Host smart-86c08a70-34e9-4c95-9fe2-3919dace88ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52702
5967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.527025967
Directory /workspace/13.usbdev_in_trans/latest


Test location /workspace/coverage/default/13.usbdev_invalid_sync.4114254831
Short name T122
Test name
Test status
Simulation time 4683832195 ps
CPU time 137.21 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 218288 kb
Host smart-a94bbca0-41bd-4662-8c3e-ca5189ade370
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4114254831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.4114254831
Directory /workspace/13.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/13.usbdev_iso_retraction.1053424829
Short name T1824
Test name
Test status
Simulation time 8241958168 ps
CPU time 55.3 seconds
Started Aug 02 05:29:46 PM PDT 24
Finished Aug 02 05:30:41 PM PDT 24
Peak memory 207560 kb
Host smart-84cf4a49-55a0-42e9-9814-c2f17652921e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1053424829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.1053424829
Directory /workspace/13.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/13.usbdev_link_in_err.172153739
Short name T2628
Test name
Test status
Simulation time 237041070 ps
CPU time 0.98 seconds
Started Aug 02 05:29:46 PM PDT 24
Finished Aug 02 05:29:47 PM PDT 24
Peak memory 207344 kb
Host smart-d3b9e2c2-1d46-4221-b89f-6066841b1411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17215
3739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.172153739
Directory /workspace/13.usbdev_link_in_err/latest


Test location /workspace/coverage/default/13.usbdev_link_resume.3644720761
Short name T3037
Test name
Test status
Simulation time 11900407346 ps
CPU time 13.71 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:17 PM PDT 24
Peak memory 207704 kb
Host smart-148cf16c-cdc8-4d39-b219-483c6bedf076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36447
20761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3644720761
Directory /workspace/13.usbdev_link_resume/latest


Test location /workspace/coverage/default/13.usbdev_link_suspend.1636833261
Short name T1377
Test name
Test status
Simulation time 10230122822 ps
CPU time 13.13 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:58 PM PDT 24
Peak memory 207628 kb
Host smart-12f57479-947a-4040-baf9-f1200527c9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16368
33261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.1636833261
Directory /workspace/13.usbdev_link_suspend/latest


Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.1933067475
Short name T1414
Test name
Test status
Simulation time 3162485086 ps
CPU time 87.02 seconds
Started Aug 02 05:29:46 PM PDT 24
Finished Aug 02 05:31:13 PM PDT 24
Peak memory 215892 kb
Host smart-dbb4d493-268f-4ebf-a0cf-a8d5e229c429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19330
67475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.1933067475
Directory /workspace/13.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.677511028
Short name T239
Test name
Test status
Simulation time 2740736299 ps
CPU time 75.19 seconds
Started Aug 02 05:29:46 PM PDT 24
Finished Aug 02 05:31:02 PM PDT 24
Peak memory 216008 kb
Host smart-9e6e1086-bb22-4107-bb9e-02f671575ecf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=677511028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.677511028
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1637656880
Short name T2732
Test name
Test status
Simulation time 296215150 ps
CPU time 1.03 seconds
Started Aug 02 05:29:47 PM PDT 24
Finished Aug 02 05:29:48 PM PDT 24
Peak memory 207420 kb
Host smart-5f23d173-2a6c-4dd4-b248-cc1e3c9ec347
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1637656880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1637656880
Directory /workspace/13.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.1277946265
Short name T1493
Test name
Test status
Simulation time 211159078 ps
CPU time 0.96 seconds
Started Aug 02 05:29:49 PM PDT 24
Finished Aug 02 05:29:50 PM PDT 24
Peak memory 207384 kb
Host smart-7c09bdde-e07d-4837-a0f9-7c7dfeb96bbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12779
46265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.1277946265
Directory /workspace/13.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_max_non_iso_usb_traffic.2800065083
Short name T1878
Test name
Test status
Simulation time 2245631396 ps
CPU time 16.47 seconds
Started Aug 02 05:29:47 PM PDT 24
Finished Aug 02 05:30:03 PM PDT 24
Peak memory 224040 kb
Host smart-a576c85c-60a6-4fe4-ba40-c421fc637c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28000
65083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_non_iso_usb_traffic.2800065083
Directory /workspace/13.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2870371179
Short name T1790
Test name
Test status
Simulation time 1863517665 ps
CPU time 53.27 seconds
Started Aug 02 05:29:46 PM PDT 24
Finished Aug 02 05:30:39 PM PDT 24
Peak memory 223940 kb
Host smart-977b8de2-88f5-4e6e-a6c0-6a1209bd6444
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2870371179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2870371179
Directory /workspace/13.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.619336194
Short name T2792
Test name
Test status
Simulation time 3577355829 ps
CPU time 99.94 seconds
Started Aug 02 05:29:47 PM PDT 24
Finished Aug 02 05:31:27 PM PDT 24
Peak memory 217464 kb
Host smart-57ab4247-8607-4cb5-a4dd-59bad051b964
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=619336194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.619336194
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2345161969
Short name T2739
Test name
Test status
Simulation time 150361924 ps
CPU time 0.92 seconds
Started Aug 02 05:29:46 PM PDT 24
Finished Aug 02 05:29:48 PM PDT 24
Peak memory 207452 kb
Host smart-bd6256ec-c5c9-4410-8ff7-51d2f5ed74ab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2345161969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2345161969
Directory /workspace/13.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2727660394
Short name T2510
Test name
Test status
Simulation time 157224168 ps
CPU time 0.88 seconds
Started Aug 02 05:29:46 PM PDT 24
Finished Aug 02 05:29:47 PM PDT 24
Peak memory 207368 kb
Host smart-d3e5ab19-6f99-45f1-ac99-cfafc4fef928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276
60394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2727660394
Directory /workspace/13.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_out_iso.3675337945
Short name T809
Test name
Test status
Simulation time 212879554 ps
CPU time 0.94 seconds
Started Aug 02 05:29:47 PM PDT 24
Finished Aug 02 05:29:49 PM PDT 24
Peak memory 207340 kb
Host smart-d25327a8-2ce1-4ff2-b6d7-e68b1dca661f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36753
37945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3675337945
Directory /workspace/13.usbdev_out_iso/latest


Test location /workspace/coverage/default/13.usbdev_out_stall.1915115914
Short name T2184
Test name
Test status
Simulation time 171127775 ps
CPU time 0.86 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207388 kb
Host smart-ed8421cb-b486-49a3-b609-8e3083d67410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19151
15914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.1915115914
Directory /workspace/13.usbdev_out_stall/latest


Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2406335338
Short name T691
Test name
Test status
Simulation time 188179488 ps
CPU time 0.92 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207368 kb
Host smart-60cd3fdd-d1e2-4440-87db-5cea150e0895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24063
35338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2406335338
Directory /workspace/13.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/13.usbdev_pending_in_trans.2520704074
Short name T3103
Test name
Test status
Simulation time 159858480 ps
CPU time 0.83 seconds
Started Aug 02 05:29:47 PM PDT 24
Finished Aug 02 05:29:48 PM PDT 24
Peak memory 207380 kb
Host smart-51c83078-1bea-48c7-9a42-504979eeb7f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25207
04074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.2520704074
Directory /workspace/13.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3415782807
Short name T2959
Test name
Test status
Simulation time 208275020 ps
CPU time 1.01 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207372 kb
Host smart-f6729ce3-6f81-4293-b54d-bad7a116b994
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3415782807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3415782807
Directory /workspace/13.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1162839093
Short name T1998
Test name
Test status
Simulation time 145746157 ps
CPU time 0.84 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207292 kb
Host smart-e09819c3-16e5-4bf5-a8ed-0e51de38c259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11628
39093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1162839093
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.951986836
Short name T852
Test name
Test status
Simulation time 33557757 ps
CPU time 0.69 seconds
Started Aug 02 05:29:49 PM PDT 24
Finished Aug 02 05:29:50 PM PDT 24
Peak memory 207392 kb
Host smart-fec85d74-560c-4ae7-8d73-90c74f37c3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95198
6836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.951986836
Directory /workspace/13.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1447123332
Short name T1850
Test name
Test status
Simulation time 18134608545 ps
CPU time 44.33 seconds
Started Aug 02 05:29:47 PM PDT 24
Finished Aug 02 05:30:32 PM PDT 24
Peak memory 215872 kb
Host smart-76a6b457-253d-40f8-99d9-532344534784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14471
23332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1447123332
Directory /workspace/13.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/13.usbdev_pkt_received.1885793151
Short name T1419
Test name
Test status
Simulation time 186848775 ps
CPU time 0.92 seconds
Started Aug 02 05:29:44 PM PDT 24
Finished Aug 02 05:29:45 PM PDT 24
Peak memory 207424 kb
Host smart-31f4c107-4503-4469-ac88-5f5a2e0e670d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18857
93151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1885793151
Directory /workspace/13.usbdev_pkt_received/latest


Test location /workspace/coverage/default/13.usbdev_pkt_sent.325892390
Short name T497
Test name
Test status
Simulation time 206750437 ps
CPU time 0.91 seconds
Started Aug 02 05:29:47 PM PDT 24
Finished Aug 02 05:29:48 PM PDT 24
Peak memory 207448 kb
Host smart-55d5a763-2ccd-4cda-9da3-e6f986da7afe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32589
2390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.325892390
Directory /workspace/13.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.2701606377
Short name T2900
Test name
Test status
Simulation time 161669177 ps
CPU time 0.83 seconds
Started Aug 02 05:29:57 PM PDT 24
Finished Aug 02 05:29:58 PM PDT 24
Peak memory 207428 kb
Host smart-3055ac3e-f2b1-4c10-8f80-fadfc6c45d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27016
06377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.2701606377
Directory /workspace/13.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1477337847
Short name T508
Test name
Test status
Simulation time 206917643 ps
CPU time 0.97 seconds
Started Aug 02 05:30:00 PM PDT 24
Finished Aug 02 05:30:02 PM PDT 24
Peak memory 207420 kb
Host smart-0a5b158a-5347-4e52-b5b8-02da4662ead5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14773
37847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1477337847
Directory /workspace/13.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2554889175
Short name T1299
Test name
Test status
Simulation time 184711175 ps
CPU time 0.91 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:29:54 PM PDT 24
Peak memory 207404 kb
Host smart-706fbf55-f120-4238-81a4-8169291d6ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25548
89175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2554889175
Directory /workspace/13.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/13.usbdev_rx_full.2413456211
Short name T3005
Test name
Test status
Simulation time 249843696 ps
CPU time 1.15 seconds
Started Aug 02 05:30:03 PM PDT 24
Finished Aug 02 05:30:04 PM PDT 24
Peak memory 207424 kb
Host smart-fef04dba-1277-40c2-bb26-9cf57b5134ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24134
56211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_full.2413456211
Directory /workspace/13.usbdev_rx_full/latest


Test location /workspace/coverage/default/13.usbdev_setup_stage.1258206739
Short name T2646
Test name
Test status
Simulation time 195990895 ps
CPU time 0.86 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:05 PM PDT 24
Peak memory 207400 kb
Host smart-fc74c57b-b4ce-42ef-8fb6-b22dd5e3d6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
06739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1258206739
Directory /workspace/13.usbdev_setup_stage/latest


Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.344757361
Short name T2909
Test name
Test status
Simulation time 164304470 ps
CPU time 0.84 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:29:54 PM PDT 24
Peak memory 207408 kb
Host smart-eeb5fdf4-6b47-4329-be1f-6fa0d8dacba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34475
7361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.344757361
Directory /workspace/13.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/13.usbdev_smoke.2765009856
Short name T2377
Test name
Test status
Simulation time 249469566 ps
CPU time 1.12 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:29:54 PM PDT 24
Peak memory 207408 kb
Host smart-19c8aab0-cc72-444d-a475-95c0fc25e565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27650
09856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.2765009856
Directory /workspace/13.usbdev_smoke/latest


Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3263304698
Short name T2075
Test name
Test status
Simulation time 1893927853 ps
CPU time 14.8 seconds
Started Aug 02 05:29:48 PM PDT 24
Finished Aug 02 05:30:03 PM PDT 24
Peak memory 217384 kb
Host smart-fede026e-0262-4fea-ac59-f940d1e467a0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3263304698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3263304698
Directory /workspace/13.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.628244454
Short name T712
Test name
Test status
Simulation time 185073562 ps
CPU time 0.91 seconds
Started Aug 02 05:29:58 PM PDT 24
Finished Aug 02 05:29:59 PM PDT 24
Peak memory 207432 kb
Host smart-d321c851-6d3b-4887-9531-e38ca7eee907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62824
4454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.628244454
Directory /workspace/13.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/13.usbdev_stall_trans.944897905
Short name T572
Test name
Test status
Simulation time 273276703 ps
CPU time 0.98 seconds
Started Aug 02 05:29:45 PM PDT 24
Finished Aug 02 05:29:46 PM PDT 24
Peak memory 207400 kb
Host smart-f066a85f-6d42-4717-af9b-2c67e0623a93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94489
7905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.944897905
Directory /workspace/13.usbdev_stall_trans/latest


Test location /workspace/coverage/default/13.usbdev_stream_len_max.2073033451
Short name T2895
Test name
Test status
Simulation time 443665699 ps
CPU time 1.47 seconds
Started Aug 02 05:30:00 PM PDT 24
Finished Aug 02 05:30:02 PM PDT 24
Peak memory 207384 kb
Host smart-fe123370-6a64-4cea-a49d-4acfdd2defc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730
33451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2073033451
Directory /workspace/13.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/13.usbdev_streaming_out.1066965151
Short name T930
Test name
Test status
Simulation time 3689932335 ps
CPU time 106.24 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:31:39 PM PDT 24
Peak memory 217344 kb
Host smart-91bb994b-eb6e-4ed2-bb76-036b6dad30b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10669
65151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1066965151
Directory /workspace/13.usbdev_streaming_out/latest


Test location /workspace/coverage/default/13.usbdev_timeout_missing_host_handshake.2290373876
Short name T2717
Test name
Test status
Simulation time 2932702189 ps
CPU time 27.27 seconds
Started Aug 02 05:29:43 PM PDT 24
Finished Aug 02 05:30:11 PM PDT 24
Peak memory 207664 kb
Host smart-aac79f13-82d4-4df9-9ff4-a3cef4888a6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290373876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_timeout_missing_hos
t_handshake.2290373876
Directory /workspace/13.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/130.usbdev_endpoint_types.2949699019
Short name T362
Test name
Test status
Simulation time 620529614 ps
CPU time 1.57 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207332 kb
Host smart-b741d4d7-42ff-4bac-845c-4e9c5bf09dc0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2949699019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.usbdev_endpoint_types.2949699019
Directory /workspace/130.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/131.usbdev_endpoint_types.3361899012
Short name T225
Test name
Test status
Simulation time 790601922 ps
CPU time 1.83 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:35:18 PM PDT 24
Peak memory 207368 kb
Host smart-1421d0ab-c3ef-4c5a-a939-4ae4174388c9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3361899012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.usbdev_endpoint_types.3361899012
Directory /workspace/131.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/132.usbdev_endpoint_types.3179254361
Short name T314
Test name
Test status
Simulation time 419274289 ps
CPU time 1.43 seconds
Started Aug 02 05:35:13 PM PDT 24
Finished Aug 02 05:35:14 PM PDT 24
Peak memory 207176 kb
Host smart-e00c3bb2-d86b-406d-9bca-8eaead2c0da5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3179254361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.usbdev_endpoint_types.3179254361
Directory /workspace/132.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/133.usbdev_endpoint_types.2945900058
Short name T2328
Test name
Test status
Simulation time 555716895 ps
CPU time 1.5 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207360 kb
Host smart-288e7950-c03f-4fdd-90a5-ddc6460b57c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2945900058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.usbdev_endpoint_types.2945900058
Directory /workspace/133.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/134.usbdev_endpoint_types.1062737588
Short name T346
Test name
Test status
Simulation time 712706293 ps
CPU time 1.6 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207404 kb
Host smart-52a5d9ff-9bee-4bf8-8928-dfb43b66f635
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1062737588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.usbdev_endpoint_types.1062737588
Directory /workspace/134.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/135.usbdev_endpoint_types.3389237570
Short name T444
Test name
Test status
Simulation time 330359288 ps
CPU time 1.18 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207332 kb
Host smart-a62b4fc3-c783-426b-b698-e3a7043684a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3389237570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.usbdev_endpoint_types.3389237570
Directory /workspace/135.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/138.usbdev_endpoint_types.445254741
Short name T2519
Test name
Test status
Simulation time 162448286 ps
CPU time 0.88 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:35:17 PM PDT 24
Peak memory 207384 kb
Host smart-831c8844-7299-4e1f-93be-fd498879cc19
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=445254741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.usbdev_endpoint_types.445254741
Directory /workspace/138.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/139.usbdev_endpoint_types.1058859350
Short name T18
Test name
Test status
Simulation time 493489651 ps
CPU time 1.34 seconds
Started Aug 02 05:35:15 PM PDT 24
Finished Aug 02 05:35:17 PM PDT 24
Peak memory 207392 kb
Host smart-e2b9ce83-1a4a-4969-8389-f5dbac4154d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1058859350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.usbdev_endpoint_types.1058859350
Directory /workspace/139.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/14.usbdev_alert_test.302242731
Short name T2844
Test name
Test status
Simulation time 41724583 ps
CPU time 0.66 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:05 PM PDT 24
Peak memory 207460 kb
Host smart-6532a289-7787-48d8-9d5b-5bc227ab94ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=302242731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.302242731
Directory /workspace/14.usbdev_alert_test/latest


Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.1961773138
Short name T959
Test name
Test status
Simulation time 4042031735 ps
CPU time 5.88 seconds
Started Aug 02 05:29:57 PM PDT 24
Finished Aug 02 05:30:03 PM PDT 24
Peak memory 215876 kb
Host smart-820f71f6-0e86-4720-94b7-eb4c4fd6d9aa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961773138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_a
on_wake_disconnect.1961773138
Directory /workspace/14.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.1767157395
Short name T2910
Test name
Test status
Simulation time 15049340865 ps
CPU time 20.31 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:25 PM PDT 24
Peak memory 215900 kb
Host smart-83f9b8f5-2403-4687-b208-e219b2b12837
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767157395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.1767157395
Directory /workspace/14.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.326729173
Short name T2537
Test name
Test status
Simulation time 24751608379 ps
CPU time 29.87 seconds
Started Aug 02 05:29:54 PM PDT 24
Finished Aug 02 05:30:24 PM PDT 24
Peak memory 215848 kb
Host smart-818090ca-bb16-431d-8ac6-aa7be124ca40
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326729173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_ao
n_wake_resume.326729173
Directory /workspace/14.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/14.usbdev_av_buffer.1130994336
Short name T1092
Test name
Test status
Simulation time 156565004 ps
CPU time 0.89 seconds
Started Aug 02 05:29:59 PM PDT 24
Finished Aug 02 05:30:00 PM PDT 24
Peak memory 207376 kb
Host smart-537abd33-098e-4673-b8a2-4c426aa379a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11309
94336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1130994336
Directory /workspace/14.usbdev_av_buffer/latest


Test location /workspace/coverage/default/14.usbdev_bitstuff_err.107776100
Short name T2354
Test name
Test status
Simulation time 163911555 ps
CPU time 0.85 seconds
Started Aug 02 05:29:57 PM PDT 24
Finished Aug 02 05:29:58 PM PDT 24
Peak memory 207344 kb
Host smart-b998f604-9eb7-4616-9698-be105c7a0712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10777
6100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.107776100
Directory /workspace/14.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.4002147827
Short name T1707
Test name
Test status
Simulation time 230438761 ps
CPU time 1.09 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 207404 kb
Host smart-9a533916-72dd-4ceb-aa18-5032ee281871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40021
47827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.4002147827
Directory /workspace/14.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2154957715
Short name T2097
Test name
Test status
Simulation time 1160528816 ps
CPU time 3.19 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:29:56 PM PDT 24
Peak memory 207576 kb
Host smart-f03f4308-ef3a-420f-962c-51f88d77b1f5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2154957715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2154957715
Directory /workspace/14.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/14.usbdev_device_address.2448245014
Short name T3024
Test name
Test status
Simulation time 41686870850 ps
CPU time 63.69 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:30:55 PM PDT 24
Peak memory 207644 kb
Host smart-0cbd90e1-dab2-4606-bc3e-f9fead46c60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24482
45014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.2448245014
Directory /workspace/14.usbdev_device_address/latest


Test location /workspace/coverage/default/14.usbdev_device_timeout.2031363770
Short name T2478
Test name
Test status
Simulation time 3638172007 ps
CPU time 23.05 seconds
Started Aug 02 05:29:57 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 207724 kb
Host smart-9ade30b4-ece0-48ca-90f0-6ba9ab5260b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031363770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_timeout.2031363770
Directory /workspace/14.usbdev_device_timeout/latest


Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2969604667
Short name T2166
Test name
Test status
Simulation time 870373825 ps
CPU time 1.98 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:29:55 PM PDT 24
Peak memory 207368 kb
Host smart-6396103d-8cf6-4899-af3f-7d83bcfa09c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29696
04667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2969604667
Directory /workspace/14.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/14.usbdev_disconnected.4182970423
Short name T1124
Test name
Test status
Simulation time 142125526 ps
CPU time 0.84 seconds
Started Aug 02 05:30:00 PM PDT 24
Finished Aug 02 05:30:01 PM PDT 24
Peak memory 207396 kb
Host smart-0a3cee47-f7c4-4e92-8252-66ae3eabe633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41829
70423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.4182970423
Directory /workspace/14.usbdev_disconnected/latest


Test location /workspace/coverage/default/14.usbdev_enable.830857337
Short name T2997
Test name
Test status
Simulation time 31651316 ps
CPU time 0.7 seconds
Started Aug 02 05:29:54 PM PDT 24
Finished Aug 02 05:29:55 PM PDT 24
Peak memory 207376 kb
Host smart-f1b5b96e-3bd6-49b2-8687-e04fcabf8866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83085
7337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.830857337
Directory /workspace/14.usbdev_enable/latest


Test location /workspace/coverage/default/14.usbdev_endpoint_access.2265342128
Short name T1447
Test name
Test status
Simulation time 991455627 ps
CPU time 2.85 seconds
Started Aug 02 05:29:50 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 207608 kb
Host smart-256bbd4a-70b2-4178-ac7b-8945a654ba0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22653
42128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2265342128
Directory /workspace/14.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/14.usbdev_fifo_rst.301307067
Short name T2859
Test name
Test status
Simulation time 356011611 ps
CPU time 2.43 seconds
Started Aug 02 05:29:54 PM PDT 24
Finished Aug 02 05:29:57 PM PDT 24
Peak memory 207560 kb
Host smart-36c7af47-6fbe-4d3d-a68c-166e0cce38db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30130
7067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.301307067
Directory /workspace/14.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/14.usbdev_in_iso.54140582
Short name T697
Test name
Test status
Simulation time 202329354 ps
CPU time 1 seconds
Started Aug 02 05:29:59 PM PDT 24
Finished Aug 02 05:30:00 PM PDT 24
Peak memory 207376 kb
Host smart-3b240e59-73b9-4504-94a1-035bf0e9c09c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=54140582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.54140582
Directory /workspace/14.usbdev_in_iso/latest


Test location /workspace/coverage/default/14.usbdev_in_stall.3203487812
Short name T255
Test name
Test status
Simulation time 160539242 ps
CPU time 0.82 seconds
Started Aug 02 05:29:54 PM PDT 24
Finished Aug 02 05:29:55 PM PDT 24
Peak memory 207352 kb
Host smart-f797090e-ff40-44b6-9b1c-e92de4f9c1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32034
87812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3203487812
Directory /workspace/14.usbdev_in_stall/latest


Test location /workspace/coverage/default/14.usbdev_in_trans.981595820
Short name T2868
Test name
Test status
Simulation time 226465189 ps
CPU time 0.98 seconds
Started Aug 02 05:29:54 PM PDT 24
Finished Aug 02 05:29:55 PM PDT 24
Peak memory 207312 kb
Host smart-a91a20a9-d514-4a98-934b-642e83874479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98159
5820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.981595820
Directory /workspace/14.usbdev_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_invalid_sync.1721929688
Short name T1973
Test name
Test status
Simulation time 3304139571 ps
CPU time 95.47 seconds
Started Aug 02 05:29:59 PM PDT 24
Finished Aug 02 05:31:35 PM PDT 24
Peak memory 215884 kb
Host smart-e007058f-d640-40a5-8c06-72720a484f74
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1721929688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.1721929688
Directory /workspace/14.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/14.usbdev_iso_retraction.1894128876
Short name T1486
Test name
Test status
Simulation time 7753281917 ps
CPU time 90.16 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:31:23 PM PDT 24
Peak memory 207664 kb
Host smart-f407e22f-cc10-40bb-977a-59053497d3a3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1894128876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.1894128876
Directory /workspace/14.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/14.usbdev_link_in_err.420527568
Short name T1319
Test name
Test status
Simulation time 174501208 ps
CPU time 0.83 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 207352 kb
Host smart-9b301366-5162-4e21-ba3c-00d72d0d3456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42052
7568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.420527568
Directory /workspace/14.usbdev_link_in_err/latest


Test location /workspace/coverage/default/14.usbdev_link_resume.2916756414
Short name T1091
Test name
Test status
Simulation time 32344945100 ps
CPU time 44.74 seconds
Started Aug 02 05:29:57 PM PDT 24
Finished Aug 02 05:30:42 PM PDT 24
Peak memory 207644 kb
Host smart-d446d342-40e1-42d6-96f7-ffc6d397af7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29167
56414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2916756414
Directory /workspace/14.usbdev_link_resume/latest


Test location /workspace/coverage/default/14.usbdev_link_suspend.724426147
Short name T1380
Test name
Test status
Simulation time 5833857850 ps
CPU time 8.7 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:30:01 PM PDT 24
Peak memory 215920 kb
Host smart-9f829e68-27f9-48bd-a845-6ff02f773e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72442
6147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.724426147
Directory /workspace/14.usbdev_link_suspend/latest


Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.607095164
Short name T2325
Test name
Test status
Simulation time 3409402855 ps
CPU time 26.28 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:30:19 PM PDT 24
Peak memory 224076 kb
Host smart-7a6865d7-af78-484a-96fd-cfc5b4db402b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60709
5164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.607095164
Directory /workspace/14.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1597453678
Short name T864
Test name
Test status
Simulation time 2526319069 ps
CPU time 71.36 seconds
Started Aug 02 05:29:54 PM PDT 24
Finished Aug 02 05:31:06 PM PDT 24
Peak memory 215872 kb
Host smart-38a3216e-e77d-436a-8a7c-02d5b866c119
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1597453678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1597453678
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2412426529
Short name T2623
Test name
Test status
Simulation time 244325703 ps
CPU time 0.96 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 207400 kb
Host smart-1edf1df3-fe61-4388-8550-a89c8ca89b0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2412426529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2412426529
Directory /workspace/14.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.918962075
Short name T2861
Test name
Test status
Simulation time 192154920 ps
CPU time 0.91 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:29:54 PM PDT 24
Peak memory 207364 kb
Host smart-dc258639-51bc-4e2e-8192-dbcfb3f58a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91896
2075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.918962075
Directory /workspace/14.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_max_non_iso_usb_traffic.274843058
Short name T238
Test name
Test status
Simulation time 3555783838 ps
CPU time 107.03 seconds
Started Aug 02 05:29:58 PM PDT 24
Finished Aug 02 05:31:45 PM PDT 24
Peak memory 215872 kb
Host smart-9761cc9b-d913-4b67-b54b-6ce5a453d3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27484
3058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_non_iso_usb_traffic.274843058
Directory /workspace/14.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.105454926
Short name T133
Test name
Test status
Simulation time 2623610963 ps
CPU time 29.58 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 218088 kb
Host smart-0df4015d-1e8e-4b27-bc36-0b0cdc5ff1e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=105454926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.105454926
Directory /workspace/14.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.2877624220
Short name T1461
Test name
Test status
Simulation time 3349800543 ps
CPU time 26.19 seconds
Started Aug 02 05:29:51 PM PDT 24
Finished Aug 02 05:30:18 PM PDT 24
Peak memory 207616 kb
Host smart-0ae728e2-95af-4890-8527-ea8745021045
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2877624220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.2877624220
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2845690107
Short name T3107
Test name
Test status
Simulation time 153282350 ps
CPU time 0.82 seconds
Started Aug 02 05:29:52 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 207408 kb
Host smart-05a5a48a-2a71-4d37-80ed-02038ce4efe0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2845690107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2845690107
Directory /workspace/14.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3905099135
Short name T2119
Test name
Test status
Simulation time 152748122 ps
CPU time 0.91 seconds
Started Aug 02 05:30:18 PM PDT 24
Finished Aug 02 05:30:19 PM PDT 24
Peak memory 207428 kb
Host smart-f913d3b2-c3fe-4fbc-bf4f-87027d898137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39050
99135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3905099135
Directory /workspace/14.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_out_iso.3420123107
Short name T2297
Test name
Test status
Simulation time 175783978 ps
CPU time 0.92 seconds
Started Aug 02 05:29:58 PM PDT 24
Finished Aug 02 05:29:59 PM PDT 24
Peak memory 207428 kb
Host smart-53e066a0-5ac5-46a4-8ac5-95d9ca991ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34201
23107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.3420123107
Directory /workspace/14.usbdev_out_iso/latest


Test location /workspace/coverage/default/14.usbdev_out_stall.1125327574
Short name T1605
Test name
Test status
Simulation time 209938737 ps
CPU time 0.92 seconds
Started Aug 02 05:29:54 PM PDT 24
Finished Aug 02 05:29:55 PM PDT 24
Peak memory 207404 kb
Host smart-a61e4b8c-7fa9-448a-aeac-0457a1c5b74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11253
27574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1125327574
Directory /workspace/14.usbdev_out_stall/latest


Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2220876906
Short name T996
Test name
Test status
Simulation time 182792696 ps
CPU time 0.85 seconds
Started Aug 02 05:29:57 PM PDT 24
Finished Aug 02 05:29:58 PM PDT 24
Peak memory 207376 kb
Host smart-bddd790e-67d8-4303-9a2e-dbf7006caca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22208
76906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2220876906
Directory /workspace/14.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2726966366
Short name T1583
Test name
Test status
Simulation time 151622264 ps
CPU time 0.83 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 207352 kb
Host smart-76bf8fb2-022b-4e4c-8c3e-39333df9b693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27269
66366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2726966366
Directory /workspace/14.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.4140748603
Short name T860
Test name
Test status
Simulation time 196308767 ps
CPU time 0.92 seconds
Started Aug 02 05:29:54 PM PDT 24
Finished Aug 02 05:29:55 PM PDT 24
Peak memory 207284 kb
Host smart-42bfe003-f8a5-4a5d-abae-356dd27a1097
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4140748603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.4140748603
Directory /workspace/14.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.2321595148
Short name T893
Test name
Test status
Simulation time 151589377 ps
CPU time 0.85 seconds
Started Aug 02 05:29:51 PM PDT 24
Finished Aug 02 05:29:52 PM PDT 24
Peak memory 207372 kb
Host smart-ccc75d88-0e3c-4d20-acc8-36187f7f92ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23215
95148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.2321595148
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.207932724
Short name T2319
Test name
Test status
Simulation time 38591441 ps
CPU time 0.68 seconds
Started Aug 02 05:29:53 PM PDT 24
Finished Aug 02 05:29:54 PM PDT 24
Peak memory 207392 kb
Host smart-94b59b57-d87e-4703-9394-5495b9edb2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20793
2724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.207932724
Directory /workspace/14.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3492989686
Short name T260
Test name
Test status
Simulation time 7009639259 ps
CPU time 20.45 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:25 PM PDT 24
Peak memory 215828 kb
Host smart-df23a684-11b9-4054-985c-df03fa347bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34929
89686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3492989686
Directory /workspace/14.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/14.usbdev_pkt_received.263635029
Short name T1859
Test name
Test status
Simulation time 230642463 ps
CPU time 0.99 seconds
Started Aug 02 05:30:03 PM PDT 24
Finished Aug 02 05:30:04 PM PDT 24
Peak memory 207404 kb
Host smart-fd0e4cbf-b38e-4a5c-9631-35ec66c5952b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26363
5029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.263635029
Directory /workspace/14.usbdev_pkt_received/latest


Test location /workspace/coverage/default/14.usbdev_pkt_sent.1757047005
Short name T3074
Test name
Test status
Simulation time 268717786 ps
CPU time 1.06 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:05 PM PDT 24
Peak memory 207332 kb
Host smart-b911f3a1-bfc6-4ba4-bd23-9e82463b1d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17570
47005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.1757047005
Directory /workspace/14.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3991863206
Short name T680
Test name
Test status
Simulation time 248649762 ps
CPU time 0.96 seconds
Started Aug 02 05:30:03 PM PDT 24
Finished Aug 02 05:30:04 PM PDT 24
Peak memory 207352 kb
Host smart-64182209-2078-487f-89b1-a496aa7173e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39918
63206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3991863206
Directory /workspace/14.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2067247848
Short name T3016
Test name
Test status
Simulation time 241226205 ps
CPU time 1.02 seconds
Started Aug 02 05:30:08 PM PDT 24
Finished Aug 02 05:30:09 PM PDT 24
Peak memory 207412 kb
Host smart-9ff918f1-5d51-4762-a0a1-41db2c343edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20672
47848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2067247848
Directory /workspace/14.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2676352550
Short name T2280
Test name
Test status
Simulation time 141893223 ps
CPU time 0.84 seconds
Started Aug 02 05:30:06 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207420 kb
Host smart-11e13202-a228-4c1a-b047-fde4862ea8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26763
52550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2676352550
Directory /workspace/14.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/14.usbdev_rx_full.1224185741
Short name T2099
Test name
Test status
Simulation time 252962582 ps
CPU time 1.12 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:05 PM PDT 24
Peak memory 207376 kb
Host smart-19f287cf-58d2-45a5-9fe2-761f8c222b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12241
85741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_full.1224185741
Directory /workspace/14.usbdev_rx_full/latest


Test location /workspace/coverage/default/14.usbdev_setup_stage.1064809837
Short name T2453
Test name
Test status
Simulation time 155947474 ps
CPU time 0.84 seconds
Started Aug 02 05:30:07 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207384 kb
Host smart-a370d41a-6734-4265-b652-fe689679cecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10648
09837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1064809837
Directory /workspace/14.usbdev_setup_stage/latest


Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.4171413684
Short name T1634
Test name
Test status
Simulation time 145508490 ps
CPU time 0.88 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:06 PM PDT 24
Peak memory 207384 kb
Host smart-27cf738e-3650-4f49-8b54-ad238c083a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41714
13684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.4171413684
Directory /workspace/14.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/14.usbdev_smoke.284106360
Short name T1675
Test name
Test status
Simulation time 278388627 ps
CPU time 1.09 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:06 PM PDT 24
Peak memory 207408 kb
Host smart-dd459fe1-ef3a-4a5c-9603-a9b4120cd66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28410
6360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.284106360
Directory /workspace/14.usbdev_smoke/latest


Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1833903231
Short name T529
Test name
Test status
Simulation time 2936975470 ps
CPU time 85.22 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 217556 kb
Host smart-11ea366d-6032-419c-879e-e593714fbbaa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1833903231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1833903231
Directory /workspace/14.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1407196992
Short name T2249
Test name
Test status
Simulation time 155035518 ps
CPU time 0.83 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:05 PM PDT 24
Peak memory 207364 kb
Host smart-5a3d6d3d-4ab6-4572-be52-9c5c5eb46c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14071
96992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1407196992
Directory /workspace/14.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/14.usbdev_stall_trans.3523239494
Short name T2204
Test name
Test status
Simulation time 222610182 ps
CPU time 0.92 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:06 PM PDT 24
Peak memory 207352 kb
Host smart-37b6acd3-0df8-41f1-a273-5bb25eab2925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35232
39494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3523239494
Directory /workspace/14.usbdev_stall_trans/latest


Test location /workspace/coverage/default/14.usbdev_stream_len_max.3579270805
Short name T1062
Test name
Test status
Simulation time 1086546321 ps
CPU time 2.74 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207552 kb
Host smart-db196afb-2f36-404f-8b1a-72cfaaa36e1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35792
70805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.3579270805
Directory /workspace/14.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/14.usbdev_streaming_out.1451687792
Short name T2538
Test name
Test status
Simulation time 2292670926 ps
CPU time 17.33 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 207600 kb
Host smart-cf83a902-f2ac-4904-96c1-d481929985e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14516
87792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1451687792
Directory /workspace/14.usbdev_streaming_out/latest


Test location /workspace/coverage/default/14.usbdev_timeout_missing_host_handshake.384318579
Short name T63
Test name
Test status
Simulation time 7065591066 ps
CPU time 43.7 seconds
Started Aug 02 05:29:59 PM PDT 24
Finished Aug 02 05:30:42 PM PDT 24
Peak memory 207744 kb
Host smart-177ff717-8b8d-49fe-9e98-3770cc36090f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384318579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_timeout_missing_host
_handshake.384318579
Directory /workspace/14.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/142.usbdev_endpoint_types.571498516
Short name T2065
Test name
Test status
Simulation time 217878777 ps
CPU time 0.92 seconds
Started Aug 02 05:34:57 PM PDT 24
Finished Aug 02 05:34:59 PM PDT 24
Peak memory 207352 kb
Host smart-6fbbb6e2-a3c7-411e-9f5f-aad055c3344b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=571498516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.usbdev_endpoint_types.571498516
Directory /workspace/142.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/143.usbdev_endpoint_types.880465326
Short name T2162
Test name
Test status
Simulation time 259937159 ps
CPU time 1.02 seconds
Started Aug 02 05:35:07 PM PDT 24
Finished Aug 02 05:35:08 PM PDT 24
Peak memory 207312 kb
Host smart-3addecab-0473-416c-ac96-e6b17a76fffb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=880465326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.usbdev_endpoint_types.880465326
Directory /workspace/143.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/144.usbdev_endpoint_types.3317342765
Short name T469
Test name
Test status
Simulation time 322282948 ps
CPU time 1.05 seconds
Started Aug 02 05:34:57 PM PDT 24
Finished Aug 02 05:34:59 PM PDT 24
Peak memory 207292 kb
Host smart-b1ce424e-841e-4135-bdc7-28665d8a6b25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3317342765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.usbdev_endpoint_types.3317342765
Directory /workspace/144.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/145.usbdev_endpoint_types.3431799669
Short name T440
Test name
Test status
Simulation time 667923577 ps
CPU time 1.68 seconds
Started Aug 02 05:35:12 PM PDT 24
Finished Aug 02 05:35:19 PM PDT 24
Peak memory 207288 kb
Host smart-0d6bdab7-46f0-4daf-b3ec-4555d4706c61
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3431799669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.usbdev_endpoint_types.3431799669
Directory /workspace/145.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/146.usbdev_endpoint_types.2133408729
Short name T1553
Test name
Test status
Simulation time 163555013 ps
CPU time 0.88 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207368 kb
Host smart-c1b716f7-ae5c-477b-aebf-66a58046d935
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2133408729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.usbdev_endpoint_types.2133408729
Directory /workspace/146.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/147.usbdev_endpoint_types.1406408687
Short name T451
Test name
Test status
Simulation time 409012790 ps
CPU time 1.42 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207300 kb
Host smart-750f4067-e818-48f2-a2ff-9733829860a4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1406408687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.usbdev_endpoint_types.1406408687
Directory /workspace/147.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/149.usbdev_endpoint_types.3264516655
Short name T428
Test name
Test status
Simulation time 618476356 ps
CPU time 1.5 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207304 kb
Host smart-b9973c30-621a-4647-87a8-db7d788cdb25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3264516655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.usbdev_endpoint_types.3264516655
Directory /workspace/149.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/15.usbdev_alert_test.4098300861
Short name T2285
Test name
Test status
Simulation time 39068017 ps
CPU time 0.71 seconds
Started Aug 02 05:30:16 PM PDT 24
Finished Aug 02 05:30:17 PM PDT 24
Peak memory 207484 kb
Host smart-40018662-828b-458a-ad95-53d024767696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4098300861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.4098300861
Directory /workspace/15.usbdev_alert_test/latest


Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.2710680615
Short name T1047
Test name
Test status
Simulation time 9173653039 ps
CPU time 13.41 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:18 PM PDT 24
Peak memory 207684 kb
Host smart-cec4e5b3-d300-4cd1-b092-b0381b4fd537
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710680615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_disconnect.2710680615
Directory /workspace/15.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.2446196797
Short name T1007
Test name
Test status
Simulation time 28722721960 ps
CPU time 31.05 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:36 PM PDT 24
Peak memory 207700 kb
Host smart-b46b25dd-a4a9-4969-848f-210097b7cbdb
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446196797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_a
on_wake_resume.2446196797
Directory /workspace/15.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/15.usbdev_av_buffer.2211569292
Short name T1206
Test name
Test status
Simulation time 174173888 ps
CPU time 0.87 seconds
Started Aug 02 05:30:06 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207400 kb
Host smart-b24d16c1-898d-4384-ba84-70b2688555f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22115
69292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.2211569292
Directory /workspace/15.usbdev_av_buffer/latest


Test location /workspace/coverage/default/15.usbdev_bitstuff_err.4091104708
Short name T2061
Test name
Test status
Simulation time 184746373 ps
CPU time 0.86 seconds
Started Aug 02 05:30:06 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207428 kb
Host smart-6f38e768-56ab-4f17-a2e6-4728281a59e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40911
04708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.4091104708
Directory /workspace/15.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.2893925289
Short name T1837
Test name
Test status
Simulation time 363674080 ps
CPU time 1.37 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207428 kb
Host smart-33676c2d-538b-416a-8034-a8e6ad5d6fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28939
25289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.2893925289
Directory /workspace/15.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2562701321
Short name T1300
Test name
Test status
Simulation time 921237393 ps
CPU time 2.35 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207588 kb
Host smart-16f5dd45-f7d9-4a44-bd09-b601cbfcb92f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2562701321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2562701321
Directory /workspace/15.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/15.usbdev_device_timeout.543311095
Short name T1981
Test name
Test status
Simulation time 873268473 ps
CPU time 18.73 seconds
Started Aug 02 05:30:03 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 207580 kb
Host smart-278c0608-4d51-45f2-b442-cb2e7ca96385
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543311095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.543311095
Directory /workspace/15.usbdev_device_timeout/latest


Test location /workspace/coverage/default/15.usbdev_disable_endpoint.3799624510
Short name T3101
Test name
Test status
Simulation time 752995977 ps
CPU time 1.77 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207372 kb
Host smart-e14b5e57-86a8-40c6-9de9-5a4872853197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37996
24510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.3799624510
Directory /workspace/15.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/15.usbdev_disconnected.2565067426
Short name T1547
Test name
Test status
Simulation time 136660142 ps
CPU time 0.79 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:06 PM PDT 24
Peak memory 207360 kb
Host smart-b8a5baa3-f332-4a87-82f3-75b4d041b511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650
67426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2565067426
Directory /workspace/15.usbdev_disconnected/latest


Test location /workspace/coverage/default/15.usbdev_enable.3095436935
Short name T2095
Test name
Test status
Simulation time 38533938 ps
CPU time 0.71 seconds
Started Aug 02 05:30:06 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207348 kb
Host smart-326fad14-448d-4ec0-84ef-924036ca608c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30954
36935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3095436935
Directory /workspace/15.usbdev_enable/latest


Test location /workspace/coverage/default/15.usbdev_endpoint_access.664108748
Short name T1305
Test name
Test status
Simulation time 926424947 ps
CPU time 2.46 seconds
Started Aug 02 05:30:06 PM PDT 24
Finished Aug 02 05:30:08 PM PDT 24
Peak memory 207644 kb
Host smart-37e695ca-969f-437c-9ccf-49839339e156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66410
8748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.664108748
Directory /workspace/15.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/15.usbdev_endpoint_types.1531158359
Short name T438
Test name
Test status
Simulation time 518128539 ps
CPU time 1.48 seconds
Started Aug 02 05:30:06 PM PDT 24
Finished Aug 02 05:30:08 PM PDT 24
Peak memory 207360 kb
Host smart-c127866b-7012-4c51-a97d-f1c6de640810
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1531158359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_types.1531158359
Directory /workspace/15.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/15.usbdev_fifo_rst.3702636627
Short name T897
Test name
Test status
Simulation time 160222520 ps
CPU time 1.76 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207616 kb
Host smart-85fffd98-cf77-437d-88ea-d70f2a0299f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37026
36627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3702636627
Directory /workspace/15.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/15.usbdev_in_iso.676893005
Short name T2050
Test name
Test status
Simulation time 218122083 ps
CPU time 1.13 seconds
Started Aug 02 05:30:06 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 215836 kb
Host smart-9b4824dd-858b-4661-9895-37eb7f0ffd3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=676893005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.676893005
Directory /workspace/15.usbdev_in_iso/latest


Test location /workspace/coverage/default/15.usbdev_in_stall.2084695811
Short name T565
Test name
Test status
Simulation time 153447051 ps
CPU time 0.82 seconds
Started Aug 02 05:30:06 PM PDT 24
Finished Aug 02 05:30:07 PM PDT 24
Peak memory 207368 kb
Host smart-f92ca04d-a978-4031-894a-1018e8bbd6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20846
95811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2084695811
Directory /workspace/15.usbdev_in_stall/latest


Test location /workspace/coverage/default/15.usbdev_in_trans.3236003800
Short name T1609
Test name
Test status
Simulation time 171599072 ps
CPU time 0.9 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:06 PM PDT 24
Peak memory 207372 kb
Host smart-3d855cec-678a-43bf-be29-d85410e9dc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32360
03800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.3236003800
Directory /workspace/15.usbdev_in_trans/latest


Test location /workspace/coverage/default/15.usbdev_invalid_sync.716749586
Short name T2637
Test name
Test status
Simulation time 3504308152 ps
CPU time 26.41 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:31 PM PDT 24
Peak memory 218172 kb
Host smart-9f0de3f0-39cc-43b6-b256-d93a28a9e78b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=716749586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.716749586
Directory /workspace/15.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/15.usbdev_iso_retraction.2989427815
Short name T1176
Test name
Test status
Simulation time 8112952433 ps
CPU time 98.79 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:31:43 PM PDT 24
Peak memory 207648 kb
Host smart-ca009526-cbac-468d-94aa-77c125ad54f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2989427815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.2989427815
Directory /workspace/15.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/15.usbdev_link_in_err.2448152266
Short name T1763
Test name
Test status
Simulation time 209821394 ps
CPU time 0.92 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:06 PM PDT 24
Peak memory 207400 kb
Host smart-880272a9-2f2f-43dd-9d12-c2cad796b21c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24481
52266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2448152266
Directory /workspace/15.usbdev_link_in_err/latest


Test location /workspace/coverage/default/15.usbdev_link_resume.2945518377
Short name T200
Test name
Test status
Simulation time 11915115781 ps
CPU time 16.77 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 207692 kb
Host smart-ed34da6d-24a4-4f46-88c4-d960ead9fef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29455
18377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.2945518377
Directory /workspace/15.usbdev_link_resume/latest


Test location /workspace/coverage/default/15.usbdev_link_suspend.1071997414
Short name T2503
Test name
Test status
Simulation time 9662389818 ps
CPU time 12.56 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:17 PM PDT 24
Peak memory 207620 kb
Host smart-6a1ed6d5-d53b-4a49-a2f2-b37a39fbcbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10719
97414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.1071997414
Directory /workspace/15.usbdev_link_suspend/latest


Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.17092625
Short name T1725
Test name
Test status
Simulation time 4491806432 ps
CPU time 43.11 seconds
Started Aug 02 05:30:05 PM PDT 24
Finished Aug 02 05:30:49 PM PDT 24
Peak memory 224080 kb
Host smart-428d4244-f5c8-45b1-bf64-5004f58adc97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17092
625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.17092625
Directory /workspace/15.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2812333657
Short name T633
Test name
Test status
Simulation time 2581862784 ps
CPU time 74.35 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:31:19 PM PDT 24
Peak memory 224088 kb
Host smart-fd1b2dbf-291b-45eb-9d2a-82564a7bb79b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2812333657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2812333657
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2483385260
Short name T953
Test name
Test status
Simulation time 248680742 ps
CPU time 0.97 seconds
Started Aug 02 05:30:04 PM PDT 24
Finished Aug 02 05:30:06 PM PDT 24
Peak memory 207444 kb
Host smart-5658debb-96ba-46d2-8db9-24ab0015a6fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2483385260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2483385260
Directory /workspace/15.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.968188453
Short name T1953
Test name
Test status
Simulation time 197964162 ps
CPU time 0.98 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207348 kb
Host smart-b4bc0372-4c1a-42e8-b24f-1f4bf8bc2f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96818
8453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.968188453
Directory /workspace/15.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_max_non_iso_usb_traffic.553035229
Short name T944
Test name
Test status
Simulation time 3311042707 ps
CPU time 32.51 seconds
Started Aug 02 05:30:16 PM PDT 24
Finished Aug 02 05:30:48 PM PDT 24
Peak memory 223952 kb
Host smart-eda3058d-3053-4344-840c-ad5060950fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55303
5229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_non_iso_usb_traffic.553035229
Directory /workspace/15.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2235263124
Short name T2429
Test name
Test status
Simulation time 3406895547 ps
CPU time 99.96 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:31:54 PM PDT 24
Peak memory 217256 kb
Host smart-a93b4594-5aec-4048-b449-95f0d30aa739
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2235263124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2235263124
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.4196798647
Short name T1247
Test name
Test status
Simulation time 151279330 ps
CPU time 0.9 seconds
Started Aug 02 05:30:15 PM PDT 24
Finished Aug 02 05:30:16 PM PDT 24
Peak memory 207380 kb
Host smart-fe6451ee-1fa0-4987-ab26-69e6163f26f9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4196798647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.4196798647
Directory /workspace/15.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.3241717918
Short name T1940
Test name
Test status
Simulation time 148673931 ps
CPU time 0.83 seconds
Started Aug 02 05:30:11 PM PDT 24
Finished Aug 02 05:30:12 PM PDT 24
Peak memory 207412 kb
Host smart-241aec2a-25bf-4fce-8f9d-36f577b442a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32417
17918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.3241717918
Directory /workspace/15.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_out_iso.967727959
Short name T2485
Test name
Test status
Simulation time 226258398 ps
CPU time 0.96 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:13 PM PDT 24
Peak memory 207376 kb
Host smart-b1c4493f-a857-4113-9931-df021c21edb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96772
7959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.967727959
Directory /workspace/15.usbdev_out_iso/latest


Test location /workspace/coverage/default/15.usbdev_out_stall.1311019658
Short name T1833
Test name
Test status
Simulation time 177822693 ps
CPU time 1 seconds
Started Aug 02 05:30:11 PM PDT 24
Finished Aug 02 05:30:12 PM PDT 24
Peak memory 207412 kb
Host smart-1e821b82-2ee3-482b-8ca8-888716797392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13110
19658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1311019658
Directory /workspace/15.usbdev_out_stall/latest


Test location /workspace/coverage/default/15.usbdev_out_trans_nak.39673227
Short name T1976
Test name
Test status
Simulation time 192003130 ps
CPU time 0.93 seconds
Started Aug 02 05:30:13 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 207320 kb
Host smart-b9ecf08f-cde9-45e8-82fc-ed6bb41a4a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39673
227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.39673227
Directory /workspace/15.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/15.usbdev_pending_in_trans.408750916
Short name T2953
Test name
Test status
Simulation time 183131570 ps
CPU time 0.87 seconds
Started Aug 02 05:30:17 PM PDT 24
Finished Aug 02 05:30:18 PM PDT 24
Peak memory 207432 kb
Host smart-2658ab72-0ad2-4230-93a6-c684e5be96f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40875
0916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.408750916
Directory /workspace/15.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1579472341
Short name T1267
Test name
Test status
Simulation time 206448650 ps
CPU time 0.99 seconds
Started Aug 02 05:30:17 PM PDT 24
Finished Aug 02 05:30:19 PM PDT 24
Peak memory 207400 kb
Host smart-4a3e4ba1-aa7d-4df5-b997-24ac26b6750e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1579472341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1579472341
Directory /workspace/15.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.409610931
Short name T1394
Test name
Test status
Simulation time 176196301 ps
CPU time 0.88 seconds
Started Aug 02 05:30:15 PM PDT 24
Finished Aug 02 05:30:16 PM PDT 24
Peak memory 207372 kb
Host smart-e025d4c9-299c-4c93-852e-e5409237b576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40961
0931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.409610931
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.3375048268
Short name T1778
Test name
Test status
Simulation time 101732325 ps
CPU time 0.74 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:13 PM PDT 24
Peak memory 207392 kb
Host smart-94935167-fe8f-4ee6-9f15-0e7ebab602ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33750
48268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.3375048268
Directory /workspace/15.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3686103735
Short name T2650
Test name
Test status
Simulation time 15892504369 ps
CPU time 41.02 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:53 PM PDT 24
Peak memory 224088 kb
Host smart-49dc63f7-e58f-4662-a35d-6835f74bf048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36861
03735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3686103735
Directory /workspace/15.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/15.usbdev_pkt_received.2866524623
Short name T2819
Test name
Test status
Simulation time 199368099 ps
CPU time 0.91 seconds
Started Aug 02 05:30:11 PM PDT 24
Finished Aug 02 05:30:12 PM PDT 24
Peak memory 207332 kb
Host smart-a569ec80-ffc8-4162-ba6c-64d27da2ce5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28665
24623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.2866524623
Directory /workspace/15.usbdev_pkt_received/latest


Test location /workspace/coverage/default/15.usbdev_pkt_sent.1347232243
Short name T2903
Test name
Test status
Simulation time 219129768 ps
CPU time 0.94 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:13 PM PDT 24
Peak memory 207372 kb
Host smart-50a32894-5c82-4912-9cf6-f94750436c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13472
32243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.1347232243
Directory /workspace/15.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1055030199
Short name T3044
Test name
Test status
Simulation time 262099401 ps
CPU time 1.04 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 207360 kb
Host smart-70815b5f-20b9-41f7-95b5-2b573ba3b562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10550
30199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1055030199
Directory /workspace/15.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1580863719
Short name T1373
Test name
Test status
Simulation time 175678388 ps
CPU time 0.95 seconds
Started Aug 02 05:30:16 PM PDT 24
Finished Aug 02 05:30:17 PM PDT 24
Peak memory 207392 kb
Host smart-53f36115-b045-43ab-892f-54fef429782e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15808
63719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1580863719
Directory /workspace/15.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/15.usbdev_rx_crc_err.568879351
Short name T2740
Test name
Test status
Simulation time 198652626 ps
CPU time 0.96 seconds
Started Aug 02 05:30:15 PM PDT 24
Finished Aug 02 05:30:16 PM PDT 24
Peak memory 207392 kb
Host smart-58aaa4c4-6d77-4f34-a2ef-aafb20a7eb8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56887
9351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.568879351
Directory /workspace/15.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/15.usbdev_rx_full.284917536
Short name T1945
Test name
Test status
Simulation time 347923668 ps
CPU time 1.15 seconds
Started Aug 02 05:30:13 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 207400 kb
Host smart-478621c9-05f9-49cb-a2eb-d40f512aef78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28491
7536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_full.284917536
Directory /workspace/15.usbdev_rx_full/latest


Test location /workspace/coverage/default/15.usbdev_setup_stage.2001297608
Short name T2541
Test name
Test status
Simulation time 157989417 ps
CPU time 0.84 seconds
Started Aug 02 05:30:13 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 207400 kb
Host smart-41012910-9496-4dbf-81da-0109d9699874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20012
97608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2001297608
Directory /workspace/15.usbdev_setup_stage/latest


Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.692253174
Short name T2714
Test name
Test status
Simulation time 164479702 ps
CPU time 0.88 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207336 kb
Host smart-a11f01f5-6e00-4c81-96d2-a7ea2bc39773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69225
3174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.692253174
Directory /workspace/15.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/15.usbdev_smoke.4169120419
Short name T44
Test name
Test status
Simulation time 243498737 ps
CPU time 1.03 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:13 PM PDT 24
Peak memory 207428 kb
Host smart-a8a87d38-56ea-44d9-afdb-3a8545a775ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41691
20419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.4169120419
Directory /workspace/15.usbdev_smoke/latest


Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.3622995048
Short name T2522
Test name
Test status
Simulation time 2295823345 ps
CPU time 65.95 seconds
Started Aug 02 05:30:16 PM PDT 24
Finished Aug 02 05:31:22 PM PDT 24
Peak memory 217484 kb
Host smart-04b5c7d1-f87b-412a-b9df-f40c674bf4f8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3622995048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.3622995048
Directory /workspace/15.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3236552021
Short name T1731
Test name
Test status
Simulation time 163282957 ps
CPU time 0.94 seconds
Started Aug 02 05:30:15 PM PDT 24
Finished Aug 02 05:30:16 PM PDT 24
Peak memory 207384 kb
Host smart-ada1ea25-c8f1-458d-8f5f-e6fd0869540a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32365
52021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3236552021
Directory /workspace/15.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/15.usbdev_stall_trans.3872856442
Short name T1983
Test name
Test status
Simulation time 153455691 ps
CPU time 0.81 seconds
Started Aug 02 05:30:13 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 207416 kb
Host smart-becaea05-4937-4c3b-ae8e-d2c6402711b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38728
56442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3872856442
Directory /workspace/15.usbdev_stall_trans/latest


Test location /workspace/coverage/default/15.usbdev_stream_len_max.3095915026
Short name T2138
Test name
Test status
Simulation time 1367290400 ps
CPU time 2.97 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:17 PM PDT 24
Peak memory 207520 kb
Host smart-d70bfa84-60d1-49b7-adad-1b2d0e6a7224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30959
15026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3095915026
Directory /workspace/15.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/15.usbdev_streaming_out.2139167001
Short name T2496
Test name
Test status
Simulation time 3727197469 ps
CPU time 108.39 seconds
Started Aug 02 05:30:17 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 217232 kb
Host smart-89930671-9125-4ee0-97b9-419655c25763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21391
67001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2139167001
Directory /workspace/15.usbdev_streaming_out/latest


Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.3228015553
Short name T1048
Test name
Test status
Simulation time 857834021 ps
CPU time 5.24 seconds
Started Aug 02 05:30:03 PM PDT 24
Finished Aug 02 05:30:08 PM PDT 24
Peak memory 207612 kb
Host smart-0f342b5e-5ed6-4f13-a1cf-67ecbf1579da
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228015553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_hos
t_handshake.3228015553
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/150.usbdev_endpoint_types.3460427956
Short name T2524
Test name
Test status
Simulation time 487857971 ps
CPU time 1.38 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207364 kb
Host smart-5fe8c943-4e1e-4783-ba98-672a07c41fb4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3460427956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.usbdev_endpoint_types.3460427956
Directory /workspace/150.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/151.usbdev_endpoint_types.3358722187
Short name T433
Test name
Test status
Simulation time 364081342 ps
CPU time 1.15 seconds
Started Aug 02 05:35:17 PM PDT 24
Finished Aug 02 05:35:18 PM PDT 24
Peak memory 207176 kb
Host smart-51e9369d-8f86-4c52-b354-43c1f6b38918
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3358722187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.usbdev_endpoint_types.3358722187
Directory /workspace/151.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/154.usbdev_endpoint_types.2514114661
Short name T1627
Test name
Test status
Simulation time 495692626 ps
CPU time 1.39 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207376 kb
Host smart-f0ca5124-652f-4f16-9f7a-fdaf6d8005ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2514114661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.usbdev_endpoint_types.2514114661
Directory /workspace/154.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/155.usbdev_endpoint_types.2614020456
Short name T2700
Test name
Test status
Simulation time 449851584 ps
CPU time 1.42 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207400 kb
Host smart-a7b8b97b-bd86-401c-bbed-d0dc99ae72d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2614020456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.usbdev_endpoint_types.2614020456
Directory /workspace/155.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/157.usbdev_endpoint_types.4160425657
Short name T1139
Test name
Test status
Simulation time 156989272 ps
CPU time 0.84 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207428 kb
Host smart-49a9ea91-988a-4da0-ad55-b317c921930a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4160425657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.usbdev_endpoint_types.4160425657
Directory /workspace/157.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/158.usbdev_endpoint_types.58414368
Short name T389
Test name
Test status
Simulation time 379406971 ps
CPU time 1.21 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:11 PM PDT 24
Peak memory 207360 kb
Host smart-b4ef2b81-ff3e-497c-85e6-ffde911c9af2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=58414368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.usbdev_endpoint_types.58414368
Directory /workspace/158.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/159.usbdev_endpoint_types.3536005058
Short name T420
Test name
Test status
Simulation time 381364407 ps
CPU time 1.19 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:08 PM PDT 24
Peak memory 207312 kb
Host smart-44061b2a-8e35-4d15-b477-93b89ab579e6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3536005058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.usbdev_endpoint_types.3536005058
Directory /workspace/159.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/16.usbdev_alert_test.3015989235
Short name T1037
Test name
Test status
Simulation time 41163178 ps
CPU time 0.7 seconds
Started Aug 02 05:30:23 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 207448 kb
Host smart-b388a1c6-eab9-47ab-9d5c-2938f9244cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3015989235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3015989235
Directory /workspace/16.usbdev_alert_test/latest


Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.407196352
Short name T1044
Test name
Test status
Simulation time 8950568266 ps
CPU time 10.55 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 207748 kb
Host smart-99a4139f-fc42-4d27-84bd-ba3f260b1b3f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407196352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_ao
n_wake_disconnect.407196352
Directory /workspace/16.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.1003588399
Short name T2921
Test name
Test status
Simulation time 21416475692 ps
CPU time 22.44 seconds
Started Aug 02 05:30:13 PM PDT 24
Finished Aug 02 05:30:35 PM PDT 24
Peak memory 207624 kb
Host smart-9c6c126f-58fe-47d2-a3d5-188214e84926
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003588399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.1003588399
Directory /workspace/16.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.1489156391
Short name T1876
Test name
Test status
Simulation time 29654071958 ps
CPU time 40.77 seconds
Started Aug 02 05:30:13 PM PDT 24
Finished Aug 02 05:30:54 PM PDT 24
Peak memory 207668 kb
Host smart-451694db-7a40-42ec-b259-b99066ad5b14
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489156391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_a
on_wake_resume.1489156391
Directory /workspace/16.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/16.usbdev_av_buffer.1822504717
Short name T2881
Test name
Test status
Simulation time 158277754 ps
CPU time 0.89 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207376 kb
Host smart-3c2dc6f9-ed86-43c5-8da2-81177bb4777c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18225
04717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1822504717
Directory /workspace/16.usbdev_av_buffer/latest


Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.893498278
Short name T967
Test name
Test status
Simulation time 331262786 ps
CPU time 1.36 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207392 kb
Host smart-11cda718-93d4-42bc-a763-dbcb595a58e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89349
8278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.893498278
Directory /workspace/16.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.690037937
Short name T912
Test name
Test status
Simulation time 717647917 ps
CPU time 1.91 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207392 kb
Host smart-a245e229-f6f5-4fb4-adfa-6e34301d6cf4
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=690037937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.690037937
Directory /workspace/16.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/16.usbdev_device_address.1913117578
Short name T2191
Test name
Test status
Simulation time 25813551100 ps
CPU time 44.2 seconds
Started Aug 02 05:30:15 PM PDT 24
Finished Aug 02 05:30:59 PM PDT 24
Peak memory 207628 kb
Host smart-b0069e62-1f6f-4913-a184-3495d35d0099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19131
17578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1913117578
Directory /workspace/16.usbdev_device_address/latest


Test location /workspace/coverage/default/16.usbdev_device_timeout.1317970351
Short name T1445
Test name
Test status
Simulation time 978927752 ps
CPU time 22.5 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:35 PM PDT 24
Peak memory 207540 kb
Host smart-30ea0b54-c909-49a3-91ea-a8c532655b34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317970351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_timeout.1317970351
Directory /workspace/16.usbdev_device_timeout/latest


Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1358762340
Short name T1072
Test name
Test status
Simulation time 620149663 ps
CPU time 1.48 seconds
Started Aug 02 05:30:11 PM PDT 24
Finished Aug 02 05:30:13 PM PDT 24
Peak memory 207328 kb
Host smart-94ad676e-6347-4d7b-9a7b-0c43ccb44212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13587
62340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1358762340
Directory /workspace/16.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/16.usbdev_disconnected.4213591699
Short name T1272
Test name
Test status
Simulation time 162159517 ps
CPU time 0.86 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 207396 kb
Host smart-527bd225-f57b-4093-af7c-126de89fee26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135
91699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.4213591699
Directory /workspace/16.usbdev_disconnected/latest


Test location /workspace/coverage/default/16.usbdev_enable.988477882
Short name T103
Test name
Test status
Simulation time 42364705 ps
CPU time 0.7 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:13 PM PDT 24
Peak memory 207344 kb
Host smart-00724150-b749-45b1-95fa-a9996f56a678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98847
7882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.988477882
Directory /workspace/16.usbdev_enable/latest


Test location /workspace/coverage/default/16.usbdev_endpoint_access.1958927592
Short name T1917
Test name
Test status
Simulation time 940325666 ps
CPU time 2.38 seconds
Started Aug 02 05:30:10 PM PDT 24
Finished Aug 02 05:30:12 PM PDT 24
Peak memory 207592 kb
Host smart-78d7159c-53d9-4c1a-8025-2e8ce14a66de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19589
27592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1958927592
Directory /workspace/16.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/16.usbdev_endpoint_types.1880485805
Short name T390
Test name
Test status
Simulation time 514314419 ps
CPU time 1.49 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 207364 kb
Host smart-3b97c9d4-b9d6-494c-ab69-4051944db065
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1880485805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_types.1880485805
Directory /workspace/16.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/16.usbdev_fifo_rst.776095548
Short name T1856
Test name
Test status
Simulation time 303647135 ps
CPU time 2.45 seconds
Started Aug 02 05:30:13 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207636 kb
Host smart-6f403612-3f02-4aef-bbd2-708172a59f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77609
5548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.776095548
Directory /workspace/16.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/16.usbdev_in_iso.153647707
Short name T2630
Test name
Test status
Simulation time 254228480 ps
CPU time 1.25 seconds
Started Aug 02 05:30:13 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 215764 kb
Host smart-eec5002b-9c2a-4e85-9100-1e622814f653
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=153647707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.153647707
Directory /workspace/16.usbdev_in_iso/latest


Test location /workspace/coverage/default/16.usbdev_in_stall.1251889632
Short name T1141
Test name
Test status
Simulation time 158988560 ps
CPU time 0.84 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207320 kb
Host smart-b1fbbc4f-1117-4929-80dd-31a6ac7d1d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12518
89632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1251889632
Directory /workspace/16.usbdev_in_stall/latest


Test location /workspace/coverage/default/16.usbdev_in_trans.3358231110
Short name T626
Test name
Test status
Simulation time 192094437 ps
CPU time 0.95 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207316 kb
Host smart-f01e4d6a-851c-4bf9-9908-90dc9edc4be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33582
31110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.3358231110
Directory /workspace/16.usbdev_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_invalid_sync.1625006932
Short name T2641
Test name
Test status
Simulation time 3249709430 ps
CPU time 96.36 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:31:49 PM PDT 24
Peak memory 215860 kb
Host smart-99d88bad-412b-4917-b3c4-6fb4c2c036ff
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1625006932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1625006932
Directory /workspace/16.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/16.usbdev_iso_retraction.3616687813
Short name T1222
Test name
Test status
Simulation time 8914795217 ps
CPU time 112.6 seconds
Started Aug 02 05:30:13 PM PDT 24
Finished Aug 02 05:32:06 PM PDT 24
Peak memory 207628 kb
Host smart-c0f128ab-8176-41c9-b701-bf3c52c99e5e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3616687813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.3616687813
Directory /workspace/16.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/16.usbdev_link_in_err.3093187281
Short name T688
Test name
Test status
Simulation time 237921129 ps
CPU time 1.04 seconds
Started Aug 02 05:30:12 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 207444 kb
Host smart-051e2e66-215d-4256-85ef-3d22b5491c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30931
87281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3093187281
Directory /workspace/16.usbdev_link_in_err/latest


Test location /workspace/coverage/default/16.usbdev_link_resume.2812459329
Short name T2536
Test name
Test status
Simulation time 15226335983 ps
CPU time 21.14 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:41 PM PDT 24
Peak memory 207632 kb
Host smart-39194e18-2fcc-4d76-a184-b924d703cd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28124
59329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.2812459329
Directory /workspace/16.usbdev_link_resume/latest


Test location /workspace/coverage/default/16.usbdev_link_suspend.2050887142
Short name T3000
Test name
Test status
Simulation time 8391133297 ps
CPU time 10.77 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:25 PM PDT 24
Peak memory 207680 kb
Host smart-7f0a47a5-3121-4cac-905d-1edb1f57fa59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20508
87142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.2050887142
Directory /workspace/16.usbdev_link_suspend/latest


Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1024148370
Short name T92
Test name
Test status
Simulation time 3548176080 ps
CPU time 33.8 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:53 PM PDT 24
Peak memory 218608 kb
Host smart-a92b53e8-1e2e-4d49-85a0-ca156700f16c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10241
48370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1024148370
Directory /workspace/16.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.2851510966
Short name T803
Test name
Test status
Simulation time 2056024022 ps
CPU time 19.75 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:34 PM PDT 24
Peak memory 215824 kb
Host smart-d8df4f9a-d7da-4fec-86df-1ed01f3216fe
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2851510966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.2851510966
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1378150719
Short name T662
Test name
Test status
Simulation time 262711523 ps
CPU time 1.01 seconds
Started Aug 02 05:30:16 PM PDT 24
Finished Aug 02 05:30:17 PM PDT 24
Peak memory 207380 kb
Host smart-be5e8411-b286-4132-bfca-de0421e4f376
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1378150719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1378150719
Directory /workspace/16.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.982279775
Short name T2342
Test name
Test status
Simulation time 197951823 ps
CPU time 0.93 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:21 PM PDT 24
Peak memory 207388 kb
Host smart-23489533-414f-48b6-8301-82d75f2ae0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98227
9775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.982279775
Directory /workspace/16.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_max_non_iso_usb_traffic.3332097944
Short name T1235
Test name
Test status
Simulation time 2802810997 ps
CPU time 20.39 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:40 PM PDT 24
Peak memory 207728 kb
Host smart-9ac69a14-ea8a-4b7d-bb7b-1473e4584bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33320
97944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_non_iso_usb_traffic.3332097944
Directory /workspace/16.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1974301530
Short name T2211
Test name
Test status
Simulation time 4075263856 ps
CPU time 119.5 seconds
Started Aug 02 05:30:15 PM PDT 24
Finished Aug 02 05:32:15 PM PDT 24
Peak memory 217160 kb
Host smart-041b7ba0-3c76-40e7-893f-20930c686814
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1974301530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1974301530
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3459170802
Short name T2102
Test name
Test status
Simulation time 191809071 ps
CPU time 0.91 seconds
Started Aug 02 05:30:15 PM PDT 24
Finished Aug 02 05:30:16 PM PDT 24
Peak memory 207380 kb
Host smart-61972a37-89ef-4e89-97ac-604d45ab3d40
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3459170802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3459170802
Directory /workspace/16.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.901872251
Short name T1255
Test name
Test status
Simulation time 143987181 ps
CPU time 0.8 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207388 kb
Host smart-4287f9fe-69ca-41d6-8fd7-6e2a3e8a879d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90187
2251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.901872251
Directory /workspace/16.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_nak_trans.2666750665
Short name T1571
Test name
Test status
Simulation time 245827714 ps
CPU time 1.04 seconds
Started Aug 02 05:30:20 PM PDT 24
Finished Aug 02 05:30:21 PM PDT 24
Peak memory 207396 kb
Host smart-dadc41f3-40b7-43e4-b314-e860833f8567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26667
50665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2666750665
Directory /workspace/16.usbdev_nak_trans/latest


Test location /workspace/coverage/default/16.usbdev_out_iso.3890607844
Short name T877
Test name
Test status
Simulation time 180790007 ps
CPU time 0.89 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 207392 kb
Host smart-5a42f902-c60f-443f-925a-1d59f4127c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38906
07844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.3890607844
Directory /workspace/16.usbdev_out_iso/latest


Test location /workspace/coverage/default/16.usbdev_out_stall.740660225
Short name T829
Test name
Test status
Simulation time 193479973 ps
CPU time 0.9 seconds
Started Aug 02 05:30:16 PM PDT 24
Finished Aug 02 05:30:17 PM PDT 24
Peak memory 207356 kb
Host smart-e4437649-3730-47c6-8073-ea7d24d9f12d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74066
0225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.740660225
Directory /workspace/16.usbdev_out_stall/latest


Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1359652653
Short name T1815
Test name
Test status
Simulation time 238946512 ps
CPU time 1 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 207356 kb
Host smart-1bd86a4d-f649-4ae7-9c94-d446db3eb699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13596
52653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1359652653
Directory /workspace/16.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/16.usbdev_pending_in_trans.2952033345
Short name T2958
Test name
Test status
Simulation time 142934804 ps
CPU time 0.83 seconds
Started Aug 02 05:30:14 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 207424 kb
Host smart-3be7b783-ac9e-481a-bbf8-f78131c5e912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29520
33345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.2952033345
Directory /workspace/16.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3795040493
Short name T1713
Test name
Test status
Simulation time 249739525 ps
CPU time 1.09 seconds
Started Aug 02 05:30:16 PM PDT 24
Finished Aug 02 05:30:18 PM PDT 24
Peak memory 207356 kb
Host smart-ba057384-23fe-4370-944e-cdebb674833e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3795040493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3795040493
Directory /workspace/16.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2506143402
Short name T2197
Test name
Test status
Simulation time 158454813 ps
CPU time 0.86 seconds
Started Aug 02 05:30:18 PM PDT 24
Finished Aug 02 05:30:19 PM PDT 24
Peak memory 207328 kb
Host smart-a4f3c810-5004-4d59-abb5-4d2be27f63ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061
43402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2506143402
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.563794929
Short name T2733
Test name
Test status
Simulation time 64486900 ps
CPU time 0.69 seconds
Started Aug 02 05:30:15 PM PDT 24
Finished Aug 02 05:30:16 PM PDT 24
Peak memory 207320 kb
Host smart-8e817ad9-2cdc-4085-b1fe-039f2fbf278f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56379
4929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.563794929
Directory /workspace/16.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1136543026
Short name T292
Test name
Test status
Simulation time 7674912288 ps
CPU time 20.52 seconds
Started Aug 02 05:30:16 PM PDT 24
Finished Aug 02 05:30:37 PM PDT 24
Peak memory 215884 kb
Host smart-ba65e222-df0f-4839-8d9d-c7d42244c2f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11365
43026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1136543026
Directory /workspace/16.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/16.usbdev_pkt_received.1305176236
Short name T1789
Test name
Test status
Simulation time 171836330 ps
CPU time 0.9 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 207392 kb
Host smart-002504f8-ed57-40b9-b714-88c494865f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13051
76236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1305176236
Directory /workspace/16.usbdev_pkt_received/latest


Test location /workspace/coverage/default/16.usbdev_pkt_sent.3781330773
Short name T772
Test name
Test status
Simulation time 240778820 ps
CPU time 1.03 seconds
Started Aug 02 05:30:24 PM PDT 24
Finished Aug 02 05:30:25 PM PDT 24
Peak memory 207404 kb
Host smart-1ffe9928-c6e8-48b3-9b75-309523dfd444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37813
30773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.3781330773
Directory /workspace/16.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1693336170
Short name T1154
Test name
Test status
Simulation time 181115447 ps
CPU time 0.88 seconds
Started Aug 02 05:30:20 PM PDT 24
Finished Aug 02 05:30:21 PM PDT 24
Peak memory 207428 kb
Host smart-94e0c935-fba2-461e-a2d7-fa412f775af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16933
36170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1693336170
Directory /workspace/16.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.2030454156
Short name T509
Test name
Test status
Simulation time 194690444 ps
CPU time 0.95 seconds
Started Aug 02 05:30:22 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 207392 kb
Host smart-517bfd4c-f9a3-4990-b1e8-eba644d965fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20304
54156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.2030454156
Directory /workspace/16.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3943955544
Short name T1531
Test name
Test status
Simulation time 158269975 ps
CPU time 0.83 seconds
Started Aug 02 05:30:23 PM PDT 24
Finished Aug 02 05:30:24 PM PDT 24
Peak memory 207400 kb
Host smart-0acdcb63-d1fd-4e75-949e-6f8f0a094961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39439
55544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3943955544
Directory /workspace/16.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/16.usbdev_rx_full.469098581
Short name T1134
Test name
Test status
Simulation time 256670285 ps
CPU time 1.03 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 207376 kb
Host smart-f61f893a-e9fc-4c42-9857-15ad90494c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46909
8581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_full.469098581
Directory /workspace/16.usbdev_rx_full/latest


Test location /workspace/coverage/default/16.usbdev_setup_stage.1965686421
Short name T2260
Test name
Test status
Simulation time 151259887 ps
CPU time 0.81 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 207336 kb
Host smart-e5dbdf3a-fbd0-44b9-bf90-57754e6f72c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19656
86421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1965686421
Directory /workspace/16.usbdev_setup_stage/latest


Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2043894744
Short name T1301
Test name
Test status
Simulation time 159533399 ps
CPU time 0.84 seconds
Started Aug 02 05:30:20 PM PDT 24
Finished Aug 02 05:30:21 PM PDT 24
Peak memory 207452 kb
Host smart-3e755936-0cea-43fd-9608-26a8b623b7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20438
94744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2043894744
Directory /workspace/16.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/16.usbdev_smoke.3443886855
Short name T2183
Test name
Test status
Simulation time 258437628 ps
CPU time 1.09 seconds
Started Aug 02 05:30:38 PM PDT 24
Finished Aug 02 05:30:40 PM PDT 24
Peak memory 207416 kb
Host smart-5015a325-e781-41b7-8775-f52926262b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34438
86855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.3443886855
Directory /workspace/16.usbdev_smoke/latest


Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.3582531045
Short name T3066
Test name
Test status
Simulation time 2521325919 ps
CPU time 18.9 seconds
Started Aug 02 05:30:20 PM PDT 24
Finished Aug 02 05:30:39 PM PDT 24
Peak memory 207628 kb
Host smart-b76aaa32-9ffa-4ea4-9ab9-f1f8fd91e45a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3582531045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.3582531045
Directory /workspace/16.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.2496116216
Short name T2746
Test name
Test status
Simulation time 228372757 ps
CPU time 0.92 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 207384 kb
Host smart-9cc537ab-888d-4dcf-b10d-69943208dba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
16216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.2496116216
Directory /workspace/16.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/16.usbdev_stall_trans.2284770821
Short name T550
Test name
Test status
Simulation time 178280936 ps
CPU time 0.84 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 207460 kb
Host smart-cb0a058b-cf9b-4e0b-9b9a-4be07eeff91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22847
70821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2284770821
Directory /workspace/16.usbdev_stall_trans/latest


Test location /workspace/coverage/default/16.usbdev_stream_len_max.2197666892
Short name T1215
Test name
Test status
Simulation time 886001754 ps
CPU time 2.18 seconds
Started Aug 02 05:30:38 PM PDT 24
Finished Aug 02 05:30:41 PM PDT 24
Peak memory 207636 kb
Host smart-8258e4a1-ac2a-4a64-b28e-8dc9da7ba5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21976
66892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.2197666892
Directory /workspace/16.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/16.usbdev_streaming_out.1924975606
Short name T614
Test name
Test status
Simulation time 2237890148 ps
CPU time 22.51 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:43 PM PDT 24
Peak memory 217224 kb
Host smart-20cd0c9a-a16b-4821-bd00-0a75bf2eaba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19249
75606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.1924975606
Directory /workspace/16.usbdev_streaming_out/latest


Test location /workspace/coverage/default/16.usbdev_timeout_missing_host_handshake.443751051
Short name T1017
Test name
Test status
Simulation time 902951490 ps
CPU time 19.15 seconds
Started Aug 02 05:30:16 PM PDT 24
Finished Aug 02 05:30:35 PM PDT 24
Peak memory 207528 kb
Host smart-786e7e56-ba53-45c0-a125-2420a5e1bf5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443751051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_timeout_missing_host
_handshake.443751051
Directory /workspace/16.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/160.usbdev_endpoint_types.3375450296
Short name T419
Test name
Test status
Simulation time 416257974 ps
CPU time 1.3 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207332 kb
Host smart-a4bf630e-a329-4118-a30f-4a15498984d8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3375450296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.usbdev_endpoint_types.3375450296
Directory /workspace/160.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/161.usbdev_endpoint_types.3225986207
Short name T2725
Test name
Test status
Simulation time 495664625 ps
CPU time 1.34 seconds
Started Aug 02 05:35:11 PM PDT 24
Finished Aug 02 05:35:13 PM PDT 24
Peak memory 207176 kb
Host smart-7575b8be-df37-4a9c-8a20-2564be3795ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3225986207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.usbdev_endpoint_types.3225986207
Directory /workspace/161.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/162.usbdev_endpoint_types.3797089514
Short name T454
Test name
Test status
Simulation time 441711820 ps
CPU time 1.32 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207356 kb
Host smart-f99d550e-85c2-46ee-86dc-38e5c271948a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3797089514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.usbdev_endpoint_types.3797089514
Directory /workspace/162.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/163.usbdev_endpoint_types.2502930868
Short name T2631
Test name
Test status
Simulation time 713546889 ps
CPU time 1.89 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207356 kb
Host smart-ccf9ac1a-447e-46a3-a078-7e32ed6da26e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2502930868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.usbdev_endpoint_types.2502930868
Directory /workspace/163.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/164.usbdev_endpoint_types.1826635406
Short name T2935
Test name
Test status
Simulation time 425169229 ps
CPU time 1.26 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:35:18 PM PDT 24
Peak memory 207344 kb
Host smart-8815c310-ab64-432f-af98-746bb75bbd9d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1826635406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.usbdev_endpoint_types.1826635406
Directory /workspace/164.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/165.usbdev_endpoint_types.1111341475
Short name T471
Test name
Test status
Simulation time 176652178 ps
CPU time 0.89 seconds
Started Aug 02 05:35:24 PM PDT 24
Finished Aug 02 05:35:25 PM PDT 24
Peak memory 207176 kb
Host smart-05d833ac-9156-443d-b2af-b11981bebb64
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1111341475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.usbdev_endpoint_types.1111341475
Directory /workspace/165.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/167.usbdev_endpoint_types.3643163092
Short name T357
Test name
Test status
Simulation time 913822911 ps
CPU time 2.21 seconds
Started Aug 02 05:34:57 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 207344 kb
Host smart-86298f23-8580-43be-bef6-a4677b35f0ed
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3643163092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.usbdev_endpoint_types.3643163092
Directory /workspace/167.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/168.usbdev_endpoint_types.183939929
Short name T1325
Test name
Test status
Simulation time 375697050 ps
CPU time 1.12 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207328 kb
Host smart-7eced660-cf6a-4fc4-aa87-b8dd530f94d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=183939929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.usbdev_endpoint_types.183939929
Directory /workspace/168.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/17.usbdev_alert_test.534158374
Short name T2578
Test name
Test status
Simulation time 70054375 ps
CPU time 0.77 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207428 kb
Host smart-cb93a3bb-6aab-42fc-9405-f7ad9f40fadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=534158374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.534158374
Directory /workspace/17.usbdev_alert_test/latest


Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3386695892
Short name T2067
Test name
Test status
Simulation time 9843489264 ps
CPU time 11.33 seconds
Started Aug 02 05:30:22 PM PDT 24
Finished Aug 02 05:30:34 PM PDT 24
Peak memory 207624 kb
Host smart-9458a170-991c-42c4-841f-b07f41b66c32
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386695892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_disconnect.3386695892
Directory /workspace/17.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2976910180
Short name T2603
Test name
Test status
Simulation time 14530899459 ps
CPU time 15.57 seconds
Started Aug 02 05:30:22 PM PDT 24
Finished Aug 02 05:30:38 PM PDT 24
Peak memory 215824 kb
Host smart-9dc879e3-ff13-4492-bdc3-462958bed932
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976910180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2976910180
Directory /workspace/17.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2941172065
Short name T13
Test name
Test status
Simulation time 28693800079 ps
CPU time 34.98 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:54 PM PDT 24
Peak memory 207672 kb
Host smart-5f203841-40ce-4c3a-973f-74b0d8876642
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941172065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_a
on_wake_resume.2941172065
Directory /workspace/17.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/17.usbdev_av_buffer.1843696226
Short name T1256
Test name
Test status
Simulation time 180626825 ps
CPU time 0.87 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 207424 kb
Host smart-9ab384c0-afea-4cb0-ae66-bddc17649420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18436
96226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1843696226
Directory /workspace/17.usbdev_av_buffer/latest


Test location /workspace/coverage/default/17.usbdev_bitstuff_err.3163849871
Short name T1922
Test name
Test status
Simulation time 149575443 ps
CPU time 0.83 seconds
Started Aug 02 05:30:22 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 207384 kb
Host smart-ed9e7606-eba5-441b-801b-0ec626c54150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31638
49871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.3163849871
Directory /workspace/17.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.3311769939
Short name T1733
Test name
Test status
Simulation time 170697850 ps
CPU time 0.93 seconds
Started Aug 02 05:30:20 PM PDT 24
Finished Aug 02 05:30:21 PM PDT 24
Peak memory 207400 kb
Host smart-0662d431-6318-4367-9bee-d9f8119818cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33117
69939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.3311769939
Directory /workspace/17.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1138112256
Short name T1183
Test name
Test status
Simulation time 1276340584 ps
CPU time 3 seconds
Started Aug 02 05:30:38 PM PDT 24
Finished Aug 02 05:30:42 PM PDT 24
Peak memory 207604 kb
Host smart-c7ff6316-e100-43e3-ac8d-5fc8f8b31a9e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1138112256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1138112256
Directory /workspace/17.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/17.usbdev_device_address.3902642550
Short name T3018
Test name
Test status
Simulation time 49819818527 ps
CPU time 82.22 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:31:44 PM PDT 24
Peak memory 207652 kb
Host smart-059883e3-82df-45cf-8b16-aee1b3391555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39026
42550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.3902642550
Directory /workspace/17.usbdev_device_address/latest


Test location /workspace/coverage/default/17.usbdev_device_timeout.972251455
Short name T870
Test name
Test status
Simulation time 5629013116 ps
CPU time 37.37 seconds
Started Aug 02 05:30:24 PM PDT 24
Finished Aug 02 05:31:01 PM PDT 24
Peak memory 207672 kb
Host smart-491849da-8cb9-407a-a6ac-b537779e2909
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972251455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_timeout.972251455
Directory /workspace/17.usbdev_device_timeout/latest


Test location /workspace/coverage/default/17.usbdev_disable_endpoint.960645376
Short name T1916
Test name
Test status
Simulation time 781167914 ps
CPU time 2.01 seconds
Started Aug 02 05:30:23 PM PDT 24
Finished Aug 02 05:30:26 PM PDT 24
Peak memory 207360 kb
Host smart-f6429dd0-5fea-4774-a2b6-b96cd0276a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96064
5376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.960645376
Directory /workspace/17.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/17.usbdev_disconnected.235537098
Short name T1718
Test name
Test status
Simulation time 143462909 ps
CPU time 0.83 seconds
Started Aug 02 05:30:20 PM PDT 24
Finished Aug 02 05:30:21 PM PDT 24
Peak memory 207296 kb
Host smart-b83e9226-831b-4324-986d-4c6e7fddb60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23553
7098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.235537098
Directory /workspace/17.usbdev_disconnected/latest


Test location /workspace/coverage/default/17.usbdev_enable.2403951046
Short name T493
Test name
Test status
Simulation time 47414164 ps
CPU time 0.71 seconds
Started Aug 02 05:30:24 PM PDT 24
Finished Aug 02 05:30:25 PM PDT 24
Peak memory 207384 kb
Host smart-eb3c1adc-b397-46e0-b531-0d75f6c539ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24039
51046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.2403951046
Directory /workspace/17.usbdev_enable/latest


Test location /workspace/coverage/default/17.usbdev_endpoint_access.3042594800
Short name T2927
Test name
Test status
Simulation time 964346316 ps
CPU time 2.5 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:24 PM PDT 24
Peak memory 207652 kb
Host smart-fd2df309-105a-4085-aba1-a22a87894abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30425
94800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3042594800
Directory /workspace/17.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/17.usbdev_endpoint_types.1903693806
Short name T388
Test name
Test status
Simulation time 926140755 ps
CPU time 1.98 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 207392 kb
Host smart-d96f7361-aa31-4eef-b2b3-81c96a743683
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1903693806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_types.1903693806
Directory /workspace/17.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/17.usbdev_fifo_rst.2092001994
Short name T1398
Test name
Test status
Simulation time 201992651 ps
CPU time 2.67 seconds
Started Aug 02 05:30:20 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 207592 kb
Host smart-9002804d-fba0-433c-9a3a-265e3be9d3ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20920
01994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2092001994
Directory /workspace/17.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/17.usbdev_in_iso.2258781772
Short name T2526
Test name
Test status
Simulation time 175043604 ps
CPU time 0.95 seconds
Started Aug 02 05:30:36 PM PDT 24
Finished Aug 02 05:30:37 PM PDT 24
Peak memory 207416 kb
Host smart-1afe03eb-1804-4eda-b1b0-19fdbfc19195
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2258781772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2258781772
Directory /workspace/17.usbdev_in_iso/latest


Test location /workspace/coverage/default/17.usbdev_in_stall.1700109331
Short name T2270
Test name
Test status
Simulation time 156046534 ps
CPU time 0.84 seconds
Started Aug 02 05:30:20 PM PDT 24
Finished Aug 02 05:30:21 PM PDT 24
Peak memory 206792 kb
Host smart-5e166938-11f8-4860-a80e-7eb7749e5d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17001
09331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1700109331
Directory /workspace/17.usbdev_in_stall/latest


Test location /workspace/coverage/default/17.usbdev_in_trans.1106228765
Short name T845
Test name
Test status
Simulation time 212544113 ps
CPU time 0.98 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 207432 kb
Host smart-bbf298ae-39c4-4604-a599-65bd6a0b025d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11062
28765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1106228765
Directory /workspace/17.usbdev_in_trans/latest


Test location /workspace/coverage/default/17.usbdev_invalid_sync.33211576
Short name T1582
Test name
Test status
Simulation time 2600818334 ps
CPU time 24.98 seconds
Started Aug 02 05:30:36 PM PDT 24
Finished Aug 02 05:31:01 PM PDT 24
Peak memory 224048 kb
Host smart-499aa137-de83-4832-be70-d10da48b3a85
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=33211576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.33211576
Directory /workspace/17.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/17.usbdev_iso_retraction.4155531555
Short name T2054
Test name
Test status
Simulation time 6995047793 ps
CPU time 87.4 seconds
Started Aug 02 05:30:36 PM PDT 24
Finished Aug 02 05:32:03 PM PDT 24
Peak memory 207688 kb
Host smart-a574ae9c-5766-4b5f-9339-3c878393d48a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4155531555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.4155531555
Directory /workspace/17.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/17.usbdev_link_in_err.2975932247
Short name T3011
Test name
Test status
Simulation time 166156953 ps
CPU time 0.85 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 207348 kb
Host smart-8d8dd0e5-44ae-4a21-ae73-5e640648844e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29759
32247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2975932247
Directory /workspace/17.usbdev_link_in_err/latest


Test location /workspace/coverage/default/17.usbdev_link_resume.1695000733
Short name T1807
Test name
Test status
Simulation time 24664996884 ps
CPU time 37.01 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 216600 kb
Host smart-103ab020-bf36-4413-8a22-4ab7548c5657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16950
00733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.1695000733
Directory /workspace/17.usbdev_link_resume/latest


Test location /workspace/coverage/default/17.usbdev_link_suspend.4197718848
Short name T1351
Test name
Test status
Simulation time 4227961043 ps
CPU time 6.3 seconds
Started Aug 02 05:30:24 PM PDT 24
Finished Aug 02 05:30:30 PM PDT 24
Peak memory 215872 kb
Host smart-758b6b1b-3a5e-4116-873e-547d9cf0761c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41977
18848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.4197718848
Directory /workspace/17.usbdev_link_suspend/latest


Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.3367208643
Short name T1895
Test name
Test status
Simulation time 4476730933 ps
CPU time 45.17 seconds
Started Aug 02 05:30:23 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 218456 kb
Host smart-8dd6abc0-07f8-45f0-bbbb-dce13aa1e6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33672
08643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.3367208643
Directory /workspace/17.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.67587306
Short name T352
Test name
Test status
Simulation time 2266616744 ps
CPU time 64.64 seconds
Started Aug 02 05:30:20 PM PDT 24
Finished Aug 02 05:31:25 PM PDT 24
Peak memory 217300 kb
Host smart-6b7ec116-c983-4bfa-9134-23dd7927b50d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=67587306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.67587306
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2743904466
Short name T1443
Test name
Test status
Simulation time 255999221 ps
CPU time 1.16 seconds
Started Aug 02 05:30:22 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 207388 kb
Host smart-f96613b4-04d2-4f82-9da7-a94607f22dcf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2743904466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2743904466
Directory /workspace/17.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.3845971481
Short name T1185
Test name
Test status
Simulation time 202557287 ps
CPU time 0.94 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:22 PM PDT 24
Peak memory 207324 kb
Host smart-468e4b80-cbea-455f-bd15-78057775e098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38459
71481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.3845971481
Directory /workspace/17.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_max_non_iso_usb_traffic.813993703
Short name T2607
Test name
Test status
Simulation time 1789791385 ps
CPU time 13.5 seconds
Started Aug 02 05:30:41 PM PDT 24
Finished Aug 02 05:30:54 PM PDT 24
Peak memory 223916 kb
Host smart-9f435173-cdb6-464d-b84c-40b8c1cc57ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81399
3703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_non_iso_usb_traffic.813993703
Directory /workspace/17.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.1673950434
Short name T2560
Test name
Test status
Simulation time 3093897629 ps
CPU time 22.15 seconds
Started Aug 02 05:30:21 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 215812 kb
Host smart-def717ab-fee7-4096-b6ca-bfd66ea6ef0b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1673950434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.1673950434
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.3331129978
Short name T1918
Test name
Test status
Simulation time 165637311 ps
CPU time 0.86 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 207328 kb
Host smart-2cab5a6b-7458-4cae-b39c-2961b9a10f33
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3331129978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.3331129978
Directory /workspace/17.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.70762921
Short name T1290
Test name
Test status
Simulation time 138184748 ps
CPU time 0.85 seconds
Started Aug 02 05:30:19 PM PDT 24
Finished Aug 02 05:30:20 PM PDT 24
Peak memory 207424 kb
Host smart-740a8c3e-2a10-445f-ba7e-18d283f981b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70762
921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.70762921
Directory /workspace/17.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_nak_trans.1252469392
Short name T162
Test name
Test status
Simulation time 202983662 ps
CPU time 0.91 seconds
Started Aug 02 05:30:41 PM PDT 24
Finished Aug 02 05:30:42 PM PDT 24
Peak memory 207416 kb
Host smart-6596034d-12b7-4d7f-8ba6-91c6133beee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12524
69392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1252469392
Directory /workspace/17.usbdev_nak_trans/latest


Test location /workspace/coverage/default/17.usbdev_out_iso.3312507656
Short name T909
Test name
Test status
Simulation time 164651305 ps
CPU time 0.86 seconds
Started Aug 02 05:30:30 PM PDT 24
Finished Aug 02 05:30:31 PM PDT 24
Peak memory 207368 kb
Host smart-98e745c6-fc32-4079-8251-78b935bcf979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33125
07656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.3312507656
Directory /workspace/17.usbdev_out_iso/latest


Test location /workspace/coverage/default/17.usbdev_out_stall.4176651536
Short name T1476
Test name
Test status
Simulation time 164167552 ps
CPU time 0.85 seconds
Started Aug 02 05:30:32 PM PDT 24
Finished Aug 02 05:30:33 PM PDT 24
Peak memory 207380 kb
Host smart-86be6c58-8442-4a86-b442-d3b7adb29d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41766
51536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.4176651536
Directory /workspace/17.usbdev_out_stall/latest


Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2181922833
Short name T1930
Test name
Test status
Simulation time 200376845 ps
CPU time 1.01 seconds
Started Aug 02 05:30:27 PM PDT 24
Finished Aug 02 05:30:28 PM PDT 24
Peak memory 207420 kb
Host smart-d24d1182-bb37-4edb-a223-72b3d6ee42dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21819
22833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2181922833
Directory /workspace/17.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/17.usbdev_pending_in_trans.2321851829
Short name T1717
Test name
Test status
Simulation time 171239735 ps
CPU time 0.87 seconds
Started Aug 02 05:30:26 PM PDT 24
Finished Aug 02 05:30:27 PM PDT 24
Peak memory 207380 kb
Host smart-bbd06881-c712-40d2-8316-71a375935c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23218
51829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.2321851829
Directory /workspace/17.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.3245707914
Short name T1199
Test name
Test status
Simulation time 248880314 ps
CPU time 1.11 seconds
Started Aug 02 05:30:43 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 207324 kb
Host smart-19763569-2f52-40ac-afe5-1b71a849702f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3245707914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.3245707914
Directory /workspace/17.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.895052547
Short name T515
Test name
Test status
Simulation time 201178220 ps
CPU time 0.9 seconds
Started Aug 02 05:30:26 PM PDT 24
Finished Aug 02 05:30:27 PM PDT 24
Peak memory 207380 kb
Host smart-90bd0051-ac7e-44ca-a741-79ada5481e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89505
2547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.895052547
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2348159654
Short name T2438
Test name
Test status
Simulation time 35735315 ps
CPU time 0.67 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:30:31 PM PDT 24
Peak memory 207136 kb
Host smart-74376bce-0aad-4ef3-9a26-64210c5329a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23481
59654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2348159654
Directory /workspace/17.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3954107236
Short name T2853
Test name
Test status
Simulation time 14955128614 ps
CPU time 37.67 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:31:06 PM PDT 24
Peak memory 220180 kb
Host smart-eb4b8cbf-e94b-4b82-9bb0-f30afc7277d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39541
07236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3954107236
Directory /workspace/17.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/17.usbdev_pkt_received.2800101984
Short name T1872
Test name
Test status
Simulation time 210175426 ps
CPU time 0.95 seconds
Started Aug 02 05:30:30 PM PDT 24
Finished Aug 02 05:30:31 PM PDT 24
Peak memory 207380 kb
Host smart-d3d03f8e-91f4-431c-b23b-91cebb61a2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28001
01984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2800101984
Directory /workspace/17.usbdev_pkt_received/latest


Test location /workspace/coverage/default/17.usbdev_pkt_sent.1163653636
Short name T1934
Test name
Test status
Simulation time 219399060 ps
CPU time 0.96 seconds
Started Aug 02 05:30:45 PM PDT 24
Finished Aug 02 05:30:46 PM PDT 24
Peak memory 207388 kb
Host smart-7e0ea04a-607b-4a15-af12-23fdeeadb605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11636
53636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1163653636
Directory /workspace/17.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2506206551
Short name T551
Test name
Test status
Simulation time 196225048 ps
CPU time 0.89 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207404 kb
Host smart-b9fd3de3-d957-414e-87e1-3463fe5ef954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25062
06551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2506206551
Directory /workspace/17.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.223304136
Short name T2290
Test name
Test status
Simulation time 183745968 ps
CPU time 0.94 seconds
Started Aug 02 05:30:33 PM PDT 24
Finished Aug 02 05:30:34 PM PDT 24
Peak memory 207392 kb
Host smart-ceaada6a-364b-4f80-b4c0-55f1b02dbdca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22330
4136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.223304136
Directory /workspace/17.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1023608339
Short name T2406
Test name
Test status
Simulation time 202538363 ps
CPU time 0.88 seconds
Started Aug 02 05:30:26 PM PDT 24
Finished Aug 02 05:30:27 PM PDT 24
Peak memory 207360 kb
Host smart-0f4e3c9f-6cee-48d3-b3a0-8a6a892c79b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10236
08339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1023608339
Directory /workspace/17.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/17.usbdev_rx_full.2076915169
Short name T341
Test name
Test status
Simulation time 295858506 ps
CPU time 1.09 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207400 kb
Host smart-3a10bd84-0c23-470e-acdb-e6bb17908523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20769
15169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_full.2076915169
Directory /workspace/17.usbdev_rx_full/latest


Test location /workspace/coverage/default/17.usbdev_setup_stage.1384530953
Short name T732
Test name
Test status
Simulation time 151120649 ps
CPU time 0.81 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:30:32 PM PDT 24
Peak memory 207380 kb
Host smart-af701445-aa94-456a-b7da-094a3649df96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13845
30953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1384530953
Directory /workspace/17.usbdev_setup_stage/latest


Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1479760878
Short name T2826
Test name
Test status
Simulation time 187742469 ps
CPU time 0.87 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207344 kb
Host smart-572dc5c8-7fea-4217-bb13-5ff1a652c786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14797
60878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1479760878
Directory /workspace/17.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/17.usbdev_smoke.3653078648
Short name T1075
Test name
Test status
Simulation time 234106841 ps
CPU time 1.01 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207352 kb
Host smart-bb9ad264-8b93-4ac5-bfa6-1e3b022d0d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36530
78648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3653078648
Directory /workspace/17.usbdev_smoke/latest


Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2994029501
Short name T687
Test name
Test status
Simulation time 2076298180 ps
CPU time 56.51 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:31:28 PM PDT 24
Peak memory 217232 kb
Host smart-4dfec425-d60c-4e4d-8070-3824f8827c1e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2994029501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2994029501
Directory /workspace/17.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2380305873
Short name T525
Test name
Test status
Simulation time 165088483 ps
CPU time 0.88 seconds
Started Aug 02 05:30:30 PM PDT 24
Finished Aug 02 05:30:31 PM PDT 24
Peak memory 207384 kb
Host smart-be7ff5cd-ffed-4d5f-b8f7-ec8a6caa4770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23803
05873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2380305873
Directory /workspace/17.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/17.usbdev_stall_trans.831144842
Short name T983
Test name
Test status
Simulation time 177642228 ps
CPU time 0.89 seconds
Started Aug 02 05:30:27 PM PDT 24
Finished Aug 02 05:30:28 PM PDT 24
Peak memory 207352 kb
Host smart-3d1a24ea-0ce3-482a-8725-e114ce8a8f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83114
4842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.831144842
Directory /workspace/17.usbdev_stall_trans/latest


Test location /workspace/coverage/default/17.usbdev_stream_len_max.3390162043
Short name T3022
Test name
Test status
Simulation time 1138443025 ps
CPU time 2.63 seconds
Started Aug 02 05:30:25 PM PDT 24
Finished Aug 02 05:30:28 PM PDT 24
Peak memory 207552 kb
Host smart-5986f693-d4e4-4c96-b872-cee851cdf797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33901
62043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3390162043
Directory /workspace/17.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/17.usbdev_streaming_out.2219216225
Short name T1416
Test name
Test status
Simulation time 2857522334 ps
CPU time 21.12 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 215356 kb
Host smart-5bc27aea-61b4-4902-bc62-7d370c95df59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22192
16225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2219216225
Directory /workspace/17.usbdev_streaming_out/latest


Test location /workspace/coverage/default/17.usbdev_timeout_missing_host_handshake.4262856046
Short name T1117
Test name
Test status
Simulation time 6677108081 ps
CPU time 45.99 seconds
Started Aug 02 05:30:22 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 207612 kb
Host smart-bfc0cab4-ba25-44b3-9cba-203cbf54269c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262856046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_timeout_missing_hos
t_handshake.4262856046
Directory /workspace/17.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/171.usbdev_endpoint_types.4006554564
Short name T414
Test name
Test status
Simulation time 495077209 ps
CPU time 1.34 seconds
Started Aug 02 05:35:20 PM PDT 24
Finished Aug 02 05:35:21 PM PDT 24
Peak memory 207380 kb
Host smart-ee51cea1-a020-4d51-99bb-158b91bfad4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4006554564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.usbdev_endpoint_types.4006554564
Directory /workspace/171.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/172.usbdev_endpoint_types.1081797643
Short name T2295
Test name
Test status
Simulation time 538491335 ps
CPU time 1.59 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207332 kb
Host smart-60106578-bad3-47ff-8284-18fe8b3d3260
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1081797643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.usbdev_endpoint_types.1081797643
Directory /workspace/172.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/173.usbdev_endpoint_types.1004433146
Short name T411
Test name
Test status
Simulation time 224768790 ps
CPU time 0.94 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:08 PM PDT 24
Peak memory 207304 kb
Host smart-77820695-fdfd-44bf-8023-e369df7ffbab
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1004433146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.usbdev_endpoint_types.1004433146
Directory /workspace/173.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/174.usbdev_endpoint_types.1637988285
Short name T366
Test name
Test status
Simulation time 521658585 ps
CPU time 1.42 seconds
Started Aug 02 05:35:13 PM PDT 24
Finished Aug 02 05:35:14 PM PDT 24
Peak memory 207356 kb
Host smart-67099754-6c47-4fc0-8a04-c8cd76ecbeb0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1637988285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.usbdev_endpoint_types.1637988285
Directory /workspace/174.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/176.usbdev_endpoint_types.855232092
Short name T445
Test name
Test status
Simulation time 187640051 ps
CPU time 0.88 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207176 kb
Host smart-b2a9c7e9-c7ad-4de8-91bf-7414a33c0396
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=855232092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.usbdev_endpoint_types.855232092
Directory /workspace/176.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/178.usbdev_endpoint_types.3139157296
Short name T2581
Test name
Test status
Simulation time 734303242 ps
CPU time 1.81 seconds
Started Aug 02 05:35:30 PM PDT 24
Finished Aug 02 05:35:32 PM PDT 24
Peak memory 207352 kb
Host smart-d422ba6b-ae1e-4812-a50f-fee74b3fbe34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3139157296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.usbdev_endpoint_types.3139157296
Directory /workspace/178.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/179.usbdev_endpoint_types.1162699285
Short name T412
Test name
Test status
Simulation time 386176087 ps
CPU time 1.19 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:35:17 PM PDT 24
Peak memory 207268 kb
Host smart-cb83b171-43dd-4baf-afa3-917b6987d626
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1162699285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.usbdev_endpoint_types.1162699285
Directory /workspace/179.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/18.usbdev_alert_test.2866908450
Short name T2458
Test name
Test status
Simulation time 39130984 ps
CPU time 0.67 seconds
Started Aug 02 05:30:34 PM PDT 24
Finished Aug 02 05:30:35 PM PDT 24
Peak memory 207552 kb
Host smart-513b24c6-506a-434e-a619-f06381aee4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2866908450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.2866908450
Directory /workspace/18.usbdev_alert_test/latest


Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.93865609
Short name T2171
Test name
Test status
Simulation time 9934740530 ps
CPU time 13.09 seconds
Started Aug 02 05:30:29 PM PDT 24
Finished Aug 02 05:30:42 PM PDT 24
Peak memory 207620 kb
Host smart-0e659b18-0043-488b-b5f0-a50b9aa4acfe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93865609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon
_wake_disconnect.93865609
Directory /workspace/18.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1915459352
Short name T2398
Test name
Test status
Simulation time 21192141541 ps
CPU time 25.16 seconds
Started Aug 02 05:30:25 PM PDT 24
Finished Aug 02 05:30:51 PM PDT 24
Peak memory 207624 kb
Host smart-ee90a912-946a-4c33-9464-f5e62d329415
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915459352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1915459352
Directory /workspace/18.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3576008547
Short name T2667
Test name
Test status
Simulation time 29693511831 ps
CPU time 32.14 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:31:04 PM PDT 24
Peak memory 207604 kb
Host smart-7fcbc1dc-990c-4147-8c4c-eccfabf408ef
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576008547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_a
on_wake_resume.3576008547
Directory /workspace/18.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/18.usbdev_av_buffer.4231474724
Short name T2841
Test name
Test status
Simulation time 246453391 ps
CPU time 0.97 seconds
Started Aug 02 05:30:29 PM PDT 24
Finished Aug 02 05:30:30 PM PDT 24
Peak memory 207452 kb
Host smart-66fdd040-cb91-4fe0-af20-3844afe6bd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42314
74724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.4231474724
Directory /workspace/18.usbdev_av_buffer/latest


Test location /workspace/coverage/default/18.usbdev_bitstuff_err.3973701197
Short name T1848
Test name
Test status
Simulation time 166498711 ps
CPU time 0.85 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207344 kb
Host smart-33341b2a-edf0-4fd9-8822-b1d09b373c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39737
01197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.3973701197
Directory /workspace/18.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.4017140396
Short name T557
Test name
Test status
Simulation time 461948941 ps
CPU time 1.46 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:30 PM PDT 24
Peak memory 207452 kb
Host smart-9363f429-8c31-4021-bdd8-3abf41c341ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40171
40396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.4017140396
Directory /workspace/18.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1898296003
Short name T1162
Test name
Test status
Simulation time 985980712 ps
CPU time 2.6 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:30 PM PDT 24
Peak memory 207576 kb
Host smart-00652970-a65a-4004-89ce-eb76af7507e1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1898296003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1898296003
Directory /workspace/18.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/18.usbdev_device_timeout.3695723693
Short name T1323
Test name
Test status
Simulation time 175505157 ps
CPU time 0.96 seconds
Started Aug 02 05:30:32 PM PDT 24
Finished Aug 02 05:30:33 PM PDT 24
Peak memory 207396 kb
Host smart-e1850b52-9bd1-4467-a8cd-e8c4311975bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695723693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_timeout.3695723693
Directory /workspace/18.usbdev_device_timeout/latest


Test location /workspace/coverage/default/18.usbdev_disable_endpoint.3279574717
Short name T1248
Test name
Test status
Simulation time 694422349 ps
CPU time 1.94 seconds
Started Aug 02 05:30:27 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207300 kb
Host smart-bf06a78f-9ee8-45ed-ac4c-870fe2a5d832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32795
74717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.3279574717
Directory /workspace/18.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/18.usbdev_disconnected.3910373849
Short name T24
Test name
Test status
Simulation time 151187439 ps
CPU time 0.79 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207412 kb
Host smart-c763e0a4-8f6a-4725-a6f8-6dfab8b9f328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39103
73849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.3910373849
Directory /workspace/18.usbdev_disconnected/latest


Test location /workspace/coverage/default/18.usbdev_enable.1981246329
Short name T2568
Test name
Test status
Simulation time 38265901 ps
CPU time 0.7 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:29 PM PDT 24
Peak memory 207332 kb
Host smart-cc095fab-2aac-4497-b80f-6e3b9c76ce05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19812
46329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1981246329
Directory /workspace/18.usbdev_enable/latest


Test location /workspace/coverage/default/18.usbdev_endpoint_access.715606805
Short name T1268
Test name
Test status
Simulation time 856082427 ps
CPU time 2.29 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:31 PM PDT 24
Peak memory 207488 kb
Host smart-6ed4abab-3d92-4dc3-98fe-d140a96d97f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71560
6805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.715606805
Directory /workspace/18.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/18.usbdev_endpoint_types.3288429555
Short name T365
Test name
Test status
Simulation time 542241051 ps
CPU time 1.4 seconds
Started Aug 02 05:30:28 PM PDT 24
Finished Aug 02 05:30:30 PM PDT 24
Peak memory 207368 kb
Host smart-53a1b05e-8c57-4b5b-9a81-c480c97c9f28
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3288429555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_types.3288429555
Directory /workspace/18.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/18.usbdev_fifo_rst.3321875858
Short name T2530
Test name
Test status
Simulation time 171579176 ps
CPU time 2.2 seconds
Started Aug 02 05:30:29 PM PDT 24
Finished Aug 02 05:30:31 PM PDT 24
Peak memory 207520 kb
Host smart-1c25e7f4-f730-4ee2-a93b-e3d93174b071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33218
75858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3321875858
Directory /workspace/18.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/18.usbdev_in_iso.252287958
Short name T929
Test name
Test status
Simulation time 239254704 ps
CPU time 1.12 seconds
Started Aug 02 05:30:29 PM PDT 24
Finished Aug 02 05:30:31 PM PDT 24
Peak memory 207560 kb
Host smart-e7604d13-8610-4052-b040-598ff4de76ff
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=252287958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.252287958
Directory /workspace/18.usbdev_in_iso/latest


Test location /workspace/coverage/default/18.usbdev_in_stall.3614426182
Short name T3043
Test name
Test status
Simulation time 155921492 ps
CPU time 0.81 seconds
Started Aug 02 05:30:29 PM PDT 24
Finished Aug 02 05:30:30 PM PDT 24
Peak memory 207356 kb
Host smart-1f09953b-a8b5-4a91-914e-b4a0b742fccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36144
26182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.3614426182
Directory /workspace/18.usbdev_in_stall/latest


Test location /workspace/coverage/default/18.usbdev_in_trans.2938655414
Short name T3080
Test name
Test status
Simulation time 198157606 ps
CPU time 0.92 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:30:32 PM PDT 24
Peak memory 207388 kb
Host smart-d7532797-f95e-4ade-95cc-3ae1bb65a132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29386
55414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2938655414
Directory /workspace/18.usbdev_in_trans/latest


Test location /workspace/coverage/default/18.usbdev_invalid_sync.1432318230
Short name T1424
Test name
Test status
Simulation time 2410519311 ps
CPU time 22 seconds
Started Aug 02 05:30:38 PM PDT 24
Finished Aug 02 05:31:01 PM PDT 24
Peak memory 218540 kb
Host smart-edd33fee-9c4f-4718-94a1-eaa45098cab5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1432318230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.1432318230
Directory /workspace/18.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/18.usbdev_iso_retraction.3296008797
Short name T892
Test name
Test status
Simulation time 8982899377 ps
CPU time 59 seconds
Started Aug 02 05:30:32 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207680 kb
Host smart-a56072d2-db0f-4a1c-a42c-f0b37dd4bc45
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3296008797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.3296008797
Directory /workspace/18.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/18.usbdev_link_in_err.3154822350
Short name T1426
Test name
Test status
Simulation time 286429969 ps
CPU time 1.07 seconds
Started Aug 02 05:30:32 PM PDT 24
Finished Aug 02 05:30:33 PM PDT 24
Peak memory 207404 kb
Host smart-c0587f48-2fcf-4d56-90ae-e48c79a23573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31548
22350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3154822350
Directory /workspace/18.usbdev_link_in_err/latest


Test location /workspace/coverage/default/18.usbdev_link_resume.27226936
Short name T2392
Test name
Test status
Simulation time 22952186902 ps
CPU time 43.67 seconds
Started Aug 02 05:30:30 PM PDT 24
Finished Aug 02 05:31:13 PM PDT 24
Peak memory 215868 kb
Host smart-859085ce-ef4b-4f97-a248-426f7db4d0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27226
936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.27226936
Directory /workspace/18.usbdev_link_resume/latest


Test location /workspace/coverage/default/18.usbdev_link_suspend.627243977
Short name T2993
Test name
Test status
Simulation time 10204155101 ps
CPU time 16.1 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:30:47 PM PDT 24
Peak memory 207484 kb
Host smart-684ff68c-9687-4892-b455-3278ae6513ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62724
3977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.627243977
Directory /workspace/18.usbdev_link_suspend/latest


Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.2366372643
Short name T2124
Test name
Test status
Simulation time 5370698526 ps
CPU time 153.53 seconds
Started Aug 02 05:30:29 PM PDT 24
Finished Aug 02 05:33:03 PM PDT 24
Peak memory 218492 kb
Host smart-de5d04a7-f4df-41d6-a062-0b0c1dffeb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23663
72643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.2366372643
Directory /workspace/18.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.3581362967
Short name T657
Test name
Test status
Simulation time 4021053764 ps
CPU time 115.29 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 216656 kb
Host smart-1ff05e85-09a7-4792-9f1b-1eda4eb22730
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3581362967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.3581362967
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1897071225
Short name T871
Test name
Test status
Simulation time 240220940 ps
CPU time 1.05 seconds
Started Aug 02 05:30:29 PM PDT 24
Finished Aug 02 05:30:30 PM PDT 24
Peak memory 207380 kb
Host smart-0651e9ad-83aa-46a6-b24a-0b7783b315b8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1897071225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1897071225
Directory /workspace/18.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.835099071
Short name T541
Test name
Test status
Simulation time 182497477 ps
CPU time 0.91 seconds
Started Aug 02 05:30:38 PM PDT 24
Finished Aug 02 05:30:39 PM PDT 24
Peak memory 207388 kb
Host smart-71e38f58-b0e3-46cd-abc4-e0c5c7c3e10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83509
9071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.835099071
Directory /workspace/18.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_max_non_iso_usb_traffic.3286306881
Short name T2305
Test name
Test status
Simulation time 2204716901 ps
CPU time 59.72 seconds
Started Aug 02 05:30:35 PM PDT 24
Finished Aug 02 05:31:35 PM PDT 24
Peak memory 215780 kb
Host smart-d7e92509-9087-4fab-85c3-8a40f6d6b905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
06881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_non_iso_usb_traffic.3286306881
Directory /workspace/18.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3817138156
Short name T2763
Test name
Test status
Simulation time 3391352374 ps
CPU time 25.76 seconds
Started Aug 02 05:30:32 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 215900 kb
Host smart-986d802f-3f2b-4796-bf37-573daeecf937
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3817138156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3817138156
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3224871301
Short name T1633
Test name
Test status
Simulation time 178347926 ps
CPU time 0.9 seconds
Started Aug 02 05:30:32 PM PDT 24
Finished Aug 02 05:30:33 PM PDT 24
Peak memory 207392 kb
Host smart-beff3a5f-f5b5-450a-870d-241a52974dc2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3224871301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3224871301
Directory /workspace/18.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1410613879
Short name T1110
Test name
Test status
Simulation time 181878743 ps
CPU time 0.87 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:30:32 PM PDT 24
Peak memory 207316 kb
Host smart-2838a616-2917-467a-b63f-435798cec825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14106
13879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1410613879
Directory /workspace/18.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_nak_trans.2705435750
Short name T160
Test name
Test status
Simulation time 203190645 ps
CPU time 0.88 seconds
Started Aug 02 05:30:41 PM PDT 24
Finished Aug 02 05:30:42 PM PDT 24
Peak memory 207316 kb
Host smart-492a24cb-4061-479d-a076-4c171fe1a8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27054
35750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.2705435750
Directory /workspace/18.usbdev_nak_trans/latest


Test location /workspace/coverage/default/18.usbdev_out_iso.3951592543
Short name T2849
Test name
Test status
Simulation time 156936014 ps
CPU time 0.84 seconds
Started Aug 02 05:30:31 PM PDT 24
Finished Aug 02 05:30:32 PM PDT 24
Peak memory 206824 kb
Host smart-30c469b3-c8eb-479f-b278-d18a00d390fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39515
92543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3951592543
Directory /workspace/18.usbdev_out_iso/latest


Test location /workspace/coverage/default/18.usbdev_out_stall.1297212297
Short name T22
Test name
Test status
Simulation time 174556724 ps
CPU time 0.87 seconds
Started Aug 02 05:30:32 PM PDT 24
Finished Aug 02 05:30:33 PM PDT 24
Peak memory 207340 kb
Host smart-f7f16995-89f0-44ed-8615-129d703fcddf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12972
12297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1297212297
Directory /workspace/18.usbdev_out_stall/latest


Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2880053157
Short name T2857
Test name
Test status
Simulation time 158659852 ps
CPU time 0.83 seconds
Started Aug 02 05:30:32 PM PDT 24
Finished Aug 02 05:30:33 PM PDT 24
Peak memory 207340 kb
Host smart-efa2f2f1-0947-475b-814c-a040ce750c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28800
53157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2880053157
Directory /workspace/18.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/18.usbdev_pending_in_trans.2886435415
Short name T3032
Test name
Test status
Simulation time 151910994 ps
CPU time 0.89 seconds
Started Aug 02 05:30:34 PM PDT 24
Finished Aug 02 05:30:35 PM PDT 24
Peak memory 207408 kb
Host smart-c57f67c7-caca-4b9c-803b-362a51efad1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28864
35415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.2886435415
Directory /workspace/18.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3640909363
Short name T674
Test name
Test status
Simulation time 225107486 ps
CPU time 1.04 seconds
Started Aug 02 05:30:45 PM PDT 24
Finished Aug 02 05:30:46 PM PDT 24
Peak memory 207368 kb
Host smart-9a46eb51-e127-4dd9-83b2-a53806fa1e4b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3640909363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3640909363
Directory /workspace/18.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.4209993399
Short name T706
Test name
Test status
Simulation time 143862635 ps
CPU time 0.8 seconds
Started Aug 02 05:30:37 PM PDT 24
Finished Aug 02 05:30:38 PM PDT 24
Peak memory 207388 kb
Host smart-79e6f85e-5492-4b52-b04b-9c7a4edbc761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42099
93399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.4209993399
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3543537322
Short name T1033
Test name
Test status
Simulation time 44054574 ps
CPU time 0.7 seconds
Started Aug 02 05:30:52 PM PDT 24
Finished Aug 02 05:30:53 PM PDT 24
Peak memory 207324 kb
Host smart-a5041957-cb39-4cbf-800b-a92025118380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35435
37322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3543537322
Directory /workspace/18.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/18.usbdev_pkt_buffer.1719787149
Short name T2542
Test name
Test status
Simulation time 15760411782 ps
CPU time 41.36 seconds
Started Aug 02 05:30:35 PM PDT 24
Finished Aug 02 05:31:16 PM PDT 24
Peak memory 215888 kb
Host smart-743ff2b7-abae-447d-a05e-128925245d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17197
87149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.1719787149
Directory /workspace/18.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/18.usbdev_pkt_received.2213920047
Short name T576
Test name
Test status
Simulation time 190105778 ps
CPU time 0.97 seconds
Started Aug 02 05:30:34 PM PDT 24
Finished Aug 02 05:30:35 PM PDT 24
Peak memory 207408 kb
Host smart-4a605c4e-92da-4045-a113-5857f0692d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22139
20047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2213920047
Directory /workspace/18.usbdev_pkt_received/latest


Test location /workspace/coverage/default/18.usbdev_pkt_sent.3670863631
Short name T563
Test name
Test status
Simulation time 240836261 ps
CPU time 1.05 seconds
Started Aug 02 05:30:39 PM PDT 24
Finished Aug 02 05:30:40 PM PDT 24
Peak memory 207384 kb
Host smart-31bf02af-26a3-4f03-aaf1-f727c9ec5d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36708
63631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3670863631
Directory /workspace/18.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3765168836
Short name T2712
Test name
Test status
Simulation time 247692409 ps
CPU time 0.96 seconds
Started Aug 02 05:30:42 PM PDT 24
Finished Aug 02 05:30:43 PM PDT 24
Peak memory 207416 kb
Host smart-bd3aa550-fbe2-40ab-a48e-e5a7c66c7884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37651
68836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3765168836
Directory /workspace/18.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.10110602
Short name T1978
Test name
Test status
Simulation time 178483301 ps
CPU time 0.87 seconds
Started Aug 02 05:30:35 PM PDT 24
Finished Aug 02 05:30:36 PM PDT 24
Peak memory 207392 kb
Host smart-da8d0343-6838-46d5-9f93-b9f42c340da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10110
602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.10110602
Directory /workspace/18.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/18.usbdev_rx_crc_err.741069236
Short name T1874
Test name
Test status
Simulation time 147089101 ps
CPU time 0.92 seconds
Started Aug 02 05:30:42 PM PDT 24
Finished Aug 02 05:30:43 PM PDT 24
Peak memory 207372 kb
Host smart-71a03eb0-3731-4320-a36f-7e938cf67e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74106
9236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.741069236
Directory /workspace/18.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/18.usbdev_rx_full.539694390
Short name T1105
Test name
Test status
Simulation time 412157952 ps
CPU time 1.32 seconds
Started Aug 02 05:30:37 PM PDT 24
Finished Aug 02 05:30:38 PM PDT 24
Peak memory 207404 kb
Host smart-6f9eca8b-0ac4-4d22-9db4-abb5d142afdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53969
4390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_full.539694390
Directory /workspace/18.usbdev_rx_full/latest


Test location /workspace/coverage/default/18.usbdev_setup_stage.2144168707
Short name T811
Test name
Test status
Simulation time 158447041 ps
CPU time 0.84 seconds
Started Aug 02 05:30:37 PM PDT 24
Finished Aug 02 05:30:38 PM PDT 24
Peak memory 207352 kb
Host smart-a1f3fc01-30ac-48dd-a171-2aa0a71033d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21441
68707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2144168707
Directory /workspace/18.usbdev_setup_stage/latest


Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.2163220586
Short name T3069
Test name
Test status
Simulation time 159641924 ps
CPU time 0.85 seconds
Started Aug 02 05:30:36 PM PDT 24
Finished Aug 02 05:30:37 PM PDT 24
Peak memory 207432 kb
Host smart-906ab9e2-ca74-4bf9-b789-4cf5969c9128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
20586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.2163220586
Directory /workspace/18.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/18.usbdev_smoke.3575929846
Short name T2851
Test name
Test status
Simulation time 234640181 ps
CPU time 1.09 seconds
Started Aug 02 05:30:38 PM PDT 24
Finished Aug 02 05:30:40 PM PDT 24
Peak memory 207440 kb
Host smart-8423ef71-7dab-4f05-8166-018b982748f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35759
29846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.3575929846
Directory /workspace/18.usbdev_smoke/latest


Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2536036099
Short name T1201
Test name
Test status
Simulation time 2075001438 ps
CPU time 20.58 seconds
Started Aug 02 05:30:48 PM PDT 24
Finished Aug 02 05:31:09 PM PDT 24
Peak memory 223864 kb
Host smart-f7b6263d-1e78-4cad-9910-54b954d31bf9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2536036099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2536036099
Directory /workspace/18.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.2028386884
Short name T2308
Test name
Test status
Simulation time 179778303 ps
CPU time 0.88 seconds
Started Aug 02 05:30:43 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 207376 kb
Host smart-90663464-e95e-4169-898e-518908edcc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20283
86884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.2028386884
Directory /workspace/18.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/18.usbdev_stall_trans.4289026870
Short name T814
Test name
Test status
Simulation time 191498542 ps
CPU time 0.92 seconds
Started Aug 02 05:30:41 PM PDT 24
Finished Aug 02 05:30:42 PM PDT 24
Peak memory 207316 kb
Host smart-5cd70cf7-15ea-4681-8b3d-2d1ac86be180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42890
26870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.4289026870
Directory /workspace/18.usbdev_stall_trans/latest


Test location /workspace/coverage/default/18.usbdev_stream_len_max.54860887
Short name T1849
Test name
Test status
Simulation time 946267983 ps
CPU time 2.37 seconds
Started Aug 02 05:30:33 PM PDT 24
Finished Aug 02 05:30:36 PM PDT 24
Peak memory 207544 kb
Host smart-079e49e0-8307-4b8b-8bea-cf04bb698a4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54860
887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.54860887
Directory /workspace/18.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/18.usbdev_streaming_out.2344466872
Short name T1538
Test name
Test status
Simulation time 2733237218 ps
CPU time 21.75 seconds
Started Aug 02 05:30:40 PM PDT 24
Finished Aug 02 05:31:02 PM PDT 24
Peak memory 215912 kb
Host smart-bdab5805-8bf7-413b-8b71-a49f735e0597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
66872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2344466872
Directory /workspace/18.usbdev_streaming_out/latest


Test location /workspace/coverage/default/18.usbdev_timeout_missing_host_handshake.4132863264
Short name T2368
Test name
Test status
Simulation time 2951735204 ps
CPU time 24.45 seconds
Started Aug 02 05:30:29 PM PDT 24
Finished Aug 02 05:30:53 PM PDT 24
Peak memory 207716 kb
Host smart-e77c5e65-5f05-4f8b-9061-b44001bc422c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132863264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_timeout_missing_hos
t_handshake.4132863264
Directory /workspace/18.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/180.usbdev_endpoint_types.1696574139
Short name T485
Test name
Test status
Simulation time 233787534 ps
CPU time 1.01 seconds
Started Aug 02 05:35:33 PM PDT 24
Finished Aug 02 05:35:34 PM PDT 24
Peak memory 207308 kb
Host smart-3a659466-d122-44d0-9f6c-e8271a72aeaa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1696574139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.usbdev_endpoint_types.1696574139
Directory /workspace/180.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/181.usbdev_endpoint_types.126791966
Short name T377
Test name
Test status
Simulation time 258110312 ps
CPU time 0.97 seconds
Started Aug 02 05:35:17 PM PDT 24
Finished Aug 02 05:35:18 PM PDT 24
Peak memory 207364 kb
Host smart-7d5ed019-453a-4c24-b903-57b34cb67304
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=126791966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.usbdev_endpoint_types.126791966
Directory /workspace/181.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/182.usbdev_endpoint_types.3540062925
Short name T378
Test name
Test status
Simulation time 745018759 ps
CPU time 1.67 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207300 kb
Host smart-4f7fad60-593f-4538-8145-74d728515a84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3540062925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.usbdev_endpoint_types.3540062925
Directory /workspace/182.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/183.usbdev_endpoint_types.3629775427
Short name T407
Test name
Test status
Simulation time 849274410 ps
CPU time 1.7 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207356 kb
Host smart-3d332d7b-add2-41e5-ba81-b717395cbfb7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3629775427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.usbdev_endpoint_types.3629775427
Directory /workspace/183.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/184.usbdev_endpoint_types.3724319272
Short name T101
Test name
Test status
Simulation time 288268574 ps
CPU time 1 seconds
Started Aug 02 05:35:21 PM PDT 24
Finished Aug 02 05:35:22 PM PDT 24
Peak memory 207336 kb
Host smart-5a9ba948-6ea7-4b18-96a7-97009afcc77a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3724319272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.usbdev_endpoint_types.3724319272
Directory /workspace/184.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/185.usbdev_endpoint_types.3675064548
Short name T472
Test name
Test status
Simulation time 473130768 ps
CPU time 1.27 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207408 kb
Host smart-e02d1a42-17ab-4880-b1ee-4040fb5847b1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3675064548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.usbdev_endpoint_types.3675064548
Directory /workspace/185.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/186.usbdev_endpoint_types.1497261949
Short name T1811
Test name
Test status
Simulation time 519294974 ps
CPU time 1.48 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:35:17 PM PDT 24
Peak memory 207356 kb
Host smart-e4c4c296-94a8-43b0-8b8c-7605771917e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1497261949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.usbdev_endpoint_types.1497261949
Directory /workspace/186.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/187.usbdev_endpoint_types.589318759
Short name T2209
Test name
Test status
Simulation time 402533060 ps
CPU time 1.28 seconds
Started Aug 02 05:35:12 PM PDT 24
Finished Aug 02 05:35:13 PM PDT 24
Peak memory 207388 kb
Host smart-3595dfea-315e-4b15-af82-9b131c3fd5f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=589318759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.usbdev_endpoint_types.589318759
Directory /workspace/187.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/188.usbdev_endpoint_types.3936546834
Short name T1678
Test name
Test status
Simulation time 260795399 ps
CPU time 0.97 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207408 kb
Host smart-8eefdc9d-5aab-4c18-a656-86c8248fe4c8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3936546834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.usbdev_endpoint_types.3936546834
Directory /workspace/188.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/189.usbdev_endpoint_types.3643659258
Short name T2423
Test name
Test status
Simulation time 280772439 ps
CPU time 1.01 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207308 kb
Host smart-f958b48c-6936-4eb9-b77f-c546ccd1167e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3643659258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.usbdev_endpoint_types.3643659258
Directory /workspace/189.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/19.usbdev_alert_test.2862492726
Short name T2140
Test name
Test status
Simulation time 69594087 ps
CPU time 0.73 seconds
Started Aug 02 05:30:49 PM PDT 24
Finished Aug 02 05:30:50 PM PDT 24
Peak memory 207544 kb
Host smart-d58c1eec-ebdf-4ff1-b59a-a5f1bbe8e2e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2862492726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2862492726
Directory /workspace/19.usbdev_alert_test/latest


Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.3123909206
Short name T2292
Test name
Test status
Simulation time 6908785288 ps
CPU time 8.69 seconds
Started Aug 02 05:30:35 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 215816 kb
Host smart-ef8b21e9-3609-4c5b-b182-28c8c3b8110b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123909206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_a
on_wake_disconnect.3123909206
Directory /workspace/19.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.3499517210
Short name T2179
Test name
Test status
Simulation time 19692156905 ps
CPU time 27 seconds
Started Aug 02 05:30:34 PM PDT 24
Finished Aug 02 05:31:02 PM PDT 24
Peak memory 207668 kb
Host smart-fbcf2afb-f42d-4144-9dc3-d461bb159a4c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499517210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.3499517210
Directory /workspace/19.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.112724673
Short name T1650
Test name
Test status
Simulation time 29801153160 ps
CPU time 41.59 seconds
Started Aug 02 05:30:41 PM PDT 24
Finished Aug 02 05:31:22 PM PDT 24
Peak memory 207672 kb
Host smart-575af1bb-5807-4a83-8518-c0c1cf70f854
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112724673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_ao
n_wake_resume.112724673
Directory /workspace/19.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/19.usbdev_av_buffer.3575484909
Short name T1865
Test name
Test status
Simulation time 191149453 ps
CPU time 0.9 seconds
Started Aug 02 05:30:57 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 207316 kb
Host smart-092795cd-8f7b-43d3-b517-5df1e612eb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35754
84909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.3575484909
Directory /workspace/19.usbdev_av_buffer/latest


Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1403160220
Short name T1475
Test name
Test status
Simulation time 140560182 ps
CPU time 0.86 seconds
Started Aug 02 05:30:48 PM PDT 24
Finished Aug 02 05:30:49 PM PDT 24
Peak memory 207388 kb
Host smart-e3c9ba6b-c67f-4a19-a136-c15898f684e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14031
60220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1403160220
Directory /workspace/19.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.940386111
Short name T805
Test name
Test status
Simulation time 343683160 ps
CPU time 1.26 seconds
Started Aug 02 05:30:35 PM PDT 24
Finished Aug 02 05:30:37 PM PDT 24
Peak memory 207404 kb
Host smart-c80fd528-49f3-4340-ba6d-3b52f111b940
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94038
6111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.940386111
Directory /workspace/19.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3138519604
Short name T2212
Test name
Test status
Simulation time 1135982996 ps
CPU time 2.82 seconds
Started Aug 02 05:30:45 PM PDT 24
Finished Aug 02 05:30:48 PM PDT 24
Peak memory 207648 kb
Host smart-2ae219e3-49cb-4da5-9eb0-b25e4b3c1a5a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3138519604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3138519604
Directory /workspace/19.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/19.usbdev_device_address.3388290657
Short name T1919
Test name
Test status
Simulation time 49415259220 ps
CPU time 69 seconds
Started Aug 02 05:30:51 PM PDT 24
Finished Aug 02 05:32:00 PM PDT 24
Peak memory 207628 kb
Host smart-9392bb4a-745b-4c89-a688-a0512b9ac2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33882
90657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.3388290657
Directory /workspace/19.usbdev_device_address/latest


Test location /workspace/coverage/default/19.usbdev_device_timeout.1838289669
Short name T1477
Test name
Test status
Simulation time 3843796434 ps
CPU time 35.16 seconds
Started Aug 02 05:30:36 PM PDT 24
Finished Aug 02 05:31:11 PM PDT 24
Peak memory 207760 kb
Host smart-54194da5-7a4b-44b7-916f-145f7bbd48d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838289669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_timeout.1838289669
Directory /workspace/19.usbdev_device_timeout/latest


Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1153241513
Short name T2813
Test name
Test status
Simulation time 1189488706 ps
CPU time 2.32 seconds
Started Aug 02 05:30:36 PM PDT 24
Finished Aug 02 05:30:39 PM PDT 24
Peak memory 207380 kb
Host smart-c1984065-07c8-4b9c-93ee-09cb5c57eb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11532
41513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1153241513
Directory /workspace/19.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/19.usbdev_disconnected.1549408203
Short name T2459
Test name
Test status
Simulation time 136051417 ps
CPU time 0.86 seconds
Started Aug 02 05:30:43 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 207328 kb
Host smart-dfd2c716-3949-493a-8b95-531362485ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15494
08203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1549408203
Directory /workspace/19.usbdev_disconnected/latest


Test location /workspace/coverage/default/19.usbdev_enable.368503873
Short name T1435
Test name
Test status
Simulation time 33554598 ps
CPU time 0.72 seconds
Started Aug 02 05:30:46 PM PDT 24
Finished Aug 02 05:30:47 PM PDT 24
Peak memory 207304 kb
Host smart-176c8e09-074d-4652-8685-893ce8550234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36850
3873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.368503873
Directory /workspace/19.usbdev_enable/latest


Test location /workspace/coverage/default/19.usbdev_endpoint_access.2655069241
Short name T3035
Test name
Test status
Simulation time 785218166 ps
CPU time 2.18 seconds
Started Aug 02 05:30:37 PM PDT 24
Finished Aug 02 05:30:40 PM PDT 24
Peak memory 207584 kb
Host smart-37f3e67c-9092-446e-b6e5-79d81bc6f53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26550
69241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2655069241
Directory /workspace/19.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/19.usbdev_endpoint_types.3186099453
Short name T480
Test name
Test status
Simulation time 161430220 ps
CPU time 0.84 seconds
Started Aug 02 05:30:40 PM PDT 24
Finished Aug 02 05:30:41 PM PDT 24
Peak memory 207268 kb
Host smart-6c814a02-80ff-4d9a-9e5e-37f274853d84
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3186099453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_types.3186099453
Directory /workspace/19.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/19.usbdev_fifo_rst.2028695748
Short name T1432
Test name
Test status
Simulation time 192406809 ps
CPU time 2.24 seconds
Started Aug 02 05:30:46 PM PDT 24
Finished Aug 02 05:30:49 PM PDT 24
Peak memory 207492 kb
Host smart-2584124c-119d-4055-9f6e-0d79195eb348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20286
95748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.2028695748
Directory /workspace/19.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/19.usbdev_in_iso.1922441889
Short name T1808
Test name
Test status
Simulation time 162858485 ps
CPU time 0.9 seconds
Started Aug 02 05:30:48 PM PDT 24
Finished Aug 02 05:30:49 PM PDT 24
Peak memory 207400 kb
Host smart-af6932dd-833e-472d-b0c1-9d0b2c701c8e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1922441889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.1922441889
Directory /workspace/19.usbdev_in_iso/latest


Test location /workspace/coverage/default/19.usbdev_in_stall.2182986648
Short name T1467
Test name
Test status
Simulation time 146000809 ps
CPU time 0.87 seconds
Started Aug 02 05:30:40 PM PDT 24
Finished Aug 02 05:30:41 PM PDT 24
Peak memory 207288 kb
Host smart-5df120d3-8ef2-4d57-bb47-1f69f9833dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21829
86648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2182986648
Directory /workspace/19.usbdev_in_stall/latest


Test location /workspace/coverage/default/19.usbdev_in_trans.2157421323
Short name T1943
Test name
Test status
Simulation time 272194010 ps
CPU time 0.98 seconds
Started Aug 02 05:30:34 PM PDT 24
Finished Aug 02 05:30:35 PM PDT 24
Peak memory 207404 kb
Host smart-e1d0715c-a818-4d6d-a9a9-b9475dc781cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21574
21323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2157421323
Directory /workspace/19.usbdev_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_invalid_sync.2027640957
Short name T1132
Test name
Test status
Simulation time 3604909096 ps
CPU time 36.26 seconds
Started Aug 02 05:30:36 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 223916 kb
Host smart-1ec81c9d-f002-467c-87ad-6f723ffe9d6c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2027640957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.2027640957
Directory /workspace/19.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/19.usbdev_iso_retraction.4111228616
Short name T1427
Test name
Test status
Simulation time 3619837707 ps
CPU time 24.35 seconds
Started Aug 02 05:30:34 PM PDT 24
Finished Aug 02 05:30:59 PM PDT 24
Peak memory 207676 kb
Host smart-7c53b9fb-ff9f-45ce-bf3d-b40d85e4072d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4111228616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.4111228616
Directory /workspace/19.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/19.usbdev_link_in_err.3649727175
Short name T2843
Test name
Test status
Simulation time 231040972 ps
CPU time 0.98 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:56 PM PDT 24
Peak memory 207412 kb
Host smart-808d0eff-b91f-4ea1-afea-9880b455bfa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36497
27175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3649727175
Directory /workspace/19.usbdev_link_in_err/latest


Test location /workspace/coverage/default/19.usbdev_link_resume.1953840016
Short name T2979
Test name
Test status
Simulation time 29164876851 ps
CPU time 49.07 seconds
Started Aug 02 05:30:33 PM PDT 24
Finished Aug 02 05:31:23 PM PDT 24
Peak memory 207612 kb
Host smart-f7da3c67-b2fb-4009-b11c-6e8703703d63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19538
40016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.1953840016
Directory /workspace/19.usbdev_link_resume/latest


Test location /workspace/coverage/default/19.usbdev_link_suspend.1996313720
Short name T3093
Test name
Test status
Simulation time 5432601003 ps
CPU time 7.99 seconds
Started Aug 02 05:30:41 PM PDT 24
Finished Aug 02 05:30:49 PM PDT 24
Peak memory 207568 kb
Host smart-b437a44b-6277-4c33-a6d0-d523568c7d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19963
13720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1996313720
Directory /workspace/19.usbdev_link_suspend/latest


Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.4083782709
Short name T554
Test name
Test status
Simulation time 4991348315 ps
CPU time 35.55 seconds
Started Aug 02 05:30:39 PM PDT 24
Finished Aug 02 05:31:15 PM PDT 24
Peak memory 217640 kb
Host smart-ba0fb91e-41a6-4e50-b94e-bdb9c4cdf972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40837
82709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.4083782709
Directory /workspace/19.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3761523959
Short name T2007
Test name
Test status
Simulation time 2715884235 ps
CPU time 76.98 seconds
Started Aug 02 05:30:39 PM PDT 24
Finished Aug 02 05:31:56 PM PDT 24
Peak memory 217392 kb
Host smart-165e8d7e-539a-4a4d-840f-373466d6fec9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3761523959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3761523959
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.1510941797
Short name T2335
Test name
Test status
Simulation time 243006506 ps
CPU time 1.07 seconds
Started Aug 02 05:30:44 PM PDT 24
Finished Aug 02 05:30:45 PM PDT 24
Peak memory 207432 kb
Host smart-1fd65aba-ab36-41c1-9fa7-7de2541fc7b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1510941797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.1510941797
Directory /workspace/19.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.1078121069
Short name T2185
Test name
Test status
Simulation time 193375962 ps
CPU time 1 seconds
Started Aug 02 05:30:35 PM PDT 24
Finished Aug 02 05:30:36 PM PDT 24
Peak memory 207344 kb
Host smart-7a8cdf30-feab-4849-959b-ae0a08543f1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10781
21069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.1078121069
Directory /workspace/19.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_max_non_iso_usb_traffic.1297759105
Short name T2267
Test name
Test status
Simulation time 2720034201 ps
CPU time 28.29 seconds
Started Aug 02 05:30:43 PM PDT 24
Finished Aug 02 05:31:11 PM PDT 24
Peak memory 224096 kb
Host smart-b3ad68fc-7425-4d35-8b70-3d1e31e7f870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12977
59105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_non_iso_usb_traffic.1297759105
Directory /workspace/19.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3721249021
Short name T2127
Test name
Test status
Simulation time 4170060050 ps
CPU time 40.94 seconds
Started Aug 02 05:30:39 PM PDT 24
Finished Aug 02 05:31:20 PM PDT 24
Peak memory 217392 kb
Host smart-ae07ac2b-c7ec-4b80-9b10-b40bacf5cf78
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3721249021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3721249021
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.900706951
Short name T1175
Test name
Test status
Simulation time 174262025 ps
CPU time 0.84 seconds
Started Aug 02 05:30:41 PM PDT 24
Finished Aug 02 05:30:42 PM PDT 24
Peak memory 207376 kb
Host smart-8214fd2a-cf3a-4551-b459-9937dddd871b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=900706951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.900706951
Directory /workspace/19.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.2280892118
Short name T1164
Test name
Test status
Simulation time 214956256 ps
CPU time 0.86 seconds
Started Aug 02 05:30:42 PM PDT 24
Finished Aug 02 05:30:43 PM PDT 24
Peak memory 207408 kb
Host smart-b9b7d715-4e43-43be-ba3b-e3f73b241d1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22808
92118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.2280892118
Directory /workspace/19.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_nak_trans.1787537655
Short name T2715
Test name
Test status
Simulation time 179204989 ps
CPU time 0.84 seconds
Started Aug 02 05:30:48 PM PDT 24
Finished Aug 02 05:30:49 PM PDT 24
Peak memory 207316 kb
Host smart-99e444b1-14c6-45ce-825a-8ffdf1884d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17875
37655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1787537655
Directory /workspace/19.usbdev_nak_trans/latest


Test location /workspace/coverage/default/19.usbdev_out_iso.799444946
Short name T2701
Test name
Test status
Simulation time 191948609 ps
CPU time 0.93 seconds
Started Aug 02 05:30:42 PM PDT 24
Finished Aug 02 05:30:43 PM PDT 24
Peak memory 207324 kb
Host smart-bbc1d93e-af0e-40f8-8210-1c9f46324d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79944
4946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.799444946
Directory /workspace/19.usbdev_out_iso/latest


Test location /workspace/coverage/default/19.usbdev_out_stall.2698408087
Short name T785
Test name
Test status
Simulation time 168224513 ps
CPU time 0.97 seconds
Started Aug 02 05:30:41 PM PDT 24
Finished Aug 02 05:30:42 PM PDT 24
Peak memory 207404 kb
Host smart-fc1ab077-f573-4ab6-b229-e8510a5252ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26984
08087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2698408087
Directory /workspace/19.usbdev_out_stall/latest


Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2263099064
Short name T2030
Test name
Test status
Simulation time 161607397 ps
CPU time 0.83 seconds
Started Aug 02 05:30:44 PM PDT 24
Finished Aug 02 05:30:45 PM PDT 24
Peak memory 207432 kb
Host smart-16cd6b74-e585-4d1f-b0ab-71f1af158520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22630
99064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2263099064
Directory /workspace/19.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1869107903
Short name T826
Test name
Test status
Simulation time 181459025 ps
CPU time 0.86 seconds
Started Aug 02 05:30:45 PM PDT 24
Finished Aug 02 05:30:46 PM PDT 24
Peak memory 207400 kb
Host smart-273b015f-70eb-4737-8202-d57480b5a72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18691
07903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1869107903
Directory /workspace/19.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.2445773870
Short name T1628
Test name
Test status
Simulation time 234654039 ps
CPU time 1.05 seconds
Started Aug 02 05:30:43 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 207404 kb
Host smart-059ccb48-a4e3-4053-a22d-a32ea11519f4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2445773870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.2445773870
Directory /workspace/19.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.868345953
Short name T2163
Test name
Test status
Simulation time 166066587 ps
CPU time 0.83 seconds
Started Aug 02 05:30:44 PM PDT 24
Finished Aug 02 05:30:45 PM PDT 24
Peak memory 207348 kb
Host smart-efdb7fd2-5c16-4170-a895-6bd38c5df9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86834
5953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.868345953
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.861239292
Short name T37
Test name
Test status
Simulation time 45201313 ps
CPU time 0.73 seconds
Started Aug 02 05:30:44 PM PDT 24
Finished Aug 02 05:30:45 PM PDT 24
Peak memory 207400 kb
Host smart-4835224c-a298-47bc-a66d-8458e2734712
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86123
9292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.861239292
Directory /workspace/19.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/19.usbdev_pkt_buffer.4039509066
Short name T1853
Test name
Test status
Simulation time 21667901636 ps
CPU time 61.52 seconds
Started Aug 02 05:30:52 PM PDT 24
Finished Aug 02 05:31:54 PM PDT 24
Peak memory 220760 kb
Host smart-7578450d-4ff4-40bc-addc-3f1391ac4b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40395
09066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.4039509066
Directory /workspace/19.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/19.usbdev_pkt_received.3731834864
Short name T795
Test name
Test status
Simulation time 175765990 ps
CPU time 0.93 seconds
Started Aug 02 05:30:44 PM PDT 24
Finished Aug 02 05:30:45 PM PDT 24
Peak memory 207384 kb
Host smart-c288976d-ecd9-4a9f-923d-d45ab94eb39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37318
34864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3731834864
Directory /workspace/19.usbdev_pkt_received/latest


Test location /workspace/coverage/default/19.usbdev_pkt_sent.3798296320
Short name T1637
Test name
Test status
Simulation time 259029028 ps
CPU time 1 seconds
Started Aug 02 05:30:49 PM PDT 24
Finished Aug 02 05:30:50 PM PDT 24
Peak memory 207332 kb
Host smart-a0b650ce-8936-4ff7-b0b8-5e077743b671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37982
96320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.3798296320
Directory /workspace/19.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2533937271
Short name T1975
Test name
Test status
Simulation time 221183628 ps
CPU time 0.96 seconds
Started Aug 02 05:30:51 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207428 kb
Host smart-7e1ab0f9-5a47-45f7-90ae-f56f709a4f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25339
37271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2533937271
Directory /workspace/19.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.609226095
Short name T1313
Test name
Test status
Simulation time 192240897 ps
CPU time 0.91 seconds
Started Aug 02 05:30:54 PM PDT 24
Finished Aug 02 05:30:55 PM PDT 24
Peak memory 207364 kb
Host smart-6749105a-fdde-4b7f-9f0b-ab8a342dc2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60922
6095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.609226095
Directory /workspace/19.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3631045420
Short name T2391
Test name
Test status
Simulation time 163300081 ps
CPU time 0.88 seconds
Started Aug 02 05:30:44 PM PDT 24
Finished Aug 02 05:30:45 PM PDT 24
Peak memory 207400 kb
Host smart-f1c442d4-671a-40d2-a652-e8ddb6172334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36310
45420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3631045420
Directory /workspace/19.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/19.usbdev_setup_stage.1587193258
Short name T1814
Test name
Test status
Simulation time 166862219 ps
CPU time 0.84 seconds
Started Aug 02 05:30:44 PM PDT 24
Finished Aug 02 05:30:45 PM PDT 24
Peak memory 207372 kb
Host smart-f691150a-b32a-41a3-9691-649b7b7d17ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871
93258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1587193258
Directory /workspace/19.usbdev_setup_stage/latest


Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3042955800
Short name T1660
Test name
Test status
Simulation time 176743158 ps
CPU time 0.87 seconds
Started Aug 02 05:31:01 PM PDT 24
Finished Aug 02 05:31:02 PM PDT 24
Peak memory 207324 kb
Host smart-a309c7fe-2e80-49cd-97e9-00cb6d58d623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30429
55800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3042955800
Directory /workspace/19.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/19.usbdev_smoke.3193402151
Short name T956
Test name
Test status
Simulation time 250937112 ps
CPU time 1.09 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207420 kb
Host smart-528aacab-3616-4edb-bf60-ab242f21040b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31934
02151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3193402151
Directory /workspace/19.usbdev_smoke/latest


Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3492495831
Short name T2452
Test name
Test status
Simulation time 2342139698 ps
CPU time 64.59 seconds
Started Aug 02 05:30:42 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 217380 kb
Host smart-aae98fe4-1c5c-49eb-a10b-bc8d95c51186
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3492495831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3492495831
Directory /workspace/19.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.414574934
Short name T1535
Test name
Test status
Simulation time 196364446 ps
CPU time 1.03 seconds
Started Aug 02 05:30:43 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 207408 kb
Host smart-e4280565-d380-4a11-8581-ae610bc4dcfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41457
4934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.414574934
Directory /workspace/19.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/19.usbdev_stall_trans.3295711906
Short name T773
Test name
Test status
Simulation time 191341786 ps
CPU time 0.91 seconds
Started Aug 02 05:30:43 PM PDT 24
Finished Aug 02 05:30:44 PM PDT 24
Peak memory 207388 kb
Host smart-6ccb2647-b857-4bee-994b-a363a90016a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32957
11906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.3295711906
Directory /workspace/19.usbdev_stall_trans/latest


Test location /workspace/coverage/default/19.usbdev_stream_len_max.3911797023
Short name T2332
Test name
Test status
Simulation time 1310615993 ps
CPU time 3.03 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:59 PM PDT 24
Peak memory 207552 kb
Host smart-e2aed5f2-d2ee-47f8-8161-cd6bfa46bcc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39117
97023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.3911797023
Directory /workspace/19.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/19.usbdev_streaming_out.2652744396
Short name T2648
Test name
Test status
Simulation time 1328769277 ps
CPU time 13.23 seconds
Started Aug 02 05:30:47 PM PDT 24
Finished Aug 02 05:31:01 PM PDT 24
Peak memory 217024 kb
Host smart-60821c34-7f8b-4538-b1b5-36a1faaf328b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26527
44396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.2652744396
Directory /workspace/19.usbdev_streaming_out/latest


Test location /workspace/coverage/default/19.usbdev_timeout_missing_host_handshake.2309824262
Short name T1408
Test name
Test status
Simulation time 2459860625 ps
CPU time 22.16 seconds
Started Aug 02 05:30:36 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 207680 kb
Host smart-940fe88d-04b7-404c-a7fd-23acaf383454
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309824262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_timeout_missing_hos
t_handshake.2309824262
Directory /workspace/19.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/190.usbdev_endpoint_types.3194214073
Short name T417
Test name
Test status
Simulation time 312748923 ps
CPU time 1.17 seconds
Started Aug 02 05:35:09 PM PDT 24
Finished Aug 02 05:35:10 PM PDT 24
Peak memory 207336 kb
Host smart-7d32b6f0-df9f-4015-bedb-781f0e26e718
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3194214073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.usbdev_endpoint_types.3194214073
Directory /workspace/190.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/191.usbdev_endpoint_types.696793485
Short name T2156
Test name
Test status
Simulation time 244673567 ps
CPU time 0.95 seconds
Started Aug 02 05:35:11 PM PDT 24
Finished Aug 02 05:35:12 PM PDT 24
Peak memory 207436 kb
Host smart-410a7aa6-c77c-4d13-b45a-d93b49d0d715
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=696793485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.usbdev_endpoint_types.696793485
Directory /workspace/191.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/193.usbdev_endpoint_types.3612383935
Short name T477
Test name
Test status
Simulation time 172327823 ps
CPU time 0.89 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207400 kb
Host smart-fab4455e-dd8f-414f-8ef9-9450668ad166
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3612383935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.usbdev_endpoint_types.3612383935
Directory /workspace/193.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/194.usbdev_endpoint_types.3797575465
Short name T313
Test name
Test status
Simulation time 493211812 ps
CPU time 1.33 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207356 kb
Host smart-190f226e-9059-42dc-895c-20543fcee89d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3797575465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.usbdev_endpoint_types.3797575465
Directory /workspace/194.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/195.usbdev_endpoint_types.4100742352
Short name T2093
Test name
Test status
Simulation time 637055398 ps
CPU time 1.56 seconds
Started Aug 02 05:35:27 PM PDT 24
Finished Aug 02 05:35:29 PM PDT 24
Peak memory 207356 kb
Host smart-37472b70-e123-422c-82b3-7698dd177f39
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4100742352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.usbdev_endpoint_types.4100742352
Directory /workspace/195.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/196.usbdev_endpoint_types.4016139308
Short name T359
Test name
Test status
Simulation time 601139064 ps
CPU time 1.39 seconds
Started Aug 02 05:35:14 PM PDT 24
Finished Aug 02 05:35:16 PM PDT 24
Peak memory 207332 kb
Host smart-36b9e703-c746-4be1-8977-1b560d9f3904
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4016139308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.usbdev_endpoint_types.4016139308
Directory /workspace/196.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/198.usbdev_endpoint_types.910711496
Short name T2468
Test name
Test status
Simulation time 538376875 ps
CPU time 1.5 seconds
Started Aug 02 05:35:22 PM PDT 24
Finished Aug 02 05:35:24 PM PDT 24
Peak memory 207308 kb
Host smart-557ad14c-9365-427d-a11e-167c35dbf493
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=910711496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.usbdev_endpoint_types.910711496
Directory /workspace/198.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/199.usbdev_endpoint_types.639940025
Short name T408
Test name
Test status
Simulation time 246141176 ps
CPU time 0.99 seconds
Started Aug 02 05:35:27 PM PDT 24
Finished Aug 02 05:35:28 PM PDT 24
Peak memory 207392 kb
Host smart-99cd938c-21c6-41bf-b3af-59acc34a22d4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=639940025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.usbdev_endpoint_types.639940025
Directory /workspace/199.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/2.usbdev_alert_test.791980074
Short name T1340
Test name
Test status
Simulation time 39129637 ps
CPU time 0.69 seconds
Started Aug 02 05:27:18 PM PDT 24
Finished Aug 02 05:27:19 PM PDT 24
Peak memory 207492 kb
Host smart-959fe620-c00d-4c49-a2dc-41ddc195c0f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=791980074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.791980074
Directory /workspace/2.usbdev_alert_test/latest


Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2797920431
Short name T898
Test name
Test status
Simulation time 11112386642 ps
CPU time 12.58 seconds
Started Aug 02 05:26:58 PM PDT 24
Finished Aug 02 05:27:11 PM PDT 24
Peak memory 207644 kb
Host smart-409bbebf-15dc-4590-9666-f03eeddab736
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797920431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_disconnect.2797920431
Directory /workspace/2.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.585647228
Short name T915
Test name
Test status
Simulation time 20468956713 ps
CPU time 22.74 seconds
Started Aug 02 05:26:56 PM PDT 24
Finished Aug 02 05:27:19 PM PDT 24
Peak memory 207624 kb
Host smart-422805c5-5e5a-4ae2-abdc-0eabcc8d1a5e
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=585647228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.585647228
Directory /workspace/2.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1609731897
Short name T2618
Test name
Test status
Simulation time 29321005953 ps
CPU time 42.68 seconds
Started Aug 02 05:27:06 PM PDT 24
Finished Aug 02 05:27:49 PM PDT 24
Peak memory 207592 kb
Host smart-16ca892e-d165-4565-8d98-5758b06a7a09
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609731897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_ao
n_wake_resume.1609731897
Directory /workspace/2.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/2.usbdev_av_buffer.2679246701
Short name T2484
Test name
Test status
Simulation time 149129992 ps
CPU time 0.85 seconds
Started Aug 02 05:26:57 PM PDT 24
Finished Aug 02 05:26:58 PM PDT 24
Peak memory 206824 kb
Host smart-4651dd4b-25ec-409d-aed2-44876001fd7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26792
46701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2679246701
Directory /workspace/2.usbdev_av_buffer/latest


Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.69344033
Short name T1867
Test name
Test status
Simulation time 547970721 ps
CPU time 1.77 seconds
Started Aug 02 05:26:58 PM PDT 24
Finished Aug 02 05:27:00 PM PDT 24
Peak memory 207348 kb
Host smart-12156a4f-0fa7-4948-9e62-cc09b7b6988a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69344
033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.69344033
Directory /workspace/2.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3921074574
Short name T869
Test name
Test status
Simulation time 968271929 ps
CPU time 2.68 seconds
Started Aug 02 05:27:08 PM PDT 24
Finished Aug 02 05:27:11 PM PDT 24
Peak memory 207612 kb
Host smart-d331de05-a8a8-4a1d-89c1-28233db683b3
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3921074574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3921074574
Directory /workspace/2.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/2.usbdev_device_address.6714385
Short name T3075
Test name
Test status
Simulation time 43756144191 ps
CPU time 60.54 seconds
Started Aug 02 05:27:06 PM PDT 24
Finished Aug 02 05:28:07 PM PDT 24
Peak memory 207644 kb
Host smart-fdf0b9cc-e9bd-40a0-819d-fb7e232cfcd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67143
85 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.6714385
Directory /workspace/2.usbdev_device_address/latest


Test location /workspace/coverage/default/2.usbdev_device_timeout.3417020300
Short name T2427
Test name
Test status
Simulation time 6200756983 ps
CPU time 38.91 seconds
Started Aug 02 05:27:00 PM PDT 24
Finished Aug 02 05:27:39 PM PDT 24
Peak memory 207496 kb
Host smart-f2a9653c-1b8b-49bd-b642-d0d81b83f9d7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417020300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_timeout.3417020300
Directory /workspace/2.usbdev_device_timeout/latest


Test location /workspace/coverage/default/2.usbdev_disable_endpoint.331069035
Short name T1329
Test name
Test status
Simulation time 797857210 ps
CPU time 1.83 seconds
Started Aug 02 05:26:58 PM PDT 24
Finished Aug 02 05:27:00 PM PDT 24
Peak memory 207332 kb
Host smart-3376428d-ea29-4148-a0fe-fe883c38a337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33106
9035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.331069035
Directory /workspace/2.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/2.usbdev_disconnected.1668401487
Short name T2161
Test name
Test status
Simulation time 147751678 ps
CPU time 0.82 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:07 PM PDT 24
Peak memory 207372 kb
Host smart-abb415d0-2453-4a5a-a0e1-23190e86c04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16684
01487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.1668401487
Directory /workspace/2.usbdev_disconnected/latest


Test location /workspace/coverage/default/2.usbdev_enable.3983698083
Short name T2230
Test name
Test status
Simulation time 47070745 ps
CPU time 0.67 seconds
Started Aug 02 05:26:59 PM PDT 24
Finished Aug 02 05:27:00 PM PDT 24
Peak memory 207368 kb
Host smart-e00e7197-cd0b-4009-adb8-49ab59eb1076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39836
98083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3983698083
Directory /workspace/2.usbdev_enable/latest


Test location /workspace/coverage/default/2.usbdev_endpoint_access.1759297317
Short name T2046
Test name
Test status
Simulation time 834995284 ps
CPU time 2.54 seconds
Started Aug 02 05:26:55 PM PDT 24
Finished Aug 02 05:26:58 PM PDT 24
Peak memory 207568 kb
Host smart-50694c64-692d-4961-9807-268004831942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17592
97317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1759297317
Directory /workspace/2.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/2.usbdev_endpoint_types.4185705628
Short name T2830
Test name
Test status
Simulation time 357348590 ps
CPU time 1.06 seconds
Started Aug 02 05:26:58 PM PDT 24
Finished Aug 02 05:26:59 PM PDT 24
Peak memory 207348 kb
Host smart-8e0878b8-31df-49b3-9e20-36cd9f1ed09b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4185705628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_types.4185705628
Directory /workspace/2.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/2.usbdev_fifo_rst.1436220068
Short name T2940
Test name
Test status
Simulation time 368248297 ps
CPU time 2.46 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:10 PM PDT 24
Peak memory 207476 kb
Host smart-f1515bc5-2b65-4716-b324-efa48fd28b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14362
20068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1436220068
Directory /workspace/2.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3566440695
Short name T1087
Test name
Test status
Simulation time 113208451796 ps
CPU time 178.45 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:30:05 PM PDT 24
Peak memory 207624 kb
Host smart-ba3235e1-af36-4d65-b5cd-6c5a79730165
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3566440695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3566440695
Directory /workspace/2.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1714307851
Short name T1005
Test name
Test status
Simulation time 84058659515 ps
CPU time 131.47 seconds
Started Aug 02 05:27:09 PM PDT 24
Finished Aug 02 05:29:20 PM PDT 24
Peak memory 207736 kb
Host smart-a51a8241-7732-4860-82f4-8d529dea9fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714307851 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1714307851
Directory /workspace/2.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/2.usbdev_freq_loclk.908614791
Short name T2525
Test name
Test status
Simulation time 87129180685 ps
CPU time 132.27 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:29:19 PM PDT 24
Peak memory 207700 kb
Host smart-e9235f0b-d0a2-471f-aec2-82d59d873391
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=908614791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.908614791
Directory /workspace/2.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1401576900
Short name T1518
Test name
Test status
Simulation time 114142189120 ps
CPU time 172.71 seconds
Started Aug 02 05:27:09 PM PDT 24
Finished Aug 02 05:30:02 PM PDT 24
Peak memory 207688 kb
Host smart-d7412db0-bf19-4719-9bf4-3c6d9fc93084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401576900 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1401576900
Directory /workspace/2.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/2.usbdev_freq_phase.3142604225
Short name T3071
Test name
Test status
Simulation time 104190560620 ps
CPU time 160.71 seconds
Started Aug 02 05:27:12 PM PDT 24
Finished Aug 02 05:29:53 PM PDT 24
Peak memory 207744 kb
Host smart-8f19f250-f94b-4f93-b8fc-d3772387673e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31426
04225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3142604225
Directory /workspace/2.usbdev_freq_phase/latest


Test location /workspace/coverage/default/2.usbdev_in_iso.2945391409
Short name T1273
Test name
Test status
Simulation time 166458014 ps
CPU time 0.87 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:08 PM PDT 24
Peak memory 207380 kb
Host smart-7faa411c-3f96-45f4-ad28-bb00eb796b5d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2945391409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.2945391409
Directory /workspace/2.usbdev_in_iso/latest


Test location /workspace/coverage/default/2.usbdev_in_stall.3093494493
Short name T2200
Test name
Test status
Simulation time 141820470 ps
CPU time 0.78 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:08 PM PDT 24
Peak memory 207432 kb
Host smart-c0d7f1dd-0792-4d76-bc1e-354ec77839e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30934
94493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3093494493
Directory /workspace/2.usbdev_in_stall/latest


Test location /workspace/coverage/default/2.usbdev_in_trans.3448204798
Short name T2986
Test name
Test status
Simulation time 210284221 ps
CPU time 0.93 seconds
Started Aug 02 05:27:09 PM PDT 24
Finished Aug 02 05:27:10 PM PDT 24
Peak memory 207408 kb
Host smart-210894d5-855a-4beb-9d5c-e2c1104969b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34482
04798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3448204798
Directory /workspace/2.usbdev_in_trans/latest


Test location /workspace/coverage/default/2.usbdev_invalid_sync.2525927811
Short name T1761
Test name
Test status
Simulation time 3994506101 ps
CPU time 30.26 seconds
Started Aug 02 05:27:09 PM PDT 24
Finished Aug 02 05:27:39 PM PDT 24
Peak memory 217188 kb
Host smart-a4aa5911-712c-4f46-8bc5-5ed97478cf49
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2525927811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.2525927811
Directory /workspace/2.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/2.usbdev_iso_retraction.2110507090
Short name T670
Test name
Test status
Simulation time 9817229534 ps
CPU time 117.34 seconds
Started Aug 02 05:27:08 PM PDT 24
Finished Aug 02 05:29:05 PM PDT 24
Peak memory 207652 kb
Host smart-8d4967aa-fca7-498d-9f5b-d18b7c3b2775
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2110507090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.2110507090
Directory /workspace/2.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/2.usbdev_link_in_err.939106630
Short name T723
Test name
Test status
Simulation time 197071060 ps
CPU time 0.97 seconds
Started Aug 02 05:27:12 PM PDT 24
Finished Aug 02 05:27:13 PM PDT 24
Peak memory 207400 kb
Host smart-1cd72d05-ce59-42f0-9123-0c80f05e569f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93910
6630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.939106630
Directory /workspace/2.usbdev_link_in_err/latest


Test location /workspace/coverage/default/2.usbdev_link_resume.3844308839
Short name T1515
Test name
Test status
Simulation time 34354518609 ps
CPU time 46.83 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:54 PM PDT 24
Peak memory 207700 kb
Host smart-e9d1ea83-9b2b-4ed5-976c-07a052cedd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38443
08839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.3844308839
Directory /workspace/2.usbdev_link_resume/latest


Test location /workspace/coverage/default/2.usbdev_link_suspend.2241564694
Short name T1181
Test name
Test status
Simulation time 3794992964 ps
CPU time 5.49 seconds
Started Aug 02 05:27:09 PM PDT 24
Finished Aug 02 05:27:15 PM PDT 24
Peak memory 215776 kb
Host smart-966b649c-73f0-4b11-9492-10d3e608f15d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22415
64694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.2241564694
Directory /workspace/2.usbdev_link_suspend/latest


Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.285817835
Short name T925
Test name
Test status
Simulation time 4198074497 ps
CPU time 31.14 seconds
Started Aug 02 05:27:05 PM PDT 24
Finished Aug 02 05:27:37 PM PDT 24
Peak memory 224096 kb
Host smart-8420ab4a-374e-4413-bc43-a6ef050cf82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28581
7835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.285817835
Directory /workspace/2.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.1147714328
Short name T1897
Test name
Test status
Simulation time 2451854992 ps
CPU time 18.94 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:26 PM PDT 24
Peak memory 217660 kb
Host smart-7bd28a30-a442-4956-bc69-41efc7976b99
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1147714328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.1147714328
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.2543121623
Short name T2582
Test name
Test status
Simulation time 243193094 ps
CPU time 1.08 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:09 PM PDT 24
Peak memory 207408 kb
Host smart-0d35c0be-2055-480d-8300-0758ef5b16f9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2543121623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.2543121623
Directory /workspace/2.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.867553395
Short name T2414
Test name
Test status
Simulation time 195095930 ps
CPU time 0.94 seconds
Started Aug 02 05:27:08 PM PDT 24
Finished Aug 02 05:27:09 PM PDT 24
Peak memory 207400 kb
Host smart-0ffda0a7-2bc9-4a86-846b-58705e44b741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86755
3395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.867553395
Directory /workspace/2.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_max_non_iso_usb_traffic.792492273
Short name T1338
Test name
Test status
Simulation time 1831080737 ps
CPU time 45.73 seconds
Started Aug 02 05:27:08 PM PDT 24
Finished Aug 02 05:27:54 PM PDT 24
Peak memory 223900 kb
Host smart-d6404bf9-a48b-498b-a7a5-48017e7a79c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79249
2273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_non_iso_usb_traffic.792492273
Directory /workspace/2.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1497860024
Short name T3038
Test name
Test status
Simulation time 3497574732 ps
CPU time 29.23 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:37 PM PDT 24
Peak memory 223820 kb
Host smart-e838dfd7-a596-4d2e-b3b7-4c63dfda1880
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1497860024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1497860024
Directory /workspace/2.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.1574485561
Short name T3082
Test name
Test status
Simulation time 3233934788 ps
CPU time 32.07 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:39 PM PDT 24
Peak memory 217472 kb
Host smart-285749ec-ce8b-4dbd-97a6-a39a1cf870ee
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1574485561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.1574485561
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.823139934
Short name T2608
Test name
Test status
Simulation time 157908384 ps
CPU time 0.85 seconds
Started Aug 02 05:27:08 PM PDT 24
Finished Aug 02 05:27:09 PM PDT 24
Peak memory 207392 kb
Host smart-07247722-ee6d-4ebf-9e6c-dc036d910982
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=823139934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.823139934
Directory /workspace/2.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.721002980
Short name T1431
Test name
Test status
Simulation time 164831688 ps
CPU time 0.81 seconds
Started Aug 02 05:27:07 PM PDT 24
Finished Aug 02 05:27:08 PM PDT 24
Peak memory 207356 kb
Host smart-fed6e620-81a1-49e0-8f7e-d1dcda47b5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72100
2980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.721002980
Directory /workspace/2.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_nak_trans.277287552
Short name T2190
Test name
Test status
Simulation time 237099538 ps
CPU time 0.94 seconds
Started Aug 02 05:27:16 PM PDT 24
Finished Aug 02 05:27:17 PM PDT 24
Peak memory 207404 kb
Host smart-0e7627a1-e843-413b-894e-c620365408a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27728
7552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.277287552
Directory /workspace/2.usbdev_nak_trans/latest


Test location /workspace/coverage/default/2.usbdev_out_iso.1514440843
Short name T2106
Test name
Test status
Simulation time 177088552 ps
CPU time 0.94 seconds
Started Aug 02 05:27:11 PM PDT 24
Finished Aug 02 05:27:12 PM PDT 24
Peak memory 206824 kb
Host smart-d57dc1b7-dd79-46e7-8e6f-e2e79af6133a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15144
40843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.1514440843
Directory /workspace/2.usbdev_out_iso/latest


Test location /workspace/coverage/default/2.usbdev_out_stall.4262231533
Short name T1827
Test name
Test status
Simulation time 161676244 ps
CPU time 0.81 seconds
Started Aug 02 05:27:16 PM PDT 24
Finished Aug 02 05:27:17 PM PDT 24
Peak memory 207188 kb
Host smart-0c64c4cb-3258-4266-8983-594acb715df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42622
31533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.4262231533
Directory /workspace/2.usbdev_out_stall/latest


Test location /workspace/coverage/default/2.usbdev_out_trans_nak.2049146918
Short name T1654
Test name
Test status
Simulation time 157940758 ps
CPU time 0.87 seconds
Started Aug 02 05:27:12 PM PDT 24
Finished Aug 02 05:27:13 PM PDT 24
Peak memory 207348 kb
Host smart-bee5fb47-4b81-4036-a55b-1c9f6311b7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20491
46918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.2049146918
Directory /workspace/2.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/2.usbdev_pending_in_trans.906585499
Short name T187
Test name
Test status
Simulation time 153374791 ps
CPU time 0.84 seconds
Started Aug 02 05:27:10 PM PDT 24
Finished Aug 02 05:27:11 PM PDT 24
Peak memory 207388 kb
Host smart-ffbf8ba2-e277-42e6-944e-f818b1b9787d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90658
5499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.906585499
Directory /workspace/2.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1354373223
Short name T1238
Test name
Test status
Simulation time 208926886 ps
CPU time 0.93 seconds
Started Aug 02 05:27:16 PM PDT 24
Finished Aug 02 05:27:17 PM PDT 24
Peak memory 207204 kb
Host smart-1593fc4e-3c42-42f3-957e-7d029ce3dc11
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1354373223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1354373223
Directory /workspace/2.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.250306886
Short name T3056
Test name
Test status
Simulation time 232880141 ps
CPU time 1 seconds
Started Aug 02 05:27:12 PM PDT 24
Finished Aug 02 05:27:13 PM PDT 24
Peak memory 207408 kb
Host smart-a69e3124-38cc-4417-9784-d842cce474a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25030
6886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.250306886
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2913958734
Short name T1294
Test name
Test status
Simulation time 157075367 ps
CPU time 0.78 seconds
Started Aug 02 05:27:12 PM PDT 24
Finished Aug 02 05:27:12 PM PDT 24
Peak memory 207364 kb
Host smart-ba044f1f-c21e-45b7-899a-bbefc6c1452e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29139
58734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2913958734
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.2761231
Short name T2117
Test name
Test status
Simulation time 42903384 ps
CPU time 0.68 seconds
Started Aug 02 05:27:12 PM PDT 24
Finished Aug 02 05:27:13 PM PDT 24
Peak memory 207352 kb
Host smart-ed6e28b4-8946-433c-98b4-9462efd82c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27612
31 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.2761231
Directory /workspace/2.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/2.usbdev_pkt_received.2514289101
Short name T2695
Test name
Test status
Simulation time 151206651 ps
CPU time 0.81 seconds
Started Aug 02 05:27:16 PM PDT 24
Finished Aug 02 05:27:17 PM PDT 24
Peak memory 207204 kb
Host smart-d2471263-ba58-4366-99a7-eebf77567c48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25142
89101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.2514289101
Directory /workspace/2.usbdev_pkt_received/latest


Test location /workspace/coverage/default/2.usbdev_pkt_sent.250954184
Short name T1708
Test name
Test status
Simulation time 223320823 ps
CPU time 0.89 seconds
Started Aug 02 05:27:11 PM PDT 24
Finished Aug 02 05:27:12 PM PDT 24
Peak memory 207404 kb
Host smart-7f4ef8cd-dce2-4ebf-b383-936980c7ec41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25095
4184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.250954184
Directory /workspace/2.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.2413770938
Short name T1661
Test name
Test status
Simulation time 2540641300 ps
CPU time 61.44 seconds
Started Aug 02 05:27:18 PM PDT 24
Finished Aug 02 05:28:20 PM PDT 24
Peak memory 217712 kb
Host smart-db386a92-bfae-45b5-b4f1-b024e09f4fab
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413770938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2413770938
Directory /workspace/2.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2912514438
Short name T178
Test name
Test status
Simulation time 7459805698 ps
CPU time 33.19 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 224096 kb
Host smart-fb54cd87-f5a0-4bab-b764-72e12539d478
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2912514438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2912514438
Directory /workspace/2.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/2.usbdev_rand_suspends.4013777329
Short name T1021
Test name
Test status
Simulation time 5074463207 ps
CPU time 18.71 seconds
Started Aug 02 05:27:18 PM PDT 24
Finished Aug 02 05:27:37 PM PDT 24
Peak memory 219120 kb
Host smart-28071a11-6e94-4e84-a8b6-bee1a4ce8bd7
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013777329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.4013777329
Directory /workspace/2.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.78121240
Short name T1658
Test name
Test status
Simulation time 198394871 ps
CPU time 0.89 seconds
Started Aug 02 05:27:11 PM PDT 24
Finished Aug 02 05:27:12 PM PDT 24
Peak memory 207436 kb
Host smart-f1bc1745-d758-4fc9-941e-3e1cd3ab3f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78121
240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.78121240
Directory /workspace/2.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2046317634
Short name T664
Test name
Test status
Simulation time 156518417 ps
CPU time 0.84 seconds
Started Aug 02 05:27:12 PM PDT 24
Finished Aug 02 05:27:13 PM PDT 24
Peak memory 207400 kb
Host smart-836a9145-8429-4473-9c05-7b3108322cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20463
17634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2046317634
Directory /workspace/2.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3465157140
Short name T3062
Test name
Test status
Simulation time 141796180 ps
CPU time 0.83 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:20 PM PDT 24
Peak memory 207364 kb
Host smart-3909707d-5fe7-4b55-b9f1-1a84a9c9a777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34651
57140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3465157140
Directory /workspace/2.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/2.usbdev_rx_full.721982643
Short name T1067
Test name
Test status
Simulation time 303421304 ps
CPU time 1.2 seconds
Started Aug 02 05:27:18 PM PDT 24
Finished Aug 02 05:27:20 PM PDT 24
Peak memory 207420 kb
Host smart-4fed5f7f-1ced-4691-a118-c727644ab595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72198
2643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_full.721982643
Directory /workspace/2.usbdev_rx_full/latest


Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2049907697
Short name T76
Test name
Test status
Simulation time 148322439 ps
CPU time 0.82 seconds
Started Aug 02 05:27:22 PM PDT 24
Finished Aug 02 05:27:22 PM PDT 24
Peak memory 207352 kb
Host smart-dc7acc3e-a79e-43f1-8ba2-a42f791c36e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20499
07697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2049907697
Directory /workspace/2.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/2.usbdev_sec_cm.3187634045
Short name T220
Test name
Test status
Simulation time 427913787 ps
CPU time 1.37 seconds
Started Aug 02 05:27:24 PM PDT 24
Finished Aug 02 05:27:26 PM PDT 24
Peak memory 224324 kb
Host smart-e5449685-b8d4-4149-a865-8d97827721ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3187634045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3187634045
Directory /workspace/2.usbdev_sec_cm/latest


Test location /workspace/coverage/default/2.usbdev_setup_priority.3064694653
Short name T52
Test name
Test status
Simulation time 366330901 ps
CPU time 1.33 seconds
Started Aug 02 05:27:18 PM PDT 24
Finished Aug 02 05:27:19 PM PDT 24
Peak memory 207444 kb
Host smart-51aad804-75e6-49ce-9cc0-b32a1b14d014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30646
94653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.3064694653
Directory /workspace/2.usbdev_setup_priority/latest


Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.499238358
Short name T2251
Test name
Test status
Simulation time 241592073 ps
CPU time 0.96 seconds
Started Aug 02 05:27:17 PM PDT 24
Finished Aug 02 05:27:18 PM PDT 24
Peak memory 207348 kb
Host smart-2b5b25c5-0630-4bb5-b364-1d3ac44064e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49923
8358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.499238358
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/2.usbdev_setup_stage.3722455927
Short name T3089
Test name
Test status
Simulation time 161991945 ps
CPU time 0.9 seconds
Started Aug 02 05:27:25 PM PDT 24
Finished Aug 02 05:27:26 PM PDT 24
Peak memory 207284 kb
Host smart-d53a71ad-5a89-4afa-85d5-2697bdad2852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37224
55927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3722455927
Directory /workspace/2.usbdev_setup_stage/latest


Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3369374996
Short name T2276
Test name
Test status
Simulation time 155808450 ps
CPU time 0.84 seconds
Started Aug 02 05:27:17 PM PDT 24
Finished Aug 02 05:27:19 PM PDT 24
Peak memory 207376 kb
Host smart-27c9a3b9-8eb9-4677-87d8-7b1d059f910a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33693
74996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3369374996
Directory /workspace/2.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/2.usbdev_smoke.4269546152
Short name T1539
Test name
Test status
Simulation time 224396469 ps
CPU time 1.04 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:20 PM PDT 24
Peak memory 207412 kb
Host smart-8ea1bf8d-d783-4acb-9a90-edb2b647d3e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42695
46152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4269546152
Directory /workspace/2.usbdev_smoke/latest


Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.599172423
Short name T3048
Test name
Test status
Simulation time 2213043594 ps
CPU time 21.34 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:40 PM PDT 24
Peak memory 223988 kb
Host smart-23243a7c-cb64-48ca-ac5a-668d870ee2b5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=599172423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.599172423
Directory /workspace/2.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.3210029378
Short name T2307
Test name
Test status
Simulation time 169713734 ps
CPU time 0.88 seconds
Started Aug 02 05:27:26 PM PDT 24
Finished Aug 02 05:27:27 PM PDT 24
Peak memory 207324 kb
Host smart-c7215eea-ffb2-47b3-997a-6c154557740e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100
29378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.3210029378
Directory /workspace/2.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/2.usbdev_stall_trans.1157094287
Short name T685
Test name
Test status
Simulation time 142227665 ps
CPU time 0.83 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:20 PM PDT 24
Peak memory 207324 kb
Host smart-5484e54d-b46a-4461-90f5-d74a87b8eaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11570
94287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.1157094287
Directory /workspace/2.usbdev_stall_trans/latest


Test location /workspace/coverage/default/2.usbdev_stream_len_max.406815850
Short name T1242
Test name
Test status
Simulation time 750110039 ps
CPU time 1.91 seconds
Started Aug 02 05:27:18 PM PDT 24
Finished Aug 02 05:27:20 PM PDT 24
Peak memory 207372 kb
Host smart-28828526-d9c9-4603-b887-a75a5b6b70e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40681
5850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.406815850
Directory /workspace/2.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/2.usbdev_streaming_out.2975201171
Short name T2413
Test name
Test status
Simulation time 3117094905 ps
CPU time 23.06 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:42 PM PDT 24
Peak memory 215864 kb
Host smart-31dd4ebc-7628-4185-a96d-8a00f97a1ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29752
01171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2975201171
Directory /workspace/2.usbdev_streaming_out/latest


Test location /workspace/coverage/default/2.usbdev_timeout_missing_host_handshake.629179677
Short name T598
Test name
Test status
Simulation time 607233685 ps
CPU time 11.29 seconds
Started Aug 02 05:26:59 PM PDT 24
Finished Aug 02 05:27:10 PM PDT 24
Peak memory 207452 kb
Host smart-4919d901-15f2-43d3-9cd0-404ea3991453
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629179677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_timeout_missing_host_
handshake.629179677
Directory /workspace/2.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/20.usbdev_alert_test.449109430
Short name T844
Test name
Test status
Simulation time 39482936 ps
CPU time 0.66 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:56 PM PDT 24
Peak memory 207436 kb
Host smart-a68bde57-c591-484b-a8cc-9468e7e23731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=449109430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.449109430
Directory /workspace/20.usbdev_alert_test/latest


Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.1222286272
Short name T1339
Test name
Test status
Simulation time 4253363150 ps
CPU time 6.14 seconds
Started Aug 02 05:30:43 PM PDT 24
Finished Aug 02 05:30:50 PM PDT 24
Peak memory 215816 kb
Host smart-c7899700-b1dc-4f56-b941-1d406d86a6cb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222286272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_disconnect.1222286272
Directory /workspace/20.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2942539663
Short name T12
Test name
Test status
Simulation time 14083622347 ps
CPU time 16.88 seconds
Started Aug 02 05:30:48 PM PDT 24
Finished Aug 02 05:31:05 PM PDT 24
Peak memory 215856 kb
Host smart-adb6840f-3629-40ec-9bfd-1d9c15053614
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942539663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2942539663
Directory /workspace/20.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.2750403545
Short name T1104
Test name
Test status
Simulation time 30958316883 ps
CPU time 36.85 seconds
Started Aug 02 05:30:42 PM PDT 24
Finished Aug 02 05:31:19 PM PDT 24
Peak memory 207660 kb
Host smart-baef8f51-c5aa-488f-a950-b94d414ead64
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750403545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_a
on_wake_resume.2750403545
Directory /workspace/20.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/20.usbdev_av_buffer.2894443913
Short name T1847
Test name
Test status
Simulation time 154534398 ps
CPU time 0.83 seconds
Started Aug 02 05:30:48 PM PDT 24
Finished Aug 02 05:30:49 PM PDT 24
Peak memory 207396 kb
Host smart-190f82c7-5759-41ef-b163-699fcba62f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28944
43913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2894443913
Directory /workspace/20.usbdev_av_buffer/latest


Test location /workspace/coverage/default/20.usbdev_bitstuff_err.2965274437
Short name T81
Test name
Test status
Simulation time 139415645 ps
CPU time 0.79 seconds
Started Aug 02 05:30:48 PM PDT 24
Finished Aug 02 05:30:49 PM PDT 24
Peak memory 207364 kb
Host smart-725f1538-5027-443e-87ea-f6459253e19a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29652
74437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.2965274437
Directory /workspace/20.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.584115693
Short name T2936
Test name
Test status
Simulation time 319632199 ps
CPU time 1.32 seconds
Started Aug 02 05:30:42 PM PDT 24
Finished Aug 02 05:30:43 PM PDT 24
Peak memory 207308 kb
Host smart-86d4cbcd-2bb7-4640-9297-0178ec6f8d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58411
5693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.584115693
Directory /workspace/20.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1774153064
Short name T1155
Test name
Test status
Simulation time 368957210 ps
CPU time 1.28 seconds
Started Aug 02 05:30:45 PM PDT 24
Finished Aug 02 05:30:46 PM PDT 24
Peak memory 207332 kb
Host smart-69d6f296-1809-4e6c-b6e4-4dc6d7a0b934
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1774153064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1774153064
Directory /workspace/20.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/20.usbdev_device_address.2361266127
Short name T2978
Test name
Test status
Simulation time 32595180497 ps
CPU time 55.86 seconds
Started Aug 02 05:30:45 PM PDT 24
Finished Aug 02 05:31:41 PM PDT 24
Peak memory 207696 kb
Host smart-2475997e-0932-4b4a-9536-7890d5a462e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23612
66127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2361266127
Directory /workspace/20.usbdev_device_address/latest


Test location /workspace/coverage/default/20.usbdev_device_timeout.1763719385
Short name T973
Test name
Test status
Simulation time 2441638503 ps
CPU time 21.08 seconds
Started Aug 02 05:30:43 PM PDT 24
Finished Aug 02 05:31:04 PM PDT 24
Peak memory 207680 kb
Host smart-75a6bd1e-c36d-4387-a147-cb3df3b764b5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763719385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_timeout.1763719385
Directory /workspace/20.usbdev_device_timeout/latest


Test location /workspace/coverage/default/20.usbdev_disable_endpoint.1625209281
Short name T1881
Test name
Test status
Simulation time 925107327 ps
CPU time 2.03 seconds
Started Aug 02 05:30:45 PM PDT 24
Finished Aug 02 05:30:47 PM PDT 24
Peak memory 207360 kb
Host smart-75033797-477f-4748-9845-d6c75221fcb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
09281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.1625209281
Directory /workspace/20.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/20.usbdev_disconnected.2906222915
Short name T2611
Test name
Test status
Simulation time 133131424 ps
CPU time 0.81 seconds
Started Aug 02 05:30:57 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 207292 kb
Host smart-b58a85ea-33bc-47dd-a7d6-068733ef5ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29062
22915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2906222915
Directory /workspace/20.usbdev_disconnected/latest


Test location /workspace/coverage/default/20.usbdev_enable.3570605511
Short name T2259
Test name
Test status
Simulation time 34325512 ps
CPU time 0.74 seconds
Started Aug 02 05:30:56 PM PDT 24
Finished Aug 02 05:30:57 PM PDT 24
Peak memory 207380 kb
Host smart-fcdca309-3d51-4d25-9978-d16da895ca9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35706
05511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3570605511
Directory /workspace/20.usbdev_enable/latest


Test location /workspace/coverage/default/20.usbdev_endpoint_access.49061334
Short name T1938
Test name
Test status
Simulation time 959544800 ps
CPU time 2.51 seconds
Started Aug 02 05:30:52 PM PDT 24
Finished Aug 02 05:31:00 PM PDT 24
Peak memory 207580 kb
Host smart-911b0fc7-3167-4d5e-8b8c-8226bf03dd3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49061
334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.49061334
Directory /workspace/20.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/20.usbdev_fifo_rst.2818153615
Short name T105
Test name
Test status
Simulation time 181003895 ps
CPU time 1.86 seconds
Started Aug 02 05:30:52 PM PDT 24
Finished Aug 02 05:30:54 PM PDT 24
Peak memory 207560 kb
Host smart-a8b2a792-4a07-4e2e-8b3d-8564b605c9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28181
53615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2818153615
Directory /workspace/20.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/20.usbdev_in_iso.3600146969
Short name T96
Test name
Test status
Simulation time 154330928 ps
CPU time 0.88 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:56 PM PDT 24
Peak memory 207340 kb
Host smart-b91e364f-b23f-4e18-879f-edaca456b96d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3600146969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.3600146969
Directory /workspace/20.usbdev_in_iso/latest


Test location /workspace/coverage/default/20.usbdev_in_stall.76471810
Short name T1109
Test name
Test status
Simulation time 137113387 ps
CPU time 0.79 seconds
Started Aug 02 05:30:52 PM PDT 24
Finished Aug 02 05:30:53 PM PDT 24
Peak memory 207408 kb
Host smart-60de2d0a-11c8-4a52-b4d5-a64b991e7e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76471
810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.76471810
Directory /workspace/20.usbdev_in_stall/latest


Test location /workspace/coverage/default/20.usbdev_in_trans.2337514552
Short name T2587
Test name
Test status
Simulation time 156286956 ps
CPU time 0.87 seconds
Started Aug 02 05:30:51 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207384 kb
Host smart-a422761c-1e32-4818-99ef-46600aa97378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23375
14552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.2337514552
Directory /workspace/20.usbdev_in_trans/latest


Test location /workspace/coverage/default/20.usbdev_invalid_sync.2056546509
Short name T624
Test name
Test status
Simulation time 3795382641 ps
CPU time 109.02 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:32:39 PM PDT 24
Peak memory 223984 kb
Host smart-18f371f5-ecc0-4681-848d-cbf70090ad78
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2056546509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_invalid_sync.2056546509
Directory /workspace/20.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/20.usbdev_iso_retraction.4237122728
Short name T1774
Test name
Test status
Simulation time 13888080983 ps
CPU time 89.41 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:32:19 PM PDT 24
Peak memory 207648 kb
Host smart-decffbd0-817a-4819-a572-f6cfdc2a9e12
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4237122728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.4237122728
Directory /workspace/20.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/20.usbdev_link_in_err.3640145838
Short name T2143
Test name
Test status
Simulation time 257899327 ps
CPU time 1 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:51 PM PDT 24
Peak memory 207376 kb
Host smart-01d89fd4-177f-4798-8e53-72e452538e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36401
45838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3640145838
Directory /workspace/20.usbdev_link_in_err/latest


Test location /workspace/coverage/default/20.usbdev_link_resume.2570684144
Short name T2112
Test name
Test status
Simulation time 9191070481 ps
CPU time 13.64 seconds
Started Aug 02 05:31:08 PM PDT 24
Finished Aug 02 05:31:21 PM PDT 24
Peak memory 215988 kb
Host smart-c0117401-96a3-4c53-96f5-00e10c187806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25706
84144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.2570684144
Directory /workspace/20.usbdev_link_resume/latest


Test location /workspace/coverage/default/20.usbdev_link_suspend.1815293420
Short name T2547
Test name
Test status
Simulation time 8718851834 ps
CPU time 13 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:31:04 PM PDT 24
Peak memory 207644 kb
Host smart-cd735b48-2303-4537-8eff-bf6e4739e1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18152
93420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1815293420
Directory /workspace/20.usbdev_link_suspend/latest


Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.1508421689
Short name T622
Test name
Test status
Simulation time 4004766921 ps
CPU time 29.24 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:31:19 PM PDT 24
Peak memory 224096 kb
Host smart-239e774e-32ae-4637-b63f-e54c729a399d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15084
21689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.1508421689
Directory /workspace/20.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.1085172586
Short name T1397
Test name
Test status
Simulation time 2156072729 ps
CPU time 21.06 seconds
Started Aug 02 05:31:01 PM PDT 24
Finished Aug 02 05:31:22 PM PDT 24
Peak memory 215832 kb
Host smart-df0185dc-6971-4cd9-afc2-68be3dbf898b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1085172586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.1085172586
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.42632617
Short name T1108
Test name
Test status
Simulation time 246385904 ps
CPU time 0.94 seconds
Started Aug 02 05:30:51 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207404 kb
Host smart-e97a88c5-4a01-4fdb-b46e-80adb13f8d9c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=42632617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.42632617
Directory /workspace/20.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.3475214433
Short name T861
Test name
Test status
Simulation time 250977875 ps
CPU time 1 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207420 kb
Host smart-51c3f7a1-d6f0-404a-a244-9f25651990f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34752
14433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.3475214433
Directory /workspace/20.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_max_non_iso_usb_traffic.1106969231
Short name T2232
Test name
Test status
Simulation time 3677360729 ps
CPU time 36.49 seconds
Started Aug 02 05:30:54 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 224088 kb
Host smart-121419b2-f4d7-4094-a11f-349bdd8f69c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11069
69231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_non_iso_usb_traffic.1106969231
Directory /workspace/20.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1948391301
Short name T547
Test name
Test status
Simulation time 2533981083 ps
CPU time 70.94 seconds
Started Aug 02 05:31:05 PM PDT 24
Finished Aug 02 05:32:16 PM PDT 24
Peak memory 217312 kb
Host smart-ba9ec83d-82db-484b-a01c-fe45308fa990
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1948391301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1948391301
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.782277972
Short name T553
Test name
Test status
Simulation time 166488733 ps
CPU time 0.84 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:51 PM PDT 24
Peak memory 207432 kb
Host smart-eb45e5c6-d2c0-4214-aab9-36f4f5b28435
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=782277972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.782277972
Directory /workspace/20.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.1384028478
Short name T907
Test name
Test status
Simulation time 149693873 ps
CPU time 0.86 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:51 PM PDT 24
Peak memory 207432 kb
Host smart-916e6c1d-122a-4b21-aa31-90dc8deb6ffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13840
28478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.1384028478
Directory /workspace/20.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_nak_trans.2428780
Short name T3039
Test name
Test status
Simulation time 206270500 ps
CPU time 0.9 seconds
Started Aug 02 05:30:49 PM PDT 24
Finished Aug 02 05:30:50 PM PDT 24
Peak memory 207420 kb
Host smart-6f52872a-0500-4a9e-a395-960c1701db87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24287
80 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2428780
Directory /workspace/20.usbdev_nak_trans/latest


Test location /workspace/coverage/default/20.usbdev_out_iso.6817330
Short name T2775
Test name
Test status
Simulation time 195583328 ps
CPU time 0.96 seconds
Started Aug 02 05:30:53 PM PDT 24
Finished Aug 02 05:30:54 PM PDT 24
Peak memory 207380 kb
Host smart-c2877bf2-10b9-4d45-b45c-8866180f420c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68173
30 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.6817330
Directory /workspace/20.usbdev_out_iso/latest


Test location /workspace/coverage/default/20.usbdev_out_stall.2786546612
Short name T1750
Test name
Test status
Simulation time 225321249 ps
CPU time 0.93 seconds
Started Aug 02 05:30:56 PM PDT 24
Finished Aug 02 05:30:57 PM PDT 24
Peak memory 207320 kb
Host smart-62adc653-78d6-4806-9e8d-a24331f99198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27865
46612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.2786546612
Directory /workspace/20.usbdev_out_stall/latest


Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3592068731
Short name T873
Test name
Test status
Simulation time 164762913 ps
CPU time 0.84 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207432 kb
Host smart-749b95e0-ee35-4592-bed7-dcd133ca6612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35920
68731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3592068731
Directory /workspace/20.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3445337283
Short name T2019
Test name
Test status
Simulation time 184027431 ps
CPU time 0.82 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:51 PM PDT 24
Peak memory 207396 kb
Host smart-6ce56796-ebeb-439b-9045-4c3ebba1070d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34453
37283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3445337283
Directory /workspace/20.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.3414524117
Short name T839
Test name
Test status
Simulation time 243968504 ps
CPU time 1 seconds
Started Aug 02 05:30:51 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207428 kb
Host smart-52b2e9b3-8e26-4b1f-84ea-48b351911fa1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3414524117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.3414524117
Directory /workspace/20.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.3075421004
Short name T923
Test name
Test status
Simulation time 154567271 ps
CPU time 0.84 seconds
Started Aug 02 05:30:54 PM PDT 24
Finished Aug 02 05:30:55 PM PDT 24
Peak memory 207400 kb
Host smart-882e2f59-f617-490c-987e-77493428d20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30754
21004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.3075421004
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.4225679472
Short name T1068
Test name
Test status
Simulation time 51716062 ps
CPU time 0.72 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:51 PM PDT 24
Peak memory 207384 kb
Host smart-63ea7f79-978d-4d6d-b44e-d1a0ab25352f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42256
79472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.4225679472
Directory /workspace/20.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/20.usbdev_pkt_buffer.333561896
Short name T2213
Test name
Test status
Simulation time 8181871178 ps
CPU time 20.91 seconds
Started Aug 02 05:30:57 PM PDT 24
Finished Aug 02 05:31:18 PM PDT 24
Peak memory 215900 kb
Host smart-dfc0503b-7bb6-4616-bb29-5b3a6d8f37bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33356
1896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.333561896
Directory /workspace/20.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/20.usbdev_pkt_sent.3062365988
Short name T1579
Test name
Test status
Simulation time 214473784 ps
CPU time 0.95 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207356 kb
Host smart-9dfcc63c-8c2b-4211-895a-c9a164393a51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30623
65988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3062365988
Directory /workspace/20.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.4242807323
Short name T878
Test name
Test status
Simulation time 244526478 ps
CPU time 0.97 seconds
Started Aug 02 05:30:54 PM PDT 24
Finished Aug 02 05:30:56 PM PDT 24
Peak memory 207408 kb
Host smart-74514dc4-8402-464d-afb2-02281bc5d16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42428
07323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.4242807323
Directory /workspace/20.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.4124211642
Short name T1485
Test name
Test status
Simulation time 144798586 ps
CPU time 0.87 seconds
Started Aug 02 05:30:53 PM PDT 24
Finished Aug 02 05:30:54 PM PDT 24
Peak memory 207392 kb
Host smart-383c4a2a-1258-4f5a-9898-0cf0f733a55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41242
11642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.4124211642
Directory /workspace/20.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3675328714
Short name T2728
Test name
Test status
Simulation time 169910379 ps
CPU time 0.93 seconds
Started Aug 02 05:30:54 PM PDT 24
Finished Aug 02 05:30:55 PM PDT 24
Peak memory 207352 kb
Host smart-74960f45-7c91-44da-8db2-93569ac142bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36753
28714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3675328714
Directory /workspace/20.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/20.usbdev_rx_full.3178587041
Short name T302
Test name
Test status
Simulation time 278410465 ps
CPU time 1.17 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:56 PM PDT 24
Peak memory 207388 kb
Host smart-0cccdce7-ef5f-4a89-80bc-d945a157af90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31785
87041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_full.3178587041
Directory /workspace/20.usbdev_rx_full/latest


Test location /workspace/coverage/default/20.usbdev_setup_stage.4037364040
Short name T1656
Test name
Test status
Simulation time 185831746 ps
CPU time 0.87 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207412 kb
Host smart-7e9ed062-5f74-4bfa-bd23-14e46d83af32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
64040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.4037364040
Directory /workspace/20.usbdev_setup_stage/latest


Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.4166185644
Short name T2575
Test name
Test status
Simulation time 165143842 ps
CPU time 0.83 seconds
Started Aug 02 05:30:54 PM PDT 24
Finished Aug 02 05:30:55 PM PDT 24
Peak memory 207428 kb
Host smart-12877521-4f7e-47f1-b424-0fe3fc8d336e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661
85644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.4166185644
Directory /workspace/20.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/20.usbdev_smoke.4082801706
Short name T2125
Test name
Test status
Simulation time 231930229 ps
CPU time 0.95 seconds
Started Aug 02 05:30:52 PM PDT 24
Finished Aug 02 05:30:53 PM PDT 24
Peak memory 207340 kb
Host smart-8330a4a8-225c-40a5-b748-98fea61d70f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40828
01706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.4082801706
Directory /workspace/20.usbdev_smoke/latest


Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2325052450
Short name T1460
Test name
Test status
Simulation time 2923333268 ps
CPU time 88.55 seconds
Started Aug 02 05:31:02 PM PDT 24
Finished Aug 02 05:32:31 PM PDT 24
Peak memory 217792 kb
Host smart-9ad46395-5d7a-489d-a80e-01573e9cffb6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2325052450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2325052450
Directory /workspace/20.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2526262734
Short name T2793
Test name
Test status
Simulation time 189499817 ps
CPU time 0.93 seconds
Started Aug 02 05:31:03 PM PDT 24
Finished Aug 02 05:31:04 PM PDT 24
Peak memory 207364 kb
Host smart-0c7da159-8bb5-423d-bda3-a9f5343e4b32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25262
62734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2526262734
Directory /workspace/20.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/20.usbdev_stall_trans.200027268
Short name T800
Test name
Test status
Simulation time 184956188 ps
CPU time 0.93 seconds
Started Aug 02 05:30:54 PM PDT 24
Finished Aug 02 05:30:55 PM PDT 24
Peak memory 207432 kb
Host smart-35dfde55-63d7-43b0-908c-9affd36e57b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20002
7268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.200027268
Directory /workspace/20.usbdev_stall_trans/latest


Test location /workspace/coverage/default/20.usbdev_stream_len_max.748502893
Short name T853
Test name
Test status
Simulation time 1192587046 ps
CPU time 2.86 seconds
Started Aug 02 05:30:51 PM PDT 24
Finished Aug 02 05:30:54 PM PDT 24
Peak memory 207592 kb
Host smart-43985d63-48b7-4181-bafe-8d1b19b0f471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74850
2893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.748502893
Directory /workspace/20.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/20.usbdev_streaming_out.1289974650
Short name T1595
Test name
Test status
Simulation time 2880851414 ps
CPU time 78.39 seconds
Started Aug 02 05:30:56 PM PDT 24
Finished Aug 02 05:32:14 PM PDT 24
Peak memory 217432 kb
Host smart-bf34c629-742a-4212-be6f-8b6a61cbe6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12899
74650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.1289974650
Directory /workspace/20.usbdev_streaming_out/latest


Test location /workspace/coverage/default/20.usbdev_timeout_missing_host_handshake.122860083
Short name T2914
Test name
Test status
Simulation time 1697784329 ps
CPU time 41.5 seconds
Started Aug 02 05:30:49 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207528 kb
Host smart-4dec4401-529c-437d-9665-c57d974f50b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122860083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_timeout_missing_host
_handshake.122860083
Directory /workspace/20.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/21.usbdev_alert_test.4179362174
Short name T1360
Test name
Test status
Simulation time 57176509 ps
CPU time 0.67 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207508 kb
Host smart-e355d6a6-610a-4008-a98b-c576ab8469bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4179362174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.4179362174
Directory /workspace/21.usbdev_alert_test/latest


Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2165631490
Short name T2852
Test name
Test status
Simulation time 4292257672 ps
CPU time 6.04 seconds
Started Aug 02 05:30:58 PM PDT 24
Finished Aug 02 05:31:04 PM PDT 24
Peak memory 215780 kb
Host smart-9f3e2840-9de8-4a2f-8938-fc76ec6c976f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165631490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_disconnect.2165631490
Directory /workspace/21.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1692193086
Short name T10
Test name
Test status
Simulation time 20358761839 ps
CPU time 23.27 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:31:19 PM PDT 24
Peak memory 207692 kb
Host smart-8a9f516a-e342-4b56-937d-632f754d9f54
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692193086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1692193086
Directory /workspace/21.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.3681736119
Short name T1420
Test name
Test status
Simulation time 31157099197 ps
CPU time 36.82 seconds
Started Aug 02 05:30:53 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 207648 kb
Host smart-935382b3-b652-4b50-9c18-e268c708365a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681736119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_a
on_wake_resume.3681736119
Directory /workspace/21.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/21.usbdev_av_buffer.1775689137
Short name T226
Test name
Test status
Simulation time 147620946 ps
CPU time 0.82 seconds
Started Aug 02 05:30:49 PM PDT 24
Finished Aug 02 05:30:50 PM PDT 24
Peak memory 207356 kb
Host smart-d4a14a32-03e7-4f16-9654-9a8d35345da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17756
89137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1775689137
Directory /workspace/21.usbdev_av_buffer/latest


Test location /workspace/coverage/default/21.usbdev_bitstuff_err.3915087456
Short name T1353
Test name
Test status
Simulation time 156916063 ps
CPU time 0.91 seconds
Started Aug 02 05:31:00 PM PDT 24
Finished Aug 02 05:31:01 PM PDT 24
Peak memory 207320 kb
Host smart-d70a8725-4159-43cb-88a6-9404d33d7472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39150
87456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.3915087456
Directory /workspace/21.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1431838550
Short name T1788
Test name
Test status
Simulation time 421895626 ps
CPU time 1.5 seconds
Started Aug 02 05:30:50 PM PDT 24
Finished Aug 02 05:30:52 PM PDT 24
Peak memory 207420 kb
Host smart-fb72161b-f15a-43ea-8153-0ca578dafb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14318
38550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1431838550
Directory /workspace/21.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.1795972553
Short name T2543
Test name
Test status
Simulation time 1182952946 ps
CPU time 3.03 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 207608 kb
Host smart-11431fa5-e40d-44fb-bd83-fd8481f67b46
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1795972553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.1795972553
Directory /workspace/21.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/21.usbdev_device_address.605181826
Short name T185
Test name
Test status
Simulation time 30756872895 ps
CPU time 45.5 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:31:41 PM PDT 24
Peak memory 207784 kb
Host smart-7274afb7-228f-46f3-afa9-38544d55bc5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60518
1826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.605181826
Directory /workspace/21.usbdev_device_address/latest


Test location /workspace/coverage/default/21.usbdev_device_timeout.282692313
Short name T2214
Test name
Test status
Simulation time 2934336121 ps
CPU time 25.35 seconds
Started Aug 02 05:31:01 PM PDT 24
Finished Aug 02 05:31:27 PM PDT 24
Peak memory 207684 kb
Host smart-8d523672-f899-4044-b579-978afd3f13c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282692313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_timeout.282692313
Directory /workspace/21.usbdev_device_timeout/latest


Test location /workspace/coverage/default/21.usbdev_disable_endpoint.30018737
Short name T2074
Test name
Test status
Simulation time 1104746341 ps
CPU time 2.21 seconds
Started Aug 02 05:30:54 PM PDT 24
Finished Aug 02 05:30:57 PM PDT 24
Peak memory 207408 kb
Host smart-fbe4bab5-32f2-4b81-8957-290d2e72a84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30018
737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.30018737
Directory /workspace/21.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/21.usbdev_disconnected.366236331
Short name T2202
Test name
Test status
Simulation time 185198867 ps
CPU time 0.87 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:56 PM PDT 24
Peak memory 207372 kb
Host smart-8775c29d-587a-4a6e-8788-07671182e5b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36623
6331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.366236331
Directory /workspace/21.usbdev_disconnected/latest


Test location /workspace/coverage/default/21.usbdev_enable.811038031
Short name T3041
Test name
Test status
Simulation time 32772836 ps
CPU time 0.72 seconds
Started Aug 02 05:30:52 PM PDT 24
Finished Aug 02 05:30:53 PM PDT 24
Peak memory 207348 kb
Host smart-e99ce6ae-466c-4b60-b0fe-a2b7b1b0ab3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81103
8031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.811038031
Directory /workspace/21.usbdev_enable/latest


Test location /workspace/coverage/default/21.usbdev_endpoint_types.432888107
Short name T345
Test name
Test status
Simulation time 687752626 ps
CPU time 1.83 seconds
Started Aug 02 05:30:56 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 207340 kb
Host smart-e31c5d6e-9a52-4b1e-baf9-256d753844df
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=432888107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_types.432888107
Directory /workspace/21.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/21.usbdev_fifo_rst.309679753
Short name T2620
Test name
Test status
Simulation time 217835638 ps
CPU time 2.65 seconds
Started Aug 02 05:31:05 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 207528 kb
Host smart-459a4e20-283d-4369-8b32-20e22d416622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30967
9753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.309679753
Directory /workspace/21.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/21.usbdev_in_iso.2274722101
Short name T926
Test name
Test status
Simulation time 243821667 ps
CPU time 1.31 seconds
Started Aug 02 05:31:05 PM PDT 24
Finished Aug 02 05:31:07 PM PDT 24
Peak memory 215756 kb
Host smart-26fa653f-4328-4ebb-9715-2cdd0d1ed8f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2274722101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2274722101
Directory /workspace/21.usbdev_in_iso/latest


Test location /workspace/coverage/default/21.usbdev_in_stall.786857665
Short name T842
Test name
Test status
Simulation time 139728977 ps
CPU time 0.82 seconds
Started Aug 02 05:31:08 PM PDT 24
Finished Aug 02 05:31:09 PM PDT 24
Peak memory 207312 kb
Host smart-1314f0e3-b09d-4e7b-bdc5-0432261c90df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78685
7665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.786857665
Directory /workspace/21.usbdev_in_stall/latest


Test location /workspace/coverage/default/21.usbdev_in_trans.2641488292
Short name T1010
Test name
Test status
Simulation time 171574691 ps
CPU time 0.93 seconds
Started Aug 02 05:30:59 PM PDT 24
Finished Aug 02 05:31:00 PM PDT 24
Peak memory 207360 kb
Host smart-d0223c21-9653-4e0f-92c7-aefccb0f4149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26414
88292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2641488292
Directory /workspace/21.usbdev_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_invalid_sync.2398849004
Short name T1088
Test name
Test status
Simulation time 5097246810 ps
CPU time 40.13 seconds
Started Aug 02 05:30:59 PM PDT 24
Finished Aug 02 05:31:40 PM PDT 24
Peak memory 215864 kb
Host smart-493148bc-1aca-4b69-bf53-db2953542eaa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2398849004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.2398849004
Directory /workspace/21.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/21.usbdev_iso_retraction.3752804785
Short name T779
Test name
Test status
Simulation time 7818867813 ps
CPU time 51.93 seconds
Started Aug 02 05:30:59 PM PDT 24
Finished Aug 02 05:31:51 PM PDT 24
Peak memory 207600 kb
Host smart-9562805a-09fe-4712-8ec8-3946dc2e242d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3752804785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.3752804785
Directory /workspace/21.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/21.usbdev_link_in_err.3664677469
Short name T726
Test name
Test status
Simulation time 233649015 ps
CPU time 1.02 seconds
Started Aug 02 05:31:08 PM PDT 24
Finished Aug 02 05:31:09 PM PDT 24
Peak memory 207384 kb
Host smart-52337d59-4bb7-4e29-844d-3672e59be5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36646
77469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3664677469
Directory /workspace/21.usbdev_link_in_err/latest


Test location /workspace/coverage/default/21.usbdev_link_resume.1830921959
Short name T663
Test name
Test status
Simulation time 31334326947 ps
CPU time 45.53 seconds
Started Aug 02 05:31:02 PM PDT 24
Finished Aug 02 05:31:48 PM PDT 24
Peak memory 207624 kb
Host smart-ab4a8466-2eeb-4df9-8382-1b0166a823bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18309
21959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.1830921959
Directory /workspace/21.usbdev_link_resume/latest


Test location /workspace/coverage/default/21.usbdev_link_suspend.3896884843
Short name T2546
Test name
Test status
Simulation time 4381055073 ps
CPU time 5.52 seconds
Started Aug 02 05:31:04 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 216012 kb
Host smart-e69ad010-912b-44db-a130-5b72c08f9d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38968
84843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3896884843
Directory /workspace/21.usbdev_link_suspend/latest


Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1925064491
Short name T681
Test name
Test status
Simulation time 4483532866 ps
CPU time 31.91 seconds
Started Aug 02 05:31:00 PM PDT 24
Finished Aug 02 05:31:32 PM PDT 24
Peak memory 224140 kb
Host smart-a45850e8-a4ac-4095-8ed3-9bbd4dcf2f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19250
64491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1925064491
Directory /workspace/21.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3918262566
Short name T1682
Test name
Test status
Simulation time 2243255155 ps
CPU time 22.16 seconds
Started Aug 02 05:30:59 PM PDT 24
Finished Aug 02 05:31:21 PM PDT 24
Peak memory 217536 kb
Host smart-2ab4aa7b-a0af-4aa7-9987-c9b91e117892
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3918262566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3918262566
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.4017501668
Short name T506
Test name
Test status
Simulation time 278624219 ps
CPU time 1.05 seconds
Started Aug 02 05:30:55 PM PDT 24
Finished Aug 02 05:30:57 PM PDT 24
Peak memory 207368 kb
Host smart-ec3207e6-53cb-4ce4-9a18-3d1c2fc72001
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4017501668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.4017501668
Directory /workspace/21.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1043593433
Short name T2721
Test name
Test status
Simulation time 196368274 ps
CPU time 0.94 seconds
Started Aug 02 05:31:02 PM PDT 24
Finished Aug 02 05:31:03 PM PDT 24
Peak memory 207344 kb
Host smart-358290ef-d089-461c-97c8-a26c035ebfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10435
93433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1043593433
Directory /workspace/21.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_max_non_iso_usb_traffic.4243100980
Short name T755
Test name
Test status
Simulation time 1741644956 ps
CPU time 16.7 seconds
Started Aug 02 05:31:00 PM PDT 24
Finished Aug 02 05:31:16 PM PDT 24
Peak memory 223956 kb
Host smart-4ad5f339-5dab-466a-a407-2a3eecb66e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42431
00980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_non_iso_usb_traffic.4243100980
Directory /workspace/21.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.4291527139
Short name T2498
Test name
Test status
Simulation time 2097367751 ps
CPU time 14.77 seconds
Started Aug 02 05:31:10 PM PDT 24
Finished Aug 02 05:31:25 PM PDT 24
Peak memory 223912 kb
Host smart-9aabd33f-4f87-49a8-8b81-c201d6a3a9d5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4291527139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.4291527139
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1880508246
Short name T1016
Test name
Test status
Simulation time 168358538 ps
CPU time 1.02 seconds
Started Aug 02 05:30:57 PM PDT 24
Finished Aug 02 05:30:59 PM PDT 24
Peak memory 207392 kb
Host smart-a656243c-d663-4c44-b024-fe2234d1f0d4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1880508246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1880508246
Directory /workspace/21.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.1574529146
Short name T2141
Test name
Test status
Simulation time 148836458 ps
CPU time 0.79 seconds
Started Aug 02 05:31:06 PM PDT 24
Finished Aug 02 05:31:07 PM PDT 24
Peak memory 207392 kb
Host smart-8d4bbd0a-3ec9-410e-82f1-208c642c43bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15745
29146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.1574529146
Directory /workspace/21.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_out_iso.1505182900
Short name T955
Test name
Test status
Simulation time 196092921 ps
CPU time 0.96 seconds
Started Aug 02 05:31:02 PM PDT 24
Finished Aug 02 05:31:03 PM PDT 24
Peak memory 207364 kb
Host smart-7120901c-dd1d-42cd-bd51-7acdd5a34ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15051
82900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1505182900
Directory /workspace/21.usbdev_out_iso/latest


Test location /workspace/coverage/default/21.usbdev_out_stall.2037648932
Short name T1050
Test name
Test status
Simulation time 195701621 ps
CPU time 0.9 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207376 kb
Host smart-1f9adf29-a515-4e87-a2d7-f9df9683c20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20376
48932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.2037648932
Directory /workspace/21.usbdev_out_stall/latest


Test location /workspace/coverage/default/21.usbdev_out_trans_nak.691851263
Short name T2828
Test name
Test status
Simulation time 229386342 ps
CPU time 0.97 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207428 kb
Host smart-a707c990-c5c9-416d-9b53-f8d2ad3671a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69185
1263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.691851263
Directory /workspace/21.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2214969921
Short name T2770
Test name
Test status
Simulation time 167931841 ps
CPU time 0.86 seconds
Started Aug 02 05:30:58 PM PDT 24
Finished Aug 02 05:30:59 PM PDT 24
Peak memory 207400 kb
Host smart-ba50ab97-410e-4f14-9eef-97bddad20f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22149
69921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2214969921
Directory /workspace/21.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.2547905699
Short name T2037
Test name
Test status
Simulation time 268951797 ps
CPU time 1.06 seconds
Started Aug 02 05:31:06 PM PDT 24
Finished Aug 02 05:31:07 PM PDT 24
Peak memory 207348 kb
Host smart-f59c261b-9e33-4ac7-bcd2-ee7f3c3f738e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2547905699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.2547905699
Directory /workspace/21.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3652144246
Short name T3008
Test name
Test status
Simulation time 135966723 ps
CPU time 0.85 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:11 PM PDT 24
Peak memory 207372 kb
Host smart-e44956db-4596-4b2e-b6f4-cc805803b9d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36521
44246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3652144246
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.4284470322
Short name T3059
Test name
Test status
Simulation time 47693353 ps
CPU time 0.72 seconds
Started Aug 02 05:30:56 PM PDT 24
Finished Aug 02 05:30:56 PM PDT 24
Peak memory 207356 kb
Host smart-92e24b6d-8ffd-4f19-b312-3cc934a9f344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42844
70322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.4284470322
Directory /workspace/21.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2831835471
Short name T2052
Test name
Test status
Simulation time 19284887198 ps
CPU time 48.93 seconds
Started Aug 02 05:31:01 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 215932 kb
Host smart-5ba35af8-317b-4d73-ac49-64ea9e34b93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28318
35471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2831835471
Directory /workspace/21.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/21.usbdev_pkt_received.1232457925
Short name T2975
Test name
Test status
Simulation time 243478946 ps
CPU time 1 seconds
Started Aug 02 05:31:03 PM PDT 24
Finished Aug 02 05:31:04 PM PDT 24
Peak memory 207444 kb
Host smart-80db94bd-80b4-46fd-8502-d4ac2eed96d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12324
57925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1232457925
Directory /workspace/21.usbdev_pkt_received/latest


Test location /workspace/coverage/default/21.usbdev_pkt_sent.528598556
Short name T1100
Test name
Test status
Simulation time 184819910 ps
CPU time 0.91 seconds
Started Aug 02 05:30:58 PM PDT 24
Finished Aug 02 05:30:59 PM PDT 24
Peak memory 207380 kb
Host smart-e4d94943-fb84-4bf1-ba1c-03067b4d1abb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52859
8556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.528598556
Directory /workspace/21.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.541201873
Short name T2749
Test name
Test status
Simulation time 313232044 ps
CPU time 1.11 seconds
Started Aug 02 05:30:58 PM PDT 24
Finished Aug 02 05:30:59 PM PDT 24
Peak memory 207360 kb
Host smart-a9eba104-6cee-42db-970b-6b601674a56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54120
1873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.541201873
Directory /workspace/21.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3248036826
Short name T2982
Test name
Test status
Simulation time 189395431 ps
CPU time 0.98 seconds
Started Aug 02 05:31:02 PM PDT 24
Finished Aug 02 05:31:03 PM PDT 24
Peak memory 207460 kb
Host smart-9408a532-f87d-4a57-b4e5-7d2672fd9483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32480
36826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3248036826
Directory /workspace/21.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2180722170
Short name T1911
Test name
Test status
Simulation time 167313719 ps
CPU time 0.86 seconds
Started Aug 02 05:31:00 PM PDT 24
Finished Aug 02 05:31:01 PM PDT 24
Peak memory 207432 kb
Host smart-6fce16b9-b053-403c-9e58-db5746b5abbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21807
22170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2180722170
Directory /workspace/21.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/21.usbdev_rx_full.1258736324
Short name T2757
Test name
Test status
Simulation time 243125141 ps
CPU time 1.09 seconds
Started Aug 02 05:31:06 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 207396 kb
Host smart-2fa5e808-b7ca-4992-be18-6a43860cb53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12587
36324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_full.1258736324
Directory /workspace/21.usbdev_rx_full/latest


Test location /workspace/coverage/default/21.usbdev_setup_stage.3107520177
Short name T1580
Test name
Test status
Simulation time 170506746 ps
CPU time 0.83 seconds
Started Aug 02 05:31:08 PM PDT 24
Finished Aug 02 05:31:09 PM PDT 24
Peak memory 207380 kb
Host smart-9a7535dc-8a1b-4221-a10b-c5d89b516428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31075
20177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.3107520177
Directory /workspace/21.usbdev_setup_stage/latest


Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.2507767663
Short name T2971
Test name
Test status
Simulation time 155422743 ps
CPU time 0.89 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 207352 kb
Host smart-23326168-531b-4c8c-91f4-20093de5610c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25077
67663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.2507767663
Directory /workspace/21.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/21.usbdev_smoke.3659919126
Short name T667
Test name
Test status
Simulation time 240571245 ps
CPU time 1.05 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:09 PM PDT 24
Peak memory 207392 kb
Host smart-3b6e03fa-6031-4e25-b54f-9fc62c1f720f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36599
19126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.3659919126
Directory /workspace/21.usbdev_smoke/latest


Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1647032388
Short name T2534
Test name
Test status
Simulation time 3311618648 ps
CPU time 25.04 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:32 PM PDT 24
Peak memory 224028 kb
Host smart-13e4a77a-cb08-482a-ba94-a2b8d090586b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1647032388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1647032388
Directory /workspace/21.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.740184960
Short name T2302
Test name
Test status
Simulation time 169296159 ps
CPU time 0.92 seconds
Started Aug 02 05:31:05 PM PDT 24
Finished Aug 02 05:31:06 PM PDT 24
Peak memory 207392 kb
Host smart-a4a81126-83b6-45f9-a521-4715fd440243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74018
4960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.740184960
Directory /workspace/21.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/21.usbdev_stall_trans.390677432
Short name T3054
Test name
Test status
Simulation time 184237360 ps
CPU time 0.85 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207356 kb
Host smart-4811c0a9-30ab-4668-8d7e-81917d717674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39067
7432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.390677432
Directory /workspace/21.usbdev_stall_trans/latest


Test location /workspace/coverage/default/21.usbdev_stream_len_max.3355019950
Short name T1130
Test name
Test status
Simulation time 258651701 ps
CPU time 1.04 seconds
Started Aug 02 05:30:57 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 207356 kb
Host smart-61e84b0f-abb1-4db0-8f45-3c711301cbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33550
19950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3355019950
Directory /workspace/21.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/21.usbdev_streaming_out.430265905
Short name T2686
Test name
Test status
Simulation time 2722866414 ps
CPU time 26.54 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:32:03 PM PDT 24
Peak memory 224076 kb
Host smart-e987fd7d-e06f-4a2a-9e0b-667bf0defbd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43026
5905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.430265905
Directory /workspace/21.usbdev_streaming_out/latest


Test location /workspace/coverage/default/21.usbdev_timeout_missing_host_handshake.2656283289
Short name T490
Test name
Test status
Simulation time 2447988675 ps
CPU time 21.55 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207724 kb
Host smart-85382b02-52ea-43e3-af3e-59d1e7c71c3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656283289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_timeout_missing_hos
t_handshake.2656283289
Directory /workspace/21.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/22.usbdev_alert_test.1375964967
Short name T197
Test name
Test status
Simulation time 49082840 ps
CPU time 0.68 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 207464 kb
Host smart-b6f51e7e-2e9a-49d7-b67e-47a7de757a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1375964967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1375964967
Directory /workspace/22.usbdev_alert_test/latest


Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1373546280
Short name T2799
Test name
Test status
Simulation time 10438288039 ps
CPU time 12.66 seconds
Started Aug 02 05:31:03 PM PDT 24
Finished Aug 02 05:31:16 PM PDT 24
Peak memory 207624 kb
Host smart-3363fb41-2ea2-4e92-8fda-5e3102b746b2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373546280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_disconnect.1373546280
Directory /workspace/22.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.1033494700
Short name T2961
Test name
Test status
Simulation time 14982395733 ps
CPU time 16.52 seconds
Started Aug 02 05:30:57 PM PDT 24
Finished Aug 02 05:31:14 PM PDT 24
Peak memory 215856 kb
Host smart-9315e3dc-93ae-41e1-a047-2ef3285dd789
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033494700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.1033494700
Directory /workspace/22.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1737094427
Short name T2088
Test name
Test status
Simulation time 23777726250 ps
CPU time 29.5 seconds
Started Aug 02 05:30:57 PM PDT 24
Finished Aug 02 05:31:27 PM PDT 24
Peak memory 215856 kb
Host smart-95efe9b2-5396-416b-bbb3-fd3a865faec1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737094427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_a
on_wake_resume.1737094427
Directory /workspace/22.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/22.usbdev_av_buffer.2650984016
Short name T1151
Test name
Test status
Simulation time 153618123 ps
CPU time 0.84 seconds
Started Aug 02 05:31:05 PM PDT 24
Finished Aug 02 05:31:06 PM PDT 24
Peak memory 207384 kb
Host smart-7722fb34-551a-44dd-9695-68799b5cb3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26509
84016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.2650984016
Directory /workspace/22.usbdev_av_buffer/latest


Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2251049228
Short name T2339
Test name
Test status
Simulation time 183321326 ps
CPU time 0.88 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 207316 kb
Host smart-195ef6a7-fe1a-4531-b40e-2b218e9f08aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22510
49228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2251049228
Directory /workspace/22.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.99081636
Short name T2860
Test name
Test status
Simulation time 506875090 ps
CPU time 1.6 seconds
Started Aug 02 05:31:00 PM PDT 24
Finished Aug 02 05:31:02 PM PDT 24
Peak memory 207444 kb
Host smart-ccda4b05-03a3-4abd-832c-a05ff8370c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99081
636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.99081636
Directory /workspace/22.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1812547898
Short name T1936
Test name
Test status
Simulation time 553701452 ps
CPU time 1.79 seconds
Started Aug 02 05:30:59 PM PDT 24
Finished Aug 02 05:31:01 PM PDT 24
Peak memory 207320 kb
Host smart-32f78797-0e06-4743-a496-e8bb2fe48d9b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1812547898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1812547898
Directory /workspace/22.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/22.usbdev_device_address.1518895630
Short name T1965
Test name
Test status
Simulation time 53356418500 ps
CPU time 84.47 seconds
Started Aug 02 05:31:00 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 207704 kb
Host smart-d6cea9b0-3400-44d8-9b5e-7fe2e246627e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15188
95630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.1518895630
Directory /workspace/22.usbdev_device_address/latest


Test location /workspace/coverage/default/22.usbdev_device_timeout.2260979875
Short name T2937
Test name
Test status
Simulation time 3734888902 ps
CPU time 25.38 seconds
Started Aug 02 05:31:10 PM PDT 24
Finished Aug 02 05:31:35 PM PDT 24
Peak memory 207688 kb
Host smart-78015c5b-84f8-401f-b466-176e5e8ac20d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260979875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_timeout.2260979875
Directory /workspace/22.usbdev_device_timeout/latest


Test location /workspace/coverage/default/22.usbdev_disable_endpoint.1192402981
Short name T1241
Test name
Test status
Simulation time 803952035 ps
CPU time 1.72 seconds
Started Aug 02 05:31:03 PM PDT 24
Finished Aug 02 05:31:05 PM PDT 24
Peak memory 207428 kb
Host smart-a4d942de-8a16-47e7-9cff-55382f8db7bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11924
02981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.1192402981
Directory /workspace/22.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/22.usbdev_disconnected.880468876
Short name T2523
Test name
Test status
Simulation time 150108610 ps
CPU time 0.79 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207316 kb
Host smart-0820f8e5-cbcc-4819-b0e6-7e13f4196001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88046
8876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.880468876
Directory /workspace/22.usbdev_disconnected/latest


Test location /workspace/coverage/default/22.usbdev_enable.2201696341
Short name T608
Test name
Test status
Simulation time 48198831 ps
CPU time 0.68 seconds
Started Aug 02 05:31:08 PM PDT 24
Finished Aug 02 05:31:09 PM PDT 24
Peak memory 207320 kb
Host smart-7f117226-f389-4db2-ae1e-c418275bc869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22016
96341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.2201696341
Directory /workspace/22.usbdev_enable/latest


Test location /workspace/coverage/default/22.usbdev_endpoint_access.1087360988
Short name T1552
Test name
Test status
Simulation time 744531051 ps
CPU time 2.13 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 207652 kb
Host smart-a99d2fa3-b9ee-4538-8e77-ac0d6bfd9b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10873
60988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1087360988
Directory /workspace/22.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/22.usbdev_endpoint_types.2476009096
Short name T391
Test name
Test status
Simulation time 549768671 ps
CPU time 1.58 seconds
Started Aug 02 05:31:06 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 207348 kb
Host smart-dc18b66f-e8f5-4520-a165-17c262c56461
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2476009096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_types.2476009096
Directory /workspace/22.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/22.usbdev_fifo_rst.1360493617
Short name T1719
Test name
Test status
Simulation time 345771459 ps
CPU time 2.51 seconds
Started Aug 02 05:31:01 PM PDT 24
Finished Aug 02 05:31:04 PM PDT 24
Peak memory 207584 kb
Host smart-e1280279-5c20-47e1-a858-38bdd42f8d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13604
93617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1360493617
Directory /workspace/22.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/22.usbdev_in_iso.1965745259
Short name T885
Test name
Test status
Simulation time 225068234 ps
CPU time 1.17 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 215832 kb
Host smart-e8424078-3b10-4b1a-a7ff-ec3cdd8d40a0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1965745259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.1965745259
Directory /workspace/22.usbdev_in_iso/latest


Test location /workspace/coverage/default/22.usbdev_in_stall.977035553
Short name T1914
Test name
Test status
Simulation time 156890879 ps
CPU time 0.83 seconds
Started Aug 02 05:31:00 PM PDT 24
Finished Aug 02 05:31:01 PM PDT 24
Peak memory 207340 kb
Host smart-2b09f021-3bd3-4b73-ab64-4a25b00fe0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97703
5553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.977035553
Directory /workspace/22.usbdev_in_stall/latest


Test location /workspace/coverage/default/22.usbdev_in_trans.2670756036
Short name T2334
Test name
Test status
Simulation time 169901206 ps
CPU time 0.87 seconds
Started Aug 02 05:31:06 PM PDT 24
Finished Aug 02 05:31:07 PM PDT 24
Peak memory 207388 kb
Host smart-efc67142-a46b-43f9-b0f2-d3b6177d288b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26707
56036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2670756036
Directory /workspace/22.usbdev_in_trans/latest


Test location /workspace/coverage/default/22.usbdev_invalid_sync.1979211621
Short name T1642
Test name
Test status
Simulation time 4747060121 ps
CPU time 138.49 seconds
Started Aug 02 05:31:04 PM PDT 24
Finished Aug 02 05:33:23 PM PDT 24
Peak memory 215852 kb
Host smart-469f5201-2364-4eca-b4a9-30d6649c69d6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1979211621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.1979211621
Directory /workspace/22.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/22.usbdev_iso_retraction.1333322608
Short name T267
Test name
Test status
Simulation time 7739781262 ps
CPU time 47.65 seconds
Started Aug 02 05:31:01 PM PDT 24
Finished Aug 02 05:31:49 PM PDT 24
Peak memory 207632 kb
Host smart-8a6467d9-2f56-4cb9-bbab-f445ac76f6ef
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1333322608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.1333322608
Directory /workspace/22.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/22.usbdev_link_in_err.3788888175
Short name T2996
Test name
Test status
Simulation time 209322139 ps
CPU time 0.95 seconds
Started Aug 02 05:31:01 PM PDT 24
Finished Aug 02 05:31:02 PM PDT 24
Peak memory 207388 kb
Host smart-3ca4ee82-76ab-4cc1-978f-63f52a2cbf8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37888
88175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3788888175
Directory /workspace/22.usbdev_link_in_err/latest


Test location /workspace/coverage/default/22.usbdev_link_resume.1239331637
Short name T1588
Test name
Test status
Simulation time 32879723694 ps
CPU time 44.05 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:51 PM PDT 24
Peak memory 207640 kb
Host smart-9be883d2-47f6-408a-919c-ce35c849da5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12393
31637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1239331637
Directory /workspace/22.usbdev_link_resume/latest


Test location /workspace/coverage/default/22.usbdev_link_suspend.2289257972
Short name T1751
Test name
Test status
Simulation time 5957738964 ps
CPU time 7.58 seconds
Started Aug 02 05:31:02 PM PDT 24
Finished Aug 02 05:31:09 PM PDT 24
Peak memory 215872 kb
Host smart-332a8834-03ff-452e-9d8b-1ae330d63b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22892
57972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.2289257972
Directory /workspace/22.usbdev_link_suspend/latest


Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.948133177
Short name T599
Test name
Test status
Simulation time 2499829173 ps
CPU time 19.34 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:29 PM PDT 24
Peak memory 217588 kb
Host smart-e05e9588-4d78-412c-bacf-a65b70a6404e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=948133177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.948133177
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.4133248122
Short name T2296
Test name
Test status
Simulation time 278810135 ps
CPU time 1.07 seconds
Started Aug 02 05:31:03 PM PDT 24
Finished Aug 02 05:31:05 PM PDT 24
Peak memory 207408 kb
Host smart-a1bb5f55-e8a2-4f3e-9e94-9b9ac8122514
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4133248122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.4133248122
Directory /workspace/22.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.465902358
Short name T3092
Test name
Test status
Simulation time 225179895 ps
CPU time 1.02 seconds
Started Aug 02 05:31:06 PM PDT 24
Finished Aug 02 05:31:07 PM PDT 24
Peak memory 207424 kb
Host smart-3b3af3cb-c962-4546-818c-349cc1cd5f1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46590
2358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.465902358
Directory /workspace/22.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_max_non_iso_usb_traffic.2332310549
Short name T2902
Test name
Test status
Simulation time 3086023993 ps
CPU time 85.36 seconds
Started Aug 02 05:31:04 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 217780 kb
Host smart-6e0ac8f5-e878-4db2-a6fb-72e9a0168583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23323
10549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_non_iso_usb_traffic.2332310549
Directory /workspace/22.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.3631405653
Short name T1823
Test name
Test status
Simulation time 2211759006 ps
CPU time 16.55 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:26 PM PDT 24
Peak memory 215944 kb
Host smart-ef494168-03a6-4d40-b065-cb1fe9ac5f7b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3631405653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.3631405653
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.634229297
Short name T813
Test name
Test status
Simulation time 172344698 ps
CPU time 0.86 seconds
Started Aug 02 05:31:14 PM PDT 24
Finished Aug 02 05:31:15 PM PDT 24
Peak memory 207376 kb
Host smart-5bb58427-e2a9-4888-b355-52c854932f09
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=634229297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.634229297
Directory /workspace/22.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.3856964136
Short name T1498
Test name
Test status
Simulation time 140341140 ps
CPU time 0.8 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 207392 kb
Host smart-83a5c20c-6f10-43f5-b8d8-8c317c86a884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38569
64136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.3856964136
Directory /workspace/22.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_nak_trans.913874142
Short name T150
Test name
Test status
Simulation time 213777576 ps
CPU time 0.99 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 207372 kb
Host smart-93153d3c-93b5-4b43-a474-af25c7981eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91387
4142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.913874142
Directory /workspace/22.usbdev_nak_trans/latest


Test location /workspace/coverage/default/22.usbdev_out_iso.1484825018
Short name T2440
Test name
Test status
Simulation time 183461058 ps
CPU time 0.94 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:08 PM PDT 24
Peak memory 207388 kb
Host smart-154c9856-5a70-4389-bab9-dad667604ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14848
25018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.1484825018
Directory /workspace/22.usbdev_out_iso/latest


Test location /workspace/coverage/default/22.usbdev_out_stall.1215366633
Short name T2178
Test name
Test status
Simulation time 197535657 ps
CPU time 0.9 seconds
Started Aug 02 05:31:19 PM PDT 24
Finished Aug 02 05:31:20 PM PDT 24
Peak memory 207400 kb
Host smart-a5bf2c77-e640-480e-8ed6-a12dbd5c7399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12153
66633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1215366633
Directory /workspace/22.usbdev_out_stall/latest


Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2420121792
Short name T2670
Test name
Test status
Simulation time 184920179 ps
CPU time 0.86 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207332 kb
Host smart-fb0f4bc1-7540-4183-b613-7007d7f37665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24201
21792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2420121792
Directory /workspace/22.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/22.usbdev_pending_in_trans.3649116856
Short name T1390
Test name
Test status
Simulation time 149499639 ps
CPU time 0.87 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 207400 kb
Host smart-df9904b3-dde2-4359-ad94-175999266014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36491
16856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.3649116856
Directory /workspace/22.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.353505285
Short name T2320
Test name
Test status
Simulation time 217518105 ps
CPU time 1 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:31:36 PM PDT 24
Peak memory 207208 kb
Host smart-d24daec5-5342-49c6-8042-6938e0d2bc28
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=353505285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.353505285
Directory /workspace/22.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.2180870439
Short name T1979
Test name
Test status
Simulation time 142645223 ps
CPU time 0.8 seconds
Started Aug 02 05:31:10 PM PDT 24
Finished Aug 02 05:31:11 PM PDT 24
Peak memory 207284 kb
Host smart-89fb114f-e86e-4bda-ba3f-150515b9004a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21808
70439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.2180870439
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.311504768
Short name T2203
Test name
Test status
Simulation time 136118044 ps
CPU time 0.8 seconds
Started Aug 02 05:31:08 PM PDT 24
Finished Aug 02 05:31:09 PM PDT 24
Peak memory 207388 kb
Host smart-070e5d1d-fd67-4663-90b0-966430b6fcf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31150
4768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.311504768
Directory /workspace/22.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/22.usbdev_pkt_buffer.4291242908
Short name T2405
Test name
Test status
Simulation time 22661049534 ps
CPU time 54.3 seconds
Started Aug 02 05:31:16 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 215916 kb
Host smart-877e5e36-1da2-40aa-82ec-3a74452c38ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42912
42908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.4291242908
Directory /workspace/22.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/22.usbdev_pkt_received.2976707882
Short name T2255
Test name
Test status
Simulation time 202617980 ps
CPU time 0.89 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207332 kb
Host smart-2c5eb0a4-8387-4d9d-af00-00e08349c181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29767
07882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2976707882
Directory /workspace/22.usbdev_pkt_received/latest


Test location /workspace/coverage/default/22.usbdev_pkt_sent.2304966035
Short name T2528
Test name
Test status
Simulation time 217443385 ps
CPU time 0.91 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:31:35 PM PDT 24
Peak memory 207196 kb
Host smart-15057efa-867d-4513-99e4-68cc3943c94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23049
66035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2304966035
Directory /workspace/22.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.4022482532
Short name T2151
Test name
Test status
Simulation time 208519243 ps
CPU time 0.92 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 207336 kb
Host smart-2d8020f3-5c65-4fc3-be1f-3e1933091721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40224
82532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.4022482532
Directory /workspace/22.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.1216038928
Short name T951
Test name
Test status
Simulation time 205261727 ps
CPU time 0.95 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207412 kb
Host smart-1436a7cf-704b-485b-b79c-fa577044a27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12160
38928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.1216038928
Directory /workspace/22.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/22.usbdev_rx_crc_err.1418082861
Short name T3091
Test name
Test status
Simulation time 184843891 ps
CPU time 0.95 seconds
Started Aug 02 05:31:15 PM PDT 24
Finished Aug 02 05:31:16 PM PDT 24
Peak memory 207356 kb
Host smart-a1984447-a525-4b0b-a906-72e6eb467de9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14180
82861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.1418082861
Directory /workspace/22.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/22.usbdev_setup_stage.526095962
Short name T592
Test name
Test status
Simulation time 175208554 ps
CPU time 0.88 seconds
Started Aug 02 05:31:17 PM PDT 24
Finished Aug 02 05:31:18 PM PDT 24
Peak memory 207372 kb
Host smart-680aecbc-27da-4d45-ae02-a799181519fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52609
5962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.526095962
Directory /workspace/22.usbdev_setup_stage/latest


Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3220447775
Short name T1345
Test name
Test status
Simulation time 184976580 ps
CPU time 0.84 seconds
Started Aug 02 05:31:19 PM PDT 24
Finished Aug 02 05:31:20 PM PDT 24
Peak memory 207408 kb
Host smart-414ce112-4890-4d83-9b32-8b33fe41adc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32204
47775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3220447775
Directory /workspace/22.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/22.usbdev_smoke.502015671
Short name T654
Test name
Test status
Simulation time 219386695 ps
CPU time 0.99 seconds
Started Aug 02 05:31:10 PM PDT 24
Finished Aug 02 05:31:11 PM PDT 24
Peak memory 207372 kb
Host smart-23c9be7d-218e-4e50-b6d9-d9a3f500992b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50201
5671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.502015671
Directory /workspace/22.usbdev_smoke/latest


Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1807043931
Short name T1403
Test name
Test status
Simulation time 3548798765 ps
CPU time 35.28 seconds
Started Aug 02 05:31:10 PM PDT 24
Finished Aug 02 05:31:46 PM PDT 24
Peak memory 224084 kb
Host smart-0e997054-6216-42a5-8dfd-b8bd1d7a210d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1807043931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1807043931
Directory /workspace/22.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.999511619
Short name T2848
Test name
Test status
Simulation time 239607326 ps
CPU time 1 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207352 kb
Host smart-3c6db979-eda5-41eb-a940-bad815b97902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99951
1619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.999511619
Directory /workspace/22.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/22.usbdev_stall_trans.2955537488
Short name T979
Test name
Test status
Simulation time 178734080 ps
CPU time 0.85 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207208 kb
Host smart-1ff3793a-9646-43d4-8181-785c0f592556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29555
37488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2955537488
Directory /workspace/22.usbdev_stall_trans/latest


Test location /workspace/coverage/default/22.usbdev_stream_len_max.1853081883
Short name T1003
Test name
Test status
Simulation time 984401444 ps
CPU time 2.43 seconds
Started Aug 02 05:31:13 PM PDT 24
Finished Aug 02 05:31:15 PM PDT 24
Peak memory 207616 kb
Host smart-44ccc171-ff52-4182-a1e0-e47951571e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18530
81883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1853081883
Directory /workspace/22.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/22.usbdev_streaming_out.1700508722
Short name T3088
Test name
Test status
Simulation time 2602165314 ps
CPU time 18.34 seconds
Started Aug 02 05:31:20 PM PDT 24
Finished Aug 02 05:31:38 PM PDT 24
Peak memory 215912 kb
Host smart-18bee176-33ed-469a-b482-a9fb382c4d99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17005
08722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.1700508722
Directory /workspace/22.usbdev_streaming_out/latest


Test location /workspace/coverage/default/22.usbdev_timeout_missing_host_handshake.35528479
Short name T57
Test name
Test status
Simulation time 280734027 ps
CPU time 4.53 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:15 PM PDT 24
Peak memory 207604 kb
Host smart-107b8c18-8da9-4292-af39-6f3dc1576cf4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35528479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_timeout_missing_host_
handshake.35528479
Directory /workspace/22.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/23.usbdev_alert_test.2593100851
Short name T2421
Test name
Test status
Simulation time 32912454 ps
CPU time 0.67 seconds
Started Aug 02 05:31:23 PM PDT 24
Finished Aug 02 05:31:24 PM PDT 24
Peak memory 207488 kb
Host smart-bfc093f9-4dd0-44a4-8a63-595f7cb3fa0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2593100851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.2593100851
Directory /workspace/23.usbdev_alert_test/latest


Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.2558881421
Short name T1995
Test name
Test status
Simulation time 11096707871 ps
CPU time 15.02 seconds
Started Aug 02 05:31:06 PM PDT 24
Finished Aug 02 05:31:21 PM PDT 24
Peak memory 207092 kb
Host smart-43f9216d-ddf9-441f-9e67-3002b178c264
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558881421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_a
on_wake_disconnect.2558881421
Directory /workspace/23.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2033081938
Short name T889
Test name
Test status
Simulation time 21288196120 ps
CPU time 25.39 seconds
Started Aug 02 05:31:08 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 207628 kb
Host smart-44802c21-6658-4282-8c63-6769ca52319c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033081938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2033081938
Directory /workspace/23.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.787880494
Short name T2985
Test name
Test status
Simulation time 23388038437 ps
CPU time 30.02 seconds
Started Aug 02 05:31:09 PM PDT 24
Finished Aug 02 05:31:39 PM PDT 24
Peak memory 215896 kb
Host smart-0922b492-92cb-460c-87dd-e18e322181ce
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787880494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_ao
n_wake_resume.787880494
Directory /workspace/23.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/23.usbdev_av_buffer.3062039622
Short name T1686
Test name
Test status
Simulation time 171822941 ps
CPU time 0.91 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 207392 kb
Host smart-99ce1360-cbb8-465a-ad50-0a46b2af72fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30620
39622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3062039622
Directory /workspace/23.usbdev_av_buffer/latest


Test location /workspace/coverage/default/23.usbdev_bitstuff_err.3329718042
Short name T1085
Test name
Test status
Simulation time 204609053 ps
CPU time 0.91 seconds
Started Aug 02 05:31:12 PM PDT 24
Finished Aug 02 05:31:13 PM PDT 24
Peak memory 207412 kb
Host smart-d4cd2356-4262-4099-b83f-2b947427a387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33297
18042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.3329718042
Directory /workspace/23.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1378102322
Short name T1994
Test name
Test status
Simulation time 533164246 ps
CPU time 1.73 seconds
Started Aug 02 05:31:21 PM PDT 24
Finished Aug 02 05:31:23 PM PDT 24
Peak memory 207392 kb
Host smart-eac38beb-c266-4016-908d-12c4b895023a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13781
02322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1378102322
Directory /workspace/23.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.506619030
Short name T1630
Test name
Test status
Simulation time 1186243297 ps
CPU time 3.09 seconds
Started Aug 02 05:31:16 PM PDT 24
Finished Aug 02 05:31:20 PM PDT 24
Peak memory 207640 kb
Host smart-34dbb22e-ff8a-4704-9ba6-02d7be957a1e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=506619030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.506619030
Directory /workspace/23.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/23.usbdev_device_timeout.3082613362
Short name T2445
Test name
Test status
Simulation time 1152213910 ps
CPU time 25.85 seconds
Started Aug 02 05:31:08 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 207584 kb
Host smart-571aa650-3914-48e6-b87d-cec8c3c56c03
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082613362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_timeout.3082613362
Directory /workspace/23.usbdev_device_timeout/latest


Test location /workspace/coverage/default/23.usbdev_disable_endpoint.1219288830
Short name T913
Test name
Test status
Simulation time 709025473 ps
CPU time 1.64 seconds
Started Aug 02 05:31:26 PM PDT 24
Finished Aug 02 05:31:28 PM PDT 24
Peak memory 207388 kb
Host smart-dd64ebfa-3304-41c4-be74-92a3d138cb12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12192
88830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.1219288830
Directory /workspace/23.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/23.usbdev_disconnected.2548187304
Short name T1967
Test name
Test status
Simulation time 142056977 ps
CPU time 0.86 seconds
Started Aug 02 05:31:13 PM PDT 24
Finished Aug 02 05:31:14 PM PDT 24
Peak memory 207384 kb
Host smart-ecbb84f4-4dd6-4501-a458-bb5700a82a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25481
87304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.2548187304
Directory /workspace/23.usbdev_disconnected/latest


Test location /workspace/coverage/default/23.usbdev_enable.2316593493
Short name T2566
Test name
Test status
Simulation time 46152603 ps
CPU time 0.73 seconds
Started Aug 02 05:31:10 PM PDT 24
Finished Aug 02 05:31:11 PM PDT 24
Peak memory 207384 kb
Host smart-02ff6c8c-7cf9-4c64-9093-66355848dfb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23165
93493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.2316593493
Directory /workspace/23.usbdev_enable/latest


Test location /workspace/coverage/default/23.usbdev_endpoint_access.126440843
Short name T1136
Test name
Test status
Simulation time 1004335959 ps
CPU time 2.56 seconds
Started Aug 02 05:31:10 PM PDT 24
Finished Aug 02 05:31:13 PM PDT 24
Peak memory 207532 kb
Host smart-416f849f-8b4d-4a42-ba9e-9a8cad3d052f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12644
0843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.126440843
Directory /workspace/23.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/23.usbdev_endpoint_types.3423987177
Short name T2153
Test name
Test status
Simulation time 180044661 ps
CPU time 0.96 seconds
Started Aug 02 05:31:13 PM PDT 24
Finished Aug 02 05:31:14 PM PDT 24
Peak memory 207356 kb
Host smart-c30ff93d-8a13-4dc6-b106-d969340f75d5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3423987177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_types.3423987177
Directory /workspace/23.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/23.usbdev_fifo_rst.3890522707
Short name T1950
Test name
Test status
Simulation time 222296315 ps
CPU time 1.36 seconds
Started Aug 02 05:31:21 PM PDT 24
Finished Aug 02 05:31:22 PM PDT 24
Peak memory 207376 kb
Host smart-d843212a-3020-418a-8dfc-8ca46d5b7ef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38905
22707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.3890522707
Directory /workspace/23.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/23.usbdev_in_iso.3511000854
Short name T630
Test name
Test status
Simulation time 247543509 ps
CPU time 1.1 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 215580 kb
Host smart-f3c4de5b-3c44-4daa-862e-8ad9182086bd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3511000854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3511000854
Directory /workspace/23.usbdev_in_iso/latest


Test location /workspace/coverage/default/23.usbdev_in_stall.2576409867
Short name T1331
Test name
Test status
Simulation time 139132963 ps
CPU time 0.79 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:31:35 PM PDT 24
Peak memory 207176 kb
Host smart-630ed763-9639-48dc-aa25-a0d990216ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25764
09867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.2576409867
Directory /workspace/23.usbdev_in_stall/latest


Test location /workspace/coverage/default/23.usbdev_in_trans.1001807707
Short name T1794
Test name
Test status
Simulation time 170467509 ps
CPU time 1 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 207328 kb
Host smart-715b1050-68c9-4c24-b426-69177cc24944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10018
07707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1001807707
Directory /workspace/23.usbdev_in_trans/latest


Test location /workspace/coverage/default/23.usbdev_invalid_sync.3504779460
Short name T2544
Test name
Test status
Simulation time 3180361924 ps
CPU time 86.1 seconds
Started Aug 02 05:31:19 PM PDT 24
Finished Aug 02 05:32:46 PM PDT 24
Peak memory 224028 kb
Host smart-42ba8276-b86a-4c27-aef3-fb091ff77c1e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3504779460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3504779460
Directory /workspace/23.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/23.usbdev_iso_retraction.3455048803
Short name T89
Test name
Test status
Simulation time 4564828208 ps
CPU time 32.34 seconds
Started Aug 02 05:31:13 PM PDT 24
Finished Aug 02 05:31:46 PM PDT 24
Peak memory 207648 kb
Host smart-9343fc23-2f2c-41a2-b758-a55ae993c7f7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3455048803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.3455048803
Directory /workspace/23.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/23.usbdev_link_in_err.313756320
Short name T2181
Test name
Test status
Simulation time 156628413 ps
CPU time 0.89 seconds
Started Aug 02 05:31:12 PM PDT 24
Finished Aug 02 05:31:13 PM PDT 24
Peak memory 207400 kb
Host smart-07ed7363-0ef6-4afb-897f-95c2af108206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31375
6320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.313756320
Directory /workspace/23.usbdev_link_in_err/latest


Test location /workspace/coverage/default/23.usbdev_link_resume.3420897338
Short name T1221
Test name
Test status
Simulation time 32258344473 ps
CPU time 46.43 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 207680 kb
Host smart-68e56129-921d-41f2-9e39-2aba0a27d854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34208
97338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3420897338
Directory /workspace/23.usbdev_link_resume/latest


Test location /workspace/coverage/default/23.usbdev_link_suspend.2104655966
Short name T317
Test name
Test status
Simulation time 9985173952 ps
CPU time 12.46 seconds
Started Aug 02 05:31:16 PM PDT 24
Finished Aug 02 05:31:28 PM PDT 24
Peak memory 207624 kb
Host smart-c8f40820-b241-4da4-bca2-92e6d59e0bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21046
55966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.2104655966
Directory /workspace/23.usbdev_link_suspend/latest


Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1125830670
Short name T577
Test name
Test status
Simulation time 4764930420 ps
CPU time 135.4 seconds
Started Aug 02 05:31:14 PM PDT 24
Finished Aug 02 05:33:30 PM PDT 24
Peak memory 215880 kb
Host smart-784ea821-2106-4dad-bc3f-4e10f0d74573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11258
30670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1125830670
Directory /workspace/23.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1646087610
Short name T2059
Test name
Test status
Simulation time 1649252969 ps
CPU time 12.04 seconds
Started Aug 02 05:31:07 PM PDT 24
Finished Aug 02 05:31:19 PM PDT 24
Peak memory 207564 kb
Host smart-31d660d2-7f1d-49b4-8d44-a5ebb7cd2dd3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1646087610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1646087610
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.3187255767
Short name T1900
Test name
Test status
Simulation time 275019751 ps
CPU time 1.02 seconds
Started Aug 02 05:31:43 PM PDT 24
Finished Aug 02 05:31:44 PM PDT 24
Peak memory 207216 kb
Host smart-26d7395f-4566-41f4-8fa9-1514c72fd598
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3187255767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.3187255767
Directory /workspace/23.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.3524723800
Short name T2968
Test name
Test status
Simulation time 232948090 ps
CPU time 0.97 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:31:42 PM PDT 24
Peak memory 207208 kb
Host smart-7db403f2-fc05-479d-bb99-c1169d20799f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35247
23800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.3524723800
Directory /workspace/23.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_max_non_iso_usb_traffic.932735603
Short name T1135
Test name
Test status
Simulation time 2174583855 ps
CPU time 62.9 seconds
Started Aug 02 05:31:25 PM PDT 24
Finished Aug 02 05:32:28 PM PDT 24
Peak memory 215848 kb
Host smart-fb0ed572-b81e-41a8-b195-ef7aad6c7aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93273
5603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_non_iso_usb_traffic.932735603
Directory /workspace/23.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2457329671
Short name T887
Test name
Test status
Simulation time 2290199316 ps
CPU time 23.22 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:53 PM PDT 24
Peak memory 217404 kb
Host smart-872bc4da-af55-41f8-a092-720f93ed7817
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2457329671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2457329671
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2753521987
Short name T1829
Test name
Test status
Simulation time 162581574 ps
CPU time 0.87 seconds
Started Aug 02 05:31:33 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207364 kb
Host smart-34aaafb0-7daf-4949-a16a-7ec39403c11d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2753521987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2753521987
Directory /workspace/23.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3141340503
Short name T2262
Test name
Test status
Simulation time 172803624 ps
CPU time 0.82 seconds
Started Aug 02 05:31:14 PM PDT 24
Finished Aug 02 05:31:15 PM PDT 24
Peak memory 207432 kb
Host smart-fea74fe0-dc6a-451f-9aad-b5122c1102eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31413
40503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3141340503
Directory /workspace/23.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_nak_trans.857207974
Short name T2397
Test name
Test status
Simulation time 202812829 ps
CPU time 0.9 seconds
Started Aug 02 05:31:25 PM PDT 24
Finished Aug 02 05:31:26 PM PDT 24
Peak memory 207408 kb
Host smart-3d30907f-5c07-4adc-8c32-d674d50ac221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85720
7974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.857207974
Directory /workspace/23.usbdev_nak_trans/latest


Test location /workspace/coverage/default/23.usbdev_out_iso.4010254517
Short name T2899
Test name
Test status
Simulation time 160121165 ps
CPU time 0.89 seconds
Started Aug 02 05:31:31 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207384 kb
Host smart-b21cf5d4-4c42-4782-a8ef-8a8321cb0caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40102
54517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.4010254517
Directory /workspace/23.usbdev_out_iso/latest


Test location /workspace/coverage/default/23.usbdev_out_stall.3865639755
Short name T2562
Test name
Test status
Simulation time 195974320 ps
CPU time 0.94 seconds
Started Aug 02 05:31:22 PM PDT 24
Finished Aug 02 05:31:23 PM PDT 24
Peak memory 207468 kb
Host smart-fcfcad67-62df-45c0-8f39-14f7139f43f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38656
39755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.3865639755
Directory /workspace/23.usbdev_out_stall/latest


Test location /workspace/coverage/default/23.usbdev_out_trans_nak.1439693386
Short name T343
Test name
Test status
Simulation time 183321685 ps
CPU time 0.93 seconds
Started Aug 02 05:31:21 PM PDT 24
Finished Aug 02 05:31:22 PM PDT 24
Peak memory 207316 kb
Host smart-6394db2f-e738-4b90-bf31-1901f95b52bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14396
93386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.1439693386
Directory /workspace/23.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2107133583
Short name T1904
Test name
Test status
Simulation time 179332857 ps
CPU time 0.9 seconds
Started Aug 02 05:31:13 PM PDT 24
Finished Aug 02 05:31:14 PM PDT 24
Peak memory 207380 kb
Host smart-98d1dc87-d2fd-476b-b2dd-a69a257db828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21071
33583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2107133583
Directory /workspace/23.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.1483931654
Short name T1346
Test name
Test status
Simulation time 261849642 ps
CPU time 1.01 seconds
Started Aug 02 05:31:27 PM PDT 24
Finished Aug 02 05:31:28 PM PDT 24
Peak memory 207416 kb
Host smart-43da3f2f-69a2-442a-ac9b-c2dc72dcc766
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1483931654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.1483931654
Directory /workspace/23.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.42705609
Short name T2242
Test name
Test status
Simulation time 144127489 ps
CPU time 0.83 seconds
Started Aug 02 05:31:23 PM PDT 24
Finished Aug 02 05:31:24 PM PDT 24
Peak memory 207364 kb
Host smart-0e221a90-4ad4-4221-9855-8a3d19ccea89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42705
609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.42705609
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2010689366
Short name T1769
Test name
Test status
Simulation time 30823182 ps
CPU time 0.69 seconds
Started Aug 02 05:31:46 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207324 kb
Host smart-4d7e7069-2c9e-4217-bf40-39a489da5c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20106
89366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2010689366
Directory /workspace/23.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2254594629
Short name T2089
Test name
Test status
Simulation time 11888576270 ps
CPU time 30.89 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:42 PM PDT 24
Peak memory 215964 kb
Host smart-671c00ce-28d7-4465-abfc-5574bf7074ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22545
94629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2254594629
Directory /workspace/23.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/23.usbdev_pkt_received.3345120734
Short name T327
Test name
Test status
Simulation time 173593586 ps
CPU time 0.93 seconds
Started Aug 02 05:31:13 PM PDT 24
Finished Aug 02 05:31:15 PM PDT 24
Peak memory 207408 kb
Host smart-57fec783-c9ff-42df-9587-91686ed881c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33451
20734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.3345120734
Directory /workspace/23.usbdev_pkt_received/latest


Test location /workspace/coverage/default/23.usbdev_pkt_sent.3434836609
Short name T2148
Test name
Test status
Simulation time 180342201 ps
CPU time 0.9 seconds
Started Aug 02 05:31:24 PM PDT 24
Finished Aug 02 05:31:25 PM PDT 24
Peak memory 207316 kb
Host smart-b99a3d6a-1788-432e-9a23-836f615de6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34348
36609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.3434836609
Directory /workspace/23.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1032344000
Short name T1239
Test name
Test status
Simulation time 167524234 ps
CPU time 0.82 seconds
Started Aug 02 05:31:21 PM PDT 24
Finished Aug 02 05:31:22 PM PDT 24
Peak memory 207412 kb
Host smart-b6fdb078-2d82-4a24-a00f-d3e67cd3f0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10323
44000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1032344000
Directory /workspace/23.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.1439461456
Short name T1528
Test name
Test status
Simulation time 163373421 ps
CPU time 0.86 seconds
Started Aug 02 05:31:14 PM PDT 24
Finished Aug 02 05:31:15 PM PDT 24
Peak memory 207392 kb
Host smart-dad6717d-3653-43e3-a3be-ad8365a14dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14394
61456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.1439461456
Directory /workspace/23.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/23.usbdev_rx_crc_err.4271508247
Short name T1987
Test name
Test status
Simulation time 170000629 ps
CPU time 0.86 seconds
Started Aug 02 05:31:24 PM PDT 24
Finished Aug 02 05:31:25 PM PDT 24
Peak memory 207356 kb
Host smart-26758077-7c8d-4323-955f-e34814949883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42715
08247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.4271508247
Directory /workspace/23.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/23.usbdev_rx_full.397796586
Short name T817
Test name
Test status
Simulation time 250134223 ps
CPU time 1.08 seconds
Started Aug 02 05:31:13 PM PDT 24
Finished Aug 02 05:31:15 PM PDT 24
Peak memory 207392 kb
Host smart-5f1be455-353c-4ca8-9abb-d978395d5a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39779
6586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_full.397796586
Directory /workspace/23.usbdev_rx_full/latest


Test location /workspace/coverage/default/23.usbdev_setup_stage.1145567167
Short name T1966
Test name
Test status
Simulation time 182436497 ps
CPU time 0.82 seconds
Started Aug 02 05:31:26 PM PDT 24
Finished Aug 02 05:31:27 PM PDT 24
Peak memory 207400 kb
Host smart-2178e74a-f0ce-43d2-a462-609e82f45baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11455
67167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1145567167
Directory /workspace/23.usbdev_setup_stage/latest


Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.2757978210
Short name T1504
Test name
Test status
Simulation time 191790906 ps
CPU time 0.87 seconds
Started Aug 02 05:31:22 PM PDT 24
Finished Aug 02 05:31:23 PM PDT 24
Peak memory 207392 kb
Host smart-5ea0790b-80e7-4512-94dc-d0e4929ad8ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27579
78210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.2757978210
Directory /workspace/23.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/23.usbdev_smoke.3661676166
Short name T1932
Test name
Test status
Simulation time 204480145 ps
CPU time 0.93 seconds
Started Aug 02 05:31:29 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 207324 kb
Host smart-d597adfb-bafa-4ac8-a871-7046f99f076b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36616
76166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3661676166
Directory /workspace/23.usbdev_smoke/latest


Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.1657169465
Short name T588
Test name
Test status
Simulation time 2522544637 ps
CPU time 24.18 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:54 PM PDT 24
Peak memory 223972 kb
Host smart-88ce5b23-9421-4a30-bd54-82a75a3eec62
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1657169465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.1657169465
Directory /workspace/23.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.556389065
Short name T629
Test name
Test status
Simulation time 187033350 ps
CPU time 0.9 seconds
Started Aug 02 05:31:22 PM PDT 24
Finished Aug 02 05:31:23 PM PDT 24
Peak memory 207328 kb
Host smart-999114de-0979-4587-a15b-a2efe8ea537d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55638
9065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.556389065
Directory /workspace/23.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/23.usbdev_stall_trans.1175588305
Short name T259
Test name
Test status
Simulation time 188525016 ps
CPU time 0.86 seconds
Started Aug 02 05:31:22 PM PDT 24
Finished Aug 02 05:31:23 PM PDT 24
Peak memory 207388 kb
Host smart-753ecb67-2b1a-44f8-84c2-f72f7bc1d997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11755
88305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1175588305
Directory /workspace/23.usbdev_stall_trans/latest


Test location /workspace/coverage/default/23.usbdev_stream_len_max.976187732
Short name T1180
Test name
Test status
Simulation time 378782877 ps
CPU time 1.22 seconds
Started Aug 02 05:31:35 PM PDT 24
Finished Aug 02 05:31:36 PM PDT 24
Peak memory 207360 kb
Host smart-a9e615f8-2159-4624-bc5a-4a26aecd7012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97618
7732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.976187732
Directory /workspace/23.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/23.usbdev_streaming_out.240399925
Short name T981
Test name
Test status
Simulation time 2182935908 ps
CPU time 22.1 seconds
Started Aug 02 05:31:20 PM PDT 24
Finished Aug 02 05:31:43 PM PDT 24
Peak memory 215936 kb
Host smart-8f81ece3-8890-40c7-b00d-625a0eec9843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24039
9925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.240399925
Directory /workspace/23.usbdev_streaming_out/latest


Test location /workspace/coverage/default/23.usbdev_timeout_missing_host_handshake.722408931
Short name T927
Test name
Test status
Simulation time 673104506 ps
CPU time 4.98 seconds
Started Aug 02 05:31:16 PM PDT 24
Finished Aug 02 05:31:21 PM PDT 24
Peak memory 207596 kb
Host smart-e997dd09-924d-4ef0-b6c2-c75524844bde
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722408931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_timeout_missing_host
_handshake.722408931
Directory /workspace/23.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/24.usbdev_alert_test.1978648035
Short name T1753
Test name
Test status
Simulation time 48091984 ps
CPU time 0.64 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207540 kb
Host smart-cfa6629b-f649-4ab2-b418-595587b394b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1978648035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.1978648035
Directory /workspace/24.usbdev_alert_test/latest


Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.2581300507
Short name T2081
Test name
Test status
Simulation time 5909016150 ps
CPU time 8.37 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:20 PM PDT 24
Peak memory 215876 kb
Host smart-b07a1d5e-5550-4784-a0c1-2aa396b29789
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581300507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_disconnect.2581300507
Directory /workspace/24.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2210240995
Short name T1210
Test name
Test status
Simulation time 19797969750 ps
CPU time 21.03 seconds
Started Aug 02 05:31:26 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207680 kb
Host smart-753f7ba2-e16b-4dfc-9d88-d28c42082c51
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210240995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2210240995
Directory /workspace/24.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1782555393
Short name T2134
Test name
Test status
Simulation time 31005169152 ps
CPU time 36.88 seconds
Started Aug 02 05:31:15 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 207616 kb
Host smart-402211bb-04bb-4000-8f41-de3bddb8987a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782555393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_a
on_wake_resume.1782555393
Directory /workspace/24.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/24.usbdev_av_buffer.4260878654
Short name T2563
Test name
Test status
Simulation time 201155493 ps
CPU time 0.89 seconds
Started Aug 02 05:31:11 PM PDT 24
Finished Aug 02 05:31:12 PM PDT 24
Peak memory 207356 kb
Host smart-66ae7206-39e5-443a-a8a7-291f8d82ee94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42608
78654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.4260878654
Directory /workspace/24.usbdev_av_buffer/latest


Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2228542492
Short name T1214
Test name
Test status
Simulation time 138590247 ps
CPU time 0.8 seconds
Started Aug 02 05:31:14 PM PDT 24
Finished Aug 02 05:31:15 PM PDT 24
Peak memory 207400 kb
Host smart-6f957f68-004f-4eb7-ac16-fd5e04adcbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22285
42492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2228542492
Directory /workspace/24.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.1217766549
Short name T631
Test name
Test status
Simulation time 260058995 ps
CPU time 1.12 seconds
Started Aug 02 05:31:22 PM PDT 24
Finished Aug 02 05:31:23 PM PDT 24
Peak memory 207392 kb
Host smart-9a485fd4-4ace-468d-83ca-0d7bfa922177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12177
66549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.1217766549
Directory /workspace/24.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2437144384
Short name T2691
Test name
Test status
Simulation time 863412061 ps
CPU time 2.38 seconds
Started Aug 02 05:31:27 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 207600 kb
Host smart-4353b71b-0de6-41a8-8f7d-19269f2f9cff
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2437144384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2437144384
Directory /workspace/24.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/24.usbdev_device_address.3730531215
Short name T1935
Test name
Test status
Simulation time 44465485289 ps
CPU time 81.6 seconds
Started Aug 02 05:31:32 PM PDT 24
Finished Aug 02 05:32:54 PM PDT 24
Peak memory 207640 kb
Host smart-315633f0-16c0-488f-ae6b-9ad740106500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37305
31215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3730531215
Directory /workspace/24.usbdev_device_address/latest


Test location /workspace/coverage/default/24.usbdev_device_timeout.3026024468
Short name T2384
Test name
Test status
Simulation time 4297715712 ps
CPU time 28.08 seconds
Started Aug 02 05:31:35 PM PDT 24
Finished Aug 02 05:32:03 PM PDT 24
Peak memory 207596 kb
Host smart-ed4fb03e-085c-41af-8f93-81bbb787bf14
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026024468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_timeout.3026024468
Directory /workspace/24.usbdev_device_timeout/latest


Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2495256958
Short name T2653
Test name
Test status
Simulation time 875448115 ps
CPU time 1.84 seconds
Started Aug 02 05:31:12 PM PDT 24
Finished Aug 02 05:31:14 PM PDT 24
Peak memory 207336 kb
Host smart-fa7e2ac3-a610-4a6d-9560-49a60fa9c579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24952
56958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2495256958
Directory /workspace/24.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/24.usbdev_disconnected.1220324454
Short name T581
Test name
Test status
Simulation time 134008290 ps
CPU time 0.81 seconds
Started Aug 02 05:31:12 PM PDT 24
Finished Aug 02 05:31:13 PM PDT 24
Peak memory 207384 kb
Host smart-3e8a5946-e56e-4c93-bba8-d917c54338a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12203
24454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1220324454
Directory /workspace/24.usbdev_disconnected/latest


Test location /workspace/coverage/default/24.usbdev_enable.941396689
Short name T513
Test name
Test status
Simulation time 37443290 ps
CPU time 0.69 seconds
Started Aug 02 05:31:22 PM PDT 24
Finished Aug 02 05:31:23 PM PDT 24
Peak memory 207316 kb
Host smart-b386e7e0-e0a5-4635-8133-9c19f8654255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94139
6689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.941396689
Directory /workspace/24.usbdev_enable/latest


Test location /workspace/coverage/default/24.usbdev_endpoint_access.3275742211
Short name T1576
Test name
Test status
Simulation time 1033519405 ps
CPU time 2.54 seconds
Started Aug 02 05:31:29 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207596 kb
Host smart-c408a3d1-782e-4540-8a8e-f20e335fd67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32757
42211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3275742211
Directory /workspace/24.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/24.usbdev_endpoint_types.3375018144
Short name T2880
Test name
Test status
Simulation time 310005175 ps
CPU time 1.07 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207180 kb
Host smart-b6d1f1d7-f6f1-4376-a5d9-8b421e3c8246
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3375018144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_types.3375018144
Directory /workspace/24.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/24.usbdev_fifo_rst.693150857
Short name T3026
Test name
Test status
Simulation time 239525127 ps
CPU time 1.55 seconds
Started Aug 02 05:31:15 PM PDT 24
Finished Aug 02 05:31:16 PM PDT 24
Peak memory 207504 kb
Host smart-0f22de22-aa48-44ca-908b-f3819a2889f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69315
0857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.693150857
Directory /workspace/24.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/24.usbdev_in_iso.1709557234
Short name T2847
Test name
Test status
Simulation time 154268588 ps
CPU time 0.87 seconds
Started Aug 02 05:31:24 PM PDT 24
Finished Aug 02 05:31:25 PM PDT 24
Peak memory 207404 kb
Host smart-34c7db7e-3607-408b-91a0-cabb0f6e2150
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1709557234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1709557234
Directory /workspace/24.usbdev_in_iso/latest


Test location /workspace/coverage/default/24.usbdev_in_stall.1295009504
Short name T1512
Test name
Test status
Simulation time 132791543 ps
CPU time 0.81 seconds
Started Aug 02 05:31:12 PM PDT 24
Finished Aug 02 05:31:13 PM PDT 24
Peak memory 207352 kb
Host smart-f696a240-32b2-4199-ad49-bf33fd37cb2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12950
09504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1295009504
Directory /workspace/24.usbdev_in_stall/latest


Test location /workspace/coverage/default/24.usbdev_in_trans.3785857954
Short name T1428
Test name
Test status
Simulation time 206312633 ps
CPU time 0.98 seconds
Started Aug 02 05:31:23 PM PDT 24
Finished Aug 02 05:31:24 PM PDT 24
Peak memory 207396 kb
Host smart-f4414653-b5ac-45fd-8b71-ceb5246b43e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37858
57954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3785857954
Directory /workspace/24.usbdev_in_trans/latest


Test location /workspace/coverage/default/24.usbdev_invalid_sync.3606356486
Short name T1404
Test name
Test status
Simulation time 3857772393 ps
CPU time 38.09 seconds
Started Aug 02 05:31:13 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 223936 kb
Host smart-3263b33a-4f8b-4c83-ba40-f350ab87c563
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3606356486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.3606356486
Directory /workspace/24.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/24.usbdev_iso_retraction.1521257522
Short name T2535
Test name
Test status
Simulation time 8117700553 ps
CPU time 95.7 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:33:12 PM PDT 24
Peak memory 207684 kb
Host smart-284c08ce-a7cc-4f60-b017-3855cf3ac71f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1521257522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.1521257522
Directory /workspace/24.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/24.usbdev_link_in_err.3520280068
Short name T1285
Test name
Test status
Simulation time 237139849 ps
CPU time 1.04 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:31:36 PM PDT 24
Peak memory 207208 kb
Host smart-a9df0772-70b6-4c51-a096-33116e313032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35202
80068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.3520280068
Directory /workspace/24.usbdev_link_in_err/latest


Test location /workspace/coverage/default/24.usbdev_link_resume.74183179
Short name T67
Test name
Test status
Simulation time 10814697716 ps
CPU time 12.54 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:43 PM PDT 24
Peak memory 207620 kb
Host smart-45a28014-01a6-4360-967a-decbbed62a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74183
179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.74183179
Directory /workspace/24.usbdev_link_resume/latest


Test location /workspace/coverage/default/24.usbdev_link_suspend.2225824137
Short name T2507
Test name
Test status
Simulation time 9037669584 ps
CPU time 12.57 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207684 kb
Host smart-03b3fd5a-1047-4ce8-be89-4908b1f77b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22258
24137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.2225824137
Directory /workspace/24.usbdev_link_suspend/latest


Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1111330892
Short name T731
Test name
Test status
Simulation time 3948813023 ps
CPU time 111.68 seconds
Started Aug 02 05:31:26 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 224064 kb
Host smart-fc4b2081-993e-44fd-8e3f-f31284e4e24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11113
30892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1111330892
Directory /workspace/24.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.3460308684
Short name T106
Test name
Test status
Simulation time 2279219285 ps
CPU time 17.31 seconds
Started Aug 02 05:31:24 PM PDT 24
Finished Aug 02 05:31:42 PM PDT 24
Peak memory 207660 kb
Host smart-5b5c65b3-72b8-45fb-bb86-2561dfd4d408
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3460308684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.3460308684
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1183451970
Short name T2660
Test name
Test status
Simulation time 277815370 ps
CPU time 1.02 seconds
Started Aug 02 05:31:27 PM PDT 24
Finished Aug 02 05:31:28 PM PDT 24
Peak memory 207376 kb
Host smart-ff2bf19d-9998-4063-9042-101a49a05dcb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1183451970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1183451970
Directory /workspace/24.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.1920882424
Short name T591
Test name
Test status
Simulation time 189656846 ps
CPU time 0.95 seconds
Started Aug 02 05:31:46 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207392 kb
Host smart-8ca83fc3-be37-43ad-90c8-b3e6b9c3a2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19208
82424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.1920882424
Directory /workspace/24.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_max_non_iso_usb_traffic.887927147
Short name T766
Test name
Test status
Simulation time 1907546173 ps
CPU time 18.79 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:55 PM PDT 24
Peak memory 223940 kb
Host smart-8d317780-c945-45d7-9acd-c0102ceb5cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88792
7147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_non_iso_usb_traffic.887927147
Directory /workspace/24.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3759622796
Short name T992
Test name
Test status
Simulation time 1725929900 ps
CPU time 47.04 seconds
Started Aug 02 05:31:26 PM PDT 24
Finished Aug 02 05:32:13 PM PDT 24
Peak memory 215728 kb
Host smart-f27f8446-0db2-442d-a818-b17fd12eb80f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3759622796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3759622796
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3294273439
Short name T2357
Test name
Test status
Simulation time 167888902 ps
CPU time 0.92 seconds
Started Aug 02 05:31:29 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 207380 kb
Host smart-d0f2b04b-9110-4f4d-bca7-3f96a78b2064
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3294273439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3294273439
Directory /workspace/24.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2268270106
Short name T2304
Test name
Test status
Simulation time 165042761 ps
CPU time 0.84 seconds
Started Aug 02 05:31:31 PM PDT 24
Finished Aug 02 05:31:32 PM PDT 24
Peak memory 207360 kb
Host smart-6dc928f1-4e64-42cf-b2c8-62959728b46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22682
70106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2268270106
Directory /workspace/24.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_nak_trans.303630124
Short name T156
Test name
Test status
Simulation time 212176451 ps
CPU time 1.07 seconds
Started Aug 02 05:31:23 PM PDT 24
Finished Aug 02 05:31:24 PM PDT 24
Peak memory 207400 kb
Host smart-585330e7-9c18-4d42-841a-4874c0f4e412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30363
0124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.303630124
Directory /workspace/24.usbdev_nak_trans/latest


Test location /workspace/coverage/default/24.usbdev_out_iso.3832956228
Short name T2505
Test name
Test status
Simulation time 170560381 ps
CPU time 0.92 seconds
Started Aug 02 05:31:24 PM PDT 24
Finished Aug 02 05:31:25 PM PDT 24
Peak memory 207360 kb
Host smart-a583c196-11a2-4b18-9a71-0539fe6954fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38329
56228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.3832956228
Directory /workspace/24.usbdev_out_iso/latest


Test location /workspace/coverage/default/24.usbdev_out_stall.2057430214
Short name T759
Test name
Test status
Simulation time 198205417 ps
CPU time 0.92 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:31:42 PM PDT 24
Peak memory 207352 kb
Host smart-c7e4874e-99bb-4f92-bf7d-69c4720dda2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20574
30214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.2057430214
Directory /workspace/24.usbdev_out_stall/latest


Test location /workspace/coverage/default/24.usbdev_out_trans_nak.348847760
Short name T1907
Test name
Test status
Simulation time 172259145 ps
CPU time 0.85 seconds
Started Aug 02 05:31:27 PM PDT 24
Finished Aug 02 05:31:28 PM PDT 24
Peak memory 207300 kb
Host smart-ff7891ad-b711-4e4b-8d9e-df4c531f1a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34884
7760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.348847760
Directory /workspace/24.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3697528430
Short name T189
Test name
Test status
Simulation time 155062386 ps
CPU time 0.86 seconds
Started Aug 02 05:31:33 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 207412 kb
Host smart-4a9cf753-4bd1-4886-a236-43ad15bd9424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36975
28430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3697528430
Directory /workspace/24.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1468426583
Short name T1819
Test name
Test status
Simulation time 224849751 ps
CPU time 1.03 seconds
Started Aug 02 05:31:31 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207424 kb
Host smart-284e0843-c2e5-401d-8ac1-7bcbd9b06baa
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1468426583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1468426583
Directory /workspace/24.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.115711261
Short name T2938
Test name
Test status
Simulation time 153033876 ps
CPU time 0.88 seconds
Started Aug 02 05:31:31 PM PDT 24
Finished Aug 02 05:31:32 PM PDT 24
Peak memory 207352 kb
Host smart-2e314b3b-b81d-460d-bbc6-96531a8d767c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11571
1261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.115711261
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2379460562
Short name T3102
Test name
Test status
Simulation time 44960794 ps
CPU time 0.71 seconds
Started Aug 02 05:31:28 PM PDT 24
Finished Aug 02 05:31:29 PM PDT 24
Peak memory 207340 kb
Host smart-1ed74b8a-00b3-4af4-850c-03dd99da4238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23794
60562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2379460562
Directory /workspace/24.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/24.usbdev_pkt_buffer.2499522314
Short name T266
Test name
Test status
Simulation time 14767645515 ps
CPU time 36.71 seconds
Started Aug 02 05:31:28 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 224048 kb
Host smart-be8f22b1-a107-41de-96dd-d4d262c8e639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24995
22314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.2499522314
Directory /workspace/24.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/24.usbdev_pkt_received.1460744240
Short name T1851
Test name
Test status
Simulation time 149881777 ps
CPU time 0.85 seconds
Started Aug 02 05:31:29 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 207384 kb
Host smart-39ffb759-3e3f-4aed-bf83-a6d3662705de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14607
44240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1460744240
Directory /workspace/24.usbdev_pkt_received/latest


Test location /workspace/coverage/default/24.usbdev_pkt_sent.374522321
Short name T555
Test name
Test status
Simulation time 198653543 ps
CPU time 0.95 seconds
Started Aug 02 05:31:24 PM PDT 24
Finished Aug 02 05:31:26 PM PDT 24
Peak memory 207336 kb
Host smart-9cab5915-367e-49d9-84b5-7257f2982815
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37452
2321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.374522321
Directory /workspace/24.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.1910178825
Short name T2268
Test name
Test status
Simulation time 177524764 ps
CPU time 0.87 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207416 kb
Host smart-8bd4eb5d-bbcd-4272-9266-dc4808d96d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19101
78825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.1910178825
Directory /workspace/24.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.2469959355
Short name T1742
Test name
Test status
Simulation time 200807105 ps
CPU time 0.97 seconds
Started Aug 02 05:31:28 PM PDT 24
Finished Aug 02 05:31:29 PM PDT 24
Peak memory 207404 kb
Host smart-44feb939-d229-4675-9a0d-f3ef26c27203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24699
59355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.2469959355
Directory /workspace/24.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/24.usbdev_rx_crc_err.431536150
Short name T566
Test name
Test status
Simulation time 188840861 ps
CPU time 0.88 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207380 kb
Host smart-7f12e826-61a3-4008-853b-f9d7a981417b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43153
6150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.431536150
Directory /workspace/24.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/24.usbdev_rx_full.99672871
Short name T1581
Test name
Test status
Simulation time 273473565 ps
CPU time 1.07 seconds
Started Aug 02 05:31:32 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207412 kb
Host smart-0b5f7583-9be8-4d2b-afba-163db17dcbbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99672
871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_full.99672871
Directory /workspace/24.usbdev_rx_full/latest


Test location /workspace/coverage/default/24.usbdev_setup_stage.3307263991
Short name T1071
Test name
Test status
Simulation time 143869193 ps
CPU time 0.87 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207352 kb
Host smart-79670bc9-ad35-4a6f-bdd1-2d720cf1a549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33072
63991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3307263991
Directory /workspace/24.usbdev_setup_stage/latest


Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3289119111
Short name T1765
Test name
Test status
Simulation time 150359488 ps
CPU time 0.83 seconds
Started Aug 02 05:31:27 PM PDT 24
Finished Aug 02 05:31:29 PM PDT 24
Peak memory 207408 kb
Host smart-f545da3d-1ecc-4939-8347-93cfcf3d61f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32891
19111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3289119111
Directory /workspace/24.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/24.usbdev_smoke.3890129895
Short name T3085
Test name
Test status
Simulation time 222124307 ps
CPU time 0.98 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:31:42 PM PDT 24
Peak memory 207360 kb
Host smart-2e9aa984-28cb-45f8-960b-9a2d8765b83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38901
29895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3890129895
Directory /workspace/24.usbdev_smoke/latest


Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1185725142
Short name T2408
Test name
Test status
Simulation time 1850174066 ps
CPU time 18.41 seconds
Started Aug 02 05:31:27 PM PDT 24
Finished Aug 02 05:31:46 PM PDT 24
Peak memory 223964 kb
Host smart-5940f437-53d6-411b-9e2f-3cd7cfd23232
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1185725142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1185725142
Directory /workspace/24.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.389579847
Short name T2289
Test name
Test status
Simulation time 156292014 ps
CPU time 0.9 seconds
Started Aug 02 05:31:23 PM PDT 24
Finished Aug 02 05:31:24 PM PDT 24
Peak memory 207384 kb
Host smart-b1fa8c27-65ce-4742-844c-6c1fd1634711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38957
9847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.389579847
Directory /workspace/24.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/24.usbdev_stall_trans.2044479144
Short name T2891
Test name
Test status
Simulation time 229402238 ps
CPU time 0.97 seconds
Started Aug 02 05:31:31 PM PDT 24
Finished Aug 02 05:31:32 PM PDT 24
Peak memory 207412 kb
Host smart-c5d8f083-f00b-43c6-93d6-ff38084dcf71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20444
79144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2044479144
Directory /workspace/24.usbdev_stall_trans/latest


Test location /workspace/coverage/default/24.usbdev_stream_len_max.3938713172
Short name T1842
Test name
Test status
Simulation time 928959233 ps
CPU time 2.25 seconds
Started Aug 02 05:31:28 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 207536 kb
Host smart-ffe005c1-0340-4fc5-b016-3455b05aa550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39387
13172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3938713172
Directory /workspace/24.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/24.usbdev_streaming_out.3153044507
Short name T2969
Test name
Test status
Simulation time 1967677795 ps
CPU time 15.17 seconds
Started Aug 02 05:31:27 PM PDT 24
Finished Aug 02 05:31:43 PM PDT 24
Peak memory 207616 kb
Host smart-4ed634f7-4b53-4a9e-9bcf-92899f8f3134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31530
44507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.3153044507
Directory /workspace/24.usbdev_streaming_out/latest


Test location /workspace/coverage/default/24.usbdev_timeout_missing_host_handshake.96637363
Short name T2845
Test name
Test status
Simulation time 441809870 ps
CPU time 7.71 seconds
Started Aug 02 05:31:20 PM PDT 24
Finished Aug 02 05:31:27 PM PDT 24
Peak memory 207532 kb
Host smart-99ca4f18-4ec2-4850-876a-57da93d3ca86
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96637363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_timeout_missing_host_
handshake.96637363
Directory /workspace/24.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/25.usbdev_alert_test.2494956137
Short name T2087
Test name
Test status
Simulation time 44652627 ps
CPU time 0.67 seconds
Started Aug 02 05:31:33 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 207472 kb
Host smart-7c562f0e-a975-43ed-81ec-8ae74456e444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2494956137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.2494956137
Directory /workspace/25.usbdev_alert_test/latest


Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.3899169510
Short name T971
Test name
Test status
Simulation time 4124263999 ps
CPU time 5.75 seconds
Started Aug 02 05:31:32 PM PDT 24
Finished Aug 02 05:31:38 PM PDT 24
Peak memory 215768 kb
Host smart-cbfe174d-4b64-4c6d-9074-9126730d3e54
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899169510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_disconnect.3899169510
Directory /workspace/25.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.2022569222
Short name T1462
Test name
Test status
Simulation time 19394384324 ps
CPU time 21.62 seconds
Started Aug 02 05:31:26 PM PDT 24
Finished Aug 02 05:31:48 PM PDT 24
Peak memory 207648 kb
Host smart-032e2022-cb4b-41c0-aa46-1584ef4fb898
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022569222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.2022569222
Directory /workspace/25.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.3354604832
Short name T7
Test name
Test status
Simulation time 30973143037 ps
CPU time 46.4 seconds
Started Aug 02 05:31:28 PM PDT 24
Finished Aug 02 05:32:15 PM PDT 24
Peak memory 207696 kb
Host smart-4cb7a95b-da63-4b26-b6fd-266b80367e90
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354604832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_a
on_wake_resume.3354604832
Directory /workspace/25.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/25.usbdev_av_buffer.2231748331
Short name T602
Test name
Test status
Simulation time 150958207 ps
CPU time 0.82 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207408 kb
Host smart-628b544f-2d9e-4f93-8f18-b2812d6c7c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22317
48331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2231748331
Directory /workspace/25.usbdev_av_buffer/latest


Test location /workspace/coverage/default/25.usbdev_bitstuff_err.2346713207
Short name T995
Test name
Test status
Simulation time 167984356 ps
CPU time 0.87 seconds
Started Aug 02 05:31:48 PM PDT 24
Finished Aug 02 05:31:49 PM PDT 24
Peak memory 207336 kb
Host smart-107a6521-77c6-4242-9e1e-60c71560adc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23467
13207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.2346713207
Directory /workspace/25.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.2861597391
Short name T1366
Test name
Test status
Simulation time 529774661 ps
CPU time 1.71 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:38 PM PDT 24
Peak memory 207420 kb
Host smart-705c7d51-2756-4a5d-a4be-1d93b2f3d502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28615
97391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2861597391
Directory /workspace/25.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2851496012
Short name T1802
Test name
Test status
Simulation time 642570291 ps
CPU time 1.87 seconds
Started Aug 02 05:31:31 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207364 kb
Host smart-6b8a952a-9252-4888-acc3-8f39544862a6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2851496012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2851496012
Directory /workspace/25.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/25.usbdev_device_address.237314266
Short name T179
Test name
Test status
Simulation time 48671742307 ps
CPU time 73.84 seconds
Started Aug 02 05:31:29 PM PDT 24
Finished Aug 02 05:32:44 PM PDT 24
Peak memory 207672 kb
Host smart-ee415d18-a931-4c68-b2f7-26f502cb7a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23731
4266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.237314266
Directory /workspace/25.usbdev_device_address/latest


Test location /workspace/coverage/default/25.usbdev_device_timeout.3670416212
Short name T546
Test name
Test status
Simulation time 1033065753 ps
CPU time 22.12 seconds
Started Aug 02 05:31:32 PM PDT 24
Finished Aug 02 05:31:54 PM PDT 24
Peak memory 207520 kb
Host smart-3630b863-abb9-4931-bdd8-7e84a02ebae3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670416212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_timeout.3670416212
Directory /workspace/25.usbdev_device_timeout/latest


Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3410082589
Short name T1265
Test name
Test status
Simulation time 531741445 ps
CPU time 1.44 seconds
Started Aug 02 05:31:33 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 207372 kb
Host smart-ac5dbdcd-0bb0-4f46-aaac-1703e2627dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34100
82589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3410082589
Directory /workspace/25.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/25.usbdev_disconnected.258180820
Short name T256
Test name
Test status
Simulation time 151261947 ps
CPU time 0.83 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207384 kb
Host smart-a543b361-9843-496c-89c8-926841315028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25818
0820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.258180820
Directory /workspace/25.usbdev_disconnected/latest


Test location /workspace/coverage/default/25.usbdev_enable.4163885360
Short name T526
Test name
Test status
Simulation time 25688410 ps
CPU time 0.67 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207388 kb
Host smart-69c81481-09c2-4c07-a3c2-06f354ad6b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41638
85360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.4163885360
Directory /workspace/25.usbdev_enable/latest


Test location /workspace/coverage/default/25.usbdev_endpoint_access.3969230669
Short name T775
Test name
Test status
Simulation time 920222262 ps
CPU time 2.41 seconds
Started Aug 02 05:31:31 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 207636 kb
Host smart-aebb9935-c135-44ed-b3dd-d2488032caaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39692
30669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.3969230669
Directory /workspace/25.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/25.usbdev_fifo_rst.373333865
Short name T1095
Test name
Test status
Simulation time 278704246 ps
CPU time 2.01 seconds
Started Aug 02 05:31:26 PM PDT 24
Finished Aug 02 05:31:28 PM PDT 24
Peak memory 207612 kb
Host smart-51496f5f-c6ec-4672-bd2d-44a2f4acb6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37333
3865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.373333865
Directory /workspace/25.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/25.usbdev_in_iso.2567487350
Short name T980
Test name
Test status
Simulation time 179648221 ps
CPU time 1.01 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207388 kb
Host smart-98f73764-779a-4a52-b6ab-87ff3091b2b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2567487350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2567487350
Directory /workspace/25.usbdev_in_iso/latest


Test location /workspace/coverage/default/25.usbdev_in_stall.4161778357
Short name T3002
Test name
Test status
Simulation time 148817415 ps
CPU time 0.87 seconds
Started Aug 02 05:31:32 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207384 kb
Host smart-069c8f45-ee2c-4ecd-bd29-4d8cbd3e5a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617
78357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.4161778357
Directory /workspace/25.usbdev_in_stall/latest


Test location /workspace/coverage/default/25.usbdev_in_trans.2767801097
Short name T1524
Test name
Test status
Simulation time 150282662 ps
CPU time 0.86 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:31:43 PM PDT 24
Peak memory 207432 kb
Host smart-ac862bde-d653-43f3-93df-59aa904457be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27678
01097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2767801097
Directory /workspace/25.usbdev_in_trans/latest


Test location /workspace/coverage/default/25.usbdev_invalid_sync.1019379050
Short name T1496
Test name
Test status
Simulation time 4274339097 ps
CPU time 42.02 seconds
Started Aug 02 05:31:33 PM PDT 24
Finished Aug 02 05:32:15 PM PDT 24
Peak memory 217692 kb
Host smart-0c52d775-5f4d-4c01-8343-bdd2edd9f3d8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1019379050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1019379050
Directory /workspace/25.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/25.usbdev_iso_retraction.2379615803
Short name T857
Test name
Test status
Simulation time 4708100484 ps
CPU time 34.21 seconds
Started Aug 02 05:31:33 PM PDT 24
Finished Aug 02 05:32:08 PM PDT 24
Peak memory 207652 kb
Host smart-fc4acec4-cb17-4cb4-af16-f242006505eb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2379615803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.2379615803
Directory /workspace/25.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/25.usbdev_link_in_err.1749513365
Short name T3106
Test name
Test status
Simulation time 228618862 ps
CPU time 1.02 seconds
Started Aug 02 05:31:39 PM PDT 24
Finished Aug 02 05:31:40 PM PDT 24
Peak memory 207404 kb
Host smart-4b1359c9-455f-406f-8b75-cd554cc12568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17495
13365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1749513365
Directory /workspace/25.usbdev_link_in_err/latest


Test location /workspace/coverage/default/25.usbdev_link_resume.4260569362
Short name T1236
Test name
Test status
Simulation time 11634738894 ps
CPU time 19.07 seconds
Started Aug 02 05:31:44 PM PDT 24
Finished Aug 02 05:32:03 PM PDT 24
Peak memory 207700 kb
Host smart-1714829a-3fe6-438a-ad4c-e79e074733cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42605
69362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.4260569362
Directory /workspace/25.usbdev_link_resume/latest


Test location /workspace/coverage/default/25.usbdev_link_suspend.1999289568
Short name T2973
Test name
Test status
Simulation time 10558115036 ps
CPU time 15.23 seconds
Started Aug 02 05:31:42 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 207592 kb
Host smart-c2810677-0d70-469e-ab12-35389da48d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19992
89568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1999289568
Directory /workspace/25.usbdev_link_suspend/latest


Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2539434845
Short name T1997
Test name
Test status
Simulation time 4771402610 ps
CPU time 45.28 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:32:19 PM PDT 24
Peak memory 217380 kb
Host smart-094560d7-f208-4b16-aed6-4c46cf9dfa6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25394
34845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2539434845
Directory /workspace/25.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.3193004369
Short name T2084
Test name
Test status
Simulation time 3978447375 ps
CPU time 115.38 seconds
Started Aug 02 05:31:26 PM PDT 24
Finished Aug 02 05:33:22 PM PDT 24
Peak memory 217240 kb
Host smart-fdff4289-e919-490b-ad8e-541dfeaf84a6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3193004369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.3193004369
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.259045185
Short name T1800
Test name
Test status
Simulation time 263773643 ps
CPU time 1.07 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:31:42 PM PDT 24
Peak memory 207408 kb
Host smart-8c4f4659-8174-4ced-8b10-41d0dd6641d4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=259045185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.259045185
Directory /workspace/25.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1323907793
Short name T2974
Test name
Test status
Simulation time 216629468 ps
CPU time 0.99 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 207356 kb
Host smart-a265ca53-2de9-4c07-9fd2-04e5e7e69985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13239
07793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1323907793
Directory /workspace/25.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1736534212
Short name T1013
Test name
Test status
Simulation time 3422818276 ps
CPU time 98.93 seconds
Started Aug 02 05:31:48 PM PDT 24
Finished Aug 02 05:33:27 PM PDT 24
Peak memory 217168 kb
Host smart-d7c77b01-698b-4d07-a72a-a60c4aa31b6e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1736534212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1736534212
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2398336329
Short name T1406
Test name
Test status
Simulation time 163110956 ps
CPU time 0.86 seconds
Started Aug 02 05:31:52 PM PDT 24
Finished Aug 02 05:31:53 PM PDT 24
Peak memory 207420 kb
Host smart-fb6d154c-5bb4-48ac-b46c-a7dbe6f4c467
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2398336329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2398336329
Directory /workspace/25.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2826103570
Short name T2651
Test name
Test status
Simulation time 146532494 ps
CPU time 0.86 seconds
Started Aug 02 05:31:43 PM PDT 24
Finished Aug 02 05:31:44 PM PDT 24
Peak memory 207324 kb
Host smart-0cb966fd-d14d-4982-9ff1-298adc7872d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28261
03570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2826103570
Directory /workspace/25.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_nak_trans.2990290489
Short name T2380
Test name
Test status
Simulation time 223417793 ps
CPU time 0.99 seconds
Started Aug 02 05:31:48 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207360 kb
Host smart-c36fb858-5d5a-4c7c-95ce-426e9ab9aebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29902
90489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2990290489
Directory /workspace/25.usbdev_nak_trans/latest


Test location /workspace/coverage/default/25.usbdev_out_iso.3422226984
Short name T1311
Test name
Test status
Simulation time 186509162 ps
CPU time 0.97 seconds
Started Aug 02 05:31:50 PM PDT 24
Finished Aug 02 05:31:51 PM PDT 24
Peak memory 207408 kb
Host smart-266e291c-46ad-4273-ac28-8d576a75fed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34222
26984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3422226984
Directory /workspace/25.usbdev_out_iso/latest


Test location /workspace/coverage/default/25.usbdev_out_stall.836584615
Short name T936
Test name
Test status
Simulation time 171777175 ps
CPU time 0.85 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207400 kb
Host smart-06462a79-1772-461f-b812-a3f29499572a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83658
4615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.836584615
Directory /workspace/25.usbdev_out_stall/latest


Test location /workspace/coverage/default/25.usbdev_out_trans_nak.4124395359
Short name T1804
Test name
Test status
Simulation time 194180487 ps
CPU time 0.94 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:31:31 PM PDT 24
Peak memory 207384 kb
Host smart-428e2464-4976-4894-81a6-0e703e0a0cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41243
95359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.4124395359
Directory /workspace/25.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3401860401
Short name T193
Test name
Test status
Simulation time 154369540 ps
CPU time 0.84 seconds
Started Aug 02 05:31:46 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207420 kb
Host smart-d02010fe-b692-45c6-a066-1eaec096716f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34018
60401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3401860401
Directory /workspace/25.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.1261246167
Short name T2336
Test name
Test status
Simulation time 216580435 ps
CPU time 0.99 seconds
Started Aug 02 05:31:40 PM PDT 24
Finished Aug 02 05:31:41 PM PDT 24
Peak memory 207260 kb
Host smart-b0af7cde-42e7-40d1-997a-020cc24d8df4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1261246167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.1261246167
Directory /workspace/25.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3045244876
Short name T1389
Test name
Test status
Simulation time 159162889 ps
CPU time 0.83 seconds
Started Aug 02 05:31:31 PM PDT 24
Finished Aug 02 05:31:32 PM PDT 24
Peak memory 207412 kb
Host smart-a6eecb88-6e63-4555-b73e-5d5f13fcdc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30452
44876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3045244876
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2834252623
Short name T2359
Test name
Test status
Simulation time 28295712 ps
CPU time 0.67 seconds
Started Aug 02 05:31:49 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207348 kb
Host smart-a398f22c-e084-495d-9b24-e99319c3e1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28342
52623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2834252623
Directory /workspace/25.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/25.usbdev_pkt_buffer.3443370878
Short name T2947
Test name
Test status
Simulation time 18243837247 ps
CPU time 43.89 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:32:18 PM PDT 24
Peak memory 215880 kb
Host smart-656872bb-78bd-43ef-975e-cc7689fdd282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34433
70878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.3443370878
Directory /workspace/25.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/25.usbdev_pkt_received.2379172549
Short name T3055
Test name
Test status
Simulation time 180412080 ps
CPU time 0.86 seconds
Started Aug 02 05:31:38 PM PDT 24
Finished Aug 02 05:31:39 PM PDT 24
Peak memory 207356 kb
Host smart-c4b78d6a-3c29-4e16-bd48-64953e235f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23791
72549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.2379172549
Directory /workspace/25.usbdev_pkt_received/latest


Test location /workspace/coverage/default/25.usbdev_pkt_sent.3697565847
Short name T1770
Test name
Test status
Simulation time 173757797 ps
CPU time 0.88 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:31:35 PM PDT 24
Peak memory 207396 kb
Host smart-8bc2b2ed-31ef-4eee-9248-a3c382b0c0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36975
65847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3697565847
Directory /workspace/25.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.794039995
Short name T1324
Test name
Test status
Simulation time 201119907 ps
CPU time 0.93 seconds
Started Aug 02 05:31:33 PM PDT 24
Finished Aug 02 05:31:34 PM PDT 24
Peak memory 207416 kb
Host smart-7858df85-55d2-4b2c-9f07-a0e36cdb0fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79403
9995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.794039995
Directory /workspace/25.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2256978810
Short name T2272
Test name
Test status
Simulation time 193483543 ps
CPU time 0.94 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207380 kb
Host smart-96489c45-86ab-4c69-9762-13099c765325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22569
78810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2256978810
Directory /workspace/25.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1693725778
Short name T1906
Test name
Test status
Simulation time 144138065 ps
CPU time 0.8 seconds
Started Aug 02 05:31:46 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207324 kb
Host smart-2a7d464f-1b09-4a4b-afa5-d3cc24c8ebf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16937
25778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1693725778
Directory /workspace/25.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/25.usbdev_rx_full.1011494029
Short name T49
Test name
Test status
Simulation time 244635082 ps
CPU time 1.05 seconds
Started Aug 02 05:31:31 PM PDT 24
Finished Aug 02 05:31:32 PM PDT 24
Peak memory 207380 kb
Host smart-bac40eaa-a30b-4ff1-aa96-fff2c04d6c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10114
94029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_full.1011494029
Directory /workspace/25.usbdev_rx_full/latest


Test location /workspace/coverage/default/25.usbdev_setup_stage.82735970
Short name T1635
Test name
Test status
Simulation time 156769087 ps
CPU time 0.8 seconds
Started Aug 02 05:31:49 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207344 kb
Host smart-0b80dab1-7bc3-4fed-9ef1-96ccdb763d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82735
970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.82735970
Directory /workspace/25.usbdev_setup_stage/latest


Test location /workspace/coverage/default/25.usbdev_smoke.164205497
Short name T1171
Test name
Test status
Simulation time 216445870 ps
CPU time 1.02 seconds
Started Aug 02 05:31:32 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207372 kb
Host smart-b856f8e5-ff0a-46c1-b11e-29cd2a5f11ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16420
5497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.164205497
Directory /workspace/25.usbdev_smoke/latest


Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.1281633217
Short name T596
Test name
Test status
Simulation time 3564985164 ps
CPU time 26.56 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 224020 kb
Host smart-0f61ff94-dd8d-4f29-9ce7-c325ee01a142
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1281633217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.1281633217
Directory /workspace/25.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1306482228
Short name T1228
Test name
Test status
Simulation time 222614160 ps
CPU time 0.95 seconds
Started Aug 02 05:31:53 PM PDT 24
Finished Aug 02 05:31:54 PM PDT 24
Peak memory 207300 kb
Host smart-aec7f745-1369-4697-b380-b8ea6a6a6715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13064
82228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1306482228
Directory /workspace/25.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/25.usbdev_stall_trans.2324073762
Short name T2605
Test name
Test status
Simulation time 191418269 ps
CPU time 0.9 seconds
Started Aug 02 05:31:43 PM PDT 24
Finished Aug 02 05:31:44 PM PDT 24
Peak memory 207388 kb
Host smart-e21bfe8e-ac36-4db9-9602-e1af227c6c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23240
73762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2324073762
Directory /workspace/25.usbdev_stall_trans/latest


Test location /workspace/coverage/default/25.usbdev_stream_len_max.3307257273
Short name T1030
Test name
Test status
Simulation time 903687625 ps
CPU time 2.17 seconds
Started Aug 02 05:31:35 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207508 kb
Host smart-cdd5e6c7-7e5a-4ffb-bcba-e1c0e71b6446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33072
57273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3307257273
Directory /workspace/25.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/25.usbdev_streaming_out.71068737
Short name T2988
Test name
Test status
Simulation time 2133062629 ps
CPU time 60.97 seconds
Started Aug 02 05:31:33 PM PDT 24
Finished Aug 02 05:32:34 PM PDT 24
Peak memory 215744 kb
Host smart-5dd565a4-02c7-4816-a744-01b4b1d41671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71068
737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.71068737
Directory /workspace/25.usbdev_streaming_out/latest


Test location /workspace/coverage/default/25.usbdev_timeout_missing_host_handshake.2944373476
Short name T2481
Test name
Test status
Simulation time 5212333499 ps
CPU time 46.39 seconds
Started Aug 02 05:31:30 PM PDT 24
Finished Aug 02 05:32:17 PM PDT 24
Peak memory 207680 kb
Host smart-d7182288-4378-44c8-a77a-0ed711e2affd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944373476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_timeout_missing_hos
t_handshake.2944373476
Directory /workspace/25.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/26.usbdev_alert_test.644481945
Short name T2957
Test name
Test status
Simulation time 60963046 ps
CPU time 0.72 seconds
Started Aug 02 05:31:35 PM PDT 24
Finished Aug 02 05:31:35 PM PDT 24
Peak memory 207468 kb
Host smart-10954789-ec6c-40ce-a4bd-2020b2a2a84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=644481945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.644481945
Directory /workspace/26.usbdev_alert_test/latest


Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.148157955
Short name T11
Test name
Test status
Simulation time 9917124811 ps
CPU time 12.46 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:31:54 PM PDT 24
Peak memory 207704 kb
Host smart-7c60ccfd-9d8a-491f-83c7-96b43ee6b7fb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148157955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_ao
n_wake_disconnect.148157955
Directory /workspace/26.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2504487487
Short name T2422
Test name
Test status
Simulation time 15151452289 ps
CPU time 17.3 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 215844 kb
Host smart-398a6f7b-e70e-48c3-b389-a0519323a25f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504487487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2504487487
Directory /workspace/26.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.2914654375
Short name T2434
Test name
Test status
Simulation time 25939339294 ps
CPU time 30.77 seconds
Started Aug 02 05:31:27 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 215856 kb
Host smart-ceca2c29-5dfb-4838-8ff9-604abc204556
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914654375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_a
on_wake_resume.2914654375
Directory /workspace/26.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/26.usbdev_av_buffer.3631967335
Short name T1816
Test name
Test status
Simulation time 202186623 ps
CPU time 0.89 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:38 PM PDT 24
Peak memory 207432 kb
Host smart-62228c16-3876-4c65-a265-b228ec164ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36319
67335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3631967335
Directory /workspace/26.usbdev_av_buffer/latest


Test location /workspace/coverage/default/26.usbdev_bitstuff_err.466550202
Short name T1603
Test name
Test status
Simulation time 148047083 ps
CPU time 0.84 seconds
Started Aug 02 05:31:29 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 207396 kb
Host smart-750d3782-ea4e-4177-814c-26c2af50b0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46655
0202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.466550202
Directory /workspace/26.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3745219915
Short name T701
Test name
Test status
Simulation time 191354482 ps
CPU time 0.9 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:31:35 PM PDT 24
Peak memory 207348 kb
Host smart-7fda7fa2-93e7-482c-83dc-c9ae3924e94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37452
19915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3745219915
Directory /workspace/26.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3120627069
Short name T2254
Test name
Test status
Simulation time 390688272 ps
CPU time 1.3 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207392 kb
Host smart-8108e75b-dfae-4acc-aa71-02c21491a946
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3120627069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3120627069
Directory /workspace/26.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/26.usbdev_device_address.374015100
Short name T2643
Test name
Test status
Simulation time 34649335983 ps
CPU time 54.64 seconds
Started Aug 02 05:31:40 PM PDT 24
Finished Aug 02 05:32:35 PM PDT 24
Peak memory 207580 kb
Host smart-032b1922-3711-4385-b882-bad526a8dfdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37401
5100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.374015100
Directory /workspace/26.usbdev_device_address/latest


Test location /workspace/coverage/default/26.usbdev_device_timeout.1696433346
Short name T501
Test name
Test status
Simulation time 2481489545 ps
CPU time 21.86 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:32:13 PM PDT 24
Peak memory 207564 kb
Host smart-313e9f31-9d6f-4937-baa6-49ae9129408c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696433346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_timeout.1696433346
Directory /workspace/26.usbdev_device_timeout/latest


Test location /workspace/coverage/default/26.usbdev_disable_endpoint.283761573
Short name T2430
Test name
Test status
Simulation time 1018619234 ps
CPU time 2 seconds
Started Aug 02 05:31:34 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207316 kb
Host smart-3c71e69a-bf26-4256-8707-3273ce27616b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28376
1573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.283761573
Directory /workspace/26.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/26.usbdev_disconnected.2919865448
Short name T2466
Test name
Test status
Simulation time 184564061 ps
CPU time 0.86 seconds
Started Aug 02 05:31:32 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207372 kb
Host smart-a9e26275-87e9-4caf-91c1-f936cc191223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29198
65448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2919865448
Directory /workspace/26.usbdev_disconnected/latest


Test location /workspace/coverage/default/26.usbdev_enable.2256961378
Short name T2633
Test name
Test status
Simulation time 32854254 ps
CPU time 0.68 seconds
Started Aug 02 05:31:40 PM PDT 24
Finished Aug 02 05:31:41 PM PDT 24
Peak memory 207304 kb
Host smart-710dd853-ae4f-4030-b7c5-7d9fb1d65bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22569
61378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2256961378
Directory /workspace/26.usbdev_enable/latest


Test location /workspace/coverage/default/26.usbdev_endpoint_access.704895512
Short name T1755
Test name
Test status
Simulation time 742579991 ps
CPU time 2.12 seconds
Started Aug 02 05:31:37 PM PDT 24
Finished Aug 02 05:31:39 PM PDT 24
Peak memory 207620 kb
Host smart-de391bc2-7aa2-4ea5-8fc7-cca9d7180175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70489
5512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.704895512
Directory /workspace/26.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/26.usbdev_endpoint_types.2503717474
Short name T1519
Test name
Test status
Simulation time 210114146 ps
CPU time 0.93 seconds
Started Aug 02 05:31:42 PM PDT 24
Finished Aug 02 05:31:43 PM PDT 24
Peak memory 207348 kb
Host smart-3699b0f8-272c-4bcd-990b-e4d8d1142f24
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2503717474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_types.2503717474
Directory /workspace/26.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/26.usbdev_fifo_rst.3173027653
Short name T2168
Test name
Test status
Simulation time 291330486 ps
CPU time 1.92 seconds
Started Aug 02 05:31:48 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207524 kb
Host smart-95a5e5cb-5d94-4803-b2d4-947a94dea333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31730
27653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3173027653
Directory /workspace/26.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/26.usbdev_in_iso.3438349476
Short name T2617
Test name
Test status
Simulation time 165815150 ps
CPU time 0.86 seconds
Started Aug 02 05:31:29 PM PDT 24
Finished Aug 02 05:31:30 PM PDT 24
Peak memory 207364 kb
Host smart-4f78d248-1e14-4778-8583-995d59f51110
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3438349476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3438349476
Directory /workspace/26.usbdev_in_iso/latest


Test location /workspace/coverage/default/26.usbdev_in_stall.3693785234
Short name T2246
Test name
Test status
Simulation time 181273211 ps
CPU time 0.88 seconds
Started Aug 02 05:31:40 PM PDT 24
Finished Aug 02 05:31:41 PM PDT 24
Peak memory 207352 kb
Host smart-dd1cbb1e-b0cf-44c0-a421-4d0b768b18dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36937
85234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.3693785234
Directory /workspace/26.usbdev_in_stall/latest


Test location /workspace/coverage/default/26.usbdev_in_trans.2197209330
Short name T2003
Test name
Test status
Simulation time 170225066 ps
CPU time 0.88 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:31:42 PM PDT 24
Peak memory 207360 kb
Host smart-ec7b6be3-b7d2-43e0-a8ef-c1a86d033adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21972
09330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2197209330
Directory /workspace/26.usbdev_in_trans/latest


Test location /workspace/coverage/default/26.usbdev_invalid_sync.1808112248
Short name T2785
Test name
Test status
Simulation time 2942573189 ps
CPU time 81.09 seconds
Started Aug 02 05:31:43 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 215908 kb
Host smart-af6ced65-616e-43ed-9910-f8f0fa20e57f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1808112248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.1808112248
Directory /workspace/26.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/26.usbdev_iso_retraction.2536272986
Short name T1187
Test name
Test status
Simulation time 9935608645 ps
CPU time 70.6 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 207624 kb
Host smart-47dd2ce1-d25b-41f1-9215-0c915ff4cbd8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2536272986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.2536272986
Directory /workspace/26.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/26.usbdev_link_in_err.1813331142
Short name T3108
Test name
Test status
Simulation time 233279038 ps
CPU time 0.92 seconds
Started Aug 02 05:31:39 PM PDT 24
Finished Aug 02 05:31:40 PM PDT 24
Peak memory 207420 kb
Host smart-14105921-3264-42c0-9052-2017eef635e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18133
31142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1813331142
Directory /workspace/26.usbdev_link_in_err/latest


Test location /workspace/coverage/default/26.usbdev_link_resume.1455296820
Short name T1089
Test name
Test status
Simulation time 8778814043 ps
CPU time 14 seconds
Started Aug 02 05:31:46 PM PDT 24
Finished Aug 02 05:32:00 PM PDT 24
Peak memory 207664 kb
Host smart-ad777f25-37d2-4845-b0dd-6cf1ac2840c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14552
96820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.1455296820
Directory /workspace/26.usbdev_link_resume/latest


Test location /workspace/coverage/default/26.usbdev_link_suspend.2381835992
Short name T1600
Test name
Test status
Simulation time 11065491804 ps
CPU time 14.06 seconds
Started Aug 02 05:31:38 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 207720 kb
Host smart-08f580a4-2101-4531-91eb-f288011812b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23818
35992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2381835992
Directory /workspace/26.usbdev_link_suspend/latest


Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.2883502058
Short name T2572
Test name
Test status
Simulation time 2645520871 ps
CPU time 72.17 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:33:04 PM PDT 24
Peak memory 215800 kb
Host smart-9be31c4e-869b-4675-884a-9d70d88f3356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28835
02058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.2883502058
Directory /workspace/26.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1776676546
Short name T1942
Test name
Test status
Simulation time 2170499065 ps
CPU time 59.55 seconds
Started Aug 02 05:31:56 PM PDT 24
Finished Aug 02 05:32:56 PM PDT 24
Peak memory 215860 kb
Host smart-5679cc39-7a69-47af-8983-b1d74e62baf1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1776676546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1776676546
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.1074843309
Short name T3083
Test name
Test status
Simulation time 294552100 ps
CPU time 1.03 seconds
Started Aug 02 05:31:59 PM PDT 24
Finished Aug 02 05:32:00 PM PDT 24
Peak memory 207416 kb
Host smart-88b73385-c4bc-4625-88c7-1d5d1a46ec10
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1074843309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.1074843309
Directory /workspace/26.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3895855011
Short name T1312
Test name
Test status
Simulation time 190712401 ps
CPU time 0.91 seconds
Started Aug 02 05:31:38 PM PDT 24
Finished Aug 02 05:31:39 PM PDT 24
Peak memory 207416 kb
Host smart-e407ebe9-5de3-4d35-8c85-f843e32bd59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38958
55011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3895855011
Directory /workspace/26.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.924480097
Short name T1277
Test name
Test status
Simulation time 3010505267 ps
CPU time 81.69 seconds
Started Aug 02 05:31:40 PM PDT 24
Finished Aug 02 05:33:02 PM PDT 24
Peak memory 217232 kb
Host smart-a478db55-1dce-49e3-af3f-aaa68e9e3000
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=924480097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.924480097
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.395046714
Short name T2472
Test name
Test status
Simulation time 151028563 ps
CPU time 0.86 seconds
Started Aug 02 05:31:46 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207332 kb
Host smart-168c95c2-1512-4198-be2f-089be116a3a6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=395046714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.395046714
Directory /workspace/26.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2238079081
Short name T2960
Test name
Test status
Simulation time 182042433 ps
CPU time 0.89 seconds
Started Aug 02 05:31:49 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207312 kb
Host smart-23b750e4-5f93-4f96-ae45-c506522faed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22380
79081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2238079081
Directory /workspace/26.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_nak_trans.3254625083
Short name T134
Test name
Test status
Simulation time 210597349 ps
CPU time 0.97 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 207356 kb
Host smart-b2c08cdc-2833-410c-a09e-2a5220cbb575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32546
25083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3254625083
Directory /workspace/26.usbdev_nak_trans/latest


Test location /workspace/coverage/default/26.usbdev_out_iso.3172380357
Short name T2788
Test name
Test status
Simulation time 162984766 ps
CPU time 0.83 seconds
Started Aug 02 05:31:35 PM PDT 24
Finished Aug 02 05:31:36 PM PDT 24
Peak memory 207424 kb
Host smart-65173ef3-60d7-4c7e-b6f7-5570cd1b70b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31723
80357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3172380357
Directory /workspace/26.usbdev_out_iso/latest


Test location /workspace/coverage/default/26.usbdev_out_stall.1653332298
Short name T534
Test name
Test status
Simulation time 150037815 ps
CPU time 0.85 seconds
Started Aug 02 05:31:37 PM PDT 24
Finished Aug 02 05:31:38 PM PDT 24
Peak memory 207400 kb
Host smart-d2957e4e-8f4c-42f8-bc27-97263f1eeb01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16533
32298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1653332298
Directory /workspace/26.usbdev_out_stall/latest


Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2799684257
Short name T2238
Test name
Test status
Simulation time 224533352 ps
CPU time 0.91 seconds
Started Aug 02 05:31:48 PM PDT 24
Finished Aug 02 05:31:49 PM PDT 24
Peak memory 207384 kb
Host smart-c46a908e-174c-494e-8bcf-8b1430a7270b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27996
84257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2799684257
Directory /workspace/26.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/26.usbdev_pending_in_trans.13169088
Short name T2069
Test name
Test status
Simulation time 187022227 ps
CPU time 0.89 seconds
Started Aug 02 05:31:45 PM PDT 24
Finished Aug 02 05:31:46 PM PDT 24
Peak memory 207364 kb
Host smart-e2200b93-2d3a-4fbe-9ae3-33ea8a092b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13169
088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.13169088
Directory /workspace/26.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1041904881
Short name T2509
Test name
Test status
Simulation time 241775989 ps
CPU time 1.06 seconds
Started Aug 02 05:31:47 PM PDT 24
Finished Aug 02 05:31:48 PM PDT 24
Peak memory 207400 kb
Host smart-a495f03c-abe7-40a9-8d54-15fb17de5859
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1041904881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1041904881
Directory /workspace/26.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.834312219
Short name T781
Test name
Test status
Simulation time 144549183 ps
CPU time 0.89 seconds
Started Aug 02 05:31:54 PM PDT 24
Finished Aug 02 05:31:55 PM PDT 24
Peak memory 207364 kb
Host smart-937e9f8f-ac95-425a-851d-75629b85b5ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83431
2219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.834312219
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1582145164
Short name T2798
Test name
Test status
Simulation time 53315760 ps
CPU time 0.65 seconds
Started Aug 02 05:31:39 PM PDT 24
Finished Aug 02 05:31:40 PM PDT 24
Peak memory 207344 kb
Host smart-64c8b290-4f3c-4c21-bada-5d7e209283b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15821
45164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1582145164
Directory /workspace/26.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3250940736
Short name T2039
Test name
Test status
Simulation time 10741698161 ps
CPU time 25.61 seconds
Started Aug 02 05:31:45 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 215916 kb
Host smart-871c7cd2-61a5-47d2-9e65-950113772f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32509
40736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3250940736
Directory /workspace/26.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/26.usbdev_pkt_received.3050662646
Short name T978
Test name
Test status
Simulation time 255157406 ps
CPU time 1.01 seconds
Started Aug 02 05:31:37 PM PDT 24
Finished Aug 02 05:31:38 PM PDT 24
Peak memory 207408 kb
Host smart-94024120-901a-4060-9262-7c01e0fe50fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30506
62646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3050662646
Directory /workspace/26.usbdev_pkt_received/latest


Test location /workspace/coverage/default/26.usbdev_pkt_sent.1147592769
Short name T1192
Test name
Test status
Simulation time 184150916 ps
CPU time 0.94 seconds
Started Aug 02 05:31:43 PM PDT 24
Finished Aug 02 05:31:44 PM PDT 24
Peak memory 207308 kb
Host smart-600de1fa-e7dc-4e3d-af4e-318c7dc29674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11475
92769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1147592769
Directory /workspace/26.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.569279670
Short name T673
Test name
Test status
Simulation time 238242607 ps
CPU time 0.97 seconds
Started Aug 02 05:31:47 PM PDT 24
Finished Aug 02 05:31:48 PM PDT 24
Peak memory 207340 kb
Host smart-162efc5f-8431-4bcf-a894-7869f1e70f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56927
9670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.569279670
Directory /workspace/26.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.883810953
Short name T606
Test name
Test status
Simulation time 164440450 ps
CPU time 0.84 seconds
Started Aug 02 05:31:37 PM PDT 24
Finished Aug 02 05:31:38 PM PDT 24
Peak memory 207392 kb
Host smart-fb1ba01a-aa2a-40fb-9a80-fdacb3f01334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88381
0953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.883810953
Directory /workspace/26.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2739412019
Short name T3105
Test name
Test status
Simulation time 201117648 ps
CPU time 0.89 seconds
Started Aug 02 05:31:39 PM PDT 24
Finished Aug 02 05:31:40 PM PDT 24
Peak memory 207376 kb
Host smart-3b67f8df-2571-4722-8d52-75d62c97fa5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27394
12019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2739412019
Directory /workspace/26.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/26.usbdev_rx_full.1452024649
Short name T1014
Test name
Test status
Simulation time 334903503 ps
CPU time 1.2 seconds
Started Aug 02 05:31:45 PM PDT 24
Finished Aug 02 05:31:46 PM PDT 24
Peak memory 207416 kb
Host smart-64140f70-4c77-41e6-93af-9364e8d0b873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14520
24649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_full.1452024649
Directory /workspace/26.usbdev_rx_full/latest


Test location /workspace/coverage/default/26.usbdev_setup_stage.2374918970
Short name T2477
Test name
Test status
Simulation time 187234004 ps
CPU time 0.89 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207344 kb
Host smart-9ac47683-ab0b-422f-95f4-fd3ad469fe84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23749
18970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2374918970
Directory /workspace/26.usbdev_setup_stage/latest


Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.4179002496
Short name T1167
Test name
Test status
Simulation time 150415365 ps
CPU time 0.83 seconds
Started Aug 02 05:31:52 PM PDT 24
Finished Aug 02 05:31:53 PM PDT 24
Peak memory 207408 kb
Host smart-27c5e3de-a5e1-413c-9a20-28baa3631aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41790
02496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.4179002496
Directory /workspace/26.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/26.usbdev_smoke.2934249528
Short name T1425
Test name
Test status
Simulation time 260629235 ps
CPU time 1.07 seconds
Started Aug 02 05:31:35 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207364 kb
Host smart-9f2a8ba3-c747-48e0-b51f-501bb34fa157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29342
49528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2934249528
Directory /workspace/26.usbdev_smoke/latest


Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2011002845
Short name T2443
Test name
Test status
Simulation time 2968575352 ps
CPU time 27.96 seconds
Started Aug 02 05:31:52 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 217984 kb
Host smart-ab051b6f-16f0-43d7-ae9c-ade319985fb7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2011002845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2011002845
Directory /workspace/26.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1993251953
Short name T2889
Test name
Test status
Simulation time 158511988 ps
CPU time 0.86 seconds
Started Aug 02 05:31:39 PM PDT 24
Finished Aug 02 05:31:40 PM PDT 24
Peak memory 207448 kb
Host smart-5e9d1649-b811-4edc-b981-223ef2b5f742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19932
51953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1993251953
Directory /workspace/26.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/26.usbdev_stall_trans.1951150927
Short name T1558
Test name
Test status
Simulation time 181679500 ps
CPU time 0.88 seconds
Started Aug 02 05:31:43 PM PDT 24
Finished Aug 02 05:31:44 PM PDT 24
Peak memory 207332 kb
Host smart-186ee8d5-8965-4ae8-8351-46809f096504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19511
50927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.1951150927
Directory /workspace/26.usbdev_stall_trans/latest


Test location /workspace/coverage/default/26.usbdev_stream_len_max.75577045
Short name T1664
Test name
Test status
Simulation time 322740573 ps
CPU time 1.15 seconds
Started Aug 02 05:31:49 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207384 kb
Host smart-0bc6aaac-1483-4743-a1de-4d801da41b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75577
045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.75577045
Directory /workspace/26.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/26.usbdev_streaming_out.776627290
Short name T2658
Test name
Test status
Simulation time 2738822035 ps
CPU time 27.34 seconds
Started Aug 02 05:31:50 PM PDT 24
Finished Aug 02 05:32:18 PM PDT 24
Peak memory 217504 kb
Host smart-567587df-8331-412b-890e-4af217caf974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77662
7290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.776627290
Directory /workspace/26.usbdev_streaming_out/latest


Test location /workspace/coverage/default/26.usbdev_timeout_missing_host_handshake.2713538998
Short name T2008
Test name
Test status
Simulation time 633202525 ps
CPU time 4.66 seconds
Started Aug 02 05:31:27 PM PDT 24
Finished Aug 02 05:31:33 PM PDT 24
Peak memory 207600 kb
Host smart-ce8e6e49-8d21-409a-8f0c-4ca6f182ae74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713538998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_timeout_missing_hos
t_handshake.2713538998
Directory /workspace/26.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/27.usbdev_alert_test.589292417
Short name T2250
Test name
Test status
Simulation time 62789748 ps
CPU time 0.7 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 207440 kb
Host smart-c09a7bf4-519c-48e7-9c76-6acc5713ffb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=589292417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.589292417
Directory /workspace/27.usbdev_alert_test/latest


Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.2910529338
Short name T1407
Test name
Test status
Simulation time 10975949428 ps
CPU time 14.05 seconds
Started Aug 02 05:32:07 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 207588 kb
Host smart-02ca83f1-6849-4617-92e4-862d1e8d97d8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910529338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_disconnect.2910529338
Directory /workspace/27.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1548543960
Short name T2500
Test name
Test status
Simulation time 26366426068 ps
CPU time 30.03 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 215844 kb
Host smart-fb67b5e3-cc41-4366-960a-9d67f717c574
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548543960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_a
on_wake_resume.1548543960
Directory /workspace/27.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/27.usbdev_av_buffer.414058918
Short name T3057
Test name
Test status
Simulation time 161184561 ps
CPU time 0.87 seconds
Started Aug 02 05:31:58 PM PDT 24
Finished Aug 02 05:31:59 PM PDT 24
Peak memory 207400 kb
Host smart-e6f50824-67b1-4162-9c93-3bed86549e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41405
8918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.414058918
Directory /workspace/27.usbdev_av_buffer/latest


Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3162062993
Short name T2316
Test name
Test status
Simulation time 159005912 ps
CPU time 0.85 seconds
Started Aug 02 05:31:37 PM PDT 24
Finished Aug 02 05:31:38 PM PDT 24
Peak memory 207392 kb
Host smart-419eab43-3dfd-4c7c-bb30-c21ce47ac3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31620
62993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3162062993
Directory /workspace/27.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.3021468840
Short name T2822
Test name
Test status
Simulation time 277021243 ps
CPU time 1.14 seconds
Started Aug 02 05:31:58 PM PDT 24
Finished Aug 02 05:31:59 PM PDT 24
Peak memory 207320 kb
Host smart-21b60e4c-81db-440a-acba-6094d38cb331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30214
68840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3021468840
Directory /workspace/27.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.270399254
Short name T2586
Test name
Test status
Simulation time 742274161 ps
CPU time 1.99 seconds
Started Aug 02 05:31:58 PM PDT 24
Finished Aug 02 05:32:00 PM PDT 24
Peak memory 207564 kb
Host smart-5d94202a-2b62-49cb-bf10-e4bd4ba99d0e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=270399254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.270399254
Directory /workspace/27.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/27.usbdev_device_address.1809257474
Short name T176
Test name
Test status
Simulation time 31012050246 ps
CPU time 55.5 seconds
Started Aug 02 05:31:37 PM PDT 24
Finished Aug 02 05:32:33 PM PDT 24
Peak memory 207668 kb
Host smart-75839dae-7b47-430b-9111-982532f8600c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18092
57474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.1809257474
Directory /workspace/27.usbdev_device_address/latest


Test location /workspace/coverage/default/27.usbdev_device_timeout.1497969631
Short name T2222
Test name
Test status
Simulation time 725812084 ps
CPU time 15.65 seconds
Started Aug 02 05:31:53 PM PDT 24
Finished Aug 02 05:32:08 PM PDT 24
Peak memory 207548 kb
Host smart-334864f8-2f95-4bc2-b178-51496b481abf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497969631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_timeout.1497969631
Directory /workspace/27.usbdev_device_timeout/latest


Test location /workspace/coverage/default/27.usbdev_disable_endpoint.788803508
Short name T1330
Test name
Test status
Simulation time 904303435 ps
CPU time 1.93 seconds
Started Aug 02 05:31:53 PM PDT 24
Finished Aug 02 05:31:55 PM PDT 24
Peak memory 207376 kb
Host smart-2a2a067e-1d17-4fe1-aefe-546b62550c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78880
3508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.788803508
Directory /workspace/27.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/27.usbdev_disconnected.3830014346
Short name T3068
Test name
Test status
Simulation time 140977370 ps
CPU time 0.84 seconds
Started Aug 02 05:31:43 PM PDT 24
Finished Aug 02 05:31:44 PM PDT 24
Peak memory 207276 kb
Host smart-a0ff1b1e-ca7d-4bac-9884-c5afffaa8528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38300
14346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.3830014346
Directory /workspace/27.usbdev_disconnected/latest


Test location /workspace/coverage/default/27.usbdev_enable.926065140
Short name T254
Test name
Test status
Simulation time 35496102 ps
CPU time 0.69 seconds
Started Aug 02 05:31:36 PM PDT 24
Finished Aug 02 05:31:37 PM PDT 24
Peak memory 207356 kb
Host smart-9867c908-d921-43b0-a40b-4be6eabdd42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92606
5140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.926065140
Directory /workspace/27.usbdev_enable/latest


Test location /workspace/coverage/default/27.usbdev_endpoint_access.692423589
Short name T2136
Test name
Test status
Simulation time 859898580 ps
CPU time 2.36 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:32:00 PM PDT 24
Peak memory 207552 kb
Host smart-6512513c-36d6-4555-bc54-c5704780a497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69242
3589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.692423589
Directory /workspace/27.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/27.usbdev_endpoint_types.223422223
Short name T2767
Test name
Test status
Simulation time 258170238 ps
CPU time 1.01 seconds
Started Aug 02 05:31:50 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 207388 kb
Host smart-3da180da-9071-4334-9aa8-5fb41116e687
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=223422223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_types.223422223
Directory /workspace/27.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/27.usbdev_fifo_rst.2322575428
Short name T1667
Test name
Test status
Simulation time 253023463 ps
CPU time 1.94 seconds
Started Aug 02 05:31:37 PM PDT 24
Finished Aug 02 05:31:39 PM PDT 24
Peak memory 207616 kb
Host smart-ccd79c42-a616-4024-a9b9-e478f1d30920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23225
75428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2322575428
Directory /workspace/27.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/27.usbdev_in_iso.2869234268
Short name T1316
Test name
Test status
Simulation time 262652722 ps
CPU time 1.21 seconds
Started Aug 02 05:31:55 PM PDT 24
Finished Aug 02 05:31:57 PM PDT 24
Peak memory 207496 kb
Host smart-ad9d492c-1df0-4930-8a57-a51e6fae5898
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2869234268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.2869234268
Directory /workspace/27.usbdev_in_iso/latest


Test location /workspace/coverage/default/27.usbdev_in_stall.4087650205
Short name T986
Test name
Test status
Simulation time 144929015 ps
CPU time 0.8 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 207356 kb
Host smart-ccd188fd-5dcd-4348-8ca1-51236d7fd299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40876
50205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.4087650205
Directory /workspace/27.usbdev_in_stall/latest


Test location /workspace/coverage/default/27.usbdev_in_trans.1689846497
Short name T102
Test name
Test status
Simulation time 228723126 ps
CPU time 0.97 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 207320 kb
Host smart-454df37f-704c-4366-8dbc-474588f89332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16898
46497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1689846497
Directory /workspace/27.usbdev_in_trans/latest


Test location /workspace/coverage/default/27.usbdev_invalid_sync.130015468
Short name T762
Test name
Test status
Simulation time 3997883503 ps
CPU time 105.92 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:33:27 PM PDT 24
Peak memory 224100 kb
Host smart-57c1141f-e12e-4d24-b55c-ccd36a6989f6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=130015468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.130015468
Directory /workspace/27.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/27.usbdev_link_in_err.3156893527
Short name T1705
Test name
Test status
Simulation time 229350284 ps
CPU time 0.99 seconds
Started Aug 02 05:31:49 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207400 kb
Host smart-6bf50351-d4ca-41ae-9e78-16e31da5d443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31568
93527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3156893527
Directory /workspace/27.usbdev_link_in_err/latest


Test location /workspace/coverage/default/27.usbdev_link_resume.4075816277
Short name T600
Test name
Test status
Simulation time 29334488239 ps
CPU time 39.95 seconds
Started Aug 02 05:31:41 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 207708 kb
Host smart-f4586684-113a-488f-b2a9-cc4c8a741ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40758
16277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.4075816277
Directory /workspace/27.usbdev_link_resume/latest


Test location /workspace/coverage/default/27.usbdev_link_suspend.2027275251
Short name T1586
Test name
Test status
Simulation time 4197384666 ps
CPU time 5.95 seconds
Started Aug 02 05:31:50 PM PDT 24
Finished Aug 02 05:31:56 PM PDT 24
Peak memory 215788 kb
Host smart-98e36302-3cde-4acd-9bdf-821c910263dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20272
75251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2027275251
Directory /workspace/27.usbdev_link_suspend/latest


Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2236704292
Short name T1133
Test name
Test status
Simulation time 4634293990 ps
CPU time 34.53 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 217596 kb
Host smart-118e6ec8-e454-44ba-8e4f-41228188f761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22367
04292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2236704292
Directory /workspace/27.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3081643369
Short name T1355
Test name
Test status
Simulation time 4040637371 ps
CPU time 40.5 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:32:37 PM PDT 24
Peak memory 215832 kb
Host smart-24aa015b-58b7-4c19-94d3-759a4568e297
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3081643369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3081643369
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.32897883
Short name T1691
Test name
Test status
Simulation time 257571028 ps
CPU time 1.12 seconds
Started Aug 02 05:31:47 PM PDT 24
Finished Aug 02 05:31:48 PM PDT 24
Peak memory 207324 kb
Host smart-66c7c376-f3ac-4ca9-919d-f3e6e9a6273c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=32897883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.32897883
Directory /workspace/27.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2353490199
Short name T742
Test name
Test status
Simulation time 218600436 ps
CPU time 1 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 207400 kb
Host smart-c94c239a-4225-4e34-962e-6e8247fddf71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23534
90199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2353490199
Directory /workspace/27.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1737104876
Short name T2663
Test name
Test status
Simulation time 2669918963 ps
CPU time 19.81 seconds
Started Aug 02 05:31:50 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 217568 kb
Host smart-16b14821-38cf-40e6-9557-03568c404e4c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1737104876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1737104876
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.1699398219
Short name T2625
Test name
Test status
Simulation time 147085724 ps
CPU time 0.82 seconds
Started Aug 02 05:31:52 PM PDT 24
Finished Aug 02 05:31:53 PM PDT 24
Peak memory 207384 kb
Host smart-d016022a-0e79-497f-a9d9-e0f61050c570
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1699398219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.1699398219
Directory /workspace/27.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1599689658
Short name T682
Test name
Test status
Simulation time 151737396 ps
CPU time 0.87 seconds
Started Aug 02 05:32:00 PM PDT 24
Finished Aug 02 05:32:01 PM PDT 24
Peak memory 207344 kb
Host smart-4330b710-b007-4481-80d7-9cbeb264525a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15996
89658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1599689658
Directory /workspace/27.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_nak_trans.2329299077
Short name T146
Test name
Test status
Simulation time 229065582 ps
CPU time 0.94 seconds
Started Aug 02 05:31:44 PM PDT 24
Finished Aug 02 05:31:45 PM PDT 24
Peak memory 207384 kb
Host smart-b8f1df83-9efd-4ff6-894a-b248d80aea24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23292
99077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2329299077
Directory /workspace/27.usbdev_nak_trans/latest


Test location /workspace/coverage/default/27.usbdev_out_iso.1544388211
Short name T2118
Test name
Test status
Simulation time 160580819 ps
CPU time 0.88 seconds
Started Aug 02 05:31:48 PM PDT 24
Finished Aug 02 05:31:49 PM PDT 24
Peak memory 207352 kb
Host smart-2ac3e110-b6cf-4066-a3fc-b0cc1986174b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15443
88211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1544388211
Directory /workspace/27.usbdev_out_iso/latest


Test location /workspace/coverage/default/27.usbdev_out_stall.2336290766
Short name T1094
Test name
Test status
Simulation time 151521741 ps
CPU time 0.86 seconds
Started Aug 02 05:31:52 PM PDT 24
Finished Aug 02 05:31:53 PM PDT 24
Peak memory 206820 kb
Host smart-fb9de21f-8368-41da-ae5e-a222c3d8dde8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23362
90766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.2336290766
Directory /workspace/27.usbdev_out_stall/latest


Test location /workspace/coverage/default/27.usbdev_out_trans_nak.652197572
Short name T1093
Test name
Test status
Simulation time 179279518 ps
CPU time 0.88 seconds
Started Aug 02 05:31:55 PM PDT 24
Finished Aug 02 05:31:56 PM PDT 24
Peak memory 207384 kb
Host smart-c5aa30c7-e26c-4903-9e73-5befaf2fb8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65219
7572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.652197572
Directory /workspace/27.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2708270447
Short name T1980
Test name
Test status
Simulation time 182263038 ps
CPU time 0.85 seconds
Started Aug 02 05:31:56 PM PDT 24
Finished Aug 02 05:31:57 PM PDT 24
Peak memory 207460 kb
Host smart-b2c5a06c-78b9-4629-b825-f7fda1a1c05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27082
70447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2708270447
Directory /workspace/27.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.3822447185
Short name T708
Test name
Test status
Simulation time 201591618 ps
CPU time 1 seconds
Started Aug 02 05:32:00 PM PDT 24
Finished Aug 02 05:32:01 PM PDT 24
Peak memory 207348 kb
Host smart-b965fab2-576e-4273-9965-931ceab7279d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3822447185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.3822447185
Directory /workspace/27.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3103812384
Short name T984
Test name
Test status
Simulation time 142396874 ps
CPU time 0.78 seconds
Started Aug 02 05:31:52 PM PDT 24
Finished Aug 02 05:31:53 PM PDT 24
Peak memory 207408 kb
Host smart-8166bcc9-fdf1-4895-a42c-c8de0df8c8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31038
12384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3103812384
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.3004549605
Short name T648
Test name
Test status
Simulation time 43513977 ps
CPU time 0.68 seconds
Started Aug 02 05:32:01 PM PDT 24
Finished Aug 02 05:32:02 PM PDT 24
Peak memory 207376 kb
Host smart-865aa0ef-bb54-4465-b55c-844ef836273d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30045
49605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.3004549605
Directory /workspace/27.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1869056704
Short name T288
Test name
Test status
Simulation time 10417143106 ps
CPU time 25.85 seconds
Started Aug 02 05:31:52 PM PDT 24
Finished Aug 02 05:32:18 PM PDT 24
Peak memory 220504 kb
Host smart-19c4049e-da8c-440d-86c7-6a1eb5e8d416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18690
56704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1869056704
Directory /workspace/27.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/27.usbdev_pkt_received.3335931308
Short name T2966
Test name
Test status
Simulation time 160572746 ps
CPU time 0.86 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 207460 kb
Host smart-32906a39-eaff-459a-ad8f-67e8ceae6f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33359
31308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3335931308
Directory /workspace/27.usbdev_pkt_received/latest


Test location /workspace/coverage/default/27.usbdev_pkt_sent.3054346720
Short name T492
Test name
Test status
Simulation time 215169230 ps
CPU time 0.89 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 206804 kb
Host smart-f39f4d68-113d-47f2-8fa9-e7fa227345d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30543
46720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3054346720
Directory /workspace/27.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2435679798
Short name T2395
Test name
Test status
Simulation time 212493652 ps
CPU time 0.89 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 207352 kb
Host smart-e8673f86-8053-461c-a8d8-e22ec3506671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24356
79798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2435679798
Directory /workspace/27.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3408663386
Short name T3067
Test name
Test status
Simulation time 183991696 ps
CPU time 0.88 seconds
Started Aug 02 05:31:55 PM PDT 24
Finished Aug 02 05:31:56 PM PDT 24
Peak memory 207376 kb
Host smart-1ead6644-7351-48fb-9a14-6a4f6d05df6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34086
63386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3408663386
Directory /workspace/27.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/27.usbdev_rx_crc_err.4019525608
Short name T20
Test name
Test status
Simulation time 179280169 ps
CPU time 0.92 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:31:53 PM PDT 24
Peak memory 207360 kb
Host smart-04f33f67-4673-41b3-bae3-56d062832bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40195
25608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.4019525608
Directory /workspace/27.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/27.usbdev_rx_full.324981139
Short name T309
Test name
Test status
Simulation time 329057939 ps
CPU time 1.15 seconds
Started Aug 02 05:31:43 PM PDT 24
Finished Aug 02 05:31:44 PM PDT 24
Peak memory 207380 kb
Host smart-3a70f320-c9dd-4a7a-b87d-7aa2c275babc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32498
1139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_full.324981139
Directory /workspace/27.usbdev_rx_full/latest


Test location /workspace/coverage/default/27.usbdev_setup_stage.1106861969
Short name T2779
Test name
Test status
Simulation time 157441974 ps
CPU time 0.91 seconds
Started Aug 02 05:31:46 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207324 kb
Host smart-199771d8-be36-45b6-b502-296c979d6193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11068
61969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1106861969
Directory /workspace/27.usbdev_setup_stage/latest


Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3674758582
Short name T754
Test name
Test status
Simulation time 152237233 ps
CPU time 0.81 seconds
Started Aug 02 05:31:49 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207364 kb
Host smart-a202982c-d2b3-4af7-8286-ce10a2472552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36747
58582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3674758582
Directory /workspace/27.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/27.usbdev_smoke.2631990780
Short name T692
Test name
Test status
Simulation time 225121081 ps
CPU time 1.05 seconds
Started Aug 02 05:31:55 PM PDT 24
Finished Aug 02 05:31:57 PM PDT 24
Peak memory 207404 kb
Host smart-c75c8609-5a20-4786-9ba2-9cc1080cd0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26319
90780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.2631990780
Directory /workspace/27.usbdev_smoke/latest


Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.2192769008
Short name T1991
Test name
Test status
Simulation time 2566624017 ps
CPU time 25.55 seconds
Started Aug 02 05:32:14 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 217792 kb
Host smart-b10671d3-123d-46f7-b12f-7cf61fcfbe3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2192769008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.2192769008
Directory /workspace/27.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.2727645530
Short name T2814
Test name
Test status
Simulation time 168567907 ps
CPU time 0.87 seconds
Started Aug 02 05:31:58 PM PDT 24
Finished Aug 02 05:31:59 PM PDT 24
Peak memory 207388 kb
Host smart-6a293895-3661-423b-b1ab-cad08b7f88f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27276
45530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.2727645530
Directory /workspace/27.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/27.usbdev_stall_trans.42411735
Short name T820
Test name
Test status
Simulation time 174529804 ps
CPU time 0.87 seconds
Started Aug 02 05:31:49 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207332 kb
Host smart-c8335cca-9240-4dbf-b5d2-6718161aa5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42411
735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.42411735
Directory /workspace/27.usbdev_stall_trans/latest


Test location /workspace/coverage/default/27.usbdev_stream_len_max.776245534
Short name T1520
Test name
Test status
Simulation time 834361723 ps
CPU time 2.02 seconds
Started Aug 02 05:32:03 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207524 kb
Host smart-8463e1bf-e28d-4516-bbbe-07d2c6837462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77624
5534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.776245534
Directory /workspace/27.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/27.usbdev_streaming_out.1415079983
Short name T2723
Test name
Test status
Simulation time 4089093151 ps
CPU time 115.74 seconds
Started Aug 02 05:31:54 PM PDT 24
Finished Aug 02 05:33:50 PM PDT 24
Peak memory 215844 kb
Host smart-624d85f3-6f05-4402-9b17-a1064dcbd5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14150
79983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1415079983
Directory /workspace/27.usbdev_streaming_out/latest


Test location /workspace/coverage/default/27.usbdev_timeout_missing_host_handshake.1615646622
Short name T764
Test name
Test status
Simulation time 473324939 ps
CPU time 8 seconds
Started Aug 02 05:31:39 PM PDT 24
Finished Aug 02 05:31:47 PM PDT 24
Peak memory 207648 kb
Host smart-cac779ce-267d-4e45-8e9c-28cc0031143d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615646622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_timeout_missing_hos
t_handshake.1615646622
Directory /workspace/27.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/28.usbdev_alert_test.1214827282
Short name T1574
Test name
Test status
Simulation time 58718930 ps
CPU time 0.7 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207460 kb
Host smart-dcd09ab3-e6d9-4ffb-8626-879398c19b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1214827282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1214827282
Directory /workspace/28.usbdev_alert_test/latest


Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1818691079
Short name T1281
Test name
Test status
Simulation time 6755647644 ps
CPU time 9.03 seconds
Started Aug 02 05:31:59 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 215884 kb
Host smart-6f5d198c-cd95-4fe4-8127-28b53f9143d7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818691079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_disconnect.1818691079
Directory /workspace/28.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.1750893471
Short name T1012
Test name
Test status
Simulation time 15399491988 ps
CPU time 17.3 seconds
Started Aug 02 05:31:52 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 215864 kb
Host smart-919d0477-b25c-4de3-a6f8-600308e8105f
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750893471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.1750893471
Directory /workspace/28.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3574251687
Short name T1639
Test name
Test status
Simulation time 24177910380 ps
CPU time 29.28 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 215912 kb
Host smart-ab8b325e-3400-46a0-bf8d-c1f1a0be81a6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574251687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_a
on_wake_resume.3574251687
Directory /workspace/28.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/28.usbdev_av_buffer.2543197606
Short name T2378
Test name
Test status
Simulation time 185940037 ps
CPU time 0.93 seconds
Started Aug 02 05:31:56 PM PDT 24
Finished Aug 02 05:31:57 PM PDT 24
Peak memory 207400 kb
Host smart-653e011c-6088-4cb2-b208-91a4587c4b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25431
97606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.2543197606
Directory /workspace/28.usbdev_av_buffer/latest


Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1683274538
Short name T2374
Test name
Test status
Simulation time 152111471 ps
CPU time 0.81 seconds
Started Aug 02 05:31:54 PM PDT 24
Finished Aug 02 05:31:55 PM PDT 24
Peak memory 207328 kb
Host smart-9f5f31fd-2c91-49d7-9880-ed62970559eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16832
74538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1683274538
Directory /workspace/28.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.1283284978
Short name T536
Test name
Test status
Simulation time 478194328 ps
CPU time 1.6 seconds
Started Aug 02 05:31:48 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 207340 kb
Host smart-baea7fbd-0ad7-428e-b3e8-2d3889693f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
84978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.1283284978
Directory /workspace/28.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2656315077
Short name T353
Test name
Test status
Simulation time 1098599411 ps
CPU time 2.88 seconds
Started Aug 02 05:31:55 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 207548 kb
Host smart-8bb882a9-9aa2-4730-8b50-387a34413a3a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2656315077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2656315077
Directory /workspace/28.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/28.usbdev_device_address.341294999
Short name T2326
Test name
Test status
Simulation time 18286377699 ps
CPU time 28.03 seconds
Started Aug 02 05:31:58 PM PDT 24
Finished Aug 02 05:32:26 PM PDT 24
Peak memory 207704 kb
Host smart-aed5b0ff-18c0-47e2-89fd-8e886461f797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34129
4999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.341294999
Directory /workspace/28.usbdev_device_address/latest


Test location /workspace/coverage/default/28.usbdev_device_timeout.4260985549
Short name T2512
Test name
Test status
Simulation time 4749292187 ps
CPU time 42.13 seconds
Started Aug 02 05:32:00 PM PDT 24
Finished Aug 02 05:32:42 PM PDT 24
Peak memory 207628 kb
Host smart-96ce5d01-bf64-417d-a5c1-8c350146d4b9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260985549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_timeout.4260985549
Directory /workspace/28.usbdev_device_timeout/latest


Test location /workspace/coverage/default/28.usbdev_disable_endpoint.2849932993
Short name T2479
Test name
Test status
Simulation time 575092310 ps
CPU time 1.5 seconds
Started Aug 02 05:31:59 PM PDT 24
Finished Aug 02 05:32:00 PM PDT 24
Peak memory 207356 kb
Host smart-e25d6d34-7360-4834-9853-336f3cf43068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28499
32993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.2849932993
Directory /workspace/28.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/28.usbdev_disconnected.1163581
Short name T1122
Test name
Test status
Simulation time 141238821 ps
CPU time 0.84 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207380 kb
Host smart-f825a259-de2f-49d0-85b7-2d013228281e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11635
81 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1163581
Directory /workspace/28.usbdev_disconnected/latest


Test location /workspace/coverage/default/28.usbdev_enable.1792176957
Short name T2322
Test name
Test status
Simulation time 48311163 ps
CPU time 0.69 seconds
Started Aug 02 05:31:52 PM PDT 24
Finished Aug 02 05:31:53 PM PDT 24
Peak memory 207380 kb
Host smart-aa688ef7-7fd6-4d96-935a-1262c103c134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17921
76957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1792176957
Directory /workspace/28.usbdev_enable/latest


Test location /workspace/coverage/default/28.usbdev_endpoint_access.3543936402
Short name T1059
Test name
Test status
Simulation time 875905459 ps
CPU time 2.36 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 207588 kb
Host smart-8672dcb9-d8bb-4d2c-8933-1527a6d235d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35439
36402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3543936402
Directory /workspace/28.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/28.usbdev_endpoint_types.3406100838
Short name T409
Test name
Test status
Simulation time 532329637 ps
CPU time 1.36 seconds
Started Aug 02 05:32:05 PM PDT 24
Finished Aug 02 05:32:07 PM PDT 24
Peak memory 207352 kb
Host smart-df1ce096-78df-41bb-a659-e73011380d1f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3406100838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_types.3406100838
Directory /workspace/28.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/28.usbdev_fifo_rst.424063302
Short name T806
Test name
Test status
Simulation time 302372191 ps
CPU time 2.48 seconds
Started Aug 02 05:32:02 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207612 kb
Host smart-8a02952b-375c-4730-afc1-c50cb8c56cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42406
3302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.424063302
Directory /workspace/28.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/28.usbdev_in_iso.1058534066
Short name T1952
Test name
Test status
Simulation time 237495593 ps
CPU time 1.24 seconds
Started Aug 02 05:32:29 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 215764 kb
Host smart-48bb90e0-a593-4c5e-abe2-353652a51f2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1058534066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1058534066
Directory /workspace/28.usbdev_in_iso/latest


Test location /workspace/coverage/default/28.usbdev_in_stall.896933422
Short name T1468
Test name
Test status
Simulation time 159102803 ps
CPU time 0.8 seconds
Started Aug 02 05:32:07 PM PDT 24
Finished Aug 02 05:32:08 PM PDT 24
Peak memory 207344 kb
Host smart-947e1462-e2ec-4192-82cc-c9f5276cadfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89693
3422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.896933422
Directory /workspace/28.usbdev_in_stall/latest


Test location /workspace/coverage/default/28.usbdev_in_trans.447641616
Short name T2146
Test name
Test status
Simulation time 179635022 ps
CPU time 0.92 seconds
Started Aug 02 05:32:05 PM PDT 24
Finished Aug 02 05:32:06 PM PDT 24
Peak memory 207308 kb
Host smart-b8aae423-210a-4d5a-9490-9fbec2f82104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44764
1616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.447641616
Directory /workspace/28.usbdev_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_invalid_sync.2907404748
Short name T788
Test name
Test status
Simulation time 4728550904 ps
CPU time 38.75 seconds
Started Aug 02 05:32:10 PM PDT 24
Finished Aug 02 05:32:49 PM PDT 24
Peak memory 218152 kb
Host smart-b41d9dd9-9d1a-4a18-b5e9-3eaa1e127fce
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2907404748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.2907404748
Directory /workspace/28.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/28.usbdev_iso_retraction.135922657
Short name T1893
Test name
Test status
Simulation time 10236176260 ps
CPU time 64.84 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:33:09 PM PDT 24
Peak memory 207640 kb
Host smart-3370c50b-9782-4b13-a6ec-2f6926451f2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=135922657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.135922657
Directory /workspace/28.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/28.usbdev_link_in_err.2532276299
Short name T1417
Test name
Test status
Simulation time 171749153 ps
CPU time 0.85 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 207376 kb
Host smart-3d4e98a0-83e0-4304-8db6-e7ae7cc3ad62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25322
76299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2532276299
Directory /workspace/28.usbdev_link_in_err/latest


Test location /workspace/coverage/default/28.usbdev_link_resume.224721585
Short name T1564
Test name
Test status
Simulation time 11204609662 ps
CPU time 16.49 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 207656 kb
Host smart-0c49dddd-5e4b-493d-9bdd-5130ae613728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22472
1585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.224721585
Directory /workspace/28.usbdev_link_resume/latest


Test location /workspace/coverage/default/28.usbdev_link_suspend.1370049347
Short name T1006
Test name
Test status
Simulation time 4541447754 ps
CPU time 6.21 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:14 PM PDT 24
Peak memory 207688 kb
Host smart-0250b600-5073-4b26-b5b4-d73408382cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13700
49347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.1370049347
Directory /workspace/28.usbdev_link_suspend/latest


Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2786834958
Short name T3060
Test name
Test status
Simulation time 4166284228 ps
CPU time 28.71 seconds
Started Aug 02 05:31:53 PM PDT 24
Finished Aug 02 05:32:22 PM PDT 24
Peak memory 217508 kb
Host smart-06559b2a-524d-4bf9-b5af-18e407d1ad0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27868
34958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2786834958
Directory /workspace/28.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.2223896414
Short name T1196
Test name
Test status
Simulation time 3471153890 ps
CPU time 94.15 seconds
Started Aug 02 05:32:01 PM PDT 24
Finished Aug 02 05:33:35 PM PDT 24
Peak memory 217280 kb
Host smart-f3745a29-dd8e-4aad-95c5-e0a1d2ae6cfd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2223896414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.2223896414
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.978406078
Short name T2005
Test name
Test status
Simulation time 246312147 ps
CPU time 1.05 seconds
Started Aug 02 05:32:06 PM PDT 24
Finished Aug 02 05:32:07 PM PDT 24
Peak memory 207424 kb
Host smart-804e0757-3978-4603-a015-cf92fe464971
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=978406078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.978406078
Directory /workspace/28.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.690812738
Short name T777
Test name
Test status
Simulation time 200364675 ps
CPU time 0.96 seconds
Started Aug 02 05:32:00 PM PDT 24
Finished Aug 02 05:32:01 PM PDT 24
Peak memory 207364 kb
Host smart-5d5cb5df-e5eb-43c0-a581-a9e9e8e15ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69081
2738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.690812738
Directory /workspace/28.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.279676073
Short name T725
Test name
Test status
Simulation time 2046596909 ps
CPU time 20.09 seconds
Started Aug 02 05:32:07 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 223880 kb
Host smart-eeba34ec-9e48-4c7b-a58f-619e9a54767d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=279676073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.279676073
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.947515483
Short name T590
Test name
Test status
Simulation time 169718830 ps
CPU time 0.87 seconds
Started Aug 02 05:32:07 PM PDT 24
Finished Aug 02 05:32:08 PM PDT 24
Peak memory 207444 kb
Host smart-6cdb1997-c4b1-44e6-9202-0e9e321128ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=947515483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.947515483
Directory /workspace/28.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.3688522160
Short name T561
Test name
Test status
Simulation time 160345652 ps
CPU time 0.88 seconds
Started Aug 02 05:31:58 PM PDT 24
Finished Aug 02 05:31:59 PM PDT 24
Peak memory 207420 kb
Host smart-227d1cb6-0dc1-4621-a70a-521c655f6abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36885
22160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.3688522160
Directory /workspace/28.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_nak_trans.2968219316
Short name T158
Test name
Test status
Simulation time 199361211 ps
CPU time 0.97 seconds
Started Aug 02 05:31:54 PM PDT 24
Finished Aug 02 05:31:55 PM PDT 24
Peak memory 207356 kb
Host smart-88d00dce-79ab-42c4-a19c-c21021a45ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29682
19316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2968219316
Directory /workspace/28.usbdev_nak_trans/latest


Test location /workspace/coverage/default/28.usbdev_out_iso.2648130131
Short name T1607
Test name
Test status
Simulation time 179646062 ps
CPU time 0.88 seconds
Started Aug 02 05:31:59 PM PDT 24
Finished Aug 02 05:32:00 PM PDT 24
Peak memory 207376 kb
Host smart-22d960d1-5808-4382-ab7b-83ed53b82d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26481
30131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2648130131
Directory /workspace/28.usbdev_out_iso/latest


Test location /workspace/coverage/default/28.usbdev_out_stall.3714166883
Short name T1898
Test name
Test status
Simulation time 165472376 ps
CPU time 0.84 seconds
Started Aug 02 05:32:00 PM PDT 24
Finished Aug 02 05:32:01 PM PDT 24
Peak memory 207388 kb
Host smart-270e86aa-912e-45cd-86fe-3a0cc5179bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37141
66883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.3714166883
Directory /workspace/28.usbdev_out_stall/latest


Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3445836608
Short name T2657
Test name
Test status
Simulation time 196312193 ps
CPU time 0.88 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207444 kb
Host smart-8438bf00-a824-4570-b50a-eba5385eaacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34458
36608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3445836608
Directory /workspace/28.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1232623800
Short name T2199
Test name
Test status
Simulation time 211627980 ps
CPU time 0.87 seconds
Started Aug 02 05:32:24 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 207388 kb
Host smart-1856b177-d2c9-4d9a-96c2-742127e1ced9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12326
23800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1232623800
Directory /workspace/28.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.1515386033
Short name T45
Test name
Test status
Simulation time 241839640 ps
CPU time 1.12 seconds
Started Aug 02 05:32:14 PM PDT 24
Finished Aug 02 05:32:16 PM PDT 24
Peak memory 207320 kb
Host smart-9482e019-9cbd-4911-868a-db1084b5bc5b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1515386033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.1515386033
Directory /workspace/28.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.3279086449
Short name T202
Test name
Test status
Simulation time 225696243 ps
CPU time 0.92 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 207372 kb
Host smart-e9d0b390-b6ca-478a-a221-00eb2cd39fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32790
86449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.3279086449
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3228353766
Short name T2621
Test name
Test status
Simulation time 59146835 ps
CPU time 0.69 seconds
Started Aug 02 05:32:15 PM PDT 24
Finished Aug 02 05:32:16 PM PDT 24
Peak memory 207352 kb
Host smart-98a74514-1320-4ffc-8fa1-3c4ddac72a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32283
53766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3228353766
Directory /workspace/28.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/28.usbdev_pkt_buffer.841576729
Short name T1858
Test name
Test status
Simulation time 12056978575 ps
CPU time 28.05 seconds
Started Aug 02 05:31:58 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 215896 kb
Host smart-1ed4e8ba-ddd0-4ca3-94da-d9ff6988f9c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84157
6729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.841576729
Directory /workspace/28.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/28.usbdev_pkt_received.2049685540
Short name T2164
Test name
Test status
Simulation time 176506627 ps
CPU time 0.95 seconds
Started Aug 02 05:32:07 PM PDT 24
Finished Aug 02 05:32:08 PM PDT 24
Peak memory 207432 kb
Host smart-46fbbefd-627f-44f1-a741-0ed0051da844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20496
85540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2049685540
Directory /workspace/28.usbdev_pkt_received/latest


Test location /workspace/coverage/default/28.usbdev_pkt_sent.1850745086
Short name T807
Test name
Test status
Simulation time 241274085 ps
CPU time 1.01 seconds
Started Aug 02 05:32:06 PM PDT 24
Finished Aug 02 05:32:07 PM PDT 24
Peak memory 207376 kb
Host smart-f4428f3d-4782-42cb-a95b-f4a494e613e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18507
45086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1850745086
Directory /workspace/28.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.4257549234
Short name T1963
Test name
Test status
Simulation time 265411273 ps
CPU time 1.1 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 207352 kb
Host smart-2aa5a550-d7cd-4f77-a10f-0c3b8150ac26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42575
49234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.4257549234
Directory /workspace/28.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1966114067
Short name T2193
Test name
Test status
Simulation time 191307510 ps
CPU time 0.91 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:24 PM PDT 24
Peak memory 207372 kb
Host smart-a86f6fef-5ed6-4dfa-900d-96784b3b177f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19661
14067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1966114067
Directory /workspace/28.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3360003475
Short name T2323
Test name
Test status
Simulation time 142217713 ps
CPU time 0.81 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:31:58 PM PDT 24
Peak memory 207368 kb
Host smart-6592ec82-fc3d-45dc-a933-0a239df79bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33600
03475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3360003475
Directory /workspace/28.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/28.usbdev_rx_full.3110815182
Short name T901
Test name
Test status
Simulation time 271018488 ps
CPU time 1.06 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207416 kb
Host smart-782fe19e-af8c-4c69-bf72-16fca786d8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31108
15182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_full.3110815182
Directory /workspace/28.usbdev_rx_full/latest


Test location /workspace/coverage/default/28.usbdev_setup_stage.40268210
Short name T1689
Test name
Test status
Simulation time 178067088 ps
CPU time 0.87 seconds
Started Aug 02 05:31:59 PM PDT 24
Finished Aug 02 05:32:00 PM PDT 24
Peak memory 207368 kb
Host smart-b9a36039-e02c-474d-8d45-697d725610ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40268
210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.40268210
Directory /workspace/28.usbdev_setup_stage/latest


Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1668438280
Short name T1103
Test name
Test status
Simulation time 148054701 ps
CPU time 0.81 seconds
Started Aug 02 05:32:06 PM PDT 24
Finished Aug 02 05:32:12 PM PDT 24
Peak memory 207352 kb
Host smart-aef7738a-df2d-4932-8f75-f826fafe1837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16684
38280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1668438280
Directory /workspace/28.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/28.usbdev_smoke.1218815552
Short name T2923
Test name
Test status
Simulation time 226139500 ps
CPU time 0.98 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207340 kb
Host smart-f03dba71-9464-4185-bb68-5d6eef85713f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12188
15552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1218815552
Directory /workspace/28.usbdev_smoke/latest


Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.1684662774
Short name T1282
Test name
Test status
Simulation time 2737697080 ps
CPU time 77.82 seconds
Started Aug 02 05:32:13 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 217544 kb
Host smart-4943b935-a48e-414c-aa3e-8e9d81d359f0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1684662774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.1684662774
Directory /workspace/28.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.530607193
Short name T3064
Test name
Test status
Simulation time 213348711 ps
CPU time 0.91 seconds
Started Aug 02 05:31:58 PM PDT 24
Finished Aug 02 05:31:59 PM PDT 24
Peak memory 207444 kb
Host smart-a1e1e481-1b90-4f6d-bd49-006e99af0cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53060
7193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.530607193
Directory /workspace/28.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/28.usbdev_stall_trans.1005647774
Short name T2226
Test name
Test status
Simulation time 227796880 ps
CPU time 0.9 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 207368 kb
Host smart-815b4970-b2f1-4643-900e-c413edc39c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10056
47774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1005647774
Directory /workspace/28.usbdev_stall_trans/latest


Test location /workspace/coverage/default/28.usbdev_stream_len_max.1981628058
Short name T833
Test name
Test status
Simulation time 921986826 ps
CPU time 2.37 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 207608 kb
Host smart-ce0a6451-e712-4706-afb3-16a82976b415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19816
28058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.1981628058
Directory /workspace/28.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/28.usbdev_streaming_out.2823237556
Short name T1101
Test name
Test status
Simulation time 1827393248 ps
CPU time 51.03 seconds
Started Aug 02 05:32:03 PM PDT 24
Finished Aug 02 05:32:54 PM PDT 24
Peak memory 215748 kb
Host smart-3f795c61-1c1e-4a09-90cf-c1ec49b58405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28232
37556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2823237556
Directory /workspace/28.usbdev_streaming_out/latest


Test location /workspace/coverage/default/28.usbdev_timeout_missing_host_handshake.1335795229
Short name T749
Test name
Test status
Simulation time 139923876 ps
CPU time 0.85 seconds
Started Aug 02 05:31:51 PM PDT 24
Finished Aug 02 05:31:52 PM PDT 24
Peak memory 207292 kb
Host smart-847e1503-5dce-44a0-91f8-d0f75369e925
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335795229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_timeout_missing_hos
t_handshake.1335795229
Directory /workspace/28.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/29.usbdev_alert_test.1707338508
Short name T1982
Test name
Test status
Simulation time 73809137 ps
CPU time 0.68 seconds
Started Aug 02 05:32:26 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 207472 kb
Host smart-52c48fbd-81ca-4049-89f5-af1297dc40d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1707338508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1707338508
Directory /workspace/29.usbdev_alert_test/latest


Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1051633912
Short name T2569
Test name
Test status
Simulation time 8654675491 ps
CPU time 11.89 seconds
Started Aug 02 05:32:06 PM PDT 24
Finished Aug 02 05:32:18 PM PDT 24
Peak memory 207704 kb
Host smart-378ecab9-a853-454b-9b86-3f1f6ff6633a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051633912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_disconnect.1051633912
Directory /workspace/29.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3093146470
Short name T2258
Test name
Test status
Simulation time 15282289740 ps
CPU time 17.81 seconds
Started Aug 02 05:32:02 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 215824 kb
Host smart-dd08745a-7413-4321-8a8c-7a2e61e06cfb
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093146470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3093146470
Directory /workspace/29.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3144926943
Short name T1810
Test name
Test status
Simulation time 25732884332 ps
CPU time 31.58 seconds
Started Aug 02 05:32:11 PM PDT 24
Finished Aug 02 05:32:42 PM PDT 24
Peak memory 215852 kb
Host smart-ec56cc78-1082-4b54-8396-7a7a559c6932
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144926943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_a
on_wake_resume.3144926943
Directory /workspace/29.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/29.usbdev_av_buffer.4209437477
Short name T2616
Test name
Test status
Simulation time 210404699 ps
CPU time 0.99 seconds
Started Aug 02 05:32:03 PM PDT 24
Finished Aug 02 05:32:04 PM PDT 24
Peak memory 207408 kb
Host smart-6782315a-b018-4f7f-9bed-f8a2e5b1acc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42094
37477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.4209437477
Directory /workspace/29.usbdev_av_buffer/latest


Test location /workspace/coverage/default/29.usbdev_bitstuff_err.2878499045
Short name T1194
Test name
Test status
Simulation time 172682420 ps
CPU time 0.88 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207268 kb
Host smart-a352dec6-3d1c-4161-bec6-fcdff1dad7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28784
99045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.2878499045
Directory /workspace/29.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.1681769085
Short name T822
Test name
Test status
Simulation time 199701390 ps
CPU time 0.93 seconds
Started Aug 02 05:32:11 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 207312 kb
Host smart-088ea1ad-f945-41ff-8148-81d2c148f073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16817
69085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.1681769085
Directory /workspace/29.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1189168388
Short name T2317
Test name
Test status
Simulation time 432866498 ps
CPU time 1.26 seconds
Started Aug 02 05:32:03 PM PDT 24
Finished Aug 02 05:32:04 PM PDT 24
Peak memory 207356 kb
Host smart-289ec61d-afe6-4a3a-87ad-c2bfe016307e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1189168388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1189168388
Directory /workspace/29.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/29.usbdev_device_address.4294686763
Short name T186
Test name
Test status
Simulation time 27546483153 ps
CPU time 44.27 seconds
Started Aug 02 05:32:11 PM PDT 24
Finished Aug 02 05:32:55 PM PDT 24
Peak memory 207696 kb
Host smart-e587e6e2-8880-459e-8665-50033fcb422f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42946
86763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.4294686763
Directory /workspace/29.usbdev_device_address/latest


Test location /workspace/coverage/default/29.usbdev_device_timeout.2128599050
Short name T2517
Test name
Test status
Simulation time 2960331242 ps
CPU time 26.01 seconds
Started Aug 02 05:32:03 PM PDT 24
Finished Aug 02 05:32:29 PM PDT 24
Peak memory 207784 kb
Host smart-bbdc80b2-7f33-472a-9619-1ab5fbd54d2b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128599050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_timeout.2128599050
Directory /workspace/29.usbdev_device_timeout/latest


Test location /workspace/coverage/default/29.usbdev_disable_endpoint.541151560
Short name T370
Test name
Test status
Simulation time 832893425 ps
CPU time 2.01 seconds
Started Aug 02 05:32:03 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207380 kb
Host smart-5e0a5351-20e0-4ede-a803-70ca7a9ce2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54115
1560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.541151560
Directory /workspace/29.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/29.usbdev_disconnected.2565484683
Short name T3020
Test name
Test status
Simulation time 166911884 ps
CPU time 0.86 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 207328 kb
Host smart-2164e036-57bd-4127-acbf-3e0275615b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25654
84683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.2565484683
Directory /workspace/29.usbdev_disconnected/latest


Test location /workspace/coverage/default/29.usbdev_enable.2041212178
Short name T2424
Test name
Test status
Simulation time 42077431 ps
CPU time 0.73 seconds
Started Aug 02 05:32:06 PM PDT 24
Finished Aug 02 05:32:07 PM PDT 24
Peak memory 207388 kb
Host smart-407c93f7-d5f1-41d1-a0cd-96cd707f3db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20412
12178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2041212178
Directory /workspace/29.usbdev_enable/latest


Test location /workspace/coverage/default/29.usbdev_endpoint_access.3862361452
Short name T672
Test name
Test status
Simulation time 945077549 ps
CPU time 2.32 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 207520 kb
Host smart-832d1be4-c4cb-4417-a761-8c1aeed94c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38623
61452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3862361452
Directory /workspace/29.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/29.usbdev_endpoint_types.3338135463
Short name T376
Test name
Test status
Simulation time 597436307 ps
CPU time 1.62 seconds
Started Aug 02 05:32:05 PM PDT 24
Finished Aug 02 05:32:07 PM PDT 24
Peak memory 207304 kb
Host smart-8a199762-b521-468d-9552-bcc6db15caee
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3338135463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_types.3338135463
Directory /workspace/29.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/29.usbdev_fifo_rst.3406100832
Short name T2437
Test name
Test status
Simulation time 316694383 ps
CPU time 2.71 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:12 PM PDT 24
Peak memory 207532 kb
Host smart-0de77535-cdac-4ad4-81d2-905ac9627195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34061
00832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3406100832
Directory /workspace/29.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/29.usbdev_in_iso.1380122988
Short name T2243
Test name
Test status
Simulation time 198834304 ps
CPU time 0.98 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 215768 kb
Host smart-9266696d-00b5-47a8-85c8-eb3b28c4e5f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1380122988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1380122988
Directory /workspace/29.usbdev_in_iso/latest


Test location /workspace/coverage/default/29.usbdev_in_stall.1265457478
Short name T2330
Test name
Test status
Simulation time 157608187 ps
CPU time 0.87 seconds
Started Aug 02 05:31:56 PM PDT 24
Finished Aug 02 05:31:57 PM PDT 24
Peak memory 207348 kb
Host smart-5d5fafbc-2af2-4d06-a10d-b294a2ea875d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12654
57478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.1265457478
Directory /workspace/29.usbdev_in_stall/latest


Test location /workspace/coverage/default/29.usbdev_in_trans.937172925
Short name T1357
Test name
Test status
Simulation time 227462102 ps
CPU time 0.94 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207424 kb
Host smart-b5939a15-2435-46d1-b585-3b9e18e90808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93717
2925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.937172925
Directory /workspace/29.usbdev_in_trans/latest


Test location /workspace/coverage/default/29.usbdev_invalid_sync.2088800674
Short name T2098
Test name
Test status
Simulation time 4143761309 ps
CPU time 117.99 seconds
Started Aug 02 05:31:57 PM PDT 24
Finished Aug 02 05:33:55 PM PDT 24
Peak memory 218156 kb
Host smart-ebad4ddb-09ba-4cd4-82a6-b10d6ce1570c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2088800674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2088800674
Directory /workspace/29.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/29.usbdev_iso_retraction.734786062
Short name T922
Test name
Test status
Simulation time 8338234077 ps
CPU time 92.44 seconds
Started Aug 02 05:31:55 PM PDT 24
Finished Aug 02 05:33:28 PM PDT 24
Peak memory 207640 kb
Host smart-dd6bef4c-23c4-4c73-b793-61ba5cf6b754
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=734786062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.734786062
Directory /workspace/29.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/29.usbdev_link_in_err.3476589860
Short name T2737
Test name
Test status
Simulation time 215611175 ps
CPU time 0.95 seconds
Started Aug 02 05:32:24 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 207388 kb
Host smart-019744e3-1f0d-40ff-887a-d11992985a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34765
89860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.3476589860
Directory /workspace/29.usbdev_link_in_err/latest


Test location /workspace/coverage/default/29.usbdev_link_resume.1881514626
Short name T902
Test name
Test status
Simulation time 26184139209 ps
CPU time 35.9 seconds
Started Aug 02 05:32:11 PM PDT 24
Finished Aug 02 05:32:47 PM PDT 24
Peak memory 215848 kb
Host smart-20b1a52b-4683-46ee-814f-b373c4033bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18815
14626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1881514626
Directory /workspace/29.usbdev_link_resume/latest


Test location /workspace/coverage/default/29.usbdev_link_suspend.1243700318
Short name T650
Test name
Test status
Simulation time 10108435433 ps
CPU time 12 seconds
Started Aug 02 05:32:13 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 207688 kb
Host smart-0d77bc63-c274-448a-aa64-4a8ceb2bc73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12437
00318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1243700318
Directory /workspace/29.usbdev_link_suspend/latest


Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.1708554917
Short name T652
Test name
Test status
Simulation time 4192943530 ps
CPU time 28.79 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:50 PM PDT 24
Peak memory 224052 kb
Host smart-ee19ffc6-e17c-45bc-a8cc-969178183ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17085
54917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1708554917
Directory /workspace/29.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.2319353563
Short name T1321
Test name
Test status
Simulation time 2224755720 ps
CPU time 21.63 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:32:47 PM PDT 24
Peak memory 215896 kb
Host smart-dc4cbca4-919f-4388-b8d8-fac71564b739
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2319353563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.2319353563
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.366119908
Short name T1791
Test name
Test status
Simulation time 232548276 ps
CPU time 1.03 seconds
Started Aug 02 05:32:00 PM PDT 24
Finished Aug 02 05:32:01 PM PDT 24
Peak memory 207376 kb
Host smart-770c2fd2-42c8-4c6d-9e27-75ea636362f4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=366119908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.366119908
Directory /workspace/29.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1851742277
Short name T2699
Test name
Test status
Simulation time 200073944 ps
CPU time 0.92 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 207340 kb
Host smart-08637370-e6e6-4182-8860-77235fcea4f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18517
42277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1851742277
Directory /workspace/29.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.1355961914
Short name T2463
Test name
Test status
Simulation time 3016950861 ps
CPU time 30.28 seconds
Started Aug 02 05:32:05 PM PDT 24
Finished Aug 02 05:32:35 PM PDT 24
Peak memory 224064 kb
Host smart-0b7147ec-5323-4d39-9a17-ff1f5a297e89
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1355961914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1355961914
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.2599431629
Short name T1764
Test name
Test status
Simulation time 158857404 ps
CPU time 0.85 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 207380 kb
Host smart-ef092f57-0386-41c9-a097-24d8f97fbeb9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2599431629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.2599431629
Directory /workspace/29.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1966940293
Short name T1249
Test name
Test status
Simulation time 160105695 ps
CPU time 0.83 seconds
Started Aug 02 05:32:10 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 207424 kb
Host smart-4ed194ad-33d8-4df1-81fb-a4680db846de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19669
40293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1966940293
Directory /workspace/29.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_nak_trans.2276841124
Short name T2455
Test name
Test status
Simulation time 191437207 ps
CPU time 0.89 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 207396 kb
Host smart-a92a5a8d-3720-408e-a75a-19d7c91c9a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22768
41124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2276841124
Directory /workspace/29.usbdev_nak_trans/latest


Test location /workspace/coverage/default/29.usbdev_out_iso.3412358219
Short name T1968
Test name
Test status
Simulation time 177067062 ps
CPU time 0.91 seconds
Started Aug 02 05:32:05 PM PDT 24
Finished Aug 02 05:32:06 PM PDT 24
Peak memory 207404 kb
Host smart-5c2f4c12-8c50-4272-aecb-748fd370528d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34123
58219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.3412358219
Directory /workspace/29.usbdev_out_iso/latest


Test location /workspace/coverage/default/29.usbdev_out_stall.2724107189
Short name T1972
Test name
Test status
Simulation time 161684347 ps
CPU time 0.85 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 207380 kb
Host smart-e963b7cd-d0e2-4b5b-ba48-b98f5f83e053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27241
07189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2724107189
Directory /workspace/29.usbdev_out_stall/latest


Test location /workspace/coverage/default/29.usbdev_out_trans_nak.604208455
Short name T1261
Test name
Test status
Simulation time 214246930 ps
CPU time 0.96 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207356 kb
Host smart-2a7111e0-2313-475f-92a0-84e8c1af5465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60420
8455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.604208455
Directory /workspace/29.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2992608813
Short name T2752
Test name
Test status
Simulation time 154546424 ps
CPU time 0.84 seconds
Started Aug 02 05:32:14 PM PDT 24
Finished Aug 02 05:32:15 PM PDT 24
Peak memory 207400 kb
Host smart-e4079f91-e5cb-4163-8db8-afec2eaab62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29926
08813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2992608813
Directory /workspace/29.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1619421868
Short name T2585
Test name
Test status
Simulation time 227326059 ps
CPU time 1.01 seconds
Started Aug 02 05:32:17 PM PDT 24
Finished Aug 02 05:32:18 PM PDT 24
Peak memory 207360 kb
Host smart-d1a8fcb3-2f52-47af-b608-f11d120784e0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1619421868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1619421868
Directory /workspace/29.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3511269696
Short name T891
Test name
Test status
Simulation time 195235029 ps
CPU time 0.84 seconds
Started Aug 02 05:32:15 PM PDT 24
Finished Aug 02 05:32:16 PM PDT 24
Peak memory 207364 kb
Host smart-1fe19ee5-0ec4-477d-8385-3475956ee9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35112
69696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3511269696
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2552432067
Short name T1233
Test name
Test status
Simulation time 33415232 ps
CPU time 0.71 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 207348 kb
Host smart-d7bf51ca-a9bf-4d4b-8a1f-57130505a2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
32067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2552432067
Directory /workspace/29.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/29.usbdev_pkt_buffer.373215929
Short name T1752
Test name
Test status
Simulation time 9429704764 ps
CPU time 24.15 seconds
Started Aug 02 05:31:59 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 224032 kb
Host smart-91fc8571-099a-495e-bdeb-880ea88633e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37321
5929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.373215929
Directory /workspace/29.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/29.usbdev_pkt_received.2111166016
Short name T2352
Test name
Test status
Simulation time 171320004 ps
CPU time 0.93 seconds
Started Aug 02 05:32:27 PM PDT 24
Finished Aug 02 05:32:28 PM PDT 24
Peak memory 207368 kb
Host smart-fa2f1d68-69dc-4a65-9383-c163c5a4bbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21111
66016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.2111166016
Directory /workspace/29.usbdev_pkt_received/latest


Test location /workspace/coverage/default/29.usbdev_pkt_sent.2475411784
Short name T859
Test name
Test status
Simulation time 231890749 ps
CPU time 0.92 seconds
Started Aug 02 05:32:04 PM PDT 24
Finished Aug 02 05:32:05 PM PDT 24
Peak memory 207364 kb
Host smart-993e2125-aaa8-479b-9c50-186c8f2de90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24754
11784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2475411784
Directory /workspace/29.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.3927850766
Short name T2382
Test name
Test status
Simulation time 246714458 ps
CPU time 0.99 seconds
Started Aug 02 05:32:05 PM PDT 24
Finished Aug 02 05:32:06 PM PDT 24
Peak memory 207360 kb
Host smart-4614e520-4148-4d20-85f2-4de6390ef7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39278
50766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.3927850766
Directory /workspace/29.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3204698976
Short name T1536
Test name
Test status
Simulation time 170085550 ps
CPU time 0.88 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 207412 kb
Host smart-fd2f234c-3fb8-4067-8af4-5d195833bc96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32046
98976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3204698976
Directory /workspace/29.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/29.usbdev_rx_crc_err.142369322
Short name T728
Test name
Test status
Simulation time 247483245 ps
CPU time 1.01 seconds
Started Aug 02 05:32:10 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 207356 kb
Host smart-9b52d08f-4060-46bf-a57d-c8bc406b78b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14236
9322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.142369322
Directory /workspace/29.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/29.usbdev_rx_full.2416154550
Short name T832
Test name
Test status
Simulation time 317470416 ps
CPU time 1.16 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207392 kb
Host smart-dbd2ad6f-573c-4a46-ae0d-b01389e6e9ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24161
54550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_full.2416154550
Directory /workspace/29.usbdev_rx_full/latest


Test location /workspace/coverage/default/29.usbdev_setup_stage.533989767
Short name T2462
Test name
Test status
Simulation time 191816097 ps
CPU time 0.87 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 207384 kb
Host smart-232ab50a-755c-4663-92dc-d0f16e391baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53398
9767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.533989767
Directory /workspace/29.usbdev_setup_stage/latest


Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.2079004119
Short name T540
Test name
Test status
Simulation time 153258017 ps
CPU time 0.88 seconds
Started Aug 02 05:32:13 PM PDT 24
Finished Aug 02 05:32:14 PM PDT 24
Peak memory 207408 kb
Host smart-17dd4304-a838-4bc6-bea3-bfdcac7175df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20790
04119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.2079004119
Directory /workspace/29.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/29.usbdev_smoke.1784898532
Short name T789
Test name
Test status
Simulation time 273224934 ps
CPU time 1.09 seconds
Started Aug 02 05:32:12 PM PDT 24
Finished Aug 02 05:32:13 PM PDT 24
Peak memory 207408 kb
Host smart-6ae5eba0-8bd2-4657-bdbc-35f574e1da6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17848
98532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1784898532
Directory /workspace/29.usbdev_smoke/latest


Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3433699948
Short name T1611
Test name
Test status
Simulation time 1952863375 ps
CPU time 15.25 seconds
Started Aug 02 05:32:24 PM PDT 24
Finished Aug 02 05:32:39 PM PDT 24
Peak memory 223904 kb
Host smart-5cfb0392-0aef-4a56-8e98-57a8b96c20ee
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3433699948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3433699948
Directory /workspace/29.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/29.usbdev_stall_trans.2259216001
Short name T562
Test name
Test status
Simulation time 173566652 ps
CPU time 0.83 seconds
Started Aug 02 05:32:11 PM PDT 24
Finished Aug 02 05:32:12 PM PDT 24
Peak memory 207352 kb
Host smart-e4445659-f203-4213-8aa0-3441c9e70085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22592
16001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2259216001
Directory /workspace/29.usbdev_stall_trans/latest


Test location /workspace/coverage/default/29.usbdev_stream_len_max.1447468058
Short name T2816
Test name
Test status
Simulation time 1037911527 ps
CPU time 2.72 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:12 PM PDT 24
Peak memory 207520 kb
Host smart-deba6fc9-63b5-4501-8bab-df5b76d6f830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14474
68058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1447468058
Directory /workspace/29.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/29.usbdev_streaming_out.3530218149
Short name T644
Test name
Test status
Simulation time 3076620229 ps
CPU time 88.25 seconds
Started Aug 02 05:32:05 PM PDT 24
Finished Aug 02 05:33:33 PM PDT 24
Peak memory 217568 kb
Host smart-d799211d-27fb-4076-8697-e8e9caef6d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35302
18149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3530218149
Directory /workspace/29.usbdev_streaming_out/latest


Test location /workspace/coverage/default/29.usbdev_timeout_missing_host_handshake.1463168591
Short name T2225
Test name
Test status
Simulation time 1667850977 ps
CPU time 40.78 seconds
Started Aug 02 05:32:17 PM PDT 24
Finished Aug 02 05:32:58 PM PDT 24
Peak memory 207584 kb
Host smart-6ce24141-28c4-409e-b9f0-91e7622bcfd3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463168591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_timeout_missing_hos
t_handshake.1463168591
Directory /workspace/29.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/3.usbdev_alert_test.1506202564
Short name T198
Test name
Test status
Simulation time 86346197 ps
CPU time 0.71 seconds
Started Aug 02 05:27:42 PM PDT 24
Finished Aug 02 05:27:43 PM PDT 24
Peak memory 207468 kb
Host smart-62c3a618-59e7-417d-8833-7bad8b586633
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1506202564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1506202564
Directory /workspace/3.usbdev_alert_test/latest


Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.4190118223
Short name T2269
Test name
Test status
Simulation time 10131010788 ps
CPU time 13.74 seconds
Started Aug 02 05:27:23 PM PDT 24
Finished Aug 02 05:27:37 PM PDT 24
Peak memory 207620 kb
Host smart-40b35631-168b-49bd-a6bb-3f74e48af921
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190118223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_ao
n_wake_disconnect.4190118223
Directory /workspace/3.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.65731433
Short name T1490
Test name
Test status
Simulation time 13478708806 ps
CPU time 15.06 seconds
Started Aug 02 05:27:22 PM PDT 24
Finished Aug 02 05:27:37 PM PDT 24
Peak memory 215880 kb
Host smart-e3720c41-ff06-41d5-b2f3-c1b3f7e69272
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=65731433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.65731433
Directory /workspace/3.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.993142632
Short name T1452
Test name
Test status
Simulation time 30417399455 ps
CPU time 36.13 seconds
Started Aug 02 05:27:25 PM PDT 24
Finished Aug 02 05:28:02 PM PDT 24
Peak memory 207632 kb
Host smart-c3396c93-3b74-4c49-804d-11c04057d6d4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993142632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon
_wake_resume.993142632
Directory /workspace/3.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/3.usbdev_av_buffer.2837854067
Short name T499
Test name
Test status
Simulation time 211093322 ps
CPU time 0.91 seconds
Started Aug 02 05:27:17 PM PDT 24
Finished Aug 02 05:27:18 PM PDT 24
Peak memory 207400 kb
Host smart-c358737d-d4dc-495e-ba21-f84a17685363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28378
54067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2837854067
Directory /workspace/3.usbdev_av_buffer/latest


Test location /workspace/coverage/default/3.usbdev_av_empty.2534819733
Short name T47
Test name
Test status
Simulation time 210740478 ps
CPU time 0.94 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:20 PM PDT 24
Peak memory 207308 kb
Host smart-db9992cd-d2fc-42d3-9d6d-553093c52da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25348
19733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2534819733
Directory /workspace/3.usbdev_av_empty/latest


Test location /workspace/coverage/default/3.usbdev_av_overflow.2874429683
Short name T60
Test name
Test status
Simulation time 141955197 ps
CPU time 0.84 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:20 PM PDT 24
Peak memory 207332 kb
Host smart-ff9a84af-2619-4542-b8d2-86b37209bfde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28744
29683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2874429683
Directory /workspace/3.usbdev_av_overflow/latest


Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3703150490
Short name T1720
Test name
Test status
Simulation time 149063907 ps
CPU time 0.79 seconds
Started Aug 02 05:27:18 PM PDT 24
Finished Aug 02 05:27:19 PM PDT 24
Peak memory 207376 kb
Host smart-f9721efb-c6d6-40d6-9228-ece78fc68b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37031
50490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3703150490
Directory /workspace/3.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.767035264
Short name T1729
Test name
Test status
Simulation time 427946188 ps
CPU time 1.46 seconds
Started Aug 02 05:27:19 PM PDT 24
Finished Aug 02 05:27:21 PM PDT 24
Peak memory 207392 kb
Host smart-4af9204a-7cbe-4763-a0a8-0795b9f0c8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76703
5264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.767035264
Directory /workspace/3.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.3151125679
Short name T1873
Test name
Test status
Simulation time 306873835 ps
CPU time 1.04 seconds
Started Aug 02 05:27:21 PM PDT 24
Finished Aug 02 05:27:22 PM PDT 24
Peak memory 207428 kb
Host smart-46a15ce6-e71e-4ee3-badd-592b0fa75846
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3151125679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.3151125679
Directory /workspace/3.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/3.usbdev_device_address.1105124361
Short name T2790
Test name
Test status
Simulation time 37355523285 ps
CPU time 56.63 seconds
Started Aug 02 05:27:22 PM PDT 24
Finished Aug 02 05:28:18 PM PDT 24
Peak memory 207644 kb
Host smart-a3622c3a-9713-456d-9bae-98a39711c484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11051
24361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.1105124361
Directory /workspace/3.usbdev_device_address/latest


Test location /workspace/coverage/default/3.usbdev_device_timeout.502128457
Short name T2554
Test name
Test status
Simulation time 1823051935 ps
CPU time 44.72 seconds
Started Aug 02 05:27:26 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 207504 kb
Host smart-464c3a5b-7f69-4df5-8883-e4c9cca7c2e2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502128457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_timeout.502128457
Directory /workspace/3.usbdev_device_timeout/latest


Test location /workspace/coverage/default/3.usbdev_disable_endpoint.1039620840
Short name T355
Test name
Test status
Simulation time 1350076664 ps
CPU time 2.51 seconds
Started Aug 02 05:27:25 PM PDT 24
Finished Aug 02 05:27:28 PM PDT 24
Peak memory 207396 kb
Host smart-31434920-6e3a-40b8-befb-74178331adf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10396
20840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.1039620840
Directory /workspace/3.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/3.usbdev_disconnected.4271430464
Short name T2072
Test name
Test status
Simulation time 172070404 ps
CPU time 0.82 seconds
Started Aug 02 05:27:30 PM PDT 24
Finished Aug 02 05:27:31 PM PDT 24
Peak memory 207376 kb
Host smart-8da9bee1-6b06-4b5a-9acd-868b5fc25221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42714
30464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.4271430464
Directory /workspace/3.usbdev_disconnected/latest


Test location /workspace/coverage/default/3.usbdev_enable.1416304495
Short name T2780
Test name
Test status
Simulation time 57341899 ps
CPU time 0.69 seconds
Started Aug 02 05:27:26 PM PDT 24
Finished Aug 02 05:27:27 PM PDT 24
Peak memory 207320 kb
Host smart-fefb3bc7-0c04-4538-a2bd-e75e6391b456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14163
04495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1416304495
Directory /workspace/3.usbdev_enable/latest


Test location /workspace/coverage/default/3.usbdev_endpoint_access.3966188985
Short name T2913
Test name
Test status
Simulation time 833239955 ps
CPU time 2.4 seconds
Started Aug 02 05:27:26 PM PDT 24
Finished Aug 02 05:27:28 PM PDT 24
Peak memory 207604 kb
Host smart-529ee8b8-aaa5-401a-ac8e-73c4bc35ae30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39661
88985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3966188985
Directory /workspace/3.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/3.usbdev_endpoint_types.2137065569
Short name T392
Test name
Test status
Simulation time 462234556 ps
CPU time 1.17 seconds
Started Aug 02 05:27:30 PM PDT 24
Finished Aug 02 05:27:32 PM PDT 24
Peak memory 207344 kb
Host smart-441690bb-cee8-4e49-91f8-30d352f37e6c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2137065569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_types.2137065569
Directory /workspace/3.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/3.usbdev_fifo_rst.1011066860
Short name T1621
Test name
Test status
Simulation time 171695157 ps
CPU time 1.92 seconds
Started Aug 02 05:27:25 PM PDT 24
Finished Aug 02 05:27:27 PM PDT 24
Peak memory 207616 kb
Host smart-32fa29ab-c712-493e-9daa-7e3b8799dd85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10110
66860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1011066860
Directory /workspace/3.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3956252991
Short name T320
Test name
Test status
Simulation time 104179478880 ps
CPU time 150.77 seconds
Started Aug 02 05:27:29 PM PDT 24
Finished Aug 02 05:29:59 PM PDT 24
Peak memory 207696 kb
Host smart-6624ee54-4328-4c12-a16d-eef78d7c888c
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3956252991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3956252991
Directory /workspace/3.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.3046382605
Short name T1263
Test name
Test status
Simulation time 108414970732 ps
CPU time 160.4 seconds
Started Aug 02 05:27:29 PM PDT 24
Finished Aug 02 05:30:09 PM PDT 24
Peak memory 207664 kb
Host smart-5cc56856-a84f-4dc6-af71-453f24b144c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046382605 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.3046382605
Directory /workspace/3.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/3.usbdev_freq_loclk.1837784433
Short name T1699
Test name
Test status
Simulation time 88114822176 ps
CPU time 131.71 seconds
Started Aug 02 05:27:28 PM PDT 24
Finished Aug 02 05:29:40 PM PDT 24
Peak memory 207652 kb
Host smart-fda15df0-3894-4560-a2dc-7ae4485c6721
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1837784433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.1837784433
Directory /workspace/3.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.1782335097
Short name T2918
Test name
Test status
Simulation time 111269487256 ps
CPU time 211.48 seconds
Started Aug 02 05:27:26 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 207628 kb
Host smart-64df0e24-6169-417f-b141-f8722e4bb148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782335097 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1782335097
Directory /workspace/3.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/3.usbdev_freq_phase.466876360
Short name T1227
Test name
Test status
Simulation time 83140777733 ps
CPU time 143.14 seconds
Started Aug 02 05:27:27 PM PDT 24
Finished Aug 02 05:29:50 PM PDT 24
Peak memory 207624 kb
Host smart-e8a88d83-e61b-40a9-a102-1faad088e547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46687
6360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.466876360
Directory /workspace/3.usbdev_freq_phase/latest


Test location /workspace/coverage/default/3.usbdev_in_iso.371852462
Short name T2652
Test name
Test status
Simulation time 244998478 ps
CPU time 1.17 seconds
Started Aug 02 05:27:27 PM PDT 24
Finished Aug 02 05:27:29 PM PDT 24
Peak memory 215784 kb
Host smart-7202ff18-e151-47db-8533-436e0ea721ac
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=371852462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.371852462
Directory /workspace/3.usbdev_in_iso/latest


Test location /workspace/coverage/default/3.usbdev_in_stall.2628637817
Short name T989
Test name
Test status
Simulation time 140264944 ps
CPU time 0.78 seconds
Started Aug 02 05:27:30 PM PDT 24
Finished Aug 02 05:27:31 PM PDT 24
Peak memory 207176 kb
Host smart-e71c850c-c554-43af-82a5-42e005306fb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26286
37817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2628637817
Directory /workspace/3.usbdev_in_stall/latest


Test location /workspace/coverage/default/3.usbdev_in_trans.473080707
Short name T1533
Test name
Test status
Simulation time 206102300 ps
CPU time 0.91 seconds
Started Aug 02 05:27:31 PM PDT 24
Finished Aug 02 05:27:32 PM PDT 24
Peak memory 207388 kb
Host smart-ca4eabf7-591f-4a39-99a8-9b14e3895788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47308
0707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.473080707
Directory /workspace/3.usbdev_in_trans/latest


Test location /workspace/coverage/default/3.usbdev_invalid_sync.1636282257
Short name T510
Test name
Test status
Simulation time 5029242495 ps
CPU time 140.1 seconds
Started Aug 02 05:27:30 PM PDT 24
Finished Aug 02 05:29:51 PM PDT 24
Peak memory 224044 kb
Host smart-60bf66b8-3ce9-412f-8716-dde2755107cd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1636282257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.1636282257
Directory /workspace/3.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/3.usbdev_iso_retraction.134994674
Short name T111
Test name
Test status
Simulation time 11480644323 ps
CPU time 145.88 seconds
Started Aug 02 05:27:26 PM PDT 24
Finished Aug 02 05:29:52 PM PDT 24
Peak memory 207708 kb
Host smart-623ba79f-3f5f-429e-94dd-7f564a0d41cf
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=134994674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.134994674
Directory /workspace/3.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/3.usbdev_link_in_err.2551379468
Short name T1274
Test name
Test status
Simulation time 212012275 ps
CPU time 0.97 seconds
Started Aug 02 05:27:31 PM PDT 24
Finished Aug 02 05:27:32 PM PDT 24
Peak memory 207388 kb
Host smart-6399c38b-6019-4869-9ff9-37a3d2461c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25513
79468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2551379468
Directory /workspace/3.usbdev_link_in_err/latest


Test location /workspace/coverage/default/3.usbdev_link_suspend.795357598
Short name T1220
Test name
Test status
Simulation time 5826652655 ps
CPU time 7.5 seconds
Started Aug 02 05:27:35 PM PDT 24
Finished Aug 02 05:27:43 PM PDT 24
Peak memory 215956 kb
Host smart-07b36b7e-ec79-4a79-8567-e7c32ba3d4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79535
7598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.795357598
Directory /workspace/3.usbdev_link_suspend/latest


Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1547630079
Short name T2639
Test name
Test status
Simulation time 4306061576 ps
CPU time 31.24 seconds
Started Aug 02 05:27:40 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 218048 kb
Host smart-1274b823-946c-48a7-9ef1-f64eea4152a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15476
30079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1547630079
Directory /workspace/3.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.3865862766
Short name T2085
Test name
Test status
Simulation time 2290394194 ps
CPU time 22.62 seconds
Started Aug 02 05:27:40 PM PDT 24
Finished Aug 02 05:28:03 PM PDT 24
Peak memory 224020 kb
Host smart-e6fc2ce5-261d-4bf2-ad8a-b188e240ad96
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3865862766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.3865862766
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1884998320
Short name T896
Test name
Test status
Simulation time 254777725 ps
CPU time 0.98 seconds
Started Aug 02 05:27:34 PM PDT 24
Finished Aug 02 05:27:36 PM PDT 24
Peak memory 207436 kb
Host smart-bef3d232-b7af-4d8a-9489-8d0b3b4bcc30
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1884998320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1884998320
Directory /workspace/3.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.493873503
Short name T595
Test name
Test status
Simulation time 206598359 ps
CPU time 0.96 seconds
Started Aug 02 05:27:40 PM PDT 24
Finished Aug 02 05:27:41 PM PDT 24
Peak memory 207392 kb
Host smart-f9dadea7-f337-4881-a6db-45bb85c51e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49387
3503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.493873503
Directory /workspace/3.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_max_non_iso_usb_traffic.1321470342
Short name T1730
Test name
Test status
Simulation time 2997326706 ps
CPU time 82.26 seconds
Started Aug 02 05:27:37 PM PDT 24
Finished Aug 02 05:29:00 PM PDT 24
Peak memory 217752 kb
Host smart-46d8ccd7-ebd0-4b33-9e15-61cfaec4a953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13214
70342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_non_iso_usb_traffic.1321470342
Directory /workspace/3.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.1448851838
Short name T127
Test name
Test status
Simulation time 2453311051 ps
CPU time 26.77 seconds
Started Aug 02 05:27:34 PM PDT 24
Finished Aug 02 05:28:01 PM PDT 24
Peak memory 224004 kb
Host smart-99239d48-cb79-42e0-95d1-5a8a758a92e0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1448851838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.1448851838
Directory /workspace/3.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.909994657
Short name T2274
Test name
Test status
Simulation time 1593185305 ps
CPU time 15.44 seconds
Started Aug 02 05:27:34 PM PDT 24
Finished Aug 02 05:27:50 PM PDT 24
Peak memory 217064 kb
Host smart-996dde33-e05e-460e-ba5f-49661c38d1c6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=909994657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.909994657
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3366183413
Short name T1291
Test name
Test status
Simulation time 160197088 ps
CPU time 0.87 seconds
Started Aug 02 05:27:34 PM PDT 24
Finished Aug 02 05:27:35 PM PDT 24
Peak memory 207352 kb
Host smart-a61c6534-50fa-48a2-a287-288e64161b7a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3366183413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3366183413
Directory /workspace/3.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1030867206
Short name T1224
Test name
Test status
Simulation time 176966088 ps
CPU time 0.83 seconds
Started Aug 02 05:27:35 PM PDT 24
Finished Aug 02 05:27:36 PM PDT 24
Peak memory 207316 kb
Host smart-bc468289-7644-4279-a3e7-92a7f83c8b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10308
67206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1030867206
Directory /workspace/3.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_nak_trans.36141746
Short name T149
Test name
Test status
Simulation time 229522024 ps
CPU time 0.92 seconds
Started Aug 02 05:27:33 PM PDT 24
Finished Aug 02 05:27:35 PM PDT 24
Peak memory 207352 kb
Host smart-5782084f-25f0-4dc4-833f-22c4afd76936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36141
746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.36141746
Directory /workspace/3.usbdev_nak_trans/latest


Test location /workspace/coverage/default/3.usbdev_out_iso.2058077124
Short name T1402
Test name
Test status
Simulation time 260221984 ps
CPU time 0.95 seconds
Started Aug 02 05:27:34 PM PDT 24
Finished Aug 02 05:27:36 PM PDT 24
Peak memory 207368 kb
Host smart-ddf8dd38-6cf8-4561-b05b-a84b57531bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20580
77124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2058077124
Directory /workspace/3.usbdev_out_iso/latest


Test location /workspace/coverage/default/3.usbdev_out_stall.3386292438
Short name T1862
Test name
Test status
Simulation time 154384879 ps
CPU time 0.85 seconds
Started Aug 02 05:27:34 PM PDT 24
Finished Aug 02 05:27:35 PM PDT 24
Peak memory 207352 kb
Host smart-312d3d98-2ec4-42b5-83f7-05ce85a531d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33862
92438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3386292438
Directory /workspace/3.usbdev_out_stall/latest


Test location /workspace/coverage/default/3.usbdev_out_trans_nak.3521031751
Short name T1066
Test name
Test status
Simulation time 203816560 ps
CPU time 0.9 seconds
Started Aug 02 05:27:33 PM PDT 24
Finished Aug 02 05:27:34 PM PDT 24
Peak memory 207360 kb
Host smart-4ce0e2d2-a470-4385-b171-c91c5cc61bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35210
31751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.3521031751
Directory /workspace/3.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2706031255
Short name T2474
Test name
Test status
Simulation time 226037702 ps
CPU time 0.9 seconds
Started Aug 02 05:27:33 PM PDT 24
Finished Aug 02 05:27:34 PM PDT 24
Peak memory 207392 kb
Host smart-f7854eea-ca32-41b6-acaa-e5088be073a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27060
31255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2706031255
Directory /workspace/3.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.718697241
Short name T1453
Test name
Test status
Simulation time 240413571 ps
CPU time 1.07 seconds
Started Aug 02 05:27:35 PM PDT 24
Finished Aug 02 05:27:36 PM PDT 24
Peak memory 207392 kb
Host smart-7dc7608e-5bd0-4e19-939f-3095a6aa109d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=718697241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.718697241
Directory /workspace/3.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3406152597
Short name T816
Test name
Test status
Simulation time 248542469 ps
CPU time 1.06 seconds
Started Aug 02 05:27:37 PM PDT 24
Finished Aug 02 05:27:39 PM PDT 24
Peak memory 207380 kb
Host smart-26603f1d-adab-454e-b33b-1294bb0496fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34061
52597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3406152597
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.814367697
Short name T316
Test name
Test status
Simulation time 147776343 ps
CPU time 0.85 seconds
Started Aug 02 05:27:37 PM PDT 24
Finished Aug 02 05:27:38 PM PDT 24
Peak memory 207396 kb
Host smart-c1af4f2c-1953-4e96-be39-0cb41330f7d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81436
7697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.814367697
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3203867418
Short name T868
Test name
Test status
Simulation time 44231330 ps
CPU time 0.7 seconds
Started Aug 02 05:27:33 PM PDT 24
Finished Aug 02 05:27:34 PM PDT 24
Peak memory 207324 kb
Host smart-a7946719-153c-4170-8ba0-2124ea42182a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32038
67418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3203867418
Directory /workspace/3.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3145512306
Short name T289
Test name
Test status
Simulation time 20437721502 ps
CPU time 49.31 seconds
Started Aug 02 05:27:34 PM PDT 24
Finished Aug 02 05:28:24 PM PDT 24
Peak memory 215932 kb
Host smart-84f0f27d-0629-47d4-9578-c521a5414b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31455
12306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3145512306
Directory /workspace/3.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/3.usbdev_pkt_received.3208683666
Short name T535
Test name
Test status
Simulation time 197059600 ps
CPU time 0.9 seconds
Started Aug 02 05:27:34 PM PDT 24
Finished Aug 02 05:27:35 PM PDT 24
Peak memory 207360 kb
Host smart-1a79fa96-7cbc-47ce-a379-aa323380454b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32086
83666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3208683666
Directory /workspace/3.usbdev_pkt_received/latest


Test location /workspace/coverage/default/3.usbdev_pkt_sent.115762370
Short name T2416
Test name
Test status
Simulation time 164758610 ps
CPU time 0.87 seconds
Started Aug 02 05:27:35 PM PDT 24
Finished Aug 02 05:27:36 PM PDT 24
Peak memory 207416 kb
Host smart-8aff351d-d3e0-4117-90b3-902141799fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11576
2370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.115762370
Directory /workspace/3.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.442561359
Short name T165
Test name
Test status
Simulation time 6865142311 ps
CPU time 67 seconds
Started Aug 02 05:27:38 PM PDT 24
Finished Aug 02 05:28:45 PM PDT 24
Peak memory 218184 kb
Host smart-c064620c-72b4-4686-b1b2-cd0702766621
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=442561359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.442561359
Directory /workspace/3.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.114184482
Short name T677
Test name
Test status
Simulation time 9755626104 ps
CPU time 181.63 seconds
Started Aug 02 05:27:37 PM PDT 24
Finished Aug 02 05:30:39 PM PDT 24
Peak memory 224016 kb
Host smart-57ebebdc-3111-44d7-9c32-6ae738f675cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=114184482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.114184482
Directory /workspace/3.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/3.usbdev_rand_suspends.1037329993
Short name T2060
Test name
Test status
Simulation time 9999311267 ps
CPU time 66.32 seconds
Started Aug 02 05:27:36 PM PDT 24
Finished Aug 02 05:28:42 PM PDT 24
Peak memory 223960 kb
Host smart-ea5ffa13-bfb2-4139-8c2a-ecf40517824c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037329993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.1037329993
Directory /workspace/3.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.3780820777
Short name T549
Test name
Test status
Simulation time 190196160 ps
CPU time 0.96 seconds
Started Aug 02 05:27:40 PM PDT 24
Finished Aug 02 05:27:41 PM PDT 24
Peak memory 207396 kb
Host smart-33390c6f-af29-405f-85dc-a3c16442d18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37808
20777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.3780820777
Directory /workspace/3.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2036473845
Short name T1659
Test name
Test status
Simulation time 185805527 ps
CPU time 0.88 seconds
Started Aug 02 05:27:40 PM PDT 24
Finished Aug 02 05:27:41 PM PDT 24
Peak memory 207324 kb
Host smart-42b1726c-3aab-410f-af90-7c65f25320ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20364
73845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2036473845
Directory /workspace/3.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3721111034
Short name T796
Test name
Test status
Simulation time 149316326 ps
CPU time 0.79 seconds
Started Aug 02 05:27:40 PM PDT 24
Finished Aug 02 05:27:41 PM PDT 24
Peak memory 207296 kb
Host smart-23950aca-3881-43b9-a28a-63e706e6fb0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37211
11034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3721111034
Directory /workspace/3.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/3.usbdev_rx_full.2121731009
Short name T521
Test name
Test status
Simulation time 392697686 ps
CPU time 1.36 seconds
Started Aug 02 05:27:39 PM PDT 24
Finished Aug 02 05:27:40 PM PDT 24
Peak memory 207320 kb
Host smart-b035ecde-8f5e-4a88-b209-bbfdf6497c7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21217
31009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_full.2121731009
Directory /workspace/3.usbdev_rx_full/latest


Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3347100519
Short name T79
Test name
Test status
Simulation time 197711639 ps
CPU time 0.95 seconds
Started Aug 02 05:27:37 PM PDT 24
Finished Aug 02 05:27:38 PM PDT 24
Peak memory 207340 kb
Host smart-d0a312d9-425d-457d-a454-6af75ba4180b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33471
00519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3347100519
Directory /workspace/3.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/3.usbdev_sec_cm.2033111837
Short name T221
Test name
Test status
Simulation time 394885377 ps
CPU time 1.15 seconds
Started Aug 02 05:27:45 PM PDT 24
Finished Aug 02 05:27:46 PM PDT 24
Peak memory 223592 kb
Host smart-e022e2db-f051-4f64-860d-4488908dacb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2033111837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.2033111837
Directory /workspace/3.usbdev_sec_cm/latest


Test location /workspace/coverage/default/3.usbdev_setup_priority.677579400
Short name T51
Test name
Test status
Simulation time 444341639 ps
CPU time 1.51 seconds
Started Aug 02 05:27:33 PM PDT 24
Finished Aug 02 05:27:35 PM PDT 24
Peak memory 207396 kb
Host smart-02081dfe-daf9-4228-964d-4f5cf0808de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67757
9400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.677579400
Directory /workspace/3.usbdev_setup_priority/latest


Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.1295083227
Short name T2593
Test name
Test status
Simulation time 316083787 ps
CPU time 1.09 seconds
Started Aug 02 05:27:35 PM PDT 24
Finished Aug 02 05:27:36 PM PDT 24
Peak memory 207296 kb
Host smart-0a42539b-fbdf-429e-aefd-e176942245c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12950
83227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.1295083227
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/3.usbdev_setup_stage.3051627644
Short name T974
Test name
Test status
Simulation time 151329826 ps
CPU time 0.83 seconds
Started Aug 02 05:27:43 PM PDT 24
Finished Aug 02 05:27:44 PM PDT 24
Peak memory 207384 kb
Host smart-146e1386-e690-499d-9e12-c8e922fdd1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30516
27644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3051627644
Directory /workspace/3.usbdev_setup_stage/latest


Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.2770405794
Short name T23
Test name
Test status
Simulation time 154282585 ps
CPU time 0.83 seconds
Started Aug 02 05:27:42 PM PDT 24
Finished Aug 02 05:27:43 PM PDT 24
Peak memory 207384 kb
Host smart-ae637e52-edf7-4889-9de3-841909691f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27704
05794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.2770405794
Directory /workspace/3.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/3.usbdev_smoke.3054993399
Short name T2070
Test name
Test status
Simulation time 216721356 ps
CPU time 1.04 seconds
Started Aug 02 05:27:43 PM PDT 24
Finished Aug 02 05:27:44 PM PDT 24
Peak memory 207308 kb
Host smart-908a278b-8746-4aa5-8e0d-dbeeac9cd284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30549
93399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.3054993399
Directory /workspace/3.usbdev_smoke/latest


Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3477810235
Short name T1172
Test name
Test status
Simulation time 1753849644 ps
CPU time 12.93 seconds
Started Aug 02 05:27:43 PM PDT 24
Finished Aug 02 05:27:56 PM PDT 24
Peak memory 223828 kb
Host smart-533e3cb9-0f44-4186-afbb-2cbf89932371
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3477810235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3477810235
Directory /workspace/3.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.347748608
Short name T2132
Test name
Test status
Simulation time 161596467 ps
CPU time 0.87 seconds
Started Aug 02 05:27:42 PM PDT 24
Finished Aug 02 05:27:43 PM PDT 24
Peak memory 207416 kb
Host smart-f04c63ce-c66c-436c-8b7f-d7d899215c44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34774
8608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.347748608
Directory /workspace/3.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/3.usbdev_stall_trans.93559712
Short name T2288
Test name
Test status
Simulation time 179323537 ps
CPU time 0.88 seconds
Started Aug 02 05:27:42 PM PDT 24
Finished Aug 02 05:27:43 PM PDT 24
Peak memory 207376 kb
Host smart-c6c96414-5498-4105-8046-77f4141f0420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93559
712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.93559712
Directory /workspace/3.usbdev_stall_trans/latest


Test location /workspace/coverage/default/3.usbdev_stream_len_max.1095381497
Short name T1140
Test name
Test status
Simulation time 879345852 ps
CPU time 2.51 seconds
Started Aug 02 05:27:43 PM PDT 24
Finished Aug 02 05:27:46 PM PDT 24
Peak memory 207476 kb
Host smart-777a416b-9227-48c3-9871-55f0f8e12bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10953
81497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1095381497
Directory /workspace/3.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/3.usbdev_streaming_out.2764341553
Short name T228
Test name
Test status
Simulation time 2257320349 ps
CPU time 22.41 seconds
Started Aug 02 05:27:43 PM PDT 24
Finished Aug 02 05:28:06 PM PDT 24
Peak memory 223968 kb
Host smart-13cc1307-631f-4638-82a0-3c457df1b469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27643
41553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2764341553
Directory /workspace/3.usbdev_streaming_out/latest


Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1577007905
Short name T80
Test name
Test status
Simulation time 6705690480 ps
CPU time 188.77 seconds
Started Aug 02 05:27:44 PM PDT 24
Finished Aug 02 05:30:53 PM PDT 24
Peak memory 218224 kb
Host smart-9242f394-992c-4f11-abd6-563d4dd7362b
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577007905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1577007905
Directory /workspace/3.usbdev_stress_usb_traffic/latest


Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.3185527607
Short name T1669
Test name
Test status
Simulation time 1934108146 ps
CPU time 12.98 seconds
Started Aug 02 05:27:27 PM PDT 24
Finished Aug 02 05:27:40 PM PDT 24
Peak memory 207536 kb
Host smart-08c38e2e-af13-4c59-a5b8-ce8ababbd096
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185527607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host
_handshake.3185527607
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/30.usbdev_alert_test.4196548453
Short name T2565
Test name
Test status
Simulation time 47468813 ps
CPU time 0.74 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:32:26 PM PDT 24
Peak memory 207440 kb
Host smart-3cc3ffa4-f4fb-40cc-89fc-daa4ce0d2265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4196548453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.4196548453
Directory /workspace/30.usbdev_alert_test/latest


Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.3256047421
Short name T1885
Test name
Test status
Simulation time 5143702233 ps
CPU time 7.24 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 215668 kb
Host smart-beae7736-055d-43d1-a522-77953a498051
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256047421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_a
on_wake_disconnect.3256047421
Directory /workspace/30.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3989403550
Short name T1602
Test name
Test status
Simulation time 19883846804 ps
CPU time 22.94 seconds
Started Aug 02 05:32:27 PM PDT 24
Finished Aug 02 05:32:51 PM PDT 24
Peak memory 207680 kb
Host smart-9d5bad16-e237-4e6a-8c02-618cffdea751
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989403550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3989403550
Directory /workspace/30.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.527104977
Short name T1529
Test name
Test status
Simulation time 30520024600 ps
CPU time 37.85 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:33:01 PM PDT 24
Peak memory 207692 kb
Host smart-10541794-8b0b-4787-b3d9-8f981d8da422
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527104977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_ao
n_wake_resume.527104977
Directory /workspace/30.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/30.usbdev_av_buffer.373305974
Short name T740
Test name
Test status
Simulation time 200117504 ps
CPU time 0.96 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 207408 kb
Host smart-56c10e88-4c50-499d-94d1-ff4f77f0ec43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37330
5974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.373305974
Directory /workspace/30.usbdev_av_buffer/latest


Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2257269725
Short name T1246
Test name
Test status
Simulation time 145020318 ps
CPU time 0.83 seconds
Started Aug 02 05:32:12 PM PDT 24
Finished Aug 02 05:32:13 PM PDT 24
Peak memory 207296 kb
Host smart-b0955c1d-a0d4-47e4-bb11-7937cd50bd5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22572
69725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2257269725
Directory /workspace/30.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.296165171
Short name T2772
Test name
Test status
Simulation time 462147244 ps
CPU time 1.55 seconds
Started Aug 02 05:32:26 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 207344 kb
Host smart-a4db784c-6d03-4dd4-8e98-fc8f289078d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29616
5171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.296165171
Directory /workspace/30.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.908068863
Short name T1915
Test name
Test status
Simulation time 943874560 ps
CPU time 2.42 seconds
Started Aug 02 05:32:00 PM PDT 24
Finished Aug 02 05:32:03 PM PDT 24
Peak memory 207624 kb
Host smart-630ff0b5-fcf4-4da4-9263-6729fe3fc6d7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=908068863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.908068863
Directory /workspace/30.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/30.usbdev_device_address.3158130315
Short name T2324
Test name
Test status
Simulation time 55104055254 ps
CPU time 78.47 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:33:41 PM PDT 24
Peak memory 207716 kb
Host smart-6a805d12-3c8a-4089-a767-6a1a39162795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31581
30315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.3158130315
Directory /workspace/30.usbdev_device_address/latest


Test location /workspace/coverage/default/30.usbdev_device_timeout.2241781051
Short name T1500
Test name
Test status
Simulation time 4959790317 ps
CPU time 32.87 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:46 PM PDT 24
Peak memory 207664 kb
Host smart-14dbf1b5-71ab-44c3-94ef-4225e7ac64b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241781051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_timeout.2241781051
Directory /workspace/30.usbdev_device_timeout/latest


Test location /workspace/coverage/default/30.usbdev_disable_endpoint.1570298939
Short name T1147
Test name
Test status
Simulation time 389460882 ps
CPU time 1.3 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 207320 kb
Host smart-b8d4ed04-b506-4506-a4a7-2d3fd550b621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15702
98939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.1570298939
Directory /workspace/30.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/30.usbdev_disconnected.3168511875
Short name T2451
Test name
Test status
Simulation time 133004993 ps
CPU time 0.82 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 207268 kb
Host smart-0a0bdb62-49ed-492d-a0ad-5b7a7a0cfec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31685
11875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3168511875
Directory /workspace/30.usbdev_disconnected/latest


Test location /workspace/coverage/default/30.usbdev_enable.2553252683
Short name T21
Test name
Test status
Simulation time 51400791 ps
CPU time 0.71 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:10 PM PDT 24
Peak memory 207352 kb
Host smart-5e855690-f5ed-47d6-b834-f3ade54e1fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25532
52683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2553252683
Directory /workspace/30.usbdev_enable/latest


Test location /workspace/coverage/default/30.usbdev_endpoint_access.4124456884
Short name T711
Test name
Test status
Simulation time 756298863 ps
CPU time 2.15 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:12 PM PDT 24
Peak memory 207688 kb
Host smart-d1271e49-ceaa-4302-b418-34c048d01066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41244
56884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.4124456884
Directory /workspace/30.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/30.usbdev_endpoint_types.2077369113
Short name T474
Test name
Test status
Simulation time 527166795 ps
CPU time 1.52 seconds
Started Aug 02 05:32:10 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 207368 kb
Host smart-231dd3a0-6511-4c60-ae65-9dd4401ae7c0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2077369113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_types.2077369113
Directory /workspace/30.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/30.usbdev_fifo_rst.1359543755
Short name T1027
Test name
Test status
Simulation time 366028749 ps
CPU time 2.41 seconds
Started Aug 02 05:32:18 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 207512 kb
Host smart-85d773d1-ac2a-49d0-a46f-84e18ee3a22c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13595
43755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1359543755
Directory /workspace/30.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/30.usbdev_in_iso.1888841978
Short name T2301
Test name
Test status
Simulation time 229039699 ps
CPU time 1.01 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:24 PM PDT 24
Peak memory 207576 kb
Host smart-c55bfe85-51ac-4e8a-b9d5-7363ac8e2d06
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1888841978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1888841978
Directory /workspace/30.usbdev_in_iso/latest


Test location /workspace/coverage/default/30.usbdev_in_stall.2205898489
Short name T2433
Test name
Test status
Simulation time 181799271 ps
CPU time 0.85 seconds
Started Aug 02 05:32:31 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207384 kb
Host smart-1b35116a-e1dc-4159-8b54-1d1e090b5ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22058
98489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2205898489
Directory /workspace/30.usbdev_in_stall/latest


Test location /workspace/coverage/default/30.usbdev_in_trans.3368063259
Short name T790
Test name
Test status
Simulation time 194191052 ps
CPU time 0.93 seconds
Started Aug 02 05:32:13 PM PDT 24
Finished Aug 02 05:32:14 PM PDT 24
Peak memory 207364 kb
Host smart-e6cc6799-ec99-4f19-9e66-d84522c39a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33680
63259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3368063259
Directory /workspace/30.usbdev_in_trans/latest


Test location /workspace/coverage/default/30.usbdev_invalid_sync.931825351
Short name T2795
Test name
Test status
Simulation time 2652242354 ps
CPU time 25.74 seconds
Started Aug 02 05:32:20 PM PDT 24
Finished Aug 02 05:32:46 PM PDT 24
Peak memory 217708 kb
Host smart-d2c8b2fe-9b0d-4df8-b5d5-4da556380ec4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=931825351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.931825351
Directory /workspace/30.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/30.usbdev_iso_retraction.3790642602
Short name T2697
Test name
Test status
Simulation time 5587322029 ps
CPU time 68.3 seconds
Started Aug 02 05:32:10 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207680 kb
Host smart-515c3456-458b-4f96-89e5-aae4afc3ed4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3790642602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.3790642602
Directory /workspace/30.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/30.usbdev_link_in_err.2233985820
Short name T2431
Test name
Test status
Simulation time 207173216 ps
CPU time 0.93 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:32:22 PM PDT 24
Peak memory 207404 kb
Host smart-a6682f54-0aaa-47e6-9ecf-6f5fcf84330f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22339
85820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2233985820
Directory /workspace/30.usbdev_link_in_err/latest


Test location /workspace/coverage/default/30.usbdev_link_resume.2844883613
Short name T2049
Test name
Test status
Simulation time 8574120357 ps
CPU time 12.69 seconds
Started Aug 02 05:32:17 PM PDT 24
Finished Aug 02 05:32:29 PM PDT 24
Peak memory 207668 kb
Host smart-fdc2f0b7-6f2b-4fcc-83db-9e62a52f5548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28448
83613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2844883613
Directory /workspace/30.usbdev_link_resume/latest


Test location /workspace/coverage/default/30.usbdev_link_suspend.1572900172
Short name T120
Test name
Test status
Simulation time 8999601449 ps
CPU time 12.54 seconds
Started Aug 02 05:32:34 PM PDT 24
Finished Aug 02 05:32:47 PM PDT 24
Peak memory 207728 kb
Host smart-7bdf86be-e26f-48d1-b82d-93028136a3cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15729
00172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1572900172
Directory /workspace/30.usbdev_link_suspend/latest


Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1379410537
Short name T874
Test name
Test status
Simulation time 3656032257 ps
CPU time 26.2 seconds
Started Aug 02 05:32:09 PM PDT 24
Finished Aug 02 05:32:35 PM PDT 24
Peak memory 224004 kb
Host smart-09050da6-3253-477b-b4d8-3cb67a0f5069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13794
10537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1379410537
Directory /workspace/30.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.411844819
Short name T609
Test name
Test status
Simulation time 1818997988 ps
CPU time 12.95 seconds
Started Aug 02 05:32:27 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 207564 kb
Host smart-2a876554-e0bc-4759-84dd-4eab6f5edeae
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=411844819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.411844819
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.284909691
Short name T782
Test name
Test status
Simulation time 272688140 ps
CPU time 0.97 seconds
Started Aug 02 05:32:17 PM PDT 24
Finished Aug 02 05:32:18 PM PDT 24
Peak memory 207404 kb
Host smart-cbef19cd-0b50-40b4-a3c2-8f914b81db55
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=284909691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.284909691
Directory /workspace/30.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2771077280
Short name T1625
Test name
Test status
Simulation time 189405210 ps
CPU time 1.04 seconds
Started Aug 02 05:32:29 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 207428 kb
Host smart-efb1e8ed-3166-42aa-a935-c4af0eb609fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27710
77280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2771077280
Directory /workspace/30.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3660167110
Short name T168
Test name
Test status
Simulation time 2286241425 ps
CPU time 61.71 seconds
Started Aug 02 05:32:34 PM PDT 24
Finished Aug 02 05:33:36 PM PDT 24
Peak memory 217416 kb
Host smart-b9d574b6-7bff-4ad5-9375-0d42f8f912e4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3660167110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3660167110
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.2083869277
Short name T1506
Test name
Test status
Simulation time 174975840 ps
CPU time 0.88 seconds
Started Aug 02 05:32:08 PM PDT 24
Finished Aug 02 05:32:09 PM PDT 24
Peak memory 207364 kb
Host smart-76940416-816b-4d23-af61-a1ccfb827ecc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2083869277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.2083869277
Directory /workspace/30.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.699676063
Short name T1566
Test name
Test status
Simulation time 154578826 ps
CPU time 0.84 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 207432 kb
Host smart-ab44edf6-a343-475c-a883-83e2a7f79d30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69967
6063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.699676063
Directory /workspace/30.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_nak_trans.3592573682
Short name T155
Test name
Test status
Simulation time 190139933 ps
CPU time 0.97 seconds
Started Aug 02 05:32:18 PM PDT 24
Finished Aug 02 05:32:19 PM PDT 24
Peak memory 207388 kb
Host smart-1eb369a3-28a4-4fff-8221-b7eea3052cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35925
73682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3592573682
Directory /workspace/30.usbdev_nak_trans/latest


Test location /workspace/coverage/default/30.usbdev_out_iso.2295913406
Short name T1747
Test name
Test status
Simulation time 194766367 ps
CPU time 0.92 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 207316 kb
Host smart-d1bd0af5-da2c-422b-8e1f-8bd76774cdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22959
13406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.2295913406
Directory /workspace/30.usbdev_out_iso/latest


Test location /workspace/coverage/default/30.usbdev_out_stall.3136943916
Short name T2237
Test name
Test status
Simulation time 182464373 ps
CPU time 0.92 seconds
Started Aug 02 05:32:07 PM PDT 24
Finished Aug 02 05:32:08 PM PDT 24
Peak memory 207380 kb
Host smart-cbe26e8a-be2b-48a0-a8a5-e760ab2eeb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31369
43916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3136943916
Directory /workspace/30.usbdev_out_stall/latest


Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1064423533
Short name T1211
Test name
Test status
Simulation time 165376889 ps
CPU time 0.9 seconds
Started Aug 02 05:32:10 PM PDT 24
Finished Aug 02 05:32:11 PM PDT 24
Peak memory 207404 kb
Host smart-f9a9bb7d-945f-404d-b9ef-4e1388fdb521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10644
23533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1064423533
Directory /workspace/30.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3517548548
Short name T2548
Test name
Test status
Simulation time 156436832 ps
CPU time 0.9 seconds
Started Aug 02 05:32:07 PM PDT 24
Finished Aug 02 05:32:08 PM PDT 24
Peak memory 207312 kb
Host smart-95621e72-4c0b-44a1-bfae-5b1c5d9f256b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35175
48548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3517548548
Directory /workspace/30.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3251603138
Short name T1514
Test name
Test status
Simulation time 260888789 ps
CPU time 1.05 seconds
Started Aug 02 05:32:16 PM PDT 24
Finished Aug 02 05:32:17 PM PDT 24
Peak memory 207408 kb
Host smart-40119395-0669-40ee-9277-4e82e56cb672
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3251603138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3251603138
Directory /workspace/30.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.1194111414
Short name T710
Test name
Test status
Simulation time 221358849 ps
CPU time 0.98 seconds
Started Aug 02 05:32:16 PM PDT 24
Finished Aug 02 05:32:18 PM PDT 24
Peak memory 207360 kb
Host smart-a7e9543b-8a50-4ac1-8db1-bb34d0cd8031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11941
11414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.1194111414
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2114196538
Short name T2854
Test name
Test status
Simulation time 91596911 ps
CPU time 0.72 seconds
Started Aug 02 05:32:20 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 207316 kb
Host smart-b78edb2f-4dcc-4847-b1bc-9c32c88f01da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21141
96538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2114196538
Directory /workspace/30.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/30.usbdev_pkt_buffer.610450170
Short name T287
Test name
Test status
Simulation time 15799766088 ps
CPU time 39.47 seconds
Started Aug 02 05:32:06 PM PDT 24
Finished Aug 02 05:32:46 PM PDT 24
Peak memory 215840 kb
Host smart-a0d5d95e-61aa-45fd-a93d-97a2d37b345f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61045
0170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.610450170
Directory /workspace/30.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/30.usbdev_pkt_received.3804716562
Short name T1892
Test name
Test status
Simulation time 161367744 ps
CPU time 0.86 seconds
Started Aug 02 05:32:20 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 207392 kb
Host smart-f94e9b46-c47d-4e5b-9feb-b290504e6f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38047
16562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3804716562
Directory /workspace/30.usbdev_pkt_received/latest


Test location /workspace/coverage/default/30.usbdev_pkt_sent.1886379250
Short name T1483
Test name
Test status
Simulation time 237477338 ps
CPU time 0.93 seconds
Started Aug 02 05:32:35 PM PDT 24
Finished Aug 02 05:32:36 PM PDT 24
Peak memory 207380 kb
Host smart-fc7c5d42-bc5d-4d2b-bb7e-567ecc2fc26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18863
79250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1886379250
Directory /workspace/30.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.2327122483
Short name T2275
Test name
Test status
Simulation time 240430195 ps
CPU time 1.04 seconds
Started Aug 02 05:32:27 PM PDT 24
Finished Aug 02 05:32:29 PM PDT 24
Peak memory 207352 kb
Host smart-017d0edf-a468-47e4-bba6-11dd36e4774d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23271
22483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2327122483
Directory /workspace/30.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.4175803895
Short name T615
Test name
Test status
Simulation time 179093328 ps
CPU time 0.93 seconds
Started Aug 02 05:32:32 PM PDT 24
Finished Aug 02 05:32:33 PM PDT 24
Peak memory 207328 kb
Host smart-88b1f57b-7378-44ae-b354-6146040be930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41758
03895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.4175803895
Directory /workspace/30.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/30.usbdev_rx_crc_err.400951642
Short name T1061
Test name
Test status
Simulation time 158668143 ps
CPU time 0.87 seconds
Started Aug 02 05:32:27 PM PDT 24
Finished Aug 02 05:32:28 PM PDT 24
Peak memory 207340 kb
Host smart-63f612e6-2016-47ab-bd3e-33613fd7a825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40095
1642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.400951642
Directory /workspace/30.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/30.usbdev_rx_full.3813860742
Short name T3072
Test name
Test status
Simulation time 378765752 ps
CPU time 1.32 seconds
Started Aug 02 05:32:12 PM PDT 24
Finished Aug 02 05:32:14 PM PDT 24
Peak memory 207360 kb
Host smart-2acadb6a-22c5-425f-98e2-cd1aebc5b0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38138
60742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_full.3813860742
Directory /workspace/30.usbdev_rx_full/latest


Test location /workspace/coverage/default/30.usbdev_setup_stage.1015564667
Short name T2794
Test name
Test status
Simulation time 149874824 ps
CPU time 0.87 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 207368 kb
Host smart-6f61f3a5-d447-4272-8b42-bd1f09e82fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10155
64667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1015564667
Directory /workspace/30.usbdev_setup_stage/latest


Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.1101304504
Short name T1269
Test name
Test status
Simulation time 145697323 ps
CPU time 0.85 seconds
Started Aug 02 05:32:18 PM PDT 24
Finished Aug 02 05:32:19 PM PDT 24
Peak memory 207412 kb
Host smart-99a3d619-c205-4af4-bbb7-d68ccecb320f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11013
04504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.1101304504
Directory /workspace/30.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/30.usbdev_smoke.2002914790
Short name T1302
Test name
Test status
Simulation time 212554478 ps
CPU time 0.98 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 207400 kb
Host smart-9a0d8a0a-42ad-4f3a-995d-d015e6b3d03b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20029
14790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2002914790
Directory /workspace/30.usbdev_smoke/latest


Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.647531156
Short name T1799
Test name
Test status
Simulation time 2555858386 ps
CPU time 24.98 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:47 PM PDT 24
Peak memory 217684 kb
Host smart-b686d591-e311-4143-8ec8-55860008e339
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=647531156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.647531156
Directory /workspace/30.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2856605183
Short name T1251
Test name
Test status
Simulation time 164537862 ps
CPU time 0.88 seconds
Started Aug 02 05:32:17 PM PDT 24
Finished Aug 02 05:32:18 PM PDT 24
Peak memory 207360 kb
Host smart-38fde9be-6a23-4bed-bf5b-8342bf8194d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28566
05183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2856605183
Directory /workspace/30.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/30.usbdev_stall_trans.3598101285
Short name T1612
Test name
Test status
Simulation time 194412807 ps
CPU time 0.88 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 207444 kb
Host smart-f62829cc-a09f-4cb1-83fb-143fab0e498e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35981
01285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.3598101285
Directory /workspace/30.usbdev_stall_trans/latest


Test location /workspace/coverage/default/30.usbdev_stream_len_max.3551753514
Short name T2361
Test name
Test status
Simulation time 1324321080 ps
CPU time 2.75 seconds
Started Aug 02 05:32:28 PM PDT 24
Finished Aug 02 05:32:31 PM PDT 24
Peak memory 207540 kb
Host smart-8e80ca37-abb6-4357-86e2-a46e0580cc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35517
53514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3551753514
Directory /workspace/30.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/30.usbdev_streaming_out.2873968709
Short name T881
Test name
Test status
Simulation time 3710131835 ps
CPU time 35.47 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:55 PM PDT 24
Peak memory 217608 kb
Host smart-0a5b74dc-5026-4a99-8bd7-9243267c0671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28739
68709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2873968709
Directory /workspace/30.usbdev_streaming_out/latest


Test location /workspace/coverage/default/30.usbdev_timeout_missing_host_handshake.344170302
Short name T1773
Test name
Test status
Simulation time 432671081 ps
CPU time 8.38 seconds
Started Aug 02 05:32:03 PM PDT 24
Finished Aug 02 05:32:12 PM PDT 24
Peak memory 207568 kb
Host smart-3a091208-343e-433f-94d7-ba8115c93a4e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344170302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_timeout_missing_host
_handshake.344170302
Directory /workspace/30.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/31.usbdev_alert_test.1972489645
Short name T669
Test name
Test status
Simulation time 78847096 ps
CPU time 0.72 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 207448 kb
Host smart-05d25464-3a02-47dd-828f-99ee5e8c2919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1972489645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1972489645
Directory /workspace/31.usbdev_alert_test/latest


Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3350949488
Short name T15
Test name
Test status
Simulation time 9537189115 ps
CPU time 13.04 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207628 kb
Host smart-5ffe3cd6-30fe-4531-a994-3c9796b80662
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350949488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_disconnect.3350949488
Directory /workspace/31.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1291634181
Short name T1057
Test name
Test status
Simulation time 21373956129 ps
CPU time 23.57 seconds
Started Aug 02 05:32:42 PM PDT 24
Finished Aug 02 05:33:06 PM PDT 24
Peak memory 207692 kb
Host smart-7ce0b150-dd78-471b-8959-1f81279d8aa6
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291634181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1291634181
Directory /workspace/31.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3703443998
Short name T2883
Test name
Test status
Simulation time 25885545993 ps
CPU time 31.46 seconds
Started Aug 02 05:32:20 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 215892 kb
Host smart-253a8fc9-5f68-4bd1-bacc-f744e3eb264b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703443998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_a
on_wake_resume.3703443998
Directory /workspace/31.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/31.usbdev_av_buffer.3296246180
Short name T3030
Test name
Test status
Simulation time 157996561 ps
CPU time 0.88 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 207412 kb
Host smart-57088350-d6e8-4614-a28c-7f3471078793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32962
46180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3296246180
Directory /workspace/31.usbdev_av_buffer/latest


Test location /workspace/coverage/default/31.usbdev_bitstuff_err.3947854033
Short name T2668
Test name
Test status
Simulation time 195797396 ps
CPU time 0.89 seconds
Started Aug 02 05:32:53 PM PDT 24
Finished Aug 02 05:32:54 PM PDT 24
Peak memory 207268 kb
Host smart-0339de9f-9036-4386-bae3-46a44969b5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39478
54033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.3947854033
Directory /workspace/31.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1709579298
Short name T1756
Test name
Test status
Simulation time 278406372 ps
CPU time 1.07 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 207356 kb
Host smart-dcfaefea-50ac-4c58-9f09-043772185e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17095
79298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1709579298
Directory /workspace/31.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.4187829074
Short name T1378
Test name
Test status
Simulation time 620947035 ps
CPU time 1.74 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 207368 kb
Host smart-a443e9de-a7f5-403a-85db-70599e94229c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4187829074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.4187829074
Directory /workspace/31.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/31.usbdev_device_address.1991996300
Short name T1472
Test name
Test status
Simulation time 16937783358 ps
CPU time 30.83 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:32:56 PM PDT 24
Peak memory 207744 kb
Host smart-c1891b9a-9598-4c6f-bc67-509f4341ac6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19919
96300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1991996300
Directory /workspace/31.usbdev_device_address/latest


Test location /workspace/coverage/default/31.usbdev_device_timeout.3771012910
Short name T1728
Test name
Test status
Simulation time 3424445277 ps
CPU time 28.46 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:50 PM PDT 24
Peak memory 207744 kb
Host smart-05bb958d-93cf-4463-bee8-cb590394073c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771012910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_timeout.3771012910
Directory /workspace/31.usbdev_device_timeout/latest


Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3505690970
Short name T1128
Test name
Test status
Simulation time 826197959 ps
CPU time 1.97 seconds
Started Aug 02 05:32:30 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207344 kb
Host smart-21ca31b1-e8ff-48c5-a48e-3b06df87b1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35056
90970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3505690970
Directory /workspace/31.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/31.usbdev_enable.4128634255
Short name T2558
Test name
Test status
Simulation time 33206118 ps
CPU time 0.69 seconds
Started Aug 02 05:32:43 PM PDT 24
Finished Aug 02 05:32:44 PM PDT 24
Peak memory 207288 kb
Host smart-a3749fbb-1221-4917-b8c1-1600d59f70d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41286
34255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.4128634255
Directory /workspace/31.usbdev_enable/latest


Test location /workspace/coverage/default/31.usbdev_endpoint_access.2187628076
Short name T3027
Test name
Test status
Simulation time 916814101 ps
CPU time 2.35 seconds
Started Aug 02 05:32:20 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207552 kb
Host smart-488f3300-47f6-47a5-aa76-a339738e42ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21876
28076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2187628076
Directory /workspace/31.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/31.usbdev_endpoint_types.3716220871
Short name T478
Test name
Test status
Simulation time 559593028 ps
CPU time 1.52 seconds
Started Aug 02 05:32:31 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207420 kb
Host smart-9599acfe-ba00-41a1-bf3a-298120c05b10
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3716220871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_types.3716220871
Directory /workspace/31.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/31.usbdev_fifo_rst.2792397778
Short name T1053
Test name
Test status
Simulation time 243371423 ps
CPU time 1.73 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:32:41 PM PDT 24
Peak memory 207592 kb
Host smart-d44ae741-fc44-4281-84e8-ced4a481d3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
97778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.2792397778
Directory /workspace/31.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/31.usbdev_in_iso.3709756098
Short name T1275
Test name
Test status
Simulation time 182011485 ps
CPU time 0.92 seconds
Started Aug 02 05:32:42 PM PDT 24
Finished Aug 02 05:32:43 PM PDT 24
Peak memory 215736 kb
Host smart-a99a64f9-7460-48a9-a816-70237b5bc65d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3709756098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.3709756098
Directory /workspace/31.usbdev_in_iso/latest


Test location /workspace/coverage/default/31.usbdev_in_stall.176572826
Short name T933
Test name
Test status
Simulation time 159773553 ps
CPU time 0.81 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:32:45 PM PDT 24
Peak memory 207364 kb
Host smart-06c21d2a-ab68-4b0e-809a-1f633588db0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17657
2826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.176572826
Directory /workspace/31.usbdev_in_stall/latest


Test location /workspace/coverage/default/31.usbdev_in_trans.1609577842
Short name T2999
Test name
Test status
Simulation time 165043820 ps
CPU time 0.88 seconds
Started Aug 02 05:32:35 PM PDT 24
Finished Aug 02 05:32:36 PM PDT 24
Peak memory 207412 kb
Host smart-944385f6-29a4-477c-8ece-542d9829fa59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16095
77842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.1609577842
Directory /workspace/31.usbdev_in_trans/latest


Test location /workspace/coverage/default/31.usbdev_invalid_sync.1793010206
Short name T1073
Test name
Test status
Simulation time 3020909528 ps
CPU time 22.55 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:32:44 PM PDT 24
Peak memory 224000 kb
Host smart-6c612d1c-f4f2-4ea0-83b0-73ca59ab5d84
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1793010206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.1793010206
Directory /workspace/31.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/31.usbdev_iso_retraction.1638927507
Short name T261
Test name
Test status
Simulation time 11749415489 ps
CPU time 72.22 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:33:37 PM PDT 24
Peak memory 207600 kb
Host smart-83b2f647-4d08-4feb-9160-246b11e954b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1638927507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.1638927507
Directory /workspace/31.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/31.usbdev_link_in_err.609876025
Short name T83
Test name
Test status
Simulation time 186031266 ps
CPU time 0.95 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207248 kb
Host smart-f6e7ff88-1fcb-475a-ae7d-70770514e689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60987
6025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.609876025
Directory /workspace/31.usbdev_link_in_err/latest


Test location /workspace/coverage/default/31.usbdev_link_resume.1749552424
Short name T2802
Test name
Test status
Simulation time 27427104865 ps
CPU time 41.2 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:33:03 PM PDT 24
Peak memory 215976 kb
Host smart-e979e135-a8ba-469a-9ff0-1006f3f699da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17495
52424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1749552424
Directory /workspace/31.usbdev_link_resume/latest


Test location /workspace/coverage/default/31.usbdev_link_suspend.440570105
Short name T906
Test name
Test status
Simulation time 9378741580 ps
CPU time 10.63 seconds
Started Aug 02 05:32:38 PM PDT 24
Finished Aug 02 05:32:49 PM PDT 24
Peak memory 207712 kb
Host smart-8d232dba-79ab-4af5-bf39-0123dbb1f797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44057
0105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.440570105
Directory /workspace/31.usbdev_link_suspend/latest


Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.1753750487
Short name T851
Test name
Test status
Simulation time 4756266544 ps
CPU time 35.19 seconds
Started Aug 02 05:32:40 PM PDT 24
Finished Aug 02 05:33:15 PM PDT 24
Peak memory 224120 kb
Host smart-89ff510e-3667-418b-9891-158f772cd292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17537
50487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.1753750487
Directory /workspace/31.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1946729697
Short name T1831
Test name
Test status
Simulation time 3851442573 ps
CPU time 107.48 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 217440 kb
Host smart-30113cef-2722-41ac-a184-e935e6ff0c03
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1946729697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1946729697
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.1858651566
Short name T3017
Test name
Test status
Simulation time 284332263 ps
CPU time 1.1 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 207440 kb
Host smart-b5d96013-0553-42bb-b3fc-cdc336e031c1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1858651566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.1858651566
Directory /workspace/31.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1131261083
Short name T2449
Test name
Test status
Simulation time 195355383 ps
CPU time 0.93 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207432 kb
Host smart-a3f57723-19c1-41ff-9f02-5ab95512dc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11312
61083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1131261083
Directory /workspace/31.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.4048081614
Short name T705
Test name
Test status
Simulation time 2743020319 ps
CPU time 25.06 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:32:51 PM PDT 24
Peak memory 217556 kb
Host smart-8721aa2d-c055-4e30-b378-7ac82bb56c42
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4048081614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.4048081614
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.234728309
Short name T1078
Test name
Test status
Simulation time 152519972 ps
CPU time 0.84 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:32:26 PM PDT 24
Peak memory 207380 kb
Host smart-37d97bc4-e73b-49b0-ac82-9c57222f5d31
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=234728309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.234728309
Directory /workspace/31.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.4137414591
Short name T1318
Test name
Test status
Simulation time 155686914 ps
CPU time 0.86 seconds
Started Aug 02 05:32:28 PM PDT 24
Finished Aug 02 05:32:29 PM PDT 24
Peak memory 207368 kb
Host smart-68b0f85c-4685-431f-acd5-770b7ab97c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41374
14591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.4137414591
Directory /workspace/31.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_nak_trans.3614901076
Short name T138
Test name
Test status
Simulation time 228870996 ps
CPU time 1 seconds
Started Aug 02 05:32:49 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 207396 kb
Host smart-9212939e-e4e8-4bdd-bdc7-cf299bea3077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36149
01076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3614901076
Directory /workspace/31.usbdev_nak_trans/latest


Test location /workspace/coverage/default/31.usbdev_out_iso.2649185088
Short name T2309
Test name
Test status
Simulation time 176232882 ps
CPU time 0.88 seconds
Started Aug 02 05:32:29 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 207208 kb
Host smart-06935102-8471-4e45-9783-826e43fb6969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26491
85088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2649185088
Directory /workspace/31.usbdev_out_iso/latest


Test location /workspace/coverage/default/31.usbdev_out_stall.701481601
Short name T1527
Test name
Test status
Simulation time 226895542 ps
CPU time 0.91 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 207392 kb
Host smart-99bc4afc-d871-4608-be52-efec82260408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70148
1601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.701481601
Directory /workspace/31.usbdev_out_stall/latest


Test location /workspace/coverage/default/31.usbdev_out_trans_nak.1077738789
Short name T613
Test name
Test status
Simulation time 174197818 ps
CPU time 0.95 seconds
Started Aug 02 05:32:18 PM PDT 24
Finished Aug 02 05:32:19 PM PDT 24
Peak memory 207416 kb
Host smart-cf4583b8-2cf0-4b65-af31-dac45e74a003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10777
38789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.1077738789
Directory /workspace/31.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3885966834
Short name T1508
Test name
Test status
Simulation time 156054108 ps
CPU time 0.85 seconds
Started Aug 02 05:32:35 PM PDT 24
Finished Aug 02 05:32:36 PM PDT 24
Peak memory 207352 kb
Host smart-a74a69b2-e502-4353-b65b-64a50b45f93e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38859
66834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3885966834
Directory /workspace/31.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.3583995451
Short name T1157
Test name
Test status
Simulation time 287704363 ps
CPU time 1.1 seconds
Started Aug 02 05:32:16 PM PDT 24
Finished Aug 02 05:32:17 PM PDT 24
Peak memory 207408 kb
Host smart-f67c6f02-7772-4dc8-8109-3457b6717db8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3583995451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.3583995451
Directory /workspace/31.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2868723744
Short name T2078
Test name
Test status
Simulation time 163741768 ps
CPU time 0.84 seconds
Started Aug 02 05:32:26 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 207328 kb
Host smart-21183165-90b2-424c-882f-3ef24d263dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28687
23744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2868723744
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.4009554214
Short name T2257
Test name
Test status
Simulation time 58859242 ps
CPU time 0.72 seconds
Started Aug 02 05:32:40 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 207284 kb
Host smart-1604aec6-3c4c-46be-8b55-4734ebf4228a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40095
54214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.4009554214
Directory /workspace/31.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3174566774
Short name T2248
Test name
Test status
Simulation time 15556469439 ps
CPU time 39.01 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:33:01 PM PDT 24
Peak memory 215924 kb
Host smart-ec840773-e5f0-452f-93fa-86c04ed99bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31745
66774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3174566774
Directory /workspace/31.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/31.usbdev_pkt_received.1560818338
Short name T2516
Test name
Test status
Simulation time 194508404 ps
CPU time 0.91 seconds
Started Aug 02 05:32:16 PM PDT 24
Finished Aug 02 05:32:17 PM PDT 24
Peak memory 207412 kb
Host smart-b432b849-5e22-425f-af52-5c383943a27e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15608
18338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.1560818338
Directory /workspace/31.usbdev_pkt_received/latest


Test location /workspace/coverage/default/31.usbdev_pkt_sent.3988635054
Short name T2531
Test name
Test status
Simulation time 261363460 ps
CPU time 1.09 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 207396 kb
Host smart-866743f2-d480-4f77-9f11-40b5244705ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39886
35054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3988635054
Directory /workspace/31.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1552811794
Short name T2483
Test name
Test status
Simulation time 219171928 ps
CPU time 0.96 seconds
Started Aug 02 05:32:37 PM PDT 24
Finished Aug 02 05:32:43 PM PDT 24
Peak memory 207360 kb
Host smart-26f06bde-d2b9-4b75-9178-9b5db4e92566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15528
11794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1552811794
Directory /workspace/31.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.1823228103
Short name T503
Test name
Test status
Simulation time 231348481 ps
CPU time 1.05 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 207432 kb
Host smart-aef73b33-4444-48da-8997-d04178cb466a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18232
28103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.1823228103
Directory /workspace/31.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/31.usbdev_rx_crc_err.4091546945
Short name T1801
Test name
Test status
Simulation time 157679635 ps
CPU time 0.8 seconds
Started Aug 02 05:32:37 PM PDT 24
Finished Aug 02 05:32:38 PM PDT 24
Peak memory 207324 kb
Host smart-68c5413c-82bb-4e6f-b946-454c0fd0c5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40915
46945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.4091546945
Directory /workspace/31.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/31.usbdev_rx_full.2436440548
Short name T2026
Test name
Test status
Simulation time 304990555 ps
CPU time 1.21 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:24 PM PDT 24
Peak memory 207396 kb
Host smart-1169368a-5bdc-48b2-9dde-e0dac9dd9304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24364
40548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_full.2436440548
Directory /workspace/31.usbdev_rx_full/latest


Test location /workspace/coverage/default/31.usbdev_setup_stage.618374107
Short name T2038
Test name
Test status
Simulation time 159922814 ps
CPU time 0.83 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:20 PM PDT 24
Peak memory 207380 kb
Host smart-e085f47b-f9d7-4ef7-a919-390ff2aa3e44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61837
4107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.618374107
Directory /workspace/31.usbdev_setup_stage/latest


Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1465465179
Short name T2122
Test name
Test status
Simulation time 147879765 ps
CPU time 0.83 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207408 kb
Host smart-a7a73740-7163-4178-984e-4615235bfc7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14654
65179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1465465179
Directory /workspace/31.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/31.usbdev_smoke.3251739994
Short name T952
Test name
Test status
Simulation time 176418863 ps
CPU time 0.93 seconds
Started Aug 02 05:32:32 PM PDT 24
Finished Aug 02 05:32:33 PM PDT 24
Peak memory 207404 kb
Host smart-ee57fc0a-ecd6-41ee-8921-7ecafc175049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32517
39994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3251739994
Directory /workspace/31.usbdev_smoke/latest


Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.871815551
Short name T1704
Test name
Test status
Simulation time 3520899445 ps
CPU time 34.12 seconds
Started Aug 02 05:32:31 PM PDT 24
Finished Aug 02 05:33:06 PM PDT 24
Peak memory 224088 kb
Host smart-5b1d3e59-1225-4d08-805d-71a298edcce9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=871815551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.871815551
Directory /workspace/31.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.269447711
Short name T1121
Test name
Test status
Simulation time 212889699 ps
CPU time 0.89 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207408 kb
Host smart-e45ba2cd-6c56-4c9e-81a8-36f6c42d8cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26944
7711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.269447711
Directory /workspace/31.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/31.usbdev_stall_trans.1197068049
Short name T1358
Test name
Test status
Simulation time 157918544 ps
CPU time 0.83 seconds
Started Aug 02 05:32:45 PM PDT 24
Finished Aug 02 05:32:46 PM PDT 24
Peak memory 207316 kb
Host smart-305d4ef0-d4f6-449f-9348-30f1a619f6c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11970
68049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.1197068049
Directory /workspace/31.usbdev_stall_trans/latest


Test location /workspace/coverage/default/31.usbdev_stream_len_max.833673826
Short name T735
Test name
Test status
Simulation time 1323780702 ps
CPU time 2.96 seconds
Started Aug 02 05:32:37 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 207480 kb
Host smart-c99da79d-1a2c-4a52-96d0-9d346a4f9dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83367
3826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.833673826
Directory /workspace/31.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/31.usbdev_streaming_out.2269953209
Short name T2708
Test name
Test status
Simulation time 2182793123 ps
CPU time 62.84 seconds
Started Aug 02 05:32:36 PM PDT 24
Finished Aug 02 05:33:39 PM PDT 24
Peak memory 215892 kb
Host smart-d86d8e9c-03ea-4447-8109-229a31e92031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22699
53209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2269953209
Directory /workspace/31.usbdev_streaming_out/latest


Test location /workspace/coverage/default/31.usbdev_timeout_missing_host_handshake.3504732531
Short name T1610
Test name
Test status
Simulation time 885342756 ps
CPU time 5.61 seconds
Started Aug 02 05:32:33 PM PDT 24
Finished Aug 02 05:32:39 PM PDT 24
Peak memory 207564 kb
Host smart-f6a95db5-f16c-4375-8275-ef52276c9b9b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504732531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_timeout_missing_hos
t_handshake.3504732531
Directory /workspace/31.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/32.usbdev_alert_test.3290459791
Short name T1000
Test name
Test status
Simulation time 85356907 ps
CPU time 0.69 seconds
Started Aug 02 05:32:41 PM PDT 24
Finished Aug 02 05:32:42 PM PDT 24
Peak memory 207460 kb
Host smart-f47d8afc-1c55-4408-8c62-d045ae35257a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3290459791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3290459791
Directory /workspace/32.usbdev_alert_test/latest


Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.4037601054
Short name T977
Test name
Test status
Simulation time 11632622373 ps
CPU time 15.09 seconds
Started Aug 02 05:32:32 PM PDT 24
Finished Aug 02 05:32:47 PM PDT 24
Peak memory 207684 kb
Host smart-1273f639-6ed6-4b42-b341-cae6cfbc3ba8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037601054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_a
on_wake_disconnect.4037601054
Directory /workspace/32.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.1236366657
Short name T2493
Test name
Test status
Simulation time 13869563382 ps
CPU time 20.11 seconds
Started Aug 02 05:32:18 PM PDT 24
Finished Aug 02 05:32:38 PM PDT 24
Peak memory 215808 kb
Host smart-64055efd-9a55-432e-a217-18a26387d1c8
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236366657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.1236366657
Directory /workspace/32.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.94909516
Short name T2727
Test name
Test status
Simulation time 29957880555 ps
CPU time 32.29 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:32:57 PM PDT 24
Peak memory 207640 kb
Host smart-c1041c70-eb26-46b9-9245-146dba66035b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94909516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon
_wake_resume.94909516
Directory /workspace/32.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/32.usbdev_av_buffer.3988761225
Short name T2393
Test name
Test status
Simulation time 158004042 ps
CPU time 0.87 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:32:22 PM PDT 24
Peak memory 207404 kb
Host smart-411c0272-9425-4d51-b28e-0cd757a4621a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39887
61225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.3988761225
Directory /workspace/32.usbdev_av_buffer/latest


Test location /workspace/coverage/default/32.usbdev_bitstuff_err.2890604830
Short name T2992
Test name
Test status
Simulation time 162651566 ps
CPU time 0.89 seconds
Started Aug 02 05:32:41 PM PDT 24
Finished Aug 02 05:32:42 PM PDT 24
Peak memory 207376 kb
Host smart-31fcaaf9-64e5-479c-9141-d94fa57e00db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28906
04830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.2890604830
Directory /workspace/32.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.3682518877
Short name T1405
Test name
Test status
Simulation time 454898330 ps
CPU time 1.5 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 207208 kb
Host smart-b2b28b0b-ffee-46fa-88e8-a3b24e3f3b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36825
18877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.3682518877
Directory /workspace/32.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1958844063
Short name T2820
Test name
Test status
Simulation time 677508505 ps
CPU time 1.91 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207616 kb
Host smart-3733c3a8-04f6-4f27-b38b-8e1594f292d1
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1958844063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1958844063
Directory /workspace/32.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/32.usbdev_device_address.1233584452
Short name T1396
Test name
Test status
Simulation time 58199482937 ps
CPU time 92.81 seconds
Started Aug 02 05:32:40 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 207476 kb
Host smart-bc7c3fd9-f481-4f50-9d82-001885e2e564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12335
84452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.1233584452
Directory /workspace/32.usbdev_device_address/latest


Test location /workspace/coverage/default/32.usbdev_device_timeout.1712679503
Short name T707
Test name
Test status
Simulation time 833007453 ps
CPU time 5.18 seconds
Started Aug 02 05:32:49 PM PDT 24
Finished Aug 02 05:32:54 PM PDT 24
Peak memory 207332 kb
Host smart-18fc967a-6cbd-4004-8551-9ba4114e1286
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712679503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_timeout.1712679503
Directory /workspace/32.usbdev_device_timeout/latest


Test location /workspace/coverage/default/32.usbdev_disable_endpoint.1013152062
Short name T1332
Test name
Test status
Simulation time 955605441 ps
CPU time 2.08 seconds
Started Aug 02 05:32:35 PM PDT 24
Finished Aug 02 05:32:38 PM PDT 24
Peak memory 207344 kb
Host smart-5d7eed38-0635-41e4-a08b-57f1015764fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10131
52062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.1013152062
Directory /workspace/32.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/32.usbdev_disconnected.743506809
Short name T823
Test name
Test status
Simulation time 137561611 ps
CPU time 0.85 seconds
Started Aug 02 05:32:18 PM PDT 24
Finished Aug 02 05:32:19 PM PDT 24
Peak memory 207372 kb
Host smart-b06c5d01-d7c4-400d-84ec-edb58c3d8c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74350
6809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.743506809
Directory /workspace/32.usbdev_disconnected/latest


Test location /workspace/coverage/default/32.usbdev_enable.3279382000
Short name T1484
Test name
Test status
Simulation time 82448054 ps
CPU time 0.75 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207388 kb
Host smart-823c476b-698a-4e6e-a180-a5c72453268b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32793
82000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3279382000
Directory /workspace/32.usbdev_enable/latest


Test location /workspace/coverage/default/32.usbdev_endpoint_access.2985798469
Short name T2635
Test name
Test status
Simulation time 990066729 ps
CPU time 2.55 seconds
Started Aug 02 05:32:48 PM PDT 24
Finished Aug 02 05:32:51 PM PDT 24
Peak memory 207600 kb
Host smart-fc129a65-1cfc-4fff-a335-1bc6c2ced6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29857
98469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2985798469
Directory /workspace/32.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/32.usbdev_fifo_rst.1313982702
Short name T905
Test name
Test status
Simulation time 146782664 ps
CPU time 1.35 seconds
Started Aug 02 05:32:37 PM PDT 24
Finished Aug 02 05:32:39 PM PDT 24
Peak memory 207560 kb
Host smart-1965d9bb-846d-4fbc-8a4e-63f38e886fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13139
82702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1313982702
Directory /workspace/32.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/32.usbdev_in_iso.415334098
Short name T1364
Test name
Test status
Simulation time 161708405 ps
CPU time 0.91 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 207384 kb
Host smart-33d56863-bfb7-4fa4-9f90-b1da686b1165
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=415334098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.415334098
Directory /workspace/32.usbdev_in_iso/latest


Test location /workspace/coverage/default/32.usbdev_in_stall.2510320144
Short name T658
Test name
Test status
Simulation time 157822712 ps
CPU time 0.81 seconds
Started Aug 02 05:32:35 PM PDT 24
Finished Aug 02 05:32:36 PM PDT 24
Peak memory 207356 kb
Host smart-dbb7e491-f867-481d-9e2d-a737a06fafc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25103
20144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2510320144
Directory /workspace/32.usbdev_in_stall/latest


Test location /workspace/coverage/default/32.usbdev_in_trans.1820759640
Short name T1444
Test name
Test status
Simulation time 208255936 ps
CPU time 0.91 seconds
Started Aug 02 05:32:24 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 207388 kb
Host smart-5ab93fad-86b9-48f6-ad49-a39e4acf5be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18207
59640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1820759640
Directory /workspace/32.usbdev_in_trans/latest


Test location /workspace/coverage/default/32.usbdev_invalid_sync.2893916375
Short name T636
Test name
Test status
Simulation time 3983625575 ps
CPU time 109.3 seconds
Started Aug 02 05:32:35 PM PDT 24
Finished Aug 02 05:34:25 PM PDT 24
Peak memory 218320 kb
Host smart-b7183fe9-aec7-418b-a804-b384b181b8a9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2893916375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.2893916375
Directory /workspace/32.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/32.usbdev_iso_retraction.3943233410
Short name T1229
Test name
Test status
Simulation time 5937884343 ps
CPU time 37.44 seconds
Started Aug 02 05:32:48 PM PDT 24
Finished Aug 02 05:33:25 PM PDT 24
Peak memory 207656 kb
Host smart-236c9fff-a029-4cc2-b5d1-4bfdc35c0566
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3943233410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.3943233410
Directory /workspace/32.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/32.usbdev_link_in_err.714538173
Short name T2688
Test name
Test status
Simulation time 162585199 ps
CPU time 0.85 seconds
Started Aug 02 05:32:20 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 207420 kb
Host smart-58986e9f-f372-46de-a210-3f22ee56e984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71453
8173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.714538173
Directory /workspace/32.usbdev_link_in_err/latest


Test location /workspace/coverage/default/32.usbdev_link_resume.188479800
Short name T582
Test name
Test status
Simulation time 27899343336 ps
CPU time 41.94 seconds
Started Aug 02 05:32:35 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 215920 kb
Host smart-cbb2d183-06ae-447f-b899-4580b37d1098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18847
9800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.188479800
Directory /workspace/32.usbdev_link_resume/latest


Test location /workspace/coverage/default/32.usbdev_link_suspend.3498672169
Short name T1989
Test name
Test status
Simulation time 11342175555 ps
CPU time 14.14 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:37 PM PDT 24
Peak memory 207700 kb
Host smart-4f9060de-9eae-4693-8896-f8d6d96773ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34986
72169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3498672169
Directory /workspace/32.usbdev_link_suspend/latest


Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2302418588
Short name T2464
Test name
Test status
Simulation time 4021494741 ps
CPU time 114.17 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:34:17 PM PDT 24
Peak memory 224020 kb
Host smart-b7b5e83d-d748-42d7-9e8f-d28202b771cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23024
18588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2302418588
Directory /workspace/32.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.140604329
Short name T2480
Test name
Test status
Simulation time 3362847541 ps
CPU time 28.12 seconds
Started Aug 02 05:32:19 PM PDT 24
Finished Aug 02 05:32:47 PM PDT 24
Peak memory 217416 kb
Host smart-cd2a0380-f6f5-4892-b780-b3496bff4ce5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=140604329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.140604329
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.169061305
Short name T884
Test name
Test status
Simulation time 272413876 ps
CPU time 1.02 seconds
Started Aug 02 05:32:36 PM PDT 24
Finished Aug 02 05:32:37 PM PDT 24
Peak memory 207352 kb
Host smart-bcefac05-803f-4338-a6be-8fb07f60069e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=169061305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.169061305
Directory /workspace/32.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.2081207697
Short name T836
Test name
Test status
Simulation time 195136063 ps
CPU time 0.92 seconds
Started Aug 02 05:32:45 PM PDT 24
Finished Aug 02 05:32:46 PM PDT 24
Peak memory 207404 kb
Host smart-148b2888-0bca-49e3-9562-e3bc5718af19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20812
07697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.2081207697
Directory /workspace/32.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.3399906694
Short name T2155
Test name
Test status
Simulation time 2699859442 ps
CPU time 73.9 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:33:53 PM PDT 24
Peak memory 217404 kb
Host smart-30eb9720-64d4-4ca1-a938-516bf7b8e140
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3399906694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.3399906694
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2011640873
Short name T1643
Test name
Test status
Simulation time 180111670 ps
CPU time 0.89 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207380 kb
Host smart-3e17928c-bee3-4f19-a421-41dfa24fc714
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2011640873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2011640873
Directory /workspace/32.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1264905136
Short name T2786
Test name
Test status
Simulation time 146913561 ps
CPU time 0.82 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 207340 kb
Host smart-9fc5db3f-3413-47c9-860a-f50322e65782
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12649
05136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1264905136
Directory /workspace/32.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_nak_trans.84811345
Short name T140
Test name
Test status
Simulation time 198226415 ps
CPU time 0.9 seconds
Started Aug 02 05:32:32 PM PDT 24
Finished Aug 02 05:32:33 PM PDT 24
Peak memory 207364 kb
Host smart-51027577-fe90-424d-976c-8d0f20613312
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84811
345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.84811345
Directory /workspace/32.usbdev_nak_trans/latest


Test location /workspace/coverage/default/32.usbdev_out_iso.2335863684
Short name T1029
Test name
Test status
Simulation time 148794200 ps
CPU time 0.87 seconds
Started Aug 02 05:32:26 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207376 kb
Host smart-fdb3ea85-4ef3-4513-b604-20a3fa16a5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
63684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.2335863684
Directory /workspace/32.usbdev_out_iso/latest


Test location /workspace/coverage/default/32.usbdev_out_stall.2290408307
Short name T2023
Test name
Test status
Simulation time 176936939 ps
CPU time 0.87 seconds
Started Aug 02 05:32:51 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 207356 kb
Host smart-02fbb585-4654-40b3-bb88-73a8e526f168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22904
08307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2290408307
Directory /workspace/32.usbdev_out_stall/latest


Test location /workspace/coverage/default/32.usbdev_out_trans_nak.700175635
Short name T1090
Test name
Test status
Simulation time 173007394 ps
CPU time 0.88 seconds
Started Aug 02 05:32:26 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 207384 kb
Host smart-d2726b99-9d1d-454e-b26b-c36342f79526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70017
5635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.700175635
Directory /workspace/32.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/32.usbdev_pending_in_trans.2700130436
Short name T1870
Test name
Test status
Simulation time 151330514 ps
CPU time 0.81 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:32:22 PM PDT 24
Peak memory 207312 kb
Host smart-8193b070-9995-4af4-848c-476d199099f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27001
30436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.2700130436
Directory /workspace/32.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3684724668
Short name T2675
Test name
Test status
Simulation time 198147349 ps
CPU time 0.97 seconds
Started Aug 02 05:32:26 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 207428 kb
Host smart-63e8357a-4f91-459e-a4e5-bb25307810d3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3684724668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3684724668
Directory /workspace/32.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2230367202
Short name T524
Test name
Test status
Simulation time 182089980 ps
CPU time 0.83 seconds
Started Aug 02 05:33:46 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 206956 kb
Host smart-72b68639-2ee0-4c03-bc89-2813af6e3948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22303
67202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2230367202
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.4002249332
Short name T1184
Test name
Test status
Simulation time 47657176 ps
CPU time 0.69 seconds
Started Aug 02 05:32:44 PM PDT 24
Finished Aug 02 05:32:45 PM PDT 24
Peak memory 207176 kb
Host smart-665c8f31-3d8e-482e-a621-ef5f847c05ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40022
49332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.4002249332
Directory /workspace/32.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1852367770
Short name T2068
Test name
Test status
Simulation time 13105414168 ps
CPU time 31.99 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:54 PM PDT 24
Peak memory 215844 kb
Host smart-fd6142f9-35f0-49df-941d-2f4d515e1835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18523
67770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1852367770
Directory /workspace/32.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/32.usbdev_pkt_received.171044296
Short name T2747
Test name
Test status
Simulation time 175754075 ps
CPU time 0.85 seconds
Started Aug 02 05:32:49 PM PDT 24
Finished Aug 02 05:32:50 PM PDT 24
Peak memory 206824 kb
Host smart-5fabb133-2eb5-4d9e-8de0-3addf62a115c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17104
4296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.171044296
Directory /workspace/32.usbdev_pkt_received/latest


Test location /workspace/coverage/default/32.usbdev_pkt_sent.2619736813
Short name T2681
Test name
Test status
Simulation time 216314355 ps
CPU time 0.98 seconds
Started Aug 02 05:32:41 PM PDT 24
Finished Aug 02 05:32:42 PM PDT 24
Peak memory 207412 kb
Host smart-3b528d6f-46af-4a1d-b69e-cc0e50362463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26197
36813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.2619736813
Directory /workspace/32.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2551529614
Short name T938
Test name
Test status
Simulation time 216777162 ps
CPU time 0.95 seconds
Started Aug 02 05:32:27 PM PDT 24
Finished Aug 02 05:32:28 PM PDT 24
Peak memory 207384 kb
Host smart-0c1ecac4-a89a-41da-b96b-4349c683eeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25515
29614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2551529614
Directory /workspace/32.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1542496161
Short name T2456
Test name
Test status
Simulation time 154755890 ps
CPU time 0.86 seconds
Started Aug 02 05:32:40 PM PDT 24
Finished Aug 02 05:32:41 PM PDT 24
Peak memory 207328 kb
Host smart-688f44c3-ec98-41f3-a9e3-e38c4783d5af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15424
96161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1542496161
Directory /workspace/32.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1026446020
Short name T2083
Test name
Test status
Simulation time 189670136 ps
CPU time 0.88 seconds
Started Aug 02 05:32:20 PM PDT 24
Finished Aug 02 05:32:21 PM PDT 24
Peak memory 207424 kb
Host smart-7bf8064d-b1f5-44fd-8338-5ad2eb8c4b74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10264
46020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1026446020
Directory /workspace/32.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/32.usbdev_setup_stage.28308079
Short name T2347
Test name
Test status
Simulation time 177700289 ps
CPU time 0.83 seconds
Started Aug 02 05:32:28 PM PDT 24
Finished Aug 02 05:32:29 PM PDT 24
Peak memory 207400 kb
Host smart-d45f2346-2c54-4450-9aea-3f9d684da76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28308
079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.28308079
Directory /workspace/32.usbdev_setup_stage/latest


Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.2539621267
Short name T2298
Test name
Test status
Simulation time 165568739 ps
CPU time 0.94 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:32:22 PM PDT 24
Peak memory 207452 kb
Host smart-1ecf6548-5731-4660-a3fc-baa70ba2b18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25396
21267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.2539621267
Directory /workspace/32.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/32.usbdev_smoke.3133334054
Short name T919
Test name
Test status
Simulation time 282926209 ps
CPU time 1.04 seconds
Started Aug 02 05:32:40 PM PDT 24
Finished Aug 02 05:32:41 PM PDT 24
Peak memory 207340 kb
Host smart-1e010448-e0d4-4f27-a641-6e13c46e63e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31333
34054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3133334054
Directory /workspace/32.usbdev_smoke/latest


Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.2363126022
Short name T1399
Test name
Test status
Simulation time 2850940837 ps
CPU time 27.16 seconds
Started Aug 02 05:32:40 PM PDT 24
Finished Aug 02 05:33:08 PM PDT 24
Peak memory 217836 kb
Host smart-1f69492d-29f6-4c77-9315-ca626122515c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2363126022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.2363126022
Directory /workspace/32.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2975047810
Short name T2071
Test name
Test status
Simulation time 179843990 ps
CPU time 0.88 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:24 PM PDT 24
Peak memory 207384 kb
Host smart-27eadc6f-1109-45cb-9033-ee639aa8c41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29750
47810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2975047810
Directory /workspace/32.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/32.usbdev_stall_trans.1063273269
Short name T718
Test name
Test status
Simulation time 185631559 ps
CPU time 0.88 seconds
Started Aug 02 05:32:44 PM PDT 24
Finished Aug 02 05:32:45 PM PDT 24
Peak memory 207372 kb
Host smart-3b19ed0c-bf62-49e6-ae09-6f3f894fb5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10632
73269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1063273269
Directory /workspace/32.usbdev_stall_trans/latest


Test location /workspace/coverage/default/32.usbdev_stream_len_max.3476757220
Short name T2696
Test name
Test status
Simulation time 678215932 ps
CPU time 1.79 seconds
Started Aug 02 05:32:51 PM PDT 24
Finished Aug 02 05:32:53 PM PDT 24
Peak memory 207344 kb
Host smart-28b08156-5b29-400f-bcfa-0827ea62492c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34767
57220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.3476757220
Directory /workspace/32.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/32.usbdev_streaming_out.1862776865
Short name T2615
Test name
Test status
Simulation time 2646525671 ps
CPU time 75.63 seconds
Started Aug 02 05:32:21 PM PDT 24
Finished Aug 02 05:33:36 PM PDT 24
Peak memory 217408 kb
Host smart-4f68e3d5-288e-4d69-a1e4-8df90d5d1a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18627
76865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.1862776865
Directory /workspace/32.usbdev_streaming_out/latest


Test location /workspace/coverage/default/32.usbdev_timeout_missing_host_handshake.2061171993
Short name T2344
Test name
Test status
Simulation time 198017152 ps
CPU time 0.95 seconds
Started Aug 02 05:32:22 PM PDT 24
Finished Aug 02 05:32:23 PM PDT 24
Peak memory 207352 kb
Host smart-96af87df-c6d0-4168-ab77-14c03d92bf79
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061171993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_timeout_missing_hos
t_handshake.2061171993
Directory /workspace/32.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/33.usbdev_alert_test.3271614721
Short name T1297
Test name
Test status
Simulation time 57716681 ps
CPU time 0.65 seconds
Started Aug 02 05:32:27 PM PDT 24
Finished Aug 02 05:32:28 PM PDT 24
Peak memory 207472 kb
Host smart-cadddf92-4aa5-4a12-9c98-04ba354efdd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3271614721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3271614721
Directory /workspace/33.usbdev_alert_test/latest


Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.885332391
Short name T1785
Test name
Test status
Simulation time 5181692124 ps
CPU time 7.3 seconds
Started Aug 02 05:32:27 PM PDT 24
Finished Aug 02 05:32:35 PM PDT 24
Peak memory 215876 kb
Host smart-4204e9ab-cf76-40c4-b157-76294ce026c7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885332391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_ao
n_wake_disconnect.885332391
Directory /workspace/33.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3472717646
Short name T831
Test name
Test status
Simulation time 16286876638 ps
CPU time 18.06 seconds
Started Aug 02 05:32:43 PM PDT 24
Finished Aug 02 05:33:02 PM PDT 24
Peak memory 216008 kb
Host smart-60271c70-7dc1-49bc-ab86-3d18623fe297
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472717646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3472717646
Directory /workspace/33.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.4204420657
Short name T2227
Test name
Test status
Simulation time 25364630260 ps
CPU time 29.85 seconds
Started Aug 02 05:32:35 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 215820 kb
Host smart-81ac3600-0ec2-4459-95c0-072dfff38aed
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204420657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_a
on_wake_resume.4204420657
Directory /workspace/33.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/33.usbdev_av_buffer.572407663
Short name T1096
Test name
Test status
Simulation time 189346606 ps
CPU time 0.9 seconds
Started Aug 02 05:32:58 PM PDT 24
Finished Aug 02 05:32:59 PM PDT 24
Peak memory 207420 kb
Host smart-def5731a-ff01-4694-8a9e-f95124d931f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57240
7663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.572407663
Directory /workspace/33.usbdev_av_buffer/latest


Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3164100193
Short name T778
Test name
Test status
Simulation time 203165330 ps
CPU time 0.89 seconds
Started Aug 02 05:32:26 PM PDT 24
Finished Aug 02 05:32:27 PM PDT 24
Peak memory 207352 kb
Host smart-3f4c8b57-3c76-4a13-88ea-99fa55ae721f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31641
00193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3164100193
Directory /workspace/33.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.844189458
Short name T1540
Test name
Test status
Simulation time 296652282 ps
CPU time 1.13 seconds
Started Aug 02 05:32:43 PM PDT 24
Finished Aug 02 05:32:44 PM PDT 24
Peak memory 207416 kb
Host smart-074cae90-d3c7-4cc7-99ab-13d93692d4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84418
9458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.844189458
Directory /workspace/33.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3368398671
Short name T1693
Test name
Test status
Simulation time 1240558002 ps
CPU time 3.4 seconds
Started Aug 02 05:32:45 PM PDT 24
Finished Aug 02 05:32:48 PM PDT 24
Peak memory 207384 kb
Host smart-1cf50b73-fa80-4e0f-a463-fae6da7d5f00
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3368398671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3368398671
Directory /workspace/33.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/33.usbdev_device_address.2042042342
Short name T3001
Test name
Test status
Simulation time 26918432027 ps
CPU time 44.9 seconds
Started Aug 02 05:32:47 PM PDT 24
Finished Aug 02 05:33:32 PM PDT 24
Peak memory 207476 kb
Host smart-2a5f8630-058c-4781-83fb-be8ecf00c17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20420
42342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.2042042342
Directory /workspace/33.usbdev_device_address/latest


Test location /workspace/coverage/default/33.usbdev_device_timeout.3698782594
Short name T2771
Test name
Test status
Simulation time 3855351088 ps
CPU time 31.2 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:54 PM PDT 24
Peak memory 207712 kb
Host smart-9013105d-d301-46f3-892d-4623789f13ea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698782594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_timeout.3698782594
Directory /workspace/33.usbdev_device_timeout/latest


Test location /workspace/coverage/default/33.usbdev_disable_endpoint.246758116
Short name T1279
Test name
Test status
Simulation time 714490545 ps
CPU time 1.72 seconds
Started Aug 02 05:32:26 PM PDT 24
Finished Aug 02 05:32:28 PM PDT 24
Peak memory 207408 kb
Host smart-98e6e333-9f0f-4cd9-8e52-25b9aba5c57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24675
8116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.246758116
Directory /workspace/33.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/33.usbdev_disconnected.3923446579
Short name T668
Test name
Test status
Simulation time 149677308 ps
CPU time 0.8 seconds
Started Aug 02 05:32:25 PM PDT 24
Finished Aug 02 05:32:26 PM PDT 24
Peak memory 207368 kb
Host smart-dd32b087-b78b-4cc6-86a7-a10517d1ff23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39234
46579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.3923446579
Directory /workspace/33.usbdev_disconnected/latest


Test location /workspace/coverage/default/33.usbdev_enable.2367851941
Short name T2501
Test name
Test status
Simulation time 46045257 ps
CPU time 0.7 seconds
Started Aug 02 05:32:42 PM PDT 24
Finished Aug 02 05:32:43 PM PDT 24
Peak memory 207172 kb
Host smart-a2a13e43-cce4-4d04-a285-c480113f7e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23678
51941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.2367851941
Directory /workspace/33.usbdev_enable/latest


Test location /workspace/coverage/default/33.usbdev_endpoint_access.2211334826
Short name T354
Test name
Test status
Simulation time 738601339 ps
CPU time 2.15 seconds
Started Aug 02 05:32:47 PM PDT 24
Finished Aug 02 05:32:53 PM PDT 24
Peak memory 207484 kb
Host smart-9b5b8946-1787-4ed2-a86b-81106cb1c05c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22113
34826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.2211334826
Directory /workspace/33.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/33.usbdev_endpoint_types.3933825654
Short name T421
Test name
Test status
Simulation time 626641745 ps
CPU time 1.5 seconds
Started Aug 02 05:32:23 PM PDT 24
Finished Aug 02 05:32:25 PM PDT 24
Peak memory 207352 kb
Host smart-6b5a33f0-4d5e-435f-9c55-8d34ce9038f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3933825654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_types.3933825654
Directory /workspace/33.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/33.usbdev_fifo_rst.2561219544
Short name T2473
Test name
Test status
Simulation time 233968760 ps
CPU time 1.54 seconds
Started Aug 02 05:32:24 PM PDT 24
Finished Aug 02 05:32:26 PM PDT 24
Peak memory 207532 kb
Host smart-23c1755e-7f6d-4c94-b88a-d22678f3f77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25612
19544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2561219544
Directory /workspace/33.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/33.usbdev_in_iso.2230758251
Short name T2504
Test name
Test status
Simulation time 243684077 ps
CPU time 1.12 seconds
Started Aug 02 05:32:55 PM PDT 24
Finished Aug 02 05:32:56 PM PDT 24
Peak memory 215784 kb
Host smart-a1f0a1f3-4a91-4ec7-b792-e783dd7ab76e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2230758251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2230758251
Directory /workspace/33.usbdev_in_iso/latest


Test location /workspace/coverage/default/33.usbdev_in_stall.1940784149
Short name T1578
Test name
Test status
Simulation time 142050365 ps
CPU time 0.81 seconds
Started Aug 02 05:32:54 PM PDT 24
Finished Aug 02 05:32:55 PM PDT 24
Peak memory 207340 kb
Host smart-39f6309c-d7ec-4f4e-9efd-dfd030261b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19407
84149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1940784149
Directory /workspace/33.usbdev_in_stall/latest


Test location /workspace/coverage/default/33.usbdev_in_trans.2340409820
Short name T917
Test name
Test status
Simulation time 209893131 ps
CPU time 0.92 seconds
Started Aug 02 05:32:56 PM PDT 24
Finished Aug 02 05:32:57 PM PDT 24
Peak memory 207384 kb
Host smart-380f6264-9df4-419f-ae6f-61d0f218b35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23404
09820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.2340409820
Directory /workspace/33.usbdev_in_trans/latest


Test location /workspace/coverage/default/33.usbdev_invalid_sync.1981256455
Short name T2689
Test name
Test status
Simulation time 3700452633 ps
CPU time 34.65 seconds
Started Aug 02 05:32:47 PM PDT 24
Finished Aug 02 05:33:22 PM PDT 24
Peak memory 223852 kb
Host smart-0cd90141-1d1a-41e0-bf52-90bae86a7e44
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1981256455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1981256455
Directory /workspace/33.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/33.usbdev_iso_retraction.1044900979
Short name T2577
Test name
Test status
Simulation time 13431097207 ps
CPU time 85.17 seconds
Started Aug 02 05:32:46 PM PDT 24
Finished Aug 02 05:34:16 PM PDT 24
Peak memory 207628 kb
Host smart-56aa7edb-a497-4bd5-8833-eb22c1d884b7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1044900979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.1044900979
Directory /workspace/33.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/33.usbdev_link_in_err.3532726386
Short name T818
Test name
Test status
Simulation time 200473413 ps
CPU time 0.94 seconds
Started Aug 02 05:32:31 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207408 kb
Host smart-945178b9-21df-4360-a94b-b743a814e524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35327
26386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3532726386
Directory /workspace/33.usbdev_link_in_err/latest


Test location /workspace/coverage/default/33.usbdev_link_resume.2795624618
Short name T607
Test name
Test status
Simulation time 31006587674 ps
CPU time 45.77 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:33:25 PM PDT 24
Peak memory 207660 kb
Host smart-1e962dc3-6cf8-4992-81f2-2af54e63eb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27956
24618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2795624618
Directory /workspace/33.usbdev_link_resume/latest


Test location /workspace/coverage/default/33.usbdev_link_suspend.2450967714
Short name T2831
Test name
Test status
Simulation time 4888837940 ps
CPU time 6.21 seconds
Started Aug 02 05:32:52 PM PDT 24
Finished Aug 02 05:32:58 PM PDT 24
Peak memory 215848 kb
Host smart-a0c438af-e6ec-40be-a001-3882acf59685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24509
67714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2450967714
Directory /workspace/33.usbdev_link_suspend/latest


Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2948063172
Short name T2210
Test name
Test status
Simulation time 4542618071 ps
CPU time 121 seconds
Started Aug 02 05:32:44 PM PDT 24
Finished Aug 02 05:34:45 PM PDT 24
Peak memory 223964 kb
Host smart-2e440a53-d25b-4bc9-b940-3e6ce12b8e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29480
63172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2948063172
Directory /workspace/33.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.861284656
Short name T3078
Test name
Test status
Simulation time 2531406408 ps
CPU time 70.72 seconds
Started Aug 02 05:32:42 PM PDT 24
Finished Aug 02 05:33:53 PM PDT 24
Peak memory 217276 kb
Host smart-10010888-661d-4ca5-ad97-943735ab2969
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=861284656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.861284656
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1610442572
Short name T2428
Test name
Test status
Simulation time 258937578 ps
CPU time 1.06 seconds
Started Aug 02 05:32:36 PM PDT 24
Finished Aug 02 05:32:37 PM PDT 24
Peak memory 207328 kb
Host smart-d2643541-5362-4d79-8592-8b910f9d2d35
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1610442572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1610442572
Directory /workspace/33.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.3460611090
Short name T1666
Test name
Test status
Simulation time 189986611 ps
CPU time 0.96 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:32:40 PM PDT 24
Peak memory 207360 kb
Host smart-3d8fb460-e73b-4af3-ae1f-f95de1ab5423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34606
11090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.3460611090
Directory /workspace/33.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.284044693
Short name T945
Test name
Test status
Simulation time 2485806043 ps
CPU time 69.77 seconds
Started Aug 02 05:32:44 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 217164 kb
Host smart-0242f785-0e67-44a8-9351-1dca572393d1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=284044693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.284044693
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3110836051
Short name T1649
Test name
Test status
Simulation time 165036787 ps
CPU time 0.84 seconds
Started Aug 02 05:32:46 PM PDT 24
Finished Aug 02 05:32:47 PM PDT 24
Peak memory 207332 kb
Host smart-8631e0d5-7091-4dcd-b126-bbdeaf41bc8f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3110836051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3110836051
Directory /workspace/33.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3465241859
Short name T2713
Test name
Test status
Simulation time 159294585 ps
CPU time 0.8 seconds
Started Aug 02 05:34:00 PM PDT 24
Finished Aug 02 05:34:01 PM PDT 24
Peak memory 207204 kb
Host smart-d8e2764e-44ad-4663-a295-75d1dec0174b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34652
41859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3465241859
Directory /workspace/33.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_nak_trans.259917913
Short name T2432
Test name
Test status
Simulation time 168350741 ps
CPU time 0.84 seconds
Started Aug 02 05:32:40 PM PDT 24
Finished Aug 02 05:32:41 PM PDT 24
Peak memory 207408 kb
Host smart-a83a2585-b382-4a69-af5f-f79d47b3927c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25991
7913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.259917913
Directory /workspace/33.usbdev_nak_trans/latest


Test location /workspace/coverage/default/33.usbdev_out_iso.2665175452
Short name T1644
Test name
Test status
Simulation time 186835976 ps
CPU time 0.92 seconds
Started Aug 02 05:32:41 PM PDT 24
Finished Aug 02 05:32:42 PM PDT 24
Peak memory 207340 kb
Host smart-40cbd59f-7d62-4f1f-8401-6399667be978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26651
75452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2665175452
Directory /workspace/33.usbdev_out_iso/latest


Test location /workspace/coverage/default/33.usbdev_out_stall.4028072026
Short name T583
Test name
Test status
Simulation time 207896059 ps
CPU time 0.86 seconds
Started Aug 02 05:32:43 PM PDT 24
Finished Aug 02 05:32:44 PM PDT 24
Peak memory 207004 kb
Host smart-53c8a6e2-d7d8-415c-855c-24ff011ff214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40280
72026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.4028072026
Directory /workspace/33.usbdev_out_stall/latest


Test location /workspace/coverage/default/33.usbdev_out_trans_nak.481810780
Short name T1028
Test name
Test status
Simulation time 164787867 ps
CPU time 0.84 seconds
Started Aug 02 05:33:46 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 206992 kb
Host smart-c98d924e-52d0-4e97-935e-abc061e3cdec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48181
0780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.481810780
Directory /workspace/33.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/33.usbdev_pending_in_trans.4270150460
Short name T962
Test name
Test status
Simulation time 152612345 ps
CPU time 0.83 seconds
Started Aug 02 05:32:31 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207420 kb
Host smart-f4a752d4-f03e-4bfc-8079-097a511684cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42701
50460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.4270150460
Directory /workspace/33.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2960288933
Short name T659
Test name
Test status
Simulation time 271820161 ps
CPU time 1.05 seconds
Started Aug 02 05:32:29 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 207364 kb
Host smart-dc12c229-1c52-47d5-ace7-bdee7665180a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2960288933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2960288933
Directory /workspace/33.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1039324591
Short name T1161
Test name
Test status
Simulation time 151411717 ps
CPU time 0.86 seconds
Started Aug 02 05:32:31 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207284 kb
Host smart-536c16c9-93d1-4f02-818e-b055d84f9cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10393
24591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1039324591
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3286601505
Short name T2277
Test name
Test status
Simulation time 80100773 ps
CPU time 0.74 seconds
Started Aug 02 05:32:41 PM PDT 24
Finished Aug 02 05:32:42 PM PDT 24
Peak memory 207372 kb
Host smart-64518874-56a3-4c87-96fd-6b67fccc73b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32866
01505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3286601505
Directory /workspace/33.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3521375380
Short name T1542
Test name
Test status
Simulation time 7138944111 ps
CPU time 18.75 seconds
Started Aug 02 05:32:48 PM PDT 24
Finished Aug 02 05:33:07 PM PDT 24
Peak memory 215852 kb
Host smart-f37794ca-38cd-40d1-b80e-adfa4d846b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35213
75380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3521375380
Directory /workspace/33.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/33.usbdev_pkt_received.316460383
Short name T1060
Test name
Test status
Simulation time 196556198 ps
CPU time 0.93 seconds
Started Aug 02 05:32:59 PM PDT 24
Finished Aug 02 05:33:00 PM PDT 24
Peak memory 207380 kb
Host smart-21175c67-2c5d-4d3d-b027-4f68360582b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31646
0383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.316460383
Directory /workspace/33.usbdev_pkt_received/latest


Test location /workspace/coverage/default/33.usbdev_pkt_sent.3071856942
Short name T1052
Test name
Test status
Simulation time 241663440 ps
CPU time 1 seconds
Started Aug 02 05:32:57 PM PDT 24
Finished Aug 02 05:32:58 PM PDT 24
Peak memory 207352 kb
Host smart-6ad1fa8f-3654-4831-9ae1-22014f988dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30718
56942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3071856942
Directory /workspace/33.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.810106822
Short name T2064
Test name
Test status
Simulation time 268049591 ps
CPU time 0.97 seconds
Started Aug 02 05:32:46 PM PDT 24
Finished Aug 02 05:32:47 PM PDT 24
Peak memory 207372 kb
Host smart-0e638d26-51de-45a7-aff3-a3835f0240d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81010
6822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.810106822
Directory /workspace/33.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.973133761
Short name T1530
Test name
Test status
Simulation time 173024816 ps
CPU time 0.85 seconds
Started Aug 02 05:32:40 PM PDT 24
Finished Aug 02 05:32:41 PM PDT 24
Peak memory 207408 kb
Host smart-9e19fe93-0c98-4e6e-8aa4-a5fa1b95f8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97313
3761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.973133761
Directory /workspace/33.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/33.usbdev_rx_crc_err.287316257
Short name T2928
Test name
Test status
Simulation time 163447270 ps
CPU time 0.81 seconds
Started Aug 02 05:32:49 PM PDT 24
Finished Aug 02 05:32:50 PM PDT 24
Peak memory 207376 kb
Host smart-727912b8-43d2-4cfc-ad3e-6b4613d81c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28731
6257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.287316257
Directory /workspace/33.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/33.usbdev_setup_stage.2496473083
Short name T738
Test name
Test status
Simulation time 173860500 ps
CPU time 0.85 seconds
Started Aug 02 05:32:29 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 207392 kb
Host smart-892e861d-ff7b-43f0-a527-87ea5f523f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24964
73083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.2496473083
Directory /workspace/33.usbdev_setup_stage/latest


Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.2746178909
Short name T920
Test name
Test status
Simulation time 151430805 ps
CPU time 0.83 seconds
Started Aug 02 05:34:02 PM PDT 24
Finished Aug 02 05:34:03 PM PDT 24
Peak memory 207192 kb
Host smart-3f94c130-0006-4251-a8bd-c40acb330550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27461
78909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.2746178909
Directory /workspace/33.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/33.usbdev_smoke.4215426125
Short name T2987
Test name
Test status
Simulation time 192452597 ps
CPU time 1 seconds
Started Aug 02 05:32:44 PM PDT 24
Finished Aug 02 05:32:45 PM PDT 24
Peak memory 207404 kb
Host smart-f7f13502-38ee-4d67-bccd-ea664a8d7832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42154
26125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.4215426125
Directory /workspace/33.usbdev_smoke/latest


Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.1638047703
Short name T2340
Test name
Test status
Simulation time 2938372059 ps
CPU time 21.48 seconds
Started Aug 02 05:32:51 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 217576 kb
Host smart-48747b9f-528a-4d55-be9b-52d74b214b86
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1638047703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.1638047703
Directory /workspace/33.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2461782562
Short name T1949
Test name
Test status
Simulation time 179954944 ps
CPU time 0.86 seconds
Started Aug 02 05:32:31 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207428 kb
Host smart-581348ed-d7a0-4dc9-adf0-aa243df2dbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24617
82562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2461782562
Directory /workspace/33.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/33.usbdev_stall_trans.3332617487
Short name T1440
Test name
Test status
Simulation time 176056098 ps
CPU time 0.86 seconds
Started Aug 02 05:32:51 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 207368 kb
Host smart-0a41d291-819a-49de-a2ab-1c6ad56bce6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33326
17487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3332617487
Directory /workspace/33.usbdev_stall_trans/latest


Test location /workspace/coverage/default/33.usbdev_stream_len_max.472616763
Short name T1541
Test name
Test status
Simulation time 452036087 ps
CPU time 1.39 seconds
Started Aug 02 05:32:28 PM PDT 24
Finished Aug 02 05:32:30 PM PDT 24
Peak memory 207360 kb
Host smart-b104fd6e-677b-4998-a050-bcaf4e782848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47261
6763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.472616763
Directory /workspace/33.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/33.usbdev_streaming_out.2029435734
Short name T1448
Test name
Test status
Simulation time 2509248597 ps
CPU time 20.28 seconds
Started Aug 02 05:32:51 PM PDT 24
Finished Aug 02 05:33:11 PM PDT 24
Peak memory 217648 kb
Host smart-7c22caa4-b824-4831-baa7-b3975eb5138d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20294
35734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.2029435734
Directory /workspace/33.usbdev_streaming_out/latest


Test location /workspace/coverage/default/33.usbdev_timeout_missing_host_handshake.2300918113
Short name T2825
Test name
Test status
Simulation time 2904398421 ps
CPU time 17.12 seconds
Started Aug 02 05:33:37 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 206688 kb
Host smart-fe1ccabd-594c-4f25-9d22-41107577edd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300918113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_timeout_missing_hos
t_handshake.2300918113
Directory /workspace/33.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/34.usbdev_alert_test.1004038323
Short name T1861
Test name
Test status
Simulation time 38876257 ps
CPU time 0.62 seconds
Started Aug 02 05:34:03 PM PDT 24
Finished Aug 02 05:34:04 PM PDT 24
Peak memory 207296 kb
Host smart-544dccc8-4613-4c9a-808e-226dd024dcd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1004038323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.1004038323
Directory /workspace/34.usbdev_alert_test/latest


Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.1901633635
Short name T234
Test name
Test status
Simulation time 10085236468 ps
CPU time 12.73 seconds
Started Aug 02 05:32:36 PM PDT 24
Finished Aug 02 05:32:49 PM PDT 24
Peak memory 207680 kb
Host smart-feb07cd7-aabe-4b90-b6e2-95b69a51a7c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901633635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_disconnect.1901633635
Directory /workspace/34.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.2466906912
Short name T1077
Test name
Test status
Simulation time 21020217215 ps
CPU time 30.6 seconds
Started Aug 02 05:32:55 PM PDT 24
Finished Aug 02 05:33:26 PM PDT 24
Peak memory 207700 kb
Host smart-a4b25b18-d2ea-4b7a-8a39-f6b42b080c6b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466906912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.2466906912
Directory /workspace/34.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1961799664
Short name T2834
Test name
Test status
Simulation time 23679622671 ps
CPU time 29.48 seconds
Started Aug 02 05:32:45 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 215840 kb
Host smart-ac0acb89-8e39-479f-b0d7-b13210f41eac
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961799664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_a
on_wake_resume.1961799664
Directory /workspace/34.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/34.usbdev_av_buffer.408483649
Short name T1688
Test name
Test status
Simulation time 230072028 ps
CPU time 0.96 seconds
Started Aug 02 05:32:36 PM PDT 24
Finished Aug 02 05:32:37 PM PDT 24
Peak memory 207412 kb
Host smart-1e831b99-e061-41b5-b401-aa386b3ab2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40848
3649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.408483649
Directory /workspace/34.usbdev_av_buffer/latest


Test location /workspace/coverage/default/34.usbdev_bitstuff_err.3469662540
Short name T713
Test name
Test status
Simulation time 174844345 ps
CPU time 0.86 seconds
Started Aug 02 05:32:52 PM PDT 24
Finished Aug 02 05:32:53 PM PDT 24
Peak memory 207380 kb
Host smart-23659bb1-ed1b-44db-b518-2e31cb79faad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34696
62540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.3469662540
Directory /workspace/34.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.838282246
Short name T1411
Test name
Test status
Simulation time 337320916 ps
CPU time 1.3 seconds
Started Aug 02 05:32:45 PM PDT 24
Finished Aug 02 05:32:46 PM PDT 24
Peak memory 207432 kb
Host smart-e50c2676-1fda-4fac-b427-6da59e2e5d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83828
2246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.838282246
Directory /workspace/34.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.944050870
Short name T1022
Test name
Test status
Simulation time 361402889 ps
CPU time 1.19 seconds
Started Aug 02 05:32:33 PM PDT 24
Finished Aug 02 05:32:35 PM PDT 24
Peak memory 207360 kb
Host smart-1c43c4c5-2a7a-4133-8d86-e3bada8809ec
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=944050870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.944050870
Directory /workspace/34.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/34.usbdev_device_address.1810637303
Short name T2619
Test name
Test status
Simulation time 37395564719 ps
CPU time 54.26 seconds
Started Aug 02 05:32:34 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 207636 kb
Host smart-670a7391-3554-4580-9b46-b280a658a51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18106
37303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1810637303
Directory /workspace/34.usbdev_device_address/latest


Test location /workspace/coverage/default/34.usbdev_device_timeout.1627327259
Short name T1218
Test name
Test status
Simulation time 6382878314 ps
CPU time 41.12 seconds
Started Aug 02 05:32:45 PM PDT 24
Finished Aug 02 05:33:26 PM PDT 24
Peak memory 207696 kb
Host smart-6420972b-0e6c-42a7-8f93-c0996292c6fd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627327259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_timeout.1627327259
Directory /workspace/34.usbdev_device_timeout/latest


Test location /workspace/coverage/default/34.usbdev_disable_endpoint.457856053
Short name T2261
Test name
Test status
Simulation time 966153428 ps
CPU time 1.98 seconds
Started Aug 02 05:32:47 PM PDT 24
Finished Aug 02 05:32:50 PM PDT 24
Peak memory 207344 kb
Host smart-dd799c0f-c4e9-40e1-bd62-b820aca03c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45785
6053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.457856053
Directory /workspace/34.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/34.usbdev_disconnected.2341533508
Short name T768
Test name
Test status
Simulation time 172707173 ps
CPU time 0.82 seconds
Started Aug 02 05:32:55 PM PDT 24
Finished Aug 02 05:32:55 PM PDT 24
Peak memory 206792 kb
Host smart-e7a28669-66d9-4753-ae65-126c53fd2cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23415
33508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.2341533508
Directory /workspace/34.usbdev_disconnected/latest


Test location /workspace/coverage/default/34.usbdev_enable.2522790591
Short name T250
Test name
Test status
Simulation time 41209133 ps
CPU time 0.72 seconds
Started Aug 02 05:33:46 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 206956 kb
Host smart-310ac043-108d-4bbc-8dbc-6c8db0ae441c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25227
90591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2522790591
Directory /workspace/34.usbdev_enable/latest


Test location /workspace/coverage/default/34.usbdev_endpoint_access.518345988
Short name T1169
Test name
Test status
Simulation time 942663775 ps
CPU time 2.29 seconds
Started Aug 02 05:32:54 PM PDT 24
Finished Aug 02 05:32:57 PM PDT 24
Peak memory 207532 kb
Host smart-ba0d0c23-9887-41cd-862c-911464e7a494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51834
5988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.518345988
Directory /workspace/34.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/34.usbdev_endpoint_types.265425475
Short name T393
Test name
Test status
Simulation time 669520493 ps
CPU time 1.48 seconds
Started Aug 02 05:33:58 PM PDT 24
Finished Aug 02 05:33:59 PM PDT 24
Peak memory 207176 kb
Host smart-8f64b8c5-ba1e-4084-90a1-c63b7e791910
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=265425475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_types.265425475
Directory /workspace/34.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/34.usbdev_fifo_rst.1496921502
Short name T2224
Test name
Test status
Simulation time 317198474 ps
CPU time 1.94 seconds
Started Aug 02 05:32:39 PM PDT 24
Finished Aug 02 05:32:41 PM PDT 24
Peak memory 207576 kb
Host smart-e5116750-a894-4e9c-9d93-4f19993ebfc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14969
21502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1496921502
Directory /workspace/34.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/34.usbdev_in_iso.813911161
Short name T958
Test name
Test status
Simulation time 189461784 ps
CPU time 0.91 seconds
Started Aug 02 05:32:31 PM PDT 24
Finished Aug 02 05:32:32 PM PDT 24
Peak memory 207336 kb
Host smart-a3adb25a-80c4-43d1-bad1-0a678eb91a42
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=813911161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.813911161
Directory /workspace/34.usbdev_in_iso/latest


Test location /workspace/coverage/default/34.usbdev_in_stall.2476718596
Short name T1510
Test name
Test status
Simulation time 179153839 ps
CPU time 0.85 seconds
Started Aug 02 05:32:55 PM PDT 24
Finished Aug 02 05:32:56 PM PDT 24
Peak memory 207384 kb
Host smart-6c5d803c-be46-4490-9028-b93964eae39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24767
18596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.2476718596
Directory /workspace/34.usbdev_in_stall/latest


Test location /workspace/coverage/default/34.usbdev_in_trans.2605387496
Short name T1111
Test name
Test status
Simulation time 253047231 ps
CPU time 0.99 seconds
Started Aug 02 05:32:50 PM PDT 24
Finished Aug 02 05:32:51 PM PDT 24
Peak memory 207432 kb
Host smart-6ce1e52b-f2be-4ed1-9828-485d21dde8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26053
87496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2605387496
Directory /workspace/34.usbdev_in_trans/latest


Test location /workspace/coverage/default/34.usbdev_invalid_sync.696178693
Short name T2364
Test name
Test status
Simulation time 4550247581 ps
CPU time 119.93 seconds
Started Aug 02 05:33:45 PM PDT 24
Finished Aug 02 05:35:45 PM PDT 24
Peak memory 223644 kb
Host smart-fb3fa4c3-93d3-46dc-8c65-957a1ae6ca8a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=696178693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.696178693
Directory /workspace/34.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/34.usbdev_iso_retraction.3331504027
Short name T1287
Test name
Test status
Simulation time 4732347206 ps
CPU time 31.61 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:33 PM PDT 24
Peak memory 207624 kb
Host smart-a7d3b7c9-9ae6-4e4b-adcc-a78c3f161286
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3331504027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3331504027
Directory /workspace/34.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/34.usbdev_link_in_err.2630576700
Short name T696
Test name
Test status
Simulation time 195308914 ps
CPU time 0.87 seconds
Started Aug 02 05:32:49 PM PDT 24
Finished Aug 02 05:32:50 PM PDT 24
Peak memory 207412 kb
Host smart-6bd8aec5-a00d-40e0-98d0-0ccfe6b4382d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26305
76700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2630576700
Directory /workspace/34.usbdev_link_in_err/latest


Test location /workspace/coverage/default/34.usbdev_link_resume.32690315
Short name T671
Test name
Test status
Simulation time 27125240563 ps
CPU time 43.58 seconds
Started Aug 02 05:32:54 PM PDT 24
Finished Aug 02 05:33:37 PM PDT 24
Peak memory 207728 kb
Host smart-74bd6cb2-4354-4ec7-bcae-d769f16f485e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32690
315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.32690315
Directory /workspace/34.usbdev_link_resume/latest


Test location /workspace/coverage/default/34.usbdev_link_suspend.2123660770
Short name T1792
Test name
Test status
Simulation time 5122412070 ps
CPU time 6.35 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207632 kb
Host smart-cf262200-8821-4a47-a3a8-9ed9e42fa192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21236
60770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.2123660770
Directory /workspace/34.usbdev_link_suspend/latest


Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.470779968
Short name T4
Test name
Test status
Simulation time 3990169019 ps
CPU time 37.49 seconds
Started Aug 02 05:32:47 PM PDT 24
Finished Aug 02 05:33:25 PM PDT 24
Peak memory 224060 kb
Host smart-707806cd-9aa4-46e5-a43b-2fd5bd2265d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47077
9968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.470779968
Directory /workspace/34.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2842145458
Short name T1665
Test name
Test status
Simulation time 2636247384 ps
CPU time 26.73 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:27 PM PDT 24
Peak memory 215860 kb
Host smart-aab0a392-1a9c-4ee1-99d8-115402c8d4b0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2842145458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2842145458
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.3540883271
Short name T2690
Test name
Test status
Simulation time 289705756 ps
CPU time 0.97 seconds
Started Aug 02 05:32:58 PM PDT 24
Finished Aug 02 05:32:59 PM PDT 24
Peak memory 207376 kb
Host smart-13e336c3-2af6-4cf4-80a4-a13dcc0d5189
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3540883271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.3540883271
Directory /workspace/34.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.4288196297
Short name T507
Test name
Test status
Simulation time 197807004 ps
CPU time 0.94 seconds
Started Aug 02 05:32:54 PM PDT 24
Finished Aug 02 05:32:55 PM PDT 24
Peak memory 207352 kb
Host smart-cd0fcf28-7056-4d27-ba89-1d438361de3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42881
96297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.4288196297
Directory /workspace/34.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.1804111578
Short name T1040
Test name
Test status
Simulation time 3264266994 ps
CPU time 89.08 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:34:30 PM PDT 24
Peak memory 217264 kb
Host smart-6fb6777b-d8d2-4ee9-9a6b-c1d70920cb61
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1804111578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.1804111578
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1944150797
Short name T1924
Test name
Test status
Simulation time 181185327 ps
CPU time 0.88 seconds
Started Aug 02 05:32:50 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 207416 kb
Host smart-522201c4-5727-49d6-ab47-3b2a99c5dd3c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1944150797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1944150797
Directory /workspace/34.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.4123206059
Short name T968
Test name
Test status
Simulation time 135210704 ps
CPU time 0.79 seconds
Started Aug 02 05:32:55 PM PDT 24
Finished Aug 02 05:32:56 PM PDT 24
Peak memory 207336 kb
Host smart-1fcf4e28-5e0b-4882-b0c7-886f0fd008ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41232
06059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.4123206059
Directory /workspace/34.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_nak_trans.2892158611
Short name T2711
Test name
Test status
Simulation time 227576226 ps
CPU time 0.92 seconds
Started Aug 02 05:32:51 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 207300 kb
Host smart-4ba70362-aa0b-48b7-9af1-09d6896e18c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28921
58611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.2892158611
Directory /workspace/34.usbdev_nak_trans/latest


Test location /workspace/coverage/default/34.usbdev_out_iso.2603593674
Short name T1400
Test name
Test status
Simulation time 155549214 ps
CPU time 0.87 seconds
Started Aug 02 05:33:00 PM PDT 24
Finished Aug 02 05:33:01 PM PDT 24
Peak memory 207360 kb
Host smart-023d4357-59df-43dd-bebb-f88d478d120c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26035
93674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.2603593674
Directory /workspace/34.usbdev_out_iso/latest


Test location /workspace/coverage/default/34.usbdev_out_stall.3412674104
Short name T2943
Test name
Test status
Simulation time 175216001 ps
CPU time 0.83 seconds
Started Aug 02 05:32:48 PM PDT 24
Finished Aug 02 05:32:49 PM PDT 24
Peak memory 207352 kb
Host smart-622307b1-d7dd-4754-98a9-fb1136aab4c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34126
74104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3412674104
Directory /workspace/34.usbdev_out_stall/latest


Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2088568004
Short name T2006
Test name
Test status
Simulation time 176501214 ps
CPU time 0.85 seconds
Started Aug 02 05:32:50 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 207364 kb
Host smart-1344e71d-daf1-4054-a7f4-d5df1b5c42b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20885
68004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2088568004
Directory /workspace/34.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2256572719
Short name T192
Test name
Test status
Simulation time 159393331 ps
CPU time 0.91 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:03 PM PDT 24
Peak memory 207388 kb
Host smart-064d77d6-b5c4-48d7-8656-e6dd5506c807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22565
72719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2256572719
Directory /workspace/34.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.3323555891
Short name T872
Test name
Test status
Simulation time 199043082 ps
CPU time 0.95 seconds
Started Aug 02 05:33:00 PM PDT 24
Finished Aug 02 05:33:01 PM PDT 24
Peak memory 207380 kb
Host smart-73db2855-48c2-4ec0-8db7-d583f69dd482
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3323555891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.3323555891
Directory /workspace/34.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2138313132
Short name T729
Test name
Test status
Simulation time 155425304 ps
CPU time 0.84 seconds
Started Aug 02 05:32:55 PM PDT 24
Finished Aug 02 05:32:56 PM PDT 24
Peak memory 207312 kb
Host smart-1f7ce0ba-bca7-4ee6-bf6a-b6ec1eefb6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21383
13132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2138313132
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1282484664
Short name T2311
Test name
Test status
Simulation time 35304539 ps
CPU time 0.67 seconds
Started Aug 02 05:32:43 PM PDT 24
Finished Aug 02 05:32:44 PM PDT 24
Peak memory 207348 kb
Host smart-70bf5e02-4c96-4413-9a20-8660f8d1b303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12824
84664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1282484664
Directory /workspace/34.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1221596310
Short name T1592
Test name
Test status
Simulation time 16836541947 ps
CPU time 43.43 seconds
Started Aug 02 05:32:53 PM PDT 24
Finished Aug 02 05:33:37 PM PDT 24
Peak memory 215804 kb
Host smart-b46ca1a7-5355-42a5-b094-b14031ff5f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12215
96310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1221596310
Directory /workspace/34.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/34.usbdev_pkt_received.351075022
Short name T1307
Test name
Test status
Simulation time 165986522 ps
CPU time 0.82 seconds
Started Aug 02 05:32:47 PM PDT 24
Finished Aug 02 05:32:48 PM PDT 24
Peak memory 207428 kb
Host smart-8471c34f-411e-4be9-affe-4677a216c4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35107
5022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.351075022
Directory /workspace/34.usbdev_pkt_received/latest


Test location /workspace/coverage/default/34.usbdev_pkt_sent.2629736828
Short name T2574
Test name
Test status
Simulation time 227352171 ps
CPU time 1.04 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:02 PM PDT 24
Peak memory 207360 kb
Host smart-fe1ac4bb-bc30-4f5b-87ab-18d2bc53a71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26297
36828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2629736828
Directory /workspace/34.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.3035450534
Short name T1348
Test name
Test status
Simulation time 207404636 ps
CPU time 0.95 seconds
Started Aug 02 05:32:52 PM PDT 24
Finished Aug 02 05:32:53 PM PDT 24
Peak memory 207380 kb
Host smart-513dc427-5903-42c9-b34e-f7b68ac13cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30354
50534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.3035450534
Directory /workspace/34.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2860605945
Short name T2369
Test name
Test status
Simulation time 227023479 ps
CPU time 0.97 seconds
Started Aug 02 05:33:11 PM PDT 24
Finished Aug 02 05:33:12 PM PDT 24
Peak memory 207416 kb
Host smart-40e3e15e-5076-4851-8f76-5c83dedf88cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28606
05945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2860605945
Directory /workspace/34.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/34.usbdev_rx_crc_err.713289617
Short name T2678
Test name
Test status
Simulation time 190794668 ps
CPU time 0.85 seconds
Started Aug 02 05:32:57 PM PDT 24
Finished Aug 02 05:32:58 PM PDT 24
Peak memory 207424 kb
Host smart-faf63b24-242f-4c35-9ea0-42729f1e5a97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71328
9617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.713289617
Directory /workspace/34.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/34.usbdev_rx_full.4265478380
Short name T2904
Test name
Test status
Simulation time 391439960 ps
CPU time 1.28 seconds
Started Aug 02 05:33:04 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 207388 kb
Host smart-3bdcd744-3014-46af-aa6c-7aa95103152a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42654
78380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_full.4265478380
Directory /workspace/34.usbdev_rx_full/latest


Test location /workspace/coverage/default/34.usbdev_setup_stage.3329710167
Short name T1204
Test name
Test status
Simulation time 189671584 ps
CPU time 0.87 seconds
Started Aug 02 05:32:43 PM PDT 24
Finished Aug 02 05:32:44 PM PDT 24
Peak memory 206992 kb
Host smart-89b02c88-fa8e-40e6-9f39-c4f2e7456099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33297
10167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3329710167
Directory /workspace/34.usbdev_setup_stage/latest


Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1477790104
Short name T2858
Test name
Test status
Simulation time 143814627 ps
CPU time 0.79 seconds
Started Aug 02 05:32:55 PM PDT 24
Finished Aug 02 05:32:56 PM PDT 24
Peak memory 207336 kb
Host smart-86e0ec2a-4199-4da1-b840-43d491bcac8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14777
90104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1477790104
Directory /workspace/34.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/34.usbdev_smoke.1543593994
Short name T2789
Test name
Test status
Simulation time 231462235 ps
CPU time 0.99 seconds
Started Aug 02 05:33:50 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 207200 kb
Host smart-83fc9066-a525-41ef-aed5-c09350f1a13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15435
93994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1543593994
Directory /workspace/34.usbdev_smoke/latest


Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1651751546
Short name T734
Test name
Test status
Simulation time 2092309731 ps
CPU time 19.68 seconds
Started Aug 02 05:33:00 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 223796 kb
Host smart-eaa27c59-5e8f-42bf-9a9c-1752f35a6a9b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1651751546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1651751546
Directory /workspace/34.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1214652125
Short name T109
Test name
Test status
Simulation time 157211772 ps
CPU time 0.91 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207416 kb
Host smart-b93f84f5-f954-4c86-807e-cdc3ddabd7be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12146
52125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1214652125
Directory /workspace/34.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/34.usbdev_stall_trans.415730510
Short name T1786
Test name
Test status
Simulation time 204225788 ps
CPU time 0.92 seconds
Started Aug 02 05:32:41 PM PDT 24
Finished Aug 02 05:32:42 PM PDT 24
Peak memory 207416 kb
Host smart-fa00930f-3c12-4d66-9a34-8e7109d87e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41573
0510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.415730510
Directory /workspace/34.usbdev_stall_trans/latest


Test location /workspace/coverage/default/34.usbdev_stream_len_max.1843260518
Short name T1844
Test name
Test status
Simulation time 725776906 ps
CPU time 2.05 seconds
Started Aug 02 05:32:53 PM PDT 24
Finished Aug 02 05:32:55 PM PDT 24
Peak memory 207360 kb
Host smart-c73be139-d843-4b30-8a95-40c9f73ad6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18432
60518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1843260518
Directory /workspace/34.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/34.usbdev_streaming_out.2105158821
Short name T1825
Test name
Test status
Simulation time 2938745768 ps
CPU time 80.22 seconds
Started Aug 02 05:32:54 PM PDT 24
Finished Aug 02 05:34:14 PM PDT 24
Peak memory 217564 kb
Host smart-8729de97-ba8f-4ec3-9846-d757a1bdabc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21051
58821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2105158821
Directory /workspace/34.usbdev_streaming_out/latest


Test location /workspace/coverage/default/34.usbdev_timeout_missing_host_handshake.2335024895
Short name T918
Test name
Test status
Simulation time 725504385 ps
CPU time 13.61 seconds
Started Aug 02 05:34:02 PM PDT 24
Finished Aug 02 05:34:15 PM PDT 24
Peak memory 207400 kb
Host smart-24a5cd5a-2753-4924-853e-b0ced8164704
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335024895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_timeout_missing_hos
t_handshake.2335024895
Directory /workspace/34.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/35.usbdev_alert_test.2249154913
Short name T2673
Test name
Test status
Simulation time 43025609 ps
CPU time 0.65 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:02 PM PDT 24
Peak memory 207420 kb
Host smart-25623996-7a8f-4574-a950-c49dbcc46fd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2249154913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2249154913
Directory /workspace/35.usbdev_alert_test/latest


Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3624965709
Short name T703
Test name
Test status
Simulation time 9047897654 ps
CPU time 12.22 seconds
Started Aug 02 05:32:53 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 207664 kb
Host smart-1ae0712e-1c86-4dfd-acf2-b6f0ff87bbbe
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624965709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_a
on_wake_disconnect.3624965709
Directory /workspace/35.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2623811223
Short name T2103
Test name
Test status
Simulation time 20654319845 ps
CPU time 22.2 seconds
Started Aug 02 05:33:04 PM PDT 24
Finished Aug 02 05:33:26 PM PDT 24
Peak memory 207628 kb
Host smart-3781d53c-71ec-4f5d-9b53-a6df79bfc0a9
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623811223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2623811223
Directory /workspace/35.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.355151961
Short name T830
Test name
Test status
Simulation time 24093616832 ps
CPU time 27.54 seconds
Started Aug 02 05:33:06 PM PDT 24
Finished Aug 02 05:33:34 PM PDT 24
Peak memory 215824 kb
Host smart-ed7b68fe-02ea-459e-ad38-a4c55a2f6901
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355151961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_ao
n_wake_resume.355151961
Directory /workspace/35.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/35.usbdev_av_buffer.2382888675
Short name T1532
Test name
Test status
Simulation time 154828708 ps
CPU time 0.91 seconds
Started Aug 02 05:32:43 PM PDT 24
Finished Aug 02 05:32:44 PM PDT 24
Peak memory 207400 kb
Host smart-287d0edf-5563-405e-be34-94f0cd417d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23828
88675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2382888675
Directory /workspace/35.usbdev_av_buffer/latest


Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1910535532
Short name T2158
Test name
Test status
Simulation time 164326532 ps
CPU time 0.88 seconds
Started Aug 02 05:33:06 PM PDT 24
Finished Aug 02 05:33:07 PM PDT 24
Peak memory 207356 kb
Host smart-1403c0b7-c61d-4601-8c28-5b6b4723693c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
35532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1910535532
Directory /workspace/35.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.928267272
Short name T1572
Test name
Test status
Simulation time 396159863 ps
CPU time 1.34 seconds
Started Aug 02 05:32:58 PM PDT 24
Finished Aug 02 05:33:00 PM PDT 24
Peak memory 207340 kb
Host smart-aa863f4f-bc70-47b3-b1a0-98303c2a3cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92826
7272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.928267272
Directory /workspace/35.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.2855065573
Short name T982
Test name
Test status
Simulation time 272357440 ps
CPU time 1.03 seconds
Started Aug 02 05:32:54 PM PDT 24
Finished Aug 02 05:32:55 PM PDT 24
Peak memory 207384 kb
Host smart-1c7fc74a-5663-4fbc-82ff-24daea6af012
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2855065573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.2855065573
Directory /workspace/35.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/35.usbdev_device_address.4080397582
Short name T91
Test name
Test status
Simulation time 54055896423 ps
CPU time 91.33 seconds
Started Aug 02 05:33:07 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 207700 kb
Host smart-2258375c-083e-4821-81ee-a12b9f7e6cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40803
97582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.4080397582
Directory /workspace/35.usbdev_device_address/latest


Test location /workspace/coverage/default/35.usbdev_device_timeout.3061764667
Short name T1839
Test name
Test status
Simulation time 2926059440 ps
CPU time 27.21 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:28 PM PDT 24
Peak memory 207644 kb
Host smart-a6225b93-a2a1-4b63-af8c-40c7d68a96aa
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061764667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.3061764667
Directory /workspace/35.usbdev_device_timeout/latest


Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1335269998
Short name T1632
Test name
Test status
Simulation time 727156856 ps
CPU time 1.75 seconds
Started Aug 02 05:32:48 PM PDT 24
Finished Aug 02 05:32:50 PM PDT 24
Peak memory 207368 kb
Host smart-b202c341-7596-4f97-85e9-92994ce72a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13352
69998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1335269998
Directory /workspace/35.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/35.usbdev_disconnected.1565797169
Short name T1441
Test name
Test status
Simulation time 193569585 ps
CPU time 0.83 seconds
Started Aug 02 05:32:41 PM PDT 24
Finished Aug 02 05:32:42 PM PDT 24
Peak memory 207316 kb
Host smart-0e93048a-5551-4b1a-ae18-bcd98eae41dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15657
97169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1565797169
Directory /workspace/35.usbdev_disconnected/latest


Test location /workspace/coverage/default/35.usbdev_enable.3240067403
Short name T1344
Test name
Test status
Simulation time 98633840 ps
CPU time 0.75 seconds
Started Aug 02 05:32:57 PM PDT 24
Finished Aug 02 05:32:57 PM PDT 24
Peak memory 207388 kb
Host smart-a2b5f8bb-434f-4c03-89c7-734676c6d23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32400
67403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3240067403
Directory /workspace/35.usbdev_enable/latest


Test location /workspace/coverage/default/35.usbdev_endpoint_access.1241397672
Short name T2685
Test name
Test status
Simulation time 929499363 ps
CPU time 2.54 seconds
Started Aug 02 05:32:55 PM PDT 24
Finished Aug 02 05:32:57 PM PDT 24
Peak memory 207592 kb
Host smart-48247308-9ba6-414a-95eb-e6163e89c733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12413
97672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1241397672
Directory /workspace/35.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/35.usbdev_endpoint_types.3236672601
Short name T425
Test name
Test status
Simulation time 340764488 ps
CPU time 1.22 seconds
Started Aug 02 05:33:11 PM PDT 24
Finished Aug 02 05:33:22 PM PDT 24
Peak memory 207368 kb
Host smart-8c1f88f8-9c63-450d-b650-1c529e4dbb64
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3236672601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_types.3236672601
Directory /workspace/35.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/35.usbdev_fifo_rst.1296722735
Short name T2877
Test name
Test status
Simulation time 253670577 ps
CPU time 1.63 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 207472 kb
Host smart-60a59a92-b2db-429e-a2d2-9f61e591e6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12967
22735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1296722735
Directory /workspace/35.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/35.usbdev_in_iso.542001076
Short name T760
Test name
Test status
Simulation time 219231204 ps
CPU time 0.95 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:03 PM PDT 24
Peak memory 207460 kb
Host smart-1a099b06-b5f0-4dc4-a123-57c95a457a97
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=542001076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.542001076
Directory /workspace/35.usbdev_in_iso/latest


Test location /workspace/coverage/default/35.usbdev_in_stall.917191798
Short name T2954
Test name
Test status
Simulation time 139561809 ps
CPU time 0.76 seconds
Started Aug 02 05:33:05 PM PDT 24
Finished Aug 02 05:33:06 PM PDT 24
Peak memory 207340 kb
Host smart-573fba41-69a1-497f-b114-128417c8d748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91719
1798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.917191798
Directory /workspace/35.usbdev_in_stall/latest


Test location /workspace/coverage/default/35.usbdev_in_trans.4118170706
Short name T2508
Test name
Test status
Simulation time 186476771 ps
CPU time 0.85 seconds
Started Aug 02 05:32:56 PM PDT 24
Finished Aug 02 05:32:57 PM PDT 24
Peak memory 207372 kb
Host smart-d6e1b491-f169-4484-bf01-2e9d470344f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41181
70706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.4118170706
Directory /workspace/35.usbdev_in_trans/latest


Test location /workspace/coverage/default/35.usbdev_invalid_sync.3675725406
Short name T1317
Test name
Test status
Simulation time 4784602801 ps
CPU time 142.5 seconds
Started Aug 02 05:32:52 PM PDT 24
Finished Aug 02 05:35:15 PM PDT 24
Peak memory 224048 kb
Host smart-f9a36f0d-2bef-4fc6-b242-386e667a9223
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3675725406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3675725406
Directory /workspace/35.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/35.usbdev_iso_retraction.932763578
Short name T1863
Test name
Test status
Simulation time 8018514942 ps
CPU time 51.28 seconds
Started Aug 02 05:33:00 PM PDT 24
Finished Aug 02 05:33:56 PM PDT 24
Peak memory 207612 kb
Host smart-8bcf2308-5745-4eec-bb5e-4b977bdad78d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=932763578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.932763578
Directory /workspace/35.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/35.usbdev_link_in_err.1703337722
Short name T2062
Test name
Test status
Simulation time 236494162 ps
CPU time 1 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207344 kb
Host smart-77651d1d-7ead-418d-b3a0-3380c9df941f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
37722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1703337722
Directory /workspace/35.usbdev_link_in_err/latest


Test location /workspace/coverage/default/35.usbdev_link_resume.3448059864
Short name T2284
Test name
Test status
Simulation time 12139397023 ps
CPU time 17.05 seconds
Started Aug 02 05:32:59 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207740 kb
Host smart-ebcb362d-e69b-4400-8c7f-03e654c3a2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34480
59864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.3448059864
Directory /workspace/35.usbdev_link_resume/latest


Test location /workspace/coverage/default/35.usbdev_link_suspend.1488019899
Short name T1129
Test name
Test status
Simulation time 5354974298 ps
CPU time 6.67 seconds
Started Aug 02 05:33:06 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 216684 kb
Host smart-3d3b6cb6-07ab-40c6-89bd-894d0c3b4380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14880
19899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.1488019899
Directory /workspace/35.usbdev_link_suspend/latest


Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2700399088
Short name T2837
Test name
Test status
Simulation time 4801002883 ps
CPU time 44.58 seconds
Started Aug 02 05:33:04 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 224080 kb
Host smart-194b9bca-ce49-415e-9d13-b6ad529c105b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27003
99088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2700399088
Directory /workspace/35.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2579399890
Short name T834
Test name
Test status
Simulation time 2187508470 ps
CPU time 16.37 seconds
Started Aug 02 05:32:59 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 217372 kb
Host smart-d55cc2f7-5d62-4db3-aacd-4205db4f71d0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2579399890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2579399890
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.1408249541
Short name T2198
Test name
Test status
Simulation time 252208238 ps
CPU time 1.02 seconds
Started Aug 02 05:32:58 PM PDT 24
Finished Aug 02 05:32:59 PM PDT 24
Peak memory 207408 kb
Host smart-96c902ef-bb5e-4b77-818b-aedf723f4667
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1408249541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.1408249541
Directory /workspace/35.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1687995689
Short name T948
Test name
Test status
Simulation time 184821997 ps
CPU time 0.92 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207400 kb
Host smart-3c2e8da3-0f12-4d35-81a3-e52026106e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16879
95689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1687995689
Directory /workspace/35.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2305076211
Short name T638
Test name
Test status
Simulation time 2889369958 ps
CPU time 21.87 seconds
Started Aug 02 05:33:09 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 215900 kb
Host smart-116aff25-06ba-4935-8188-1113627bdb71
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2305076211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2305076211
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.4115714987
Short name T799
Test name
Test status
Simulation time 233699084 ps
CPU time 0.97 seconds
Started Aug 02 05:32:51 PM PDT 24
Finished Aug 02 05:32:52 PM PDT 24
Peak memory 207372 kb
Host smart-f1892b62-834a-493a-a52b-753e0ddb04ec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4115714987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.4115714987
Directory /workspace/35.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.2107601378
Short name T2874
Test name
Test status
Simulation time 216573028 ps
CPU time 0.95 seconds
Started Aug 02 05:33:07 PM PDT 24
Finished Aug 02 05:33:08 PM PDT 24
Peak memory 207352 kb
Host smart-32f5e03e-5b32-404a-984c-257b3b79b473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21076
01378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.2107601378
Directory /workspace/35.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_out_iso.2289902031
Short name T257
Test name
Test status
Simulation time 143767931 ps
CPU time 0.89 seconds
Started Aug 02 05:33:21 PM PDT 24
Finished Aug 02 05:33:22 PM PDT 24
Peak memory 207376 kb
Host smart-32778878-2c39-49d9-8e1b-1244f70edfa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22899
02031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2289902031
Directory /workspace/35.usbdev_out_iso/latest


Test location /workspace/coverage/default/35.usbdev_out_stall.1986309595
Short name T625
Test name
Test status
Simulation time 196407201 ps
CPU time 0.9 seconds
Started Aug 02 05:32:58 PM PDT 24
Finished Aug 02 05:32:59 PM PDT 24
Peak memory 207416 kb
Host smart-eaa15406-7f90-4f65-ad1e-f4de4c2346c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19863
09595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1986309595
Directory /workspace/35.usbdev_out_stall/latest


Test location /workspace/coverage/default/35.usbdev_out_trans_nak.759068294
Short name T1857
Test name
Test status
Simulation time 239103209 ps
CPU time 0.91 seconds
Started Aug 02 05:32:52 PM PDT 24
Finished Aug 02 05:32:53 PM PDT 24
Peak memory 207372 kb
Host smart-d768b803-f432-4417-ae5f-438656d8c3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75906
8294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.759068294
Directory /workspace/35.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/35.usbdev_pending_in_trans.2628976730
Short name T1521
Test name
Test status
Simulation time 170845571 ps
CPU time 0.94 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:03 PM PDT 24
Peak memory 207404 kb
Host smart-be8c10ff-9594-4555-b6d1-0c123235e1b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26289
76730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.2628976730
Directory /workspace/35.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2230118808
Short name T1463
Test name
Test status
Simulation time 259541043 ps
CPU time 1.09 seconds
Started Aug 02 05:33:05 PM PDT 24
Finished Aug 02 05:33:06 PM PDT 24
Peak memory 207348 kb
Host smart-0c41fc1c-5c1e-4eeb-96b5-dbfb80a57eee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2230118808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2230118808
Directory /workspace/35.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.3392744092
Short name T1736
Test name
Test status
Simulation time 135410496 ps
CPU time 0.78 seconds
Started Aug 02 05:32:59 PM PDT 24
Finished Aug 02 05:33:00 PM PDT 24
Peak memory 207312 kb
Host smart-c9b442b6-14ad-4f8f-a027-78be204aae85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33927
44092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.3392744092
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1735593904
Short name T29
Test name
Test status
Simulation time 52185943 ps
CPU time 0.8 seconds
Started Aug 02 05:33:07 PM PDT 24
Finished Aug 02 05:33:09 PM PDT 24
Peak memory 207316 kb
Host smart-3bba838a-a4fe-440a-9d0d-631a0cae60b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17355
93904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1735593904
Directory /workspace/35.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/35.usbdev_pkt_buffer.58748235
Short name T1499
Test name
Test status
Simulation time 22391335192 ps
CPU time 59.97 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:34:15 PM PDT 24
Peak memory 215824 kb
Host smart-e7c300d9-8477-483b-88c0-5ce24f078384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58748
235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.58748235
Directory /workspace/35.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/35.usbdev_pkt_received.3637416314
Short name T1590
Test name
Test status
Simulation time 171824051 ps
CPU time 0.86 seconds
Started Aug 02 05:33:04 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 207400 kb
Host smart-da626c80-962d-48a0-8aae-588b81560903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36374
16314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3637416314
Directory /workspace/35.usbdev_pkt_received/latest


Test location /workspace/coverage/default/35.usbdev_pkt_sent.4019711770
Short name T491
Test name
Test status
Simulation time 244447376 ps
CPU time 0.97 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:02 PM PDT 24
Peak memory 207424 kb
Host smart-0c8b432d-5b35-47d2-a248-a706d63cc6ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40197
11770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.4019711770
Directory /workspace/35.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.1226847976
Short name T1150
Test name
Test status
Simulation time 221247315 ps
CPU time 0.95 seconds
Started Aug 02 05:33:08 PM PDT 24
Finished Aug 02 05:33:09 PM PDT 24
Peak memory 207396 kb
Host smart-f20a7156-e0ec-46e5-a221-e38f0e47ab4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12268
47976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.1226847976
Directory /workspace/35.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2399776843
Short name T2370
Test name
Test status
Simulation time 198116324 ps
CPU time 0.92 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:04 PM PDT 24
Peak memory 207432 kb
Host smart-b561ca18-61fb-47ab-a37e-9ac891775a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23997
76843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2399776843
Directory /workspace/35.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2931358958
Short name T2898
Test name
Test status
Simulation time 144724954 ps
CPU time 0.77 seconds
Started Aug 02 05:33:10 PM PDT 24
Finished Aug 02 05:33:11 PM PDT 24
Peak memory 207324 kb
Host smart-9f5d03bb-6ba4-49c1-9ee1-d063e8194513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29313
58958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2931358958
Directory /workspace/35.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/35.usbdev_rx_full.3865170873
Short name T827
Test name
Test status
Simulation time 333129785 ps
CPU time 1.2 seconds
Started Aug 02 05:32:59 PM PDT 24
Finished Aug 02 05:33:00 PM PDT 24
Peak memory 207380 kb
Host smart-a6a66098-8c16-4db4-9658-cd26540987c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38651
70873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_full.3865170873
Directory /workspace/35.usbdev_rx_full/latest


Test location /workspace/coverage/default/35.usbdev_setup_stage.2460315320
Short name T1647
Test name
Test status
Simulation time 163261214 ps
CPU time 0.9 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:03 PM PDT 24
Peak memory 207368 kb
Host smart-3ce7b15a-1043-4d7c-8b8a-662e5d8bfc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24603
15320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2460315320
Directory /workspace/35.usbdev_setup_stage/latest


Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.2323183522
Short name T124
Test name
Test status
Simulation time 146213604 ps
CPU time 0.89 seconds
Started Aug 02 05:33:30 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 207300 kb
Host smart-28ab8e7a-6c0d-4191-b0d9-7b1167079ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23231
83522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.2323183522
Directory /workspace/35.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/35.usbdev_smoke.2348791617
Short name T1442
Test name
Test status
Simulation time 219860337 ps
CPU time 1.11 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:02 PM PDT 24
Peak memory 207384 kb
Host smart-2188946b-4fe5-4c23-8e14-9280d52a240a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23487
91617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2348791617
Directory /workspace/35.usbdev_smoke/latest


Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.1358899820
Short name T2612
Test name
Test status
Simulation time 2123189728 ps
CPU time 16.08 seconds
Started Aug 02 05:32:52 PM PDT 24
Finished Aug 02 05:33:08 PM PDT 24
Peak memory 223936 kb
Host smart-0d9d48e6-42b8-4f6d-8250-61acd26e3142
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1358899820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.1358899820
Directory /workspace/35.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1262567769
Short name T3036
Test name
Test status
Simulation time 147284889 ps
CPU time 0.84 seconds
Started Aug 02 05:33:07 PM PDT 24
Finished Aug 02 05:33:08 PM PDT 24
Peak memory 207444 kb
Host smart-359a4000-8554-4873-ab9e-914d559f7b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12625
67769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1262567769
Directory /workspace/35.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/35.usbdev_stall_trans.4192962579
Short name T2886
Test name
Test status
Simulation time 238068119 ps
CPU time 0.9 seconds
Started Aug 02 05:33:03 PM PDT 24
Finished Aug 02 05:33:04 PM PDT 24
Peak memory 207332 kb
Host smart-f71d95e9-a599-4868-a239-7e5e2c38fe98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41929
62579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.4192962579
Directory /workspace/35.usbdev_stall_trans/latest


Test location /workspace/coverage/default/35.usbdev_stream_len_max.645190208
Short name T2561
Test name
Test status
Simulation time 1119694144 ps
CPU time 2.81 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:04 PM PDT 24
Peak memory 207592 kb
Host smart-6bb39405-7a86-4d1d-87f0-f9e223c4ae61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64519
0208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.645190208
Directory /workspace/35.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/35.usbdev_streaming_out.1554133522
Short name T2460
Test name
Test status
Simulation time 3492207571 ps
CPU time 25.42 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:38 PM PDT 24
Peak memory 207652 kb
Host smart-67949a90-11b5-43bb-931d-7407392d38a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15541
33522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.1554133522
Directory /workspace/35.usbdev_streaming_out/latest


Test location /workspace/coverage/default/35.usbdev_timeout_missing_host_handshake.3618749757
Short name T748
Test name
Test status
Simulation time 318031816 ps
CPU time 4.47 seconds
Started Aug 02 05:32:42 PM PDT 24
Finished Aug 02 05:32:46 PM PDT 24
Peak memory 207480 kb
Host smart-6fa20e76-fdf2-417f-9884-805466b31eb8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618749757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_timeout_missing_hos
t_handshake.3618749757
Directory /workspace/35.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/36.usbdev_alert_test.2788336905
Short name T2791
Test name
Test status
Simulation time 47094905 ps
CPU time 0.69 seconds
Started Aug 02 05:33:08 PM PDT 24
Finished Aug 02 05:33:09 PM PDT 24
Peak memory 207484 kb
Host smart-aecc9baf-255c-4ac2-b462-865f54dad1bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2788336905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2788336905
Directory /workspace/36.usbdev_alert_test/latest


Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.886908609
Short name T1174
Test name
Test status
Simulation time 6038487853 ps
CPU time 8.36 seconds
Started Aug 02 05:32:58 PM PDT 24
Finished Aug 02 05:33:06 PM PDT 24
Peak memory 215880 kb
Host smart-7c59d26e-d57f-445b-94a2-698578f062be
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886908609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_ao
n_wake_disconnect.886908609
Directory /workspace/36.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.4237177818
Short name T1766
Test name
Test status
Simulation time 14953371953 ps
CPU time 16.74 seconds
Started Aug 02 05:33:08 PM PDT 24
Finished Aug 02 05:33:25 PM PDT 24
Peak memory 215852 kb
Host smart-db215ec2-6786-4868-92a3-790a28f4b976
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237177818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.4237177818
Directory /workspace/36.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.4249074142
Short name T199
Test name
Test status
Simulation time 24177473336 ps
CPU time 29.62 seconds
Started Aug 02 05:32:59 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 215824 kb
Host smart-c632ea17-e775-4a1b-9047-323103b5a452
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249074142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_a
on_wake_resume.4249074142
Directory /workspace/36.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/36.usbdev_av_buffer.1217847021
Short name T2234
Test name
Test status
Simulation time 161168061 ps
CPU time 0.83 seconds
Started Aug 02 05:33:00 PM PDT 24
Finished Aug 02 05:33:01 PM PDT 24
Peak memory 207400 kb
Host smart-9828241d-a5f2-4640-97b3-74c8383ab03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12178
47021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.1217847021
Directory /workspace/36.usbdev_av_buffer/latest


Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1206472352
Short name T2142
Test name
Test status
Simulation time 175705329 ps
CPU time 0.86 seconds
Started Aug 02 05:33:08 PM PDT 24
Finished Aug 02 05:33:09 PM PDT 24
Peak memory 207336 kb
Host smart-1eb9cee2-9e3f-46f9-82a6-b12257131bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12064
72352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1206472352
Directory /workspace/36.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.3250615830
Short name T1372
Test name
Test status
Simulation time 248693613 ps
CPU time 1.06 seconds
Started Aug 02 05:32:58 PM PDT 24
Finished Aug 02 05:32:59 PM PDT 24
Peak memory 207372 kb
Host smart-83d96b24-aeb3-4380-8def-31809954d93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32506
15830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.3250615830
Directory /workspace/36.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2772712386
Short name T85
Test name
Test status
Simulation time 857441528 ps
CPU time 2.31 seconds
Started Aug 02 05:33:04 PM PDT 24
Finished Aug 02 05:33:06 PM PDT 24
Peak memory 207636 kb
Host smart-9b102480-cdf3-42e5-b9c0-741278ca1c3a
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2772712386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2772712386
Directory /workspace/36.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/36.usbdev_device_address.1525250918
Short name T2666
Test name
Test status
Simulation time 54563075469 ps
CPU time 88.83 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:34:30 PM PDT 24
Peak memory 207688 kb
Host smart-5273958d-a579-4d3a-afb9-3acfa7ffb644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15252
50918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1525250918
Directory /workspace/36.usbdev_device_address/latest


Test location /workspace/coverage/default/36.usbdev_device_timeout.2243125908
Short name T1494
Test name
Test status
Simulation time 820637068 ps
CPU time 5.55 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:06 PM PDT 24
Peak memory 207560 kb
Host smart-4ab65aa0-b783-43ad-8fa8-6ab06d35a700
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243125908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_timeout.2243125908
Directory /workspace/36.usbdev_device_timeout/latest


Test location /workspace/coverage/default/36.usbdev_disable_endpoint.3856201849
Short name T305
Test name
Test status
Simulation time 1087857038 ps
CPU time 2.31 seconds
Started Aug 02 05:33:10 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207364 kb
Host smart-d54f1070-b61b-42d7-85f2-4d8db228b5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38562
01849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.3856201849
Directory /workspace/36.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/36.usbdev_disconnected.3585610509
Short name T2801
Test name
Test status
Simulation time 196807656 ps
CPU time 0.9 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:04 PM PDT 24
Peak memory 207348 kb
Host smart-d6a3cd4c-8388-479b-a590-24a67becd30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35856
10509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.3585610509
Directory /workspace/36.usbdev_disconnected/latest


Test location /workspace/coverage/default/36.usbdev_enable.770196571
Short name T1593
Test name
Test status
Simulation time 42343371 ps
CPU time 0.72 seconds
Started Aug 02 05:32:58 PM PDT 24
Finished Aug 02 05:32:59 PM PDT 24
Peak memory 207316 kb
Host smart-169596cb-a770-4628-8604-63965ef4124d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77019
6571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.770196571
Directory /workspace/36.usbdev_enable/latest


Test location /workspace/coverage/default/36.usbdev_endpoint_access.74692928
Short name T1809
Test name
Test status
Simulation time 773644855 ps
CPU time 2.14 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:03 PM PDT 24
Peak memory 207592 kb
Host smart-aed07342-be8e-45b6-a8e6-2e8d02c3e1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74692
928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.74692928
Directory /workspace/36.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/36.usbdev_fifo_rst.1338048680
Short name T1455
Test name
Test status
Simulation time 198793357 ps
CPU time 1.3 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:03 PM PDT 24
Peak memory 207552 kb
Host smart-dc9a129f-7d8a-467f-99b4-5f4cff4339cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13380
48680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1338048680
Directory /workspace/36.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/36.usbdev_in_iso.312054149
Short name T95
Test name
Test status
Simulation time 208341844 ps
CPU time 1 seconds
Started Aug 02 05:33:07 PM PDT 24
Finished Aug 02 05:33:08 PM PDT 24
Peak memory 207556 kb
Host smart-1c95e6de-bce7-4ad9-beaf-819db30fc052
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=312054149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.312054149
Directory /workspace/36.usbdev_in_iso/latest


Test location /workspace/coverage/default/36.usbdev_in_stall.4150530477
Short name T2600
Test name
Test status
Simulation time 167909295 ps
CPU time 0.84 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207372 kb
Host smart-b2eb5efa-f1d6-42f1-839a-edb531c8f75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41505
30477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.4150530477
Directory /workspace/36.usbdev_in_stall/latest


Test location /workspace/coverage/default/36.usbdev_in_trans.307556070
Short name T1401
Test name
Test status
Simulation time 221463918 ps
CPU time 0.97 seconds
Started Aug 02 05:33:07 PM PDT 24
Finished Aug 02 05:33:09 PM PDT 24
Peak memory 207364 kb
Host smart-761a9a88-521e-4f2a-bd62-d11186fb545f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30755
6070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.307556070
Directory /workspace/36.usbdev_in_trans/latest


Test location /workspace/coverage/default/36.usbdev_invalid_sync.30753836
Short name T3014
Test name
Test status
Simulation time 4048352132 ps
CPU time 29.21 seconds
Started Aug 02 05:32:59 PM PDT 24
Finished Aug 02 05:33:28 PM PDT 24
Peak memory 217732 kb
Host smart-9a2f2964-e570-42ae-8609-19bb8bbbb9f7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=30753836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.30753836
Directory /workspace/36.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/36.usbdev_iso_retraction.1994903381
Short name T715
Test name
Test status
Simulation time 13625559845 ps
CPU time 87.86 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:34:30 PM PDT 24
Peak memory 207628 kb
Host smart-7c3428a3-d408-46ec-8df4-aba2fa380a5b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1994903381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.1994903381
Directory /workspace/36.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/36.usbdev_link_in_err.3313399545
Short name T603
Test name
Test status
Simulation time 170342050 ps
CPU time 0.9 seconds
Started Aug 02 05:33:14 PM PDT 24
Finished Aug 02 05:33:15 PM PDT 24
Peak memory 207384 kb
Host smart-0c98c786-850d-442d-b1dc-5c1bb69d2534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33133
99545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.3313399545
Directory /workspace/36.usbdev_link_in_err/latest


Test location /workspace/coverage/default/36.usbdev_link_suspend.3073260173
Short name T957
Test name
Test status
Simulation time 11346508177 ps
CPU time 12.97 seconds
Started Aug 02 05:33:10 PM PDT 24
Finished Aug 02 05:33:23 PM PDT 24
Peak memory 207592 kb
Host smart-fe88d0e4-fef5-40cf-9d70-36e2af743924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30732
60173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3073260173
Directory /workspace/36.usbdev_link_suspend/latest


Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2316008603
Short name T1102
Test name
Test status
Simulation time 4606193065 ps
CPU time 41.83 seconds
Started Aug 02 05:33:14 PM PDT 24
Finished Aug 02 05:33:56 PM PDT 24
Peak memory 218364 kb
Host smart-113a3eac-ea61-4ce6-af61-e35c6b218721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23160
08603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2316008603
Directory /workspace/36.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.2333068340
Short name T538
Test name
Test status
Simulation time 2316074104 ps
CPU time 22.1 seconds
Started Aug 02 05:33:23 PM PDT 24
Finished Aug 02 05:33:45 PM PDT 24
Peak memory 215868 kb
Host smart-8fe1a69e-c3c5-4f03-9a82-bd82f75db700
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2333068340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.2333068340
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.1165519284
Short name T2383
Test name
Test status
Simulation time 248065406 ps
CPU time 0.99 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207392 kb
Host smart-e2dc4139-0cd6-4c03-b09b-0750c0b8ea7a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1165519284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.1165519284
Directory /workspace/36.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.4153096281
Short name T2189
Test name
Test status
Simulation time 194363747 ps
CPU time 0.91 seconds
Started Aug 02 05:33:14 PM PDT 24
Finished Aug 02 05:33:15 PM PDT 24
Peak memory 207280 kb
Host smart-e5be5dd8-fa2e-4366-b441-6988c5725731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41530
96281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.4153096281
Directory /workspace/36.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.968622856
Short name T2042
Test name
Test status
Simulation time 1918609669 ps
CPU time 19.45 seconds
Started Aug 02 05:33:00 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 217152 kb
Host smart-c5bc37e5-5af2-473b-bc88-1e17638c6dec
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=968622856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.968622856
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1288673211
Short name T2024
Test name
Test status
Simulation time 152313273 ps
CPU time 0.84 seconds
Started Aug 02 05:32:55 PM PDT 24
Finished Aug 02 05:32:56 PM PDT 24
Peak memory 207360 kb
Host smart-17fe2c24-bbbb-41d9-918f-7791b358b7ea
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1288673211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1288673211
Directory /workspace/36.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.1174861710
Short name T3004
Test name
Test status
Simulation time 137814809 ps
CPU time 0.85 seconds
Started Aug 02 05:33:04 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 207316 kb
Host smart-1e26f731-c977-4f57-8c5f-c09cc41873ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11748
61710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.1174861710
Directory /workspace/36.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_nak_trans.1807358547
Short name T163
Test name
Test status
Simulation time 234762022 ps
CPU time 0.98 seconds
Started Aug 02 05:33:11 PM PDT 24
Finished Aug 02 05:33:12 PM PDT 24
Peak memory 207316 kb
Host smart-6aa24436-58d4-4a0a-a625-bdfb661b5e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18073
58547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1807358547
Directory /workspace/36.usbdev_nak_trans/latest


Test location /workspace/coverage/default/36.usbdev_out_iso.3656475892
Short name T99
Test name
Test status
Simulation time 210050569 ps
CPU time 0.95 seconds
Started Aug 02 05:33:08 PM PDT 24
Finished Aug 02 05:33:09 PM PDT 24
Peak memory 207436 kb
Host smart-bd2f5fa4-c977-46f8-ab2a-7e5fae472f7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36564
75892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.3656475892
Directory /workspace/36.usbdev_out_iso/latest


Test location /workspace/coverage/default/36.usbdev_out_stall.3349221629
Short name T746
Test name
Test status
Simulation time 181789110 ps
CPU time 0.9 seconds
Started Aug 02 05:33:08 PM PDT 24
Finished Aug 02 05:33:09 PM PDT 24
Peak memory 207404 kb
Host smart-ba2f002a-4aad-4c0f-aabf-d4c3a6de00dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33492
21629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.3349221629
Directory /workspace/36.usbdev_out_stall/latest


Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1033569362
Short name T587
Test name
Test status
Simulation time 155600375 ps
CPU time 0.81 seconds
Started Aug 02 05:33:10 PM PDT 24
Finished Aug 02 05:33:11 PM PDT 24
Peak memory 207352 kb
Host smart-9c6fc1d1-68f5-4eff-8ff8-247b3e9a4f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10335
69362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1033569362
Directory /workspace/36.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/36.usbdev_pending_in_trans.599608344
Short name T2602
Test name
Test status
Simulation time 157198758 ps
CPU time 0.87 seconds
Started Aug 02 05:33:06 PM PDT 24
Finished Aug 02 05:33:07 PM PDT 24
Peak memory 207360 kb
Host smart-401a94de-e645-4bec-a33a-f30b76d460c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59960
8344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.599608344
Directory /workspace/36.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.4107290148
Short name T2580
Test name
Test status
Simulation time 271845400 ps
CPU time 1.17 seconds
Started Aug 02 05:33:01 PM PDT 24
Finished Aug 02 05:33:03 PM PDT 24
Peak memory 207408 kb
Host smart-12cc4e9a-a100-41af-9043-0074228c2817
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4107290148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.4107290148
Directory /workspace/36.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.367354134
Short name T1961
Test name
Test status
Simulation time 229362777 ps
CPU time 0.93 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207376 kb
Host smart-910c1962-51c9-4f4e-ad8f-5d469817ff79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36735
4134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.367354134
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.577540770
Short name T2532
Test name
Test status
Simulation time 32270983 ps
CPU time 0.71 seconds
Started Aug 02 05:33:06 PM PDT 24
Finished Aug 02 05:33:07 PM PDT 24
Peak memory 207380 kb
Host smart-45374585-968e-4aa2-9474-5665eb85550f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57754
0770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.577540770
Directory /workspace/36.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/36.usbdev_pkt_buffer.81433234
Short name T262
Test name
Test status
Simulation time 5863825705 ps
CPU time 16.09 seconds
Started Aug 02 05:33:03 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 215896 kb
Host smart-c1ea7787-8d12-431c-9bc1-78328dbf1d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81433
234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.81433234
Directory /workspace/36.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/36.usbdev_pkt_received.704277427
Short name T2627
Test name
Test status
Simulation time 227687374 ps
CPU time 0.93 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 207352 kb
Host smart-abef5dd6-b5ff-4cc2-bfe7-b2c114cfbfaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70427
7427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.704277427
Directory /workspace/36.usbdev_pkt_received/latest


Test location /workspace/coverage/default/36.usbdev_pkt_sent.2396247744
Short name T1560
Test name
Test status
Simulation time 264069850 ps
CPU time 1.06 seconds
Started Aug 02 05:33:03 PM PDT 24
Finished Aug 02 05:33:04 PM PDT 24
Peak memory 207304 kb
Host smart-19cec058-7512-4414-a015-668e910f8f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23962
47744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.2396247744
Directory /workspace/36.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1261100033
Short name T1264
Test name
Test status
Simulation time 243100700 ps
CPU time 1.06 seconds
Started Aug 02 05:33:04 PM PDT 24
Finished Aug 02 05:33:06 PM PDT 24
Peak memory 207460 kb
Host smart-c18c52ab-253a-4c49-b1c8-1af076a28f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12611
00033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1261100033
Directory /workspace/36.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.4091952721
Short name T1209
Test name
Test status
Simulation time 181330654 ps
CPU time 0.9 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:04 PM PDT 24
Peak memory 207408 kb
Host smart-0809030b-94e5-47f7-94fb-bf3cc26964f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40919
52721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.4091952721
Directory /workspace/36.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/36.usbdev_rx_crc_err.1691452991
Short name T2693
Test name
Test status
Simulation time 194966866 ps
CPU time 0.9 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207404 kb
Host smart-5173acb8-361e-4919-82e0-d9e173cb338c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16914
52991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.1691452991
Directory /workspace/36.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/36.usbdev_rx_full.2829247514
Short name T794
Test name
Test status
Simulation time 395368427 ps
CPU time 1.26 seconds
Started Aug 02 05:33:03 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 207424 kb
Host smart-9ef21b82-4255-463d-a999-6ef53a3a321a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28292
47514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_full.2829247514
Directory /workspace/36.usbdev_rx_full/latest


Test location /workspace/coverage/default/36.usbdev_setup_stage.489898356
Short name T2293
Test name
Test status
Simulation time 150037881 ps
CPU time 0.86 seconds
Started Aug 02 05:33:05 PM PDT 24
Finished Aug 02 05:33:06 PM PDT 24
Peak memory 207368 kb
Host smart-3aacbd56-2778-40c4-8a4c-3b8d89d7d8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48989
8356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.489898356
Directory /workspace/36.usbdev_setup_stage/latest


Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.2487140524
Short name T1489
Test name
Test status
Simulation time 155191972 ps
CPU time 0.86 seconds
Started Aug 02 05:33:00 PM PDT 24
Finished Aug 02 05:33:01 PM PDT 24
Peak memory 207408 kb
Host smart-0cc712f8-e0cc-4b14-b173-847610bb9984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24871
40524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.2487140524
Directory /workspace/36.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/36.usbdev_smoke.3031300981
Short name T2338
Test name
Test status
Simulation time 276552229 ps
CPU time 1.16 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:04 PM PDT 24
Peak memory 207360 kb
Host smart-d62fdaf3-26a4-4e49-8c45-7b7ee4432164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30313
00981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3031300981
Directory /workspace/36.usbdev_smoke/latest


Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.1698600413
Short name T774
Test name
Test status
Simulation time 2842610014 ps
CPU time 76.09 seconds
Started Aug 02 05:33:08 PM PDT 24
Finished Aug 02 05:34:24 PM PDT 24
Peak memory 224048 kb
Host smart-9df986f7-878b-425c-9bf0-7c0c97b08858
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1698600413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.1698600413
Directory /workspace/36.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1357907613
Short name T2056
Test name
Test status
Simulation time 171240390 ps
CPU time 0.84 seconds
Started Aug 02 05:33:11 PM PDT 24
Finished Aug 02 05:33:12 PM PDT 24
Peak memory 207380 kb
Host smart-ca30f5e6-da31-4356-a70d-9c7cc39471c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13579
07613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1357907613
Directory /workspace/36.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/36.usbdev_stall_trans.1157882874
Short name T2604
Test name
Test status
Simulation time 197922468 ps
CPU time 0.91 seconds
Started Aug 02 05:33:03 PM PDT 24
Finished Aug 02 05:33:04 PM PDT 24
Peak memory 207400 kb
Host smart-b9817297-ffe2-420e-b87b-2bbd48ea0679
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11578
82874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.1157882874
Directory /workspace/36.usbdev_stall_trans/latest


Test location /workspace/coverage/default/36.usbdev_stream_len_max.3430755409
Short name T2306
Test name
Test status
Simulation time 963209394 ps
CPU time 2.51 seconds
Started Aug 02 05:33:09 PM PDT 24
Finished Aug 02 05:33:12 PM PDT 24
Peak memory 207460 kb
Host smart-e5752903-d52d-44a8-b4ae-32f2771ec0a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34307
55409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3430755409
Directory /workspace/36.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/36.usbdev_streaming_out.496136500
Short name T1449
Test name
Test status
Simulation time 2746629239 ps
CPU time 73.4 seconds
Started Aug 02 05:33:11 PM PDT 24
Finished Aug 02 05:34:25 PM PDT 24
Peak memory 215812 kb
Host smart-010b9bdd-fdc1-4f45-b241-18bf43af75e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49613
6500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.496136500
Directory /workspace/36.usbdev_streaming_out/latest


Test location /workspace/coverage/default/36.usbdev_timeout_missing_host_handshake.3255915193
Short name T2984
Test name
Test status
Simulation time 310590690 ps
CPU time 4.41 seconds
Started Aug 02 05:33:03 PM PDT 24
Finished Aug 02 05:33:08 PM PDT 24
Peak memory 207556 kb
Host smart-eb85aa61-8c54-4329-811d-52843ed09ea8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255915193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_timeout_missing_hos
t_handshake.3255915193
Directory /workspace/36.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/37.usbdev_alert_test.2257559575
Short name T1189
Test name
Test status
Simulation time 82827124 ps
CPU time 0.69 seconds
Started Aug 02 05:33:30 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 207544 kb
Host smart-0651196e-382f-4d6e-b474-7a3d77c8e389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2257559575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2257559575
Directory /workspace/37.usbdev_alert_test/latest


Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2656407236
Short name T2476
Test name
Test status
Simulation time 5692275742 ps
CPU time 8.55 seconds
Started Aug 02 05:33:10 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 215816 kb
Host smart-d37dee73-31d1-4e50-9d77-e12a6857305f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656407236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_a
on_wake_disconnect.2656407236
Directory /workspace/37.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.901614641
Short name T2031
Test name
Test status
Simulation time 20813582075 ps
CPU time 25.57 seconds
Started Aug 02 05:33:08 PM PDT 24
Finished Aug 02 05:33:33 PM PDT 24
Peak memory 207652 kb
Host smart-5ba16aab-aa75-4e11-9b7c-ad34ffb66a74
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=901614641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.901614641
Directory /workspace/37.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.911470010
Short name T16
Test name
Test status
Simulation time 28900107542 ps
CPU time 33.19 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 207616 kb
Host smart-d3fff79d-a82d-4498-92e3-8212b8b8d947
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911470010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_ao
n_wake_resume.911470010
Directory /workspace/37.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/37.usbdev_av_buffer.2850322516
Short name T1286
Test name
Test status
Simulation time 157933387 ps
CPU time 0.84 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207360 kb
Host smart-89394bf1-f452-4fda-b258-d200197168af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28503
22516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2850322516
Directory /workspace/37.usbdev_av_buffer/latest


Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1105072422
Short name T812
Test name
Test status
Simulation time 143711994 ps
CPU time 0.85 seconds
Started Aug 02 05:33:06 PM PDT 24
Finished Aug 02 05:33:07 PM PDT 24
Peak memory 207380 kb
Host smart-496f4c9a-85b8-4151-a4de-34fd19589759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11050
72422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1105072422
Directory /workspace/37.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2718105362
Short name T1910
Test name
Test status
Simulation time 398413033 ps
CPU time 1.56 seconds
Started Aug 02 05:33:03 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 207412 kb
Host smart-71a4c8ef-9dd0-462b-8f80-0d7c0ce2b0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27181
05362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2718105362
Directory /workspace/37.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.1369747958
Short name T2318
Test name
Test status
Simulation time 859871793 ps
CPU time 2.14 seconds
Started Aug 02 05:33:02 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 207648 kb
Host smart-3095f34d-fcc7-49e6-9024-56303958b9da
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1369747958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1369747958
Directory /workspace/37.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/37.usbdev_device_address.2730588032
Short name T1759
Test name
Test status
Simulation time 57675886125 ps
CPU time 88.78 seconds
Started Aug 02 05:33:03 PM PDT 24
Finished Aug 02 05:34:32 PM PDT 24
Peak memory 207612 kb
Host smart-e5f4916d-3fdb-4fb0-985f-69865adf3245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27305
88032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.2730588032
Directory /workspace/37.usbdev_device_address/latest


Test location /workspace/coverage/default/37.usbdev_device_timeout.45769454
Short name T1909
Test name
Test status
Simulation time 2508633870 ps
CPU time 21.66 seconds
Started Aug 02 05:33:03 PM PDT 24
Finished Aug 02 05:33:25 PM PDT 24
Peak memory 207584 kb
Host smart-f939f968-1adc-4999-8fbc-2f5b54aff4e7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45769454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_timeout.45769454
Directory /workspace/37.usbdev_device_timeout/latest


Test location /workspace/coverage/default/37.usbdev_disable_endpoint.247215537
Short name T769
Test name
Test status
Simulation time 1196969638 ps
CPU time 2.43 seconds
Started Aug 02 05:33:24 PM PDT 24
Finished Aug 02 05:33:26 PM PDT 24
Peak memory 207344 kb
Host smart-3844720f-3efc-4aff-b05a-0ba108d2ba33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24721
5537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.247215537
Directory /workspace/37.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/37.usbdev_disconnected.485316854
Short name T1276
Test name
Test status
Simulation time 164533687 ps
CPU time 0.84 seconds
Started Aug 02 05:33:04 PM PDT 24
Finished Aug 02 05:33:05 PM PDT 24
Peak memory 207288 kb
Host smart-fca90255-c6f8-4ea9-90ae-ae316a470afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48531
6854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.485316854
Directory /workspace/37.usbdev_disconnected/latest


Test location /workspace/coverage/default/37.usbdev_enable.1575061593
Short name T2014
Test name
Test status
Simulation time 60602602 ps
CPU time 0.71 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207324 kb
Host smart-df864560-4fa7-4024-8fc1-7c6dd49787e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15750
61593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1575061593
Directory /workspace/37.usbdev_enable/latest


Test location /workspace/coverage/default/37.usbdev_endpoint_access.2847324117
Short name T2624
Test name
Test status
Simulation time 876836858 ps
CPU time 2.41 seconds
Started Aug 02 05:33:07 PM PDT 24
Finished Aug 02 05:33:10 PM PDT 24
Peak memory 207620 kb
Host smart-28bbca3a-7261-401e-9f2d-e0fab592cc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28473
24117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2847324117
Directory /workspace/37.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/37.usbdev_endpoint_types.1096532560
Short name T450
Test name
Test status
Simulation time 537788055 ps
CPU time 1.57 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:15 PM PDT 24
Peak memory 207392 kb
Host smart-f8698462-0d21-48e2-8431-3016f164699b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1096532560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_types.1096532560
Directory /workspace/37.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/37.usbdev_fifo_rst.1445852150
Short name T1259
Test name
Test status
Simulation time 169648529 ps
CPU time 2.02 seconds
Started Aug 02 05:33:14 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207552 kb
Host smart-9cd29218-650b-45fa-95af-5498e2427761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14458
52150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1445852150
Directory /workspace/37.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/37.usbdev_in_iso.3953785984
Short name T2419
Test name
Test status
Simulation time 171816070 ps
CPU time 0.91 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 215744 kb
Host smart-31f8751d-8ded-4315-b1ba-6f3ff173d3f5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3953785984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3953785984
Directory /workspace/37.usbdev_in_iso/latest


Test location /workspace/coverage/default/37.usbdev_in_stall.4161826570
Short name T634
Test name
Test status
Simulation time 155503028 ps
CPU time 0.82 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207392 kb
Host smart-0c2696a5-6bab-4502-bd9c-e7d38028c783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41618
26570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4161826570
Directory /workspace/37.usbdev_in_stall/latest


Test location /workspace/coverage/default/37.usbdev_in_trans.766393527
Short name T661
Test name
Test status
Simulation time 226358587 ps
CPU time 1.05 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207332 kb
Host smart-5fb29847-d536-432f-8f3e-7d2aec7f213d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76639
3527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.766393527
Directory /workspace/37.usbdev_in_trans/latest


Test location /workspace/coverage/default/37.usbdev_invalid_sync.2325758178
Short name T1470
Test name
Test status
Simulation time 4727544398 ps
CPU time 35.62 seconds
Started Aug 02 05:33:26 PM PDT 24
Finished Aug 02 05:34:01 PM PDT 24
Peak memory 217740 kb
Host smart-31ac2de8-d3b6-46ae-97f9-ecc6111fa762
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2325758178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.2325758178
Directory /workspace/37.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/37.usbdev_link_in_err.3786306643
Short name T753
Test name
Test status
Simulation time 217913455 ps
CPU time 0.96 seconds
Started Aug 02 05:33:08 PM PDT 24
Finished Aug 02 05:33:09 PM PDT 24
Peak memory 207328 kb
Host smart-20beb0fe-2176-4ed3-ab1e-b62507e0bbad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37863
06643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3786306643
Directory /workspace/37.usbdev_link_in_err/latest


Test location /workspace/coverage/default/37.usbdev_link_resume.1754199396
Short name T1137
Test name
Test status
Simulation time 26491745688 ps
CPU time 41.59 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:55 PM PDT 24
Peak memory 215996 kb
Host smart-d02dcf5b-5e77-4dbd-b612-6bd6f8f9f96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17541
99396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1754199396
Directory /workspace/37.usbdev_link_resume/latest


Test location /workspace/coverage/default/37.usbdev_link_suspend.3032607922
Short name T2555
Test name
Test status
Simulation time 5904832823 ps
CPU time 8.44 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:33:26 PM PDT 24
Peak memory 215812 kb
Host smart-338f8fa7-8aa8-4ca5-9bc3-2cde582483bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30326
07922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3032607922
Directory /workspace/37.usbdev_link_suspend/latest


Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.2242740677
Short name T2735
Test name
Test status
Simulation time 3931516916 ps
CPU time 29.33 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:41 PM PDT 24
Peak memory 215864 kb
Host smart-38c59909-3e61-43dd-a3d8-8ed7a7c65572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22427
40677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.2242740677
Directory /workspace/37.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.3178796708
Short name T2400
Test name
Test status
Simulation time 3484475287 ps
CPU time 34.91 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 215840 kb
Host smart-b43dbc1e-20c7-4bbb-a75d-08e2788a7113
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3178796708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.3178796708
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.2956982129
Short name T722
Test name
Test status
Simulation time 241474712 ps
CPU time 1.03 seconds
Started Aug 02 05:33:27 PM PDT 24
Finished Aug 02 05:33:28 PM PDT 24
Peak memory 207392 kb
Host smart-3f9e5406-7221-41d3-ad39-9be96ca974ef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2956982129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.2956982129
Directory /workspace/37.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1930540968
Short name T1182
Test name
Test status
Simulation time 193618099 ps
CPU time 0.87 seconds
Started Aug 02 05:33:34 PM PDT 24
Finished Aug 02 05:33:35 PM PDT 24
Peak memory 207460 kb
Host smart-c885165a-e436-4b87-b370-506548f58ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19305
40968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1930540968
Directory /workspace/37.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.371722533
Short name T1716
Test name
Test status
Simulation time 2335432619 ps
CPU time 65.64 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 224112 kb
Host smart-280f443b-865f-489a-8a0c-9bddb811fbf8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=371722533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.371722533
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.163779782
Short name T494
Test name
Test status
Simulation time 151957599 ps
CPU time 0.89 seconds
Started Aug 02 05:33:11 PM PDT 24
Finished Aug 02 05:33:12 PM PDT 24
Peak memory 207408 kb
Host smart-de82f405-7760-4fae-8229-89d25373f0ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=163779782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.163779782
Directory /workspace/37.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3854074420
Short name T1626
Test name
Test status
Simulation time 141293348 ps
CPU time 0.84 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207424 kb
Host smart-80dd3cd8-9f89-49a5-8d25-f9ab1921b44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38540
74420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3854074420
Directory /workspace/37.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_nak_trans.502009989
Short name T3100
Test name
Test status
Simulation time 200990326 ps
CPU time 1.01 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207364 kb
Host smart-552fa357-26a9-4061-9fb9-45ad2eca77eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50200
9989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.502009989
Directory /workspace/37.usbdev_nak_trans/latest


Test location /workspace/coverage/default/37.usbdev_out_iso.598687432
Short name T129
Test name
Test status
Simulation time 183956526 ps
CPU time 0.86 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207360 kb
Host smart-2735c93f-ac16-42d9-95b9-c0c2ffb10d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59868
7432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.598687432
Directory /workspace/37.usbdev_out_iso/latest


Test location /workspace/coverage/default/37.usbdev_out_stall.543299869
Short name T514
Test name
Test status
Simulation time 183735083 ps
CPU time 0.89 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 207440 kb
Host smart-9f7605d4-f0e5-45e2-a3c5-27c09a4e4de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54329
9869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.543299869
Directory /workspace/37.usbdev_out_stall/latest


Test location /workspace/coverage/default/37.usbdev_out_trans_nak.3805100018
Short name T2043
Test name
Test status
Simulation time 176746523 ps
CPU time 0.88 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 207428 kb
Host smart-10ce6635-5fe8-45a9-b4e8-ff83f87a9539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38051
00018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.3805100018
Directory /workspace/37.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2048621712
Short name T1142
Test name
Test status
Simulation time 191086059 ps
CPU time 0.86 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207404 kb
Host smart-6d716259-401a-471e-a301-ebbc593b0e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486
21712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2048621712
Directory /workspace/37.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.2500110949
Short name T2632
Test name
Test status
Simulation time 191491941 ps
CPU time 0.91 seconds
Started Aug 02 05:33:24 PM PDT 24
Finished Aug 02 05:33:25 PM PDT 24
Peak memory 207380 kb
Host smart-c3bb859e-1bca-4606-bbff-78a467b09b9f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2500110949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.2500110949
Directory /workspace/37.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.996823863
Short name T2386
Test name
Test status
Simulation time 167431543 ps
CPU time 0.86 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207312 kb
Host smart-91ea74a6-0ba5-4172-bc29-0aa6c10bf8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99682
3863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.996823863
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.785166084
Short name T2401
Test name
Test status
Simulation time 117199016 ps
CPU time 0.75 seconds
Started Aug 02 05:33:28 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 207320 kb
Host smart-fa288bb1-5f87-43ac-b735-1d08c214373f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78516
6084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.785166084
Directory /workspace/37.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/37.usbdev_pkt_buffer.133638241
Short name T2167
Test name
Test status
Simulation time 23786491421 ps
CPU time 64.66 seconds
Started Aug 02 05:33:32 PM PDT 24
Finished Aug 02 05:34:37 PM PDT 24
Peak memory 224144 kb
Host smart-59dc21e3-bf3b-46a3-ba00-81ad2c18f533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
8241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.133638241
Directory /workspace/37.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/37.usbdev_pkt_received.2608270615
Short name T1544
Test name
Test status
Simulation time 181698059 ps
CPU time 0.93 seconds
Started Aug 02 05:33:09 PM PDT 24
Finished Aug 02 05:33:10 PM PDT 24
Peak memory 207364 kb
Host smart-19c786c9-ef8c-4811-b424-e317e704426d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26082
70615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2608270615
Directory /workspace/37.usbdev_pkt_received/latest


Test location /workspace/coverage/default/37.usbdev_pkt_sent.1106695358
Short name T1838
Test name
Test status
Simulation time 251517369 ps
CPU time 0.98 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 207364 kb
Host smart-c71930b1-25e4-42c5-90b1-8f4b2801690e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11066
95358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1106695358
Directory /workspace/37.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.749625062
Short name T1097
Test name
Test status
Simulation time 204146516 ps
CPU time 0.96 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207424 kb
Host smart-5ffef313-27ce-45b1-a33d-d2e0a0a47413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74962
5062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.749625062
Directory /workspace/37.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.2575600079
Short name T639
Test name
Test status
Simulation time 255136873 ps
CPU time 0.99 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207376 kb
Host smart-521478c0-6263-4c35-b8b5-0de2679dc36e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25756
00079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.2575600079
Directory /workspace/37.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/37.usbdev_rx_crc_err.870996259
Short name T1854
Test name
Test status
Simulation time 161899960 ps
CPU time 0.88 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207436 kb
Host smart-9c278eba-8bba-479f-b6bd-2e2c915ecd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87099
6259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.870996259
Directory /workspace/37.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/37.usbdev_rx_full.3027422835
Short name T2415
Test name
Test status
Simulation time 333586800 ps
CPU time 1.2 seconds
Started Aug 02 05:33:06 PM PDT 24
Finished Aug 02 05:33:07 PM PDT 24
Peak memory 207360 kb
Host smart-1d637bc5-2d4d-4c65-8016-e522fcc04152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30274
22835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_full.3027422835
Directory /workspace/37.usbdev_rx_full/latest


Test location /workspace/coverage/default/37.usbdev_setup_stage.3015084728
Short name T2417
Test name
Test status
Simulation time 158082113 ps
CPU time 0.8 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:33:24 PM PDT 24
Peak memory 207372 kb
Host smart-6f490127-c9cd-4956-82cc-7bbc63652850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30150
84728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3015084728
Directory /workspace/37.usbdev_setup_stage/latest


Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.115679570
Short name T2990
Test name
Test status
Simulation time 155260748 ps
CPU time 0.82 seconds
Started Aug 02 05:33:06 PM PDT 24
Finished Aug 02 05:33:07 PM PDT 24
Peak memory 207368 kb
Host smart-f01d4f7a-170f-4c14-915e-0652e7562b68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11567
9570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.115679570
Directory /workspace/37.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/37.usbdev_smoke.4079482384
Short name T724
Test name
Test status
Simulation time 260361470 ps
CPU time 1.12 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207420 kb
Host smart-181a7af2-5919-4fd0-8de8-00b4a70ad39a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40794
82384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.4079482384
Directory /workspace/37.usbdev_smoke/latest


Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.742019916
Short name T107
Test name
Test status
Simulation time 2858747036 ps
CPU time 22.66 seconds
Started Aug 02 05:33:27 PM PDT 24
Finished Aug 02 05:33:50 PM PDT 24
Peak memory 217860 kb
Host smart-8f09a9d4-1df8-4c18-9931-825dc8d8b75d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=742019916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.742019916
Directory /workspace/37.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2361337545
Short name T2379
Test name
Test status
Simulation time 167557998 ps
CPU time 0.86 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207400 kb
Host smart-6f8c5ae6-d82b-43ad-bb36-e78d1bab7598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23613
37545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2361337545
Directory /workspace/37.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/37.usbdev_stall_trans.292883044
Short name T2403
Test name
Test status
Simulation time 187722824 ps
CPU time 0.88 seconds
Started Aug 02 05:33:23 PM PDT 24
Finished Aug 02 05:33:24 PM PDT 24
Peak memory 207344 kb
Host smart-abcf7cf9-cb92-435e-8ac9-c4dd96d61518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29288
3044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.292883044
Directory /workspace/37.usbdev_stall_trans/latest


Test location /workspace/coverage/default/37.usbdev_stream_len_max.1811712121
Short name T1988
Test name
Test status
Simulation time 307718656 ps
CPU time 1.16 seconds
Started Aug 02 05:33:10 PM PDT 24
Finished Aug 02 05:33:11 PM PDT 24
Peak memory 207356 kb
Host smart-16a415a0-4a14-41fe-9ad9-2dadeb3afc02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18117
12121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.1811712121
Directory /workspace/37.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/37.usbdev_streaming_out.2352421785
Short name T522
Test name
Test status
Simulation time 4302675366 ps
CPU time 42.64 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:34:00 PM PDT 24
Peak memory 217520 kb
Host smart-7b2e869c-b1d4-42ee-8d56-f50766053625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23524
21785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2352421785
Directory /workspace/37.usbdev_streaming_out/latest


Test location /workspace/coverage/default/37.usbdev_timeout_missing_host_handshake.736105845
Short name T1049
Test name
Test status
Simulation time 3393336287 ps
CPU time 29.1 seconds
Started Aug 02 05:33:09 PM PDT 24
Finished Aug 02 05:33:38 PM PDT 24
Peak memory 207716 kb
Host smart-3381e1a0-5f7e-4052-9116-94e8ab468fb5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736105845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_timeout_missing_host
_handshake.736105845
Directory /workspace/37.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/38.usbdev_alert_test.3216043714
Short name T2252
Test name
Test status
Simulation time 62338926 ps
CPU time 0.73 seconds
Started Aug 02 05:33:24 PM PDT 24
Finished Aug 02 05:33:25 PM PDT 24
Peak memory 207452 kb
Host smart-de4d0c78-3dbf-4217-8515-48ccd8a2f9d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3216043714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.3216043714
Directory /workspace/38.usbdev_alert_test/latest


Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.2087705629
Short name T1035
Test name
Test status
Simulation time 6137471145 ps
CPU time 8.19 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:24 PM PDT 24
Peak memory 215816 kb
Host smart-80bfd2f9-e0cb-458c-9034-54cd3bb41343
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087705629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_a
on_wake_disconnect.2087705629
Directory /workspace/38.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1730214159
Short name T117
Test name
Test status
Simulation time 14826860562 ps
CPU time 16.57 seconds
Started Aug 02 05:33:11 PM PDT 24
Finished Aug 02 05:33:28 PM PDT 24
Peak memory 215892 kb
Host smart-08552eba-af9f-49fb-901f-19eb8d38558b
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730214159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1730214159
Directory /workspace/38.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.101959567
Short name T2761
Test name
Test status
Simulation time 25352506608 ps
CPU time 29.09 seconds
Started Aug 02 05:33:23 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 215856 kb
Host smart-d4a8b6dc-f26f-432e-abea-74050be60a1b
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101959567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_ao
n_wake_resume.101959567
Directory /workspace/38.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/38.usbdev_av_buffer.3230024431
Short name T1927
Test name
Test status
Simulation time 155205923 ps
CPU time 0.85 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207380 kb
Host smart-d88dc234-b78f-4683-94ea-5cdadc760b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32300
24431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.3230024431
Directory /workspace/38.usbdev_av_buffer/latest


Test location /workspace/coverage/default/38.usbdev_bitstuff_err.90290193
Short name T1964
Test name
Test status
Simulation time 155057245 ps
CPU time 0.82 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207368 kb
Host smart-d2e2d0b8-12d3-4eba-bc29-401aebe3f62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90290
193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.90290193
Directory /workspace/38.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2620169008
Short name T1616
Test name
Test status
Simulation time 354951903 ps
CPU time 1.28 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207304 kb
Host smart-92e65059-89e4-409b-85b9-41b6d4955f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26201
69008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2620169008
Directory /workspace/38.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.4037683552
Short name T612
Test name
Test status
Simulation time 545067902 ps
CPU time 1.55 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207376 kb
Host smart-9d206c4d-fbb4-42e3-a614-6bb6527dd0fc
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=4037683552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.4037683552
Directory /workspace/38.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/38.usbdev_device_address.2636547314
Short name T173
Test name
Test status
Simulation time 18854559829 ps
CPU time 30.44 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:46 PM PDT 24
Peak memory 207720 kb
Host smart-11491d7a-a1d2-4864-9c28-8c7ed140ca8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26365
47314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.2636547314
Directory /workspace/38.usbdev_device_address/latest


Test location /workspace/coverage/default/38.usbdev_device_timeout.274080583
Short name T2333
Test name
Test status
Simulation time 3876909277 ps
CPU time 32.87 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 207640 kb
Host smart-e84d0655-fb0c-47c4-9c3a-1ffdfb6e7b01
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274080583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_timeout.274080583
Directory /workspace/38.usbdev_device_timeout/latest


Test location /workspace/coverage/default/38.usbdev_disable_endpoint.63232183
Short name T1148
Test name
Test status
Simulation time 566461533 ps
CPU time 1.64 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:15 PM PDT 24
Peak memory 207336 kb
Host smart-5788d686-719c-4dd5-8f70-9196391d7923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63232
183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.63232183
Directory /workspace/38.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/38.usbdev_disconnected.3222096792
Short name T939
Test name
Test status
Simulation time 145985947 ps
CPU time 0.9 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207344 kb
Host smart-d1cd4031-0691-4317-a2d2-2bc63d1df86c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32220
96792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3222096792
Directory /workspace/38.usbdev_disconnected/latest


Test location /workspace/coverage/default/38.usbdev_enable.1883677769
Short name T1698
Test name
Test status
Simulation time 64803386 ps
CPU time 0.69 seconds
Started Aug 02 05:33:14 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207388 kb
Host smart-8e997445-f4d0-4b6e-9fef-5dd093cc3dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18836
77769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.1883677769
Directory /workspace/38.usbdev_enable/latest


Test location /workspace/coverage/default/38.usbdev_endpoint_access.2198951748
Short name T1640
Test name
Test status
Simulation time 791170202 ps
CPU time 2.25 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207644 kb
Host smart-2a51c53e-87c0-4777-b09f-4fee66aa1742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21989
51748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2198951748
Directory /workspace/38.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/38.usbdev_endpoint_types.1653789153
Short name T2698
Test name
Test status
Simulation time 335952878 ps
CPU time 1.2 seconds
Started Aug 02 05:33:30 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 207364 kb
Host smart-297aaea9-7e02-4f8a-8ac5-656576f4bbea
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1653789153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_types.1653789153
Directory /workspace/38.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/38.usbdev_fifo_rst.3895316202
Short name T1216
Test name
Test status
Simulation time 285280145 ps
CPU time 1.99 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 207568 kb
Host smart-73aa8e53-d827-4ee1-92e3-64e9de6fa05a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38953
16202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.3895316202
Directory /workspace/38.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/38.usbdev_in_iso.2709649313
Short name T1762
Test name
Test status
Simulation time 236841560 ps
CPU time 1.21 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 215792 kb
Host smart-5e6dd2e7-98a0-41c4-a4e9-158345f5635b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2709649313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.2709649313
Directory /workspace/38.usbdev_in_iso/latest


Test location /workspace/coverage/default/38.usbdev_in_stall.3313758498
Short name T2216
Test name
Test status
Simulation time 139699669 ps
CPU time 0.84 seconds
Started Aug 02 05:33:28 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 207176 kb
Host smart-c70430a5-8fe6-4e79-8a4d-8dd2eec118da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33137
58498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3313758498
Directory /workspace/38.usbdev_in_stall/latest


Test location /workspace/coverage/default/38.usbdev_in_trans.560898884
Short name T3090
Test name
Test status
Simulation time 234743882 ps
CPU time 0.91 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207388 kb
Host smart-ace57338-52b8-455a-abb0-e30a62e4fc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56089
8884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.560898884
Directory /workspace/38.usbdev_in_trans/latest


Test location /workspace/coverage/default/38.usbdev_invalid_sync.4115648104
Short name T699
Test name
Test status
Simulation time 3947031987 ps
CPU time 113.32 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:35:08 PM PDT 24
Peak memory 217576 kb
Host smart-a54085d7-5a25-42de-9343-0f1532c870a2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4115648104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.4115648104
Directory /workspace/38.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/38.usbdev_iso_retraction.2313084356
Short name T997
Test name
Test status
Simulation time 12912424065 ps
CPU time 144.13 seconds
Started Aug 02 05:33:24 PM PDT 24
Finished Aug 02 05:35:48 PM PDT 24
Peak memory 207716 kb
Host smart-a9ea9e73-b01f-43a0-b49f-f75f8c7636cb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2313084356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.2313084356
Directory /workspace/38.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/38.usbdev_link_in_err.1438770621
Short name T2116
Test name
Test status
Simulation time 196582471 ps
CPU time 0.97 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207340 kb
Host smart-957ccc00-5e87-46ec-b4e1-6b8724d601bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14387
70621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1438770621
Directory /workspace/38.usbdev_link_in_err/latest


Test location /workspace/coverage/default/38.usbdev_link_resume.3787371251
Short name T2564
Test name
Test status
Simulation time 8690129452 ps
CPU time 11.95 seconds
Started Aug 02 05:33:06 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 215944 kb
Host smart-d14f4321-4e5e-441c-9d68-e54fd07658a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37873
71251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.3787371251
Directory /workspace/38.usbdev_link_resume/latest


Test location /workspace/coverage/default/38.usbdev_link_suspend.3214356860
Short name T1226
Test name
Test status
Simulation time 10535485423 ps
CPU time 14 seconds
Started Aug 02 05:33:21 PM PDT 24
Finished Aug 02 05:33:35 PM PDT 24
Peak memory 207696 kb
Host smart-a60da53c-81c5-40d8-983a-0cf265086913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32143
56860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3214356860
Directory /workspace/38.usbdev_link_suspend/latest


Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.3088373140
Short name T2833
Test name
Test status
Simulation time 2816460865 ps
CPU time 75.26 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:34:34 PM PDT 24
Peak memory 215896 kb
Host smart-22f069ed-de6a-4354-a736-c771a3a9f5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30883
73140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.3088373140
Directory /workspace/38.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.3324363327
Short name T2800
Test name
Test status
Simulation time 2245236934 ps
CPU time 16.16 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:28 PM PDT 24
Peak memory 215820 kb
Host smart-5b22c795-275b-453f-99ba-b2de460f2b00
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3324363327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.3324363327
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.2450069127
Short name T2327
Test name
Test status
Simulation time 239566479 ps
CPU time 0.92 seconds
Started Aug 02 05:33:12 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207340 kb
Host smart-bf0f3f4e-b3f5-48d5-9739-8520d62d12f0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2450069127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.2450069127
Directory /workspace/38.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1549165469
Short name T1575
Test name
Test status
Simulation time 197224888 ps
CPU time 0.94 seconds
Started Aug 02 05:33:24 PM PDT 24
Finished Aug 02 05:33:25 PM PDT 24
Peak memory 207368 kb
Host smart-d0fe1a09-b2cd-4aab-b1bf-a1683dee2a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15491
65469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1549165469
Directory /workspace/38.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2124093642
Short name T569
Test name
Test status
Simulation time 2301003679 ps
CPU time 21.29 seconds
Started Aug 02 05:33:27 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 223932 kb
Host smart-d6bd8406-aae5-45af-9926-08151054f894
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2124093642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2124093642
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.3546675959
Short name T1648
Test name
Test status
Simulation time 161311225 ps
CPU time 0.82 seconds
Started Aug 02 05:33:20 PM PDT 24
Finished Aug 02 05:33:21 PM PDT 24
Peak memory 207400 kb
Host smart-08393d5f-07e3-4143-9ea6-8b930c691c2e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3546675959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.3546675959
Directory /workspace/38.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3249333531
Short name T2609
Test name
Test status
Simulation time 148013284 ps
CPU time 0.82 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207432 kb
Host smart-1bfd802e-dc96-42c1-81e6-3bea716d9c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32493
33531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3249333531
Directory /workspace/38.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_nak_trans.4154874281
Short name T3006
Test name
Test status
Simulation time 216425430 ps
CPU time 0.98 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 207408 kb
Host smart-cf6a29a3-9792-45a4-a760-6b22761de586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41548
74281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.4154874281
Directory /workspace/38.usbdev_nak_trans/latest


Test location /workspace/coverage/default/38.usbdev_out_iso.367896891
Short name T1672
Test name
Test status
Simulation time 172005449 ps
CPU time 0.87 seconds
Started Aug 02 05:33:30 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 207376 kb
Host smart-0156963f-5653-48b8-bb9e-fe0c5300890f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36789
6891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.367896891
Directory /workspace/38.usbdev_out_iso/latest


Test location /workspace/coverage/default/38.usbdev_out_stall.1319010625
Short name T530
Test name
Test status
Simulation time 147092572 ps
CPU time 0.82 seconds
Started Aug 02 05:33:30 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 207400 kb
Host smart-366dafe7-7d26-48c0-9cb6-a7132d571ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13190
10625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.1319010625
Directory /workspace/38.usbdev_out_stall/latest


Test location /workspace/coverage/default/38.usbdev_out_trans_nak.1926041926
Short name T1123
Test name
Test status
Simulation time 266362037 ps
CPU time 1 seconds
Started Aug 02 05:33:31 PM PDT 24
Finished Aug 02 05:33:32 PM PDT 24
Peak memory 207392 kb
Host smart-9391810f-c63a-4173-ab75-17c91af854b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19260
41926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.1926041926
Directory /workspace/38.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/38.usbdev_pending_in_trans.2002539951
Short name T2219
Test name
Test status
Simulation time 153605354 ps
CPU time 0.85 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207416 kb
Host smart-b6afac65-e8cd-4ff2-95ee-31c8541e2889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20025
39951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.2002539951
Directory /workspace/38.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.3202469441
Short name T1212
Test name
Test status
Simulation time 231418871 ps
CPU time 1.1 seconds
Started Aug 02 05:33:27 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 207340 kb
Host smart-25a79350-2c21-4787-81c8-5bc7a398c6a4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3202469441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.3202469441
Directory /workspace/38.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.404219386
Short name T1106
Test name
Test status
Simulation time 160514573 ps
CPU time 0.82 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207380 kb
Host smart-8b3dd268-85b5-4831-9e36-3cfe3c27f1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40421
9386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.404219386
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.745165758
Short name T38
Test name
Test status
Simulation time 104565644 ps
CPU time 0.73 seconds
Started Aug 02 05:33:14 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207352 kb
Host smart-5a0a8b72-ed97-4271-b8b5-bd3925879599
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74516
5758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.745165758
Directory /workspace/38.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/38.usbdev_pkt_buffer.238592045
Short name T1422
Test name
Test status
Simulation time 12493516283 ps
CPU time 28.39 seconds
Started Aug 02 05:33:27 PM PDT 24
Finished Aug 02 05:33:55 PM PDT 24
Peak memory 215972 kb
Host smart-dfedd11a-8b0f-4d7f-a817-48021570ba39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23859
2045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.238592045
Directory /workspace/38.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/38.usbdev_pkt_received.3017317143
Short name T2511
Test name
Test status
Simulation time 184738558 ps
CPU time 0.93 seconds
Started Aug 02 05:33:11 PM PDT 24
Finished Aug 02 05:33:13 PM PDT 24
Peak memory 207324 kb
Host smart-fe76fe35-a9fe-454c-85d1-33ed674e8224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173
17143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3017317143
Directory /workspace/38.usbdev_pkt_received/latest


Test location /workspace/coverage/default/38.usbdev_pkt_sent.3014754068
Short name T2520
Test name
Test status
Simulation time 170420812 ps
CPU time 0.88 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 207348 kb
Host smart-e446ee62-83c0-47fe-b2ed-37a17ee38089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30147
54068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3014754068
Directory /workspace/38.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.562930519
Short name T1775
Test name
Test status
Simulation time 220005410 ps
CPU time 1.02 seconds
Started Aug 02 05:33:30 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 207388 kb
Host smart-5fc192c1-0f11-477c-9a29-f5c7d338bbc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56293
0519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.562930519
Directory /workspace/38.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.1464820821
Short name T505
Test name
Test status
Simulation time 162541477 ps
CPU time 0.83 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207356 kb
Host smart-af6e4d47-fc7e-4851-a1a1-df2cccf4e7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14648
20821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.1464820821
Directory /workspace/38.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/38.usbdev_rx_crc_err.965548748
Short name T1798
Test name
Test status
Simulation time 196740256 ps
CPU time 0.9 seconds
Started Aug 02 05:33:14 PM PDT 24
Finished Aug 02 05:33:15 PM PDT 24
Peak memory 207400 kb
Host smart-90e300af-7489-4fbc-9eea-d3a66c38eeb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96554
8748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.965548748
Directory /workspace/38.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/38.usbdev_rx_full.3768506422
Short name T2981
Test name
Test status
Simulation time 237359351 ps
CPU time 1.02 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 207376 kb
Host smart-3ade09bc-c59e-4fee-a372-40067eeb82fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37685
06422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_full.3768506422
Directory /workspace/38.usbdev_rx_full/latest


Test location /workspace/coverage/default/38.usbdev_setup_stage.437423590
Short name T527
Test name
Test status
Simulation time 194788150 ps
CPU time 0.88 seconds
Started Aug 02 05:33:20 PM PDT 24
Finished Aug 02 05:33:21 PM PDT 24
Peak memory 207388 kb
Host smart-62a4bb04-36de-42d0-8993-3ba964a8a6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43742
3590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.437423590
Directory /workspace/38.usbdev_setup_stage/latest


Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1005309417
Short name T1636
Test name
Test status
Simulation time 145002841 ps
CPU time 0.84 seconds
Started Aug 02 05:33:09 PM PDT 24
Finished Aug 02 05:33:10 PM PDT 24
Peak memory 207408 kb
Host smart-c5d9e5ec-af83-4fff-9c10-d347824da52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10053
09417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1005309417
Directory /workspace/38.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/38.usbdev_smoke.3408727449
Short name T1056
Test name
Test status
Simulation time 244800907 ps
CPU time 0.97 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 207404 kb
Host smart-baef02c6-0454-444d-bce4-6f739e70523d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
27449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3408727449
Directory /workspace/38.usbdev_smoke/latest


Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.1683484210
Short name T1671
Test name
Test status
Simulation time 3164738233 ps
CPU time 87.46 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:34:45 PM PDT 24
Peak memory 217568 kb
Host smart-b4a381bb-dce6-4186-96d1-c38ec38366ef
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1683484210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.1683484210
Directory /workspace/38.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.1051650002
Short name T2176
Test name
Test status
Simulation time 189236593 ps
CPU time 0.88 seconds
Started Aug 02 05:33:11 PM PDT 24
Finished Aug 02 05:33:12 PM PDT 24
Peak memory 207388 kb
Host smart-0dd3df78-a2ce-4ebb-9e6c-ca6f9d6d89f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10516
50002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.1051650002
Directory /workspace/38.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/38.usbdev_stall_trans.3600801303
Short name T564
Test name
Test status
Simulation time 250524159 ps
CPU time 0.97 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 207444 kb
Host smart-733713d3-2582-4e64-8526-f290159a15dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36008
01303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.3600801303
Directory /workspace/38.usbdev_stall_trans/latest


Test location /workspace/coverage/default/38.usbdev_stream_len_max.876045613
Short name T1502
Test name
Test status
Simulation time 562789445 ps
CPU time 1.65 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 207376 kb
Host smart-c2f1479e-f494-42cb-9ae5-3dd1a1a8f255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87604
5613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.876045613
Directory /workspace/38.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/38.usbdev_streaming_out.2398182660
Short name T862
Test name
Test status
Simulation time 2175036079 ps
CPU time 16.04 seconds
Started Aug 02 05:33:20 PM PDT 24
Finished Aug 02 05:33:36 PM PDT 24
Peak memory 217172 kb
Host smart-269c95ad-f2cb-4c19-aa2b-818df87b5383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23981
82660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2398182660
Directory /workspace/38.usbdev_streaming_out/latest


Test location /workspace/coverage/default/38.usbdev_timeout_missing_host_handshake.529054858
Short name T1740
Test name
Test status
Simulation time 4387004163 ps
CPU time 38.89 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:56 PM PDT 24
Peak memory 207704 kb
Host smart-f8add6ec-07d9-44b5-8359-3b22a72418c6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529054858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_timeout_missing_host
_handshake.529054858
Directory /workspace/38.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/39.usbdev_alert_test.3918751916
Short name T1458
Test name
Test status
Simulation time 51950505 ps
CPU time 0.69 seconds
Started Aug 02 05:33:40 PM PDT 24
Finished Aug 02 05:33:41 PM PDT 24
Peak memory 207488 kb
Host smart-16695bd8-c6a0-4fd3-bc22-8dd1b8db4f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3918751916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.3918751916
Directory /workspace/39.usbdev_alert_test/latest


Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.595429462
Short name T2758
Test name
Test status
Simulation time 5757031839 ps
CPU time 7.4 seconds
Started Aug 02 05:33:37 PM PDT 24
Finished Aug 02 05:33:45 PM PDT 24
Peak memory 215860 kb
Host smart-b09fc8e6-9f3d-4648-8618-6cfb5f563a5b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595429462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ao
n_wake_disconnect.595429462
Directory /workspace/39.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.1085143587
Short name T1845
Test name
Test status
Simulation time 18630280296 ps
CPU time 21.1 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:40 PM PDT 24
Peak memory 207628 kb
Host smart-7eeb6d54-41b6-4642-b8d7-7d027bf04578
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085143587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.1085143587
Directory /workspace/39.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.941046589
Short name T9
Test name
Test status
Simulation time 30741594326 ps
CPU time 37.16 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:50 PM PDT 24
Peak memory 207692 kb
Host smart-03ed9a56-7c68-453c-baea-9e665047f2dc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941046589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_ao
n_wake_resume.941046589
Directory /workspace/39.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/39.usbdev_av_buffer.1930753524
Short name T2497
Test name
Test status
Simulation time 178562830 ps
CPU time 0.91 seconds
Started Aug 02 05:33:14 PM PDT 24
Finished Aug 02 05:33:15 PM PDT 24
Peak memory 207372 kb
Host smart-17ab184b-97a5-40bc-a195-50109ee0a174
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19307
53524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1930753524
Directory /workspace/39.usbdev_av_buffer/latest


Test location /workspace/coverage/default/39.usbdev_bitstuff_err.3337595271
Short name T2013
Test name
Test status
Simulation time 147052738 ps
CPU time 0.84 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:15 PM PDT 24
Peak memory 207360 kb
Host smart-c3f2be42-1141-4921-8f6d-1bfa72d796b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33375
95271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.3337595271
Directory /workspace/39.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1686378044
Short name T2410
Test name
Test status
Simulation time 377477514 ps
CPU time 1.34 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:21 PM PDT 24
Peak memory 207392 kb
Host smart-78152e1a-7617-4fb2-93cc-83c9cd3e62fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16863
78044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1686378044
Directory /workspace/39.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1287061214
Short name T2741
Test name
Test status
Simulation time 999771727 ps
CPU time 2.4 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207528 kb
Host smart-57813cb2-395f-46ab-a178-df4bae1cff56
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1287061214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1287061214
Directory /workspace/39.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/39.usbdev_device_address.2024780379
Short name T344
Test name
Test status
Simulation time 31358065061 ps
CPU time 58.34 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 207676 kb
Host smart-0cc1dee1-5df7-45a0-be7c-fba2c01509cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20247
80379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2024780379
Directory /workspace/39.usbdev_device_address/latest


Test location /workspace/coverage/default/39.usbdev_device_timeout.3004000865
Short name T1974
Test name
Test status
Simulation time 2938550869 ps
CPU time 25.67 seconds
Started Aug 02 05:33:37 PM PDT 24
Finished Aug 02 05:34:03 PM PDT 24
Peak memory 207648 kb
Host smart-3b47c7b9-cbac-4399-8ed5-dc2aa06a7da2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004000865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_timeout.3004000865
Directory /workspace/39.usbdev_device_timeout/latest


Test location /workspace/coverage/default/39.usbdev_disable_endpoint.2699516857
Short name T770
Test name
Test status
Simulation time 1182836319 ps
CPU time 2.46 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:21 PM PDT 24
Peak memory 207300 kb
Host smart-e1a0d787-0b8b-427d-bce0-c95130006872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26995
16857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.2699516857
Directory /workspace/39.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/39.usbdev_disconnected.1265963643
Short name T1999
Test name
Test status
Simulation time 151481304 ps
CPU time 0.82 seconds
Started Aug 02 05:33:27 PM PDT 24
Finished Aug 02 05:33:28 PM PDT 24
Peak memory 207292 kb
Host smart-78e6d377-5128-4551-835e-341cac9a7e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12659
63643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1265963643
Directory /workspace/39.usbdev_disconnected/latest


Test location /workspace/coverage/default/39.usbdev_enable.1468215311
Short name T2718
Test name
Test status
Simulation time 86272242 ps
CPU time 0.74 seconds
Started Aug 02 05:33:34 PM PDT 24
Finished Aug 02 05:33:35 PM PDT 24
Peak memory 207324 kb
Host smart-ee28433f-c6b3-4802-bbd6-6f41814687b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14682
15311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.1468215311
Directory /workspace/39.usbdev_enable/latest


Test location /workspace/coverage/default/39.usbdev_endpoint_access.3494894450
Short name T2606
Test name
Test status
Simulation time 904229459 ps
CPU time 2.57 seconds
Started Aug 02 05:33:44 PM PDT 24
Finished Aug 02 05:33:46 PM PDT 24
Peak memory 207568 kb
Host smart-502d1dbd-b789-4c88-bdaa-a2223357558d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34948
94450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.3494894450
Directory /workspace/39.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/39.usbdev_endpoint_types.3161171874
Short name T375
Test name
Test status
Simulation time 544411837 ps
CPU time 1.33 seconds
Started Aug 02 05:33:20 PM PDT 24
Finished Aug 02 05:33:21 PM PDT 24
Peak memory 207404 kb
Host smart-97d46092-5a46-47f9-9d37-356bfe34cda9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3161171874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_types.3161171874
Directory /workspace/39.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/39.usbdev_fifo_rst.3423553730
Short name T2040
Test name
Test status
Simulation time 261134450 ps
CPU time 1.71 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207548 kb
Host smart-9dc29c2d-a716-4e34-93cb-42bc5009035e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
53730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3423553730
Directory /workspace/39.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/39.usbdev_in_iso.1772364705
Short name T947
Test name
Test status
Simulation time 192822735 ps
CPU time 0.92 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 207388 kb
Host smart-98da4f51-7319-4caf-8b30-b5b1cfd3d4a7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1772364705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1772364705
Directory /workspace/39.usbdev_in_iso/latest


Test location /workspace/coverage/default/39.usbdev_in_stall.158754570
Short name T496
Test name
Test status
Simulation time 147229615 ps
CPU time 0.8 seconds
Started Aug 02 05:33:39 PM PDT 24
Finished Aug 02 05:33:40 PM PDT 24
Peak memory 207412 kb
Host smart-b7856793-85f2-47e8-ba0a-71aef8e8c0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15875
4570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.158754570
Directory /workspace/39.usbdev_in_stall/latest


Test location /workspace/coverage/default/39.usbdev_in_trans.1840188827
Short name T2487
Test name
Test status
Simulation time 181848023 ps
CPU time 0.88 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207424 kb
Host smart-0e26b1e8-a034-4087-a235-f31f8bbe1379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18401
88827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.1840188827
Directory /workspace/39.usbdev_in_trans/latest


Test location /workspace/coverage/default/39.usbdev_invalid_sync.1742213498
Short name T849
Test name
Test status
Simulation time 5225457089 ps
CPU time 49.94 seconds
Started Aug 02 05:33:21 PM PDT 24
Finished Aug 02 05:34:11 PM PDT 24
Peak memory 218388 kb
Host smart-c23134fc-6858-4d45-9b77-875f66ad406b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1742213498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.1742213498
Directory /workspace/39.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/39.usbdev_iso_retraction.3913866970
Short name T676
Test name
Test status
Simulation time 8941847568 ps
CPU time 61.13 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:34:14 PM PDT 24
Peak memory 207632 kb
Host smart-f19541c1-0bf6-4d59-ae5d-0c89fda9a0e5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3913866970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.3913866970
Directory /workspace/39.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/39.usbdev_link_in_err.2152124912
Short name T2051
Test name
Test status
Simulation time 236170502 ps
CPU time 1.04 seconds
Started Aug 02 05:33:36 PM PDT 24
Finished Aug 02 05:33:37 PM PDT 24
Peak memory 207376 kb
Host smart-d2b45af0-2910-4e3b-a902-4ea976e175f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21521
24912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2152124912
Directory /workspace/39.usbdev_link_in_err/latest


Test location /workspace/coverage/default/39.usbdev_link_resume.1799505752
Short name T1143
Test name
Test status
Simulation time 12563370555 ps
CPU time 17.04 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:33 PM PDT 24
Peak memory 207672 kb
Host smart-3f76cf31-6bdc-41b5-945b-c2777e8e53e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17995
05752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1799505752
Directory /workspace/39.usbdev_link_resume/latest


Test location /workspace/coverage/default/39.usbdev_link_suspend.3091034978
Short name T1020
Test name
Test status
Simulation time 9391244393 ps
CPU time 11.55 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 207692 kb
Host smart-bafaaa8f-e4e8-44cd-959c-1e0eb7316956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30910
34978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3091034978
Directory /workspace/39.usbdev_link_suspend/latest


Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2884010929
Short name T2129
Test name
Test status
Simulation time 4621234864 ps
CPU time 131.76 seconds
Started Aug 02 05:33:26 PM PDT 24
Finished Aug 02 05:35:38 PM PDT 24
Peak memory 218424 kb
Host smart-b537b430-1a88-4920-aef7-0f93c5ddfe0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28840
10929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2884010929
Directory /workspace/39.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3914341112
Short name T2809
Test name
Test status
Simulation time 2876644748 ps
CPU time 83.41 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 217168 kb
Host smart-5642e47b-1121-4d9f-8c47-7ffd21ff6837
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3914341112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3914341112
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.1849572325
Short name T635
Test name
Test status
Simulation time 230759108 ps
CPU time 1.02 seconds
Started Aug 02 05:33:30 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 207392 kb
Host smart-8c8b2a71-2c75-4640-b345-a2bb8802bf09
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1849572325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.1849572325
Directory /workspace/39.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3346810474
Short name T585
Test name
Test status
Simulation time 211096142 ps
CPU time 0.99 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207404 kb
Host smart-b449bb75-065f-446e-b63f-1ddc13775f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33468
10474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3346810474
Directory /workspace/39.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.114106127
Short name T3025
Test name
Test status
Simulation time 1606476497 ps
CPU time 11.73 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:28 PM PDT 24
Peak memory 223948 kb
Host smart-5ce8fcdc-9628-45f3-9664-999475c18194
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=114106127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.114106127
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.1739250398
Short name T2016
Test name
Test status
Simulation time 204224111 ps
CPU time 0.91 seconds
Started Aug 02 05:33:29 PM PDT 24
Finished Aug 02 05:33:30 PM PDT 24
Peak memory 207392 kb
Host smart-0fddb4da-4380-411b-84fd-f96fa5cbdcda
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1739250398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.1739250398
Directory /workspace/39.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.3645055866
Short name T2595
Test name
Test status
Simulation time 144364253 ps
CPU time 0.8 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 207360 kb
Host smart-902dc4cb-e291-4920-afe2-907da2b90c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36450
55866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.3645055866
Directory /workspace/39.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_nak_trans.3906347119
Short name T2366
Test name
Test status
Simulation time 221506636 ps
CPU time 0.96 seconds
Started Aug 02 05:33:34 PM PDT 24
Finished Aug 02 05:33:36 PM PDT 24
Peak memory 207388 kb
Host smart-13b779f3-418a-4b75-a10d-723943d69ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39063
47119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3906347119
Directory /workspace/39.usbdev_nak_trans/latest


Test location /workspace/coverage/default/39.usbdev_out_iso.804836509
Short name T539
Test name
Test status
Simulation time 153436594 ps
CPU time 0.85 seconds
Started Aug 02 05:33:52 PM PDT 24
Finished Aug 02 05:33:53 PM PDT 24
Peak memory 207344 kb
Host smart-ec95e03d-11b6-43e7-8139-bbe4f0ed2b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80483
6509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.804836509
Directory /workspace/39.usbdev_out_iso/latest


Test location /workspace/coverage/default/39.usbdev_out_stall.3241663154
Short name T1250
Test name
Test status
Simulation time 178306924 ps
CPU time 0.91 seconds
Started Aug 02 05:33:26 PM PDT 24
Finished Aug 02 05:33:26 PM PDT 24
Peak memory 207416 kb
Host smart-572adc12-3a65-489a-96d3-bccc0d793590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32416
63154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.3241663154
Directory /workspace/39.usbdev_out_stall/latest


Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2968203450
Short name T1170
Test name
Test status
Simulation time 190331469 ps
CPU time 0.9 seconds
Started Aug 02 05:33:13 PM PDT 24
Finished Aug 02 05:33:14 PM PDT 24
Peak memory 207404 kb
Host smart-b8e9935a-ae7b-4c2f-a34f-a16ca09cbaa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29682
03450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2968203450
Directory /workspace/39.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1321873566
Short name T2533
Test name
Test status
Simulation time 219785171 ps
CPU time 0.95 seconds
Started Aug 02 05:33:15 PM PDT 24
Finished Aug 02 05:33:16 PM PDT 24
Peak memory 207392 kb
Host smart-26337923-bee2-4ce0-b392-b767ab99993c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13218
73566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1321873566
Directory /workspace/39.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3847348012
Short name T1548
Test name
Test status
Simulation time 279922108 ps
CPU time 1.1 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:17 PM PDT 24
Peak memory 207448 kb
Host smart-8c441440-a3c5-4c53-a046-ab6328887ac6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3847348012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3847348012
Directory /workspace/39.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2687841455
Short name T3095
Test name
Test status
Simulation time 146009020 ps
CPU time 0.78 seconds
Started Aug 02 05:33:28 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 207412 kb
Host smart-00901278-ed3c-4dea-b77c-9344d683eb9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26878
41455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2687841455
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1614989217
Short name T1886
Test name
Test status
Simulation time 48163674 ps
CPU time 0.69 seconds
Started Aug 02 05:33:28 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 207400 kb
Host smart-7f614674-4103-438b-858a-0719f67c7854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16149
89217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1614989217
Directory /workspace/39.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3826552218
Short name T2807
Test name
Test status
Simulation time 17739089790 ps
CPU time 46.74 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:34:03 PM PDT 24
Peak memory 215884 kb
Host smart-aeb71e94-18ab-4475-b00d-cea1c3a50c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38265
52218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3826552218
Directory /workspace/39.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/39.usbdev_pkt_received.2729546052
Short name T2353
Test name
Test status
Simulation time 201262020 ps
CPU time 0.97 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207316 kb
Host smart-8b8d973d-3ac6-4be7-b24e-0e9b2d835591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27295
46052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2729546052
Directory /workspace/39.usbdev_pkt_received/latest


Test location /workspace/coverage/default/39.usbdev_pkt_sent.1576047672
Short name T1177
Test name
Test status
Simulation time 216118088 ps
CPU time 0.96 seconds
Started Aug 02 05:33:32 PM PDT 24
Finished Aug 02 05:33:33 PM PDT 24
Peak memory 207384 kb
Host smart-98b3e65e-746c-4b3d-b28c-251899311ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15760
47672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1576047672
Directory /workspace/39.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3351534172
Short name T229
Test name
Test status
Simulation time 246750156 ps
CPU time 1 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207324 kb
Host smart-d0467abc-70ea-4cad-bea7-b0c76c2d4f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33515
34172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3351534172
Directory /workspace/39.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.3274926222
Short name T1871
Test name
Test status
Simulation time 180881357 ps
CPU time 0.94 seconds
Started Aug 02 05:33:16 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 207432 kb
Host smart-f02c4e35-6a47-421c-9467-480262d35f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32749
26222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.3274926222
Directory /workspace/39.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/39.usbdev_rx_crc_err.2861662712
Short name T721
Test name
Test status
Simulation time 169199868 ps
CPU time 0.87 seconds
Started Aug 02 05:33:21 PM PDT 24
Finished Aug 02 05:33:22 PM PDT 24
Peak memory 207408 kb
Host smart-d6651b14-152e-424e-b922-bf39e117573f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28616
62712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.2861662712
Directory /workspace/39.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/39.usbdev_rx_full.2496424557
Short name T666
Test name
Test status
Simulation time 386746985 ps
CPU time 1.23 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:33:19 PM PDT 24
Peak memory 207332 kb
Host smart-dd88329a-4d39-4c69-8d86-8e5a8a0a2f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24964
24557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_full.2496424557
Directory /workspace/39.usbdev_rx_full/latest


Test location /workspace/coverage/default/39.usbdev_setup_stage.1983306823
Short name T1197
Test name
Test status
Simulation time 168720367 ps
CPU time 0.82 seconds
Started Aug 02 05:33:17 PM PDT 24
Finished Aug 02 05:33:18 PM PDT 24
Peak memory 207392 kb
Host smart-7f1c06ad-27c2-49d1-8f09-060d5f692c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
06823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1983306823
Directory /workspace/39.usbdev_setup_stage/latest


Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.585624343
Short name T2680
Test name
Test status
Simulation time 159708984 ps
CPU time 0.83 seconds
Started Aug 02 05:33:38 PM PDT 24
Finished Aug 02 05:33:39 PM PDT 24
Peak memory 207424 kb
Host smart-f9154f69-3887-41ab-bc7e-1198f927775e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58562
4343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.585624343
Directory /workspace/39.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/39.usbdev_smoke.1413868131
Short name T1567
Test name
Test status
Simulation time 208174044 ps
CPU time 1.05 seconds
Started Aug 02 05:33:37 PM PDT 24
Finished Aug 02 05:33:38 PM PDT 24
Peak memory 207392 kb
Host smart-6d3304cb-76ad-4d56-b203-be72151a766d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14138
68131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1413868131
Directory /workspace/39.usbdev_smoke/latest


Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.592649412
Short name T2683
Test name
Test status
Simulation time 3273732705 ps
CPU time 33.62 seconds
Started Aug 02 05:33:35 PM PDT 24
Finished Aug 02 05:34:09 PM PDT 24
Peak memory 224032 kb
Host smart-962732a8-3d1c-4a8a-b598-eba21d4ecf2f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=592649412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.592649412
Directory /workspace/39.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.3414200067
Short name T502
Test name
Test status
Simulation time 169455321 ps
CPU time 0.87 seconds
Started Aug 02 05:33:45 PM PDT 24
Finished Aug 02 05:33:46 PM PDT 24
Peak memory 207408 kb
Host smart-0748fe57-a120-4a21-8712-32f35ea35455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34142
00067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.3414200067
Directory /workspace/39.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/39.usbdev_stall_trans.3988556962
Short name T1971
Test name
Test status
Simulation time 156240417 ps
CPU time 0.83 seconds
Started Aug 02 05:33:20 PM PDT 24
Finished Aug 02 05:33:21 PM PDT 24
Peak memory 207424 kb
Host smart-2ea5dec0-b148-4402-a60b-30052f0550b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39885
56962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.3988556962
Directory /workspace/39.usbdev_stall_trans/latest


Test location /workspace/coverage/default/39.usbdev_stream_len_max.1336825876
Short name T1624
Test name
Test status
Simulation time 903262237 ps
CPU time 2.52 seconds
Started Aug 02 05:33:20 PM PDT 24
Finished Aug 02 05:33:23 PM PDT 24
Peak memory 207536 kb
Host smart-7699e0c9-534e-4a27-ad19-e2636457bfa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13368
25876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1336825876
Directory /workspace/39.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/39.usbdev_streaming_out.1790661977
Short name T2152
Test name
Test status
Simulation time 2070086604 ps
CPU time 55.71 seconds
Started Aug 02 05:33:35 PM PDT 24
Finished Aug 02 05:34:31 PM PDT 24
Peak memory 217200 kb
Host smart-f37f3007-0a72-409f-8d4c-d8f6198ead45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17906
61977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1790661977
Directory /workspace/39.usbdev_streaming_out/latest


Test location /workspace/coverage/default/39.usbdev_timeout_missing_host_handshake.71995790
Short name T1735
Test name
Test status
Simulation time 2502241142 ps
CPU time 17.9 seconds
Started Aug 02 05:33:25 PM PDT 24
Finished Aug 02 05:33:43 PM PDT 24
Peak memory 207736 kb
Host smart-4bf9c8a3-393a-4bdf-9db8-4ff075979cd0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71995790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_timeout_missing_host_
handshake.71995790
Directory /workspace/39.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/4.usbdev_alert_test.3624038336
Short name T196
Test name
Test status
Simulation time 41137559 ps
CPU time 0.67 seconds
Started Aug 02 05:28:00 PM PDT 24
Finished Aug 02 05:28:01 PM PDT 24
Peak memory 207512 kb
Host smart-bbdde7d3-fd3a-4091-8eca-acec7d7bb203
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3624038336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3624038336
Directory /workspace/4.usbdev_alert_test/latest


Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.3969076180
Short name T1481
Test name
Test status
Simulation time 5244516519 ps
CPU time 6.64 seconds
Started Aug 02 05:27:44 PM PDT 24
Finished Aug 02 05:27:51 PM PDT 24
Peak memory 215792 kb
Host smart-d181dcac-b81d-4960-88e1-42d0fc3691c4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969076180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_disconnect.3969076180
Directory /workspace/4.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2746854614
Short name T621
Test name
Test status
Simulation time 20622693453 ps
CPU time 23.24 seconds
Started Aug 02 05:27:41 PM PDT 24
Finished Aug 02 05:28:04 PM PDT 24
Peak memory 207696 kb
Host smart-51936c68-ff9f-47b5-9863-548c5960f726
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746854614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2746854614
Directory /workspace/4.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2893004634
Short name T1880
Test name
Test status
Simulation time 23352876536 ps
CPU time 27.15 seconds
Started Aug 02 05:27:43 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 215844 kb
Host smart-cc42c58e-2d16-48fe-90e0-614eeb5edb33
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893004634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_ao
n_wake_resume.2893004634
Directory /workspace/4.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/4.usbdev_av_buffer.1304125036
Short name T1641
Test name
Test status
Simulation time 148550321 ps
CPU time 0.86 seconds
Started Aug 02 05:27:45 PM PDT 24
Finished Aug 02 05:27:46 PM PDT 24
Peak memory 207392 kb
Host smart-d4cdf944-b646-4d4b-ac6f-6dbfb40351ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13041
25036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1304125036
Directory /workspace/4.usbdev_av_buffer/latest


Test location /workspace/coverage/default/4.usbdev_av_empty.2095214429
Short name T46
Test name
Test status
Simulation time 195592372 ps
CPU time 0.92 seconds
Started Aug 02 05:27:44 PM PDT 24
Finished Aug 02 05:27:45 PM PDT 24
Peak memory 207360 kb
Host smart-0f93f01e-3710-4337-9aa7-97f3b7f25023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20952
14429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.2095214429
Directory /workspace/4.usbdev_av_empty/latest


Test location /workspace/coverage/default/4.usbdev_av_overflow.502611124
Short name T108
Test name
Test status
Simulation time 139410456 ps
CPU time 0.82 seconds
Started Aug 02 05:27:43 PM PDT 24
Finished Aug 02 05:27:44 PM PDT 24
Peak memory 207384 kb
Host smart-d5d54bd6-952a-4ab8-8ba0-89df16f5f520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50261
1124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.502611124
Directory /workspace/4.usbdev_av_overflow/latest


Test location /workspace/coverage/default/4.usbdev_bitstuff_err.2674715165
Short name T2722
Test name
Test status
Simulation time 216825607 ps
CPU time 0.88 seconds
Started Aug 02 05:27:46 PM PDT 24
Finished Aug 02 05:27:47 PM PDT 24
Peak memory 207340 kb
Host smart-f15c1b7d-3b18-427f-b594-d518197afb2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747
15165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.2674715165
Directory /workspace/4.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.3438856153
Short name T2436
Test name
Test status
Simulation time 402932469 ps
CPU time 1.5 seconds
Started Aug 02 05:27:42 PM PDT 24
Finished Aug 02 05:27:43 PM PDT 24
Peak memory 207384 kb
Host smart-f5a9e446-e7bb-4253-ad64-dd912f260157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34388
56153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.3438856153
Directory /workspace/4.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.653319558
Short name T1032
Test name
Test status
Simulation time 529010359 ps
CPU time 1.5 seconds
Started Aug 02 05:27:41 PM PDT 24
Finished Aug 02 05:27:43 PM PDT 24
Peak memory 207384 kb
Host smart-a663d708-c150-4d1f-8b8e-7ca2331580b7
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=653319558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.653319558
Directory /workspace/4.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/4.usbdev_device_address.1306133639
Short name T837
Test name
Test status
Simulation time 22059479466 ps
CPU time 30.99 seconds
Started Aug 02 05:27:50 PM PDT 24
Finished Aug 02 05:28:21 PM PDT 24
Peak memory 207700 kb
Host smart-2a5864f7-6661-4f70-b297-ec3eb2eee0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13061
33639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1306133639
Directory /workspace/4.usbdev_device_address/latest


Test location /workspace/coverage/default/4.usbdev_device_timeout.156699911
Short name T1984
Test name
Test status
Simulation time 2522136348 ps
CPU time 22.26 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:28:14 PM PDT 24
Peak memory 207696 kb
Host smart-2e6b679a-f62b-48f2-83c9-d6299d76a6b8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156699911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_timeout.156699911
Directory /workspace/4.usbdev_device_timeout/latest


Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1455504464
Short name T2559
Test name
Test status
Simulation time 1049280673 ps
CPU time 2.13 seconds
Started Aug 02 05:27:50 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 207340 kb
Host smart-7debd33b-64f2-4576-9aa2-99c03d8c7491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14555
04464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1455504464
Directory /workspace/4.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/4.usbdev_disconnected.3374949369
Short name T42
Test name
Test status
Simulation time 153308704 ps
CPU time 0.91 seconds
Started Aug 02 05:27:52 PM PDT 24
Finished Aug 02 05:27:53 PM PDT 24
Peak memory 207368 kb
Host smart-62911f02-aaf1-4b3a-b073-93de5804c370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33749
49369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3374949369
Directory /workspace/4.usbdev_disconnected/latest


Test location /workspace/coverage/default/4.usbdev_enable.3754290547
Short name T2264
Test name
Test status
Simulation time 43635139 ps
CPU time 0.69 seconds
Started Aug 02 05:27:54 PM PDT 24
Finished Aug 02 05:27:54 PM PDT 24
Peak memory 207368 kb
Host smart-37678028-3686-434a-85cc-83f9d54d6cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37542
90547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3754290547
Directory /workspace/4.usbdev_enable/latest


Test location /workspace/coverage/default/4.usbdev_endpoint_access.1065074432
Short name T351
Test name
Test status
Simulation time 845854763 ps
CPU time 2.24 seconds
Started Aug 02 05:27:52 PM PDT 24
Finished Aug 02 05:27:55 PM PDT 24
Peak memory 207580 kb
Host smart-06691078-be72-4367-8df3-0cf61c97baa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10650
74432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.1065074432
Directory /workspace/4.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/4.usbdev_fifo_rst.114626558
Short name T1606
Test name
Test status
Simulation time 220271581 ps
CPU time 1.96 seconds
Started Aug 02 05:27:49 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 207596 kb
Host smart-3fdacf69-c349-49a1-aa82-a136f13875e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11462
6558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.114626558
Directory /workspace/4.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/4.usbdev_freq_hiclk.180204183
Short name T1985
Test name
Test status
Simulation time 81175326591 ps
CPU time 142.5 seconds
Started Aug 02 05:27:50 PM PDT 24
Finished Aug 02 05:30:12 PM PDT 24
Peak memory 207692 kb
Host smart-65ceb1da-6f89-447f-a176-9ba022017705
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=180204183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.180204183
Directory /workspace/4.usbdev_freq_hiclk/latest


Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.4176857151
Short name T2759
Test name
Test status
Simulation time 84288863889 ps
CPU time 124.64 seconds
Started Aug 02 05:27:49 PM PDT 24
Finished Aug 02 05:29:54 PM PDT 24
Peak memory 207692 kb
Host smart-6d71ffb8-65f5-49d3-a5e2-8e15eea0a805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176857151 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.4176857151
Directory /workspace/4.usbdev_freq_hiclk_max/latest


Test location /workspace/coverage/default/4.usbdev_freq_loclk.712003194
Short name T1367
Test name
Test status
Simulation time 113104943498 ps
CPU time 196.51 seconds
Started Aug 02 05:27:53 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 207688 kb
Host smart-72bbb2dc-e04f-496a-aaf3-2cd7168e3fc3
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=712003194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.712003194
Directory /workspace/4.usbdev_freq_loclk/latest


Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1710158484
Short name T1706
Test name
Test status
Simulation time 100049404508 ps
CPU time 169.05 seconds
Started Aug 02 05:27:50 PM PDT 24
Finished Aug 02 05:30:39 PM PDT 24
Peak memory 207636 kb
Host smart-1ec838a3-ffb4-4037-95bf-3ef659682599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710158484 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1710158484
Directory /workspace/4.usbdev_freq_loclk_max/latest


Test location /workspace/coverage/default/4.usbdev_freq_phase.3458210569
Short name T1295
Test name
Test status
Simulation time 89154157685 ps
CPU time 153.09 seconds
Started Aug 02 05:27:48 PM PDT 24
Finished Aug 02 05:30:21 PM PDT 24
Peak memory 207724 kb
Host smart-fe84e6ac-c8bb-4646-a746-0431f402f51b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34582
10569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3458210569
Directory /workspace/4.usbdev_freq_phase/latest


Test location /workspace/coverage/default/4.usbdev_in_iso.1226547252
Short name T1501
Test name
Test status
Simulation time 258156900 ps
CPU time 1.27 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:27:53 PM PDT 24
Peak memory 215684 kb
Host smart-f74fdd2f-d782-46d5-91f2-aa5b2ef42cc1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1226547252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1226547252
Directory /workspace/4.usbdev_in_iso/latest


Test location /workspace/coverage/default/4.usbdev_in_stall.3374854563
Short name T3081
Test name
Test status
Simulation time 144398265 ps
CPU time 0.84 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 207344 kb
Host smart-5c403b24-08ab-4e55-b7af-aa35a1cc5dba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33748
54563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.3374854563
Directory /workspace/4.usbdev_in_stall/latest


Test location /workspace/coverage/default/4.usbdev_in_trans.1223920686
Short name T2878
Test name
Test status
Simulation time 197749066 ps
CPU time 0.93 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 207404 kb
Host smart-1c40f53a-89e6-4914-b2a7-a16864a25c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12239
20686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.1223920686
Directory /workspace/4.usbdev_in_trans/latest


Test location /workspace/coverage/default/4.usbdev_invalid_sync.3452241256
Short name T854
Test name
Test status
Simulation time 2774279297 ps
CPU time 78.44 seconds
Started Aug 02 05:27:54 PM PDT 24
Finished Aug 02 05:29:12 PM PDT 24
Peak memory 218204 kb
Host smart-722f3cbe-8f9a-439f-a193-24b1e9a33a02
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3452241256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.3452241256
Directory /workspace/4.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/4.usbdev_iso_retraction.4093380667
Short name T2659
Test name
Test status
Simulation time 12380299337 ps
CPU time 78.26 seconds
Started Aug 02 05:27:49 PM PDT 24
Finished Aug 02 05:29:08 PM PDT 24
Peak memory 207656 kb
Host smart-833feacc-cbd0-4e35-bcda-456b877db66c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4093380667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.4093380667
Directory /workspace/4.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/4.usbdev_link_in_err.1810633988
Short name T495
Test name
Test status
Simulation time 247924800 ps
CPU time 0.94 seconds
Started Aug 02 05:27:49 PM PDT 24
Finished Aug 02 05:27:50 PM PDT 24
Peak memory 207356 kb
Host smart-4424785f-e2e5-4bec-9cd6-a50be00f8a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18106
33988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1810633988
Directory /workspace/4.usbdev_link_in_err/latest


Test location /workspace/coverage/default/4.usbdev_link_resume.2390470346
Short name T2805
Test name
Test status
Simulation time 8337372865 ps
CPU time 11.67 seconds
Started Aug 02 05:27:50 PM PDT 24
Finished Aug 02 05:28:01 PM PDT 24
Peak memory 216036 kb
Host smart-4085db6d-bc41-4be0-ac5a-7db17253654d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23904
70346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.2390470346
Directory /workspace/4.usbdev_link_resume/latest


Test location /workspace/coverage/default/4.usbdev_link_suspend.1431880520
Short name T2778
Test name
Test status
Simulation time 3443130265 ps
CPU time 4.54 seconds
Started Aug 02 05:27:50 PM PDT 24
Finished Aug 02 05:27:55 PM PDT 24
Peak memory 216624 kb
Host smart-327a186b-6c9f-4d27-9f71-c7caf3204472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14318
80520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1431880520
Directory /workspace/4.usbdev_link_suspend/latest


Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3023263581
Short name T916
Test name
Test status
Simulation time 3741371329 ps
CPU time 26.01 seconds
Started Aug 02 05:27:50 PM PDT 24
Finished Aug 02 05:28:16 PM PDT 24
Peak memory 217580 kb
Host smart-4f0edea6-d59a-4622-b72a-04448acf7839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30232
63581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3023263581
Directory /workspace/4.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.271875268
Short name T1436
Test name
Test status
Simulation time 3334826483 ps
CPU time 93.14 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:29:24 PM PDT 24
Peak memory 217136 kb
Host smart-98f2e4d1-bd1e-43b1-a958-95486b5992e5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=271875268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.271875268
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.1520327301
Short name T1430
Test name
Test status
Simulation time 263186252 ps
CPU time 0.98 seconds
Started Aug 02 05:27:49 PM PDT 24
Finished Aug 02 05:27:50 PM PDT 24
Peak memory 207364 kb
Host smart-89ec6c3f-bcdd-4c6e-acc9-86aa49a06f52
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1520327301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.1520327301
Directory /workspace/4.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1103472417
Short name T921
Test name
Test status
Simulation time 195364826 ps
CPU time 1.04 seconds
Started Aug 02 05:27:52 PM PDT 24
Finished Aug 02 05:27:53 PM PDT 24
Peak memory 207324 kb
Host smart-04bab87d-7be2-41de-a637-2a4511c36028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11034
72417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1103472417
Directory /workspace/4.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_max_non_iso_usb_traffic.2048080009
Short name T776
Test name
Test status
Simulation time 2800993793 ps
CPU time 26.81 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:28:18 PM PDT 24
Peak memory 223996 kb
Host smart-7d820a8b-1232-4cfa-bf78-daf0a3e1fec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20480
80009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_non_iso_usb_traffic.2048080009
Directory /workspace/4.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.1774633908
Short name T1604
Test name
Test status
Simulation time 2332501308 ps
CPU time 66.62 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:28:58 PM PDT 24
Peak memory 215464 kb
Host smart-0cf4214a-c897-4281-af49-95dd0a676328
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1774633908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.1774633908
Directory /workspace/4.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.3652091380
Short name T2862
Test name
Test status
Simulation time 1646928510 ps
CPU time 44.29 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:28:35 PM PDT 24
Peak memory 215392 kb
Host smart-815ce140-8ab8-4b70-8c56-00d00cba32df
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3652091380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.3652091380
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1021707219
Short name T512
Test name
Test status
Simulation time 157149718 ps
CPU time 0.84 seconds
Started Aug 02 05:27:52 PM PDT 24
Finished Aug 02 05:27:53 PM PDT 24
Peak memory 207376 kb
Host smart-195e7e85-3ed0-4a41-b41b-b6f116a588d0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1021707219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1021707219
Directory /workspace/4.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.108556781
Short name T2121
Test name
Test status
Simulation time 160403058 ps
CPU time 0.86 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 207380 kb
Host smart-be2206c0-5de8-49e6-b15d-187462b6b246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10855
6781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.108556781
Directory /workspace/4.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_nak_trans.3648396968
Short name T141
Test name
Test status
Simulation time 205905333 ps
CPU time 0.93 seconds
Started Aug 02 05:27:48 PM PDT 24
Finished Aug 02 05:27:49 PM PDT 24
Peak memory 207384 kb
Host smart-cdd4296b-a53d-4108-96dc-75152c643406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36483
96968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3648396968
Directory /workspace/4.usbdev_nak_trans/latest


Test location /workspace/coverage/default/4.usbdev_out_iso.582633753
Short name T2035
Test name
Test status
Simulation time 207933138 ps
CPU time 0.89 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 207208 kb
Host smart-cb291b60-6984-4a1d-8dce-75cb70b33bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58263
3753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.582633753
Directory /workspace/4.usbdev_out_iso/latest


Test location /workspace/coverage/default/4.usbdev_out_stall.3626690738
Short name T2494
Test name
Test status
Simulation time 154408687 ps
CPU time 0.83 seconds
Started Aug 02 05:27:51 PM PDT 24
Finished Aug 02 05:27:52 PM PDT 24
Peak memory 207316 kb
Host smart-c55fa80f-1142-4eb7-87be-93ccecd5cdce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36266
90738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3626690738
Directory /workspace/4.usbdev_out_stall/latest


Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1425127171
Short name T611
Test name
Test status
Simulation time 202487286 ps
CPU time 0.96 seconds
Started Aug 02 05:27:50 PM PDT 24
Finished Aug 02 05:27:51 PM PDT 24
Peak memory 207348 kb
Host smart-e3a42cf2-4e41-4dc8-88d7-c0e777626bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14251
27171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1425127171
Directory /workspace/4.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2860055004
Short name T190
Test name
Test status
Simulation time 154410442 ps
CPU time 0.82 seconds
Started Aug 02 05:28:00 PM PDT 24
Finished Aug 02 05:28:00 PM PDT 24
Peak memory 207400 kb
Host smart-da73878f-88c2-4196-b821-800d4129371a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28600
55004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2860055004
Directory /workspace/4.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.4052633654
Short name T3029
Test name
Test status
Simulation time 223638551 ps
CPU time 1 seconds
Started Aug 02 05:28:00 PM PDT 24
Finished Aug 02 05:28:01 PM PDT 24
Peak memory 207408 kb
Host smart-d4f052e6-348d-4374-bf23-67fc28e65e41
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4052633654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.4052633654
Directory /workspace/4.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.4167369085
Short name T1771
Test name
Test status
Simulation time 222433211 ps
CPU time 1.04 seconds
Started Aug 02 05:27:58 PM PDT 24
Finished Aug 02 05:27:59 PM PDT 24
Peak memory 207332 kb
Host smart-e9c49fb3-7104-42b4-a9ea-8cddfa26968b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41673
69085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.4167369085
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest


Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.4143018568
Short name T2
Test name
Test status
Simulation time 151438041 ps
CPU time 0.85 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:28:02 PM PDT 24
Peak memory 207372 kb
Host smart-c199313f-ffa4-4476-aeb5-e4eb649c6f73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41430
18568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.4143018568
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.1944751781
Short name T771
Test name
Test status
Simulation time 36192836 ps
CPU time 0.68 seconds
Started Aug 02 05:28:03 PM PDT 24
Finished Aug 02 05:28:03 PM PDT 24
Peak memory 207296 kb
Host smart-bb97739b-1648-456d-b9ed-497111d3893e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19447
51781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.1944751781
Directory /workspace/4.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3654433276
Short name T1118
Test name
Test status
Simulation time 11305492534 ps
CPU time 27.9 seconds
Started Aug 02 05:28:00 PM PDT 24
Finished Aug 02 05:28:28 PM PDT 24
Peak memory 219960 kb
Host smart-10666ecf-c8b3-41ec-8359-2e217969b5a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544
33276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3654433276
Directory /workspace/4.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/4.usbdev_pkt_received.323100862
Short name T1473
Test name
Test status
Simulation time 184195673 ps
CPU time 0.94 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:28:02 PM PDT 24
Peak memory 207400 kb
Host smart-05ca9393-c6ac-44fc-b0e3-90876201e9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32310
0862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.323100862
Directory /workspace/4.usbdev_pkt_received/latest


Test location /workspace/coverage/default/4.usbdev_pkt_sent.220031572
Short name T900
Test name
Test status
Simulation time 237711147 ps
CPU time 0.96 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:28:03 PM PDT 24
Peak memory 207312 kb
Host smart-6867ba44-63a1-491d-b304-ee71ede7f301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
1572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.220031572
Directory /workspace/4.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1588031681
Short name T2017
Test name
Test status
Simulation time 6613768263 ps
CPU time 80.22 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:29:22 PM PDT 24
Peak memory 224084 kb
Host smart-7cb72f7c-b0c6-495f-ad69-20d31ce3a286
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588031681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1588031681
Directory /workspace/4.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.4138316602
Short name T1158
Test name
Test status
Simulation time 5280228399 ps
CPU time 23.53 seconds
Started Aug 02 05:28:05 PM PDT 24
Finished Aug 02 05:28:28 PM PDT 24
Peak memory 219232 kb
Host smart-0306b515-5c84-4807-8d61-53bf70f1f68a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4138316602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.4138316602
Directory /workspace/4.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/4.usbdev_rand_suspends.1570304440
Short name T1200
Test name
Test status
Simulation time 10084017178 ps
CPU time 180.74 seconds
Started Aug 02 05:28:00 PM PDT 24
Finished Aug 02 05:31:01 PM PDT 24
Peak memory 224020 kb
Host smart-00c6c156-f9b1-44c3-b52d-4274435b3a8a
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570304440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1570304440
Directory /workspace/4.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.672965203
Short name T1619
Test name
Test status
Simulation time 221576014 ps
CPU time 0.94 seconds
Started Aug 02 05:27:59 PM PDT 24
Finished Aug 02 05:28:00 PM PDT 24
Peak memory 207368 kb
Host smart-7f50b726-a0f9-4204-b116-4b2d75509b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67296
5203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.672965203
Directory /workspace/4.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1772451806
Short name T1107
Test name
Test status
Simulation time 146511404 ps
CPU time 0.86 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:28:02 PM PDT 24
Peak memory 207356 kb
Host smart-9be1e39f-49d7-48ed-b9b9-47bfd3b5f17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17724
51806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1772451806
Directory /workspace/4.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/4.usbdev_rx_crc_err.730109693
Short name T2591
Test name
Test status
Simulation time 188402514 ps
CPU time 0.91 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:28:02 PM PDT 24
Peak memory 207416 kb
Host smart-dfdffe0b-0a27-4199-a691-84ac45995119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73010
9693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.730109693
Directory /workspace/4.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/4.usbdev_rx_full.2797485999
Short name T1820
Test name
Test status
Simulation time 254229834 ps
CPU time 1.07 seconds
Started Aug 02 05:28:00 PM PDT 24
Finished Aug 02 05:28:01 PM PDT 24
Peak memory 207416 kb
Host smart-e6c52077-4864-469b-8ed4-9c97d9956afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27974
85999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_full.2797485999
Directory /workspace/4.usbdev_rx_full/latest


Test location /workspace/coverage/default/4.usbdev_rx_pid_err.1968507217
Short name T2172
Test name
Test status
Simulation time 191019039 ps
CPU time 0.89 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:28:03 PM PDT 24
Peak memory 207432 kb
Host smart-2ced058d-88cc-4b75-8f12-bdd621b10382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19685
07217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.1968507217
Directory /workspace/4.usbdev_rx_pid_err/latest


Test location /workspace/coverage/default/4.usbdev_setup_priority.1311442613
Short name T2579
Test name
Test status
Simulation time 446742230 ps
CPU time 1.45 seconds
Started Aug 02 05:27:59 PM PDT 24
Finished Aug 02 05:28:01 PM PDT 24
Peak memory 207396 kb
Host smart-c3832acd-e35e-4ba8-a2a0-fcd06b6d2f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13114
42613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.1311442613
Directory /workspace/4.usbdev_setup_priority/latest


Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2164468816
Short name T2079
Test name
Test status
Simulation time 308536756 ps
CPU time 1.04 seconds
Started Aug 02 05:28:00 PM PDT 24
Finished Aug 02 05:28:01 PM PDT 24
Peak memory 207444 kb
Host smart-f84d1a07-9761-4adc-b8af-407573d8e290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21644
68816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2164468816
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest


Test location /workspace/coverage/default/4.usbdev_setup_stage.639020234
Short name T1925
Test name
Test status
Simulation time 162497354 ps
CPU time 0.88 seconds
Started Aug 02 05:28:02 PM PDT 24
Finished Aug 02 05:28:03 PM PDT 24
Peak memory 207400 kb
Host smart-8489a95c-c5ad-4e44-8223-5601abb9b1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63902
0234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.639020234
Directory /workspace/4.usbdev_setup_stage/latest


Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.153855004
Short name T1074
Test name
Test status
Simulation time 152965060 ps
CPU time 0.85 seconds
Started Aug 02 05:28:02 PM PDT 24
Finished Aug 02 05:28:03 PM PDT 24
Peak memory 207404 kb
Host smart-297cdb81-1045-4ecf-9ad2-99026cc2bd6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15385
5004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.153855004
Directory /workspace/4.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/4.usbdev_smoke.1143435100
Short name T1933
Test name
Test status
Simulation time 232430338 ps
CPU time 1.04 seconds
Started Aug 02 05:28:02 PM PDT 24
Finished Aug 02 05:28:03 PM PDT 24
Peak memory 207396 kb
Host smart-df062404-30e2-410d-a0f3-8d6055eab332
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11434
35100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1143435100
Directory /workspace/4.usbdev_smoke/latest


Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3204798014
Short name T2583
Test name
Test status
Simulation time 1961555934 ps
CPU time 19.69 seconds
Started Aug 02 05:28:02 PM PDT 24
Finished Aug 02 05:28:22 PM PDT 24
Peak memory 217440 kb
Host smart-37cdac32-7df4-4deb-9081-8701c079ed3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3204798014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3204798014
Directory /workspace/4.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2861118878
Short name T1782
Test name
Test status
Simulation time 219900300 ps
CPU time 0.9 seconds
Started Aug 02 05:28:03 PM PDT 24
Finished Aug 02 05:28:04 PM PDT 24
Peak memory 207384 kb
Host smart-582135f5-2b8c-4e19-b629-669434a1b273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28611
18878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2861118878
Directory /workspace/4.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/4.usbdev_stall_trans.1265945849
Short name T879
Test name
Test status
Simulation time 159572151 ps
CPU time 0.84 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:28:02 PM PDT 24
Peak memory 207352 kb
Host smart-76b94dc2-bb02-4e26-82c9-ea492310f8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12659
45849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1265945849
Directory /workspace/4.usbdev_stall_trans/latest


Test location /workspace/coverage/default/4.usbdev_stream_len_max.4148397067
Short name T517
Test name
Test status
Simulation time 330853282 ps
CPU time 1.21 seconds
Started Aug 02 05:27:59 PM PDT 24
Finished Aug 02 05:28:00 PM PDT 24
Peak memory 207352 kb
Host smart-74f0e6ab-ab0a-42e1-8792-1c55457965f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41483
97067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.4148397067
Directory /workspace/4.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/4.usbdev_streaming_out.2873855829
Short name T2506
Test name
Test status
Simulation time 2957205712 ps
CPU time 22.89 seconds
Started Aug 02 05:28:00 PM PDT 24
Finished Aug 02 05:28:23 PM PDT 24
Peak memory 215892 kb
Host smart-1a209654-c53a-4216-8e3a-50da8ce1ad7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28738
55829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2873855829
Directory /workspace/4.usbdev_streaming_out/latest


Test location /workspace/coverage/default/4.usbdev_timeout_missing_host_handshake.659555201
Short name T3053
Test name
Test status
Simulation time 604187166 ps
CPU time 11.72 seconds
Started Aug 02 05:27:52 PM PDT 24
Finished Aug 02 05:28:04 PM PDT 24
Peak memory 207524 kb
Host smart-0ddcd474-0a67-4427-9612-70084f76ef26
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659555201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_timeout_missing_host_
handshake.659555201
Directory /workspace/4.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/40.usbdev_alert_test.529584334
Short name T2640
Test name
Test status
Simulation time 46436475 ps
CPU time 0.69 seconds
Started Aug 02 05:33:44 PM PDT 24
Finished Aug 02 05:33:45 PM PDT 24
Peak memory 207540 kb
Host smart-c67f4d99-7464-4b22-ae4b-ee426ce99dc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=529584334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.529584334
Directory /workspace/40.usbdev_alert_test/latest


Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2280091828
Short name T1768
Test name
Test status
Simulation time 4658130523 ps
CPU time 5.91 seconds
Started Aug 02 05:33:44 PM PDT 24
Finished Aug 02 05:33:50 PM PDT 24
Peak memory 216932 kb
Host smart-02122e17-a8a6-40f9-ae15-db8a2304b830
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280091828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_disconnect.2280091828
Directory /workspace/40.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.3329111376
Short name T224
Test name
Test status
Simulation time 13759095933 ps
CPU time 17.87 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:37 PM PDT 24
Peak memory 215864 kb
Host smart-4db1181f-3de7-4358-8da4-c00a6ca70ff0
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329111376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.3329111376
Directory /workspace/40.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2036870398
Short name T843
Test name
Test status
Simulation time 23821470465 ps
CPU time 29.83 seconds
Started Aug 02 05:33:41 PM PDT 24
Finished Aug 02 05:34:11 PM PDT 24
Peak memory 215844 kb
Host smart-697d6f7d-9a63-488a-a687-2a5a7c8399f2
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036870398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_a
on_wake_resume.2036870398
Directory /workspace/40.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/40.usbdev_av_buffer.269823447
Short name T2864
Test name
Test status
Simulation time 154203304 ps
CPU time 0.86 seconds
Started Aug 02 05:33:38 PM PDT 24
Finished Aug 02 05:33:39 PM PDT 24
Peak memory 207388 kb
Host smart-283fda5f-6386-4aa3-840c-4e9cfaacb127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26982
3447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.269823447
Directory /workspace/40.usbdev_av_buffer/latest


Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3227274767
Short name T3033
Test name
Test status
Simulation time 150084677 ps
CPU time 0.84 seconds
Started Aug 02 05:33:49 PM PDT 24
Finished Aug 02 05:33:50 PM PDT 24
Peak memory 207300 kb
Host smart-6002851a-9d24-46a3-ab3d-8edc24e5def5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32272
74767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3227274767
Directory /workspace/40.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3530077215
Short name T2871
Test name
Test status
Simulation time 294288805 ps
CPU time 1.17 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:33:44 PM PDT 24
Peak memory 207392 kb
Host smart-0a328129-f8e1-447f-9888-8d5485872105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35300
77215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3530077215
Directory /workspace/40.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2743415894
Short name T2977
Test name
Test status
Simulation time 1245462617 ps
CPU time 3.6 seconds
Started Aug 02 05:33:38 PM PDT 24
Finished Aug 02 05:33:42 PM PDT 24
Peak memory 207512 kb
Host smart-b1710ef4-a37e-44ea-81d8-d3b60aacd764
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=2743415894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2743415894
Directory /workspace/40.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/40.usbdev_device_address.1555745361
Short name T180
Test name
Test status
Simulation time 32382338864 ps
CPU time 46.87 seconds
Started Aug 02 05:33:38 PM PDT 24
Finished Aug 02 05:34:25 PM PDT 24
Peak memory 207648 kb
Host smart-4f93180e-9b0d-4701-844c-26994e465802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15557
45361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1555745361
Directory /workspace/40.usbdev_device_address/latest


Test location /workspace/coverage/default/40.usbdev_device_timeout.4131890389
Short name T866
Test name
Test status
Simulation time 622130630 ps
CPU time 5.12 seconds
Started Aug 02 05:33:20 PM PDT 24
Finished Aug 02 05:33:26 PM PDT 24
Peak memory 207584 kb
Host smart-4ba2abfb-5699-4094-871e-05a6a7fb9e42
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131890389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_timeout.4131890389
Directory /workspace/40.usbdev_device_timeout/latest


Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3740312849
Short name T1577
Test name
Test status
Simulation time 518505982 ps
CPU time 1.56 seconds
Started Aug 02 05:33:21 PM PDT 24
Finished Aug 02 05:33:23 PM PDT 24
Peak memory 207280 kb
Host smart-e7bf7d91-c665-4b91-87d0-6cf115426a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37403
12849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3740312849
Directory /workspace/40.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/40.usbdev_disconnected.3394383663
Short name T1409
Test name
Test status
Simulation time 211116523 ps
CPU time 0.85 seconds
Started Aug 02 05:33:31 PM PDT 24
Finished Aug 02 05:33:32 PM PDT 24
Peak memory 207276 kb
Host smart-e6fbc102-2747-4736-9eb2-3ad3cf9d94c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33943
83663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.3394383663
Directory /workspace/40.usbdev_disconnected/latest


Test location /workspace/coverage/default/40.usbdev_enable.1172215738
Short name T552
Test name
Test status
Simulation time 85244576 ps
CPU time 0.75 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:20 PM PDT 24
Peak memory 207292 kb
Host smart-3b9ddb67-c2f1-47ff-be55-ac5927e92269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11722
15738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1172215738
Directory /workspace/40.usbdev_enable/latest


Test location /workspace/coverage/default/40.usbdev_endpoint_access.2064490661
Short name T792
Test name
Test status
Simulation time 1042372166 ps
CPU time 2.56 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:33:45 PM PDT 24
Peak memory 207620 kb
Host smart-53c7d2a0-9a73-42be-b195-85fe3ac24072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20644
90661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2064490661
Directory /workspace/40.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/40.usbdev_endpoint_types.1516698680
Short name T401
Test name
Test status
Simulation time 342162524 ps
CPU time 1.12 seconds
Started Aug 02 05:33:35 PM PDT 24
Finished Aug 02 05:33:37 PM PDT 24
Peak memory 207300 kb
Host smart-02bf72a7-d5fd-4383-92e5-053f13d4c640
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1516698680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_types.1516698680
Directory /workspace/40.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/40.usbdev_fifo_rst.1121342495
Short name T2932
Test name
Test status
Simulation time 206923378 ps
CPU time 1.33 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:03 PM PDT 24
Peak memory 207516 kb
Host smart-a5a2426d-f8b3-48fb-b243-6d550bc663e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11213
42495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1121342495
Directory /workspace/40.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/40.usbdev_in_iso.192696993
Short name T1119
Test name
Test status
Simulation time 192582255 ps
CPU time 1.02 seconds
Started Aug 02 05:33:20 PM PDT 24
Finished Aug 02 05:33:21 PM PDT 24
Peak memory 207560 kb
Host smart-afe85aab-fdd8-49e6-8ed0-9aeb3aaf0f3f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=192696993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.192696993
Directory /workspace/40.usbdev_in_iso/latest


Test location /workspace/coverage/default/40.usbdev_in_stall.2311013941
Short name T2315
Test name
Test status
Simulation time 220389159 ps
CPU time 0.88 seconds
Started Aug 02 05:33:28 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 207328 kb
Host smart-780c3720-a444-4d5e-80ec-fbce4eed2eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23110
13941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2311013941
Directory /workspace/40.usbdev_in_stall/latest


Test location /workspace/coverage/default/40.usbdev_in_trans.4089745591
Short name T2092
Test name
Test status
Simulation time 231607774 ps
CPU time 0.95 seconds
Started Aug 02 05:33:33 PM PDT 24
Finished Aug 02 05:33:34 PM PDT 24
Peak memory 207356 kb
Host smart-86931612-06fd-43fa-916f-e36868d3aab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40897
45591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.4089745591
Directory /workspace/40.usbdev_in_trans/latest


Test location /workspace/coverage/default/40.usbdev_invalid_sync.2836089508
Short name T2552
Test name
Test status
Simulation time 4262551500 ps
CPU time 116.41 seconds
Started Aug 02 05:33:56 PM PDT 24
Finished Aug 02 05:35:52 PM PDT 24
Peak memory 218276 kb
Host smart-27d1dc2b-5f0f-46ce-ad72-cec91c4ef9dd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2836089508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2836089508
Directory /workspace/40.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/40.usbdev_iso_retraction.3166108087
Short name T730
Test name
Test status
Simulation time 3731890247 ps
CPU time 48.42 seconds
Started Aug 02 05:33:35 PM PDT 24
Finished Aug 02 05:34:23 PM PDT 24
Peak memory 207608 kb
Host smart-59f8209e-5d03-40d1-aade-ded23b136c73
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3166108087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.3166108087
Directory /workspace/40.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/40.usbdev_link_in_err.1349787106
Short name T1869
Test name
Test status
Simulation time 224037538 ps
CPU time 0.99 seconds
Started Aug 02 05:33:35 PM PDT 24
Finished Aug 02 05:33:36 PM PDT 24
Peak memory 207384 kb
Host smart-37cdb277-9baf-4e37-846f-705ba650de01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13497
87106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.1349787106
Directory /workspace/40.usbdev_link_in_err/latest


Test location /workspace/coverage/default/40.usbdev_link_resume.2857674017
Short name T2082
Test name
Test status
Simulation time 6275763649 ps
CPU time 10.4 seconds
Started Aug 02 05:33:22 PM PDT 24
Finished Aug 02 05:33:33 PM PDT 24
Peak memory 216000 kb
Host smart-9ea1d085-9cea-4fe0-b481-c03f7b66442c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28576
74017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.2857674017
Directory /workspace/40.usbdev_link_resume/latest


Test location /workspace/coverage/default/40.usbdev_link_suspend.2838949069
Short name T1278
Test name
Test status
Simulation time 10055674567 ps
CPU time 12.53 seconds
Started Aug 02 05:33:41 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207688 kb
Host smart-1a8d442a-e20d-43cc-9c93-a84b25c5640e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28389
49069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2838949069
Directory /workspace/40.usbdev_link_suspend/latest


Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.2889115616
Short name T994
Test name
Test status
Simulation time 2337822377 ps
CPU time 17.09 seconds
Started Aug 02 05:33:34 PM PDT 24
Finished Aug 02 05:33:51 PM PDT 24
Peak memory 223980 kb
Host smart-089bd205-da02-4548-89e0-9d16d32fbccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28891
15616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.2889115616
Directory /workspace/40.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2207666034
Short name T2745
Test name
Test status
Simulation time 2967842597 ps
CPU time 81.2 seconds
Started Aug 02 05:33:18 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 217216 kb
Host smart-0f56580e-6e62-403d-ad7c-4997dbdbcecd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2207666034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2207666034
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.2466098408
Short name T2371
Test name
Test status
Simulation time 240243064 ps
CPU time 1.04 seconds
Started Aug 02 05:33:22 PM PDT 24
Finished Aug 02 05:33:23 PM PDT 24
Peak memory 207328 kb
Host smart-fda9170a-3fd6-4cf9-9bb4-53add2e3b591
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2466098408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.2466098408
Directory /workspace/40.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1669272779
Short name T1866
Test name
Test status
Simulation time 209082784 ps
CPU time 0.89 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:33:21 PM PDT 24
Peak memory 207404 kb
Host smart-f11f69af-02a4-4914-ac09-ea03009cef63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16692
72779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1669272779
Directory /workspace/40.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.514406703
Short name T911
Test name
Test status
Simulation time 4081671952 ps
CPU time 113.23 seconds
Started Aug 02 05:33:19 PM PDT 24
Finished Aug 02 05:35:12 PM PDT 24
Peak memory 215896 kb
Host smart-24c14d3b-abcf-490e-82f1-e6b0c261a400
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=514406703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.514406703
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.269323257
Short name T914
Test name
Test status
Simulation time 194809520 ps
CPU time 0.84 seconds
Started Aug 02 05:33:22 PM PDT 24
Finished Aug 02 05:33:23 PM PDT 24
Peak memory 207412 kb
Host smart-a649dd4d-7ddc-40c7-9fdd-7212948fd0fb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=269323257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.269323257
Directory /workspace/40.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3641764507
Short name T1990
Test name
Test status
Simulation time 158000681 ps
CPU time 0.85 seconds
Started Aug 02 05:33:20 PM PDT 24
Finished Aug 02 05:33:21 PM PDT 24
Peak memory 207420 kb
Host smart-e7ea721f-f3db-4123-836f-10b8527d8d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36417
64507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3641764507
Directory /workspace/40.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_nak_trans.3502353726
Short name T152
Test name
Test status
Simulation time 183615535 ps
CPU time 1.01 seconds
Started Aug 02 05:33:29 PM PDT 24
Finished Aug 02 05:33:30 PM PDT 24
Peak memory 207384 kb
Host smart-d18f511a-3e63-4423-bc83-ec8c1fd5e674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35023
53726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.3502353726
Directory /workspace/40.usbdev_nak_trans/latest


Test location /workspace/coverage/default/40.usbdev_out_iso.3586853182
Short name T2381
Test name
Test status
Simulation time 185333280 ps
CPU time 0.94 seconds
Started Aug 02 05:33:39 PM PDT 24
Finished Aug 02 05:33:40 PM PDT 24
Peak memory 207352 kb
Host smart-7f7e7e07-d16b-4ce1-a27e-48df02c6dfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35868
53182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3586853182
Directory /workspace/40.usbdev_out_iso/latest


Test location /workspace/coverage/default/40.usbdev_out_stall.273710180
Short name T2145
Test name
Test status
Simulation time 160657607 ps
CPU time 0.84 seconds
Started Aug 02 05:33:35 PM PDT 24
Finished Aug 02 05:33:36 PM PDT 24
Peak memory 207404 kb
Host smart-485c8f1f-1bd6-4d9d-8f62-4e5ee3162b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27371
0180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.273710180
Directory /workspace/40.usbdev_out_stall/latest


Test location /workspace/coverage/default/40.usbdev_out_trans_nak.2729390844
Short name T1350
Test name
Test status
Simulation time 207651688 ps
CPU time 0.89 seconds
Started Aug 02 05:33:29 PM PDT 24
Finished Aug 02 05:33:30 PM PDT 24
Peak memory 207324 kb
Host smart-8c2fada7-5940-4b16-b07c-582ac5ee7aa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27293
90844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.2729390844
Directory /workspace/40.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3179083159
Short name T191
Test name
Test status
Simulation time 173431649 ps
CPU time 0.96 seconds
Started Aug 02 05:33:28 PM PDT 24
Finished Aug 02 05:33:29 PM PDT 24
Peak memory 207392 kb
Host smart-d24c5042-a60f-418a-a898-418e82c763b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31790
83159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3179083159
Directory /workspace/40.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.1867266924
Short name T2201
Test name
Test status
Simulation time 239321634 ps
CPU time 1.12 seconds
Started Aug 02 05:33:30 PM PDT 24
Finished Aug 02 05:33:31 PM PDT 24
Peak memory 207320 kb
Host smart-4f0d776a-99d8-4a35-ba37-d17a11dfe323
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1867266924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.1867266924
Directory /workspace/40.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.2190234598
Short name T1505
Test name
Test status
Simulation time 194651378 ps
CPU time 0.89 seconds
Started Aug 02 05:33:38 PM PDT 24
Finished Aug 02 05:33:39 PM PDT 24
Peak memory 207396 kb
Host smart-bca5470c-0ab5-4a7e-bd5e-d2180dccc824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21902
34598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.2190234598
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.415346888
Short name T1615
Test name
Test status
Simulation time 60259802 ps
CPU time 0.69 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:33:44 PM PDT 24
Peak memory 207348 kb
Host smart-4a3be733-0619-4574-95db-13f1685f6adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41534
6888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.415346888
Directory /workspace/40.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3580175732
Short name T1796
Test name
Test status
Simulation time 9737681958 ps
CPU time 27.17 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 223996 kb
Host smart-6af26ef1-d630-4ed4-b3c6-ba7e373af2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35801
75732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3580175732
Directory /workspace/40.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/40.usbdev_pkt_received.1659112522
Short name T1663
Test name
Test status
Simulation time 166485575 ps
CPU time 0.91 seconds
Started Aug 02 05:33:46 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 207408 kb
Host smart-b96d2ee2-1818-4b16-a336-1439d5e3f566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
12522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.1659112522
Directory /workspace/40.usbdev_pkt_received/latest


Test location /workspace/coverage/default/40.usbdev_pkt_sent.293326050
Short name T500
Test name
Test status
Simulation time 237430822 ps
CPU time 1.07 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:33:44 PM PDT 24
Peak memory 207416 kb
Host smart-3694c5a2-7af5-4fad-94b4-50da101804f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29332
6050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.293326050
Directory /workspace/40.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1113745064
Short name T801
Test name
Test status
Simulation time 229547821 ps
CPU time 0.96 seconds
Started Aug 02 05:33:39 PM PDT 24
Finished Aug 02 05:33:40 PM PDT 24
Peak memory 207368 kb
Host smart-8c8097a0-1907-4c0e-9f5f-2cf0b52e0450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11137
45064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1113745064
Directory /workspace/40.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1629247355
Short name T2073
Test name
Test status
Simulation time 174429257 ps
CPU time 0.89 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 207352 kb
Host smart-a5ac7489-4ffb-44a5-b97d-e30922cdb77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16292
47355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1629247355
Directory /workspace/40.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/40.usbdev_rx_crc_err.2017015611
Short name T1957
Test name
Test status
Simulation time 166662523 ps
CPU time 0.87 seconds
Started Aug 02 05:33:46 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 207400 kb
Host smart-1dd443ae-3589-43c3-b603-f944e0783012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20170
15611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.2017015611
Directory /workspace/40.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/40.usbdev_rx_full.3274610745
Short name T1410
Test name
Test status
Simulation time 241089139 ps
CPU time 1.09 seconds
Started Aug 02 05:33:45 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 207376 kb
Host smart-90e988b5-c8c2-4ea7-a24c-b33c1f7f61ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32746
10745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_full.3274610745
Directory /workspace/40.usbdev_rx_full/latest


Test location /workspace/coverage/default/40.usbdev_setup_stage.2155819575
Short name T2057
Test name
Test status
Simulation time 148082181 ps
CPU time 0.85 seconds
Started Aug 02 05:33:42 PM PDT 24
Finished Aug 02 05:33:43 PM PDT 24
Peak memory 207376 kb
Host smart-5a9990ea-8248-4f11-8e33-19f29a1afd2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21558
19575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2155819575
Directory /workspace/40.usbdev_setup_stage/latest


Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.917386388
Short name T1320
Test name
Test status
Simulation time 165541525 ps
CPU time 0.87 seconds
Started Aug 02 05:33:37 PM PDT 24
Finished Aug 02 05:33:38 PM PDT 24
Peak memory 207420 kb
Host smart-fd0ab429-57ae-462a-b967-e162f025a3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91738
6388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.917386388
Directory /workspace/40.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/40.usbdev_smoke.1466352576
Short name T1557
Test name
Test status
Simulation time 206503448 ps
CPU time 0.94 seconds
Started Aug 02 05:33:45 PM PDT 24
Finished Aug 02 05:33:46 PM PDT 24
Peak memory 207336 kb
Host smart-94ee55b2-25cf-49e5-990b-bde3ac4389cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14663
52576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1466352576
Directory /workspace/40.usbdev_smoke/latest


Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1318354872
Short name T2846
Test name
Test status
Simulation time 2240688361 ps
CPU time 17.52 seconds
Started Aug 02 05:33:50 PM PDT 24
Finished Aug 02 05:34:07 PM PDT 24
Peak memory 217496 kb
Host smart-46a6459a-503e-4eab-b8fb-0e8ab81b1ea8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1318354872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1318354872
Directory /workspace/40.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.68779697
Short name T1570
Test name
Test status
Simulation time 217752332 ps
CPU time 0.89 seconds
Started Aug 02 05:33:42 PM PDT 24
Finished Aug 02 05:33:43 PM PDT 24
Peak memory 207432 kb
Host smart-c45b52ad-3d7d-4c95-b787-60bd6b88c46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68779
697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.68779697
Directory /workspace/40.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/40.usbdev_stall_trans.1361477870
Short name T847
Test name
Test status
Simulation time 201041171 ps
CPU time 0.93 seconds
Started Aug 02 05:33:45 PM PDT 24
Finished Aug 02 05:33:46 PM PDT 24
Peak memory 207384 kb
Host smart-4ce70068-af2a-4216-af34-fc3d739abbec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13614
77870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.1361477870
Directory /workspace/40.usbdev_stall_trans/latest


Test location /workspace/coverage/default/40.usbdev_stream_len_max.766381635
Short name T1327
Test name
Test status
Simulation time 622153971 ps
CPU time 1.71 seconds
Started Aug 02 05:33:44 PM PDT 24
Finished Aug 02 05:33:46 PM PDT 24
Peak memory 207328 kb
Host smart-6dcebb1e-5c16-4079-b727-86cc99c91cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76638
1635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.766381635
Directory /workspace/40.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/40.usbdev_streaming_out.1048469675
Short name T835
Test name
Test status
Simulation time 2785291430 ps
CPU time 20.87 seconds
Started Aug 02 05:33:44 PM PDT 24
Finished Aug 02 05:34:05 PM PDT 24
Peak memory 215820 kb
Host smart-49923a35-dcb8-4d6e-96fa-48396ee5f530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484
69675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1048469675
Directory /workspace/40.usbdev_streaming_out/latest


Test location /workspace/coverage/default/40.usbdev_timeout_missing_host_handshake.2215639602
Short name T1039
Test name
Test status
Simulation time 727637621 ps
CPU time 15.56 seconds
Started Aug 02 05:33:42 PM PDT 24
Finished Aug 02 05:33:57 PM PDT 24
Peak memory 207560 kb
Host smart-3c258b05-a61c-44f6-879f-bd129fc156f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215639602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_timeout_missing_hos
t_handshake.2215639602
Directory /workspace/40.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/41.usbdev_alert_test.351723327
Short name T2159
Test name
Test status
Simulation time 46718620 ps
CPU time 0.65 seconds
Started Aug 02 05:33:46 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 207480 kb
Host smart-a864493d-c72d-475c-a2dd-c7ecb40773ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=351723327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.351723327
Directory /workspace/41.usbdev_alert_test/latest


Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3246759987
Short name T1362
Test name
Test status
Simulation time 4475894827 ps
CPU time 6.11 seconds
Started Aug 02 05:33:50 PM PDT 24
Finished Aug 02 05:33:57 PM PDT 24
Peak memory 215780 kb
Host smart-362a8527-34f9-4437-a0be-3c4c688587df
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246759987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_disconnect.3246759987
Directory /workspace/41.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3102010351
Short name T1308
Test name
Test status
Simulation time 15988981770 ps
CPU time 21.83 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 215800 kb
Host smart-a6e7251c-7874-4842-8f7a-3609ab5dd544
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102010351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3102010351
Directory /workspace/41.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3660556137
Short name T640
Test name
Test status
Simulation time 28579281162 ps
CPU time 38.92 seconds
Started Aug 02 05:33:40 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 207688 kb
Host smart-980e3bc1-3510-4ede-b921-375b3cb117a9
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660556137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_a
on_wake_resume.3660556137
Directory /workspace/41.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/41.usbdev_av_buffer.1703758659
Short name T702
Test name
Test status
Simulation time 169170575 ps
CPU time 0.86 seconds
Started Aug 02 05:33:44 PM PDT 24
Finished Aug 02 05:33:45 PM PDT 24
Peak memory 207404 kb
Host smart-a5321451-8b36-4d11-9618-7103b624bf1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17037
58659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1703758659
Directory /workspace/41.usbdev_av_buffer/latest


Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2831807827
Short name T2273
Test name
Test status
Simulation time 174478959 ps
CPU time 0.83 seconds
Started Aug 02 05:33:39 PM PDT 24
Finished Aug 02 05:33:40 PM PDT 24
Peak memory 207276 kb
Host smart-67b3e656-f109-4f6c-a88e-8322fa29f5fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28318
07827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2831807827
Directory /workspace/41.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3320771494
Short name T875
Test name
Test status
Simulation time 414043392 ps
CPU time 1.45 seconds
Started Aug 02 05:33:37 PM PDT 24
Finished Aug 02 05:33:38 PM PDT 24
Peak memory 207404 kb
Host smart-5d19a12c-ce45-40cc-97bf-36feb5ec32c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33207
71494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3320771494
Directory /workspace/41.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1470934889
Short name T1081
Test name
Test status
Simulation time 822296902 ps
CPU time 2.44 seconds
Started Aug 02 05:33:45 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 207556 kb
Host smart-471d3987-d26a-4beb-9a4b-8df557ff0424
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1470934889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1470934889
Directory /workspace/41.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/41.usbdev_device_address.1465149701
Short name T2009
Test name
Test status
Simulation time 30174982143 ps
CPU time 52.77 seconds
Started Aug 02 05:33:49 PM PDT 24
Finished Aug 02 05:34:42 PM PDT 24
Peak memory 207704 kb
Host smart-976ad33c-9c45-4a38-8b11-2bddd5b15ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14651
49701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1465149701
Directory /workspace/41.usbdev_device_address/latest


Test location /workspace/coverage/default/41.usbdev_device_timeout.4036581463
Short name T93
Test name
Test status
Simulation time 1185029271 ps
CPU time 24.79 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:34:16 PM PDT 24
Peak memory 207560 kb
Host smart-b9a608a9-ae25-4e7c-bde8-a5edca4ede78
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036581463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_timeout.4036581463
Directory /workspace/41.usbdev_device_timeout/latest


Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3158142158
Short name T2469
Test name
Test status
Simulation time 1251516960 ps
CPU time 2.67 seconds
Started Aug 02 05:33:36 PM PDT 24
Finished Aug 02 05:33:39 PM PDT 24
Peak memory 207320 kb
Host smart-e376d772-d949-4ae7-8337-daa26ce8e361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31581
42158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3158142158
Directory /workspace/41.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/41.usbdev_disconnected.4259353668
Short name T858
Test name
Test status
Simulation time 143210431 ps
CPU time 0.81 seconds
Started Aug 02 05:33:49 PM PDT 24
Finished Aug 02 05:33:50 PM PDT 24
Peak memory 207376 kb
Host smart-99fd2763-c663-47b9-88f9-0f284512a738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42593
53668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.4259353668
Directory /workspace/41.usbdev_disconnected/latest


Test location /workspace/coverage/default/41.usbdev_enable.783663584
Short name T1928
Test name
Test status
Simulation time 48358094 ps
CPU time 0.72 seconds
Started Aug 02 05:33:41 PM PDT 24
Finished Aug 02 05:33:42 PM PDT 24
Peak memory 207384 kb
Host smart-044c0d03-d584-4313-ade6-b9459b60de67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78366
3584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.783663584
Directory /workspace/41.usbdev_enable/latest


Test location /workspace/coverage/default/41.usbdev_endpoint_access.3939183835
Short name T2821
Test name
Test status
Simulation time 933373711 ps
CPU time 2.31 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:33:46 PM PDT 24
Peak memory 207600 kb
Host smart-cce96ca6-3ded-49f5-92e9-1a40bd0bb11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39391
83835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3939183835
Directory /workspace/41.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/41.usbdev_endpoint_types.4140032564
Short name T458
Test name
Test status
Simulation time 727417459 ps
CPU time 1.87 seconds
Started Aug 02 05:33:35 PM PDT 24
Finished Aug 02 05:33:37 PM PDT 24
Peak memory 207404 kb
Host smart-3cfa1a7e-404a-4a6f-954d-62adf01f73a9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4140032564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_types.4140032564
Directory /workspace/41.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/41.usbdev_fifo_rst.926334391
Short name T1084
Test name
Test status
Simulation time 286005453 ps
CPU time 2.06 seconds
Started Aug 02 05:33:40 PM PDT 24
Finished Aug 02 05:33:43 PM PDT 24
Peak memory 207548 kb
Host smart-330e5a45-8c1e-4a43-9f8e-ea25e7c47e67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92633
4391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.926334391
Directory /workspace/41.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/41.usbdev_in_iso.4185305413
Short name T2944
Test name
Test status
Simulation time 206787885 ps
CPU time 1.1 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 207548 kb
Host smart-da548eab-fe08-4849-900a-417b77172048
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4185305413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.4185305413
Directory /workspace/41.usbdev_in_iso/latest


Test location /workspace/coverage/default/41.usbdev_in_stall.2495881441
Short name T1939
Test name
Test status
Simulation time 154890268 ps
CPU time 0.85 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 207296 kb
Host smart-64834eb6-3830-4f47-b145-bfc45274a690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24958
81441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2495881441
Directory /workspace/41.usbdev_in_stall/latest


Test location /workspace/coverage/default/41.usbdev_in_trans.3474602376
Short name T1598
Test name
Test status
Simulation time 291261041 ps
CPU time 1.09 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:33:45 PM PDT 24
Peak memory 207392 kb
Host smart-22b9d13a-501f-42de-bc75-92397f558e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34746
02376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3474602376
Directory /workspace/41.usbdev_in_trans/latest


Test location /workspace/coverage/default/41.usbdev_invalid_sync.1302528686
Short name T1387
Test name
Test status
Simulation time 4020702942 ps
CPU time 30.31 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:34:14 PM PDT 24
Peak memory 224088 kb
Host smart-eeacc98d-abe8-48be-b2c9-5394be9cb5ff
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1302528686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.1302528686
Directory /workspace/41.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/41.usbdev_iso_retraction.2775499672
Short name T1806
Test name
Test status
Simulation time 8909616922 ps
CPU time 61.92 seconds
Started Aug 02 05:33:42 PM PDT 24
Finished Aug 02 05:34:44 PM PDT 24
Peak memory 207632 kb
Host smart-63b54d84-ec3a-49b1-9309-e2258276285d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2775499672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2775499672
Directory /workspace/41.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/41.usbdev_link_in_err.2512451954
Short name T821
Test name
Test status
Simulation time 189936745 ps
CPU time 0.93 seconds
Started Aug 02 05:33:47 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 207384 kb
Host smart-7bfb2816-9ed9-4b79-bda3-ab8bd92f6df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25124
51954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.2512451954
Directory /workspace/41.usbdev_link_in_err/latest


Test location /workspace/coverage/default/41.usbdev_link_resume.1734650031
Short name T1203
Test name
Test status
Simulation time 13646342370 ps
CPU time 22.06 seconds
Started Aug 02 05:33:50 PM PDT 24
Finished Aug 02 05:34:12 PM PDT 24
Peak memory 207668 kb
Host smart-14b6d1f7-0c0a-4516-bad7-9533e3eeb39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17346
50031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.1734650031
Directory /workspace/41.usbdev_link_resume/latest


Test location /workspace/coverage/default/41.usbdev_link_suspend.1426697238
Short name T1126
Test name
Test status
Simulation time 8921955246 ps
CPU time 13.75 seconds
Started Aug 02 05:33:35 PM PDT 24
Finished Aug 02 05:33:49 PM PDT 24
Peak memory 207672 kb
Host smart-412e56dd-1d23-48cd-9199-9bdc4a1d56f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14266
97238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1426697238
Directory /workspace/41.usbdev_link_suspend/latest


Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.865696727
Short name T1903
Test name
Test status
Simulation time 2196594000 ps
CPU time 63.86 seconds
Started Aug 02 05:33:50 PM PDT 24
Finished Aug 02 05:34:54 PM PDT 24
Peak memory 215796 kb
Host smart-e729fd2c-4a67-41a2-afb0-16862af5f606
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=865696727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.865696727
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.242490368
Short name T2912
Test name
Test status
Simulation time 236758370 ps
CPU time 0.93 seconds
Started Aug 02 05:33:42 PM PDT 24
Finished Aug 02 05:33:43 PM PDT 24
Peak memory 207420 kb
Host smart-106fb9f3-8809-4145-8b44-1c7b6d05de14
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=242490368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.242490368
Directory /workspace/41.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.2572135552
Short name T2244
Test name
Test status
Simulation time 192412519 ps
CPU time 0.93 seconds
Started Aug 02 05:33:37 PM PDT 24
Finished Aug 02 05:33:38 PM PDT 24
Peak memory 207348 kb
Host smart-69909fb2-6e69-4cdc-828d-28c4ed48de4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25721
35552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.2572135552
Directory /workspace/41.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2452717999
Short name T1063
Test name
Test status
Simulation time 3114330469 ps
CPU time 31.08 seconds
Started Aug 02 05:33:48 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 215832 kb
Host smart-916861b2-a812-4ec7-854e-8b51bf04ff85
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2452717999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2452717999
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.3321770290
Short name T2373
Test name
Test status
Simulation time 182107022 ps
CPU time 0.94 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207356 kb
Host smart-2092c679-7530-4f72-b6ef-9c74f994469e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3321770290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.3321770290
Directory /workspace/41.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1339017315
Short name T2571
Test name
Test status
Simulation time 146360897 ps
CPU time 0.79 seconds
Started Aug 02 05:33:56 PM PDT 24
Finished Aug 02 05:33:56 PM PDT 24
Peak memory 207432 kb
Host smart-99f1a4cf-e946-4bfa-b5cb-ecef93346d50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13390
17315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1339017315
Directory /workspace/41.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_nak_trans.3578555136
Short name T161
Test name
Test status
Simulation time 215362718 ps
CPU time 0.92 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207432 kb
Host smart-984e2a1d-30b2-47f7-9992-99b7f7437f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35785
55136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.3578555136
Directory /workspace/41.usbdev_nak_trans/latest


Test location /workspace/coverage/default/41.usbdev_out_iso.920123952
Short name T567
Test name
Test status
Simulation time 157926283 ps
CPU time 0.84 seconds
Started Aug 02 05:33:47 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 207428 kb
Host smart-e641d9a7-7fca-4919-9116-d286264e9885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92012
3952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.920123952
Directory /workspace/41.usbdev_out_iso/latest


Test location /workspace/coverage/default/41.usbdev_out_stall.2045373838
Short name T2256
Test name
Test status
Simulation time 178031237 ps
CPU time 0.89 seconds
Started Aug 02 05:33:50 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 207408 kb
Host smart-c7f8f3e4-e8bf-4f96-aa80-1d5d2ffde51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20453
73838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.2045373838
Directory /workspace/41.usbdev_out_stall/latest


Test location /workspace/coverage/default/41.usbdev_out_trans_nak.2932258301
Short name T2130
Test name
Test status
Simulation time 143266533 ps
CPU time 0.8 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207440 kb
Host smart-5ed6c586-3493-4e9b-aa87-206d7569a864
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29322
58301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.2932258301
Directory /workspace/41.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/41.usbdev_pending_in_trans.2506497040
Short name T1821
Test name
Test status
Simulation time 145222246 ps
CPU time 0.81 seconds
Started Aug 02 05:33:38 PM PDT 24
Finished Aug 02 05:33:39 PM PDT 24
Peak memory 207412 kb
Host smart-c12d7d3f-0c39-4f52-99e3-e12edf14bc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25064
97040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.2506497040
Directory /workspace/41.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2124061245
Short name T2228
Test name
Test status
Simulation time 218301558 ps
CPU time 1.03 seconds
Started Aug 02 05:33:46 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 207324 kb
Host smart-8882b94f-74c3-4585-b35c-2bc557d1cd01
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2124061245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2124061245
Directory /workspace/41.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1684538036
Short name T201
Test name
Test status
Simulation time 141074852 ps
CPU time 0.88 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 207360 kb
Host smart-d724674a-4a67-4a46-b84d-eecc1bef4b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16845
38036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1684538036
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3349319196
Short name T2949
Test name
Test status
Simulation time 48115752 ps
CPU time 0.69 seconds
Started Aug 02 05:33:45 PM PDT 24
Finished Aug 02 05:33:45 PM PDT 24
Peak memory 207372 kb
Host smart-1212e51b-65c7-459f-bd92-63d9087db477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33493
19196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3349319196
Directory /workspace/41.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/41.usbdev_pkt_buffer.110515228
Short name T1393
Test name
Test status
Simulation time 13386191497 ps
CPU time 31.22 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:34:24 PM PDT 24
Peak memory 224056 kb
Host smart-3a886ba1-876d-4f16-b78a-c1b3e06cca74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11051
5228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.110515228
Directory /workspace/41.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/41.usbdev_pkt_received.2815947677
Short name T1253
Test name
Test status
Simulation time 212497023 ps
CPU time 1.03 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:33:44 PM PDT 24
Peak memory 207412 kb
Host smart-2f5e8e79-a300-4ef3-8723-63d2f1062ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28159
47677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.2815947677
Directory /workspace/41.usbdev_pkt_received/latest


Test location /workspace/coverage/default/41.usbdev_pkt_sent.2601932232
Short name T1569
Test name
Test status
Simulation time 210261863 ps
CPU time 0.97 seconds
Started Aug 02 05:33:52 PM PDT 24
Finished Aug 02 05:33:53 PM PDT 24
Peak memory 207376 kb
Host smart-c52787ff-f0e2-4d6e-bb2d-9230ca6f21d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26019
32232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2601932232
Directory /workspace/41.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.693645163
Short name T3061
Test name
Test status
Simulation time 234178203 ps
CPU time 0.96 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:33:45 PM PDT 24
Peak memory 207336 kb
Host smart-7d54b727-5628-4b1e-b47a-b263a9c79d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69364
5163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.693645163
Directory /workspace/41.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.2970513477
Short name T2482
Test name
Test status
Simulation time 200040833 ps
CPU time 0.95 seconds
Started Aug 02 05:33:34 PM PDT 24
Finished Aug 02 05:33:35 PM PDT 24
Peak memory 207404 kb
Host smart-22125ecb-83dd-4e75-83ab-f46209a8ed76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29705
13477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.2970513477
Directory /workspace/41.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1155082948
Short name T73
Test name
Test status
Simulation time 146055976 ps
CPU time 0.86 seconds
Started Aug 02 05:33:49 PM PDT 24
Finished Aug 02 05:33:50 PM PDT 24
Peak memory 207368 kb
Host smart-95361ef2-1a43-4767-9d4a-6a31958ec1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11550
82948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1155082948
Directory /workspace/41.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/41.usbdev_rx_full.3204599778
Short name T545
Test name
Test status
Simulation time 252439377 ps
CPU time 1.12 seconds
Started Aug 02 05:33:46 PM PDT 24
Finished Aug 02 05:33:47 PM PDT 24
Peak memory 207388 kb
Host smart-931321f3-326f-4a09-8f95-615f9eca625b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32045
99778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_full.3204599778
Directory /workspace/41.usbdev_rx_full/latest


Test location /workspace/coverage/default/41.usbdev_setup_stage.1515630278
Short name T865
Test name
Test status
Simulation time 162033557 ps
CPU time 0.88 seconds
Started Aug 02 05:33:50 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 207368 kb
Host smart-36bfeb17-c372-48f1-82e7-5b541ee342f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15156
30278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1515630278
Directory /workspace/41.usbdev_setup_stage/latest


Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.3267202350
Short name T2674
Test name
Test status
Simulation time 159812104 ps
CPU time 0.81 seconds
Started Aug 02 05:33:49 PM PDT 24
Finished Aug 02 05:33:49 PM PDT 24
Peak memory 207212 kb
Host smart-13967b58-906d-4d5d-9d22-fbee6b4395ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32672
02350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.3267202350
Directory /workspace/41.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/41.usbdev_smoke.2488611158
Short name T1901
Test name
Test status
Simulation time 294127131 ps
CPU time 1.05 seconds
Started Aug 02 05:34:00 PM PDT 24
Finished Aug 02 05:34:01 PM PDT 24
Peak memory 207204 kb
Host smart-6ddba462-6b75-4b7d-8d66-33fe4675ccaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24886
11158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.2488611158
Directory /workspace/41.usbdev_smoke/latest


Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2903584817
Short name T3086
Test name
Test status
Simulation time 2727895653 ps
CPU time 20.77 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:34:14 PM PDT 24
Peak memory 223876 kb
Host smart-c3ab56e2-df37-42f8-b36e-5f3a3042570a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2903584817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2903584817
Directory /workspace/41.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.3759926995
Short name T2135
Test name
Test status
Simulation time 170847619 ps
CPU time 0.88 seconds
Started Aug 02 05:33:42 PM PDT 24
Finished Aug 02 05:33:43 PM PDT 24
Peak memory 207368 kb
Host smart-2bd1f287-ecd9-4fc6-8bfa-5c1a76fec288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37599
26995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.3759926995
Directory /workspace/41.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/41.usbdev_stall_trans.3596890774
Short name T3076
Test name
Test status
Simulation time 182696543 ps
CPU time 0.97 seconds
Started Aug 02 05:33:55 PM PDT 24
Finished Aug 02 05:33:56 PM PDT 24
Peak memory 207400 kb
Host smart-ae8c2449-b4f4-453c-af0c-dbb5beb94652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35968
90774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3596890774
Directory /workspace/41.usbdev_stall_trans/latest


Test location /workspace/coverage/default/41.usbdev_stream_len_max.4012258873
Short name T2682
Test name
Test status
Simulation time 746012949 ps
CPU time 1.94 seconds
Started Aug 02 05:33:36 PM PDT 24
Finished Aug 02 05:33:38 PM PDT 24
Peak memory 207348 kb
Host smart-c9eee73e-ca91-4cf2-9a83-df879399c340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40122
58873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.4012258873
Directory /workspace/41.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/41.usbdev_streaming_out.239366023
Short name T2521
Test name
Test status
Simulation time 4287309062 ps
CPU time 121.91 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:35:55 PM PDT 24
Peak memory 217072 kb
Host smart-a06e2c1a-aa51-4fda-8d7a-a4742d0cb1bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23936
6023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.239366023
Directory /workspace/41.usbdev_streaming_out/latest


Test location /workspace/coverage/default/41.usbdev_timeout_missing_host_handshake.1943193256
Short name T1421
Test name
Test status
Simulation time 3667525884 ps
CPU time 23.21 seconds
Started Aug 02 05:33:50 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 207664 kb
Host smart-0f69cfb6-ea9a-4d33-96f9-99f4ac31994c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943193256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_timeout_missing_hos
t_handshake.1943193256
Directory /workspace/41.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/42.usbdev_alert_test.3979548715
Short name T961
Test name
Test status
Simulation time 49101201 ps
CPU time 0.69 seconds
Started Aug 02 05:33:58 PM PDT 24
Finished Aug 02 05:33:59 PM PDT 24
Peak memory 207500 kb
Host smart-4253ec0b-0c41-453d-86b6-5d5302da4917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3979548715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3979548715
Directory /workspace/42.usbdev_alert_test/latest


Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.516084463
Short name T1526
Test name
Test status
Simulation time 4220509908 ps
CPU time 6.61 seconds
Started Aug 02 05:33:44 PM PDT 24
Finished Aug 02 05:33:51 PM PDT 24
Peak memory 215844 kb
Host smart-1248e345-ab5d-4910-b3d7-8451dec4f467
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516084463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_ao
n_wake_disconnect.516084463
Directory /workspace/42.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2551592303
Short name T3046
Test name
Test status
Simulation time 18970489454 ps
CPU time 21.72 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:34:05 PM PDT 24
Peak memory 207680 kb
Host smart-6a131d03-ca1d-4dd8-921c-a41c33305d1d
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551592303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2551592303
Directory /workspace/42.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1589183060
Short name T3087
Test name
Test status
Simulation time 24629768221 ps
CPU time 32.75 seconds
Started Aug 02 05:33:47 PM PDT 24
Finished Aug 02 05:34:20 PM PDT 24
Peak memory 215904 kb
Host smart-cead56f1-7488-424f-a175-219b1af55540
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589183060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_a
on_wake_resume.1589183060
Directory /workspace/42.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/42.usbdev_av_buffer.1996071246
Short name T1875
Test name
Test status
Simulation time 214095719 ps
CPU time 0.85 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:02 PM PDT 24
Peak memory 207412 kb
Host smart-2a633427-08d7-4c3f-ac5f-84587a98c1f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19960
71246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1996071246
Directory /workspace/42.usbdev_av_buffer/latest


Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3342547706
Short name T74
Test name
Test status
Simulation time 144143186 ps
CPU time 0.84 seconds
Started Aug 02 05:34:07 PM PDT 24
Finished Aug 02 05:34:08 PM PDT 24
Peak memory 207176 kb
Host smart-c692d3c9-77b3-4e56-89f8-2d24474e6280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33425
47706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3342547706
Directory /workspace/42.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.3635941010
Short name T882
Test name
Test status
Simulation time 186506446 ps
CPU time 0.9 seconds
Started Aug 02 05:33:39 PM PDT 24
Finished Aug 02 05:33:40 PM PDT 24
Peak memory 207344 kb
Host smart-47e60a9a-38bc-444d-97e0-c2f553e7d588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36359
41010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.3635941010
Directory /workspace/42.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3530832450
Short name T2694
Test name
Test status
Simulation time 419736612 ps
CPU time 1.19 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:03 PM PDT 24
Peak memory 207324 kb
Host smart-2ccf70a3-97c4-430a-8b99-11ab91495f48
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3530832450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3530832450
Directory /workspace/42.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/42.usbdev_device_address.2148200199
Short name T1516
Test name
Test status
Simulation time 41000290224 ps
CPU time 73.05 seconds
Started Aug 02 05:33:43 PM PDT 24
Finished Aug 02 05:34:56 PM PDT 24
Peak memory 207708 kb
Host smart-f03e0c0e-203b-4497-afe1-6850724a62bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21482
00199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.2148200199
Directory /workspace/42.usbdev_device_address/latest


Test location /workspace/coverage/default/42.usbdev_device_timeout.4201447304
Short name T751
Test name
Test status
Simulation time 1143231929 ps
CPU time 25.61 seconds
Started Aug 02 05:33:52 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 207580 kb
Host smart-6a6d7dd6-f24d-4e20-ade1-9066e24a90c7
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201447304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_timeout.4201447304
Directory /workspace/42.usbdev_device_timeout/latest


Test location /workspace/coverage/default/42.usbdev_disable_endpoint.1182057325
Short name T1015
Test name
Test status
Simulation time 662380212 ps
CPU time 1.82 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:55 PM PDT 24
Peak memory 207400 kb
Host smart-50b3daaf-2712-4818-8231-27ead8d3ce33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11820
57325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.1182057325
Directory /workspace/42.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/42.usbdev_disconnected.3213321144
Short name T1894
Test name
Test status
Simulation time 149520097 ps
CPU time 0.83 seconds
Started Aug 02 05:33:44 PM PDT 24
Finished Aug 02 05:33:45 PM PDT 24
Peak memory 207176 kb
Host smart-9e07a648-a138-4338-823c-8571f6f523cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32133
21144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3213321144
Directory /workspace/42.usbdev_disconnected/latest


Test location /workspace/coverage/default/42.usbdev_enable.3324839792
Short name T2818
Test name
Test status
Simulation time 64752705 ps
CPU time 0.74 seconds
Started Aug 02 05:33:45 PM PDT 24
Finished Aug 02 05:33:46 PM PDT 24
Peak memory 207372 kb
Host smart-91e37913-da8f-41f3-b58b-aafbfc296e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33248
39792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.3324839792
Directory /workspace/42.usbdev_enable/latest


Test location /workspace/coverage/default/42.usbdev_endpoint_access.1025948553
Short name T601
Test name
Test status
Simulation time 1024025907 ps
CPU time 2.73 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207652 kb
Host smart-9a343741-82fa-4629-b8a2-747048a74ce2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10259
48553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.1025948553
Directory /workspace/42.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/42.usbdev_fifo_rst.2272086113
Short name T610
Test name
Test status
Simulation time 157647291 ps
CPU time 1.61 seconds
Started Aug 02 05:33:44 PM PDT 24
Finished Aug 02 05:33:46 PM PDT 24
Peak memory 207456 kb
Host smart-bb44bb4b-4e58-4a16-8362-05bbcaed2779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22720
86113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2272086113
Directory /workspace/42.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/42.usbdev_in_iso.950024241
Short name T2169
Test name
Test status
Simulation time 165314056 ps
CPU time 0.9 seconds
Started Aug 02 05:33:57 PM PDT 24
Finished Aug 02 05:33:58 PM PDT 24
Peak memory 207416 kb
Host smart-2141e4e1-234f-4b5e-bbe9-9f9ef3dd5206
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=950024241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.950024241
Directory /workspace/42.usbdev_in_iso/latest


Test location /workspace/coverage/default/42.usbdev_in_stall.1769334420
Short name T1679
Test name
Test status
Simulation time 153481036 ps
CPU time 0.84 seconds
Started Aug 02 05:33:52 PM PDT 24
Finished Aug 02 05:33:53 PM PDT 24
Peak memory 207376 kb
Host smart-65d08e6b-7f2d-4328-a1c7-0d5333ddd53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17693
34420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1769334420
Directory /workspace/42.usbdev_in_stall/latest


Test location /workspace/coverage/default/42.usbdev_in_trans.3034579033
Short name T32
Test name
Test status
Simulation time 211967388 ps
CPU time 0.92 seconds
Started Aug 02 05:34:09 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 207320 kb
Host smart-2c94b422-70be-43f2-a047-4fc16a3a7868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30345
79033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3034579033
Directory /workspace/42.usbdev_in_trans/latest


Test location /workspace/coverage/default/42.usbdev_invalid_sync.5109927
Short name T2470
Test name
Test status
Simulation time 4759008243 ps
CPU time 136.76 seconds
Started Aug 02 05:33:41 PM PDT 24
Finished Aug 02 05:35:58 PM PDT 24
Peak memory 218124 kb
Host smart-9b918985-2dc1-4288-aded-cea107498bfe
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=5109927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.5109927
Directory /workspace/42.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/42.usbdev_link_in_err.1289291676
Short name T1252
Test name
Test status
Simulation time 210865842 ps
CPU time 0.94 seconds
Started Aug 02 05:33:54 PM PDT 24
Finished Aug 02 05:34:00 PM PDT 24
Peak memory 207416 kb
Host smart-32dc9b71-231b-405f-87a3-dd7d3367ccb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12892
91676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.1289291676
Directory /workspace/42.usbdev_link_in_err/latest


Test location /workspace/coverage/default/42.usbdev_link_resume.3729544946
Short name T856
Test name
Test status
Simulation time 26862324481 ps
CPU time 37.67 seconds
Started Aug 02 05:33:49 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 207640 kb
Host smart-1fda63d2-85e1-4e04-9c13-9b09dc1523ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37295
44946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3729544946
Directory /workspace/42.usbdev_link_resume/latest


Test location /workspace/coverage/default/42.usbdev_link_suspend.874195809
Short name T2662
Test name
Test status
Simulation time 9289116800 ps
CPU time 11.28 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:34:04 PM PDT 24
Peak memory 207672 kb
Host smart-9aa61290-ef73-4b43-b676-9f621a799c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87419
5809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.874195809
Directory /workspace/42.usbdev_link_suspend/latest


Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.157638221
Short name T972
Test name
Test status
Simulation time 5398724127 ps
CPU time 150.81 seconds
Started Aug 02 05:34:04 PM PDT 24
Finished Aug 02 05:36:35 PM PDT 24
Peak memory 215892 kb
Host smart-a118ae93-b0d8-4676-9ffa-60eabce61918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15763
8221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.157638221
Directory /workspace/42.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3210002867
Short name T1554
Test name
Test status
Simulation time 3268423118 ps
CPU time 33.39 seconds
Started Aug 02 05:33:45 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 217372 kb
Host smart-4752b6ea-d217-4016-b3bf-30875d20c47f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3210002867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3210002867
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1309304060
Short name T1721
Test name
Test status
Simulation time 239330013 ps
CPU time 0.92 seconds
Started Aug 02 05:33:49 PM PDT 24
Finished Aug 02 05:33:50 PM PDT 24
Peak memory 207420 kb
Host smart-7667af8b-d2fb-47ef-9130-677a9b85aa84
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1309304060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1309304060
Directory /workspace/42.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.152201654
Short name T2053
Test name
Test status
Simulation time 198736184 ps
CPU time 0.96 seconds
Started Aug 02 05:33:47 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 207368 kb
Host smart-f4c902fb-8c95-4845-8079-95ae852ea993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15220
1654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.152201654
Directory /workspace/42.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.246390219
Short name T2279
Test name
Test status
Simulation time 2791788862 ps
CPU time 75.59 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:35:17 PM PDT 24
Peak memory 224064 kb
Host smart-08643257-3f9d-4bfb-b139-5415c9ad3fba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=246390219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.246390219
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.5171692
Short name T1670
Test name
Test status
Simulation time 160497693 ps
CPU time 0.86 seconds
Started Aug 02 05:33:54 PM PDT 24
Finished Aug 02 05:33:55 PM PDT 24
Peak memory 207392 kb
Host smart-de0f4414-581d-4b82-bc0e-17d95d445e9a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=5171692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.5171692
Directory /workspace/42.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4097324972
Short name T2281
Test name
Test status
Simulation time 147002878 ps
CPU time 0.8 seconds
Started Aug 02 05:33:57 PM PDT 24
Finished Aug 02 05:33:58 PM PDT 24
Peak memory 207208 kb
Host smart-80a1b81a-aecf-4620-931c-3312e3692aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40973
24972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4097324972
Directory /workspace/42.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_nak_trans.2448336282
Short name T153
Test name
Test status
Simulation time 191809503 ps
CPU time 0.89 seconds
Started Aug 02 05:33:58 PM PDT 24
Finished Aug 02 05:33:59 PM PDT 24
Peak memory 207404 kb
Host smart-65242dea-391e-41f8-bb31-07985bc46e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24483
36282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.2448336282
Directory /workspace/42.usbdev_nak_trans/latest


Test location /workspace/coverage/default/42.usbdev_out_iso.3432308931
Short name T128
Test name
Test status
Simulation time 166718303 ps
CPU time 0.88 seconds
Started Aug 02 05:33:56 PM PDT 24
Finished Aug 02 05:33:57 PM PDT 24
Peak memory 207400 kb
Host smart-f10ba72c-ce1b-469a-92e3-a0c88b30ed1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34323
08931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.3432308931
Directory /workspace/42.usbdev_out_iso/latest


Test location /workspace/coverage/default/42.usbdev_out_stall.270367072
Short name T2170
Test name
Test status
Simulation time 193522555 ps
CPU time 0.88 seconds
Started Aug 02 05:33:52 PM PDT 24
Finished Aug 02 05:33:53 PM PDT 24
Peak memory 207424 kb
Host smart-af0755fe-5f3b-44be-872b-380f3aaad55c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27036
7072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.270367072
Directory /workspace/42.usbdev_out_stall/latest


Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3025514326
Short name T1896
Test name
Test status
Simulation time 184905008 ps
CPU time 0.87 seconds
Started Aug 02 05:33:47 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 207360 kb
Host smart-c7018d21-dd5f-4f40-a159-c36080f4300f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30255
14326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3025514326
Directory /workspace/42.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/42.usbdev_pending_in_trans.1609507449
Short name T1451
Test name
Test status
Simulation time 146169070 ps
CPU time 0.79 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207416 kb
Host smart-0e81a9e5-59a2-43e6-9833-22cc5b008c04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16095
07449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.1609507449
Directory /workspace/42.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3229462501
Short name T3023
Test name
Test status
Simulation time 241682490 ps
CPU time 1.05 seconds
Started Aug 02 05:33:50 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 207380 kb
Host smart-74359cf1-bee8-4d59-bf53-b5eca8b59293
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3229462501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3229462501
Directory /workspace/42.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.3448675865
Short name T2709
Test name
Test status
Simulation time 149432305 ps
CPU time 0.85 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207328 kb
Host smart-e3dc2d11-86a1-4327-bec2-1a0d53e4d1d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34486
75865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.3448675865
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2491628554
Short name T2157
Test name
Test status
Simulation time 32777176 ps
CPU time 0.71 seconds
Started Aug 02 05:33:56 PM PDT 24
Finished Aug 02 05:33:56 PM PDT 24
Peak memory 207380 kb
Host smart-955e49c9-bba7-430f-bf42-1487a1f9de6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24916
28554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2491628554
Directory /workspace/42.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/42.usbdev_pkt_buffer.4091711954
Short name T1041
Test name
Test status
Simulation time 13168559667 ps
CPU time 34.58 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:36 PM PDT 24
Peak memory 220952 kb
Host smart-07ac891f-bcfb-42cb-b374-8720d5d7b467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40917
11954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.4091711954
Directory /workspace/42.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/42.usbdev_pkt_received.2609383850
Short name T999
Test name
Test status
Simulation time 193745176 ps
CPU time 0.98 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207392 kb
Host smart-5674f034-03cc-42e7-83e0-cf0ce43218b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26093
83850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.2609383850
Directory /workspace/42.usbdev_pkt_received/latest


Test location /workspace/coverage/default/42.usbdev_pkt_sent.3623946557
Short name T593
Test name
Test status
Simulation time 235322106 ps
CPU time 1.02 seconds
Started Aug 02 05:33:54 PM PDT 24
Finished Aug 02 05:33:55 PM PDT 24
Peak memory 207344 kb
Host smart-cd4c4dab-7549-4f9e-a19b-939ce7e7cf64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36239
46557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3623946557
Directory /workspace/42.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.449524279
Short name T797
Test name
Test status
Simulation time 187989545 ps
CPU time 0.88 seconds
Started Aug 02 05:34:00 PM PDT 24
Finished Aug 02 05:34:01 PM PDT 24
Peak memory 207420 kb
Host smart-5bb49e61-4d03-409d-87aa-bd2547527450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44952
4279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.449524279
Directory /workspace/42.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.2588917813
Short name T988
Test name
Test status
Simulation time 169130965 ps
CPU time 0.9 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207348 kb
Host smart-073ac442-07ab-4d52-a4f2-d9d3b215c0ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25889
17813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.2588917813
Directory /workspace/42.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1015473407
Short name T2349
Test name
Test status
Simulation time 209993331 ps
CPU time 0.89 seconds
Started Aug 02 05:33:54 PM PDT 24
Finished Aug 02 05:33:55 PM PDT 24
Peak memory 207428 kb
Host smart-1fe8dc57-121b-4b57-836d-3ef52d4a93a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10154
73407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1015473407
Directory /workspace/42.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/42.usbdev_rx_full.3699713298
Short name T2998
Test name
Test status
Simulation time 296337703 ps
CPU time 1.05 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:02 PM PDT 24
Peak memory 207336 kb
Host smart-835f9189-87cc-4f07-8b0d-472edb5d04c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36997
13298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_full.3699713298
Directory /workspace/42.usbdev_rx_full/latest


Test location /workspace/coverage/default/42.usbdev_setup_stage.477577236
Short name T617
Test name
Test status
Simulation time 148518522 ps
CPU time 0.81 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:54 PM PDT 24
Peak memory 207384 kb
Host smart-05b5413e-f8b8-47a7-89b1-b5887c0f31a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47757
7236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.477577236
Directory /workspace/42.usbdev_setup_stage/latest


Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.3484770604
Short name T2836
Test name
Test status
Simulation time 180541318 ps
CPU time 0.86 seconds
Started Aug 02 05:33:56 PM PDT 24
Finished Aug 02 05:33:57 PM PDT 24
Peak memory 207380 kb
Host smart-57bbdb17-bb8b-45ea-bb5d-27f9b6e27ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34847
70604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.3484770604
Directory /workspace/42.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/42.usbdev_smoke.2477330455
Short name T653
Test name
Test status
Simulation time 217618571 ps
CPU time 1 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:33:52 PM PDT 24
Peak memory 207416 kb
Host smart-f82522c3-e764-4133-a01c-fc8b9e0c1335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24773
30455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2477330455
Directory /workspace/42.usbdev_smoke/latest


Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1611255512
Short name T2636
Test name
Test status
Simulation time 3551570856 ps
CPU time 27.54 seconds
Started Aug 02 05:33:51 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 224036 kb
Host smart-14a965c7-ad18-4296-a621-d34052b2be71
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1611255512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1611255512
Directory /workspace/42.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.683650297
Short name T2066
Test name
Test status
Simulation time 175062872 ps
CPU time 0.93 seconds
Started Aug 02 05:34:06 PM PDT 24
Finished Aug 02 05:34:07 PM PDT 24
Peak memory 207364 kb
Host smart-129e0279-46e7-4012-8bbb-d4fe5d7f545b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68365
0297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.683650297
Directory /workspace/42.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/42.usbdev_stall_trans.2166714302
Short name T2590
Test name
Test status
Simulation time 163918287 ps
CPU time 0.92 seconds
Started Aug 02 05:33:56 PM PDT 24
Finished Aug 02 05:33:57 PM PDT 24
Peak memory 207336 kb
Host smart-8230ffcc-1458-4a87-93c0-65a8df4e2a47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21667
14302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2166714302
Directory /workspace/42.usbdev_stall_trans/latest


Test location /workspace/coverage/default/42.usbdev_stream_len_max.512774311
Short name T2726
Test name
Test status
Simulation time 198685473 ps
CPU time 0.96 seconds
Started Aug 02 05:34:07 PM PDT 24
Finished Aug 02 05:34:08 PM PDT 24
Peak memory 207300 kb
Host smart-e35afc2c-2264-4ac5-b2e5-81fd5c0e11d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51277
4311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.512774311
Directory /workspace/42.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/42.usbdev_streaming_out.203762994
Short name T1438
Test name
Test status
Simulation time 2163663849 ps
CPU time 62.91 seconds
Started Aug 02 05:33:57 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 215860 kb
Host smart-328e85f8-5153-4ae5-be30-d2cf5fadccd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20376
2994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.203762994
Directory /workspace/42.usbdev_streaming_out/latest


Test location /workspace/coverage/default/42.usbdev_timeout_missing_host_handshake.3078351088
Short name T641
Test name
Test status
Simulation time 2489408569 ps
CPU time 22.07 seconds
Started Aug 02 05:33:47 PM PDT 24
Finished Aug 02 05:34:09 PM PDT 24
Peak memory 207688 kb
Host smart-d26f2626-7019-4970-91fb-a66b43f59f18
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078351088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_timeout_missing_hos
t_handshake.3078351088
Directory /workspace/42.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/43.usbdev_alert_test.1989137424
Short name T2638
Test name
Test status
Simulation time 51369747 ps
CPU time 0.7 seconds
Started Aug 02 05:33:47 PM PDT 24
Finished Aug 02 05:33:48 PM PDT 24
Peak memory 207480 kb
Host smart-54b3c520-6e12-48ef-9006-93bb96e3918c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1989137424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1989137424
Directory /workspace/43.usbdev_alert_test/latest


Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.3088120676
Short name T689
Test name
Test status
Simulation time 13442926870 ps
CPU time 17.62 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:34:11 PM PDT 24
Peak memory 215840 kb
Host smart-37a028b7-6420-4d41-a12c-bbf3ff1bc955
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088120676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.3088120676
Directory /workspace/43.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.2825100615
Short name T2218
Test name
Test status
Simulation time 24204047043 ps
CPU time 28.84 seconds
Started Aug 02 05:34:06 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 215856 kb
Host smart-05be49c4-691e-47ee-a12b-48efc2533bac
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825100615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_a
on_wake_resume.2825100615
Directory /workspace/43.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/43.usbdev_av_buffer.1183640639
Short name T1361
Test name
Test status
Simulation time 157443650 ps
CPU time 0.87 seconds
Started Aug 02 05:34:00 PM PDT 24
Finished Aug 02 05:34:01 PM PDT 24
Peak memory 207416 kb
Host smart-004fe2c5-35c5-4560-be1a-c48a51aaa6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11836
40639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1183640639
Directory /workspace/43.usbdev_av_buffer/latest


Test location /workspace/coverage/default/43.usbdev_bitstuff_err.963296594
Short name T1031
Test name
Test status
Simulation time 158362532 ps
CPU time 0.83 seconds
Started Aug 02 05:33:52 PM PDT 24
Finished Aug 02 05:33:53 PM PDT 24
Peak memory 207308 kb
Host smart-7f2d84c3-4b95-437d-a953-ce97c9eeedf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96329
6594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.963296594
Directory /workspace/43.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3684216573
Short name T643
Test name
Test status
Simulation time 468596017 ps
CPU time 1.63 seconds
Started Aug 02 05:34:04 PM PDT 24
Finished Aug 02 05:34:06 PM PDT 24
Peak memory 207408 kb
Host smart-c88e9e0e-9279-401b-82a5-900ba9c973fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36842
16573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3684216573
Directory /workspace/43.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1490633341
Short name T1517
Test name
Test status
Simulation time 675631675 ps
CPU time 1.78 seconds
Started Aug 02 05:33:49 PM PDT 24
Finished Aug 02 05:33:51 PM PDT 24
Peak memory 207468 kb
Host smart-c808d957-e1d0-40a1-b1a7-67e54b3650f6
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1490633341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1490633341
Directory /workspace/43.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/43.usbdev_device_address.664442160
Short name T2286
Test name
Test status
Simulation time 60730387200 ps
CPU time 102.3 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:35:54 PM PDT 24
Peak memory 207624 kb
Host smart-ef72418b-f815-405b-8a23-a4054eadfb93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66444
2160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.664442160
Directory /workspace/43.usbdev_device_address/latest


Test location /workspace/coverage/default/43.usbdev_device_timeout.756934567
Short name T1328
Test name
Test status
Simulation time 625328680 ps
CPU time 5.01 seconds
Started Aug 02 05:33:54 PM PDT 24
Finished Aug 02 05:34:00 PM PDT 24
Peak memory 207624 kb
Host smart-7460a0a2-b853-4148-adba-23536f451754
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756934567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_timeout.756934567
Directory /workspace/43.usbdev_device_timeout/latest


Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3224363952
Short name T356
Test name
Test status
Simulation time 573732927 ps
CPU time 1.64 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:33:55 PM PDT 24
Peak memory 207372 kb
Host smart-5a976906-760c-432a-9eb4-d98ca05ddeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32243
63952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3224363952
Directory /workspace/43.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/43.usbdev_disconnected.2725706666
Short name T1292
Test name
Test status
Simulation time 162171771 ps
CPU time 0.85 seconds
Started Aug 02 05:33:52 PM PDT 24
Finished Aug 02 05:33:53 PM PDT 24
Peak memory 207332 kb
Host smart-941e87c6-da5a-4cb3-b7fd-cf032223a304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27257
06666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.2725706666
Directory /workspace/43.usbdev_disconnected/latest


Test location /workspace/coverage/default/43.usbdev_enable.1699826761
Short name T1202
Test name
Test status
Simulation time 48492805 ps
CPU time 0.69 seconds
Started Aug 02 05:34:07 PM PDT 24
Finished Aug 02 05:34:08 PM PDT 24
Peak memory 207388 kb
Host smart-f8158e66-b33e-4f3f-8840-2110685b503d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16998
26761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1699826761
Directory /workspace/43.usbdev_enable/latest


Test location /workspace/coverage/default/43.usbdev_endpoint_access.744228817
Short name T2855
Test name
Test status
Simulation time 855087216 ps
CPU time 2.24 seconds
Started Aug 02 05:34:05 PM PDT 24
Finished Aug 02 05:34:07 PM PDT 24
Peak memory 207640 kb
Host smart-a69879e9-f0a0-4768-9d93-c865f6fb97bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74422
8817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.744228817
Directory /workspace/43.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/43.usbdev_endpoint_types.408070567
Short name T2271
Test name
Test status
Simulation time 353052807 ps
CPU time 1.11 seconds
Started Aug 02 05:34:05 PM PDT 24
Finished Aug 02 05:34:06 PM PDT 24
Peak memory 207392 kb
Host smart-7b0f7726-2cf8-481e-a5c8-9bb3684b7c0c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=408070567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_types.408070567
Directory /workspace/43.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/43.usbdev_fifo_rst.995612238
Short name T1347
Test name
Test status
Simulation time 307426146 ps
CPU time 1.97 seconds
Started Aug 02 05:34:06 PM PDT 24
Finished Aug 02 05:34:15 PM PDT 24
Peak memory 207528 kb
Host smart-e180040a-4531-4f29-962c-4a1c601b515d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99561
2238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.995612238
Directory /workspace/43.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/43.usbdev_in_iso.3340255366
Short name T1525
Test name
Test status
Simulation time 175631800 ps
CPU time 0.96 seconds
Started Aug 02 05:34:00 PM PDT 24
Finished Aug 02 05:34:01 PM PDT 24
Peak memory 207172 kb
Host smart-812cf4b0-d1a5-4c4c-846b-9efbfbe19c4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3340255366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.3340255366
Directory /workspace/43.usbdev_in_iso/latest


Test location /workspace/coverage/default/43.usbdev_in_stall.405333652
Short name T518
Test name
Test status
Simulation time 169822276 ps
CPU time 0.83 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:02 PM PDT 24
Peak memory 207284 kb
Host smart-72a859b0-7a51-4fdd-840c-a10b2eb67c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40533
3652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.405333652
Directory /workspace/43.usbdev_in_stall/latest


Test location /workspace/coverage/default/43.usbdev_in_trans.345734190
Short name T2021
Test name
Test status
Simulation time 257099064 ps
CPU time 1.07 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:02 PM PDT 24
Peak memory 207352 kb
Host smart-a010507b-f25c-44ab-ae19-fccb57e2316c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34573
4190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.345734190
Directory /workspace/43.usbdev_in_trans/latest


Test location /workspace/coverage/default/43.usbdev_invalid_sync.2909876815
Short name T35
Test name
Test status
Simulation time 3549676075 ps
CPU time 34.7 seconds
Started Aug 02 05:34:12 PM PDT 24
Finished Aug 02 05:34:47 PM PDT 24
Peak memory 218252 kb
Host smart-a14f6929-3c59-4c33-89da-50b4ddace293
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2909876815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.2909876815
Directory /workspace/43.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/43.usbdev_iso_retraction.4156108704
Short name T1349
Test name
Test status
Simulation time 13787910179 ps
CPU time 84.9 seconds
Started Aug 02 05:33:58 PM PDT 24
Finished Aug 02 05:35:23 PM PDT 24
Peak memory 207676 kb
Host smart-941e559a-9ad4-4660-899e-53762f8776b6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4156108704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.4156108704
Directory /workspace/43.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/43.usbdev_link_in_err.3951225783
Short name T2263
Test name
Test status
Simulation time 229959332 ps
CPU time 0.98 seconds
Started Aug 02 05:33:57 PM PDT 24
Finished Aug 02 05:33:58 PM PDT 24
Peak memory 207388 kb
Host smart-b3386f6c-f0b8-4612-8050-dfa245869a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39512
25783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3951225783
Directory /workspace/43.usbdev_link_in_err/latest


Test location /workspace/coverage/default/43.usbdev_link_resume.4264719004
Short name T116
Test name
Test status
Simulation time 28494190169 ps
CPU time 39.96 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:34:51 PM PDT 24
Peak memory 207600 kb
Host smart-c7623848-be7a-448d-8c03-ef8d1d3394f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42647
19004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.4264719004
Directory /workspace/43.usbdev_link_resume/latest


Test location /workspace/coverage/default/43.usbdev_link_suspend.2604717968
Short name T2101
Test name
Test status
Simulation time 3528485159 ps
CPU time 5.1 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:06 PM PDT 24
Peak memory 215864 kb
Host smart-7e1fddd4-27c2-408a-a4cd-122134b329dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26047
17968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2604717968
Directory /workspace/43.usbdev_link_suspend/latest


Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.3559894279
Short name T1555
Test name
Test status
Simulation time 2177682503 ps
CPU time 15.17 seconds
Started Aug 02 05:34:02 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 217900 kb
Host smart-414c8feb-cc7d-4226-99e6-cd9b223368a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35598
94279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.3559894279
Directory /workspace/43.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.2759700137
Short name T623
Test name
Test status
Simulation time 1595594610 ps
CPU time 11.56 seconds
Started Aug 02 05:34:00 PM PDT 24
Finished Aug 02 05:34:12 PM PDT 24
Peak memory 207324 kb
Host smart-4eab12de-8a39-493b-9ca4-1addb4c9f178
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2759700137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.2759700137
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.1490624197
Short name T2551
Test name
Test status
Simulation time 235069713 ps
CPU time 0.95 seconds
Started Aug 02 05:33:56 PM PDT 24
Finished Aug 02 05:33:57 PM PDT 24
Peak memory 207340 kb
Host smart-24a10f4c-4641-4e6a-bc17-ab07ef158e57
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1490624197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.1490624197
Directory /workspace/43.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3612168886
Short name T1190
Test name
Test status
Simulation time 189637932 ps
CPU time 0.9 seconds
Started Aug 02 05:34:07 PM PDT 24
Finished Aug 02 05:34:08 PM PDT 24
Peak memory 207364 kb
Host smart-3f25072c-d6c1-43ce-9449-57fe388b08d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36121
68886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3612168886
Directory /workspace/43.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3450276841
Short name T1509
Test name
Test status
Simulation time 2185212559 ps
CPU time 17.15 seconds
Started Aug 02 05:33:53 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 207692 kb
Host smart-83e119e6-a379-413a-88b2-bf7b4ce71b02
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3450276841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3450276841
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.3346391423
Short name T2647
Test name
Test status
Simulation time 160550121 ps
CPU time 0.86 seconds
Started Aug 02 05:34:04 PM PDT 24
Finished Aug 02 05:34:05 PM PDT 24
Peak memory 207384 kb
Host smart-0e0b8d80-b89d-4685-a1b6-3b51a12b1205
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3346391423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.3346391423
Directory /workspace/43.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.610395662
Short name T1828
Test name
Test status
Simulation time 160287550 ps
CPU time 0.87 seconds
Started Aug 02 05:34:15 PM PDT 24
Finished Aug 02 05:34:16 PM PDT 24
Peak memory 207344 kb
Host smart-108d8257-e09e-48ed-b3f0-ae6b185e9c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61039
5662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.610395662
Directory /workspace/43.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_nak_trans.3695711621
Short name T132
Test name
Test status
Simulation time 210535546 ps
CPU time 0.97 seconds
Started Aug 02 05:34:05 PM PDT 24
Finished Aug 02 05:34:06 PM PDT 24
Peak memory 207408 kb
Host smart-5d246257-ef3a-427a-86a8-8c75af98b3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36957
11621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3695711621
Directory /workspace/43.usbdev_nak_trans/latest


Test location /workspace/coverage/default/43.usbdev_out_iso.2355817387
Short name T2888
Test name
Test status
Simulation time 142872684 ps
CPU time 0.89 seconds
Started Aug 02 05:34:02 PM PDT 24
Finished Aug 02 05:34:04 PM PDT 24
Peak memory 207404 kb
Host smart-7f7f8db3-35cd-4248-b049-154bcd5f2ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23558
17387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2355817387
Directory /workspace/43.usbdev_out_iso/latest


Test location /workspace/coverage/default/43.usbdev_out_stall.328696082
Short name T2705
Test name
Test status
Simulation time 179740061 ps
CPU time 0.87 seconds
Started Aug 02 05:33:55 PM PDT 24
Finished Aug 02 05:33:56 PM PDT 24
Peak memory 207320 kb
Host smart-8ec7d863-6f41-4dbc-b1b7-a41900a22a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32869
6082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.328696082
Directory /workspace/43.usbdev_out_stall/latest


Test location /workspace/coverage/default/43.usbdev_out_trans_nak.61022526
Short name T2703
Test name
Test status
Simulation time 174437706 ps
CPU time 0.84 seconds
Started Aug 02 05:34:06 PM PDT 24
Finished Aug 02 05:34:07 PM PDT 24
Peak memory 207408 kb
Host smart-6e292dd3-e071-47b9-9a65-36a7ce16cdac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61022
526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.61022526
Directory /workspace/43.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/43.usbdev_pending_in_trans.2906763897
Short name T2731
Test name
Test status
Simulation time 152374012 ps
CPU time 0.81 seconds
Started Aug 02 05:34:07 PM PDT 24
Finished Aug 02 05:34:08 PM PDT 24
Peak memory 207380 kb
Host smart-13a0b0de-9ffd-4824-acb3-7eb98fda3537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29067
63897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.2906763897
Directory /workspace/43.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.646613312
Short name T1739
Test name
Test status
Simulation time 193625521 ps
CPU time 0.96 seconds
Started Aug 02 05:34:15 PM PDT 24
Finished Aug 02 05:34:16 PM PDT 24
Peak memory 207360 kb
Host smart-e9527b0e-e181-4a92-9464-ede76970cc34
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=646613312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.646613312
Directory /workspace/43.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2595264303
Short name T2360
Test name
Test status
Simulation time 159448019 ps
CPU time 0.84 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:17 PM PDT 24
Peak memory 207340 kb
Host smart-8b078d7b-7b8b-4ac6-9df5-20a45c7d9622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25952
64303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2595264303
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.2170551902
Short name T2634
Test name
Test status
Simulation time 37818566 ps
CPU time 0.66 seconds
Started Aug 02 05:33:59 PM PDT 24
Finished Aug 02 05:34:00 PM PDT 24
Peak memory 207340 kb
Host smart-2f27ff76-4f82-421a-9fd9-49de34d2cb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21705
51902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.2170551902
Directory /workspace/43.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2891910954
Short name T2454
Test name
Test status
Simulation time 17223885187 ps
CPU time 40.6 seconds
Started Aug 02 05:34:06 PM PDT 24
Finished Aug 02 05:34:47 PM PDT 24
Peak memory 215788 kb
Host smart-852c041f-edb9-4b98-8d37-d9b77cf9a7ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28919
10954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2891910954
Directory /workspace/43.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/43.usbdev_pkt_received.3749715992
Short name T2983
Test name
Test status
Simulation time 180140981 ps
CPU time 0.88 seconds
Started Aug 02 05:34:05 PM PDT 24
Finished Aug 02 05:34:06 PM PDT 24
Peak memory 207400 kb
Host smart-bcc5cc46-e1cd-40b4-a02f-b0bfc5f28807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37497
15992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.3749715992
Directory /workspace/43.usbdev_pkt_received/latest


Test location /workspace/coverage/default/43.usbdev_pkt_sent.1207900957
Short name T910
Test name
Test status
Simulation time 222703072 ps
CPU time 0.99 seconds
Started Aug 02 05:34:03 PM PDT 24
Finished Aug 02 05:34:04 PM PDT 24
Peak memory 207396 kb
Host smart-5441363a-6f1d-4e6f-92d7-4450e07fd43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12079
00957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1207900957
Directory /workspace/43.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1929840774
Short name T1480
Test name
Test status
Simulation time 154419717 ps
CPU time 0.82 seconds
Started Aug 02 05:33:58 PM PDT 24
Finished Aug 02 05:33:59 PM PDT 24
Peak memory 207320 kb
Host smart-6859560a-b6fe-4d34-91de-fb08680b52e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19298
40774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1929840774
Directory /workspace/43.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.940539911
Short name T2027
Test name
Test status
Simulation time 191932671 ps
CPU time 0.9 seconds
Started Aug 02 05:34:08 PM PDT 24
Finished Aug 02 05:34:09 PM PDT 24
Peak memory 207380 kb
Host smart-f5690558-31ce-4d25-88bd-26864505f73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94053
9911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.940539911
Directory /workspace/43.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/43.usbdev_rx_crc_err.142627660
Short name T1655
Test name
Test status
Simulation time 140157319 ps
CPU time 0.79 seconds
Started Aug 02 05:34:03 PM PDT 24
Finished Aug 02 05:34:04 PM PDT 24
Peak memory 207344 kb
Host smart-1a177c29-1751-424b-8578-a402dc8b9e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14262
7660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.142627660
Directory /workspace/43.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/43.usbdev_rx_full.408005197
Short name T1034
Test name
Test status
Simulation time 255925186 ps
CPU time 1.11 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:02 PM PDT 24
Peak memory 207392 kb
Host smart-046f3b99-65bc-4a9f-ab27-c9ae7ac9e687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40800
5197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_full.408005197
Directory /workspace/43.usbdev_rx_full/latest


Test location /workspace/coverage/default/43.usbdev_setup_stage.2985191038
Short name T2114
Test name
Test status
Simulation time 158243591 ps
CPU time 0.86 seconds
Started Aug 02 05:34:09 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 207320 kb
Host smart-f5f49376-d16a-417f-bbd4-b21164369da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29851
91038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.2985191038
Directory /workspace/43.usbdev_setup_stage/latest


Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1292310395
Short name T940
Test name
Test status
Simulation time 183007836 ps
CPU time 0.98 seconds
Started Aug 02 05:34:04 PM PDT 24
Finished Aug 02 05:34:05 PM PDT 24
Peak memory 207412 kb
Host smart-72421cab-9b9d-4121-bb71-07f45ecde6bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12923
10395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1292310395
Directory /workspace/43.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/43.usbdev_smoke.4051239811
Short name T556
Test name
Test status
Simulation time 255552501 ps
CPU time 1.05 seconds
Started Aug 02 05:34:13 PM PDT 24
Finished Aug 02 05:34:14 PM PDT 24
Peak memory 207300 kb
Host smart-9ec5f9f1-72ee-47ad-97f3-55e92c75429d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40512
39811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.4051239811
Directory /workspace/43.usbdev_smoke/latest


Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.250749911
Short name T1314
Test name
Test status
Simulation time 2483139193 ps
CPU time 24.84 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:34:36 PM PDT 24
Peak memory 224104 kb
Host smart-7a60563e-7ee8-4c1c-993f-4eef0e1cfd4a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=250749911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.250749911
Directory /workspace/43.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1717412276
Short name T960
Test name
Test status
Simulation time 187659677 ps
CPU time 0.92 seconds
Started Aug 02 05:34:03 PM PDT 24
Finished Aug 02 05:34:04 PM PDT 24
Peak memory 207412 kb
Host smart-8a1dc3d8-c9a1-41ba-9bc0-f5df436b2dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17174
12276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1717412276
Directory /workspace/43.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/43.usbdev_stall_trans.1751143388
Short name T533
Test name
Test status
Simulation time 209833378 ps
CPU time 1 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:02 PM PDT 24
Peak memory 207388 kb
Host smart-ef17b549-eded-472a-b467-a28e3a90448a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17511
43388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1751143388
Directory /workspace/43.usbdev_stall_trans/latest


Test location /workspace/coverage/default/43.usbdev_stream_len_max.4023740880
Short name T2128
Test name
Test status
Simulation time 1401579439 ps
CPU time 3.48 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:05 PM PDT 24
Peak memory 207592 kb
Host smart-ef39191a-1fba-4c0a-a41c-9656bbf58daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40237
40880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.4023740880
Directory /workspace/43.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/43.usbdev_streaming_out.2282205782
Short name T1905
Test name
Test status
Simulation time 2894417219 ps
CPU time 20.69 seconds
Started Aug 02 05:33:55 PM PDT 24
Finished Aug 02 05:34:16 PM PDT 24
Peak memory 215852 kb
Host smart-9faa65c7-6b52-4c24-9567-0993b5078bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22822
05782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2282205782
Directory /workspace/43.usbdev_streaming_out/latest


Test location /workspace/coverage/default/43.usbdev_timeout_missing_host_handshake.1769571428
Short name T946
Test name
Test status
Simulation time 2510610312 ps
CPU time 21.43 seconds
Started Aug 02 05:33:52 PM PDT 24
Finished Aug 02 05:34:14 PM PDT 24
Peak memory 207676 kb
Host smart-02332285-8f02-47e2-b68a-31966d97fbfe
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769571428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_timeout_missing_hos
t_handshake.1769571428
Directory /workspace/43.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/44.usbdev_alert_test.3841610486
Short name T2345
Test name
Test status
Simulation time 42436812 ps
CPU time 0.66 seconds
Started Aug 02 05:34:09 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 207552 kb
Host smart-2389895f-abca-4ca9-be1e-63e140af1646
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3841610486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3841610486
Directory /workspace/44.usbdev_alert_test/latest


Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.1588881362
Short name T675
Test name
Test status
Simulation time 6743835432 ps
CPU time 8.38 seconds
Started Aug 02 05:34:03 PM PDT 24
Finished Aug 02 05:34:12 PM PDT 24
Peak memory 215932 kb
Host smart-c20be2fe-d9a1-4c13-a589-ee2771cadc79
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588881362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_disconnect.1588881362
Directory /workspace/44.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.550946219
Short name T3040
Test name
Test status
Simulation time 14397449958 ps
CPU time 15.04 seconds
Started Aug 02 05:34:04 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 215884 kb
Host smart-09689106-2e53-4045-9fd5-9ec9990ce746
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=550946219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.550946219
Directory /workspace/44.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.2752096503
Short name T1948
Test name
Test status
Simulation time 30933911011 ps
CPU time 35.49 seconds
Started Aug 02 05:33:58 PM PDT 24
Finished Aug 02 05:34:33 PM PDT 24
Peak memory 207616 kb
Host smart-792ca3f8-18b3-4e21-9f07-8f44c8bcf979
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752096503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_a
on_wake_resume.2752096503
Directory /workspace/44.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/44.usbdev_av_buffer.1715711427
Short name T2402
Test name
Test status
Simulation time 151329393 ps
CPU time 0.87 seconds
Started Aug 02 05:34:01 PM PDT 24
Finished Aug 02 05:34:03 PM PDT 24
Peak memory 207388 kb
Host smart-d8bd2100-6c20-4267-99e9-f8d88dd23c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17157
11427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.1715711427
Directory /workspace/44.usbdev_av_buffer/latest


Test location /workspace/coverage/default/44.usbdev_bitstuff_err.942252323
Short name T1450
Test name
Test status
Simulation time 165756497 ps
CPU time 0.88 seconds
Started Aug 02 05:34:00 PM PDT 24
Finished Aug 02 05:34:01 PM PDT 24
Peak memory 207348 kb
Host smart-c9891482-5cac-4db7-8ec3-e256dceea42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94225
2323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.942252323
Directory /workspace/44.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2437977015
Short name T1488
Test name
Test status
Simulation time 529716309 ps
CPU time 1.77 seconds
Started Aug 02 05:33:56 PM PDT 24
Finished Aug 02 05:33:57 PM PDT 24
Peak memory 207348 kb
Host smart-c53d2475-4467-4c0d-8fd6-73e707b1ef20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24379
77015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2437977015
Directory /workspace/44.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1851551203
Short name T3094
Test name
Test status
Simulation time 799167527 ps
CPU time 2.41 seconds
Started Aug 02 05:34:00 PM PDT 24
Finished Aug 02 05:34:03 PM PDT 24
Peak memory 207612 kb
Host smart-f98eadd8-fc6a-4034-9f08-85ced72a7ca5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1851551203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1851551203
Directory /workspace/44.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/44.usbdev_device_timeout.1929108882
Short name T824
Test name
Test status
Simulation time 1430113439 ps
CPU time 32.72 seconds
Started Aug 02 05:34:05 PM PDT 24
Finished Aug 02 05:34:38 PM PDT 24
Peak memory 207424 kb
Host smart-b946b0d9-8561-4a17-b8cb-896887676204
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929108882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_timeout.1929108882
Directory /workspace/44.usbdev_device_timeout/latest


Test location /workspace/coverage/default/44.usbdev_disable_endpoint.644581037
Short name T780
Test name
Test status
Simulation time 721646895 ps
CPU time 1.86 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 207296 kb
Host smart-ed250669-0c50-4e90-a2c1-dc4f86575028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64458
1037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.644581037
Directory /workspace/44.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/44.usbdev_disconnected.3548957904
Short name T1191
Test name
Test status
Simulation time 137116421 ps
CPU time 0.85 seconds
Started Aug 02 05:34:12 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 207340 kb
Host smart-f58014eb-7488-481f-aca4-59d5e7920f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35489
57904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3548957904
Directory /workspace/44.usbdev_disconnected/latest


Test location /workspace/coverage/default/44.usbdev_enable.2427643172
Short name T1230
Test name
Test status
Simulation time 34359365 ps
CPU time 0.68 seconds
Started Aug 02 05:34:12 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 207348 kb
Host smart-58d433ef-e649-4e02-932d-2723f6230dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24276
43172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2427643172
Directory /workspace/44.usbdev_enable/latest


Test location /workspace/coverage/default/44.usbdev_endpoint_access.2169360327
Short name T888
Test name
Test status
Simulation time 724314751 ps
CPU time 2.08 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 207568 kb
Host smart-6bc606c7-5be0-4608-93c0-16c4be63f604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21693
60327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2169360327
Directory /workspace/44.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/44.usbdev_endpoint_types.703127067
Short name T470
Test name
Test status
Simulation time 193468071 ps
CPU time 0.97 seconds
Started Aug 02 05:34:08 PM PDT 24
Finished Aug 02 05:34:09 PM PDT 24
Peak memory 207364 kb
Host smart-ef3b4571-72b7-49e5-b21d-d5ed4aaa0bd5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=703127067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_types.703127067
Directory /workspace/44.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/44.usbdev_fifo_rst.2237112350
Short name T1594
Test name
Test status
Simulation time 238657006 ps
CPU time 2.08 seconds
Started Aug 02 05:34:10 PM PDT 24
Finished Aug 02 05:34:12 PM PDT 24
Peak memory 207536 kb
Host smart-9b33d108-d441-449c-90c3-c9b03cb5d40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371
12350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2237112350
Directory /workspace/44.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/44.usbdev_in_iso.527118767
Short name T2885
Test name
Test status
Simulation time 238576614 ps
CPU time 1.2 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 215712 kb
Host smart-013ddd80-14c3-4e29-8dce-be2a806b1f30
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=527118767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.527118767
Directory /workspace/44.usbdev_in_iso/latest


Test location /workspace/coverage/default/44.usbdev_in_stall.223350798
Short name T2348
Test name
Test status
Simulation time 155468057 ps
CPU time 0.85 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:34:12 PM PDT 24
Peak memory 207356 kb
Host smart-b6b09adf-a74e-46b3-bd74-15b1d39d3318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22335
0798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.223350798
Directory /workspace/44.usbdev_in_stall/latest


Test location /workspace/coverage/default/44.usbdev_in_trans.1984430181
Short name T1732
Test name
Test status
Simulation time 176094907 ps
CPU time 0.91 seconds
Started Aug 02 05:34:09 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 207404 kb
Host smart-466c87dd-d80f-4677-973a-43b1f71d9deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19844
30181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.1984430181
Directory /workspace/44.usbdev_in_trans/latest


Test location /workspace/coverage/default/44.usbdev_invalid_sync.823910611
Short name T2241
Test name
Test status
Simulation time 3861010461 ps
CPU time 39.21 seconds
Started Aug 02 05:34:04 PM PDT 24
Finished Aug 02 05:34:43 PM PDT 24
Peak memory 224040 kb
Host smart-28d1fdfd-0629-47ad-942b-4dd19b638390
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=823910611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.823910611
Directory /workspace/44.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/44.usbdev_iso_retraction.3553162637
Short name T584
Test name
Test status
Simulation time 14132139915 ps
CPU time 90.68 seconds
Started Aug 02 05:34:32 PM PDT 24
Finished Aug 02 05:36:03 PM PDT 24
Peak memory 207660 kb
Host smart-97d4d0fd-b164-4fa0-93a1-367df4cc85bb
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3553162637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3553162637
Directory /workspace/44.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/44.usbdev_link_in_err.2340975347
Short name T838
Test name
Test status
Simulation time 231269987 ps
CPU time 0.94 seconds
Started Aug 02 05:33:58 PM PDT 24
Finished Aug 02 05:33:59 PM PDT 24
Peak memory 207376 kb
Host smart-762d4f35-2e20-4421-8c27-c112fb873757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
75347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2340975347
Directory /workspace/44.usbdev_link_in_err/latest


Test location /workspace/coverage/default/44.usbdev_link_resume.2310769081
Short name T1376
Test name
Test status
Simulation time 13701560227 ps
CPU time 21.34 seconds
Started Aug 02 05:34:18 PM PDT 24
Finished Aug 02 05:34:40 PM PDT 24
Peak memory 207580 kb
Host smart-ef86c8da-9820-4322-accb-668adf64540f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23107
69081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.2310769081
Directory /workspace/44.usbdev_link_resume/latest


Test location /workspace/coverage/default/44.usbdev_link_suspend.968927305
Short name T2004
Test name
Test status
Simulation time 5827004577 ps
CPU time 7.55 seconds
Started Aug 02 05:34:19 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 216060 kb
Host smart-890cf225-cc30-4f7e-bb5b-1a38ab0d1bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96892
7305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.968927305
Directory /workspace/44.usbdev_link_suspend/latest


Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2069105940
Short name T1912
Test name
Test status
Simulation time 5568639193 ps
CPU time 38.99 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:55 PM PDT 24
Peak memory 224056 kb
Host smart-c578eb53-16ad-4fce-b148-bdef4564cd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20691
05940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2069105940
Directory /workspace/44.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1017144794
Short name T1120
Test name
Test status
Simulation time 3310861849 ps
CPU time 24.3 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:34:52 PM PDT 24
Peak memory 215852 kb
Host smart-2d6e54d8-b31b-4762-bddf-f5a574d917ee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1017144794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1017144794
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.3047204120
Short name T2358
Test name
Test status
Simulation time 297516390 ps
CPU time 1.02 seconds
Started Aug 02 05:34:06 PM PDT 24
Finished Aug 02 05:34:07 PM PDT 24
Peak memory 207392 kb
Host smart-11cb8dab-5ae7-4223-b9f0-3c26ac8be115
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3047204120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.3047204120
Directory /workspace/44.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.671819320
Short name T1113
Test name
Test status
Simulation time 197976785 ps
CPU time 0.97 seconds
Started Aug 02 05:34:10 PM PDT 24
Finished Aug 02 05:34:11 PM PDT 24
Peak memory 207328 kb
Host smart-08e4f3e8-bbfd-481d-847a-2dd1db5ca200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67181
9320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.671819320
Directory /workspace/44.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.2907100376
Short name T736
Test name
Test status
Simulation time 1533782076 ps
CPU time 11.75 seconds
Started Aug 02 05:34:03 PM PDT 24
Finished Aug 02 05:34:15 PM PDT 24
Peak memory 217272 kb
Host smart-2b55ee3a-5a1d-4850-880f-1b9bdad60091
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2907100376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.2907100376
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1274015367
Short name T1456
Test name
Test status
Simulation time 189576881 ps
CPU time 0.88 seconds
Started Aug 02 05:34:09 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 207408 kb
Host smart-988e8ae0-7793-4b22-a2b0-667f4a8ceece
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1274015367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1274015367
Directory /workspace/44.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.3065595030
Short name T798
Test name
Test status
Simulation time 152405401 ps
CPU time 0.89 seconds
Started Aug 02 05:34:04 PM PDT 24
Finished Aug 02 05:34:05 PM PDT 24
Peak memory 207408 kb
Host smart-af705b73-79f0-4bfd-ba29-0d543fd2aa13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30655
95030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.3065595030
Directory /workspace/44.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_out_iso.2164234311
Short name T1631
Test name
Test status
Simulation time 178288736 ps
CPU time 0.87 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:34:12 PM PDT 24
Peak memory 207388 kb
Host smart-456dc051-2bea-457b-8ac5-a82d8e3db1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21642
34311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2164234311
Directory /workspace/44.usbdev_out_iso/latest


Test location /workspace/coverage/default/44.usbdev_out_stall.4020499404
Short name T783
Test name
Test status
Simulation time 193124866 ps
CPU time 0.86 seconds
Started Aug 02 05:34:10 PM PDT 24
Finished Aug 02 05:34:11 PM PDT 24
Peak memory 207420 kb
Host smart-91430ec2-5b3c-40cd-af52-b740243687c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40204
99404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.4020499404
Directory /workspace/44.usbdev_out_stall/latest


Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3359010666
Short name T2388
Test name
Test status
Simulation time 203983643 ps
CPU time 0.85 seconds
Started Aug 02 05:34:12 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 207444 kb
Host smart-6c882535-8d07-417c-9353-1948003826e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33590
10666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3359010666
Directory /workspace/44.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/44.usbdev_pending_in_trans.509060533
Short name T2245
Test name
Test status
Simulation time 166739599 ps
CPU time 0.85 seconds
Started Aug 02 05:34:10 PM PDT 24
Finished Aug 02 05:34:11 PM PDT 24
Peak memory 207432 kb
Host smart-06dd8a6f-5db1-4910-866f-cc8bf845b7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50906
0533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.509060533
Directory /workspace/44.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3040390565
Short name T2362
Test name
Test status
Simulation time 217715964 ps
CPU time 1 seconds
Started Aug 02 05:34:12 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 207388 kb
Host smart-818ad62a-740a-42d9-9913-2b117f576495
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3040390565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3040390565
Directory /workspace/44.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.2511449534
Short name T528
Test name
Test status
Simulation time 207364625 ps
CPU time 0.84 seconds
Started Aug 02 05:34:29 PM PDT 24
Finished Aug 02 05:34:31 PM PDT 24
Peak memory 207176 kb
Host smart-cb37423d-7c8e-4f2b-8ca6-708cd84b8a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25114
49534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.2511449534
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2247694251
Short name T1812
Test name
Test status
Simulation time 33154059 ps
CPU time 0.66 seconds
Started Aug 02 05:34:15 PM PDT 24
Finished Aug 02 05:34:16 PM PDT 24
Peak memory 207328 kb
Host smart-da8d0d98-8695-410d-a38a-5ced85c0507c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22476
94251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2247694251
Directory /workspace/44.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3166003108
Short name T1365
Test name
Test status
Simulation time 10566009520 ps
CPU time 28.06 seconds
Started Aug 02 05:34:06 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 224100 kb
Host smart-3a7253aa-9e24-4711-9f6a-ed59add44720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31660
03108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3166003108
Directory /workspace/44.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/44.usbdev_pkt_received.2422349815
Short name T2941
Test name
Test status
Simulation time 179394427 ps
CPU time 0.91 seconds
Started Aug 02 05:34:52 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 207360 kb
Host smart-66eddf27-0f68-4f21-8ff6-70e872792889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24223
49815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2422349815
Directory /workspace/44.usbdev_pkt_received/latest


Test location /workspace/coverage/default/44.usbdev_pkt_sent.2020945459
Short name T1258
Test name
Test status
Simulation time 207795477 ps
CPU time 0.95 seconds
Started Aug 02 05:34:33 PM PDT 24
Finished Aug 02 05:34:34 PM PDT 24
Peak memory 207396 kb
Host smart-586aa8b9-f2e4-4a86-9505-3e9713b54da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20209
45459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.2020945459
Directory /workspace/44.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.2870301397
Short name T1890
Test name
Test status
Simulation time 193611991 ps
CPU time 0.86 seconds
Started Aug 02 05:34:05 PM PDT 24
Finished Aug 02 05:34:06 PM PDT 24
Peak memory 207368 kb
Host smart-d44515a7-6dd0-48d1-8f42-9db80e01cf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28703
01397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.2870301397
Directory /workspace/44.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1684572932
Short name T1741
Test name
Test status
Simulation time 177845812 ps
CPU time 0.92 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:28 PM PDT 24
Peak memory 207392 kb
Host smart-f0f6eeea-fc2f-4334-8c91-04661ddffec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16845
72932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1684572932
Directory /workspace/44.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/44.usbdev_rx_crc_err.1202327324
Short name T2376
Test name
Test status
Simulation time 166179360 ps
CPU time 0.88 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 207416 kb
Host smart-060fa1fb-b452-4ed4-bf81-9525535fbb76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12023
27324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.1202327324
Directory /workspace/44.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/44.usbdev_rx_full.2870100860
Short name T1004
Test name
Test status
Simulation time 292313239 ps
CPU time 1.13 seconds
Started Aug 02 05:34:12 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 207424 kb
Host smart-1f851ea7-c55a-4ce2-a94d-db3851f0436a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28701
00860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_full.2870100860
Directory /workspace/44.usbdev_rx_full/latest


Test location /workspace/coverage/default/44.usbdev_setup_stage.1032894533
Short name T1701
Test name
Test status
Simulation time 163034171 ps
CPU time 0.85 seconds
Started Aug 02 05:34:13 PM PDT 24
Finished Aug 02 05:34:14 PM PDT 24
Peak memory 207308 kb
Host smart-2617cf08-c2a0-4bf1-b040-8ad9dea60f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10328
94533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1032894533
Directory /workspace/44.usbdev_setup_stage/latest


Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.1372644304
Short name T2239
Test name
Test status
Simulation time 169833969 ps
CPU time 0.87 seconds
Started Aug 02 05:34:31 PM PDT 24
Finished Aug 02 05:34:32 PM PDT 24
Peak memory 207312 kb
Host smart-d4ecfbe1-eca0-4137-807f-53d0cc17c809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13726
44304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.1372644304
Directory /workspace/44.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/44.usbdev_smoke.865872980
Short name T1145
Test name
Test status
Simulation time 235249966 ps
CPU time 0.98 seconds
Started Aug 02 05:34:09 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 207416 kb
Host smart-1d16fd07-f18c-433b-a9a1-05617d09941a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86587
2980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.865872980
Directory /workspace/44.usbdev_smoke/latest


Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1660355418
Short name T683
Test name
Test status
Simulation time 2345290284 ps
CPU time 23.26 seconds
Started Aug 02 05:34:12 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 224016 kb
Host smart-b52a8816-a648-4c2b-941f-845d4aa39e25
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1660355418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1660355418
Directory /workspace/44.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.4091134829
Short name T2457
Test name
Test status
Simulation time 179039348 ps
CPU time 0.88 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 207364 kb
Host smart-48bd8ddc-155f-4278-81f2-033300f4e25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40911
34829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.4091134829
Directory /workspace/44.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/44.usbdev_stall_trans.1544933636
Short name T2601
Test name
Test status
Simulation time 198676234 ps
CPU time 0.98 seconds
Started Aug 02 05:34:04 PM PDT 24
Finished Aug 02 05:34:05 PM PDT 24
Peak memory 207360 kb
Host smart-d975a23c-a46d-43af-8cb2-7b8429034220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15449
33636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1544933636
Directory /workspace/44.usbdev_stall_trans/latest


Test location /workspace/coverage/default/44.usbdev_stream_len_max.2999961691
Short name T1646
Test name
Test status
Simulation time 1022900411 ps
CPU time 2.39 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 207504 kb
Host smart-c9315d1b-707b-4d2d-a001-3fd181a93af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29999
61691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2999961691
Directory /workspace/44.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/44.usbdev_streaming_out.4178227191
Short name T2684
Test name
Test status
Simulation time 3274841439 ps
CPU time 24.16 seconds
Started Aug 02 05:34:30 PM PDT 24
Finished Aug 02 05:34:54 PM PDT 24
Peak memory 215908 kb
Host smart-1be0f1cf-ad91-4226-905e-e16c1e6166af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41782
27191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.4178227191
Directory /workspace/44.usbdev_streaming_out/latest


Test location /workspace/coverage/default/44.usbdev_timeout_missing_host_handshake.1664963471
Short name T227
Test name
Test status
Simulation time 1010451655 ps
CPU time 21.8 seconds
Started Aug 02 05:34:08 PM PDT 24
Finished Aug 02 05:34:30 PM PDT 24
Peak memory 207532 kb
Host smart-e42900db-a21b-443d-955c-1e7a40c437b2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664963471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_timeout_missing_hos
t_handshake.1664963471
Directory /workspace/44.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/45.usbdev_alert_test.893696794
Short name T589
Test name
Test status
Simulation time 109347707 ps
CPU time 0.74 seconds
Started Aug 02 05:34:14 PM PDT 24
Finished Aug 02 05:34:15 PM PDT 24
Peak memory 207416 kb
Host smart-371ac00f-135d-4e08-9cf6-89d9677f77cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=893696794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.893696794
Directory /workspace/45.usbdev_alert_test/latest


Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1207104436
Short name T1310
Test name
Test status
Simulation time 5363539483 ps
CPU time 8.35 seconds
Started Aug 02 05:34:04 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 215848 kb
Host smart-b3b5a814-c29b-4140-9cfc-6a56bdad4ad6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207104436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_disconnect.1207104436
Directory /workspace/45.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.1754804433
Short name T846
Test name
Test status
Simulation time 16320968747 ps
CPU time 19.8 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:37 PM PDT 24
Peak memory 215876 kb
Host smart-87d4a406-cc9b-457d-a4c2-3560897866ef
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754804433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.1754804433
Directory /workspace/45.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1229172225
Short name T1257
Test name
Test status
Simulation time 24509271272 ps
CPU time 33.51 seconds
Started Aug 02 05:34:32 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 215876 kb
Host smart-52666928-304f-4dbe-9173-34753488c4b6
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229172225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_a
on_wake_resume.1229172225
Directory /workspace/45.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/45.usbdev_av_buffer.10093649
Short name T1908
Test name
Test status
Simulation time 178865406 ps
CPU time 0.9 seconds
Started Aug 02 05:34:06 PM PDT 24
Finished Aug 02 05:34:07 PM PDT 24
Peak memory 207384 kb
Host smart-e99221b0-a00a-4e69-b1dc-4a13e2919aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.10093649
Directory /workspace/45.usbdev_av_buffer/latest


Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1559733850
Short name T1337
Test name
Test status
Simulation time 172578951 ps
CPU time 0.83 seconds
Started Aug 02 05:34:22 PM PDT 24
Finished Aug 02 05:34:23 PM PDT 24
Peak memory 207320 kb
Host smart-696f7fa6-faac-4b5f-9d55-2b8cb7244f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15597
33850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1559733850
Directory /workspace/45.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2967786336
Short name T2278
Test name
Test status
Simulation time 282838540 ps
CPU time 1.17 seconds
Started Aug 02 05:33:59 PM PDT 24
Finished Aug 02 05:34:00 PM PDT 24
Peak memory 207420 kb
Host smart-41d7ffa7-42c3-4cab-bfe5-a876f3248839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29677
86336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2967786336
Directory /workspace/45.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3817493323
Short name T1776
Test name
Test status
Simulation time 915524494 ps
CPU time 2.48 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:29 PM PDT 24
Peak memory 207600 kb
Host smart-b070d84f-e3ce-472d-a04c-9b7666b46804
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3817493323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3817493323
Directory /workspace/45.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/45.usbdev_device_address.3896257281
Short name T1674
Test name
Test status
Simulation time 33049729603 ps
CPU time 50.4 seconds
Started Aug 02 05:34:10 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 207676 kb
Host smart-3abd924b-3dc9-4bcb-a14f-b76ec8d0e619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38962
57281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3896257281
Directory /workspace/45.usbdev_device_address/latest


Test location /workspace/coverage/default/45.usbdev_device_timeout.1548010592
Short name T1589
Test name
Test status
Simulation time 4345751113 ps
CPU time 28.24 seconds
Started Aug 02 05:34:10 PM PDT 24
Finished Aug 02 05:34:38 PM PDT 24
Peak memory 207720 kb
Host smart-9b128545-3b56-4bc1-957a-d98582240d4b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548010592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_timeout.1548010592
Directory /workspace/45.usbdev_device_timeout/latest


Test location /workspace/coverage/default/45.usbdev_disable_endpoint.1989030916
Short name T2720
Test name
Test status
Simulation time 532630879 ps
CPU time 1.52 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 207396 kb
Host smart-7c5805c3-ce6d-4f8b-8c9f-c443e24da6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19890
30916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.1989030916
Directory /workspace/45.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/45.usbdev_disconnected.3572672346
Short name T2000
Test name
Test status
Simulation time 198410488 ps
CPU time 0.86 seconds
Started Aug 02 05:34:24 PM PDT 24
Finished Aug 02 05:34:25 PM PDT 24
Peak memory 207396 kb
Host smart-29860687-cc7f-4655-912d-6a255f2198c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35726
72346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.3572672346
Directory /workspace/45.usbdev_disconnected/latest


Test location /workspace/coverage/default/45.usbdev_enable.3404029089
Short name T2676
Test name
Test status
Simulation time 61400596 ps
CPU time 0.75 seconds
Started Aug 02 05:34:30 PM PDT 24
Finished Aug 02 05:34:31 PM PDT 24
Peak memory 207380 kb
Host smart-c6074e08-33aa-4044-ac44-06aec74f531b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34040
29089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3404029089
Directory /workspace/45.usbdev_enable/latest


Test location /workspace/coverage/default/45.usbdev_endpoint_access.4284387942
Short name T949
Test name
Test status
Simulation time 745644333 ps
CPU time 2.05 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:34:13 PM PDT 24
Peak memory 207608 kb
Host smart-35e1a152-a88a-4657-a5ac-67c1db6bcd9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42843
87942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.4284387942
Directory /workspace/45.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/45.usbdev_endpoint_types.1190562137
Short name T464
Test name
Test status
Simulation time 209483775 ps
CPU time 1.05 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:48 PM PDT 24
Peak memory 207364 kb
Host smart-dd753017-8346-449c-9f63-ef19fe45b52e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1190562137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_types.1190562137
Directory /workspace/45.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/45.usbdev_fifo_rst.2047906983
Short name T1559
Test name
Test status
Simulation time 262797006 ps
CPU time 2.2 seconds
Started Aug 02 05:34:08 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 207620 kb
Host smart-bd644ff8-8caf-437b-9a3c-344561a5aba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20479
06983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2047906983
Directory /workspace/45.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/45.usbdev_in_iso.1701937300
Short name T2964
Test name
Test status
Simulation time 257438749 ps
CPU time 1.16 seconds
Started Aug 02 05:34:12 PM PDT 24
Finished Aug 02 05:34:14 PM PDT 24
Peak memory 215808 kb
Host smart-3ab17956-d174-4d1b-8bd1-86b92747b69a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1701937300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.1701937300
Directory /workspace/45.usbdev_in_iso/latest


Test location /workspace/coverage/default/45.usbdev_in_stall.1407802891
Short name T532
Test name
Test status
Simulation time 161168928 ps
CPU time 0.83 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 207268 kb
Host smart-3e5d5c55-5311-43d2-94d6-d602a0dde9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14078
02891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1407802891
Directory /workspace/45.usbdev_in_stall/latest


Test location /workspace/coverage/default/45.usbdev_in_trans.1989522146
Short name T1795
Test name
Test status
Simulation time 221069549 ps
CPU time 0.93 seconds
Started Aug 02 05:34:09 PM PDT 24
Finished Aug 02 05:34:10 PM PDT 24
Peak memory 207432 kb
Host smart-50f70d8b-5ccd-4231-b24f-dbe78ab9ca4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19895
22146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1989522146
Directory /workspace/45.usbdev_in_trans/latest


Test location /workspace/coverage/default/45.usbdev_invalid_sync.2924644940
Short name T1727
Test name
Test status
Simulation time 2599832076 ps
CPU time 71.67 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:35:23 PM PDT 24
Peak memory 215892 kb
Host smart-cf2e600d-ef1d-49ff-abdb-342acc6b6671
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2924644940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.2924644940
Directory /workspace/45.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/45.usbdev_iso_retraction.3813726970
Short name T2394
Test name
Test status
Simulation time 13027703659 ps
CPU time 89.2 seconds
Started Aug 02 05:34:13 PM PDT 24
Finished Aug 02 05:35:42 PM PDT 24
Peak memory 207560 kb
Host smart-e23e7a6d-5a59-4894-a120-82fff17d1cc5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3813726970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.3813726970
Directory /workspace/45.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/45.usbdev_link_in_err.2635258451
Short name T2948
Test name
Test status
Simulation time 182026381 ps
CPU time 0.94 seconds
Started Aug 02 05:34:30 PM PDT 24
Finished Aug 02 05:34:32 PM PDT 24
Peak memory 207404 kb
Host smart-79ec691a-0887-4083-8571-3072bf420343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26352
58451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2635258451
Directory /workspace/45.usbdev_link_in_err/latest


Test location /workspace/coverage/default/45.usbdev_link_resume.1396651670
Short name T2187
Test name
Test status
Simulation time 30270781206 ps
CPU time 40.15 seconds
Started Aug 02 05:34:25 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207668 kb
Host smart-dca82626-eeb9-4c07-9cfc-c42801acb548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13966
51670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1396651670
Directory /workspace/45.usbdev_link_resume/latest


Test location /workspace/coverage/default/45.usbdev_link_suspend.1380750162
Short name T1587
Test name
Test status
Simulation time 11350904936 ps
CPU time 13.8 seconds
Started Aug 02 05:34:30 PM PDT 24
Finished Aug 02 05:34:44 PM PDT 24
Peak memory 207700 kb
Host smart-7000300c-4f44-40aa-b90c-58cb2aed194a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13807
50162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.1380750162
Directory /workspace/45.usbdev_link_suspend/latest


Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.491165671
Short name T1173
Test name
Test status
Simulation time 5928756743 ps
CPU time 57.75 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:35:25 PM PDT 24
Peak memory 218572 kb
Host smart-49e761f1-6df1-461b-9068-f3cbe5d7fe29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49116
5671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.491165671
Directory /workspace/45.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3412237072
Short name T1668
Test name
Test status
Simulation time 3719937584 ps
CPU time 26.82 seconds
Started Aug 02 05:34:09 PM PDT 24
Finished Aug 02 05:34:36 PM PDT 24
Peak memory 215944 kb
Host smart-83bbb89a-1813-4260-b8c3-484e2d0d1f8b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3412237072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3412237072
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3462045593
Short name T1083
Test name
Test status
Simulation time 270725912 ps
CPU time 1.05 seconds
Started Aug 02 05:34:31 PM PDT 24
Finished Aug 02 05:34:32 PM PDT 24
Peak memory 207324 kb
Host smart-7dfcaf6c-739e-4148-826d-a01f74fea1df
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3462045593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3462045593
Directory /workspace/45.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.296517652
Short name T531
Test name
Test status
Simulation time 188827830 ps
CPU time 0.88 seconds
Started Aug 02 05:34:33 PM PDT 24
Finished Aug 02 05:34:33 PM PDT 24
Peak memory 207388 kb
Host smart-49e9ed9a-2b18-4079-8399-88667e24e558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29651
7652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.296517652
Directory /workspace/45.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2321223735
Short name T2908
Test name
Test status
Simulation time 2102340188 ps
CPU time 21.64 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:34:33 PM PDT 24
Peak memory 217052 kb
Host smart-ed07edbf-6102-47fd-bccc-50bae4f5c92a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2321223735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2321223735
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.2056972110
Short name T2753
Test name
Test status
Simulation time 152163758 ps
CPU time 0.81 seconds
Started Aug 02 05:34:10 PM PDT 24
Finished Aug 02 05:34:11 PM PDT 24
Peak memory 207388 kb
Host smart-929115aa-785a-4da7-b923-b82c52f0a7a5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2056972110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.2056972110
Directory /workspace/45.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2849373992
Short name T765
Test name
Test status
Simulation time 178931102 ps
CPU time 0.86 seconds
Started Aug 02 05:34:07 PM PDT 24
Finished Aug 02 05:34:08 PM PDT 24
Peak memory 207404 kb
Host smart-ae88d3a9-23db-4b4d-bfd5-7444bceed765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28493
73992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2849373992
Directory /workspace/45.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_nak_trans.3826565178
Short name T2300
Test name
Test status
Simulation time 216140512 ps
CPU time 0.99 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:34:29 PM PDT 24
Peak memory 207316 kb
Host smart-69e475ea-f9c6-4822-a15f-afb3fb7d4cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38265
65178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.3826565178
Directory /workspace/45.usbdev_nak_trans/latest


Test location /workspace/coverage/default/45.usbdev_out_iso.3984635836
Short name T935
Test name
Test status
Simulation time 213010128 ps
CPU time 0.94 seconds
Started Aug 02 05:34:28 PM PDT 24
Finished Aug 02 05:34:29 PM PDT 24
Peak memory 207400 kb
Host smart-c4a50434-492f-4d86-a13c-e3cdb0cd29af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39846
35836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.3984635836
Directory /workspace/45.usbdev_out_iso/latest


Test location /workspace/coverage/default/45.usbdev_out_stall.2851826283
Short name T3042
Test name
Test status
Simulation time 170569268 ps
CPU time 0.84 seconds
Started Aug 02 05:34:24 PM PDT 24
Finished Aug 02 05:34:25 PM PDT 24
Peak memory 207400 kb
Host smart-5ef5692b-d0fc-4f6b-857e-5e5622e9c84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28518
26283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2851826283
Directory /workspace/45.usbdev_out_stall/latest


Test location /workspace/coverage/default/45.usbdev_out_trans_nak.1096354659
Short name T2756
Test name
Test status
Simulation time 147216639 ps
CPU time 0.81 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 207388 kb
Host smart-c120d9d4-7c27-4fc4-a7f0-65d77a48be68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10963
54659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.1096354659
Directory /workspace/45.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3721358125
Short name T941
Test name
Test status
Simulation time 149157183 ps
CPU time 0.83 seconds
Started Aug 02 05:34:31 PM PDT 24
Finished Aug 02 05:34:32 PM PDT 24
Peak memory 207344 kb
Host smart-fba0989a-64f3-4ad9-8821-b82292902bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37213
58125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3721358125
Directory /workspace/45.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.2891608926
Short name T1614
Test name
Test status
Simulation time 245380311 ps
CPU time 0.99 seconds
Started Aug 02 05:34:33 PM PDT 24
Finished Aug 02 05:34:34 PM PDT 24
Peak memory 207384 kb
Host smart-eeca5e9c-e10e-43bf-b116-d6e594517cb2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2891608926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2891608926
Directory /workspace/45.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.3325799195
Short name T1549
Test name
Test status
Simulation time 173650896 ps
CPU time 0.84 seconds
Started Aug 02 05:34:28 PM PDT 24
Finished Aug 02 05:34:28 PM PDT 24
Peak memory 207368 kb
Host smart-d5a4dd26-5734-4b5e-9435-2c6e0a12a9b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33257
99195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.3325799195
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3640635191
Short name T1923
Test name
Test status
Simulation time 43562157 ps
CPU time 0.67 seconds
Started Aug 02 05:34:20 PM PDT 24
Finished Aug 02 05:34:20 PM PDT 24
Peak memory 207356 kb
Host smart-34fc2538-e731-4c8e-915d-5929f1e1f22d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36406
35191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3640635191
Directory /workspace/45.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/45.usbdev_pkt_buffer.1258211677
Short name T1545
Test name
Test status
Simulation time 16242209808 ps
CPU time 41.3 seconds
Started Aug 02 05:34:24 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 215896 kb
Host smart-23dfadb6-fb70-47d3-83d0-4f27771cbf94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12582
11677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.1258211677
Directory /workspace/45.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/45.usbdev_pkt_received.3869150978
Short name T2706
Test name
Test status
Simulation time 183668092 ps
CPU time 0.94 seconds
Started Aug 02 05:34:23 PM PDT 24
Finished Aug 02 05:34:24 PM PDT 24
Peak memory 207408 kb
Host smart-fe3e9e93-6baa-457e-940e-768ad5d3eb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38691
50978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3869150978
Directory /workspace/45.usbdev_pkt_received/latest


Test location /workspace/coverage/default/45.usbdev_pkt_sent.3819745516
Short name T2811
Test name
Test status
Simulation time 249774061 ps
CPU time 0.94 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:34:12 PM PDT 24
Peak memory 207428 kb
Host smart-20f1e942-0f24-4dba-8c6b-11b6b8a0625f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38197
45516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.3819745516
Directory /workspace/45.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.1866109659
Short name T1497
Test name
Test status
Simulation time 219976457 ps
CPU time 0.91 seconds
Started Aug 02 05:34:45 PM PDT 24
Finished Aug 02 05:34:46 PM PDT 24
Peak memory 207356 kb
Host smart-df560b47-3c3b-419f-994f-12526d34c684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18661
09659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.1866109659
Directory /workspace/45.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.2320426130
Short name T2488
Test name
Test status
Simulation time 176481436 ps
CPU time 0.9 seconds
Started Aug 02 05:34:29 PM PDT 24
Finished Aug 02 05:34:30 PM PDT 24
Peak memory 207416 kb
Host smart-b67650bb-2ea7-4407-a9ae-fe842fe35d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23204
26130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.2320426130
Directory /workspace/45.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/45.usbdev_rx_crc_err.2604458092
Short name T2208
Test name
Test status
Simulation time 140731855 ps
CPU time 0.81 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 207344 kb
Host smart-7cb4b554-05fd-4e7d-aee8-b4ebe91ee7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26044
58092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.2604458092
Directory /workspace/45.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/45.usbdev_rx_full.2425135335
Short name T2942
Test name
Test status
Simulation time 296776897 ps
CPU time 1.14 seconds
Started Aug 02 05:34:30 PM PDT 24
Finished Aug 02 05:34:31 PM PDT 24
Peak memory 207416 kb
Host smart-df40a411-075d-47e1-8fc9-4d1d59160522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24251
35335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_full.2425135335
Directory /workspace/45.usbdev_rx_full/latest


Test location /workspace/coverage/default/45.usbdev_setup_stage.2192963775
Short name T2058
Test name
Test status
Simulation time 149993728 ps
CPU time 0.8 seconds
Started Aug 02 05:34:39 PM PDT 24
Finished Aug 02 05:34:40 PM PDT 24
Peak memory 207344 kb
Host smart-5f52d39e-0801-48b2-b02c-bf0a00fa0e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21929
63775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2192963775
Directory /workspace/45.usbdev_setup_stage/latest


Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.3342624960
Short name T1783
Test name
Test status
Simulation time 212908115 ps
CPU time 0.85 seconds
Started Aug 02 05:34:34 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 207416 kb
Host smart-85f4b5cd-bc55-494f-a8c2-081052b3adee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33426
24960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.3342624960
Directory /workspace/45.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/45.usbdev_smoke.83228036
Short name T1439
Test name
Test status
Simulation time 191987280 ps
CPU time 0.93 seconds
Started Aug 02 05:34:28 PM PDT 24
Finished Aug 02 05:34:29 PM PDT 24
Peak memory 207428 kb
Host smart-3c01be3c-a4b4-479b-ae7c-bcf88d66ba5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83228
036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.83228036
Directory /workspace/45.usbdev_smoke/latest


Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.3690313133
Short name T733
Test name
Test status
Simulation time 3508180399 ps
CPU time 97.32 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:36:04 PM PDT 24
Peak memory 217472 kb
Host smart-eca1ca02-c5ad-4343-a5e6-d6d1c2f06980
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3690313133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.3690313133
Directory /workspace/45.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3783045231
Short name T2645
Test name
Test status
Simulation time 182970463 ps
CPU time 0.94 seconds
Started Aug 02 05:34:18 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 207412 kb
Host smart-0c79aafd-c2ff-4285-ad5b-cfd3cabb1c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37830
45231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3783045231
Directory /workspace/45.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/45.usbdev_stall_trans.1008773574
Short name T2796
Test name
Test status
Simulation time 150194162 ps
CPU time 0.88 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:17 PM PDT 24
Peak memory 207384 kb
Host smart-3448c021-6149-4b2b-a8e6-0a449ef6aee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10087
73574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.1008773574
Directory /workspace/45.usbdev_stall_trans/latest


Test location /workspace/coverage/default/45.usbdev_stream_len_max.2192374867
Short name T1700
Test name
Test status
Simulation time 681991548 ps
CPU time 1.93 seconds
Started Aug 02 05:34:18 PM PDT 24
Finished Aug 02 05:34:20 PM PDT 24
Peak memory 207368 kb
Host smart-80cad32c-e7a4-4ed0-9d6f-69e3c4ff919c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
74867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.2192374867
Directory /workspace/45.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/45.usbdev_streaming_out.3826701802
Short name T1822
Test name
Test status
Simulation time 4001502480 ps
CPU time 40.52 seconds
Started Aug 02 05:34:12 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 215848 kb
Host smart-2620ea67-35ad-4d42-a44c-aea7ee22f1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38267
01802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.3826701802
Directory /workspace/45.usbdev_streaming_out/latest


Test location /workspace/coverage/default/45.usbdev_timeout_missing_host_handshake.3164230895
Short name T1757
Test name
Test status
Simulation time 3580652570 ps
CPU time 23.72 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:40 PM PDT 24
Peak memory 207684 kb
Host smart-514d8f73-0d48-4558-aaa2-2031adafe266
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164230895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_timeout_missing_hos
t_handshake.3164230895
Directory /workspace/45.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/46.usbdev_alert_test.1454043528
Short name T1008
Test name
Test status
Simulation time 36962121 ps
CPU time 0.64 seconds
Started Aug 02 05:34:41 PM PDT 24
Finished Aug 02 05:34:41 PM PDT 24
Peak memory 207468 kb
Host smart-2b8eac0c-9802-411d-8d44-5a2d45973650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1454043528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1454043528
Directory /workspace/46.usbdev_alert_test/latest


Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1721414682
Short name T867
Test name
Test status
Simulation time 14539306721 ps
CPU time 18.25 seconds
Started Aug 02 05:34:24 PM PDT 24
Finished Aug 02 05:34:42 PM PDT 24
Peak memory 215856 kb
Host smart-d129e5d8-7e92-4c88-b8c7-5042ef3c6909
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721414682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1721414682
Directory /workspace/46.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3098744551
Short name T2873
Test name
Test status
Simulation time 26187301646 ps
CPU time 31.96 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 215844 kb
Host smart-d4babc76-fd39-4344-925b-75ccd1b9388d
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098744551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_a
on_wake_resume.3098744551
Directory /workspace/46.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/46.usbdev_av_buffer.3053600028
Short name T1271
Test name
Test status
Simulation time 199943257 ps
CPU time 0.95 seconds
Started Aug 02 05:34:11 PM PDT 24
Finished Aug 02 05:34:12 PM PDT 24
Peak memory 207348 kb
Host smart-2b52acf3-373e-4e05-8003-3b3637e508d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30536
00028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3053600028
Directory /workspace/46.usbdev_av_buffer/latest


Test location /workspace/coverage/default/46.usbdev_bitstuff_err.1966222709
Short name T2450
Test name
Test status
Simulation time 164506299 ps
CPU time 0.83 seconds
Started Aug 02 05:34:32 PM PDT 24
Finished Aug 02 05:34:33 PM PDT 24
Peak memory 207336 kb
Host smart-4ccc6dcb-abf8-4013-8e34-86a0398e9e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19662
22709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.1966222709
Directory /workspace/46.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.3390079219
Short name T3058
Test name
Test status
Simulation time 322691032 ps
CPU time 1.18 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 207412 kb
Host smart-3b45c21a-5185-4f2e-a651-0e6bc707b6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33900
79219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.3390079219
Directory /workspace/46.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1539348905
Short name T1356
Test name
Test status
Simulation time 462175164 ps
CPU time 1.49 seconds
Started Aug 02 05:34:28 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 207344 kb
Host smart-cf8b8a67-76ba-4660-b18e-0b89afe2086c
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1539348905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1539348905
Directory /workspace/46.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/46.usbdev_device_address.1832281690
Short name T1926
Test name
Test status
Simulation time 53875515742 ps
CPU time 82.58 seconds
Started Aug 02 05:34:18 PM PDT 24
Finished Aug 02 05:35:41 PM PDT 24
Peak memory 207744 kb
Host smart-8ff60b0b-7bf9-4eef-aff8-d82cb5be27e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18322
81690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.1832281690
Directory /workspace/46.usbdev_device_address/latest


Test location /workspace/coverage/default/46.usbdev_device_timeout.2277491819
Short name T1371
Test name
Test status
Simulation time 3636187166 ps
CPU time 22.99 seconds
Started Aug 02 05:34:36 PM PDT 24
Finished Aug 02 05:34:59 PM PDT 24
Peak memory 207628 kb
Host smart-d4692d42-b3fe-490e-afbc-d06358c162d9
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277491819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_timeout.2277491819
Directory /workspace/46.usbdev_device_timeout/latest


Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1441266334
Short name T2933
Test name
Test status
Simulation time 958775857 ps
CPU time 2.09 seconds
Started Aug 02 05:34:23 PM PDT 24
Finished Aug 02 05:34:25 PM PDT 24
Peak memory 207388 kb
Host smart-0b16c6fa-b3c0-4256-a2b3-37e0bab44633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14412
66334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1441266334
Directory /workspace/46.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/46.usbdev_disconnected.831739558
Short name T2842
Test name
Test status
Simulation time 152137141 ps
CPU time 0.9 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:34:28 PM PDT 24
Peak memory 207268 kb
Host smart-81d9b506-d4dc-4aa1-b34e-c9fbce9b3511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83173
9558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.831739558
Directory /workspace/46.usbdev_disconnected/latest


Test location /workspace/coverage/default/46.usbdev_enable.445913384
Short name T1710
Test name
Test status
Simulation time 32464084 ps
CPU time 0.71 seconds
Started Aug 02 05:34:20 PM PDT 24
Finished Aug 02 05:34:20 PM PDT 24
Peak memory 207336 kb
Host smart-12622009-2cb0-4cac-9cc7-4215c82f3d4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44591
3384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.445913384
Directory /workspace/46.usbdev_enable/latest


Test location /workspace/coverage/default/46.usbdev_endpoint_access.2692266996
Short name T802
Test name
Test status
Simulation time 671477512 ps
CPU time 1.94 seconds
Started Aug 02 05:34:36 PM PDT 24
Finished Aug 02 05:34:38 PM PDT 24
Peak memory 207544 kb
Host smart-16667b05-670a-4548-833c-6613d4cdd657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26922
66996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.2692266996
Directory /workspace/46.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/46.usbdev_endpoint_types.2899197723
Short name T383
Test name
Test status
Simulation time 440996873 ps
CPU time 1.47 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:23 PM PDT 24
Peak memory 207408 kb
Host smart-fb88dee6-184f-4e7d-9327-22a1ea66ea98
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2899197723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_types.2899197723
Directory /workspace/46.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/46.usbdev_fifo_rst.1476722933
Short name T1152
Test name
Test status
Simulation time 151358047 ps
CPU time 1.28 seconds
Started Aug 02 05:34:33 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 207484 kb
Host smart-665a1403-af28-43d8-853f-fd81744e58f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14767
22933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.1476722933
Directory /workspace/46.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/46.usbdev_in_iso.511377388
Short name T1266
Test name
Test status
Simulation time 219248080 ps
CPU time 1.1 seconds
Started Aug 02 05:34:23 PM PDT 24
Finished Aug 02 05:34:24 PM PDT 24
Peak memory 207576 kb
Host smart-26630b04-8a12-4e5e-858d-a99ce17f1e91
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=511377388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.511377388
Directory /workspace/46.usbdev_in_iso/latest


Test location /workspace/coverage/default/46.usbdev_in_stall.2755148839
Short name T97
Test name
Test status
Simulation time 202449900 ps
CPU time 0.88 seconds
Started Aug 02 05:34:41 PM PDT 24
Finished Aug 02 05:34:42 PM PDT 24
Peak memory 207296 kb
Host smart-356c6ca8-fb7f-423c-b585-217a749607e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27551
48839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2755148839
Directory /workspace/46.usbdev_in_stall/latest


Test location /workspace/coverage/default/46.usbdev_in_trans.915268285
Short name T2404
Test name
Test status
Simulation time 177713317 ps
CPU time 0.94 seconds
Started Aug 02 05:34:24 PM PDT 24
Finished Aug 02 05:34:25 PM PDT 24
Peak memory 207396 kb
Host smart-e4b1f8de-4ccc-45c0-929b-343f353f2e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91526
8285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.915268285
Directory /workspace/46.usbdev_in_trans/latest


Test location /workspace/coverage/default/46.usbdev_invalid_sync.2098973034
Short name T2206
Test name
Test status
Simulation time 3977999394 ps
CPU time 112.75 seconds
Started Aug 02 05:34:19 PM PDT 24
Finished Aug 02 05:36:12 PM PDT 24
Peak memory 224048 kb
Host smart-b0678a2e-3ba1-4a69-8d6e-c298a0a2a011
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2098973034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.2098973034
Directory /workspace/46.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/46.usbdev_iso_retraction.1239642587
Short name T2412
Test name
Test status
Simulation time 11358022963 ps
CPU time 73.35 seconds
Started Aug 02 05:34:15 PM PDT 24
Finished Aug 02 05:35:28 PM PDT 24
Peak memory 207676 kb
Host smart-a355b4d8-a2aa-4115-954e-79b65546f862
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1239642587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1239642587
Directory /workspace/46.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/46.usbdev_link_in_err.1424634012
Short name T1038
Test name
Test status
Simulation time 192615433 ps
CPU time 0.95 seconds
Started Aug 02 05:34:19 PM PDT 24
Finished Aug 02 05:34:20 PM PDT 24
Peak memory 207312 kb
Host smart-cd2b6ff0-6d05-4040-a54c-6b53061ecca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14246
34012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1424634012
Directory /workspace/46.usbdev_link_in_err/latest


Test location /workspace/coverage/default/46.usbdev_link_resume.2373486199
Short name T1817
Test name
Test status
Simulation time 11628109154 ps
CPU time 17.14 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:44 PM PDT 24
Peak memory 207708 kb
Host smart-65ed2837-8005-4915-996a-6e5fc523b7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23734
86199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2373486199
Directory /workspace/46.usbdev_link_resume/latest


Test location /workspace/coverage/default/46.usbdev_link_suspend.1266752345
Short name T2080
Test name
Test status
Simulation time 9822582087 ps
CPU time 12.69 seconds
Started Aug 02 05:34:22 PM PDT 24
Finished Aug 02 05:34:34 PM PDT 24
Peak memory 207672 kb
Host smart-47eb4bf5-3e7a-4931-8523-4b4206ca7d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12667
52345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.1266752345
Directory /workspace/46.usbdev_link_suspend/latest


Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1686586527
Short name T2783
Test name
Test status
Simulation time 3334993204 ps
CPU time 23.76 seconds
Started Aug 02 05:34:08 PM PDT 24
Finished Aug 02 05:34:32 PM PDT 24
Peak memory 218272 kb
Host smart-34a78d7e-9742-424c-9b04-901fb7bc329e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16865
86527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1686586527
Directory /workspace/46.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3829521885
Short name T1491
Test name
Test status
Simulation time 3586474310 ps
CPU time 34.61 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:52 PM PDT 24
Peak memory 215856 kb
Host smart-9919d531-f03c-4c91-9f31-a48832d3d331
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3829521885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3829521885
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1508881934
Short name T876
Test name
Test status
Simulation time 245279983 ps
CPU time 0.99 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 207412 kb
Host smart-084f802c-7d4b-42e4-a484-5d4463272868
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1508881934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1508881934
Directory /workspace/46.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2069144052
Short name T568
Test name
Test status
Simulation time 195413956 ps
CPU time 0.96 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:34:47 PM PDT 24
Peak memory 207432 kb
Host smart-fc5d212e-fce5-46bb-86e9-18323bac325c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20691
44052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2069144052
Directory /workspace/46.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2189488779
Short name T2108
Test name
Test status
Simulation time 1904325274 ps
CPU time 14.28 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:32 PM PDT 24
Peak memory 207600 kb
Host smart-92f68875-d0cf-4349-a837-e8a35633fbbe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2189488779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2189488779
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.107047476
Short name T511
Test name
Test status
Simulation time 181272841 ps
CPU time 0.86 seconds
Started Aug 02 05:34:24 PM PDT 24
Finished Aug 02 05:34:25 PM PDT 24
Peak memory 207376 kb
Host smart-b5e6cd4c-a180-4e95-8925-86b61e451a2d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=107047476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.107047476
Directory /workspace/46.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4192708955
Short name T1767
Test name
Test status
Simulation time 177350906 ps
CPU time 0.86 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:17 PM PDT 24
Peak memory 207392 kb
Host smart-69efdc15-d9ea-4d5a-8bc5-536f7fdff2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41927
08955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4192708955
Directory /workspace/46.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_nak_trans.1953599243
Short name T142
Test name
Test status
Simulation time 236213830 ps
CPU time 0.98 seconds
Started Aug 02 05:34:18 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 207384 kb
Host smart-298b7fb5-951a-41ae-b887-d32c465ba772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19535
99243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1953599243
Directory /workspace/46.usbdev_nak_trans/latest


Test location /workspace/coverage/default/46.usbdev_out_iso.970719922
Short name T1712
Test name
Test status
Simulation time 191124354 ps
CPU time 0.87 seconds
Started Aug 02 05:34:20 PM PDT 24
Finished Aug 02 05:34:21 PM PDT 24
Peak memory 207404 kb
Host smart-131e4ede-15f0-4dee-9cf5-7837e5f512f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97071
9922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.970719922
Directory /workspace/46.usbdev_out_iso/latest


Test location /workspace/coverage/default/46.usbdev_out_stall.4072910828
Short name T1840
Test name
Test status
Simulation time 180708241 ps
CPU time 0.92 seconds
Started Aug 02 05:34:14 PM PDT 24
Finished Aug 02 05:34:15 PM PDT 24
Peak memory 207384 kb
Host smart-c302e553-7018-4157-b698-26c7b5b9336e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40729
10828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.4072910828
Directory /workspace/46.usbdev_out_stall/latest


Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2019546712
Short name T2724
Test name
Test status
Simulation time 191091821 ps
CPU time 0.91 seconds
Started Aug 02 05:34:19 PM PDT 24
Finished Aug 02 05:34:20 PM PDT 24
Peak memory 207356 kb
Host smart-b400d762-6e35-45a5-9bd4-5f81bfc5ea98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20195
46712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2019546712
Directory /workspace/46.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1706404722
Short name T2025
Test name
Test status
Simulation time 220078498 ps
CPU time 0.9 seconds
Started Aug 02 05:34:15 PM PDT 24
Finished Aug 02 05:34:16 PM PDT 24
Peak memory 207400 kb
Host smart-d3bdaaac-aece-4d36-8448-070883542efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17064
04722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1706404722
Directory /workspace/46.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.2491119840
Short name T1852
Test name
Test status
Simulation time 210123777 ps
CPU time 0.98 seconds
Started Aug 02 05:34:16 PM PDT 24
Finished Aug 02 05:34:17 PM PDT 24
Peak memory 207380 kb
Host smart-19240c09-5e2e-4d55-b094-01bd2c7b0556
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2491119840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.2491119840
Directory /workspace/46.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.231997532
Short name T2022
Test name
Test status
Simulation time 167584791 ps
CPU time 0.84 seconds
Started Aug 02 05:34:21 PM PDT 24
Finished Aug 02 05:34:22 PM PDT 24
Peak memory 207312 kb
Host smart-43ab8cb1-a936-4e3f-9d41-260a00fe22d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23199
7532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.231997532
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.3417111635
Short name T2513
Test name
Test status
Simulation time 33494153 ps
CPU time 0.66 seconds
Started Aug 02 05:34:28 PM PDT 24
Finished Aug 02 05:34:28 PM PDT 24
Peak memory 207316 kb
Host smart-d4c4a3c3-f518-40b8-9396-ad52d34f2cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34171
11635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.3417111635
Directory /workspace/46.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/46.usbdev_pkt_buffer.1015718630
Short name T347
Test name
Test status
Simulation time 7187527075 ps
CPU time 18.03 seconds
Started Aug 02 05:34:31 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 215876 kb
Host smart-d5d780e4-ded1-4a6b-ae86-3953d9f65e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157
18630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.1015718630
Directory /workspace/46.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/46.usbdev_pkt_received.1397503736
Short name T328
Test name
Test status
Simulation time 190908239 ps
CPU time 0.91 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 207372 kb
Host smart-e62dcc1c-806b-4411-b4ee-3a334531abb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13975
03736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1397503736
Directory /workspace/46.usbdev_pkt_received/latest


Test location /workspace/coverage/default/46.usbdev_pkt_sent.1413406311
Short name T970
Test name
Test status
Simulation time 224550704 ps
CPU time 0.98 seconds
Started Aug 02 05:34:30 PM PDT 24
Finished Aug 02 05:34:31 PM PDT 24
Peak memory 207376 kb
Host smart-f7d9815b-bbb6-4f07-9127-ad47f20bd613
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14134
06311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1413406311
Directory /workspace/46.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.3940341556
Short name T3099
Test name
Test status
Simulation time 218839288 ps
CPU time 0.96 seconds
Started Aug 02 05:34:33 PM PDT 24
Finished Aug 02 05:34:34 PM PDT 24
Peak memory 207320 kb
Host smart-aeedf604-8fb0-4a12-8082-6b1a83f53a7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39403
41556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.3940341556
Directory /workspace/46.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.3618686031
Short name T1941
Test name
Test status
Simulation time 186065189 ps
CPU time 0.93 seconds
Started Aug 02 05:34:21 PM PDT 24
Finished Aug 02 05:34:22 PM PDT 24
Peak memory 207392 kb
Host smart-ea032e9d-5311-4355-b8bb-2af24065a04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36186
86031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.3618686031
Directory /workspace/46.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/46.usbdev_rx_crc_err.4160345756
Short name T1237
Test name
Test status
Simulation time 144727630 ps
CPU time 0.79 seconds
Started Aug 02 05:34:34 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 207300 kb
Host smart-216f5767-6f2c-4f05-9d98-da799188ee27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41603
45756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.4160345756
Directory /workspace/46.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/46.usbdev_rx_full.2068498797
Short name T303
Test name
Test status
Simulation time 300398670 ps
CPU time 1.18 seconds
Started Aug 02 05:34:19 PM PDT 24
Finished Aug 02 05:34:21 PM PDT 24
Peak memory 207300 kb
Host smart-378d9887-7f6e-401b-ad78-7f016765d117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20684
98797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_full.2068498797
Directory /workspace/46.usbdev_rx_full/latest


Test location /workspace/coverage/default/46.usbdev_setup_stage.1285460335
Short name T1960
Test name
Test status
Simulation time 155376766 ps
CPU time 0.87 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 207356 kb
Host smart-c99e9502-4d04-497a-b99b-41902147e594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12854
60335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.1285460335
Directory /workspace/46.usbdev_setup_stage/latest


Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.273093679
Short name T987
Test name
Test status
Simulation time 145761736 ps
CPU time 0.88 seconds
Started Aug 02 05:34:22 PM PDT 24
Finished Aug 02 05:34:23 PM PDT 24
Peak memory 207428 kb
Host smart-83631abc-5eb4-42a2-b2df-a8a422a84bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27309
3679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.273093679
Directory /workspace/46.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/46.usbdev_smoke.3522610971
Short name T2186
Test name
Test status
Simulation time 248916674 ps
CPU time 1.03 seconds
Started Aug 02 05:34:38 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 207312 kb
Host smart-6ed91b6d-d138-47a4-8465-c1f2af228441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35226
10971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.3522610971
Directory /workspace/46.usbdev_smoke/latest


Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.117632888
Short name T2707
Test name
Test status
Simulation time 1917506613 ps
CPU time 14.79 seconds
Started Aug 02 05:34:29 PM PDT 24
Finished Aug 02 05:34:44 PM PDT 24
Peak memory 217192 kb
Host smart-1af10d56-6dae-48fb-a7b1-7e3df2c5537a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=117632888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.117632888
Directory /workspace/46.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.4007611678
Short name T1986
Test name
Test status
Simulation time 175328585 ps
CPU time 0.84 seconds
Started Aug 02 05:34:25 PM PDT 24
Finished Aug 02 05:34:26 PM PDT 24
Peak memory 207348 kb
Host smart-301049a7-fb91-4b24-94f7-3d6b93b04934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40076
11678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.4007611678
Directory /workspace/46.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/46.usbdev_stall_trans.1404010880
Short name T1160
Test name
Test status
Simulation time 154067136 ps
CPU time 0.83 seconds
Started Aug 02 05:34:35 PM PDT 24
Finished Aug 02 05:34:36 PM PDT 24
Peak memory 207416 kb
Host smart-5ad245ea-5972-497e-86b2-393b90c42ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14040
10880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.1404010880
Directory /workspace/46.usbdev_stall_trans/latest


Test location /workspace/coverage/default/46.usbdev_stream_len_max.2288037859
Short name T2420
Test name
Test status
Simulation time 1320107907 ps
CPU time 3.16 seconds
Started Aug 02 05:34:28 PM PDT 24
Finished Aug 02 05:34:31 PM PDT 24
Peak memory 207616 kb
Host smart-cc850e09-dc0c-4481-b1bd-6e0910a6d263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22880
37859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2288037859
Directory /workspace/46.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/46.usbdev_streaming_out.1702129188
Short name T1507
Test name
Test status
Simulation time 2870487095 ps
CPU time 74.07 seconds
Started Aug 02 05:34:24 PM PDT 24
Finished Aug 02 05:35:38 PM PDT 24
Peak memory 224052 kb
Host smart-7497102c-3a18-4758-bf39-079e0a5013e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17021
29188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.1702129188
Directory /workspace/46.usbdev_streaming_out/latest


Test location /workspace/coverage/default/46.usbdev_timeout_missing_host_handshake.2422749790
Short name T1781
Test name
Test status
Simulation time 1548453851 ps
CPU time 9.53 seconds
Started Aug 02 05:34:18 PM PDT 24
Finished Aug 02 05:34:33 PM PDT 24
Peak memory 207564 kb
Host smart-414a3329-6197-4e0e-b1ad-7995d2eac5f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422749790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_timeout_missing_hos
t_handshake.2422749790
Directory /workspace/46.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/47.usbdev_alert_test.1082843512
Short name T1563
Test name
Test status
Simulation time 44315358 ps
CPU time 0.69 seconds
Started Aug 02 05:34:40 PM PDT 24
Finished Aug 02 05:34:41 PM PDT 24
Peak memory 207300 kb
Host smart-1ccb8cae-2abf-4fde-aff4-459be7cae958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1082843512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.1082843512
Directory /workspace/47.usbdev_alert_test/latest


Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.475039315
Short name T1884
Test name
Test status
Simulation time 6875219568 ps
CPU time 9.78 seconds
Started Aug 02 05:34:31 PM PDT 24
Finished Aug 02 05:34:40 PM PDT 24
Peak memory 215804 kb
Host smart-4e9ce1e7-c147-4cd8-99ba-4d9ece2b8343
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475039315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ao
n_wake_disconnect.475039315
Directory /workspace/47.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.953974771
Short name T1392
Test name
Test status
Simulation time 20053400883 ps
CPU time 24.85 seconds
Started Aug 02 05:34:32 PM PDT 24
Finished Aug 02 05:34:57 PM PDT 24
Peak memory 207648 kb
Host smart-9ccd396d-ab5b-483c-93c2-a19f9dc48fdc
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=953974771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.953974771
Directory /workspace/47.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.674355056
Short name T1437
Test name
Test status
Simulation time 30775286936 ps
CPU time 35.07 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207596 kb
Host smart-9a81d50e-a647-4fe4-84f8-442a75d643aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674355056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_ao
n_wake_resume.674355056
Directory /workspace/47.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/47.usbdev_av_buffer.502894426
Short name T1652
Test name
Test status
Simulation time 170410453 ps
CPU time 0.85 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:34:28 PM PDT 24
Peak memory 207392 kb
Host smart-189a5884-c0f5-4424-95f7-87ffe58bc963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50289
4426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.502894426
Directory /workspace/47.usbdev_av_buffer/latest


Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2096529884
Short name T2390
Test name
Test status
Simulation time 180974113 ps
CPU time 0.92 seconds
Started Aug 02 05:34:18 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 207368 kb
Host smart-9cb5d66b-acce-4f57-8da4-b6d0635a5cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20965
29884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2096529884
Directory /workspace/47.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.1048281394
Short name T1375
Test name
Test status
Simulation time 264808145 ps
CPU time 1.11 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:23 PM PDT 24
Peak memory 207424 kb
Host smart-ebb8fa13-60d0-4618-b7cd-9496772c84ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10482
81394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.1048281394
Directory /workspace/47.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.3141109712
Short name T523
Test name
Test status
Simulation time 275540448 ps
CPU time 0.95 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:34:52 PM PDT 24
Peak memory 207332 kb
Host smart-2e18e7d3-78ef-468f-a22d-1363581cd88b
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3141109712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.3141109712
Directory /workspace/47.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/47.usbdev_device_address.563558190
Short name T2029
Test name
Test status
Simulation time 28422597077 ps
CPU time 43.7 seconds
Started Aug 02 05:34:31 PM PDT 24
Finished Aug 02 05:35:20 PM PDT 24
Peak memory 207652 kb
Host smart-d0e670f9-f1b8-402d-bff8-dbe0b80823a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56355
8190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.563558190
Directory /workspace/47.usbdev_device_address/latest


Test location /workspace/coverage/default/47.usbdev_device_timeout.3243083391
Short name T1479
Test name
Test status
Simulation time 1869424768 ps
CPU time 42.78 seconds
Started Aug 02 05:34:29 PM PDT 24
Finished Aug 02 05:35:12 PM PDT 24
Peak memory 207468 kb
Host smart-f0f6b0f2-9467-4669-adcc-03ce6e2fd449
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243083391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_timeout.3243083391
Directory /workspace/47.usbdev_device_timeout/latest


Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1622474265
Short name T855
Test name
Test status
Simulation time 678408287 ps
CPU time 1.67 seconds
Started Aug 02 05:34:29 PM PDT 24
Finished Aug 02 05:34:31 PM PDT 24
Peak memory 207348 kb
Host smart-f77ad3ef-ed5a-4ad0-a158-517d305eb376
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16224
74265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1622474265
Directory /workspace/47.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/47.usbdev_disconnected.3973674897
Short name T2515
Test name
Test status
Simulation time 141447691 ps
CPU time 0.86 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:34:28 PM PDT 24
Peak memory 207332 kb
Host smart-b7f1c6f6-7ffb-4ce5-a2e1-a35533714cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39736
74897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3973674897
Directory /workspace/47.usbdev_disconnected/latest


Test location /workspace/coverage/default/47.usbdev_enable.1239732998
Short name T3021
Test name
Test status
Simulation time 42418477 ps
CPU time 0.72 seconds
Started Aug 02 05:34:43 PM PDT 24
Finished Aug 02 05:34:43 PM PDT 24
Peak memory 207280 kb
Host smart-a09dd338-3eff-4b4c-96cd-858a4dcf7504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397
32998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1239732998
Directory /workspace/47.usbdev_enable/latest


Test location /workspace/coverage/default/47.usbdev_endpoint_access.3977288080
Short name T2951
Test name
Test status
Simulation time 913388727 ps
CPU time 2.6 seconds
Started Aug 02 05:34:30 PM PDT 24
Finished Aug 02 05:34:32 PM PDT 24
Peak memory 207560 kb
Host smart-25d329d7-1df0-48c1-bce1-810675091656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39772
88080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.3977288080
Directory /workspace/47.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/47.usbdev_endpoint_types.926769826
Short name T395
Test name
Test status
Simulation time 421968918 ps
CPU time 1.25 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:27 PM PDT 24
Peak memory 207312 kb
Host smart-bfeb9c3a-a5a8-4e4e-a523-40fb1ed16da3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=926769826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_types.926769826
Directory /workspace/47.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/47.usbdev_fifo_rst.45924560
Short name T195
Test name
Test status
Simulation time 305791904 ps
CPU time 2.51 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:34:30 PM PDT 24
Peak memory 207476 kb
Host smart-306916f2-70f6-4646-a46e-0397c55a9c39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45924
560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.45924560
Directory /workspace/47.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/47.usbdev_in_iso.1800939729
Short name T1680
Test name
Test status
Simulation time 167291932 ps
CPU time 0.86 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:34:28 PM PDT 24
Peak memory 207396 kb
Host smart-9a050360-a6b9-4d36-a226-64d06925d111
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1800939729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.1800939729
Directory /workspace/47.usbdev_in_iso/latest


Test location /workspace/coverage/default/47.usbdev_in_stall.4109453711
Short name T1
Test name
Test status
Simulation time 139068682 ps
CPU time 0.8 seconds
Started Aug 02 05:34:29 PM PDT 24
Finished Aug 02 05:34:29 PM PDT 24
Peak memory 207356 kb
Host smart-d8c7a815-5c89-4b69-9b52-834fa9bc95d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41094
53711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.4109453711
Directory /workspace/47.usbdev_in_stall/latest


Test location /workspace/coverage/default/47.usbdev_in_trans.2736937641
Short name T1959
Test name
Test status
Simulation time 208847644 ps
CPU time 1 seconds
Started Aug 02 05:34:44 PM PDT 24
Finished Aug 02 05:34:45 PM PDT 24
Peak memory 207376 kb
Host smart-47423589-6c74-4eee-9fbf-7cc8a6d3ebdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27369
37641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2736937641
Directory /workspace/47.usbdev_in_trans/latest


Test location /workspace/coverage/default/47.usbdev_invalid_sync.4164678653
Short name T1929
Test name
Test status
Simulation time 3644382776 ps
CPU time 103.32 seconds
Started Aug 02 05:34:39 PM PDT 24
Finished Aug 02 05:36:22 PM PDT 24
Peak memory 223980 kb
Host smart-e20327bc-a758-4462-a776-923a8ba049b2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4164678653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.4164678653
Directory /workspace/47.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/47.usbdev_iso_retraction.3161224561
Short name T2965
Test name
Test status
Simulation time 4460065325 ps
CPU time 50.07 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207632 kb
Host smart-becbc5a3-230b-4970-87a6-78ad8966fe87
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3161224561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.3161224561
Directory /workspace/47.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/47.usbdev_link_in_err.1902646036
Short name T2679
Test name
Test status
Simulation time 171214111 ps
CPU time 0.91 seconds
Started Aug 02 05:34:38 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 207376 kb
Host smart-31b81ecb-1dda-4f56-812d-412e6dbda7fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19026
46036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1902646036
Directory /workspace/47.usbdev_link_in_err/latest


Test location /workspace/coverage/default/47.usbdev_link_resume.1860823730
Short name T2930
Test name
Test status
Simulation time 11158534529 ps
CPU time 13.8 seconds
Started Aug 02 05:34:24 PM PDT 24
Finished Aug 02 05:34:38 PM PDT 24
Peak memory 207700 kb
Host smart-cc4e2b2a-1f04-49ab-b1e0-bb09bfd857e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18608
23730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.1860823730
Directory /workspace/47.usbdev_link_resume/latest


Test location /workspace/coverage/default/47.usbdev_link_suspend.2969960580
Short name T1868
Test name
Test status
Simulation time 5977355952 ps
CPU time 8.52 seconds
Started Aug 02 05:34:41 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 215836 kb
Host smart-8e7a3da6-9895-4c2f-ac3a-bf85c2ff8bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29699
60580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.2969960580
Directory /workspace/47.usbdev_link_suspend/latest


Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.497349544
Short name T757
Test name
Test status
Simulation time 3568994616 ps
CPU time 34.46 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 218792 kb
Host smart-365d2bf8-a54b-463b-9637-bc0a5998f00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49734
9544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.497349544
Directory /workspace/47.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.701330701
Short name T2588
Test name
Test status
Simulation time 2440518837 ps
CPU time 23.31 seconds
Started Aug 02 05:34:26 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 217544 kb
Host smart-ac2487fb-2b8b-4760-9f0e-a48f32cf65a6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=701330701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.701330701
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3259293345
Short name T1412
Test name
Test status
Simulation time 243959193 ps
CPU time 0.99 seconds
Started Aug 02 05:34:42 PM PDT 24
Finished Aug 02 05:34:43 PM PDT 24
Peak memory 207380 kb
Host smart-2e06a2e4-6030-4be3-a580-3aa31fd849b0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3259293345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3259293345
Directory /workspace/47.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.2597738080
Short name T2629
Test name
Test status
Simulation time 213703759 ps
CPU time 0.94 seconds
Started Aug 02 05:34:38 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 207404 kb
Host smart-5672a772-d4af-4263-a936-fdb9bf75f57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25977
38080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.2597738080
Directory /workspace/47.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.40548946
Short name T1805
Test name
Test status
Simulation time 2547290201 ps
CPU time 24.64 seconds
Started Aug 02 05:34:45 PM PDT 24
Finished Aug 02 05:35:10 PM PDT 24
Peak memory 215880 kb
Host smart-0e9dc9f1-8bf7-4410-a755-583e31b42c2e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=40548946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.40548946
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3941103331
Short name T2321
Test name
Test status
Simulation time 150296087 ps
CPU time 0.82 seconds
Started Aug 02 05:34:15 PM PDT 24
Finished Aug 02 05:34:16 PM PDT 24
Peak memory 207416 kb
Host smart-540ad54f-c3a8-42af-a21e-f23d73c92cc2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3941103331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3941103331
Directory /workspace/47.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1020311170
Short name T2399
Test name
Test status
Simulation time 162528916 ps
CPU time 0.82 seconds
Started Aug 02 05:34:17 PM PDT 24
Finished Aug 02 05:34:18 PM PDT 24
Peak memory 207404 kb
Host smart-590c07a7-3fa9-4f88-9055-11be4e67fb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10203
11170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1020311170
Directory /workspace/47.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_nak_trans.2777936395
Short name T144
Test name
Test status
Simulation time 202675235 ps
CPU time 0.88 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:34:47 PM PDT 24
Peak memory 207332 kb
Host smart-752913a7-241d-496e-9cb5-cbe0f7ebeb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27779
36395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.2777936395
Directory /workspace/47.usbdev_nak_trans/latest


Test location /workspace/coverage/default/47.usbdev_out_iso.3423584759
Short name T678
Test name
Test status
Simulation time 211009892 ps
CPU time 0.94 seconds
Started Aug 02 05:34:35 PM PDT 24
Finished Aug 02 05:34:36 PM PDT 24
Peak memory 207336 kb
Host smart-76e6f22e-450f-42bd-87ab-3b80d8b7fdbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34235
84759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3423584759
Directory /workspace/47.usbdev_out_iso/latest


Test location /workspace/coverage/default/47.usbdev_out_stall.3700377099
Short name T17
Test name
Test status
Simulation time 248109751 ps
CPU time 0.96 seconds
Started Aug 02 05:34:34 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 207360 kb
Host smart-414d19f2-dd47-4497-ad88-6e5a7d44f34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37003
77099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.3700377099
Directory /workspace/47.usbdev_out_stall/latest


Test location /workspace/coverage/default/47.usbdev_out_trans_nak.2505107873
Short name T931
Test name
Test status
Simulation time 237843042 ps
CPU time 0.94 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:48 PM PDT 24
Peak memory 207444 kb
Host smart-325a27db-e5bb-4eb6-94e1-aa933ce79fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25051
07873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.2505107873
Directory /workspace/47.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/47.usbdev_pending_in_trans.1330127629
Short name T2915
Test name
Test status
Simulation time 153337901 ps
CPU time 0.83 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:34:28 PM PDT 24
Peak memory 207368 kb
Host smart-07c15e74-a1f2-433e-baf9-06b8e2ad9ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13301
27629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1330127629
Directory /workspace/47.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.891878882
Short name T2247
Test name
Test status
Simulation time 194425086 ps
CPU time 0.9 seconds
Started Aug 02 05:34:43 PM PDT 24
Finished Aug 02 05:34:44 PM PDT 24
Peak memory 207432 kb
Host smart-c6b34794-0f23-42e9-858c-556bb681e75d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=891878882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.891878882
Directory /workspace/47.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2044936566
Short name T2773
Test name
Test status
Simulation time 140984035 ps
CPU time 0.79 seconds
Started Aug 02 05:34:54 PM PDT 24
Finished Aug 02 05:34:55 PM PDT 24
Peak memory 207384 kb
Host smart-71b0dc22-7ddf-4af6-8b66-b9300cf1ec1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20449
36566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2044936566
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.4084145294
Short name T943
Test name
Test status
Simulation time 46890809 ps
CPU time 0.71 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207288 kb
Host smart-59da3736-3dad-4b1c-82b6-773bf9e569bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40841
45294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.4084145294
Directory /workspace/47.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1683238230
Short name T263
Test name
Test status
Simulation time 18428429555 ps
CPU time 47.68 seconds
Started Aug 02 05:34:36 PM PDT 24
Finished Aug 02 05:35:24 PM PDT 24
Peak memory 215916 kb
Host smart-76f5232a-39d1-476a-af43-f087281edf6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16832
38230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1683238230
Directory /workspace/47.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/47.usbdev_pkt_received.1119993215
Short name T2876
Test name
Test status
Simulation time 214408472 ps
CPU time 0.96 seconds
Started Aug 02 05:34:38 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 207348 kb
Host smart-54ec5909-0806-42cb-96da-c94027b8eeab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11199
93215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.1119993215
Directory /workspace/47.usbdev_pkt_received/latest


Test location /workspace/coverage/default/47.usbdev_pkt_sent.1702747752
Short name T819
Test name
Test status
Simulation time 207016456 ps
CPU time 0.96 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:34:48 PM PDT 24
Peak memory 207376 kb
Host smart-83d5017e-d481-4620-8735-4732bc7aacb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17027
47752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.1702747752
Directory /workspace/47.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.3480251303
Short name T498
Test name
Test status
Simulation time 194499754 ps
CPU time 0.91 seconds
Started Aug 02 05:34:27 PM PDT 24
Finished Aug 02 05:34:28 PM PDT 24
Peak memory 207420 kb
Host smart-33313921-74dc-42f7-8573-66bb884ce693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
51303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.3480251303
Directory /workspace/47.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1337915494
Short name T1793
Test name
Test status
Simulation time 189895249 ps
CPU time 0.85 seconds
Started Aug 02 05:34:18 PM PDT 24
Finished Aug 02 05:34:19 PM PDT 24
Peak memory 207412 kb
Host smart-d5bfa3cb-2f82-493a-923d-33fef2059075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13379
15494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1337915494
Directory /workspace/47.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2929405089
Short name T2426
Test name
Test status
Simulation time 246597179 ps
CPU time 0.95 seconds
Started Aug 02 05:34:30 PM PDT 24
Finished Aug 02 05:34:31 PM PDT 24
Peak memory 207408 kb
Host smart-2ef42485-53c2-4118-bfaa-d9cdd30f40a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29294
05089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2929405089
Directory /workspace/47.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/47.usbdev_rx_full.4265295176
Short name T304
Test name
Test status
Simulation time 264948070 ps
CPU time 1.1 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207332 kb
Host smart-a6964700-3a34-4cf7-8f35-8259ecf5d09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42652
95176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_full.4265295176
Directory /workspace/47.usbdev_rx_full/latest


Test location /workspace/coverage/default/47.usbdev_setup_stage.2693369426
Short name T1623
Test name
Test status
Simulation time 143356939 ps
CPU time 0.88 seconds
Started Aug 02 05:34:50 PM PDT 24
Finished Aug 02 05:34:51 PM PDT 24
Peak memory 207316 kb
Host smart-72953674-8894-45c1-880d-3950a3d44cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26933
69426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.2693369426
Directory /workspace/47.usbdev_setup_stage/latest


Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1740260740
Short name T924
Test name
Test status
Simulation time 151325384 ps
CPU time 0.83 seconds
Started Aug 02 05:34:43 PM PDT 24
Finished Aug 02 05:34:43 PM PDT 24
Peak memory 207348 kb
Host smart-522ae467-199d-46b3-980d-422c0cb35461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17402
60740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1740260740
Directory /workspace/47.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/47.usbdev_smoke.1931353038
Short name T1899
Test name
Test status
Simulation time 203051103 ps
CPU time 0.94 seconds
Started Aug 02 05:34:45 PM PDT 24
Finished Aug 02 05:34:46 PM PDT 24
Peak memory 207356 kb
Host smart-382a936f-2713-4cbb-aea6-93449cf26044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19313
53038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1931353038
Directory /workspace/47.usbdev_smoke/latest


Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.2160593116
Short name T1304
Test name
Test status
Simulation time 3238681884 ps
CPU time 26.25 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:35:13 PM PDT 24
Peak memory 223992 kb
Host smart-41288b6b-6947-43d2-a03f-a2560970946e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2160593116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.2160593116
Directory /workspace/47.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.618547323
Short name T1413
Test name
Test status
Simulation time 177010802 ps
CPU time 0.84 seconds
Started Aug 02 05:34:37 PM PDT 24
Finished Aug 02 05:34:38 PM PDT 24
Peak memory 207360 kb
Host smart-c9718f2b-0ca7-430c-b927-4d5ef89cdd82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61854
7323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.618547323
Directory /workspace/47.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/47.usbdev_stall_trans.2125114454
Short name T1749
Test name
Test status
Simulation time 163784448 ps
CPU time 0.86 seconds
Started Aug 02 05:34:40 PM PDT 24
Finished Aug 02 05:34:40 PM PDT 24
Peak memory 207356 kb
Host smart-903f0239-5a5f-4d4b-b168-416878af9077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21251
14454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.2125114454
Directory /workspace/47.usbdev_stall_trans/latest


Test location /workspace/coverage/default/47.usbdev_stream_len_max.952779703
Short name T1260
Test name
Test status
Simulation time 434268438 ps
CPU time 1.32 seconds
Started Aug 02 05:34:19 PM PDT 24
Finished Aug 02 05:34:25 PM PDT 24
Peak memory 207324 kb
Host smart-d1572b6f-61ca-46c4-b176-6820f7b99b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95277
9703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.952779703
Directory /workspace/47.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/47.usbdev_streaming_out.149555348
Short name T2105
Test name
Test status
Simulation time 3125767387 ps
CPU time 92.71 seconds
Started Aug 02 05:34:49 PM PDT 24
Finished Aug 02 05:36:22 PM PDT 24
Peak memory 217404 kb
Host smart-885f2df7-1c94-40ff-8615-db9e98149335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14955
5348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.149555348
Directory /workspace/47.usbdev_streaming_out/latest


Test location /workspace/coverage/default/47.usbdev_timeout_missing_host_handshake.334956604
Short name T1076
Test name
Test status
Simulation time 4374582139 ps
CPU time 30.24 seconds
Started Aug 02 05:34:30 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 207648 kb
Host smart-67d281a3-ae8f-4f58-be9c-59439f888f71
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334956604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_timeout_missing_host
_handshake.334956604
Directory /workspace/47.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/48.usbdev_alert_test.3479838739
Short name T1303
Test name
Test status
Simulation time 38946108 ps
CPU time 0.66 seconds
Started Aug 02 05:34:43 PM PDT 24
Finished Aug 02 05:34:44 PM PDT 24
Peak memory 207492 kb
Host smart-7ec4a59c-9e61-4256-acfb-82f1e45d9bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3479838739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3479838739
Directory /workspace/48.usbdev_alert_test/latest


Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1401187565
Short name T1213
Test name
Test status
Simulation time 5824361831 ps
CPU time 7.76 seconds
Started Aug 02 05:34:40 PM PDT 24
Finished Aug 02 05:34:48 PM PDT 24
Peak memory 215852 kb
Host smart-3ad3d68c-de9b-416e-be6d-df8009f49831
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401187565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_disconnect.1401187565
Directory /workspace/48.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.2774242523
Short name T1153
Test name
Test status
Simulation time 18437241758 ps
CPU time 20.2 seconds
Started Aug 02 05:34:36 PM PDT 24
Finished Aug 02 05:34:57 PM PDT 24
Peak memory 207656 kb
Host smart-abfac2b8-2965-492f-9562-d8c68212315c
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774242523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.2774242523
Directory /workspace/48.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.1522000720
Short name T2980
Test name
Test status
Simulation time 30226438890 ps
CPU time 43.48 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:35:30 PM PDT 24
Peak memory 207676 kb
Host smart-aa5b091c-ac57-4c40-bce3-b6ade70c9dda
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522000720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_a
on_wake_resume.1522000720
Directory /workspace/48.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/48.usbdev_av_buffer.4150203337
Short name T2100
Test name
Test status
Simulation time 198283921 ps
CPU time 0.95 seconds
Started Aug 02 05:34:39 PM PDT 24
Finished Aug 02 05:34:40 PM PDT 24
Peak memory 207360 kb
Host smart-5cc87152-62b5-46f2-8f11-f5fbeaa97eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41502
03337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.4150203337
Directory /workspace/48.usbdev_av_buffer/latest


Test location /workspace/coverage/default/48.usbdev_bitstuff_err.53587966
Short name T2734
Test name
Test status
Simulation time 160360295 ps
CPU time 0.86 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:48 PM PDT 24
Peak memory 207296 kb
Host smart-1775cc81-6476-4775-b5cb-a8e071e30dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53587
966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.53587966
Directory /workspace/48.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.4170347178
Short name T1146
Test name
Test status
Simulation time 274009421 ps
CPU time 1.08 seconds
Started Aug 02 05:34:40 PM PDT 24
Finished Aug 02 05:34:41 PM PDT 24
Peak memory 207208 kb
Host smart-ac0eaf40-48f4-45bf-88e7-db4a9cda86b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41703
47178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.4170347178
Directory /workspace/48.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.1739387566
Short name T1149
Test name
Test status
Simulation time 918272676 ps
CPU time 2.37 seconds
Started Aug 02 05:34:37 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 207584 kb
Host smart-88270366-5d99-4731-b3a1-77bc7a93f4ef
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1739387566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.1739387566
Directory /workspace/48.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/48.usbdev_device_address.4005327502
Short name T177
Test name
Test status
Simulation time 43625809876 ps
CPU time 66.98 seconds
Started Aug 02 05:34:41 PM PDT 24
Finished Aug 02 05:35:48 PM PDT 24
Peak memory 207592 kb
Host smart-8d3bf428-2de6-4eb3-a1d8-9c58afec58f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40053
27502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.4005327502
Directory /workspace/48.usbdev_device_address/latest


Test location /workspace/coverage/default/48.usbdev_device_timeout.3924528681
Short name T1289
Test name
Test status
Simulation time 2205557355 ps
CPU time 13.57 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 207608 kb
Host smart-a6169ccc-b79c-4f4a-8aee-70165a48900c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924528681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_timeout.3924528681
Directory /workspace/48.usbdev_device_timeout/latest


Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2732894197
Short name T651
Test name
Test status
Simulation time 1111282469 ps
CPU time 2.47 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 207376 kb
Host smart-48fe6876-94dc-4629-9cc2-eb386c04b98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27328
94197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2732894197
Directory /workspace/48.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/48.usbdev_disconnected.3698710433
Short name T2032
Test name
Test status
Simulation time 215354717 ps
CPU time 0.88 seconds
Started Aug 02 05:34:37 PM PDT 24
Finished Aug 02 05:34:38 PM PDT 24
Peak memory 207412 kb
Host smart-f3e4c9c2-60b7-413f-b24a-0b0a9aca97a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36987
10433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3698710433
Directory /workspace/48.usbdev_disconnected/latest


Test location /workspace/coverage/default/48.usbdev_enable.3368198306
Short name T1469
Test name
Test status
Simulation time 35795804 ps
CPU time 0.7 seconds
Started Aug 02 05:34:40 PM PDT 24
Finished Aug 02 05:34:41 PM PDT 24
Peak memory 207320 kb
Host smart-e1f1650d-9514-46a6-aebf-51d971559043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33681
98306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3368198306
Directory /workspace/48.usbdev_enable/latest


Test location /workspace/coverage/default/48.usbdev_endpoint_access.1228822203
Short name T1882
Test name
Test status
Simulation time 813255536 ps
CPU time 2.42 seconds
Started Aug 02 05:34:43 PM PDT 24
Finished Aug 02 05:34:45 PM PDT 24
Peak memory 207676 kb
Host smart-303d9339-7388-48de-8d1f-3ef469de0d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12288
22203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.1228822203
Directory /workspace/48.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/48.usbdev_endpoint_types.2981876273
Short name T1676
Test name
Test status
Simulation time 295744224 ps
CPU time 1.18 seconds
Started Aug 02 05:34:39 PM PDT 24
Finished Aug 02 05:34:40 PM PDT 24
Peak memory 207424 kb
Host smart-0db6fc37-2aa8-471e-9eda-f8236742ba39
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2981876273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_types.2981876273
Directory /workspace/48.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/48.usbdev_fifo_rst.1382980462
Short name T642
Test name
Test status
Simulation time 192424668 ps
CPU time 2 seconds
Started Aug 02 05:34:42 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207468 kb
Host smart-7a0687be-6573-45e7-a615-179d4ff5a42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13829
80462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1382980462
Directory /workspace/48.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/48.usbdev_in_iso.1817017275
Short name T1315
Test name
Test status
Simulation time 214242546 ps
CPU time 1.17 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:48 PM PDT 24
Peak memory 215780 kb
Host smart-83ab08a8-4319-49cb-aa29-44c13e76d4dd
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1817017275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1817017275
Directory /workspace/48.usbdev_in_iso/latest


Test location /workspace/coverage/default/48.usbdev_in_stall.1935101687
Short name T1944
Test name
Test status
Simulation time 141185093 ps
CPU time 0.77 seconds
Started Aug 02 05:34:40 PM PDT 24
Finished Aug 02 05:34:41 PM PDT 24
Peak memory 207356 kb
Host smart-af916fa3-995b-4e72-924c-8ffdf9405330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19351
01687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.1935101687
Directory /workspace/48.usbdev_in_stall/latest


Test location /workspace/coverage/default/48.usbdev_in_trans.4184572537
Short name T616
Test name
Test status
Simulation time 202597185 ps
CPU time 0.94 seconds
Started Aug 02 05:34:50 PM PDT 24
Finished Aug 02 05:34:52 PM PDT 24
Peak memory 207356 kb
Host smart-18aea8b4-ab86-46b3-a377-fc2fbc424bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41845
72537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.4184572537
Directory /workspace/48.usbdev_in_trans/latest


Test location /workspace/coverage/default/48.usbdev_invalid_sync.18601559
Short name T2730
Test name
Test status
Simulation time 3258135884 ps
CPU time 94.84 seconds
Started Aug 02 05:34:49 PM PDT 24
Finished Aug 02 05:36:24 PM PDT 24
Peak memory 224028 kb
Host smart-40b66dea-13cd-4890-8779-e0fa54cd9b29
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=18601559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.18601559
Directory /workspace/48.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/48.usbdev_iso_retraction.3483221894
Short name T890
Test name
Test status
Simulation time 10747904735 ps
CPU time 72.11 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:35:59 PM PDT 24
Peak memory 207660 kb
Host smart-4756a592-9237-444e-8892-e91cf5ce1e8a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3483221894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.3483221894
Directory /workspace/48.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/48.usbdev_link_in_err.2768219062
Short name T1415
Test name
Test status
Simulation time 182693123 ps
CPU time 0.92 seconds
Started Aug 02 05:34:49 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 207384 kb
Host smart-be3593e7-d843-4e15-9a8c-9ba5bdc99f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27682
19062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2768219062
Directory /workspace/48.usbdev_link_in_err/latest


Test location /workspace/coverage/default/48.usbdev_link_resume.2839217015
Short name T2972
Test name
Test status
Simulation time 10054112932 ps
CPU time 13.02 seconds
Started Aug 02 05:34:58 PM PDT 24
Finished Aug 02 05:35:11 PM PDT 24
Peak memory 207672 kb
Host smart-d8689090-476e-4231-bf4c-6236329cc5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28392
17015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2839217015
Directory /workspace/48.usbdev_link_resume/latest


Test location /workspace/coverage/default/48.usbdev_link_suspend.3738073090
Short name T3063
Test name
Test status
Simulation time 10257461885 ps
CPU time 13.57 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207716 kb
Host smart-a78f2786-3b85-4f69-8afb-59ef59a3b877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37380
73090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3738073090
Directory /workspace/48.usbdev_link_suspend/latest


Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.4281860763
Short name T1055
Test name
Test status
Simulation time 2611731055 ps
CPU time 71.63 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:35:59 PM PDT 24
Peak memory 218208 kb
Host smart-4399e55e-d434-406f-806e-7ffb5e86009a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42818
60763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.4281860763
Directory /workspace/48.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3422902149
Short name T985
Test name
Test status
Simulation time 2546500251 ps
CPU time 73.08 seconds
Started Aug 02 05:34:28 PM PDT 24
Finished Aug 02 05:35:41 PM PDT 24
Peak memory 217304 kb
Host smart-a6e4731a-bb0d-4a05-8944-163dd7812f83
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3422902149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3422902149
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.20617401
Short name T2165
Test name
Test status
Simulation time 239223551 ps
CPU time 0.99 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207408 kb
Host smart-ce6791d9-502d-4f1d-b7bc-ecff3fd2118f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=20617401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.20617401
Directory /workspace/48.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.3358402743
Short name T1826
Test name
Test status
Simulation time 210106130 ps
CPU time 0.93 seconds
Started Aug 02 05:34:37 PM PDT 24
Finished Aug 02 05:34:38 PM PDT 24
Peak memory 207352 kb
Host smart-6175eb34-4434-4bff-8555-c8eb87744a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33584
02743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.3358402743
Directory /workspace/48.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.567860596
Short name T883
Test name
Test status
Simulation time 3321433171 ps
CPU time 33.16 seconds
Started Aug 02 05:34:51 PM PDT 24
Finished Aug 02 05:35:24 PM PDT 24
Peak memory 215864 kb
Host smart-572fd5c2-dd6b-4f25-8ce0-e643bb7cea16
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=567860596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.567860596
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.495322055
Short name T1363
Test name
Test status
Simulation time 178803744 ps
CPU time 0.84 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:48 PM PDT 24
Peak memory 207376 kb
Host smart-43a845d4-61b7-45c7-a516-afa78950d26b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=495322055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.495322055
Directory /workspace/48.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.3634162631
Short name T1887
Test name
Test status
Simulation time 162495796 ps
CPU time 0.87 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207360 kb
Host smart-09f8ae99-99e8-4699-97e4-e7c91ff847f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36341
62631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.3634162631
Directory /workspace/48.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_nak_trans.2005974009
Short name T1322
Test name
Test status
Simulation time 186648871 ps
CPU time 0.92 seconds
Started Aug 02 05:34:52 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 207388 kb
Host smart-b6963a2d-edeb-4ae0-9686-b5925b4adeaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20059
74009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.2005974009
Directory /workspace/48.usbdev_nak_trans/latest


Test location /workspace/coverage/default/48.usbdev_out_iso.2990705180
Short name T1657
Test name
Test status
Simulation time 150576842 ps
CPU time 0.83 seconds
Started Aug 02 05:34:52 PM PDT 24
Finished Aug 02 05:34:52 PM PDT 24
Peak memory 207428 kb
Host smart-8277bb54-5b96-4136-a406-4ff3e454f5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29907
05180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2990705180
Directory /workspace/48.usbdev_out_iso/latest


Test location /workspace/coverage/default/48.usbdev_out_stall.3142218260
Short name T2350
Test name
Test status
Simulation time 189756281 ps
CPU time 0.83 seconds
Started Aug 02 05:34:45 PM PDT 24
Finished Aug 02 05:34:46 PM PDT 24
Peak memory 207356 kb
Host smart-eb175227-2567-430b-a7b3-10c05821b500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31422
18260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3142218260
Directory /workspace/48.usbdev_out_stall/latest


Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3237338600
Short name T1758
Test name
Test status
Simulation time 169398781 ps
CPU time 0.84 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:48 PM PDT 24
Peak memory 207340 kb
Host smart-e730d97b-19c5-437b-913f-0d70022b2e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32373
38600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3237338600
Directory /workspace/48.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/48.usbdev_pending_in_trans.1688325722
Short name T2174
Test name
Test status
Simulation time 147301418 ps
CPU time 0.8 seconds
Started Aug 02 05:34:52 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 207392 kb
Host smart-1de41ae3-c04c-461e-9403-815dca249e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16883
25722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.1688325722
Directory /workspace/48.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.4064453378
Short name T1638
Test name
Test status
Simulation time 270113071 ps
CPU time 1.07 seconds
Started Aug 02 05:34:52 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 207404 kb
Host smart-37fd54bd-d070-48f7-bec3-c40450f77704
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4064453378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.4064453378
Directory /workspace/48.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3985546425
Short name T2217
Test name
Test status
Simulation time 137720850 ps
CPU time 0.8 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:34:47 PM PDT 24
Peak memory 207372 kb
Host smart-ebe3527f-00f2-4916-935b-c8fad8547b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39855
46425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3985546425
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.1598322264
Short name T1178
Test name
Test status
Simulation time 49035588 ps
CPU time 0.69 seconds
Started Aug 02 05:34:33 PM PDT 24
Finished Aug 02 05:34:34 PM PDT 24
Peak memory 207380 kb
Host smart-28c9a2bf-6e95-4ee9-82eb-31c93d59b0e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15983
22264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.1598322264
Directory /workspace/48.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3771832224
Short name T2109
Test name
Test status
Simulation time 22988222446 ps
CPU time 55.57 seconds
Started Aug 02 05:34:51 PM PDT 24
Finished Aug 02 05:35:47 PM PDT 24
Peak memory 215908 kb
Host smart-79a86cb3-97da-47c0-9377-111810ad1d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37718
32224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3771832224
Directory /workspace/48.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/48.usbdev_pkt_received.2371624542
Short name T2365
Test name
Test status
Simulation time 159955817 ps
CPU time 0.86 seconds
Started Aug 02 05:34:59 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 207396 kb
Host smart-847a8de3-3f2b-4451-bc74-9ad1845fb4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23716
24542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2371624542
Directory /workspace/48.usbdev_pkt_received/latest


Test location /workspace/coverage/default/48.usbdev_pkt_sent.1117944497
Short name T1138
Test name
Test status
Simulation time 177048243 ps
CPU time 0.91 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 206896 kb
Host smart-9df560c7-3cd9-4950-9ba4-28a99ff12990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11179
44497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1117944497
Directory /workspace/48.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.4262684112
Short name T649
Test name
Test status
Simulation time 152754443 ps
CPU time 0.86 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207348 kb
Host smart-1319bab4-5f0d-4b6d-993b-f96abcdc8d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42626
84112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.4262684112
Directory /workspace/48.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.286471240
Short name T2890
Test name
Test status
Simulation time 197998406 ps
CPU time 0.88 seconds
Started Aug 02 05:34:54 PM PDT 24
Finished Aug 02 05:34:55 PM PDT 24
Peak memory 207424 kb
Host smart-b4199630-1f18-485b-bb92-e545860ba31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28647
1240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.286471240
Directory /workspace/48.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/48.usbdev_rx_crc_err.2465140121
Short name T1234
Test name
Test status
Simulation time 136232814 ps
CPU time 0.82 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207308 kb
Host smart-46a935e6-41bb-4a2e-9c9a-359255ff37d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24651
40121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.2465140121
Directory /workspace/48.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/48.usbdev_rx_full.794029739
Short name T308
Test name
Test status
Simulation time 353449495 ps
CPU time 1.3 seconds
Started Aug 02 05:34:34 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 207320 kb
Host smart-40ae1585-f8f9-4763-8e9d-e0349ce26f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79402
9739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_full.794029739
Directory /workspace/48.usbdev_rx_full/latest


Test location /workspace/coverage/default/48.usbdev_setup_stage.205433827
Short name T2736
Test name
Test status
Simulation time 167086065 ps
CPU time 0.81 seconds
Started Aug 02 05:34:59 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 207428 kb
Host smart-5cef4818-f896-4c62-9558-c57ba2b50627
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20543
3827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.205433827
Directory /workspace/48.usbdev_setup_stage/latest


Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3815976053
Short name T698
Test name
Test status
Simulation time 153244953 ps
CPU time 0.88 seconds
Started Aug 02 05:34:44 PM PDT 24
Finished Aug 02 05:34:45 PM PDT 24
Peak memory 207336 kb
Host smart-b21c3776-2246-49be-9136-c4b5e424a780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38159
76053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3815976053
Directory /workspace/48.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/48.usbdev_smoke.2731587321
Short name T2838
Test name
Test status
Simulation time 211433281 ps
CPU time 1.01 seconds
Started Aug 02 05:34:45 PM PDT 24
Finished Aug 02 05:34:46 PM PDT 24
Peak memory 207432 kb
Host smart-f237217b-7ec5-4302-962a-6861ecc117de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27315
87321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2731587321
Directory /workspace/48.usbdev_smoke/latest


Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1985522619
Short name T2063
Test name
Test status
Simulation time 3331053688 ps
CPU time 33.93 seconds
Started Aug 02 05:34:50 PM PDT 24
Finished Aug 02 05:35:24 PM PDT 24
Peak memory 224020 kb
Host smart-cefeeb1d-8449-4d36-85bd-5623df0a8559
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1985522619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1985522619
Directory /workspace/48.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3897527728
Short name T1683
Test name
Test status
Simulation time 196216197 ps
CPU time 0.9 seconds
Started Aug 02 05:34:55 PM PDT 24
Finished Aug 02 05:34:56 PM PDT 24
Peak memory 207416 kb
Host smart-05325d1b-3158-465d-9ae4-bfbe8475ff1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38975
27728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3897527728
Directory /workspace/48.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/48.usbdev_stall_trans.4077559275
Short name T2835
Test name
Test status
Simulation time 176893716 ps
CPU time 0.88 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:48 PM PDT 24
Peak memory 207372 kb
Host smart-c86c8db2-3699-45db-aa83-520c11c09dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40775
59275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.4077559275
Directory /workspace/48.usbdev_stall_trans/latest


Test location /workspace/coverage/default/48.usbdev_stream_len_max.262248730
Short name T2409
Test name
Test status
Simulation time 1025273936 ps
CPU time 2.34 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207500 kb
Host smart-1b5f4642-ae07-46fd-897f-5e6ea88d893e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26224
8730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.262248730
Directory /workspace/48.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/48.usbdev_streaming_out.421536160
Short name T619
Test name
Test status
Simulation time 2723329371 ps
CPU time 27.23 seconds
Started Aug 02 05:34:53 PM PDT 24
Finished Aug 02 05:35:20 PM PDT 24
Peak memory 217424 kb
Host smart-42b18f44-d046-4c80-85ef-91a590c11cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42153
6160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.421536160
Directory /workspace/48.usbdev_streaming_out/latest


Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.1803959402
Short name T25
Test name
Test status
Simulation time 415943600 ps
CPU time 8.04 seconds
Started Aug 02 05:34:45 PM PDT 24
Finished Aug 02 05:34:54 PM PDT 24
Peak memory 207568 kb
Host smart-adbe3d3e-8f07-4e35-9be1-38c6bae69854
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803959402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_hos
t_handshake.1803959402
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/49.usbdev_alert_test.1550746549
Short name T1556
Test name
Test status
Simulation time 39531968 ps
CPU time 0.68 seconds
Started Aug 02 05:34:55 PM PDT 24
Finished Aug 02 05:34:56 PM PDT 24
Peak memory 207476 kb
Host smart-f02a7edc-8ccf-4be3-8e2f-7b95d658ac01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1550746549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1550746549
Directory /workspace/49.usbdev_alert_test/latest


Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3797824434
Short name T1466
Test name
Test status
Simulation time 9675294467 ps
CPU time 11.77 seconds
Started Aug 02 05:34:38 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 207752 kb
Host smart-0948d02a-6a7f-4890-8301-d4b2e49c42bd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797824434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_disconnect.3797824434
Directory /workspace/49.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2024973925
Short name T1843
Test name
Test status
Simulation time 14168038192 ps
CPU time 15.97 seconds
Started Aug 02 05:34:43 PM PDT 24
Finished Aug 02 05:34:59 PM PDT 24
Peak memory 215864 kb
Host smart-aacd533e-22ff-42ce-b411-6794691c4d9a
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024973925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2024973925
Directory /workspace/49.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3295871622
Short name T1891
Test name
Test status
Simulation time 29646309716 ps
CPU time 32.05 seconds
Started Aug 02 05:34:31 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207700 kb
Host smart-d243ddc7-59e9-42ff-8721-cd73ae4da2fc
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295871622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_a
on_wake_resume.3295871622
Directory /workspace/49.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/49.usbdev_av_buffer.2549401942
Short name T2897
Test name
Test status
Simulation time 167581193 ps
CPU time 0.86 seconds
Started Aug 02 05:34:38 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 207384 kb
Host smart-2066efcb-c959-4d23-a079-f0faca6c1bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25494
01942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.2549401942
Directory /workspace/49.usbdev_av_buffer/latest


Test location /workspace/coverage/default/49.usbdev_bitstuff_err.4145621240
Short name T2782
Test name
Test status
Simulation time 161856170 ps
CPU time 0.85 seconds
Started Aug 02 05:34:35 PM PDT 24
Finished Aug 02 05:34:35 PM PDT 24
Peak memory 207308 kb
Host smart-55f8a3c6-120c-44ad-8469-5f9945807d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41456
21240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.4145621240
Directory /workspace/49.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.299952453
Short name T694
Test name
Test status
Simulation time 403110252 ps
CPU time 1.38 seconds
Started Aug 02 05:34:42 PM PDT 24
Finished Aug 02 05:34:43 PM PDT 24
Peak memory 207392 kb
Host smart-6c88c596-f8cb-4a72-ae84-361fc534e622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29995
2453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.299952453
Directory /workspace/49.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.719642140
Short name T1270
Test name
Test status
Simulation time 1064664786 ps
CPU time 2.8 seconds
Started Aug 02 05:34:52 PM PDT 24
Finished Aug 02 05:34:55 PM PDT 24
Peak memory 207616 kb
Host smart-0604fdbd-69ba-40f8-b686-3f002f8d96d5
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=719642140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.719642140
Directory /workspace/49.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/49.usbdev_device_timeout.1002991582
Short name T784
Test name
Test status
Simulation time 2204978738 ps
CPU time 15.23 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207740 kb
Host smart-3f801fbb-ccfc-4ce0-8832-4e26e099fb4d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002991582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_timeout.1002991582
Directory /workspace/49.usbdev_device_timeout/latest


Test location /workspace/coverage/default/49.usbdev_disable_endpoint.2390159941
Short name T2096
Test name
Test status
Simulation time 651107738 ps
CPU time 1.59 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207412 kb
Host smart-aa224270-7c94-44e6-9030-619632acbbc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23901
59941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.2390159941
Directory /workspace/49.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/49.usbdev_disconnected.1147042985
Short name T2137
Test name
Test status
Simulation time 154713052 ps
CPU time 0.79 seconds
Started Aug 02 05:34:45 PM PDT 24
Finished Aug 02 05:34:46 PM PDT 24
Peak memory 207412 kb
Host smart-fdf0ad55-be74-4864-b8cd-938e54d75bcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11470
42985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1147042985
Directory /workspace/49.usbdev_disconnected/latest


Test location /workspace/coverage/default/49.usbdev_enable.3685281662
Short name T1482
Test name
Test status
Simulation time 92836728 ps
CPU time 0.72 seconds
Started Aug 02 05:34:41 PM PDT 24
Finished Aug 02 05:34:42 PM PDT 24
Peak memory 207348 kb
Host smart-36b2c159-e52b-4081-88d9-6f8dd3a89cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36852
81662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3685281662
Directory /workspace/49.usbdev_enable/latest


Test location /workspace/coverage/default/49.usbdev_endpoint_access.3081458099
Short name T3097
Test name
Test status
Simulation time 877564004 ps
CPU time 2.2 seconds
Started Aug 02 05:34:57 PM PDT 24
Finished Aug 02 05:34:59 PM PDT 24
Peak memory 207628 kb
Host smart-d4cef1d3-4809-424b-8760-18cc5c148f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30814
58099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3081458099
Directory /workspace/49.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/49.usbdev_endpoint_types.1590769062
Short name T1946
Test name
Test status
Simulation time 153282153 ps
CPU time 0.87 seconds
Started Aug 02 05:34:44 PM PDT 24
Finished Aug 02 05:34:44 PM PDT 24
Peak memory 207404 kb
Host smart-043dcf77-0849-4072-add3-b6133358485a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1590769062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_types.1590769062
Directory /workspace/49.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/49.usbdev_fifo_rst.3072266091
Short name T934
Test name
Test status
Simulation time 178255935 ps
CPU time 2.12 seconds
Started Aug 02 05:34:36 PM PDT 24
Finished Aug 02 05:34:38 PM PDT 24
Peak memory 207608 kb
Host smart-1c46a5f8-ed67-4bba-bd02-61c24cca2803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30722
66091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.3072266091
Directory /workspace/49.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/49.usbdev_in_iso.3855969934
Short name T1534
Test name
Test status
Simulation time 227228955 ps
CPU time 1.02 seconds
Started Aug 02 05:34:37 PM PDT 24
Finished Aug 02 05:34:39 PM PDT 24
Peak memory 207536 kb
Host smart-12bdc973-cf52-438b-9111-f02a77817335
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3855969934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.3855969934
Directory /workspace/49.usbdev_in_iso/latest


Test location /workspace/coverage/default/49.usbdev_in_stall.3721353422
Short name T1471
Test name
Test status
Simulation time 142379228 ps
CPU time 0.81 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 206948 kb
Host smart-2f76c77c-86dc-4722-bcdf-0fda0f86e352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37213
53422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3721353422
Directory /workspace/49.usbdev_in_stall/latest


Test location /workspace/coverage/default/49.usbdev_in_trans.2842102016
Short name T2589
Test name
Test status
Simulation time 249047153 ps
CPU time 1.01 seconds
Started Aug 02 05:34:49 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 207380 kb
Host smart-29334b4b-e3e3-4b05-8f36-7bceab7fd2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28421
02016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.2842102016
Directory /workspace/49.usbdev_in_trans/latest


Test location /workspace/coverage/default/49.usbdev_invalid_sync.1319370921
Short name T2976
Test name
Test status
Simulation time 4262468911 ps
CPU time 120.56 seconds
Started Aug 02 05:34:45 PM PDT 24
Finished Aug 02 05:36:46 PM PDT 24
Peak memory 223884 kb
Host smart-fc796203-4067-429a-89a6-e24a58f3701e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1319370921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1319370921
Directory /workspace/49.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/49.usbdev_link_in_err.2501449283
Short name T1051
Test name
Test status
Simulation time 189420596 ps
CPU time 0.9 seconds
Started Aug 02 05:34:42 PM PDT 24
Finished Aug 02 05:34:43 PM PDT 24
Peak memory 207356 kb
Host smart-012d7000-371c-40ec-a010-3418eb9daf82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25014
49283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2501449283
Directory /workspace/49.usbdev_link_in_err/latest


Test location /workspace/coverage/default/49.usbdev_link_resume.3623299316
Short name T3079
Test name
Test status
Simulation time 30663369616 ps
CPU time 46.21 seconds
Started Aug 02 05:34:58 PM PDT 24
Finished Aug 02 05:35:44 PM PDT 24
Peak memory 207696 kb
Host smart-3e715b5f-1f78-43e5-ac22-cee2d49137f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36232
99316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.3623299316
Directory /workspace/49.usbdev_link_resume/latest


Test location /workspace/coverage/default/49.usbdev_link_suspend.1230861377
Short name T2810
Test name
Test status
Simulation time 5304880303 ps
CPU time 6.84 seconds
Started Aug 02 05:34:58 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 215960 kb
Host smart-13846bcc-fb36-48b7-9768-45d66c1426a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12308
61377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.1230861377
Directory /workspace/49.usbdev_link_suspend/latest


Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.2322376186
Short name T1956
Test name
Test status
Simulation time 4405797715 ps
CPU time 31.44 seconds
Started Aug 02 05:34:54 PM PDT 24
Finished Aug 02 05:35:26 PM PDT 24
Peak memory 224072 kb
Host smart-0c7ea2a5-7649-495c-8e43-2c2dd15c7c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23223
76186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2322376186
Directory /workspace/49.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.1300130175
Short name T2806
Test name
Test status
Simulation time 2727257287 ps
CPU time 20.19 seconds
Started Aug 02 05:34:54 PM PDT 24
Finished Aug 02 05:35:14 PM PDT 24
Peak memory 215844 kb
Host smart-8d640d48-dac4-4c22-ab85-69b629292144
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1300130175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.1300130175
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3894532920
Short name T3003
Test name
Test status
Simulation time 241442553 ps
CPU time 1 seconds
Started Aug 02 05:34:55 PM PDT 24
Finished Aug 02 05:34:56 PM PDT 24
Peak memory 207376 kb
Host smart-ef181412-d1c0-4bc5-9489-c1799d1bbe26
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3894532920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3894532920
Directory /workspace/49.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.521304369
Short name T993
Test name
Test status
Simulation time 218120682 ps
CPU time 0.97 seconds
Started Aug 02 05:34:50 PM PDT 24
Finished Aug 02 05:34:51 PM PDT 24
Peak memory 207432 kb
Host smart-3a581ca6-dfca-42b7-85e8-e3b6f6f37e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52130
4369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.521304369
Directory /workspace/49.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.2828919110
Short name T1069
Test name
Test status
Simulation time 2524528274 ps
CPU time 25.39 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:25 PM PDT 24
Peak memory 215908 kb
Host smart-2da028a8-b80b-43c8-ae59-5936887a4db8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2828919110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.2828919110
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.2587604316
Short name T975
Test name
Test status
Simulation time 165016715 ps
CPU time 0.87 seconds
Started Aug 02 05:34:45 PM PDT 24
Finished Aug 02 05:34:46 PM PDT 24
Peak memory 207372 kb
Host smart-6d1d9237-339d-428f-9d2b-d87e696849b3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2587604316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.2587604316
Directory /workspace/49.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1979689450
Short name T2755
Test name
Test status
Simulation time 151140419 ps
CPU time 0.83 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207404 kb
Host smart-8a2ecd9c-e567-4442-84f5-495410be6e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19796
89450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1979689450
Directory /workspace/49.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_nak_trans.4199621219
Short name T148
Test name
Test status
Simulation time 226978933 ps
CPU time 0.99 seconds
Started Aug 02 05:34:57 PM PDT 24
Finished Aug 02 05:34:59 PM PDT 24
Peak memory 207416 kb
Host smart-280979f7-3f98-404c-badc-b7edcba4f194
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41996
21219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.4199621219
Directory /workspace/49.usbdev_nak_trans/latest


Test location /workspace/coverage/default/49.usbdev_out_iso.817200879
Short name T2175
Test name
Test status
Simulation time 155809560 ps
CPU time 0.83 seconds
Started Aug 02 05:34:59 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 207384 kb
Host smart-94e24bd9-79f6-4e59-941d-682522054548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81720
0879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.817200879
Directory /workspace/49.usbdev_out_iso/latest


Test location /workspace/coverage/default/49.usbdev_out_stall.595646401
Short name T963
Test name
Test status
Simulation time 173794006 ps
CPU time 0.86 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207372 kb
Host smart-a900bd2d-4296-49e6-a521-7a7a43159d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59564
6401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.595646401
Directory /workspace/49.usbdev_out_stall/latest


Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3153360312
Short name T1434
Test name
Test status
Simulation time 175174002 ps
CPU time 0.9 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207420 kb
Host smart-6b6aa37d-a0d8-4ef3-95b5-e55381754a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31533
60312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3153360312
Directory /workspace/49.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/49.usbdev_pending_in_trans.3745454649
Short name T2671
Test name
Test status
Simulation time 169433901 ps
CPU time 0.89 seconds
Started Aug 02 05:34:58 PM PDT 24
Finished Aug 02 05:34:59 PM PDT 24
Peak memory 207408 kb
Host smart-b5efa2cf-064e-402d-9ed2-7efbd84c595d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37454
54649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.3745454649
Directory /workspace/49.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.1238781476
Short name T1613
Test name
Test status
Simulation time 229374806 ps
CPU time 1.07 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207404 kb
Host smart-52badea4-eff3-4067-95fc-260bc04e35c0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1238781476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.1238781476
Directory /workspace/49.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3104611262
Short name T1947
Test name
Test status
Simulation time 159443280 ps
CPU time 0.84 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207368 kb
Host smart-a38bd5b2-47e1-4163-8e46-b2940c6126ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31046
11262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3104611262
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3982590033
Short name T1977
Test name
Test status
Simulation time 8438012191 ps
CPU time 19.93 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:20 PM PDT 24
Peak memory 215824 kb
Host smart-ba06b9fc-7854-4fa7-86a2-236dd8d06182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39825
90033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3982590033
Directory /workspace/49.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/49.usbdev_pkt_received.3052755313
Short name T1262
Test name
Test status
Simulation time 200701663 ps
CPU time 1.02 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207336 kb
Host smart-e5ebd9bf-893f-4c1d-b715-5b1f70a2a2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30527
55313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3052755313
Directory /workspace/49.usbdev_pkt_received/latest


Test location /workspace/coverage/default/49.usbdev_pkt_sent.2101583229
Short name T1568
Test name
Test status
Simulation time 196335195 ps
CPU time 0.99 seconds
Started Aug 02 05:34:57 PM PDT 24
Finished Aug 02 05:34:58 PM PDT 24
Peak memory 207364 kb
Host smart-7a51b1f9-60a2-448c-a242-4c2a52e559b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21015
83229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2101583229
Directory /workspace/49.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3938283420
Short name T3012
Test name
Test status
Simulation time 251986916 ps
CPU time 0.96 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207360 kb
Host smart-0eb36115-3436-4e2b-a3e6-ea6b25a4eb84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39382
83420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3938283420
Directory /workspace/49.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.1934651773
Short name T1723
Test name
Test status
Simulation time 208668630 ps
CPU time 0.9 seconds
Started Aug 02 05:34:46 PM PDT 24
Finished Aug 02 05:34:47 PM PDT 24
Peak memory 207424 kb
Host smart-9c48e546-bb3c-48b3-ad06-ec349fc0c611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19346
51773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.1934651773
Directory /workspace/49.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/49.usbdev_rx_crc_err.241941203
Short name T1423
Test name
Test status
Simulation time 139270329 ps
CPU time 0.8 seconds
Started Aug 02 05:34:52 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 207328 kb
Host smart-6004bc94-63a4-4a95-91b1-443231bdd77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
1203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.241941203
Directory /workspace/49.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/49.usbdev_rx_full.2015336752
Short name T1231
Test name
Test status
Simulation time 247522847 ps
CPU time 1 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207368 kb
Host smart-21bfe31e-7173-48e9-a24a-0bf851cc3324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20153
36752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_full.2015336752
Directory /workspace/49.usbdev_rx_full/latest


Test location /workspace/coverage/default/49.usbdev_setup_stage.3286547294
Short name T1772
Test name
Test status
Simulation time 167061193 ps
CPU time 0.84 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207340 kb
Host smart-bdb10309-933a-4b13-9378-a4b1e7d49d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32865
47294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3286547294
Directory /workspace/49.usbdev_setup_stage/latest


Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.1195365318
Short name T1748
Test name
Test status
Simulation time 240222247 ps
CPU time 0.91 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:35:17 PM PDT 24
Peak memory 207344 kb
Host smart-6a97496a-3099-403e-ac5a-ab4a9f1c2250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11953
65318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.1195365318
Directory /workspace/49.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/49.usbdev_smoke.2404832370
Short name T679
Test name
Test status
Simulation time 215455979 ps
CPU time 0.98 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207352 kb
Host smart-ff0843c4-a15e-4af4-8916-4655a6e843ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24048
32370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.2404832370
Directory /workspace/49.usbdev_smoke/latest


Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.937960918
Short name T646
Test name
Test status
Simulation time 2263339111 ps
CPU time 59.86 seconds
Started Aug 02 05:34:54 PM PDT 24
Finished Aug 02 05:35:54 PM PDT 24
Peak memory 217344 kb
Host smart-e5c49dea-3031-4dee-abf2-42f4d6234a5f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=937960918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.937960918
Directory /workspace/49.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.452016148
Short name T1166
Test name
Test status
Simulation time 178070246 ps
CPU time 0.88 seconds
Started Aug 02 05:34:49 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 207464 kb
Host smart-380992b0-1233-4fdb-ba93-7ebfa7bdfba5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45201
6148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.452016148
Directory /workspace/49.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/49.usbdev_stall_trans.602760422
Short name T791
Test name
Test status
Simulation time 159852784 ps
CPU time 0.87 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207400 kb
Host smart-7f03dba4-29df-4602-bb36-8a7a5d6c16f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60276
0422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.602760422
Directory /workspace/49.usbdev_stall_trans/latest


Test location /workspace/coverage/default/49.usbdev_stream_len_max.4261819492
Short name T1368
Test name
Test status
Simulation time 664641009 ps
CPU time 1.87 seconds
Started Aug 02 05:34:50 PM PDT 24
Finished Aug 02 05:34:51 PM PDT 24
Peak memory 207372 kb
Host smart-5d818656-f021-412b-b924-e22cf0244df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42618
19492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.4261819492
Directory /workspace/49.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/49.usbdev_streaming_out.4142353051
Short name T1298
Test name
Test status
Simulation time 3292444578 ps
CPU time 24.49 seconds
Started Aug 02 05:34:53 PM PDT 24
Finished Aug 02 05:35:17 PM PDT 24
Peak memory 215912 kb
Host smart-31d0d6a6-289e-4f26-a8a5-668a1de7f028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41423
53051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.4142353051
Directory /workspace/49.usbdev_streaming_out/latest


Test location /workspace/coverage/default/49.usbdev_timeout_missing_host_handshake.3584542739
Short name T222
Test name
Test status
Simulation time 746016142 ps
CPU time 5.01 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:52 PM PDT 24
Peak memory 207596 kb
Host smart-2108a6af-c511-4f93-a968-e82a250f50cc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584542739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_timeout_missing_hos
t_handshake.3584542739
Directory /workspace/49.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/5.usbdev_alert_test.3926264524
Short name T741
Test name
Test status
Simulation time 40976843 ps
CPU time 0.66 seconds
Started Aug 02 05:28:19 PM PDT 24
Finished Aug 02 05:28:20 PM PDT 24
Peak memory 207440 kb
Host smart-67908047-fbac-4a64-9ca8-4c7de05a1e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3926264524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3926264524
Directory /workspace/5.usbdev_alert_test/latest


Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.4092954670
Short name T1459
Test name
Test status
Simulation time 3867425745 ps
CPU time 5.82 seconds
Started Aug 02 05:27:59 PM PDT 24
Finished Aug 02 05:28:05 PM PDT 24
Peak memory 215796 kb
Host smart-04c22c26-e07a-48d6-95ce-56e9f62e95a1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092954670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_disconnect.4092954670
Directory /workspace/5.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3433118040
Short name T928
Test name
Test status
Simulation time 20482238610 ps
CPU time 22.77 seconds
Started Aug 02 05:28:01 PM PDT 24
Finished Aug 02 05:28:24 PM PDT 24
Peak memory 207692 kb
Host smart-bf44c13e-214e-45d1-8bb9-05dd37438739
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433118040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3433118040
Directory /workspace/5.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3030191874
Short name T1254
Test name
Test status
Simulation time 24195980859 ps
CPU time 29.23 seconds
Started Aug 02 05:28:03 PM PDT 24
Finished Aug 02 05:28:32 PM PDT 24
Peak memory 215844 kb
Host smart-e18e4ec7-b614-47b7-8d62-f968c14e5462
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030191874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_ao
n_wake_resume.3030191874
Directory /workspace/5.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/5.usbdev_av_buffer.3473597074
Short name T2594
Test name
Test status
Simulation time 170280901 ps
CPU time 0.91 seconds
Started Aug 02 05:28:00 PM PDT 24
Finished Aug 02 05:28:01 PM PDT 24
Peak memory 207344 kb
Host smart-ecf2d755-1fb5-4141-9510-adafe17acb73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34735
97074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3473597074
Directory /workspace/5.usbdev_av_buffer/latest


Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2921625494
Short name T75
Test name
Test status
Simulation time 194225002 ps
CPU time 0.86 seconds
Started Aug 02 05:27:59 PM PDT 24
Finished Aug 02 05:28:00 PM PDT 24
Peak memory 207376 kb
Host smart-8df7652d-a268-4dbd-804d-c09ab609dcb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29216
25494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2921625494
Directory /workspace/5.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.920714220
Short name T2776
Test name
Test status
Simulation time 213963274 ps
CPU time 1.06 seconds
Started Aug 02 05:28:10 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 207368 kb
Host smart-d0daa3da-1f50-4871-b67a-5c62c76007ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92071
4220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.920714220
Directory /workspace/5.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1701577911
Short name T2665
Test name
Test status
Simulation time 756148968 ps
CPU time 2 seconds
Started Aug 02 05:28:09 PM PDT 24
Finished Aug 02 05:28:11 PM PDT 24
Peak memory 207348 kb
Host smart-55770ddd-4adb-4d99-a472-a29a01ada99e
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1701577911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1701577911
Directory /workspace/5.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/5.usbdev_device_address.1558547687
Short name T2656
Test name
Test status
Simulation time 26364922456 ps
CPU time 46.65 seconds
Started Aug 02 05:28:09 PM PDT 24
Finished Aug 02 05:28:56 PM PDT 24
Peak memory 207708 kb
Host smart-ea2d2813-ceb6-4d04-af3a-ed48a239429c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
47687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1558547687
Directory /workspace/5.usbdev_device_address/latest


Test location /workspace/coverage/default/5.usbdev_device_timeout.2924990849
Short name T1737
Test name
Test status
Simulation time 4241742580 ps
CPU time 27.83 seconds
Started Aug 02 05:28:08 PM PDT 24
Finished Aug 02 05:28:36 PM PDT 24
Peak memory 207668 kb
Host smart-6b367485-572c-4b3a-8777-65f72b6347c4
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924990849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_timeout.2924990849
Directory /workspace/5.usbdev_device_timeout/latest


Test location /workspace/coverage/default/5.usbdev_disable_endpoint.648004771
Short name T1591
Test name
Test status
Simulation time 775358264 ps
CPU time 1.89 seconds
Started Aug 02 05:28:12 PM PDT 24
Finished Aug 02 05:28:14 PM PDT 24
Peak memory 207284 kb
Host smart-581659ff-97e1-4e92-a39f-0aba0d34bfd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64800
4771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.648004771
Directory /workspace/5.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/5.usbdev_disconnected.3946727611
Short name T2018
Test name
Test status
Simulation time 179137346 ps
CPU time 0.9 seconds
Started Aug 02 05:28:14 PM PDT 24
Finished Aug 02 05:28:15 PM PDT 24
Peak memory 207432 kb
Host smart-24b7872c-4791-4c35-bf24-4a5e20e656ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39467
27611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.3946727611
Directory /workspace/5.usbdev_disconnected/latest


Test location /workspace/coverage/default/5.usbdev_enable.680467557
Short name T1065
Test name
Test status
Simulation time 57125441 ps
CPU time 0.73 seconds
Started Aug 02 05:28:12 PM PDT 24
Finished Aug 02 05:28:12 PM PDT 24
Peak memory 207272 kb
Host smart-fcb1a055-f2a6-4a02-b6da-7034a0b3adc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68046
7557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.680467557
Directory /workspace/5.usbdev_enable/latest


Test location /workspace/coverage/default/5.usbdev_endpoint_access.702832253
Short name T2465
Test name
Test status
Simulation time 741196192 ps
CPU time 2.17 seconds
Started Aug 02 05:28:14 PM PDT 24
Finished Aug 02 05:28:16 PM PDT 24
Peak memory 207716 kb
Host smart-ed775c72-3e44-41f8-b7e9-6fd6cd1a851c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70283
2253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.702832253
Directory /workspace/5.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/5.usbdev_endpoint_types.974629156
Short name T435
Test name
Test status
Simulation time 624080502 ps
CPU time 1.68 seconds
Started Aug 02 05:28:07 PM PDT 24
Finished Aug 02 05:28:09 PM PDT 24
Peak memory 207400 kb
Host smart-9c78beea-d5af-4572-9bcf-db0e300093ec
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=974629156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_types.974629156
Directory /workspace/5.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/5.usbdev_fifo_rst.2528335374
Short name T1561
Test name
Test status
Simulation time 337727077 ps
CPU time 2.23 seconds
Started Aug 02 05:28:08 PM PDT 24
Finished Aug 02 05:28:10 PM PDT 24
Peak memory 207592 kb
Host smart-855e6133-3e77-497b-bf28-3c8984a2b1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25283
35374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.2528335374
Directory /workspace/5.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/5.usbdev_in_iso.4075252918
Short name T1243
Test name
Test status
Simulation time 173287514 ps
CPU time 0.9 seconds
Started Aug 02 05:28:09 PM PDT 24
Finished Aug 02 05:28:10 PM PDT 24
Peak memory 207384 kb
Host smart-2fb8331f-4118-4536-bc57-1c1b2b8622c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4075252918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.4075252918
Directory /workspace/5.usbdev_in_iso/latest


Test location /workspace/coverage/default/5.usbdev_in_stall.1113975078
Short name T976
Test name
Test status
Simulation time 160656282 ps
CPU time 0.9 seconds
Started Aug 02 05:28:07 PM PDT 24
Finished Aug 02 05:28:08 PM PDT 24
Peak memory 207324 kb
Host smart-860636ed-e0bb-4bfe-8866-63abc2eb4c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11139
75078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1113975078
Directory /workspace/5.usbdev_in_stall/latest


Test location /workspace/coverage/default/5.usbdev_in_trans.1239413197
Short name T2220
Test name
Test status
Simulation time 215277098 ps
CPU time 0.91 seconds
Started Aug 02 05:28:08 PM PDT 24
Finished Aug 02 05:28:09 PM PDT 24
Peak memory 207396 kb
Host smart-541620f0-856f-4d34-9c30-d4daede9f64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12394
13197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1239413197
Directory /workspace/5.usbdev_in_trans/latest


Test location /workspace/coverage/default/5.usbdev_invalid_sync.3724474346
Short name T2765
Test name
Test status
Simulation time 4075326098 ps
CPU time 29.46 seconds
Started Aug 02 05:28:13 PM PDT 24
Finished Aug 02 05:28:43 PM PDT 24
Peak memory 217800 kb
Host smart-09a0cf4c-85f2-4b5e-a440-51c946339ba1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3724474346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3724474346
Directory /workspace/5.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/5.usbdev_iso_retraction.422953397
Short name T1474
Test name
Test status
Simulation time 7808118580 ps
CPU time 49.6 seconds
Started Aug 02 05:28:12 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 207588 kb
Host smart-32b7f4cb-689e-4065-84bd-acd27b5e09c2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=422953397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.422953397
Directory /workspace/5.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/5.usbdev_link_in_err.1075190348
Short name T2991
Test name
Test status
Simulation time 231123123 ps
CPU time 1.06 seconds
Started Aug 02 05:28:14 PM PDT 24
Finished Aug 02 05:28:15 PM PDT 24
Peak memory 207460 kb
Host smart-2946714b-50bd-473d-89d1-fcd2751c4035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10751
90348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1075190348
Directory /workspace/5.usbdev_link_in_err/latest


Test location /workspace/coverage/default/5.usbdev_link_resume.1609208848
Short name T743
Test name
Test status
Simulation time 22622529700 ps
CPU time 29.79 seconds
Started Aug 02 05:28:09 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207620 kb
Host smart-9415f138-e19b-40ee-9ea8-6a5ab49d050d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16092
08848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1609208848
Directory /workspace/5.usbdev_link_resume/latest


Test location /workspace/coverage/default/5.usbdev_link_suspend.3474778567
Short name T1681
Test name
Test status
Simulation time 3719216965 ps
CPU time 5.81 seconds
Started Aug 02 05:28:10 PM PDT 24
Finished Aug 02 05:28:16 PM PDT 24
Peak memory 216016 kb
Host smart-c7ee3565-12cb-4a0b-8c18-11f04d29fbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34747
78567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.3474778567
Directory /workspace/5.usbdev_link_suspend/latest


Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.2934508013
Short name T1112
Test name
Test status
Simulation time 3919453076 ps
CPU time 108.49 seconds
Started Aug 02 05:28:08 PM PDT 24
Finished Aug 02 05:29:56 PM PDT 24
Peak memory 218284 kb
Host smart-b956c655-9a5a-4afc-beee-17aa7f7c83a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29345
08013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.2934508013
Directory /workspace/5.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2311657583
Short name T2939
Test name
Test status
Simulation time 2230000150 ps
CPU time 64.47 seconds
Started Aug 02 05:28:08 PM PDT 24
Finished Aug 02 05:29:13 PM PDT 24
Peak memory 216944 kb
Host smart-cef923a9-d7c2-43a9-8868-850f03f7e1e2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2311657583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2311657583
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3181922196
Short name T1217
Test name
Test status
Simulation time 249753933 ps
CPU time 1.02 seconds
Started Aug 02 05:28:07 PM PDT 24
Finished Aug 02 05:28:08 PM PDT 24
Peak memory 207388 kb
Host smart-43220ada-4058-4078-9293-9a1e6804906e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3181922196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3181922196
Directory /workspace/5.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.619294268
Short name T1629
Test name
Test status
Simulation time 262830595 ps
CPU time 1.04 seconds
Started Aug 02 05:28:08 PM PDT 24
Finished Aug 02 05:28:09 PM PDT 24
Peak memory 207344 kb
Host smart-3c443bdc-b6cb-4aa8-9e37-3524b79cfa00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61929
4268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.619294268
Directory /workspace/5.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_max_non_iso_usb_traffic.2444342611
Short name T1969
Test name
Test status
Simulation time 2926808000 ps
CPU time 29.39 seconds
Started Aug 02 05:28:06 PM PDT 24
Finished Aug 02 05:28:36 PM PDT 24
Peak memory 217652 kb
Host smart-c20dd9ac-c002-4e1c-8b93-3f94e34dedaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24443
42611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_non_iso_usb_traffic.2444342611
Directory /workspace/5.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1121295198
Short name T1836
Test name
Test status
Simulation time 1926238080 ps
CPU time 53.1 seconds
Started Aug 02 05:28:09 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 217712 kb
Host smart-0a49896e-5ba7-4f3d-8db0-5b7323aebc26
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1121295198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1121295198
Directory /workspace/5.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.3178034643
Short name T645
Test name
Test status
Simulation time 3776799155 ps
CPU time 101.95 seconds
Started Aug 02 05:28:09 PM PDT 24
Finished Aug 02 05:29:51 PM PDT 24
Peak memory 215840 kb
Host smart-964ec852-2039-4d06-83ad-ddea2c520e8f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3178034643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.3178034643
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.718823258
Short name T2743
Test name
Test status
Simulation time 166969389 ps
CPU time 0.85 seconds
Started Aug 02 05:28:09 PM PDT 24
Finished Aug 02 05:28:10 PM PDT 24
Peak memory 207372 kb
Host smart-d36602b1-f6bc-4f7a-8547-fbcc1d8018ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=718823258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.718823258
Directory /workspace/5.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2863481477
Short name T1864
Test name
Test status
Simulation time 150369102 ps
CPU time 0.81 seconds
Started Aug 02 05:28:07 PM PDT 24
Finished Aug 02 05:28:08 PM PDT 24
Peak memory 207432 kb
Host smart-8e16ef44-261c-4843-86c8-96f7397c6558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28634
81477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2863481477
Directory /workspace/5.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_nak_trans.2513583334
Short name T1715
Test name
Test status
Simulation time 220175910 ps
CPU time 0.91 seconds
Started Aug 02 05:28:09 PM PDT 24
Finished Aug 02 05:28:10 PM PDT 24
Peak memory 207312 kb
Host smart-f285421c-f112-4915-a468-6c599334fb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25135
83334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.2513583334
Directory /workspace/5.usbdev_nak_trans/latest


Test location /workspace/coverage/default/5.usbdev_out_iso.3480258518
Short name T1495
Test name
Test status
Simulation time 196441109 ps
CPU time 0.9 seconds
Started Aug 02 05:28:13 PM PDT 24
Finished Aug 02 05:28:14 PM PDT 24
Peak memory 207460 kb
Host smart-ccf7f9de-3c81-4991-9667-767606cc681e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34802
58518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3480258518
Directory /workspace/5.usbdev_out_iso/latest


Test location /workspace/coverage/default/5.usbdev_out_stall.3327266435
Short name T2495
Test name
Test status
Simulation time 172045070 ps
CPU time 0.88 seconds
Started Aug 02 05:28:15 PM PDT 24
Finished Aug 02 05:28:16 PM PDT 24
Peak memory 207416 kb
Host smart-10259a72-a0e8-4ee3-8e5a-266fc5fd4436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33272
66435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.3327266435
Directory /workspace/5.usbdev_out_stall/latest


Test location /workspace/coverage/default/5.usbdev_out_trans_nak.2920709254
Short name T481
Test name
Test status
Simulation time 202596327 ps
CPU time 0.86 seconds
Started Aug 02 05:28:16 PM PDT 24
Finished Aug 02 05:28:17 PM PDT 24
Peak memory 207416 kb
Host smart-bba2feac-cfb0-4930-b6fd-d89de72a12f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207
09254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.2920709254
Directory /workspace/5.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/5.usbdev_pending_in_trans.4013756438
Short name T1036
Test name
Test status
Simulation time 179220229 ps
CPU time 0.92 seconds
Started Aug 02 05:28:20 PM PDT 24
Finished Aug 02 05:28:21 PM PDT 24
Peak memory 207416 kb
Host smart-bdf6174f-9a9d-463d-a919-0a38f7092008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40137
56438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.4013756438
Directory /workspace/5.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1177638057
Short name T2110
Test name
Test status
Simulation time 219426307 ps
CPU time 0.95 seconds
Started Aug 02 05:28:16 PM PDT 24
Finished Aug 02 05:28:17 PM PDT 24
Peak memory 206832 kb
Host smart-f0d3184c-d88d-4d65-a700-b7bdb519c969
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1177638057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1177638057
Directory /workspace/5.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.1326517555
Short name T3034
Test name
Test status
Simulation time 136518181 ps
CPU time 0.83 seconds
Started Aug 02 05:28:18 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 207368 kb
Host smart-520d58fa-e08f-491d-8289-9cd5b7c43b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13265
17555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.1326517555
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.1671513555
Short name T2229
Test name
Test status
Simulation time 38524223 ps
CPU time 0.7 seconds
Started Aug 02 05:28:13 PM PDT 24
Finished Aug 02 05:28:14 PM PDT 24
Peak memory 207320 kb
Host smart-245021f5-0940-4f9b-90ba-b6540bfa3411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16715
13555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.1671513555
Directory /workspace/5.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/5.usbdev_pkt_buffer.2890739264
Short name T291
Test name
Test status
Simulation time 14936322081 ps
CPU time 38.16 seconds
Started Aug 02 05:28:15 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 215848 kb
Host smart-3acf949a-d38a-42be-a8a3-5381ea80b0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28907
39264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.2890739264
Directory /workspace/5.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/5.usbdev_pkt_received.3459373084
Short name T3109
Test name
Test status
Simulation time 172724332 ps
CPU time 0.87 seconds
Started Aug 02 05:28:16 PM PDT 24
Finished Aug 02 05:28:17 PM PDT 24
Peak memory 207328 kb
Host smart-8cc874e8-1bb8-4a48-b20d-0995654d7d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34593
73084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.3459373084
Directory /workspace/5.usbdev_pkt_received/latest


Test location /workspace/coverage/default/5.usbdev_pkt_sent.2117420094
Short name T2343
Test name
Test status
Simulation time 199301070 ps
CPU time 0.92 seconds
Started Aug 02 05:28:16 PM PDT 24
Finished Aug 02 05:28:17 PM PDT 24
Peak memory 207340 kb
Host smart-2f05784e-4962-46c5-8ded-6d904eab32e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21174
20094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.2117420094
Directory /workspace/5.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.3652773395
Short name T1754
Test name
Test status
Simulation time 2777082721 ps
CPU time 22.12 seconds
Started Aug 02 05:28:18 PM PDT 24
Finished Aug 02 05:28:40 PM PDT 24
Peak memory 217888 kb
Host smart-6bd1e597-5bd2-4ee5-9473-d84be0215a3f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3652773395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.3652773395
Directory /workspace/5.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/5.usbdev_rand_suspends.518507452
Short name T998
Test name
Test status
Simulation time 9537189276 ps
CPU time 161.71 seconds
Started Aug 02 05:28:15 PM PDT 24
Finished Aug 02 05:30:57 PM PDT 24
Peak memory 218248 kb
Host smart-9701c2f4-799b-45c4-90c2-ffc6214b848c
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=518507452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.518507452
Directory /workspace/5.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.2307980523
Short name T2946
Test name
Test status
Simulation time 198860899 ps
CPU time 0.92 seconds
Started Aug 02 05:28:15 PM PDT 24
Finished Aug 02 05:28:16 PM PDT 24
Peak memory 207444 kb
Host smart-fff5d2ed-50a9-4132-99d3-8f5b2de4ad69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23079
80523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.2307980523
Directory /workspace/5.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.348092251
Short name T2341
Test name
Test status
Simulation time 208054729 ps
CPU time 0.94 seconds
Started Aug 02 05:28:18 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 207360 kb
Host smart-2d9ba766-be02-4937-8c73-f4021bb32582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34809
2251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.348092251
Directory /workspace/5.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/5.usbdev_rx_crc_err.244161724
Short name T1690
Test name
Test status
Simulation time 147296665 ps
CPU time 0.86 seconds
Started Aug 02 05:28:18 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 207356 kb
Host smart-3c2b8eab-031a-4839-a220-f1ab91077cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24416
1724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.244161724
Directory /workspace/5.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/5.usbdev_rx_full.2530774237
Short name T2926
Test name
Test status
Simulation time 241646266 ps
CPU time 1.09 seconds
Started Aug 02 05:28:18 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 207308 kb
Host smart-66bf268b-c7de-47b4-993d-51c1ef63a316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25307
74237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_full.2530774237
Directory /workspace/5.usbdev_rx_full/latest


Test location /workspace/coverage/default/5.usbdev_setup_stage.3659395606
Short name T2518
Test name
Test status
Simulation time 143319710 ps
CPU time 0.86 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:18 PM PDT 24
Peak memory 207336 kb
Host smart-fdfff82d-f1ba-4ab3-9abe-f02e737486dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36593
95606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.3659395606
Directory /workspace/5.usbdev_setup_stage/latest


Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.913632908
Short name T1522
Test name
Test status
Simulation time 156785196 ps
CPU time 0.86 seconds
Started Aug 02 05:28:20 PM PDT 24
Finished Aug 02 05:28:21 PM PDT 24
Peak memory 207416 kb
Host smart-85081827-a5ab-4b38-9bfa-357255e6dda5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91363
2908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.913632908
Directory /workspace/5.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/5.usbdev_smoke.4005571193
Short name T1617
Test name
Test status
Simulation time 266124843 ps
CPU time 1.02 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:18 PM PDT 24
Peak memory 207364 kb
Host smart-f75f9c97-e7d9-49b2-b257-9f425c60a44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40055
71193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.4005571193
Directory /workspace/5.usbdev_smoke/latest


Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.2380506811
Short name T1116
Test name
Test status
Simulation time 3089649034 ps
CPU time 22.97 seconds
Started Aug 02 05:28:14 PM PDT 24
Finished Aug 02 05:28:37 PM PDT 24
Peak memory 224100 kb
Host smart-9cf78d10-e804-4290-afcf-8b79d57333d7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2380506811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.2380506811
Directory /workspace/5.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.2306195155
Short name T36
Test name
Test status
Simulation time 181318595 ps
CPU time 0.87 seconds
Started Aug 02 05:28:18 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 207316 kb
Host smart-2ca379e3-2182-43af-9285-742fcadfac89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23061
95155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.2306195155
Directory /workspace/5.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/5.usbdev_stall_trans.2612011113
Short name T1379
Test name
Test status
Simulation time 173552940 ps
CPU time 0.91 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:18 PM PDT 24
Peak memory 207428 kb
Host smart-d9e12258-69ae-422c-a065-0e79dd970105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26120
11113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2612011113
Directory /workspace/5.usbdev_stall_trans/latest


Test location /workspace/coverage/default/5.usbdev_stream_len_max.574746802
Short name T2223
Test name
Test status
Simulation time 209207883 ps
CPU time 0.92 seconds
Started Aug 02 05:28:14 PM PDT 24
Finished Aug 02 05:28:15 PM PDT 24
Peak memory 207356 kb
Host smart-c3127d6a-6bb8-45ea-8b26-e674e82696e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57474
6802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.574746802
Directory /workspace/5.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/5.usbdev_streaming_out.827280092
Short name T1354
Test name
Test status
Simulation time 3574216805 ps
CPU time 34.72 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:52 PM PDT 24
Peak memory 215880 kb
Host smart-dab9876f-d2f7-4678-aa0b-82284d2465d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82728
0092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.827280092
Directory /workspace/5.usbdev_streaming_out/latest


Test location /workspace/coverage/default/5.usbdev_timeout_missing_host_handshake.633505797
Short name T2931
Test name
Test status
Simulation time 5669987912 ps
CPU time 47.81 seconds
Started Aug 02 05:28:09 PM PDT 24
Finished Aug 02 05:28:57 PM PDT 24
Peak memory 207712 kb
Host smart-2488ad05-83b7-422f-9ebe-571f2924f267
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633505797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_timeout_missing_host_
handshake.633505797
Directory /workspace/5.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/50.usbdev_endpoint_types.4280493531
Short name T2467
Test name
Test status
Simulation time 142863249 ps
CPU time 0.82 seconds
Started Aug 02 05:34:55 PM PDT 24
Finished Aug 02 05:34:56 PM PDT 24
Peak memory 207388 kb
Host smart-6e3f7d6b-c52c-43d8-867d-b1f881fec565
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4280493531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.usbdev_endpoint_types.4280493531
Directory /workspace/50.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/51.usbdev_endpoint_types.1781762804
Short name T87
Test name
Test status
Simulation time 255954780 ps
CPU time 1.02 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207392 kb
Host smart-64bd64cc-6851-4a38-a841-e39a57b44e02
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1781762804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.usbdev_endpoint_types.1781762804
Directory /workspace/51.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/52.usbdev_endpoint_types.156878787
Short name T2266
Test name
Test status
Simulation time 801275417 ps
CPU time 1.63 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207324 kb
Host smart-e897d17d-ccce-4264-b8d6-109659478c7e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=156878787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.usbdev_endpoint_types.156878787
Directory /workspace/52.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/53.usbdev_endpoint_types.1004543603
Short name T386
Test name
Test status
Simulation time 480659888 ps
CPU time 1.31 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 207312 kb
Host smart-50345608-dbb6-49ae-a946-da011468091b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1004543603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.usbdev_endpoint_types.1004543603
Directory /workspace/53.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/55.usbdev_endpoint_types.479353475
Short name T312
Test name
Test status
Simulation time 558676059 ps
CPU time 1.33 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207316 kb
Host smart-44c33ea5-ccc5-4c0a-ab1f-6ef9068d162d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=479353475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.usbdev_endpoint_types.479353475
Directory /workspace/55.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/56.usbdev_endpoint_types.1802310935
Short name T2045
Test name
Test status
Simulation time 183993012 ps
CPU time 0.95 seconds
Started Aug 02 05:34:50 PM PDT 24
Finished Aug 02 05:34:51 PM PDT 24
Peak memory 207392 kb
Host smart-56be93f3-308b-4e58-ba19-85406470bede
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1802310935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.usbdev_endpoint_types.1802310935
Directory /workspace/56.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/57.usbdev_endpoint_types.3370176650
Short name T427
Test name
Test status
Simulation time 705666823 ps
CPU time 1.69 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207344 kb
Host smart-d8d06579-a652-42c1-a797-7c4b67591931
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3370176650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.usbdev_endpoint_types.3370176650
Directory /workspace/57.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/58.usbdev_endpoint_types.3626468223
Short name T416
Test name
Test status
Simulation time 717105093 ps
CPU time 1.69 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 207356 kb
Host smart-4d025bb4-10cb-4476-8e23-c85c1fb4b094
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3626468223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.usbdev_endpoint_types.3626468223
Directory /workspace/58.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/59.usbdev_endpoint_types.1067792019
Short name T360
Test name
Test status
Simulation time 442113369 ps
CPU time 1.35 seconds
Started Aug 02 05:34:51 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 207372 kb
Host smart-7aa1a026-d35b-4423-b10d-e40fdf1a14a5
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1067792019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.usbdev_endpoint_types.1067792019
Directory /workspace/59.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/6.usbdev_alert_test.2005722685
Short name T3009
Test name
Test status
Simulation time 45111729 ps
CPU time 0.65 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207408 kb
Host smart-c1ed5bc0-b5ad-4ce7-9db8-ab4955156293
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2005722685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.2005722685
Directory /workspace/6.usbdev_alert_test/latest


Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.71441502
Short name T2729
Test name
Test status
Simulation time 9991094696 ps
CPU time 14.02 seconds
Started Aug 02 05:28:15 PM PDT 24
Finished Aug 02 05:28:29 PM PDT 24
Peak memory 207616 kb
Host smart-1b0bba2d-46ff-4d81-a759-aca9a0f289a0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71441502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_
wake_disconnect.71441502
Directory /workspace/6.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.977147065
Short name T597
Test name
Test status
Simulation time 20775036090 ps
CPU time 24.16 seconds
Started Aug 02 05:28:18 PM PDT 24
Finished Aug 02 05:28:42 PM PDT 24
Peak memory 207712 kb
Host smart-a84c2b43-226e-4e44-afab-ab9344c6e5ae
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=977147065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.977147065
Directory /workspace/6.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3208592074
Short name T1618
Test name
Test status
Simulation time 28847911155 ps
CPU time 35.09 seconds
Started Aug 02 05:28:14 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 207640 kb
Host smart-890c0c59-032d-49df-b9bd-704c9de9f4dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208592074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_ao
n_wake_resume.3208592074
Directory /workspace/6.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/6.usbdev_av_buffer.693392995
Short name T2710
Test name
Test status
Simulation time 152078501 ps
CPU time 0.85 seconds
Started Aug 02 05:28:15 PM PDT 24
Finished Aug 02 05:28:16 PM PDT 24
Peak memory 207404 kb
Host smart-5949706c-2794-4005-bfab-84f5ef2cdb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69339
2995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.693392995
Directory /workspace/6.usbdev_av_buffer/latest


Test location /workspace/coverage/default/6.usbdev_bitstuff_err.76626893
Short name T2499
Test name
Test status
Simulation time 182145420 ps
CPU time 0.86 seconds
Started Aug 02 05:28:16 PM PDT 24
Finished Aug 02 05:28:17 PM PDT 24
Peak memory 207388 kb
Host smart-8f1a112f-14bf-4a4b-8e69-e93f94457064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76626
893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.76626893
Directory /workspace/6.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.2079348984
Short name T2207
Test name
Test status
Simulation time 429237383 ps
CPU time 1.43 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 207392 kb
Host smart-603b8c76-13cb-422e-b4c0-5edd99b38b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20793
48984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.2079348984
Directory /workspace/6.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3919608017
Short name T2491
Test name
Test status
Simulation time 1050310383 ps
CPU time 3.03 seconds
Started Aug 02 05:28:15 PM PDT 24
Finished Aug 02 05:28:18 PM PDT 24
Peak memory 207572 kb
Host smart-29c01137-95f7-4575-92ae-91bdc7f2486f
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=3919608017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3919608017
Directory /workspace/6.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/6.usbdev_device_address.3244312488
Short name T182
Test name
Test status
Simulation time 33232657547 ps
CPU time 56.17 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:29:13 PM PDT 24
Peak memory 207640 kb
Host smart-21bb29bc-219b-468b-84e9-620d2a1e348a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32443
12488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3244312488
Directory /workspace/6.usbdev_device_address/latest


Test location /workspace/coverage/default/6.usbdev_device_timeout.2467541080
Short name T1703
Test name
Test status
Simulation time 6389958895 ps
CPU time 40.77 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:58 PM PDT 24
Peak memory 207712 kb
Host smart-f0579dad-9218-4462-add1-a91f8f9fa53e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467541080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_timeout.2467541080
Directory /workspace/6.usbdev_device_timeout/latest


Test location /workspace/coverage/default/6.usbdev_disable_endpoint.588722130
Short name T2905
Test name
Test status
Simulation time 604164174 ps
CPU time 1.99 seconds
Started Aug 02 05:28:20 PM PDT 24
Finished Aug 02 05:28:22 PM PDT 24
Peak memory 207380 kb
Host smart-5ca63960-cb36-40b6-ad63-4f6c0a669875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58872
2130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.588722130
Directory /workspace/6.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/6.usbdev_disconnected.2242502650
Short name T61
Test name
Test status
Simulation time 207318791 ps
CPU time 0.94 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 207400 kb
Host smart-af8dcdbf-4d05-4641-9d23-f0d4fe6c6646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22425
02650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2242502650
Directory /workspace/6.usbdev_disconnected/latest


Test location /workspace/coverage/default/6.usbdev_enable.3470617040
Short name T1240
Test name
Test status
Simulation time 37791116 ps
CPU time 0.72 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:18 PM PDT 24
Peak memory 207316 kb
Host smart-4bf2c6c1-9d53-472b-9c96-ebf6f148e7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34706
17040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3470617040
Directory /workspace/6.usbdev_enable/latest


Test location /workspace/coverage/default/6.usbdev_endpoint_access.1652547831
Short name T2303
Test name
Test status
Simulation time 923527468 ps
CPU time 2.27 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:19 PM PDT 24
Peak memory 207604 kb
Host smart-c23214cc-a046-401d-b413-a7e3a16d67a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16525
47831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1652547831
Directory /workspace/6.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/6.usbdev_endpoint_types.2975177999
Short name T342
Test name
Test status
Simulation time 197980828 ps
CPU time 0.99 seconds
Started Aug 02 05:28:14 PM PDT 24
Finished Aug 02 05:28:15 PM PDT 24
Peak memory 207336 kb
Host smart-2fe9f6b5-d61d-46a6-8850-eb3e440e2ce1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2975177999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_types.2975177999
Directory /workspace/6.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/6.usbdev_fifo_rst.2868836483
Short name T2922
Test name
Test status
Simulation time 190281214 ps
CPU time 2.13 seconds
Started Aug 02 05:28:16 PM PDT 24
Finished Aug 02 05:28:18 PM PDT 24
Peak memory 207524 kb
Host smart-1f76e0f6-ef83-4089-8685-0c0f24668d91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28688
36483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.2868836483
Directory /workspace/6.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/6.usbdev_in_iso.2294962509
Short name T627
Test name
Test status
Simulation time 212242056 ps
CPU time 1.12 seconds
Started Aug 02 05:28:24 PM PDT 24
Finished Aug 02 05:28:25 PM PDT 24
Peak memory 207516 kb
Host smart-f538cf4f-b00b-4341-97bb-0a6da9d19166
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2294962509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.2294962509
Directory /workspace/6.usbdev_in_iso/latest


Test location /workspace/coverage/default/6.usbdev_in_stall.2235446710
Short name T2492
Test name
Test status
Simulation time 145274013 ps
CPU time 0.88 seconds
Started Aug 02 05:28:28 PM PDT 24
Finished Aug 02 05:28:29 PM PDT 24
Peak memory 207360 kb
Host smart-c9d76e4c-9f49-4395-b29c-b7246ad3ff4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22354
46710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2235446710
Directory /workspace/6.usbdev_in_stall/latest


Test location /workspace/coverage/default/6.usbdev_in_trans.2175683804
Short name T2669
Test name
Test status
Simulation time 230147956 ps
CPU time 0.97 seconds
Started Aug 02 05:28:26 PM PDT 24
Finished Aug 02 05:28:27 PM PDT 24
Peak memory 207380 kb
Host smart-60d6d1ba-a9bb-41dd-bbeb-5eb6d3e05c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21756
83804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2175683804
Directory /workspace/6.usbdev_in_trans/latest


Test location /workspace/coverage/default/6.usbdev_invalid_sync.4160762672
Short name T2363
Test name
Test status
Simulation time 5685887509 ps
CPU time 41.66 seconds
Started Aug 02 05:28:16 PM PDT 24
Finished Aug 02 05:28:58 PM PDT 24
Peak memory 218276 kb
Host smart-44c81074-13de-49f3-aef7-78bcba62177e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4160762672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.4160762672
Directory /workspace/6.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/6.usbdev_iso_retraction.1586340788
Short name T2950
Test name
Test status
Simulation time 5539618412 ps
CPU time 38.02 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:29:03 PM PDT 24
Peak memory 207648 kb
Host smart-46445a26-90ee-4c51-9c2d-49376428dc47
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1586340788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.1586340788
Directory /workspace/6.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/6.usbdev_link_in_err.2730356896
Short name T1955
Test name
Test status
Simulation time 211593667 ps
CPU time 0.91 seconds
Started Aug 02 05:28:23 PM PDT 24
Finished Aug 02 05:28:24 PM PDT 24
Peak memory 207376 kb
Host smart-9d79769d-0f68-4335-9ddc-210b5c502938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27303
56896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2730356896
Directory /workspace/6.usbdev_link_in_err/latest


Test location /workspace/coverage/default/6.usbdev_link_resume.1998388026
Short name T115
Test name
Test status
Simulation time 5138540578 ps
CPU time 7.07 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:28:32 PM PDT 24
Peak memory 215868 kb
Host smart-f86a7ee9-c065-410b-9599-2701d031301b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19983
88026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.1998388026
Directory /workspace/6.usbdev_link_resume/latest


Test location /workspace/coverage/default/6.usbdev_link_suspend.3679270766
Short name T2351
Test name
Test status
Simulation time 10381737407 ps
CPU time 13.56 seconds
Started Aug 02 05:28:26 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207636 kb
Host smart-b8c55094-2a4f-4909-88c4-fb305041839f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36792
70766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.3679270766
Directory /workspace/6.usbdev_link_suspend/latest


Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.2187220871
Short name T1724
Test name
Test status
Simulation time 4075147604 ps
CPU time 39.53 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:29:04 PM PDT 24
Peak memory 218432 kb
Host smart-8abc8a46-c009-46aa-aca9-92f42f4d0441
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21872
20871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.2187220871
Directory /workspace/6.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.4128038794
Short name T570
Test name
Test status
Simulation time 3050049307 ps
CPU time 30.35 seconds
Started Aug 02 05:28:24 PM PDT 24
Finished Aug 02 05:28:55 PM PDT 24
Peak memory 215848 kb
Host smart-156ebf07-a382-4569-a212-61f592ebcaba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4128038794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.4128038794
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.1519454409
Short name T2672
Test name
Test status
Simulation time 287479669 ps
CPU time 1.18 seconds
Started Aug 02 05:28:33 PM PDT 24
Finished Aug 02 05:28:34 PM PDT 24
Peak memory 207216 kb
Host smart-2700ffa6-986a-4d99-a978-042516ddee08
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1519454409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.1519454409
Directory /workspace/6.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2146590235
Short name T1622
Test name
Test status
Simulation time 196647002 ps
CPU time 0.93 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:28:26 PM PDT 24
Peak memory 206828 kb
Host smart-ab14d915-2fde-40b6-8ed0-c7dc8b30b4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21465
90235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2146590235
Directory /workspace/6.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_max_non_iso_usb_traffic.3768909848
Short name T1832
Test name
Test status
Simulation time 3229584702 ps
CPU time 90.12 seconds
Started Aug 02 05:28:24 PM PDT 24
Finished Aug 02 05:29:54 PM PDT 24
Peak memory 224104 kb
Host smart-c99b71a3-66d4-4cb2-ae36-33b3d1cbfa9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37689
09848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_non_iso_usb_traffic.3768909848
Directory /workspace/6.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.3938299618
Short name T1714
Test name
Test status
Simulation time 2856803644 ps
CPU time 20.8 seconds
Started Aug 02 05:28:22 PM PDT 24
Finished Aug 02 05:28:43 PM PDT 24
Peak memory 207704 kb
Host smart-d20215cc-56f5-48ca-9693-3d07ae6c9fe8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3938299618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.3938299618
Directory /workspace/6.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3880271323
Short name T2768
Test name
Test status
Simulation time 1898036451 ps
CPU time 18.76 seconds
Started Aug 02 05:28:24 PM PDT 24
Finished Aug 02 05:28:43 PM PDT 24
Peak memory 217104 kb
Host smart-9cf6304a-3e11-492b-88f9-3b8bf47f2443
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3880271323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3880271323
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2672702959
Short name T2144
Test name
Test status
Simulation time 166865599 ps
CPU time 0.85 seconds
Started Aug 02 05:28:28 PM PDT 24
Finished Aug 02 05:28:29 PM PDT 24
Peak memory 207376 kb
Host smart-3aaf6181-04bb-45d6-8c7a-6cdc723361ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2672702959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2672702959
Directory /workspace/6.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3805500483
Short name T504
Test name
Test status
Simulation time 159892963 ps
CPU time 0.85 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:28:26 PM PDT 24
Peak memory 207404 kb
Host smart-cd49ce47-8e94-4fd0-ab24-06a5a2a8e120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38055
00483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3805500483
Directory /workspace/6.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_nak_trans.3048898620
Short name T34
Test name
Test status
Simulation time 205816866 ps
CPU time 0.93 seconds
Started Aug 02 05:28:27 PM PDT 24
Finished Aug 02 05:28:28 PM PDT 24
Peak memory 207392 kb
Host smart-88ad67bd-4af1-41a4-a076-28d75f5dca73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30488
98620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3048898620
Directory /workspace/6.usbdev_nak_trans/latest


Test location /workspace/coverage/default/6.usbdev_out_iso.759540184
Short name T1937
Test name
Test status
Simulation time 195623343 ps
CPU time 0.93 seconds
Started Aug 02 05:28:26 PM PDT 24
Finished Aug 02 05:28:27 PM PDT 24
Peak memory 206824 kb
Host smart-937b5464-adf9-4dae-8fc4-2839480bf8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75954
0184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.759540184
Directory /workspace/6.usbdev_out_iso/latest


Test location /workspace/coverage/default/6.usbdev_out_stall.3291200948
Short name T2882
Test name
Test status
Simulation time 149520302 ps
CPU time 0.82 seconds
Started Aug 02 05:28:26 PM PDT 24
Finished Aug 02 05:28:27 PM PDT 24
Peak memory 207376 kb
Host smart-12603e4a-9ab0-4723-a9e8-2b8d7efedc70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32912
00948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3291200948
Directory /workspace/6.usbdev_out_stall/latest


Test location /workspace/coverage/default/6.usbdev_out_trans_nak.961779566
Short name T690
Test name
Test status
Simulation time 221977870 ps
CPU time 1 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:28:26 PM PDT 24
Peak memory 207400 kb
Host smart-22e750e7-8dda-4689-863d-c069e6158667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96177
9566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.961779566
Directory /workspace/6.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/6.usbdev_pending_in_trans.4027172792
Short name T2956
Test name
Test status
Simulation time 155247081 ps
CPU time 0.84 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:28:26 PM PDT 24
Peak memory 207368 kb
Host smart-2343d45a-d976-4e0b-9c54-4f505b0719ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40271
72792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.4027172792
Directory /workspace/6.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.3483205894
Short name T43
Test name
Test status
Simulation time 236953980 ps
CPU time 1.05 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:28:26 PM PDT 24
Peak memory 207376 kb
Host smart-d29671a0-0181-4215-bc59-8b804403b855
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3483205894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.3483205894
Directory /workspace/6.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.974838440
Short name T2077
Test name
Test status
Simulation time 183873030 ps
CPU time 0.84 seconds
Started Aug 02 05:28:24 PM PDT 24
Finished Aug 02 05:28:25 PM PDT 24
Peak memory 207332 kb
Host smart-b733dacd-3eff-4a70-ac0d-eca9a1079a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97483
8440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.974838440
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.338544893
Short name T27
Test name
Test status
Simulation time 35480033 ps
CPU time 0.67 seconds
Started Aug 02 05:28:24 PM PDT 24
Finished Aug 02 05:28:25 PM PDT 24
Peak memory 207380 kb
Host smart-0ed7638d-a0ac-4b44-8a87-60d736a36065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33854
4893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.338544893
Directory /workspace/6.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/6.usbdev_pkt_buffer.442205347
Short name T265
Test name
Test status
Simulation time 12375584555 ps
CPU time 31.91 seconds
Started Aug 02 05:28:24 PM PDT 24
Finished Aug 02 05:28:56 PM PDT 24
Peak memory 215852 kb
Host smart-320d4a7b-352b-4dc7-82c0-1d28a0d69845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44220
5347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.442205347
Directory /workspace/6.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/6.usbdev_pkt_received.2816194493
Short name T1144
Test name
Test status
Simulation time 245510539 ps
CPU time 0.98 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:28:26 PM PDT 24
Peak memory 207340 kb
Host smart-cc33139b-cb07-4920-8e05-4d04c495aac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28161
94493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2816194493
Directory /workspace/6.usbdev_pkt_received/latest


Test location /workspace/coverage/default/6.usbdev_pkt_sent.2649406888
Short name T2840
Test name
Test status
Simulation time 162721464 ps
CPU time 0.88 seconds
Started Aug 02 05:28:27 PM PDT 24
Finished Aug 02 05:28:28 PM PDT 24
Peak memory 207360 kb
Host smart-249e5354-b77b-41a6-9906-251309519e4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494
06888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2649406888
Directory /workspace/6.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1364111072
Short name T170
Test name
Test status
Simulation time 3453878323 ps
CPU time 27.07 seconds
Started Aug 02 05:28:25 PM PDT 24
Finished Aug 02 05:28:52 PM PDT 24
Peak memory 217940 kb
Host smart-fd6e8fc7-9610-4d5c-8a47-4ca7ea0715dc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364111072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1364111072
Directory /workspace/6.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/6.usbdev_rand_suspends.2000653126
Short name T2823
Test name
Test status
Simulation time 14509410510 ps
CPU time 111.9 seconds
Started Aug 02 05:28:35 PM PDT 24
Finished Aug 02 05:30:27 PM PDT 24
Peak memory 223988 kb
Host smart-d5306263-aa1f-4b6b-b115-bb9a1e3999b1
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000653126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2000653126
Directory /workspace/6.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.738932291
Short name T2817
Test name
Test status
Simulation time 219503260 ps
CPU time 0.97 seconds
Started Aug 02 05:28:24 PM PDT 24
Finished Aug 02 05:28:25 PM PDT 24
Peak memory 207352 kb
Host smart-5a7fad19-dd76-49ca-8b1d-b0eccd781f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73893
2291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.738932291
Directory /workspace/6.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1907223231
Short name T1205
Test name
Test status
Simulation time 194802369 ps
CPU time 0.86 seconds
Started Aug 02 05:28:24 PM PDT 24
Finished Aug 02 05:28:25 PM PDT 24
Peak memory 207380 kb
Host smart-c72acd4a-43ed-45d5-8ae8-d88da5967b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19072
23231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1907223231
Directory /workspace/6.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3884089147
Short name T1374
Test name
Test status
Simulation time 142626880 ps
CPU time 0.81 seconds
Started Aug 02 05:28:36 PM PDT 24
Finished Aug 02 05:28:37 PM PDT 24
Peak memory 207328 kb
Host smart-06eb260d-953d-4791-9877-d7839b168b05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38840
89147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3884089147
Directory /workspace/6.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/6.usbdev_rx_full.519401677
Short name T1082
Test name
Test status
Simulation time 460836736 ps
CPU time 1.41 seconds
Started Aug 02 05:28:35 PM PDT 24
Finished Aug 02 05:28:36 PM PDT 24
Peak memory 207392 kb
Host smart-ed76560e-cda2-4917-b39b-b50c06e2e0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51940
1677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_full.519401677
Directory /workspace/6.usbdev_rx_full/latest


Test location /workspace/coverage/default/6.usbdev_setup_stage.3065167033
Short name T167
Test name
Test status
Simulation time 161441021 ps
CPU time 0.89 seconds
Started Aug 02 05:28:35 PM PDT 24
Finished Aug 02 05:28:36 PM PDT 24
Peak memory 207328 kb
Host smart-74867a29-75e9-4b0c-9b89-294d50c714b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651
67033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3065167033
Directory /workspace/6.usbdev_setup_stage/latest


Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3864968712
Short name T310
Test name
Test status
Simulation time 156846057 ps
CPU time 0.84 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207332 kb
Host smart-1d4e5877-d87c-4df9-938f-52fee0758539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649
68712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3864968712
Directory /workspace/6.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/6.usbdev_smoke.3344635773
Short name T1163
Test name
Test status
Simulation time 238233749 ps
CPU time 1 seconds
Started Aug 02 05:28:35 PM PDT 24
Finished Aug 02 05:28:37 PM PDT 24
Peak memory 207352 kb
Host smart-fd14419e-5b00-40e0-9f9d-52d0b733f568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33446
35773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3344635773
Directory /workspace/6.usbdev_smoke/latest


Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2476091739
Short name T1446
Test name
Test status
Simulation time 3435025074 ps
CPU time 34.82 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:29:12 PM PDT 24
Peak memory 217648 kb
Host smart-ae567f60-ee23-4aa5-9dfc-d67f8cb2a907
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2476091739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2476091739
Directory /workspace/6.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.167815137
Short name T253
Test name
Test status
Simulation time 163249940 ps
CPU time 0.84 seconds
Started Aug 02 05:28:35 PM PDT 24
Finished Aug 02 05:28:36 PM PDT 24
Peak memory 207348 kb
Host smart-0ed2000f-e957-47d5-ad15-a9e577a3bf7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16781
5137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.167815137
Directory /workspace/6.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/6.usbdev_stall_trans.3676761696
Short name T1165
Test name
Test status
Simulation time 219183458 ps
CPU time 0.9 seconds
Started Aug 02 05:28:33 PM PDT 24
Finished Aug 02 05:28:34 PM PDT 24
Peak memory 207408 kb
Host smart-eadfe7ca-28bd-40ea-991f-f5157afe850e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36767
61696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3676761696
Directory /workspace/6.usbdev_stall_trans/latest


Test location /workspace/coverage/default/6.usbdev_stream_len_max.97886983
Short name T1746
Test name
Test status
Simulation time 828213802 ps
CPU time 2.11 seconds
Started Aug 02 05:28:42 PM PDT 24
Finished Aug 02 05:28:44 PM PDT 24
Peak memory 207516 kb
Host smart-d0e60228-40c2-4e78-9748-f8fc75f23d44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97886
983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.97886983
Directory /workspace/6.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/6.usbdev_streaming_out.399655250
Short name T1098
Test name
Test status
Simulation time 3056099406 ps
CPU time 29.42 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:29:07 PM PDT 24
Peak memory 215864 kb
Host smart-34e5bfd2-ccb3-4e5d-bd3a-24c951e76263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39965
5250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.399655250
Directory /workspace/6.usbdev_streaming_out/latest


Test location /workspace/coverage/default/6.usbdev_timeout_missing_host_handshake.3362096593
Short name T3104
Test name
Test status
Simulation time 977790920 ps
CPU time 22.69 seconds
Started Aug 02 05:28:17 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207640 kb
Host smart-68be6015-0053-4ebe-92b3-f35187cc8d41
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362096593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_timeout_missing_host
_handshake.3362096593
Directory /workspace/6.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/60.usbdev_endpoint_types.684388969
Short name T447
Test name
Test status
Simulation time 661948983 ps
CPU time 1.48 seconds
Started Aug 02 05:34:51 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 207300 kb
Host smart-32f86b31-cd9c-4ab0-98a4-f36d549e99e3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=684388969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.usbdev_endpoint_types.684388969
Directory /workspace/60.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/61.usbdev_endpoint_types.3185995367
Short name T442
Test name
Test status
Simulation time 407034815 ps
CPU time 1.21 seconds
Started Aug 02 05:34:47 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207352 kb
Host smart-8f2a3713-5001-4d4b-a841-581969221770
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3185995367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.usbdev_endpoint_types.3185995367
Directory /workspace/61.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/62.usbdev_endpoint_types.3101450117
Short name T2139
Test name
Test status
Simulation time 166274838 ps
CPU time 0.89 seconds
Started Aug 02 05:34:57 PM PDT 24
Finished Aug 02 05:34:58 PM PDT 24
Peak memory 207384 kb
Host smart-b0757972-2a9e-4628-ad93-c51f6d67ea57
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3101450117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.usbdev_endpoint_types.3101450117
Directory /workspace/62.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/63.usbdev_endpoint_types.1689989159
Short name T486
Test name
Test status
Simulation time 435531576 ps
CPU time 1.27 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207368 kb
Host smart-d783099e-db4b-44af-bfa6-148fc87293f2
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1689989159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.usbdev_endpoint_types.1689989159
Directory /workspace/63.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/64.usbdev_endpoint_types.2372521319
Short name T2160
Test name
Test status
Simulation time 411248793 ps
CPU time 1.4 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:08 PM PDT 24
Peak memory 207180 kb
Host smart-1e8408d6-31bd-4956-82c6-c6e7cf1b8e3b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2372521319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.usbdev_endpoint_types.2372521319
Directory /workspace/64.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/65.usbdev_endpoint_types.730686716
Short name T371
Test name
Test status
Simulation time 546856884 ps
CPU time 1.68 seconds
Started Aug 02 05:34:55 PM PDT 24
Finished Aug 02 05:34:57 PM PDT 24
Peak memory 207380 kb
Host smart-48b0c261-4818-42c8-bbf6-1a0fcd699a2d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=730686716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.usbdev_endpoint_types.730686716
Directory /workspace/65.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/66.usbdev_endpoint_types.137316379
Short name T455
Test name
Test status
Simulation time 357757120 ps
CPU time 1.25 seconds
Started Aug 02 05:34:49 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 207348 kb
Host smart-fdd4edaa-7836-4f57-8aa6-aba8758e7c6a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=137316379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.usbdev_endpoint_types.137316379
Directory /workspace/66.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/68.usbdev_endpoint_types.4008704919
Short name T361
Test name
Test status
Simulation time 683929788 ps
CPU time 1.86 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207356 kb
Host smart-5b288e2a-a57e-42ee-ba9c-fceaf24dcc1b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4008704919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.usbdev_endpoint_types.4008704919
Directory /workspace/68.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/7.usbdev_alert_test.231193219
Short name T1115
Test name
Test status
Simulation time 40742821 ps
CPU time 0.67 seconds
Started Aug 02 05:28:45 PM PDT 24
Finished Aug 02 05:28:46 PM PDT 24
Peak memory 207440 kb
Host smart-7418b157-5a4d-42c9-b953-965a22322c8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=231193219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.231193219
Directory /workspace/7.usbdev_alert_test/latest


Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.3662655803
Short name T1722
Test name
Test status
Simulation time 6426004762 ps
CPU time 8.19 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:47 PM PDT 24
Peak memory 215828 kb
Host smart-37f5c8da-629c-444f-a802-c061a05213d5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662655803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_disconnect.3662655803
Directory /workspace/7.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.411612862
Short name T1787
Test name
Test status
Simulation time 14900049262 ps
CPU time 16.94 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:55 PM PDT 24
Peak memory 215764 kb
Host smart-ee31c0d1-a3ba-4c7e-a36d-f1a3fa064675
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=411612862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.411612862
Directory /workspace/7.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.2251060873
Short name T113
Test name
Test status
Simulation time 25112252830 ps
CPU time 31.41 seconds
Started Aug 02 05:28:36 PM PDT 24
Finished Aug 02 05:29:07 PM PDT 24
Peak memory 215880 kb
Host smart-db8ef7f5-86aa-49b5-8cb4-3b90625e4cd4
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251060873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_ao
n_wake_resume.2251060873
Directory /workspace/7.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/7.usbdev_av_buffer.3033408512
Short name T2744
Test name
Test status
Simulation time 185156165 ps
CPU time 0.89 seconds
Started Aug 02 05:28:33 PM PDT 24
Finished Aug 02 05:28:35 PM PDT 24
Peak memory 207400 kb
Host smart-70e73b73-8ab9-42fc-ad48-dbf3529f7866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30334
08512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3033408512
Directory /workspace/7.usbdev_av_buffer/latest


Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3743973748
Short name T750
Test name
Test status
Simulation time 156099034 ps
CPU time 0.85 seconds
Started Aug 02 05:28:35 PM PDT 24
Finished Aug 02 05:28:36 PM PDT 24
Peak memory 207284 kb
Host smart-cd963816-df15-430f-8da1-c44d636ca233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37439
73748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3743973748
Directory /workspace/7.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3299532764
Short name T1902
Test name
Test status
Simulation time 165957959 ps
CPU time 0.87 seconds
Started Aug 02 05:28:34 PM PDT 24
Finished Aug 02 05:28:35 PM PDT 24
Peak memory 207392 kb
Host smart-d4e9bf39-b42a-45c7-8db4-80d535bb34d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32995
32764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3299532764
Directory /workspace/7.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.473225054
Short name T1523
Test name
Test status
Simulation time 983531014 ps
CPU time 2.4 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:41 PM PDT 24
Peak memory 207612 kb
Host smart-4359c791-868d-4c32-9177-612f7931d9fb
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=473225054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.473225054
Directory /workspace/7.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/7.usbdev_device_address.4142788712
Short name T1962
Test name
Test status
Simulation time 38506529536 ps
CPU time 63.78 seconds
Started Aug 02 05:28:39 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 207716 kb
Host smart-9d2115b7-0437-49b8-9f05-1c7254ccc23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41427
88712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.4142788712
Directory /workspace/7.usbdev_device_address/latest


Test location /workspace/coverage/default/7.usbdev_device_timeout.437273463
Short name T2879
Test name
Test status
Simulation time 1575524132 ps
CPU time 9.95 seconds
Started Aug 02 05:28:36 PM PDT 24
Finished Aug 02 05:28:46 PM PDT 24
Peak memory 207556 kb
Host smart-980b9d2d-79db-4532-971d-54e121591d56
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437273463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_timeout.437273463
Directory /workspace/7.usbdev_device_timeout/latest


Test location /workspace/coverage/default/7.usbdev_disable_endpoint.1507746423
Short name T647
Test name
Test status
Simulation time 691505186 ps
CPU time 1.79 seconds
Started Aug 02 05:28:40 PM PDT 24
Finished Aug 02 05:28:42 PM PDT 24
Peak memory 207376 kb
Host smart-83695b1a-4cf0-4f3f-8e45-722e64fb2a9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15077
46423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.1507746423
Directory /workspace/7.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/7.usbdev_disconnected.2580771485
Short name T2094
Test name
Test status
Simulation time 151200286 ps
CPU time 0.86 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:28:38 PM PDT 24
Peak memory 207360 kb
Host smart-5369ab6b-318e-4cb4-a07a-0508c4c1a566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25807
71485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2580771485
Directory /workspace/7.usbdev_disconnected/latest


Test location /workspace/coverage/default/7.usbdev_enable.2131090796
Short name T2766
Test name
Test status
Simulation time 30471196 ps
CPU time 0.67 seconds
Started Aug 02 05:28:32 PM PDT 24
Finished Aug 02 05:28:33 PM PDT 24
Peak memory 207288 kb
Host smart-f1fbf59a-a75c-4ca9-8cba-3b09f141a42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21310
90796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2131090796
Directory /workspace/7.usbdev_enable/latest


Test location /workspace/coverage/default/7.usbdev_endpoint_access.257334687
Short name T1797
Test name
Test status
Simulation time 710160554 ps
CPU time 2.12 seconds
Started Aug 02 05:28:33 PM PDT 24
Finished Aug 02 05:28:35 PM PDT 24
Peak memory 207592 kb
Host smart-941cac57-e005-45bf-a2ee-730d398bb5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25733
4687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.257334687
Directory /workspace/7.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/7.usbdev_endpoint_types.992435629
Short name T2613
Test name
Test status
Simulation time 827935732 ps
CPU time 1.81 seconds
Started Aug 02 05:28:33 PM PDT 24
Finished Aug 02 05:28:35 PM PDT 24
Peak memory 207328 kb
Host smart-d1ee8501-2e42-4d0a-b746-727941326c25
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=992435629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_types.992435629
Directory /workspace/7.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/7.usbdev_fifo_rst.2675825670
Short name T2599
Test name
Test status
Simulation time 332134793 ps
CPU time 2.16 seconds
Started Aug 02 05:28:34 PM PDT 24
Finished Aug 02 05:28:36 PM PDT 24
Peak memory 207564 kb
Host smart-0ad46ff0-a0c6-4998-97a9-75c35aca415c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26758
25670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.2675825670
Directory /workspace/7.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/7.usbdev_in_iso.2553174055
Short name T2610
Test name
Test status
Simulation time 216965068 ps
CPU time 1.09 seconds
Started Aug 02 05:28:33 PM PDT 24
Finished Aug 02 05:28:35 PM PDT 24
Peak memory 215736 kb
Host smart-3146f3a5-d3d0-456f-9dce-9490425d87f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2553174055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.2553174055
Directory /workspace/7.usbdev_in_iso/latest


Test location /workspace/coverage/default/7.usbdev_in_stall.3531259024
Short name T1565
Test name
Test status
Simulation time 138158198 ps
CPU time 0.84 seconds
Started Aug 02 05:28:36 PM PDT 24
Finished Aug 02 05:28:37 PM PDT 24
Peak memory 207364 kb
Host smart-d19b9c88-4a2c-41dd-bdd3-6e229c2750fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35312
59024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3531259024
Directory /workspace/7.usbdev_in_stall/latest


Test location /workspace/coverage/default/7.usbdev_in_trans.328842730
Short name T2553
Test name
Test status
Simulation time 309402557 ps
CPU time 1.13 seconds
Started Aug 02 05:28:39 PM PDT 24
Finished Aug 02 05:28:40 PM PDT 24
Peak memory 207404 kb
Host smart-dd31f332-403f-4214-ab26-b7fc7bd27be0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32884
2730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.328842730
Directory /workspace/7.usbdev_in_trans/latest


Test location /workspace/coverage/default/7.usbdev_invalid_sync.454068061
Short name T2962
Test name
Test status
Simulation time 2745238175 ps
CPU time 75.48 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:29:54 PM PDT 24
Peak memory 215832 kb
Host smart-175ee56a-25fd-435c-b97c-e7e231510195
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=454068061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.454068061
Directory /workspace/7.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/7.usbdev_iso_retraction.2605411461
Short name T1382
Test name
Test status
Simulation time 8636459123 ps
CPU time 54.46 seconds
Started Aug 02 05:28:34 PM PDT 24
Finished Aug 02 05:29:28 PM PDT 24
Peak memory 207700 kb
Host smart-e16a2701-fa3d-47e1-9cd1-6e908191c01a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2605411461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2605411461
Directory /workspace/7.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/7.usbdev_link_in_err.3359604170
Short name T543
Test name
Test status
Simulation time 234697493 ps
CPU time 0.95 seconds
Started Aug 02 05:28:36 PM PDT 24
Finished Aug 02 05:28:37 PM PDT 24
Peak memory 207412 kb
Host smart-d69b159d-5687-4c8e-b83b-7e7376426f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33596
04170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.3359604170
Directory /workspace/7.usbdev_link_in_err/latest


Test location /workspace/coverage/default/7.usbdev_link_resume.3966737909
Short name T758
Test name
Test status
Simulation time 7598076232 ps
CPU time 10.16 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:48 PM PDT 24
Peak memory 215820 kb
Host smart-306c46af-ad46-4017-b2fc-536e1cee9e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39667
37909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3966737909
Directory /workspace/7.usbdev_link_resume/latest


Test location /workspace/coverage/default/7.usbdev_link_suspend.1937384880
Short name T1695
Test name
Test status
Simulation time 10899436916 ps
CPU time 13.45 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:52 PM PDT 24
Peak memory 207708 kb
Host smart-19427b0a-3da3-48a5-822b-e30ecbbcc723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19373
84880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1937384880
Directory /workspace/7.usbdev_link_suspend/latest


Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3371294670
Short name T1188
Test name
Test status
Simulation time 4606618370 ps
CPU time 45.63 seconds
Started Aug 02 05:28:39 PM PDT 24
Finished Aug 02 05:29:25 PM PDT 24
Peak memory 218068 kb
Host smart-f5621453-791d-46b3-8078-4dc1bbe7da03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33712
94670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3371294670
Directory /workspace/7.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.4228948690
Short name T2539
Test name
Test status
Simulation time 3295202202 ps
CPU time 94.02 seconds
Started Aug 02 05:28:36 PM PDT 24
Finished Aug 02 05:30:10 PM PDT 24
Peak memory 217400 kb
Host smart-8687fbde-d31d-4f7d-a234-497f4790e329
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4228948690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.4228948690
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2264263708
Short name T1487
Test name
Test status
Simulation time 243227125 ps
CPU time 1.03 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:40 PM PDT 24
Peak memory 207420 kb
Host smart-ef59f089-6e07-4f9e-80b6-3acdc9c4946c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2264263708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2264263708
Directory /workspace/7.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3824481212
Short name T1573
Test name
Test status
Simulation time 191041029 ps
CPU time 0.89 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207444 kb
Host smart-faf45d5f-cb31-4b22-9838-da8ddd37f9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38244
81212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3824481212
Directory /workspace/7.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_max_non_iso_usb_traffic.898700368
Short name T2044
Test name
Test status
Simulation time 2730336716 ps
CPU time 71.76 seconds
Started Aug 02 05:28:48 PM PDT 24
Finished Aug 02 05:30:00 PM PDT 24
Peak memory 215628 kb
Host smart-c8dd01ef-7ee8-4598-a31b-5ab720cb09fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89870
0368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_non_iso_usb_traffic.898700368
Directory /workspace/7.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3316216893
Short name T2677
Test name
Test status
Simulation time 3026884279 ps
CPU time 88.57 seconds
Started Aug 02 05:28:40 PM PDT 24
Finished Aug 02 05:30:08 PM PDT 24
Peak memory 215856 kb
Host smart-2aa7a331-91d2-4fa7-856c-aaaad4ed0858
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3316216893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3316216893
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.1455598950
Short name T2435
Test name
Test status
Simulation time 156776653 ps
CPU time 0.87 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207388 kb
Host smart-d44fc0e2-2e9e-4083-b90d-79c4fd839f8b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1455598950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.1455598950
Directory /workspace/7.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.3536542281
Short name T903
Test name
Test status
Simulation time 151990784 ps
CPU time 0.81 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207356 kb
Host smart-59a45bb3-b305-4414-918e-c6d34dfc09e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35365
42281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.3536542281
Directory /workspace/7.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_nak_trans.2510003819
Short name T135
Test name
Test status
Simulation time 180680116 ps
CPU time 0.89 seconds
Started Aug 02 05:28:43 PM PDT 24
Finished Aug 02 05:28:44 PM PDT 24
Peak memory 207340 kb
Host smart-a7cfb749-8450-4408-8341-23fc1e6bafeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25100
03819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2510003819
Directory /workspace/7.usbdev_nak_trans/latest


Test location /workspace/coverage/default/7.usbdev_out_iso.1129697570
Short name T1024
Test name
Test status
Simulation time 177567980 ps
CPU time 0.94 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207424 kb
Host smart-7cca10f5-0379-4a6b-8574-bba6f25d886d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11296
97570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1129697570
Directory /workspace/7.usbdev_out_iso/latest


Test location /workspace/coverage/default/7.usbdev_out_stall.2949617617
Short name T1537
Test name
Test status
Simulation time 193188456 ps
CPU time 0.98 seconds
Started Aug 02 05:28:41 PM PDT 24
Finished Aug 02 05:28:42 PM PDT 24
Peak memory 207396 kb
Host smart-b19e40fc-94f1-4748-abad-f32d85ed219b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29496
17617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2949617617
Directory /workspace/7.usbdev_out_stall/latest


Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1491081946
Short name T1673
Test name
Test status
Simulation time 187957363 ps
CPU time 0.89 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:28:38 PM PDT 24
Peak memory 207424 kb
Host smart-3d9682a1-cd5b-4bd5-88e1-cc83a035238f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14910
81946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1491081946
Directory /workspace/7.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3997370901
Short name T2076
Test name
Test status
Simulation time 173465221 ps
CPU time 0.87 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207336 kb
Host smart-90ad3a4c-a25b-49e0-8b9d-a87462e9b8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39973
70901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3997370901
Directory /workspace/7.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2339280442
Short name T840
Test name
Test status
Simulation time 228641050 ps
CPU time 1.13 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:28:38 PM PDT 24
Peak memory 207384 kb
Host smart-cbe00137-9499-405a-824a-f5f2288688ab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2339280442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2339280442
Directory /workspace/7.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1123044187
Short name T1951
Test name
Test status
Simulation time 151512150 ps
CPU time 0.83 seconds
Started Aug 02 05:28:48 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 207100 kb
Host smart-784ffe3d-ae02-4751-81dd-9e7a34239500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11230
44187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1123044187
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.1163326178
Short name T2687
Test name
Test status
Simulation time 38464311 ps
CPU time 0.74 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207372 kb
Host smart-ce534c91-4754-48dc-8957-6a55498ad858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11633
26178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.1163326178
Directory /workspace/7.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/7.usbdev_pkt_buffer.3454272806
Short name T290
Test name
Test status
Simulation time 7681284308 ps
CPU time 18.58 seconds
Started Aug 02 05:28:39 PM PDT 24
Finished Aug 02 05:28:58 PM PDT 24
Peak memory 224124 kb
Host smart-ac72ba6e-d463-41d7-9a28-0aa3837d3be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34542
72806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.3454272806
Directory /workspace/7.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/7.usbdev_pkt_received.1252263763
Short name T632
Test name
Test status
Simulation time 164819924 ps
CPU time 0.9 seconds
Started Aug 02 05:28:49 PM PDT 24
Finished Aug 02 05:28:50 PM PDT 24
Peak memory 207204 kb
Host smart-ffcf9689-3204-43c5-9b36-7e1feaf8e6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12522
63763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1252263763
Directory /workspace/7.usbdev_pkt_received/latest


Test location /workspace/coverage/default/7.usbdev_pkt_sent.2363016280
Short name T2622
Test name
Test status
Simulation time 271573470 ps
CPU time 0.99 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207300 kb
Host smart-57554db1-9f9f-49b7-9cc5-ab845e212701
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23630
16280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.2363016280
Directory /workspace/7.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.968955599
Short name T171
Test name
Test status
Simulation time 7375211938 ps
CPU time 53.84 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:29:31 PM PDT 24
Peak memory 224060 kb
Host smart-cadad9c1-edf7-482a-acdd-647fef013f22
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=968955599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.968955599
Directory /workspace/7.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/7.usbdev_rand_suspends.228071945
Short name T1744
Test name
Test status
Simulation time 10374330792 ps
CPU time 186.77 seconds
Started Aug 02 05:28:43 PM PDT 24
Finished Aug 02 05:31:50 PM PDT 24
Peak memory 218568 kb
Host smart-10deccb0-78cc-47d8-9095-377d960ab512
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=228071945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.228071945
Directory /workspace/7.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.1822423951
Short name T2448
Test name
Test status
Simulation time 221479978 ps
CPU time 0.96 seconds
Started Aug 02 05:28:40 PM PDT 24
Finished Aug 02 05:28:41 PM PDT 24
Peak memory 207400 kb
Host smart-4af6ee2a-bca6-42f5-be62-f1ac11d67e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18224
23951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1822423951
Directory /workspace/7.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.2565601083
Short name T2355
Test name
Test status
Simulation time 194918276 ps
CPU time 0.9 seconds
Started Aug 02 05:28:40 PM PDT 24
Finished Aug 02 05:28:41 PM PDT 24
Peak memory 207400 kb
Host smart-63bd9781-9ee3-45d3-8a05-e2ce8c12c520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25656
01083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.2565601083
Directory /workspace/7.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1201113296
Short name T950
Test name
Test status
Simulation time 143650257 ps
CPU time 0.84 seconds
Started Aug 02 05:28:49 PM PDT 24
Finished Aug 02 05:28:50 PM PDT 24
Peak memory 207160 kb
Host smart-54551372-a533-4970-b125-8254bdad3702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12011
13296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1201113296
Directory /workspace/7.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/7.usbdev_rx_full.1846652219
Short name T2866
Test name
Test status
Simulation time 326124402 ps
CPU time 1.24 seconds
Started Aug 02 05:28:49 PM PDT 24
Finished Aug 02 05:28:50 PM PDT 24
Peak memory 207208 kb
Host smart-4b6df115-0a07-4531-99da-1bb30ed633d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18466
52219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_full.1846652219
Directory /workspace/7.usbdev_rx_full/latest


Test location /workspace/coverage/default/7.usbdev_setup_stage.2857313426
Short name T1341
Test name
Test status
Simulation time 165303461 ps
CPU time 0.86 seconds
Started Aug 02 05:28:38 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207344 kb
Host smart-502b9259-43e8-40de-b9d6-9e4ffb8c0e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28573
13426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2857313426
Directory /workspace/7.usbdev_setup_stage/latest


Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3283003756
Short name T1877
Test name
Test status
Simulation time 152141008 ps
CPU time 0.83 seconds
Started Aug 02 05:28:39 PM PDT 24
Finished Aug 02 05:28:40 PM PDT 24
Peak memory 207368 kb
Host smart-5765f13d-1298-466f-8027-7c8dc01e38da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32830
03756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3283003756
Directory /workspace/7.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/7.usbdev_smoke.1337778043
Short name T763
Test name
Test status
Simulation time 231735819 ps
CPU time 1.04 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:28:38 PM PDT 24
Peak memory 207416 kb
Host smart-dc166a40-6d09-490f-94ef-dea08499fa5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13377
78043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.1337778043
Directory /workspace/7.usbdev_smoke/latest


Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.1312753643
Short name T2036
Test name
Test status
Simulation time 1877291709 ps
CPU time 13.53 seconds
Started Aug 02 05:28:48 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 223784 kb
Host smart-7b6eda5e-85e0-48b7-b4f4-496e9b00b41b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1312753643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.1312753643
Directory /workspace/7.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.651665233
Short name T1296
Test name
Test status
Simulation time 158962010 ps
CPU time 0.85 seconds
Started Aug 02 05:28:39 PM PDT 24
Finished Aug 02 05:28:40 PM PDT 24
Peak memory 207384 kb
Host smart-781d3a23-2bfc-4f95-ba8d-036242b5df2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65166
5233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.651665233
Directory /workspace/7.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/7.usbdev_stall_trans.747164463
Short name T1046
Test name
Test status
Simulation time 192660349 ps
CPU time 0.9 seconds
Started Aug 02 05:28:37 PM PDT 24
Finished Aug 02 05:28:39 PM PDT 24
Peak memory 207432 kb
Host smart-154a4b4a-e354-4dd5-aeae-b45eb45dbdc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74716
4463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.747164463
Directory /workspace/7.usbdev_stall_trans/latest


Test location /workspace/coverage/default/7.usbdev_stream_len_max.2446995432
Short name T605
Test name
Test status
Simulation time 1361401966 ps
CPU time 2.89 seconds
Started Aug 02 05:28:44 PM PDT 24
Finished Aug 02 05:28:47 PM PDT 24
Peak memory 207536 kb
Host smart-19388557-58dc-48b9-8cda-008a96fb5d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24469
95432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.2446995432
Directory /workspace/7.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/7.usbdev_streaming_out.4289280376
Short name T2461
Test name
Test status
Simulation time 3096205421 ps
CPU time 92.02 seconds
Started Aug 02 05:28:39 PM PDT 24
Finished Aug 02 05:30:11 PM PDT 24
Peak memory 217328 kb
Host smart-4bfe037b-76cf-4965-9266-e068bfcfc4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42892
80376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.4289280376
Directory /workspace/7.usbdev_streaming_out/latest


Test location /workspace/coverage/default/7.usbdev_timeout_missing_host_handshake.402284696
Short name T1921
Test name
Test status
Simulation time 565546996 ps
CPU time 11.59 seconds
Started Aug 02 05:28:42 PM PDT 24
Finished Aug 02 05:28:53 PM PDT 24
Peak memory 207584 kb
Host smart-fa54fa51-802a-453f-bfa8-4138f1fb5513
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402284696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_timeout_missing_host_
handshake.402284696
Directory /workspace/7.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/70.usbdev_endpoint_types.705804066
Short name T465
Test name
Test status
Simulation time 397321008 ps
CPU time 1.29 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207336 kb
Host smart-83834b29-f305-4004-a681-d2086d512f35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=705804066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.usbdev_endpoint_types.705804066
Directory /workspace/70.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/71.usbdev_endpoint_types.20316569
Short name T457
Test name
Test status
Simulation time 217967212 ps
CPU time 1.12 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207316 kb
Host smart-e5e30182-bbe1-4fe1-863f-e1ef3829723a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=20316569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.usbdev_endpoint_types.20316569
Directory /workspace/71.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/72.usbdev_endpoint_types.39838509
Short name T473
Test name
Test status
Simulation time 364713685 ps
CPU time 1.25 seconds
Started Aug 02 05:34:59 PM PDT 24
Finished Aug 02 05:35:00 PM PDT 24
Peak memory 207416 kb
Host smart-830b816e-134e-4f78-b3e6-70ec01bb5e6d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=39838509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.usbdev_endpoint_types.39838509
Directory /workspace/72.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/73.usbdev_endpoint_types.1725225847
Short name T449
Test name
Test status
Simulation time 300565345 ps
CPU time 1.18 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 207336 kb
Host smart-c310ff69-eef5-48ab-90b7-b72c3bfe7962
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1725225847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.usbdev_endpoint_types.1725225847
Directory /workspace/73.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/74.usbdev_endpoint_types.1041888088
Short name T2654
Test name
Test status
Simulation time 534202835 ps
CPU time 1.39 seconds
Started Aug 02 05:34:51 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 207332 kb
Host smart-fdc1fe81-a70e-44f7-9abd-3462c9bad3c3
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1041888088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.usbdev_endpoint_types.1041888088
Directory /workspace/74.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/75.usbdev_endpoint_types.3924410452
Short name T402
Test name
Test status
Simulation time 230939589 ps
CPU time 0.97 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207340 kb
Host smart-d1fb0d24-ec57-4f36-97ff-9b4e1b5533ae
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3924410452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.usbdev_endpoint_types.3924410452
Directory /workspace/75.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/76.usbdev_endpoint_types.1220679343
Short name T394
Test name
Test status
Simulation time 578207209 ps
CPU time 1.45 seconds
Started Aug 02 05:34:57 PM PDT 24
Finished Aug 02 05:34:58 PM PDT 24
Peak memory 207352 kb
Host smart-9b8cdeea-3512-4ca4-a3df-27cb1d0ae05c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1220679343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.usbdev_endpoint_types.1220679343
Directory /workspace/76.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/77.usbdev_endpoint_types.4230257105
Short name T2111
Test name
Test status
Simulation time 237841661 ps
CPU time 0.91 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207180 kb
Host smart-7f5ebad5-8cd7-4f08-b215-9deabff979d6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4230257105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.usbdev_endpoint_types.4230257105
Directory /workspace/77.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/78.usbdev_endpoint_types.843302742
Short name T413
Test name
Test status
Simulation time 636817560 ps
CPU time 1.49 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:50 PM PDT 24
Peak memory 207412 kb
Host smart-bdee8d77-af01-44ad-ae9a-16899444c01e
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=843302742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.usbdev_endpoint_types.843302742
Directory /workspace/78.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/79.usbdev_endpoint_types.2048435424
Short name T311
Test name
Test status
Simulation time 374800911 ps
CPU time 1.21 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207384 kb
Host smart-7307a41c-14f7-474e-8581-d0f044b0eb3c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2048435424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.usbdev_endpoint_types.2048435424
Directory /workspace/79.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/8.usbdev_alert_test.3172401514
Short name T2762
Test name
Test status
Simulation time 46957157 ps
CPU time 0.68 seconds
Started Aug 02 05:28:59 PM PDT 24
Finished Aug 02 05:28:59 PM PDT 24
Peak memory 207508 kb
Host smart-f8b8132f-3193-4c63-8e6f-ec276baf1757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3172401514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3172401514
Directory /workspace/8.usbdev_alert_test/latest


Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.2303259129
Short name T1026
Test name
Test status
Simulation time 10484991574 ps
CPU time 13 seconds
Started Aug 02 05:28:45 PM PDT 24
Finished Aug 02 05:28:58 PM PDT 24
Peak memory 207592 kb
Host smart-4db31b8c-aa00-4aeb-b958-60bad2d3e4b2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303259129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_ao
n_wake_disconnect.2303259129
Directory /workspace/8.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3790933153
Short name T2441
Test name
Test status
Simulation time 20896212262 ps
CPU time 22.4 seconds
Started Aug 02 05:28:46 PM PDT 24
Finished Aug 02 05:29:08 PM PDT 24
Peak memory 207560 kb
Host smart-432d1323-2690-4aa8-8e22-0ca1f28a1091
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790933153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3790933153
Directory /workspace/8.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.980023321
Short name T2907
Test name
Test status
Simulation time 29590037737 ps
CPU time 33.98 seconds
Started Aug 02 05:28:46 PM PDT 24
Finished Aug 02 05:29:20 PM PDT 24
Peak memory 207620 kb
Host smart-ab67b921-7428-4121-bb49-3914e8bd93cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980023321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon
_wake_resume.980023321
Directory /workspace/8.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/8.usbdev_av_buffer.2172154842
Short name T2598
Test name
Test status
Simulation time 153824563 ps
CPU time 0.82 seconds
Started Aug 02 05:28:44 PM PDT 24
Finished Aug 02 05:28:45 PM PDT 24
Peak memory 207404 kb
Host smart-6a83b090-579b-4f92-a26f-b6adf30bea32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21721
54842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2172154842
Directory /workspace/8.usbdev_av_buffer/latest


Test location /workspace/coverage/default/8.usbdev_bitstuff_err.133427839
Short name T1830
Test name
Test status
Simulation time 185450030 ps
CPU time 0.83 seconds
Started Aug 02 05:28:51 PM PDT 24
Finished Aug 02 05:28:52 PM PDT 24
Peak memory 207176 kb
Host smart-b98ab40f-a701-4a09-94c9-b83fb3271f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13342
7839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.133427839
Directory /workspace/8.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.233520079
Short name T1883
Test name
Test status
Simulation time 476680401 ps
CPU time 1.67 seconds
Started Aug 02 05:28:46 PM PDT 24
Finished Aug 02 05:28:48 PM PDT 24
Peak memory 207392 kb
Host smart-1e7299e3-c7c8-4b4d-a75f-06bfa2576fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23352
0079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.233520079
Directory /workspace/8.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/8.usbdev_device_address.1034176926
Short name T2655
Test name
Test status
Simulation time 46786524150 ps
CPU time 72.39 seconds
Started Aug 02 05:28:48 PM PDT 24
Finished Aug 02 05:30:01 PM PDT 24
Peak memory 207596 kb
Host smart-cdf00298-2649-4bec-93a2-f35e069b7f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10341
76926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1034176926
Directory /workspace/8.usbdev_device_address/latest


Test location /workspace/coverage/default/8.usbdev_device_timeout.2822634934
Short name T1697
Test name
Test status
Simulation time 4380859513 ps
CPU time 29.63 seconds
Started Aug 02 05:28:46 PM PDT 24
Finished Aug 02 05:29:15 PM PDT 24
Peak memory 207728 kb
Host smart-a30ea134-a20c-402b-b1b6-304cd56c2492
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822634934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_timeout.2822634934
Directory /workspace/8.usbdev_device_timeout/latest


Test location /workspace/coverage/default/8.usbdev_disable_endpoint.187823875
Short name T1018
Test name
Test status
Simulation time 1053797098 ps
CPU time 2.35 seconds
Started Aug 02 05:28:47 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 207356 kb
Host smart-a5a769fb-6009-4782-b6d8-3322f09659a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18782
3875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.187823875
Directory /workspace/8.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/8.usbdev_disconnected.943195175
Short name T693
Test name
Test status
Simulation time 139663582 ps
CPU time 0.82 seconds
Started Aug 02 05:28:49 PM PDT 24
Finished Aug 02 05:28:50 PM PDT 24
Peak memory 207176 kb
Host smart-2144835c-aa90-46dc-95b2-db43ef0f3373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94319
5175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.943195175
Directory /workspace/8.usbdev_disconnected/latest


Test location /workspace/coverage/default/8.usbdev_enable.2758414003
Short name T2011
Test name
Test status
Simulation time 52094986 ps
CPU time 0.74 seconds
Started Aug 02 05:28:46 PM PDT 24
Finished Aug 02 05:28:47 PM PDT 24
Peak memory 207272 kb
Host smart-1a40eba0-6283-48a4-9e07-ddd141bd5bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27584
14003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.2758414003
Directory /workspace/8.usbdev_enable/latest


Test location /workspace/coverage/default/8.usbdev_endpoint_access.1301104534
Short name T2177
Test name
Test status
Simulation time 881582787 ps
CPU time 2.34 seconds
Started Aug 02 05:28:48 PM PDT 24
Finished Aug 02 05:28:51 PM PDT 24
Peak memory 207500 kb
Host smart-3d7bf69b-006d-4044-9659-ac07dff33f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13011
04534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1301104534
Directory /workspace/8.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/8.usbdev_endpoint_types.598139792
Short name T3031
Test name
Test status
Simulation time 415298585 ps
CPU time 1.26 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 207344 kb
Host smart-c06d9bea-1777-4916-bfbd-8f993b7e9e7f
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=598139792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_types.598139792
Directory /workspace/8.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/8.usbdev_fifo_rst.2396578158
Short name T618
Test name
Test status
Simulation time 163533954 ps
CPU time 1.34 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:28:55 PM PDT 24
Peak memory 207536 kb
Host smart-18e24c10-5323-4e5f-b084-2a87aa93e076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23965
78158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.2396578158
Directory /workspace/8.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/8.usbdev_in_iso.634292773
Short name T1492
Test name
Test status
Simulation time 222230934 ps
CPU time 1.02 seconds
Started Aug 02 05:28:51 PM PDT 24
Finished Aug 02 05:28:52 PM PDT 24
Peak memory 207592 kb
Host smart-4c2ac2f8-9a00-4fd6-9d57-05dbb2309da1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=634292773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.634292773
Directory /workspace/8.usbdev_in_iso/latest


Test location /workspace/coverage/default/8.usbdev_in_stall.2249684898
Short name T1225
Test name
Test status
Simulation time 174365000 ps
CPU time 0.85 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 207284 kb
Host smart-bd1d31fe-fdbe-44c5-8504-d989363840e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22496
84898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2249684898
Directory /workspace/8.usbdev_in_stall/latest


Test location /workspace/coverage/default/8.usbdev_in_trans.4162046587
Short name T808
Test name
Test status
Simulation time 241521297 ps
CPU time 0.98 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 207372 kb
Host smart-cc07bc6a-4a6a-40a7-958c-0af085ac5ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41620
46587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.4162046587
Directory /workspace/8.usbdev_in_trans/latest


Test location /workspace/coverage/default/8.usbdev_invalid_sync.1277168711
Short name T1562
Test name
Test status
Simulation time 4916774482 ps
CPU time 46.61 seconds
Started Aug 02 05:28:51 PM PDT 24
Finished Aug 02 05:29:38 PM PDT 24
Peak memory 218180 kb
Host smart-b2e98117-d726-447e-ba1e-5fa496882797
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1277168711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.1277168711
Directory /workspace/8.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/8.usbdev_iso_retraction.1388518054
Short name T1343
Test name
Test status
Simulation time 9010085843 ps
CPU time 113.17 seconds
Started Aug 02 05:28:56 PM PDT 24
Finished Aug 02 05:30:49 PM PDT 24
Peak memory 207668 kb
Host smart-2ac8457c-ddaf-41ea-a6fe-99f12ffadc74
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1388518054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.1388518054
Directory /workspace/8.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/8.usbdev_link_in_err.3540784830
Short name T1114
Test name
Test status
Simulation time 277356051 ps
CPU time 1.03 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 207336 kb
Host smart-f88f19d0-4c54-4ed8-b72f-1a9e30dcd6d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35407
84830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.3540784830
Directory /workspace/8.usbdev_link_in_err/latest


Test location /workspace/coverage/default/8.usbdev_link_resume.449573700
Short name T1309
Test name
Test status
Simulation time 12501252673 ps
CPU time 16.63 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:29:10 PM PDT 24
Peak memory 207116 kb
Host smart-4330a645-0b33-45cd-9a90-aee76ea8a915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44957
3700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.449573700
Directory /workspace/8.usbdev_link_resume/latest


Test location /workspace/coverage/default/8.usbdev_link_suspend.1183134349
Short name T1597
Test name
Test status
Simulation time 5314489928 ps
CPU time 6.93 seconds
Started Aug 02 05:28:55 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 215864 kb
Host smart-5a86861f-7354-4f7a-ae06-aeb831312595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11831
34349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1183134349
Directory /workspace/8.usbdev_link_suspend/latest


Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3287743938
Short name T350
Test name
Test status
Simulation time 4193008615 ps
CPU time 121.67 seconds
Started Aug 02 05:28:56 PM PDT 24
Finished Aug 02 05:30:58 PM PDT 24
Peak memory 215908 kb
Host smart-d81bed64-6d34-4665-a509-91d1a0d9fce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32877
43938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3287743938
Directory /workspace/8.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.4091600095
Short name T2133
Test name
Test status
Simulation time 2787765407 ps
CPU time 29.18 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:29:22 PM PDT 24
Peak memory 215860 kb
Host smart-228c938d-9c28-4daa-9d62-7855e68b7a31
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4091600095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.4091600095
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.861693954
Short name T516
Test name
Test status
Simulation time 238084814 ps
CPU time 1.04 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 206788 kb
Host smart-beab86c1-2bdc-4e81-a136-e431ac731f6b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=861693954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.861693954
Directory /workspace/8.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.2121697657
Short name T2815
Test name
Test status
Simulation time 195481728 ps
CPU time 0.91 seconds
Started Aug 02 05:28:52 PM PDT 24
Finished Aug 02 05:28:53 PM PDT 24
Peak memory 207360 kb
Host smart-5b10635a-8054-428f-afe5-559dd59c969d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21216
97657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.2121697657
Directory /workspace/8.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_max_non_iso_usb_traffic.1748075210
Short name T1002
Test name
Test status
Simulation time 3054651760 ps
CPU time 87.72 seconds
Started Aug 02 05:28:51 PM PDT 24
Finished Aug 02 05:30:19 PM PDT 24
Peak memory 217620 kb
Host smart-1b074183-f4b1-4103-8cd5-d8057bce3b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17480
75210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_non_iso_usb_traffic.1748075210
Directory /workspace/8.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2976881238
Short name T126
Test name
Test status
Simulation time 2019680001 ps
CPU time 58.17 seconds
Started Aug 02 05:28:52 PM PDT 24
Finished Aug 02 05:29:51 PM PDT 24
Peak memory 223856 kb
Host smart-e09ea6fd-f5a5-4b81-8b11-2e5721e4fb35
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2976881238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2976881238
Directory /workspace/8.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.3701197494
Short name T1127
Test name
Test status
Simulation time 3117160604 ps
CPU time 94.18 seconds
Started Aug 02 05:28:54 PM PDT 24
Finished Aug 02 05:30:28 PM PDT 24
Peak memory 224056 kb
Host smart-b7d1d69a-0b18-4032-9034-cb0c6b877145
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3701197494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.3701197494
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3806751476
Short name T2337
Test name
Test status
Simulation time 181461046 ps
CPU time 0.9 seconds
Started Aug 02 05:28:55 PM PDT 24
Finished Aug 02 05:28:56 PM PDT 24
Peak memory 207412 kb
Host smart-421f8748-d57d-4601-92e4-7e1270736681
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3806751476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3806751476
Directory /workspace/8.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.1921841611
Short name T2015
Test name
Test status
Simulation time 141594762 ps
CPU time 0.8 seconds
Started Aug 02 05:28:57 PM PDT 24
Finished Aug 02 05:28:58 PM PDT 24
Peak memory 207404 kb
Host smart-b7e6cf56-fa03-467f-8fc0-5328774bf56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19218
41611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.1921841611
Directory /workspace/8.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_nak_trans.1887175645
Short name T151
Test name
Test status
Simulation time 228822720 ps
CPU time 0.93 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 207432 kb
Host smart-e825b606-30f1-4475-a762-c3b2b7c44ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18871
75645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.1887175645
Directory /workspace/8.usbdev_nak_trans/latest


Test location /workspace/coverage/default/8.usbdev_out_iso.3448851082
Short name T1306
Test name
Test status
Simulation time 165575849 ps
CPU time 0.85 seconds
Started Aug 02 05:28:52 PM PDT 24
Finished Aug 02 05:28:53 PM PDT 24
Peak memory 207408 kb
Host smart-2c072dc7-c6b5-4009-aed2-129b767b6777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
51082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3448851082
Directory /workspace/8.usbdev_out_iso/latest


Test location /workspace/coverage/default/8.usbdev_out_stall.1447990709
Short name T2231
Test name
Test status
Simulation time 163704979 ps
CPU time 0.82 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 207416 kb
Host smart-45214a3c-c279-46a9-9478-4457805210e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14479
90709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1447990709
Directory /workspace/8.usbdev_out_stall/latest


Test location /workspace/coverage/default/8.usbdev_out_trans_nak.213561145
Short name T1889
Test name
Test status
Simulation time 207220716 ps
CPU time 0.92 seconds
Started Aug 02 05:28:55 PM PDT 24
Finished Aug 02 05:28:56 PM PDT 24
Peak memory 207316 kb
Host smart-29539366-a939-467a-8ad7-a081a1acaae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21356
1145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.213561145
Directory /workspace/8.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/8.usbdev_pending_in_trans.2391618524
Short name T172
Test name
Test status
Simulation time 158017338 ps
CPU time 0.82 seconds
Started Aug 02 05:28:50 PM PDT 24
Finished Aug 02 05:28:51 PM PDT 24
Peak memory 207384 kb
Host smart-26289c14-beb1-414b-aec4-044400db65ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23916
18524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.2391618524
Directory /workspace/8.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.2949904293
Short name T2614
Test name
Test status
Simulation time 243057585 ps
CPU time 1.03 seconds
Started Aug 02 05:28:50 PM PDT 24
Finished Aug 02 05:28:52 PM PDT 24
Peak memory 207372 kb
Host smart-451dd4ed-d11b-42a2-aa61-7c3cba026ba0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2949904293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.2949904293
Directory /workspace/8.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3575205005
Short name T1803
Test name
Test status
Simulation time 155918829 ps
CPU time 0.79 seconds
Started Aug 02 05:28:51 PM PDT 24
Finished Aug 02 05:28:52 PM PDT 24
Peak memory 207356 kb
Host smart-da7eb43e-d4fd-4405-a8af-635174fcd059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35752
05005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3575205005
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1191724313
Short name T2120
Test name
Test status
Simulation time 56840196 ps
CPU time 0.71 seconds
Started Aug 02 05:28:51 PM PDT 24
Finished Aug 02 05:28:52 PM PDT 24
Peak memory 207412 kb
Host smart-c182e8af-4183-43eb-960a-70d3a564ff90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11917
24313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1191724313
Directory /workspace/8.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/8.usbdev_pkt_buffer.815155215
Short name T2233
Test name
Test status
Simulation time 11356775638 ps
CPU time 27.41 seconds
Started Aug 02 05:28:52 PM PDT 24
Finished Aug 02 05:29:20 PM PDT 24
Peak memory 215924 kb
Host smart-3525bd47-56aa-4ac2-a28d-70f725ddcbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81515
5215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.815155215
Directory /workspace/8.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/8.usbdev_pkt_received.52566772
Short name T804
Test name
Test status
Simulation time 158299228 ps
CPU time 0.9 seconds
Started Aug 02 05:28:52 PM PDT 24
Finished Aug 02 05:28:53 PM PDT 24
Peak memory 207360 kb
Host smart-88385875-d409-48a6-92c7-2918a0fe543a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52566
772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.52566772
Directory /workspace/8.usbdev_pkt_received/latest


Test location /workspace/coverage/default/8.usbdev_pkt_sent.1850906761
Short name T937
Test name
Test status
Simulation time 215219306 ps
CPU time 0.94 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:28:54 PM PDT 24
Peak memory 207388 kb
Host smart-1163f9f4-8723-4958-9624-223d3b006073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18509
06761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1850906761
Directory /workspace/8.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1890815473
Short name T714
Test name
Test status
Simulation time 3905906558 ps
CPU time 22.65 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:29:16 PM PDT 24
Peak memory 215908 kb
Host smart-391585d5-c1fe-44a2-a153-d2a715933aff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890815473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1890815473
Directory /workspace/8.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.2447869514
Short name T2002
Test name
Test status
Simulation time 5883086695 ps
CPU time 65.05 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:29:59 PM PDT 24
Peak memory 215928 kb
Host smart-f49ba7c8-30b3-459d-b006-7f9bacf6b7e8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2447869514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2447869514
Directory /workspace/8.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/8.usbdev_rand_suspends.174513123
Short name T1418
Test name
Test status
Simulation time 11119097499 ps
CPU time 51.76 seconds
Started Aug 02 05:28:58 PM PDT 24
Finished Aug 02 05:29:50 PM PDT 24
Peak memory 217076 kb
Host smart-c859bde1-82a4-48a8-bb5f-145a51888155
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=174513123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.174513123
Directory /workspace/8.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.3064832822
Short name T1738
Test name
Test status
Simulation time 212358628 ps
CPU time 0.93 seconds
Started Aug 02 05:28:52 PM PDT 24
Finished Aug 02 05:28:53 PM PDT 24
Peak memory 207404 kb
Host smart-54c67e3b-a13e-4215-a75d-96ca146cfdb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30648
32822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.3064832822
Directory /workspace/8.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.1644750872
Short name T2540
Test name
Test status
Simulation time 176710818 ps
CPU time 0.84 seconds
Started Aug 02 05:28:51 PM PDT 24
Finished Aug 02 05:28:52 PM PDT 24
Peak memory 207448 kb
Host smart-03999e4a-7b14-470c-963c-81bf8dc5fc71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16447
50872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.1644750872
Directory /workspace/8.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/8.usbdev_rx_crc_err.3112265840
Short name T1045
Test name
Test status
Simulation time 185124074 ps
CPU time 0.87 seconds
Started Aug 02 05:28:52 PM PDT 24
Finished Aug 02 05:28:53 PM PDT 24
Peak memory 207356 kb
Host smart-9041b529-ff90-4fd5-9cad-faed66769b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31122
65840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.3112265840
Directory /workspace/8.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/8.usbdev_rx_full.222242648
Short name T50
Test name
Test status
Simulation time 242217138 ps
CPU time 1.12 seconds
Started Aug 02 05:28:54 PM PDT 24
Finished Aug 02 05:28:55 PM PDT 24
Peak memory 207392 kb
Host smart-b7897ce7-04e2-4b1a-976e-672764be1efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22224
2648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_full.222242648
Directory /workspace/8.usbdev_rx_full/latest


Test location /workspace/coverage/default/8.usbdev_setup_stage.3754445946
Short name T1841
Test name
Test status
Simulation time 149248253 ps
CPU time 0.79 seconds
Started Aug 02 05:28:52 PM PDT 24
Finished Aug 02 05:28:53 PM PDT 24
Peak memory 207376 kb
Host smart-2004535d-48be-4ecf-ad64-6ab079e18964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37544
45946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3754445946
Directory /workspace/8.usbdev_setup_stage/latest


Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.883341043
Short name T2090
Test name
Test status
Simulation time 238661455 ps
CPU time 0.96 seconds
Started Aug 02 05:28:56 PM PDT 24
Finished Aug 02 05:28:57 PM PDT 24
Peak memory 207364 kb
Host smart-4b82a6ef-75e1-435f-953a-eeda29093225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88334
1043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.883341043
Directory /workspace/8.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/8.usbdev_smoke.2016784376
Short name T1677
Test name
Test status
Simulation time 210953053 ps
CPU time 1 seconds
Started Aug 02 05:28:55 PM PDT 24
Finished Aug 02 05:28:56 PM PDT 24
Peak memory 207308 kb
Host smart-0b3c83ce-3e8a-45e4-8934-9dec0e9fcd1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20167
84376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.2016784376
Directory /workspace/8.usbdev_smoke/latest


Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.2439502155
Short name T2113
Test name
Test status
Simulation time 3024338688 ps
CPU time 82.06 seconds
Started Aug 02 05:28:53 PM PDT 24
Finished Aug 02 05:30:15 PM PDT 24
Peak memory 224072 kb
Host smart-be8a8d49-31c1-44fe-a5fd-52caa7ac5821
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2439502155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.2439502155
Directory /workspace/8.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.2084956885
Short name T2917
Test name
Test status
Simulation time 159704068 ps
CPU time 0.87 seconds
Started Aug 02 05:28:52 PM PDT 24
Finished Aug 02 05:28:53 PM PDT 24
Peak memory 207408 kb
Host smart-1cec718f-5abb-41de-8b9f-7f1ce9fd9b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20849
56885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.2084956885
Directory /workspace/8.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/8.usbdev_stall_trans.1908862778
Short name T2661
Test name
Test status
Simulation time 203712095 ps
CPU time 0.93 seconds
Started Aug 02 05:28:59 PM PDT 24
Finished Aug 02 05:29:00 PM PDT 24
Peak memory 207352 kb
Host smart-c780d7e1-fe18-41ea-909e-08b21e12e269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19088
62778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1908862778
Directory /workspace/8.usbdev_stall_trans/latest


Test location /workspace/coverage/default/8.usbdev_stream_len_max.3907546730
Short name T1386
Test name
Test status
Simulation time 728310392 ps
CPU time 2.03 seconds
Started Aug 02 05:29:06 PM PDT 24
Finished Aug 02 05:29:08 PM PDT 24
Peak memory 207436 kb
Host smart-f8e7eacb-313b-421d-af64-68e01160dc81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39075
46730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3907546730
Directory /workspace/8.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/8.usbdev_streaming_out.1535926580
Short name T2131
Test name
Test status
Simulation time 2601686032 ps
CPU time 24.61 seconds
Started Aug 02 05:29:02 PM PDT 24
Finished Aug 02 05:29:26 PM PDT 24
Peak memory 215840 kb
Host smart-822e878d-7f6c-406e-98c7-0f55eecc4019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15359
26580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.1535926580
Directory /workspace/8.usbdev_streaming_out/latest


Test location /workspace/coverage/default/8.usbdev_timeout_missing_host_handshake.1571095986
Short name T1546
Test name
Test status
Simulation time 159692004 ps
CPU time 0.97 seconds
Started Aug 02 05:28:48 PM PDT 24
Finished Aug 02 05:28:49 PM PDT 24
Peak memory 207388 kb
Host smart-9489ebbe-1f22-4aa7-a781-2d5a2b876b59
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571095986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_timeout_missing_host
_handshake.1571095986
Directory /workspace/8.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/80.usbdev_endpoint_types.3892629816
Short name T423
Test name
Test status
Simulation time 451862034 ps
CPU time 1.24 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207256 kb
Host smart-e51b5219-e10c-4d0b-a0c0-487fcec55d28
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3892629816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.usbdev_endpoint_types.3892629816
Directory /workspace/80.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/81.usbdev_endpoint_types.1485653597
Short name T459
Test name
Test status
Simulation time 193542287 ps
CPU time 0.91 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207368 kb
Host smart-2da1b593-86a2-4bf9-b7b2-7026ada60197
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1485653597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.usbdev_endpoint_types.1485653597
Directory /workspace/81.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/82.usbdev_endpoint_types.2208639147
Short name T2901
Test name
Test status
Simulation time 259441832 ps
CPU time 1.08 seconds
Started Aug 02 05:34:52 PM PDT 24
Finished Aug 02 05:34:53 PM PDT 24
Peak memory 207332 kb
Host smart-533d1368-92db-4613-bb99-6a03d629660d
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2208639147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.usbdev_endpoint_types.2208639147
Directory /workspace/82.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/83.usbdev_endpoint_types.2019892644
Short name T380
Test name
Test status
Simulation time 512875267 ps
CPU time 1.37 seconds
Started Aug 02 05:34:48 PM PDT 24
Finished Aug 02 05:34:49 PM PDT 24
Peak memory 207352 kb
Host smart-eb9b11bf-5a27-4852-8578-d382169e5e34
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2019892644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.usbdev_endpoint_types.2019892644
Directory /workspace/83.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/86.usbdev_endpoint_types.3456699239
Short name T431
Test name
Test status
Simulation time 490693063 ps
CPU time 1.45 seconds
Started Aug 02 05:34:53 PM PDT 24
Finished Aug 02 05:34:54 PM PDT 24
Peak memory 207336 kb
Host smart-0c1424bd-7174-4ca4-adb0-ca68cc73d28a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3456699239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.usbdev_endpoint_types.3456699239
Directory /workspace/86.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/87.usbdev_endpoint_types.1636941060
Short name T460
Test name
Test status
Simulation time 619430274 ps
CPU time 1.44 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207292 kb
Host smart-1e869c38-10f7-485c-9198-3aae74226dca
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1636941060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.usbdev_endpoint_types.1636941060
Directory /workspace/87.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/88.usbdev_endpoint_types.3087630347
Short name T488
Test name
Test status
Simulation time 257518409 ps
CPU time 1.01 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207304 kb
Host smart-6fa1bc7a-68c9-4108-887b-286d632b80f1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3087630347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.usbdev_endpoint_types.3087630347
Directory /workspace/88.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/89.usbdev_endpoint_types.1620372025
Short name T368
Test name
Test status
Simulation time 755211062 ps
CPU time 1.65 seconds
Started Aug 02 05:34:59 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207352 kb
Host smart-9327a2b7-a4bf-4535-a0b8-19a8d28090de
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1620372025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.usbdev_endpoint_types.1620372025
Directory /workspace/89.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/9.usbdev_alert_test.257740654
Short name T575
Test name
Test status
Simulation time 54069547 ps
CPU time 0.63 seconds
Started Aug 02 05:29:16 PM PDT 24
Finished Aug 02 05:29:17 PM PDT 24
Peak memory 207432 kb
Host smart-bc50633c-fdcb-4800-b4c2-58841324495b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=257740654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.257740654
Directory /workspace/9.usbdev_alert_test/latest


Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1011344811
Short name T1009
Test name
Test status
Simulation time 5687114778 ps
CPU time 7.75 seconds
Started Aug 02 05:29:04 PM PDT 24
Finished Aug 02 05:29:12 PM PDT 24
Peak memory 215896 kb
Host smart-9eff3180-29da-40c9-8b77-c28377f853fb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011344811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_disconnect.1011344811
Directory /workspace/9.usbdev_aon_wake_disconnect/latest


Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.1249839119
Short name T586
Test name
Test status
Simulation time 21430332290 ps
CPU time 23.58 seconds
Started Aug 02 05:29:05 PM PDT 24
Finished Aug 02 05:29:29 PM PDT 24
Peak memory 207688 kb
Host smart-80421c81-fc19-45f7-9499-7b0c86a8dd86
User root
Command /workspace/default/simv +do_reset_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249839119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.1249839119
Directory /workspace/9.usbdev_aon_wake_reset/latest


Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.1462385686
Short name T1743
Test name
Test status
Simulation time 29685641155 ps
CPU time 31.78 seconds
Started Aug 02 05:29:04 PM PDT 24
Finished Aug 02 05:29:36 PM PDT 24
Peak memory 207604 kb
Host smart-7fe7ccee-4943-4d24-be7e-f0c4db7efeab
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +en_scb_rdchk_link_resume=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462385686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_ao
n_wake_resume.1462385686
Directory /workspace/9.usbdev_aon_wake_resume/latest


Test location /workspace/coverage/default/9.usbdev_av_buffer.3737042950
Short name T1513
Test name
Test status
Simulation time 222441544 ps
CPU time 0.94 seconds
Started Aug 02 05:29:00 PM PDT 24
Finished Aug 02 05:29:01 PM PDT 24
Peak memory 207432 kb
Host smart-bf43e2a8-cbc5-4d4b-a7c7-89e0ae5099f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37370
42950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.3737042950
Directory /workspace/9.usbdev_av_buffer/latest


Test location /workspace/coverage/default/9.usbdev_bitstuff_err.2689788606
Short name T1465
Test name
Test status
Simulation time 147152005 ps
CPU time 0.83 seconds
Started Aug 02 05:29:00 PM PDT 24
Finished Aug 02 05:29:01 PM PDT 24
Peak memory 207344 kb
Host smart-294613be-66a9-4330-9fb9-71c91556cf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26897
88606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.2689788606
Directory /workspace/9.usbdev_bitstuff_err/latest


Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.10544933
Short name T1131
Test name
Test status
Simulation time 317497864 ps
CPU time 1.21 seconds
Started Aug 02 05:29:04 PM PDT 24
Finished Aug 02 05:29:05 PM PDT 24
Peak memory 207376 kb
Host smart-027ca950-664e-4eab-9f78-1560199c13b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10544
933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.10544933
Directory /workspace/9.usbdev_data_toggle_clear/latest


Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1942337995
Short name T1835
Test name
Test status
Simulation time 1303861494 ps
CPU time 3.28 seconds
Started Aug 02 05:29:01 PM PDT 24
Finished Aug 02 05:29:05 PM PDT 24
Peak memory 207580 kb
Host smart-068aa27c-522f-4f31-b5ff-ca9dcec71f66
User root
Command /workspace/default/simv +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si
m.tcl +ntb_random_seed=1942337995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1942337995
Directory /workspace/9.usbdev_data_toggle_restore/latest


Test location /workspace/coverage/default/9.usbdev_device_address.2577950101
Short name T181
Test name
Test status
Simulation time 25190653727 ps
CPU time 41 seconds
Started Aug 02 05:29:01 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 207608 kb
Host smart-94a40e78-ebd6-44b1-a403-f18c3f51968e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
50101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2577950101
Directory /workspace/9.usbdev_device_address/latest


Test location /workspace/coverage/default/9.usbdev_device_timeout.1138981520
Short name T2188
Test name
Test status
Simulation time 3435239334 ps
CPU time 32 seconds
Started Aug 02 05:29:00 PM PDT 24
Finished Aug 02 05:29:32 PM PDT 24
Peak memory 207648 kb
Host smart-75a2b2c4-d405-4cee-8d26-c1ca7f4cb441
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138981520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_timeout.1138981520
Directory /workspace/9.usbdev_device_timeout/latest


Test location /workspace/coverage/default/9.usbdev_disable_endpoint.2993325954
Short name T2584
Test name
Test status
Simulation time 1034268725 ps
CPU time 2.45 seconds
Started Aug 02 05:29:05 PM PDT 24
Finished Aug 02 05:29:08 PM PDT 24
Peak memory 207396 kb
Host smart-2f6f6b74-8430-4225-9dd6-ddca633d8ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29933
25954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.2993325954
Directory /workspace/9.usbdev_disable_endpoint/latest


Test location /workspace/coverage/default/9.usbdev_disconnected.1632351970
Short name T1011
Test name
Test status
Simulation time 135854306 ps
CPU time 0.88 seconds
Started Aug 02 05:28:59 PM PDT 24
Finished Aug 02 05:29:00 PM PDT 24
Peak memory 207328 kb
Host smart-3654145d-24db-480e-b446-7f21dd5a64a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16323
51970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1632351970
Directory /workspace/9.usbdev_disconnected/latest


Test location /workspace/coverage/default/9.usbdev_enable.2022321147
Short name T899
Test name
Test status
Simulation time 47107262 ps
CPU time 0.7 seconds
Started Aug 02 05:29:02 PM PDT 24
Finished Aug 02 05:29:03 PM PDT 24
Peak memory 207384 kb
Host smart-898476a1-b368-4fae-8b26-ddd2fb4e5ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20223
21147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2022321147
Directory /workspace/9.usbdev_enable/latest


Test location /workspace/coverage/default/9.usbdev_endpoint_access.3042366821
Short name T1777
Test name
Test status
Simulation time 917265593 ps
CPU time 2.45 seconds
Started Aug 02 05:29:03 PM PDT 24
Finished Aug 02 05:29:06 PM PDT 24
Peak memory 207564 kb
Host smart-34878f99-8ce0-4300-ae6d-bd42e3fad59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30423
66821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3042366821
Directory /workspace/9.usbdev_endpoint_access/latest


Test location /workspace/coverage/default/9.usbdev_endpoint_types.2862928027
Short name T387
Test name
Test status
Simulation time 658687307 ps
CPU time 1.58 seconds
Started Aug 02 05:29:01 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 207292 kb
Host smart-e8f54a40-e4c3-4a55-b16e-8ca165b9d448
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2862928027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_types.2862928027
Directory /workspace/9.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/9.usbdev_fifo_rst.2977937225
Short name T2253
Test name
Test status
Simulation time 230414608 ps
CPU time 1.54 seconds
Started Aug 02 05:29:00 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 207500 kb
Host smart-671da29e-2418-4fa7-bff8-e75c22cef390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29779
37225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.2977937225
Directory /workspace/9.usbdev_fifo_rst/latest


Test location /workspace/coverage/default/9.usbdev_in_iso.2985379768
Short name T1369
Test name
Test status
Simulation time 165123510 ps
CPU time 0.95 seconds
Started Aug 02 05:28:58 PM PDT 24
Finished Aug 02 05:29:00 PM PDT 24
Peak memory 207420 kb
Host smart-eff5544c-dc0a-4860-b15a-44ed66721cba
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2985379768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2985379768
Directory /workspace/9.usbdev_in_iso/latest


Test location /workspace/coverage/default/9.usbdev_in_stall.4032228979
Short name T31
Test name
Test status
Simulation time 163723548 ps
CPU time 0.85 seconds
Started Aug 02 05:29:03 PM PDT 24
Finished Aug 02 05:29:04 PM PDT 24
Peak memory 207280 kb
Host smart-41be536d-444f-46a1-8d57-d50c78b01da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40322
28979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.4032228979
Directory /workspace/9.usbdev_in_stall/latest


Test location /workspace/coverage/default/9.usbdev_in_trans.2254203962
Short name T2869
Test name
Test status
Simulation time 249152998 ps
CPU time 1.01 seconds
Started Aug 02 05:29:01 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 207308 kb
Host smart-33d94ef7-8752-4576-be80-37cec29fcd2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22542
03962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2254203962
Directory /workspace/9.usbdev_in_trans/latest


Test location /workspace/coverage/default/9.usbdev_invalid_sync.737678135
Short name T123
Test name
Test status
Simulation time 3217987423 ps
CPU time 31.29 seconds
Started Aug 02 05:29:00 PM PDT 24
Finished Aug 02 05:29:31 PM PDT 24
Peak memory 217688 kb
Host smart-22cfa545-5e00-4911-b5be-ad46832b2d8a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=737678135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.737678135
Directory /workspace/9.usbdev_invalid_sync/latest


Test location /workspace/coverage/default/9.usbdev_iso_retraction.2285550011
Short name T2329
Test name
Test status
Simulation time 7833370316 ps
CPU time 55.08 seconds
Started Aug 02 05:29:05 PM PDT 24
Finished Aug 02 05:30:01 PM PDT 24
Peak memory 207732 kb
Host smart-f4a52f61-5223-4ef3-98b8-64c49419c7f6
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2285550011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.2285550011
Directory /workspace/9.usbdev_iso_retraction/latest


Test location /workspace/coverage/default/9.usbdev_link_in_err.1980832487
Short name T2824
Test name
Test status
Simulation time 196470870 ps
CPU time 0.97 seconds
Started Aug 02 05:29:02 PM PDT 24
Finished Aug 02 05:29:03 PM PDT 24
Peak memory 207408 kb
Host smart-65deaef6-fb85-4355-8370-4014f683439d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19808
32487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1980832487
Directory /workspace/9.usbdev_link_in_err/latest


Test location /workspace/coverage/default/9.usbdev_link_resume.3095668206
Short name T1779
Test name
Test status
Simulation time 29302127679 ps
CPU time 42.89 seconds
Started Aug 02 05:29:00 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 207112 kb
Host smart-edfe39bd-9c89-4266-97b3-538a3d9dbe20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30956
68206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3095668206
Directory /workspace/9.usbdev_link_resume/latest


Test location /workspace/coverage/default/9.usbdev_link_suspend.2928727821
Short name T3019
Test name
Test status
Simulation time 6185457144 ps
CPU time 8.51 seconds
Started Aug 02 05:28:59 PM PDT 24
Finished Aug 02 05:29:08 PM PDT 24
Peak memory 216676 kb
Host smart-5cc7e4f3-5045-4f3f-aa54-28f2a1e06351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29287
27821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2928727821
Directory /workspace/9.usbdev_link_suspend/latest


Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.189943959
Short name T1478
Test name
Test status
Simulation time 4438401389 ps
CPU time 128.2 seconds
Started Aug 02 05:29:01 PM PDT 24
Finished Aug 02 05:31:10 PM PDT 24
Peak memory 218580 kb
Host smart-dae0fed6-d28d-4972-bd6b-34cf7e47f89a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18994
3959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.189943959
Directory /workspace/9.usbdev_low_speed_traffic/latest


Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.4232220715
Short name T1284
Test name
Test status
Simulation time 3286716755 ps
CPU time 96.4 seconds
Started Aug 02 05:29:03 PM PDT 24
Finished Aug 02 05:30:39 PM PDT 24
Peak memory 217248 kb
Host smart-257b6b3a-5591-45bf-af1c-27d75dc20845
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4232220715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.4232220715
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest


Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3135794502
Short name T908
Test name
Test status
Simulation time 243793123 ps
CPU time 0.96 seconds
Started Aug 02 05:29:00 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 207408 kb
Host smart-7c7b6950-183a-4589-9bd3-77c361ec086a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3135794502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3135794502
Directory /workspace/9.usbdev_max_length_in_transaction/latest


Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.874560075
Short name T719
Test name
Test status
Simulation time 199693469 ps
CPU time 0.98 seconds
Started Aug 02 05:29:00 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 207380 kb
Host smart-75cafa17-913e-421b-9302-085925e46683
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87456
0075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.874560075
Directory /workspace/9.usbdev_max_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_max_non_iso_usb_traffic.3086486674
Short name T542
Test name
Test status
Simulation time 1558514745 ps
CPU time 43.93 seconds
Started Aug 02 05:28:59 PM PDT 24
Finished Aug 02 05:29:43 PM PDT 24
Peak memory 215796 kb
Host smart-05863e72-9ca6-4098-a5ac-9e223cf0b0e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30864
86674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_non_iso_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_non_iso_usb_traffic.3086486674
Directory /workspace/9.usbdev_max_non_iso_usb_traffic/latest


Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3601821667
Short name T2856
Test name
Test status
Simulation time 2805743981 ps
CPU time 81.37 seconds
Started Aug 02 05:29:05 PM PDT 24
Finished Aug 02 05:30:26 PM PDT 24
Peak memory 215928 kb
Host smart-aadb3664-0f98-43e6-b70d-3cee1180e104
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3601821667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3601821667
Directory /workspace/9.usbdev_max_usb_traffic/latest


Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.4166471291
Short name T2934
Test name
Test status
Simulation time 3653287465 ps
CPU time 104.97 seconds
Started Aug 02 05:29:06 PM PDT 24
Finished Aug 02 05:30:51 PM PDT 24
Peak memory 217312 kb
Host smart-c473e48b-fc17-4cc7-b659-e637a019b669
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4166471291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.4166471291
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest


Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2774192941
Short name T1653
Test name
Test status
Simulation time 160073032 ps
CPU time 0.86 seconds
Started Aug 02 05:29:02 PM PDT 24
Finished Aug 02 05:29:03 PM PDT 24
Peak memory 207376 kb
Host smart-304295e5-e9ec-40dc-9635-96f1dc831703
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2774192941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2774192941
Directory /workspace/9.usbdev_min_length_in_transaction/latest


Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.2661836993
Short name T339
Test name
Test status
Simulation time 144572132 ps
CPU time 0.83 seconds
Started Aug 02 05:28:59 PM PDT 24
Finished Aug 02 05:29:00 PM PDT 24
Peak memory 207364 kb
Host smart-0df1ae4d-4954-4424-89d3-eb60071b1a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26618
36993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.2661836993
Directory /workspace/9.usbdev_min_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_nak_trans.649207397
Short name T1855
Test name
Test status
Simulation time 206364286 ps
CPU time 1.05 seconds
Started Aug 02 05:29:00 PM PDT 24
Finished Aug 02 05:29:01 PM PDT 24
Peak memory 207360 kb
Host smart-00677224-fd15-4305-9e43-6e575edc74a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64920
7397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.649207397
Directory /workspace/9.usbdev_nak_trans/latest


Test location /workspace/coverage/default/9.usbdev_out_iso.2773032095
Short name T969
Test name
Test status
Simulation time 174455992 ps
CPU time 0.85 seconds
Started Aug 02 05:29:01 PM PDT 24
Finished Aug 02 05:29:02 PM PDT 24
Peak memory 207376 kb
Host smart-d005a61f-87a1-4fc3-9784-2aa7eaa0c6e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27730
32095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2773032095
Directory /workspace/9.usbdev_out_iso/latest


Test location /workspace/coverage/default/9.usbdev_out_stall.2697740545
Short name T2194
Test name
Test status
Simulation time 232728192 ps
CPU time 1.03 seconds
Started Aug 02 05:29:09 PM PDT 24
Finished Aug 02 05:29:10 PM PDT 24
Peak memory 207336 kb
Host smart-2e5f6556-21a7-436a-9002-bdf0fb24910a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26977
40545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2697740545
Directory /workspace/9.usbdev_out_stall/latest


Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2996805672
Short name T942
Test name
Test status
Simulation time 207066055 ps
CPU time 0.89 seconds
Started Aug 02 05:29:11 PM PDT 24
Finished Aug 02 05:29:12 PM PDT 24
Peak memory 207360 kb
Host smart-141b32d5-0626-401a-966b-7c3b5a5ff983
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29968
05672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2996805672
Directory /workspace/9.usbdev_out_trans_nak/latest


Test location /workspace/coverage/default/9.usbdev_pending_in_trans.1245440314
Short name T3047
Test name
Test status
Simulation time 154049842 ps
CPU time 0.86 seconds
Started Aug 02 05:29:11 PM PDT 24
Finished Aug 02 05:29:12 PM PDT 24
Peak memory 207364 kb
Host smart-0ac95238-b5c1-40b3-b761-84b3941af2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12454
40314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.1245440314
Directory /workspace/9.usbdev_pending_in_trans/latest


Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3655195484
Short name T574
Test name
Test status
Simulation time 214556731 ps
CPU time 0.92 seconds
Started Aug 02 05:29:08 PM PDT 24
Finished Aug 02 05:29:09 PM PDT 24
Peak memory 207340 kb
Host smart-bf86057a-5295-4e45-b716-37633bbff214
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3655195484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3655195484
Directory /workspace/9.usbdev_phy_config_pinflip/latest


Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.353928206
Short name T2597
Test name
Test status
Simulation time 147154799 ps
CPU time 0.8 seconds
Started Aug 02 05:29:07 PM PDT 24
Finished Aug 02 05:29:08 PM PDT 24
Peak memory 207372 kb
Host smart-3069de5f-2aa7-47e5-a1ec-ac0c2418bb05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35392
8206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.353928206
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest


Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.281030288
Short name T964
Test name
Test status
Simulation time 39130267 ps
CPU time 0.7 seconds
Started Aug 02 05:29:08 PM PDT 24
Finished Aug 02 05:29:09 PM PDT 24
Peak memory 207392 kb
Host smart-060d9996-c147-4599-b0e0-d6db933edca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28103
0288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.281030288
Directory /workspace/9.usbdev_phy_pins_sense/latest


Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3531777240
Short name T1860
Test name
Test status
Simulation time 6277645645 ps
CPU time 17.52 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:35 PM PDT 24
Peak memory 215908 kb
Host smart-c380480e-b339-4a72-b82b-bcbb9a4d1741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35317
77240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3531777240
Directory /workspace/9.usbdev_pkt_buffer/latest


Test location /workspace/coverage/default/9.usbdev_pkt_received.1323399738
Short name T580
Test name
Test status
Simulation time 163960345 ps
CPU time 0.89 seconds
Started Aug 02 05:29:10 PM PDT 24
Finished Aug 02 05:29:11 PM PDT 24
Peak memory 207316 kb
Host smart-424259ab-829b-4422-a53c-45477c1ccadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13233
99738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1323399738
Directory /workspace/9.usbdev_pkt_received/latest


Test location /workspace/coverage/default/9.usbdev_pkt_sent.3101625246
Short name T2989
Test name
Test status
Simulation time 249136600 ps
CPU time 1.11 seconds
Started Aug 02 05:29:08 PM PDT 24
Finished Aug 02 05:29:10 PM PDT 24
Peak memory 207368 kb
Host smart-6d6b1c4c-2b11-4ba4-af6d-9e6c06a3c1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31016
25246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.3101625246
Directory /workspace/9.usbdev_pkt_sent/latest


Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.217151007
Short name T2952
Test name
Test status
Simulation time 6032732335 ps
CPU time 72.63 seconds
Started Aug 02 05:29:10 PM PDT 24
Finished Aug 02 05:30:23 PM PDT 24
Peak memory 218852 kb
Host smart-6a6e1349-92c8-40b3-bd56-a3cc46ad271c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=217151007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.217151007
Directory /workspace/9.usbdev_rand_bus_disconnects/latest


Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1897096002
Short name T169
Test name
Test status
Simulation time 2275826169 ps
CPU time 64.88 seconds
Started Aug 02 05:29:09 PM PDT 24
Finished Aug 02 05:30:14 PM PDT 24
Peak memory 218616 kb
Host smart-8618157d-203e-4d61-99bd-7956cc551fec
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1897096002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1897096002
Directory /workspace/9.usbdev_rand_bus_resets/latest


Test location /workspace/coverage/default/9.usbdev_rand_suspends.1294694317
Short name T2527
Test name
Test status
Simulation time 5991420971 ps
CPU time 22.98 seconds
Started Aug 02 05:29:10 PM PDT 24
Finished Aug 02 05:29:34 PM PDT 24
Peak memory 223484 kb
Host smart-dc956cec-5a1d-4f89-a114-f453b5312544
User root
Command /workspace/default/simv +do_resume_signaling=1 +en_scb_rdchk_linkstate=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re
po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294694317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.1294694317
Directory /workspace/9.usbdev_rand_suspends/latest


Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.529771468
Short name T1503
Test name
Test status
Simulation time 233619807 ps
CPU time 0.92 seconds
Started Aug 02 05:29:07 PM PDT 24
Finished Aug 02 05:29:08 PM PDT 24
Peak memory 207384 kb
Host smart-943a2344-58e3-4502-b9c3-a1277ba05943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52977
1468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.529771468
Directory /workspace/9.usbdev_random_length_in_transaction/latest


Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3090602252
Short name T2291
Test name
Test status
Simulation time 147329649 ps
CPU time 0.81 seconds
Started Aug 02 05:29:10 PM PDT 24
Finished Aug 02 05:29:11 PM PDT 24
Peak memory 207332 kb
Host smart-ca28c570-ff35-42e7-ac63-9cd1b7f4238d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30906
02252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3090602252
Directory /workspace/9.usbdev_random_length_out_transaction/latest


Test location /workspace/coverage/default/9.usbdev_rx_crc_err.3726321504
Short name T2173
Test name
Test status
Simulation time 175483119 ps
CPU time 0.95 seconds
Started Aug 02 05:29:11 PM PDT 24
Finished Aug 02 05:29:12 PM PDT 24
Peak memory 207392 kb
Host smart-4885d289-631d-45ed-9b97-8d7958459380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37263
21504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.3726321504
Directory /workspace/9.usbdev_rx_crc_err/latest


Test location /workspace/coverage/default/9.usbdev_rx_full.1660835214
Short name T1193
Test name
Test status
Simulation time 404377328 ps
CPU time 1.35 seconds
Started Aug 02 05:29:17 PM PDT 24
Finished Aug 02 05:29:18 PM PDT 24
Peak memory 207416 kb
Host smart-4a3181a8-9e81-4524-ac2e-4b73c54cb343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16608
35214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_full.1660835214
Directory /workspace/9.usbdev_rx_full/latest


Test location /workspace/coverage/default/9.usbdev_setup_stage.1106221608
Short name T1099
Test name
Test status
Simulation time 152181942 ps
CPU time 0.86 seconds
Started Aug 02 05:29:10 PM PDT 24
Finished Aug 02 05:29:11 PM PDT 24
Peak memory 207376 kb
Host smart-37b0b398-ee49-46ef-ae7b-b81ea94d06a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11062
21608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1106221608
Directory /workspace/9.usbdev_setup_stage/latest


Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3073874573
Short name T2994
Test name
Test status
Simulation time 159867638 ps
CPU time 0.82 seconds
Started Aug 02 05:29:09 PM PDT 24
Finished Aug 02 05:29:10 PM PDT 24
Peak memory 207368 kb
Host smart-930da1d4-ce5b-4d01-aca3-036187ab5678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30738
74573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3073874573
Directory /workspace/9.usbdev_setup_trans_ignored/latest


Test location /workspace/coverage/default/9.usbdev_smoke.284657173
Short name T544
Test name
Test status
Simulation time 175508890 ps
CPU time 0.88 seconds
Started Aug 02 05:29:08 PM PDT 24
Finished Aug 02 05:29:08 PM PDT 24
Peak memory 207380 kb
Host smart-c91665d3-b07d-4cbb-8ddb-7fc6533a77e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28465
7173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.284657173
Directory /workspace/9.usbdev_smoke/latest


Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2711082276
Short name T1388
Test name
Test status
Simulation time 3134898522 ps
CPU time 91.13 seconds
Started Aug 02 05:29:08 PM PDT 24
Finished Aug 02 05:30:39 PM PDT 24
Peak memory 217640 kb
Host smart-23d5d6a8-9228-408a-a09a-d79597700ff8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2711082276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2711082276
Directory /workspace/9.usbdev_spurious_pids_ignored/latest


Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.58185463
Short name T1080
Test name
Test status
Simulation time 196560833 ps
CPU time 0.93 seconds
Started Aug 02 05:29:08 PM PDT 24
Finished Aug 02 05:29:09 PM PDT 24
Peak memory 207372 kb
Host smart-8fd93eaf-618f-4bd9-b109-f55cd8ab0c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58185
463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.58185463
Directory /workspace/9.usbdev_stall_priority_over_nak/latest


Test location /workspace/coverage/default/9.usbdev_stall_trans.3906206168
Short name T1734
Test name
Test status
Simulation time 210256806 ps
CPU time 0.89 seconds
Started Aug 02 05:29:11 PM PDT 24
Finished Aug 02 05:29:12 PM PDT 24
Peak memory 207376 kb
Host smart-fefea8ad-63ef-48df-acd6-4147e8220b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39062
06168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3906206168
Directory /workspace/9.usbdev_stall_trans/latest


Test location /workspace/coverage/default/9.usbdev_stream_len_max.3632637376
Short name T1745
Test name
Test status
Simulation time 1439749518 ps
CPU time 3.21 seconds
Started Aug 02 05:29:10 PM PDT 24
Finished Aug 02 05:29:13 PM PDT 24
Peak memory 207580 kb
Host smart-81dd148a-e949-4489-99e9-d9ba07fe1835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36326
37376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.3632637376
Directory /workspace/9.usbdev_stream_len_max/latest


Test location /workspace/coverage/default/9.usbdev_streaming_out.4123244522
Short name T2314
Test name
Test status
Simulation time 3872294879 ps
CPU time 35.99 seconds
Started Aug 02 05:29:10 PM PDT 24
Finished Aug 02 05:29:47 PM PDT 24
Peak memory 215328 kb
Host smart-4b4ba4c4-f666-41d2-8892-bf3d0482c604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41232
44522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.4123244522
Directory /workspace/9.usbdev_streaming_out/latest


Test location /workspace/coverage/default/9.usbdev_timeout_missing_host_handshake.3164262562
Short name T2265
Test name
Test status
Simulation time 4756878479 ps
CPU time 41.83 seconds
Started Aug 02 05:29:02 PM PDT 24
Finished Aug 02 05:29:44 PM PDT 24
Peak memory 207732 kb
Host smart-b52e69d6-3328-4aea-bc4d-e3cde52d9a71
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +en_scb_rdchk_link_in_err=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164262562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_timeout_missing_host
_handshake.3164262562
Directory /workspace/9.usbdev_timeout_missing_host_handshake/latest


Test location /workspace/coverage/default/90.usbdev_endpoint_types.2112355954
Short name T399
Test name
Test status
Simulation time 537790203 ps
CPU time 1.4 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207376 kb
Host smart-3e87c682-5ef0-41f9-a52d-0cffb7921ae8
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2112355954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.usbdev_endpoint_types.2112355954
Directory /workspace/90.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/91.usbdev_endpoint_types.1461809652
Short name T476
Test name
Test status
Simulation time 352766325 ps
CPU time 1.14 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 207336 kb
Host smart-9a7dd3dd-330e-4391-b20c-541ecc7fd89c
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1461809652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.usbdev_endpoint_types.1461809652
Directory /workspace/91.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/93.usbdev_endpoint_types.845430724
Short name T489
Test name
Test status
Simulation time 261188856 ps
CPU time 1.11 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 207384 kb
Host smart-244694d7-0f1d-4a99-aa2c-c13baaed136a
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=845430724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.usbdev_endpoint_types.845430724
Directory /workspace/93.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/94.usbdev_endpoint_types.3876258432
Short name T398
Test name
Test status
Simulation time 406516420 ps
CPU time 1.24 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:04 PM PDT 24
Peak memory 207288 kb
Host smart-57e4156a-df3d-4450-a686-491e4998b9db
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3876258432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.usbdev_endpoint_types.3876258432
Directory /workspace/94.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/95.usbdev_endpoint_types.2370055565
Short name T1293
Test name
Test status
Simulation time 236476629 ps
CPU time 0.93 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:01 PM PDT 24
Peak memory 207392 kb
Host smart-af170f4d-08b2-420d-a2c7-4be845e20747
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2370055565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.usbdev_endpoint_types.2370055565
Directory /workspace/95.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/96.usbdev_endpoint_types.1287261369
Short name T3084
Test name
Test status
Simulation time 260147212 ps
CPU time 1.12 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:02 PM PDT 24
Peak memory 207356 kb
Host smart-7498678e-de63-4903-8905-aa447f3ab2d1
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1287261369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.usbdev_endpoint_types.1287261369
Directory /workspace/96.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/97.usbdev_endpoint_types.2022713647
Short name T1996
Test name
Test status
Simulation time 168098211 ps
CPU time 0.88 seconds
Started Aug 02 05:35:08 PM PDT 24
Finished Aug 02 05:35:09 PM PDT 24
Peak memory 207328 kb
Host smart-0c11546b-8a0c-48fc-836e-587b9e1db3f0
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2022713647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.usbdev_endpoint_types.2022713647
Directory /workspace/97.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/98.usbdev_endpoint_types.1377905481
Short name T415
Test name
Test status
Simulation time 582177615 ps
CPU time 1.62 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207180 kb
Host smart-61ea802f-9fcd-4603-abda-a1dc020d96dc
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1377905481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.usbdev_endpoint_types.1377905481
Directory /workspace/98.usbdev_endpoint_types/latest


Test location /workspace/coverage/default/99.usbdev_endpoint_types.3442272101
Short name T369
Test name
Test status
Simulation time 345501833 ps
CPU time 1.15 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 207436 kb
Host smart-2cd55090-2663-4407-8f2c-38b9fd9e9e6b
User root
Command /workspace/default/simv +en_scb_rdchk_configin=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3442272101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_types_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.usbdev_endpoint_types.3442272101
Directory /workspace/99.usbdev_endpoint_types/latest
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