Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	89594	1		T1	2		T2	4		T3	2
all_values[1]	89594	1		T1	2		T2	4		T3	2
all_values[2]	89594	1		T1	2		T2	4		T3	2
all_values[3]	89594	1		T1	2		T2	4		T3	2
all_values[4]	89594	1		T1	2		T2	4		T3	2
all_values[5]	89594	1		T1	2		T2	4		T3	2
all_values[6]	89594	1		T1	2		T2	4		T3	2
all_values[7]	89594	1		T1	2		T2	4		T3	2
all_values[8]	89594	1		T1	2		T2	4		T3	2
all_values[9]	89594	1		T1	2		T2	4		T3	2
all_values[10]	89594	1		T1	2		T2	4		T3	2
all_values[11]	89594	1		T1	2		T2	4		T3	2
all_values[12]	89594	1		T1	2		T2	4		T3	2
all_values[13]	89594	1		T1	2		T2	4		T3	2
all_values[14]	89594	1		T1	2		T2	4		T3	2
all_values[15]	89594	1		T1	2		T2	4		T3	2
all_values[16]	89594	1		T1	2		T2	4		T3	2
all_values[17]	89594	1		T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2859785	1		T1	64		T2	124		T3	64
auto[1]	7223	1		T2	4		T33	3		T36	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2396346	1		T1	58		T2	110		T3	58
auto[1]	470662	1		T1	6		T2	18		T3	6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	63567	1		T1	2		T3	2		T30	2
all_values[0]	auto[0]	auto[1]	25207	1		T31	1		T99	1		T23	1
all_values[0]	auto[1]	auto[0]	715	1		T2	3		T48	3		T49	3
all_values[0]	auto[1]	auto[1]	105	1		T2	1		T48	1		T308	1
all_values[1]	auto[0]	auto[0]	86583	1		T1	2		T2	4		T3	2
all_values[1]	auto[0]	auto[1]	1603	1		T30	2		T32	2		T4	2
all_values[1]	auto[1]	auto[0]	530	1		T33	2		T36	2		T7	1
all_values[1]	auto[1]	auto[1]	878	1		T33	1		T36	1		T7	1
all_values[2]	auto[0]	auto[0]	3735	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	85604	1		T1	1		T2	3		T3	1
all_values[2]	auto[1]	auto[0]	157	1		T45	1		T69	1		T70	1
all_values[2]	auto[1]	auto[1]	98	1		T45	1		T69	1		T70	1
all_values[3]	auto[0]	auto[0]	87692	1		T1	2		T2	4		T3	2
all_values[3]	auto[0]	auto[1]	296	1		T38	1		T71	1		T20	1
all_values[3]	auto[1]	auto[0]	1532	1		T72	1429		T213	1		T211	1
all_values[3]	auto[1]	auto[1]	74	1		T72	1		T213	2		T211	3
all_values[4]	auto[0]	auto[0]	3715	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	85721	1		T1	1		T2	3		T3	1
all_values[4]	auto[1]	auto[0]	93	1		T73	1		T212	1		T214	1
all_values[4]	auto[1]	auto[1]	65	1		T73	1		T213	1		T214	2
all_values[5]	auto[0]	auto[0]	89095	1		T1	2		T2	4		T3	2
all_values[5]	auto[0]	auto[1]	350	1		T64	1		T7	1		T65	1
all_values[5]	auto[1]	auto[0]	94	1		T213	1		T212	5		T214	7
all_values[5]	auto[1]	auto[1]	55	1		T213	2		T211	1		T212	2
all_values[6]	auto[0]	auto[0]	89162	1		T1	2		T2	4		T3	2
all_values[6]	auto[0]	auto[1]	209	1		T39	1		T64	1		T65	1
all_values[6]	auto[1]	auto[0]	106	1		T213	1		T211	3		T212	6
all_values[6]	auto[1]	auto[1]	117	1		T46	1		T47	1		T74	1
all_values[7]	auto[0]	auto[0]	35551	1		T1	2		T3	2		T34	2
all_values[7]	auto[0]	auto[1]	53862	1		T2	4		T30	2		T31	4
all_values[7]	auto[1]	auto[0]	123	1		T50	1		T51	1		T52	1
all_values[7]	auto[1]	auto[1]	58	1		T50	1		T51	1		T52	1
all_values[8]	auto[0]	auto[0]	88842	1		T1	2		T2	4		T3	2
all_values[8]	auto[0]	auto[1]	56	1		T213	1		T211	3		T212	2
all_values[8]	auto[1]	auto[0]	608	1		T56	10		T57	10		T58	10
all_values[8]	auto[1]	auto[1]	88	1		T54	1		T55	1		T61	1
all_values[9]	auto[0]	auto[0]	89351	1		T1	2		T2	4		T3	2
all_values[9]	auto[0]	auto[1]	47	1		T213	1		T212	2		T214	3
all_values[9]	auto[1]	auto[0]	107	1		T66	3		T67	3		T68	3
all_values[9]	auto[1]	auto[1]	89	1		T66	2		T67	2		T68	2
all_values[10]	auto[0]	auto[0]	89116	1		T1	2		T2	4		T3	2
all_values[10]	auto[0]	auto[1]	309	1		T30	1		T32	1		T37	1
all_values[10]	auto[1]	auto[0]	104	1		T213	1		T212	5		T214	4
all_values[10]	auto[1]	auto[1]	65	1		T213	1		T211	1		T214	2
all_values[11]	auto[0]	auto[0]	89189	1		T1	2		T2	4		T3	2
all_values[11]	auto[0]	auto[1]	144	1		T78	1		T64	1		T79	1
all_values[11]	auto[1]	auto[0]	156	1		T80	1		T81	1		T82	1
all_values[11]	auto[1]	auto[1]	105	1		T80	1		T81	1		T82	1
all_values[12]	auto[0]	auto[0]	89364	1		T1	2		T2	4		T3	2
all_values[12]	auto[0]	auto[1]	56	1		T64	1		T79	1		T83	1
all_values[12]	auto[1]	auto[0]	115	1		T84	2		T85	2		T86	2
all_values[12]	auto[1]	auto[1]	59	1		T84	1		T85	1		T86	1
all_values[13]	auto[0]	auto[0]	89281	1		T1	2		T2	4		T3	2
all_values[13]	auto[0]	auto[1]	61	1		T64	1		T79	1		T83	1
all_values[13]	auto[1]	auto[0]	142	1		T78	1		T87	1		T88	1
all_values[13]	auto[1]	auto[1]	110	1		T78	1		T87	1		T88	1
all_values[14]	auto[0]	auto[0]	15673	1		T1	1		T2	4		T3	2
all_values[14]	auto[0]	auto[1]	73756	1		T1	1		T4	1		T5	1
all_values[14]	auto[1]	auto[0]	110	1		T213	2		T211	3		T212	5
all_values[14]	auto[1]	auto[1]	55	1		T211	1		T214	4		T280	2
all_values[15]	auto[0]	auto[0]	3748	1		T1	1		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	85670	1		T1	1		T2	3		T3	1
all_values[15]	auto[1]	auto[0]	117	1		T213	4		T211	3		T214	3
all_values[15]	auto[1]	auto[1]	59	1		T211	1		T212	2		T214	1
all_values[16]	auto[0]	auto[0]	88932	1		T1	2		T2	4		T3	1
all_values[16]	auto[0]	auto[1]	493	1		T3	1		T30	1		T32	1
all_values[16]	auto[1]	auto[0]	99	1		T75	4		T76	4		T77	4
all_values[16]	auto[1]	auto[1]	70	1		T75	4		T76	4		T77	4
all_values[17]	auto[0]	auto[0]	34414	1		T4	2		T5	2		T89	2
all_values[17]	auto[0]	auto[1]	55015	1		T1	2		T2	4		T3	2
all_values[17]	auto[1]	auto[0]	112	1		T62	1		T63	1		T212	4
all_values[17]	auto[1]	auto[1]	53	1		T62	1		T63	1		T213	1