Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	116752	1		T2	1		T3	1		T30	6
auto[1]	43896	1		T30	6		T32	2		T33	1

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29139	1		T31	1		T5	2		T71	65
max_len_m1	769	1		T32	1		T64	2		T100	4
max_len_m2	799	1		T34	1		T4	1		T6	1
max_len_m3	842	1		T5	2		T6	1		T100	4
five	1083	1		T30	1		T4	8		T5	4
four	1111	1		T30	1		T4	3		T35	1
three	669	1		T4	1		T35	1		T64	2
one	825	1		T35	1		T22	1		T25	2
zero	11462	1		T30	4		T32	1		T35	9

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24160	1		T31	1		T5	1		T64	1
max_len	auto[1]	4979	1		T5	1		T71	65		T25	3
max_len_m1	auto[0]	538	1		T32	1		T64	1		T100	2
max_len_m1	auto[1]	231	1		T64	1		T100	2		T18	2
max_len_m2	auto[0]	551	1		T34	1		T4	1		T6	1
max_len_m2	auto[1]	248	1		T64	1		T18	2		T24	1
max_len_m3	auto[0]	584	1		T5	1		T6	1		T100	2
max_len_m3	auto[1]	258	1		T5	1		T100	2		T18	2
five	auto[0]	568	1		T30	1		T4	5		T5	2
five	auto[1]	515	1		T4	3		T5	2		T6	1
four	auto[0]	560	1		T30	1		T4	2		T35	1
four	auto[1]	551	1		T4	1		T24	1		T241	13
three	auto[0]	322	1		T4	1		T35	1		T64	2
three	auto[1]	347	1		T241	15		T242	4		T245	5
one	auto[0]	354	1		T35	1		T22	1		T25	2
one	auto[1]	471	1		T241	19		T242	6		T245	10
zero	auto[0]	539	1		T78	1		T6	1		T64	2
zero	auto[1]	10923	1		T30	4		T32	1		T35	9