Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
56.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	96	48	48	50.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	2	2	50.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	48	48	50.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	67522	1		T2	1		T3	1		T30	6
auto[1]	38652	1		T30	6		T32	2		T33	1

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	8164	1		T3	1		T30	1		T31	1
endpoints[0x1]	8944	1		T30	2		T4	42		T6	18
endpoints[0x2]	11014	1		T6	18		T38	23		T64	16
endpoints[0x3]	10715	1		T30	2		T32	1		T6	18
endpoints[0x4]	10490	1		T34	1		T5	76		T99	1
endpoints[0x5]	7776	1		T32	1		T6	18		T20	10
endpoints[0x6]	7737	1		T30	1		T78	1		T64	18
endpoints[0x7]	9028	1		T30	1		T38	24		T64	18
endpoints[0x8]	7654	1		T30	2		T36	2		T38	22
endpoints[0x9]	9485	1		T2	1		T30	1		T32	1
endpoints[0xa]	6559	1		T35	19		T38	17		T64	16
endpoints[0xb]	8608	1		T30	2		T38	26		T22	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	2	2	50.00

User Defined Bins for cp_pid

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
nak	0	1	1
ack	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	48729	1		T30	4		T4	40		T35	4
data0	57427	1		T2	1		T3	1		T30	8

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	48	48	50.00	48

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER
[nak , ack]	*	*	--	--	48

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
data1	auto[0]	endpoints[0x0]	2192	1		T24	4		T25	2		T241	22
data1	auto[0]	endpoints[0x1]	2371	1		T4	10		T6	4		T38	7
data1	auto[0]	endpoints[0x2]	3375	1		T6	4		T38	6		T64	3
data1	auto[0]	endpoints[0x3]	3286	1		T6	1		T25	3		T241	19
data1	auto[0]	endpoints[0x4]	2950	1		T5	19		T64	3		T24	6
data1	auto[0]	endpoints[0x5]	1908	1		T6	2		T156	3		T241	21
data1	auto[0]	endpoints[0x6]	1831	1		T64	3		T156	3		T241	20
data1	auto[0]	endpoints[0x7]	2531	1		T38	3		T64	2		T20	11
data1	auto[0]	endpoints[0x8]	1623	1		T38	13		T64	4		T24	6
data1	auto[0]	endpoints[0x9]	2866	1		T4	10		T38	7		T64	5
data1	auto[0]	endpoints[0xa]	1419	1		T35	2		T64	2		T20	5
data1	auto[0]	endpoints[0xb]	2375	1		T30	1		T38	8		T22	1
data1	auto[1]	endpoints[0x0]	1540	1		T24	9		T25	5		T241	18
data1	auto[1]	endpoints[0x1]	1723	1		T4	10		T6	4		T38	9
data1	auto[1]	endpoints[0x2]	1752	1		T6	4		T38	4		T64	4
data1	auto[1]	endpoints[0x3]	1696	1		T30	1		T6	8		T25	3
data1	auto[1]	endpoints[0x4]	1921	1		T5	19		T37	7		T64	4
data1	auto[1]	endpoints[0x5]	1614	1		T6	7		T20	7		T156	3
data1	auto[1]	endpoints[0x6]	1724	1		T30	1		T64	4		T95	5
data1	auto[1]	endpoints[0x7]	1616	1		T30	1		T64	5		T17	4
data1	auto[1]	endpoints[0x8]	1824	1		T64	4		T24	6		T25	3
data1	auto[1]	endpoints[0x9]	1550	1		T4	10		T64	4		T100	20
data1	auto[1]	endpoints[0xa]	1471	1		T35	2		T64	4		T156	3
data1	auto[1]	endpoints[0xb]	1571	1		T25	4		T158	27		T241	18
data0	auto[0]	endpoints[0x0]	2976	1		T3	1		T30	1		T31	1
data0	auto[0]	endpoints[0x1]	3301	1		T30	1		T4	11		T6	5
data0	auto[0]	endpoints[0x2]	4266	1		T6	5		T38	11		T64	5
data0	auto[0]	endpoints[0x3]	4180	1		T30	1		T6	8		T244	1
data0	auto[0]	endpoints[0x4]	3872	1		T34	1		T5	19		T99	1
data0	auto[0]	endpoints[0x5]	2790	1		T32	1		T6	7		T156	4
data0	auto[0]	endpoints[0x6]	2534	1		T78	1		T64	6		T7	1
data0	auto[0]	endpoints[0x7]	3387	1		T38	21		T64	8		T20	22
data0	auto[0]	endpoints[0x8]	2525	1		T30	1		T36	1		T38	9
data0	auto[0]	endpoints[0x9]	3607	1		T2	1		T30	1		T32	1
data0	auto[0]	endpoints[0xa]	2184	1		T35	8		T38	17		T64	6
data0	auto[0]	endpoints[0xb]	3155	1		T38	18		T22	1		T25	4
data0	auto[1]	endpoints[0x0]	1453	1		T32	1		T33	1		T24	4
data0	auto[1]	endpoints[0x1]	1549	1		T30	1		T4	11		T6	5
data0	auto[1]	endpoints[0x2]	1619	1		T6	5		T38	2		T64	4
data0	auto[1]	endpoints[0x3]	1553	1		T32	1		T6	1		T25	4
data0	auto[1]	endpoints[0x4]	1744	1		T5	19		T37	13		T64	4
data0	auto[1]	endpoints[0x5]	1462	1		T6	2		T20	3		T156	4
data0	auto[1]	endpoints[0x6]	1645	1		T64	4		T7	1		T95	9
data0	auto[1]	endpoints[0x7]	1492	1		T64	3		T17	7		T20	7
data0	auto[1]	endpoints[0x8]	1681	1		T30	1		T36	1		T64	4
data0	auto[1]	endpoints[0x9]	1460	1		T4	11		T64	4		T100	21
data0	auto[1]	endpoints[0xa]	1485	1		T35	7		T64	4		T156	4
data0	auto[1]	endpoints[0xb]	1507	1		T30	1		T25	3		T158	27