Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	89594	1		T1	2		T2	4		T3	2
all_pins[1]	89594	1		T1	2		T2	4		T3	2
all_pins[2]	89594	1		T1	2		T2	4		T3	2
all_pins[3]	89594	1		T1	2		T2	4		T3	2
all_pins[4]	89594	1		T1	2		T2	4		T3	2
all_pins[5]	89594	1		T1	2		T2	4		T3	2
all_pins[6]	89594	1		T1	2		T2	4		T3	2
all_pins[7]	89594	1		T1	2		T2	4		T3	2
all_pins[8]	89594	1		T1	2		T2	4		T3	2
all_pins[9]	89594	1		T1	2		T2	4		T3	2
all_pins[10]	89594	1		T1	2		T2	4		T3	2
all_pins[11]	89594	1		T1	2		T2	4		T3	2
all_pins[12]	89594	1		T1	2		T2	4		T3	2
all_pins[13]	89594	1		T1	2		T2	4		T3	2
all_pins[14]	89594	1		T1	2		T2	4		T3	2
all_pins[15]	89594	1		T1	2		T2	4		T3	2
all_pins[16]	89594	1		T1	2		T2	4		T3	2
all_pins[17]	89594	1		T1	2		T2	4		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2864805	1		T1	64		T2	127		T3	64
values[0x1]	2203	1		T2	1		T33	1		T36	1
transitions[0x0=>0x1]	1974	1		T2	1		T33	1		T36	1
transitions[0x1=>0x0]	1974	1		T2	1		T33	1		T36	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89489	1		T1	2		T2	3		T3	2
all_pins[0]	values[0x1]	105	1		T2	1		T48	1		T308	1
all_pins[0]	transitions[0x0=>0x1]	96	1		T2	1		T48	1		T308	1
all_pins[0]	transitions[0x1=>0x0]	869	1		T33	1		T36	1		T7	1
all_pins[1]	values[0x0]	88716	1		T1	2		T2	4		T3	2
all_pins[1]	values[0x1]	878	1		T33	1		T36	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	869	1		T33	1		T36	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	89	1		T45	1		T69	1		T70	1
all_pins[2]	values[0x0]	89496	1		T1	2		T2	4		T3	2
all_pins[2]	values[0x1]	98	1		T45	1		T69	1		T70	1
all_pins[2]	transitions[0x0=>0x1]	83	1		T45	1		T69	1		T70	1
all_pins[2]	transitions[0x1=>0x0]	59	1		T72	1		T213	2		T211	2
all_pins[3]	values[0x0]	89520	1		T1	2		T2	4		T3	2
all_pins[3]	values[0x1]	74	1		T72	1		T213	2		T211	3
all_pins[3]	transitions[0x0=>0x1]	57	1		T72	1		T213	2		T211	3
all_pins[3]	transitions[0x1=>0x0]	48	1		T73	1		T213	1		T214	2
all_pins[4]	values[0x0]	89529	1		T1	2		T2	4		T3	2
all_pins[4]	values[0x1]	65	1		T73	1		T213	1		T214	2
all_pins[4]	transitions[0x0=>0x1]	50	1		T73	1		T213	1		T214	1
all_pins[4]	transitions[0x1=>0x0]	40	1		T213	2		T211	1		T212	2
all_pins[5]	values[0x0]	89539	1		T1	2		T2	4		T3	2
all_pins[5]	values[0x1]	55	1		T213	2		T211	1		T212	2
all_pins[5]	transitions[0x0=>0x1]	37	1		T212	2		T214	1		T281	2
all_pins[5]	transitions[0x1=>0x0]	99	1		T46	1		T47	1		T74	1
all_pins[6]	values[0x0]	89477	1		T1	2		T2	4		T3	2
all_pins[6]	values[0x1]	117	1		T46	1		T47	1		T74	1
all_pins[6]	transitions[0x0=>0x1]	101	1		T46	1		T47	1		T74	1
all_pins[6]	transitions[0x1=>0x0]	42	1		T50	1		T51	1		T52	1
all_pins[7]	values[0x0]	89536	1		T1	2		T2	4		T3	2
all_pins[7]	values[0x1]	58	1		T50	1		T51	1		T52	1
all_pins[7]	transitions[0x0=>0x1]	44	1		T50	1		T51	1		T52	1
all_pins[7]	transitions[0x1=>0x0]	74	1		T54	1		T55	1		T61	1
all_pins[8]	values[0x0]	89506	1		T1	2		T2	4		T3	2
all_pins[8]	values[0x1]	88	1		T54	1		T55	1		T61	1
all_pins[8]	transitions[0x0=>0x1]	75	1		T54	1		T55	1		T61	1
all_pins[8]	transitions[0x1=>0x0]	76	1		T66	2		T67	2		T68	2
all_pins[9]	values[0x0]	89505	1		T1	2		T2	4		T3	2
all_pins[9]	values[0x1]	89	1		T66	2		T67	2		T68	2
all_pins[9]	transitions[0x0=>0x1]	74	1		T66	2		T67	2		T68	2
all_pins[9]	transitions[0x1=>0x0]	50	1		T213	1		T214	2		T281	2
all_pins[10]	values[0x0]	89529	1		T1	2		T2	4		T3	2
all_pins[10]	values[0x1]	65	1		T213	1		T211	1		T214	2
all_pins[10]	transitions[0x0=>0x1]	50	1		T213	1		T211	1		T281	2
all_pins[10]	transitions[0x1=>0x0]	90	1		T80	1		T81	1		T82	1
all_pins[11]	values[0x0]	89489	1		T1	2		T2	4		T3	2
all_pins[11]	values[0x1]	105	1		T80	1		T81	1		T82	1
all_pins[11]	transitions[0x0=>0x1]	91	1		T80	1		T81	1		T82	1
all_pins[11]	transitions[0x1=>0x0]	45	1		T84	1		T85	1		T86	1
all_pins[12]	values[0x0]	89535	1		T1	2		T2	4		T3	2
all_pins[12]	values[0x1]	59	1		T84	1		T85	1		T86	1
all_pins[12]	transitions[0x0=>0x1]	50	1		T84	1		T85	1		T86	1
all_pins[12]	transitions[0x1=>0x0]	101	1		T78	1		T87	1		T88	1
all_pins[13]	values[0x0]	89484	1		T1	2		T2	4		T3	2
all_pins[13]	values[0x1]	110	1		T78	1		T87	1		T88	1
all_pins[13]	transitions[0x0=>0x1]	98	1		T78	1		T87	1		T88	1
all_pins[13]	transitions[0x1=>0x0]	43	1		T211	1		T214	3		T280	1
all_pins[14]	values[0x0]	89539	1		T1	2		T2	4		T3	2
all_pins[14]	values[0x1]	55	1		T211	1		T214	4		T280	2
all_pins[14]	transitions[0x0=>0x1]	42	1		T211	1		T214	3		T280	2
all_pins[14]	transitions[0x1=>0x0]	46	1		T211	1		T212	2		T280	2
all_pins[15]	values[0x0]	89535	1		T1	2		T2	4		T3	2
all_pins[15]	values[0x1]	59	1		T211	1		T212	2		T214	1
all_pins[15]	transitions[0x0=>0x1]	42	1		T211	1		T212	2		T214	1
all_pins[15]	transitions[0x1=>0x0]	53	1		T75	4		T76	4		T77	4
all_pins[16]	values[0x0]	89524	1		T1	2		T2	4		T3	2
all_pins[16]	values[0x1]	70	1		T75	4		T76	4		T77	4
all_pins[16]	transitions[0x0=>0x1]	62	1		T75	4		T76	4		T77	4
all_pins[16]	transitions[0x1=>0x0]	45	1		T62	1		T63	1		T213	1
all_pins[17]	values[0x0]	89541	1		T1	2		T2	4		T3	2
all_pins[17]	values[0x1]	53	1		T62	1		T63	1		T213	1
all_pins[17]	transitions[0x0=>0x1]	53	1		T62	1		T63	1		T213	1