Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4996	1		T4	13		T6	9		T38	76
invalid_ep[0xd]	4915	1		T4	11		T89	2		T6	6
invalid_ep[0xe]	4798	1		T4	9		T89	1		T6	7
invalid_ep[0xf]	4897	1		T4	12		T89	1		T6	4
endpoints[0x0]	12883	1		T3	1		T30	1		T31	1
endpoints[0x1]	13475	1		T30	2		T4	43		T6	19
endpoints[0x2]	15100	1		T6	19		T38	68		T64	17
endpoints[0x3]	15150	1		T30	2		T32	1		T6	19
endpoints[0x4]	14897	1		T34	1		T5	77		T99	1
endpoints[0x5]	12419	1		T32	1		T6	19		T38	77
endpoints[0x6]	12148	1		T30	1		T78	1		T38	87
endpoints[0x7]	13573	1		T30	1		T38	92		T64	21
endpoints[0x8]	11646	1		T30	2		T36	2		T38	80
endpoints[0x9]	13816	1		T2	1		T30	1		T32	1
endpoints[0xa]	11008	1		T35	19		T38	84		T71	69
endpoints[0xb]	12744	1		T30	2		T38	82		T64	7

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	22583	1		T89	1		T6	16		T38	332
pkt_types[PidTypeOutToken]	75978	1		T2	1		T3	1		T30	6
pkt_types[PidTypeInToken]	61374	1		T30	6		T32	2		T33	1

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1143	1		T38	22		T20	32		T296	2
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1082	1		T38	23		T20	31		T92	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1047	1		T38	25		T20	26		T114	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1079	1		T89	1		T38	15		T20	27
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1520	1		T38	33		T20	38		T24	6
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1551	1		T6	2		T38	24		T64	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1505	1		T38	17		T64	3		T20	31
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1605	1		T6	8		T38	22		T20	29
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1509	1		T38	20		T20	30		T298	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1515	1		T6	6		T38	15		T64	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1507	1		T38	20		T64	3		T20	31
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1515	1		T38	22		T64	5		T20	34
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1617	1		T38	16		T20	37		T163	6
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1489	1		T38	21		T64	4		T20	52
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1434	1		T38	14		T64	4		T20	36
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1465	1		T38	23		T64	2		T20	35
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1659	1		T4	13		T6	9		T38	18
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1615	1		T4	11		T89	1		T6	6
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1622	1		T4	9		T6	7		T38	24
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1609	1		T4	12		T6	4		T38	15
pkt_types[PidTypeOutToken]	endpoints[0x0]	5449	1		T3	1		T30	1		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	5853	1		T30	1		T4	21		T6	7
pkt_types[PidTypeOutToken]	endpoints[0x2]	7760	1		T6	9		T38	16		T64	5
pkt_types[PidTypeOutToken]	endpoints[0x3]	7504	1		T30	1		T6	1		T38	28
pkt_types[PidTypeOutToken]	endpoints[0x4]	6865	1		T34	1		T5	38		T99	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	4856	1		T32	1		T6	3		T38	26
pkt_types[PidTypeOutToken]	endpoints[0x6]	4662	1		T78	1		T38	26		T64	7
pkt_types[PidTypeOutToken]	endpoints[0x7]	6094	1		T38	20		T64	7		T20	25
pkt_types[PidTypeOutToken]	endpoints[0x8]	4054	1		T30	1		T36	1		T38	19
pkt_types[PidTypeOutToken]	endpoints[0x9]	6750	1		T2	1		T30	1		T32	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	3911	1		T35	10		T38	28		T64	4
pkt_types[PidTypeOutToken]	endpoints[0xb]	5715	1		T30	1		T38	19		T64	5
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1139	1		T38	18		T20	35		T115	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1109	1		T38	27		T20	36		T296	1
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1044	1		T38	20		T20	32		T296	1
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1139	1		T38	25		T20	40		T94	13
pkt_types[PidTypeInToken]	endpoints[0x0]	4712	1		T32	1		T33	1		T38	28
pkt_types[PidTypeInToken]	endpoints[0x1]	4899	1		T30	1		T4	22		T6	10
pkt_types[PidTypeInToken]	endpoints[0x2]	4692	1		T6	10		T38	17		T64	9
pkt_types[PidTypeInToken]	endpoints[0x3]	4843	1		T30	1		T32	1		T6	10
pkt_types[PidTypeInToken]	endpoints[0x4]	5281	1		T5	39		T37	20		T38	21
pkt_types[PidTypeInToken]	endpoints[0x5]	4849	1		T6	10		T38	19		T20	28
pkt_types[PidTypeInToken]	endpoints[0x6]	4782	1		T30	1		T38	18		T64	10
pkt_types[PidTypeInToken]	endpoints[0x7]	4734	1		T30	1		T38	19		T64	9
pkt_types[PidTypeInToken]	endpoints[0x8]	4863	1		T30	1		T36	1		T38	22
pkt_types[PidTypeInToken]	endpoints[0x9]	4412	1		T4	22		T38	15		T64	9
pkt_types[PidTypeInToken]	endpoints[0xa]	4500	1		T35	9		T38	23		T71	69
pkt_types[PidTypeInToken]	endpoints[0xb]	4376	1		T30	1		T38	24		T20	27