Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T213	4		T211	4		T212	7
all_values[1]	269	1		T213	4		T211	4		T212	7
all_values[2]	269	1		T213	4		T211	4		T212	7
all_values[3]	269	1		T213	4		T211	4		T212	7
all_values[4]	269	1		T213	4		T211	4		T212	7
all_values[5]	269	1		T213	4		T211	4		T212	7
all_values[6]	269	1		T213	4		T211	4		T212	7
all_values[7]	269	1		T213	4		T211	4		T212	7
all_values[8]	269	1		T213	4		T211	4		T212	7
all_values[9]	269	1		T213	4		T211	4		T212	7
all_values[10]	269	1		T213	4		T211	4		T212	7
all_values[11]	269	1		T213	4		T211	4		T212	7
all_values[12]	269	1		T213	4		T211	4		T212	7
all_values[13]	269	1		T213	4		T211	4		T212	7
all_values[14]	269	1		T213	4		T211	4		T212	7
all_values[15]	269	1		T213	4		T211	4		T212	7
all_values[16]	269	1		T213	4		T211	4		T212	7
all_values[17]	269	1		T213	4		T211	4		T212	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6361	1		T213	96		T211	90		T212	156
auto[1]	2247	1		T213	32		T211	38		T212	68

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5944	1		T213	92		T211	83		T212	158
auto[1]	2664	1		T213	36		T211	45		T212	66

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5082	1		T213	82		T211	75		T212	125
auto[1]	3526	1		T213	46		T211	53		T212	99

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	90	1		T213	4		T212	2		T214	3
all_values[0]	auto[0]	auto[1]	auto[0]	68	1		T211	2		T212	3		T214	1
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T214	1		T280	1		T281	1
all_values[0]	auto[1]	auto[1]	auto[1]	46	1		T211	2		T212	2		T214	2
all_values[1]	auto[0]	auto[0]	auto[0]	79	1		T213	1		T211	1		T212	2
all_values[1]	auto[0]	auto[1]	auto[0]	78	1		T213	1		T211	1		T212	4
all_values[1]	auto[1]	auto[0]	auto[1]	71	1		T213	1		T211	1		T212	1
all_values[1]	auto[1]	auto[1]	auto[1]	41	1		T213	1		T211	1		T214	3
all_values[2]	auto[0]	auto[0]	auto[0]	57	1		T214	1		T281	3		T282	1
all_values[2]	auto[0]	auto[0]	auto[1]	35	1		T211	1		T212	1		T214	1
all_values[2]	auto[0]	auto[1]	auto[0]	47	1		T213	2		T212	1		T214	3
all_values[2]	auto[0]	auto[1]	auto[1]	24	1		T212	1		T280	2		T301	1
all_values[2]	auto[1]	auto[0]	auto[1]	65	1		T213	2		T211	1		T212	2
all_values[2]	auto[1]	auto[1]	auto[1]	41	1		T211	2		T212	2		T280	1
all_values[3]	auto[0]	auto[0]	auto[0]	44	1		T213	1		T211	1		T214	2
all_values[3]	auto[0]	auto[0]	auto[1]	26	1		T214	1		T282	2		T302	1
all_values[3]	auto[0]	auto[1]	auto[0]	49	1		T212	1		T214	2		T280	2
all_values[3]	auto[0]	auto[1]	auto[1]	32	1		T213	1		T211	2		T212	3
all_values[3]	auto[1]	auto[0]	auto[1]	70	1		T213	1		T212	2		T214	1
all_values[3]	auto[1]	auto[1]	auto[1]	48	1		T213	1		T211	1		T212	1
all_values[4]	auto[0]	auto[0]	auto[0]	69	1		T213	1		T211	4		T212	1
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T213	2		T212	2		T214	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1		T214	1		T280	2		T281	1
all_values[4]	auto[0]	auto[1]	auto[1]	27	1		T280	1		T281	1		T303	1
all_values[4]	auto[1]	auto[0]	auto[1]	56	1		T213	1		T212	4		T214	2
all_values[4]	auto[1]	auto[1]	auto[1]	46	1		T214	2		T280	1		T281	2
all_values[5]	auto[0]	auto[0]	auto[0]	57	1		T213	1		T211	1		T212	1
all_values[5]	auto[0]	auto[0]	auto[1]	28	1		T281	1		T282	1		T303	1
all_values[5]	auto[0]	auto[1]	auto[0]	47	1		T212	1		T214	5		T302	2
all_values[5]	auto[0]	auto[1]	auto[1]	24	1		T213	1		T211	1		T212	2
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T213	1		T211	1		T280	1
all_values[5]	auto[1]	auto[1]	auto[1]	52	1		T213	1		T211	1		T212	3
all_values[6]	auto[0]	auto[0]	auto[0]	58	1		T212	1		T214	3		T281	2
all_values[6]	auto[0]	auto[0]	auto[1]	20	1		T302	2		T301	2		T304	2
all_values[6]	auto[0]	auto[1]	auto[0]	52	1		T211	1		T212	4		T280	2
all_values[6]	auto[0]	auto[1]	auto[1]	31	1		T213	1		T211	2		T214	1
all_values[6]	auto[1]	auto[0]	auto[1]	55	1		T213	2		T211	1		T212	1
all_values[6]	auto[1]	auto[1]	auto[1]	53	1		T213	1		T212	1		T214	1
all_values[7]	auto[0]	auto[0]	auto[0]	79	1		T211	1		T212	3		T214	2
all_values[7]	auto[0]	auto[1]	auto[0]	86	1		T213	3		T211	1		T212	2
all_values[7]	auto[1]	auto[0]	auto[1]	47	1		T212	2		T280	2		T282	1
all_values[7]	auto[1]	auto[1]	auto[1]	57	1		T213	1		T211	2		T214	3
all_values[8]	auto[0]	auto[0]	auto[0]	74	1		T213	3		T211	1		T212	1
all_values[8]	auto[0]	auto[1]	auto[0]	75	1		T212	2		T214	2		T280	4
all_values[8]	auto[1]	auto[0]	auto[1]	65	1		T213	1		T211	3		T212	2
all_values[8]	auto[1]	auto[1]	auto[1]	55	1		T212	2		T214	1		T280	1
all_values[9]	auto[0]	auto[0]	auto[0]	61	1		T213	2		T212	1		T280	2
all_values[9]	auto[0]	auto[0]	auto[1]	16	1		T214	1		T281	2		T282	1
all_values[9]	auto[0]	auto[1]	auto[0]	43	1		T213	1		T282	2		T303	2
all_values[9]	auto[0]	auto[1]	auto[1]	34	1		T211	3		T212	2		T280	1
all_values[9]	auto[1]	auto[0]	auto[1]	56	1		T212	3		T214	1		T280	3
all_values[9]	auto[1]	auto[1]	auto[1]	59	1		T213	1		T211	1		T212	1
all_values[10]	auto[0]	auto[0]	auto[0]	57	1		T212	1		T214	2		T280	1
all_values[10]	auto[0]	auto[0]	auto[1]	33	1		T213	1		T211	3		T280	1
all_values[10]	auto[0]	auto[1]	auto[0]	49	1		T213	1		T212	4		T214	1
all_values[10]	auto[0]	auto[1]	auto[1]	30	1		T214	1		T281	1		T303	1
all_values[10]	auto[1]	auto[0]	auto[1]	52	1		T213	1		T212	1		T214	1
all_values[10]	auto[1]	auto[1]	auto[1]	48	1		T213	1		T211	1		T212	1
all_values[11]	auto[0]	auto[0]	auto[0]	49	1		T213	1		T212	2		T214	1
all_values[11]	auto[0]	auto[0]	auto[1]	34	1		T213	1		T211	1		T282	1
all_values[11]	auto[0]	auto[1]	auto[0]	56	1		T211	1		T212	2		T214	2
all_values[11]	auto[0]	auto[1]	auto[1]	27	1		T211	1		T214	1		T280	1
all_values[11]	auto[1]	auto[0]	auto[1]	59	1		T213	2		T212	2		T280	2
all_values[11]	auto[1]	auto[1]	auto[1]	44	1		T211	1		T212	1		T214	3
all_values[12]	auto[0]	auto[0]	auto[0]	67	1		T280	1		T281	4		T282	1
all_values[12]	auto[0]	auto[0]	auto[1]	20	1		T211	1		T303	1		T305	1
all_values[12]	auto[0]	auto[1]	auto[0]	55	1		T213	1		T212	5		T280	5
all_values[12]	auto[0]	auto[1]	auto[1]	24	1		T213	2		T211	1		T214	3
all_values[12]	auto[1]	auto[0]	auto[1]	54	1		T211	1		T214	2		T281	1
all_values[12]	auto[1]	auto[1]	auto[1]	49	1		T213	1		T211	1		T212	2
all_values[13]	auto[0]	auto[0]	auto[0]	63	1		T211	1		T212	2		T214	1
all_values[13]	auto[0]	auto[0]	auto[1]	30	1		T213	1		T214	2		T280	2
all_values[13]	auto[0]	auto[1]	auto[0]	53	1		T213	2		T211	2		T212	3
all_values[13]	auto[0]	auto[1]	auto[1]	22	1		T214	1		T280	1		T305	1
all_values[13]	auto[1]	auto[0]	auto[1]	54	1		T213	1		T212	1		T214	1
all_values[13]	auto[1]	auto[1]	auto[1]	47	1		T211	1		T212	1		T214	2
all_values[14]	auto[0]	auto[0]	auto[0]	53	1		T212	1		T280	2		T281	3
all_values[14]	auto[0]	auto[0]	auto[1]	25	1		T213	1		T211	1		T303	2
all_values[14]	auto[0]	auto[1]	auto[0]	50	1		T213	2		T211	1		T212	2
all_values[14]	auto[0]	auto[1]	auto[1]	23	1		T214	1		T280	1		T282	2
all_values[14]	auto[1]	auto[0]	auto[1]	71	1		T213	1		T211	1		T212	3
all_values[14]	auto[1]	auto[1]	auto[1]	47	1		T211	1		T212	1		T214	5
all_values[15]	auto[0]	auto[0]	auto[0]	58	1		T213	2		T212	1		T214	3
all_values[15]	auto[0]	auto[0]	auto[1]	25	1		T212	2		T305	2		T306	1
all_values[15]	auto[0]	auto[1]	auto[0]	60	1		T213	2		T211	1		T214	2
all_values[15]	auto[0]	auto[1]	auto[1]	28	1		T211	2		T214	1		T280	2
all_values[15]	auto[1]	auto[0]	auto[1]	55	1		T211	1		T212	3		T303	1
all_values[15]	auto[1]	auto[1]	auto[1]	43	1		T212	1		T214	1		T280	2
all_values[16]	auto[0]	auto[0]	auto[0]	52	1		T213	2		T211	4		T212	4
all_values[16]	auto[0]	auto[0]	auto[1]	34	1		T212	1		T214	1		T281	3
all_values[16]	auto[0]	auto[1]	auto[0]	40	1		T213	2		T280	4		T305	1
all_values[16]	auto[0]	auto[1]	auto[1]	18	1		T281	1		T303	1		T307	1
all_values[16]	auto[1]	auto[0]	auto[1]	72	1		T212	1		T214	4		T281	3
all_values[16]	auto[1]	auto[1]	auto[1]	53	1		T212	1		T214	1		T280	3
all_values[17]	auto[0]	auto[0]	auto[0]	78	1		T213	1		T211	3		T214	3
all_values[17]	auto[0]	auto[1]	auto[0]	82	1		T212	3		T214	2		T280	2
all_values[17]	auto[1]	auto[0]	auto[1]	68	1		T213	1		T212	1		T214	2
all_values[17]	auto[1]	auto[1]	auto[1]	41	1		T213	2		T211	1		T212	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal